src/sys/dev/alc, branch stable/10

MFC 312250

2017-02-21T03:27:59+00:00

    alc: Add Killer E2500 support

    Reviewed by:    jhb, yongari
    Sponsored by:   Microsoft
    Differential Revision:  https://reviews.freebsd.org/D9058

MFC r295735:

2017-01-18T02:16:17+00:00

  Fix variable assignment.

MFC r304574-304575,304584:

2017-01-18T01:53:07+00:00

r304574:
  Correct DMA channel number selection on AR816x family of
  controllers. For Gigabit Ethernet version of AR816x, AR813x/AR815x
  except L1D controller, use vendor recommended ASPM parameters.
  While here, increase alc_dma_burst array size.  Broken H/W can
  return bogus value in theory.

r304575:
  Add Killer E2400 Gigabit Ethernet support.
  It seems Killer E2200/E2400 has a BIOS misconfiguration or silicon
  bug which triggers DMA write errors when driver uses advertised
  maximum payload size.  Force the maximum payload size to 128 bytes
  in DMA configuration.
  This change should fix occasional DMA write errors reported on
  Killer E2200.

r304584:
  Add a missing change in r304575.

MFC r277907:

2015-03-26T05:12:30+00:00

  Correct device description message.

MFC r272730,273018:

2014-10-21T04:48:49+00:00

  Add support for QAC AR816x/AR817x Gigabit/Fast Ethernet controllers.
  These controllers seem to have the same feature of AR813x/AR815x and
  improved RSS support(4 TX queues and 8 RX queues).  alc(4) supports
  all hardware features except RSS.  I didn't implement RX checksum
  offloading for AR816x/AR817x just because I couldn't get
  confirmation from the Vendor whether AR816x/AR817x corrected its
  predecessor's RX checksum offloading bug on fragmented packets.
  This change adds supports for the following controllers.
   o AR8161 PCIe Gigabit Ethernet controller
   o AR8162 PCIe Fast Ethernet controller
   o AR8171 PCIe Gigabit Ethernet controller
   o AR8172 PCIe Fast Ethernet controller
   o Killer E2200 Gigabit Ethernet controller

  Relnotes:	yes

MFC r272721:

2014-10-21T01:14:56+00:00

  Fix a long standing bug in MAC statistics register access.  One
  additional register was erroneously added in the MAC register set
  such that 7 TX statistics counters were wrong.

MFC r263957:

2014-04-14T04:51:59+00:00

  Increase the number of TX DMA segments from 32 to 35.  It turned
  out 32 is not enough to support a full sized TSO packet.
  While I'm here fix a long standing bug introduced in r169632 in
  bce(4) where it didn't include L2 header length of TSO packet in
  the maximum DMA segment size calculation.

Mechanically substitute flags from historic mbuf allocator with

2012-12-04T09:32:43+00:00

malloc(9) flags in sys/dev.

Switch some PCI register reads from using magic numbers to using the names

2012-09-19T12:27:23+00:00

defined in pcireg.h

MFC after:	1 week

Align the PCI Express #defines with the style used for the PCI-X

2012-09-18T22:04:59+00:00

#defines.  This also has the advantage that it makes the names more
compact, iand also allows us to correct the non-uniform naming of
the PCIM_LINK_* defines, making them all consistent amongst themselves.

This is a mostly mechanical rename:
  s/PCIR_EXPRESS_/PCIER_/g
  s/PCIM_EXP_/PCIEM_/g
  s/PCIM_LINK_/PCIEM_LINK_/g

When this is MFC'd, #defines will be added for the old names to assist
out-of-tree drivers.

Discussed with:	jhb
MFC after:	1 week