The layout for the main INT_CAUSE is a bit different for T7. MFC after: 1 week Sponsored by: Chelsio Communications
- Display an appropriate alert character instead of a question mark for unknown bits. - Display all fatal bits for a register and not just the ones that are currently set. MFC after: 1 week Sponsored by: Chelsio Communications
Obtained from: Chelsio Communications MFC after: 1 week Sponsored by: Chelsio Communications
When "options RSS" is configured, opt_rss.h defines the "RSS" token.
PR: 291068
Fixes: 17b4a0acfaf5 ("cxgbe(4): T7 related updates to shared code")
Fixes: 7b80c8b7d8d9 cxgbe(4): Expanded interrupt handling for T7 MFC after: 1 week Sponsored by: Chelsio Communications
- Catch up with the new cause/perr registers. The high level approach is the same but the T7 has an extra top level INT_CAUSE concentrator and a PERR_CAUSE concentrator with a changed layout. - Add various flags to control the interrupt handlers' behavior. - Implement a t4_intr_clear that internally use the slow handler as an iterator over known cause/perr registers. This lets the driver clear all of the interrupt sources that it knows about. The firmware sets up the interrupt enables and clears the causes normally so this call should be redundant. MFC after: 1 week Sponsored by: Chelsio Communications
- Avoid some more registers with read side-effects during regdump. - mps_tcam_size is 3x the size of T6/T5. - Update rss_rd_row to work with T7. Obtained from: Chelsio Communications MFC after: 1 week Sponsored by: Chelsio Communications
This is the first of a series of commits that will add T7 support to cxgbe. The ASIC is gen5x16 on the PCIe side and has a 400Gbps MAC on the Ethernet side. NICs using the T7 will come in the following variants: * 1 x 400Gbps with QSFP-DD connector * 2 x 200/100/40Gbps with QSFP56/QSFP28/QSFP+ connectors * 4 x 50/25/10/1Gbps with SFP28/SFP+/SFP connectors There are 8 general purpose ARM A72 cores available on select SmartNIC/DPU boards. Obtained from: Chelsio Communications MFC after: 3 days Sponsored by: Chelsio Communications
The port's tx channel and its hardware index are different things that happen to have the same value on NICs using T4 through T6. This is going to change so use the correct spelling all over the driver. Specifically, the firmware expects the hw port index in all of these: * PCIe channel for queues * TX interface for TX CPLs * PORTID in FW_PORT commands * PORTID in t4_alloc_vi * flowid in all the firmware flowc WRs * mbox commands that deal with the tx scheduler Also, create a port_id lookup table for hw_port, just like the one for tx_chan. Use it to lookup the port softc in the port_info handler. MFC after: 3 days Sponsored by: Chelsio Communications
No functional change intended. MFC after: 3 days Sponsored by: Chelsio Communications