src/sys/dev/hwpmc/hwpmc_x86.c, branch release/7.0.0_cvs

This commit was manufactured by cvs2svn to create tag

2008-02-24T05:45:17+00:00

'RELENG_7_0_0_RELEASE'.

This commit was manufactured to restore the state of the 7.0-RELEASE image.

MFC r1.6:

2007-12-03T10:50:58+00:00

"Revert revision 1.4.

 Intel CPUs with family 0x6, model 0xE and later (i.e., Intel Core(TM))
 have a PMC architecture that differs somewhat from previous CPUs in
 family 0x6.  Even though the basic programming model is similar, the
 documented set of legal values that may be loaded into their PMC MSRs
 differs from that of the previous PMCs in family 0x6 and reusing bit
 values legal for the older PMCs could result in undefined behaviour in
 the general case."

Approved by:	re (gnn)

Add support for Intel cpu model's 5 & 6.

2006-04-04T02:36:04+00:00

Approved by:	jkoshy

Add support for a new/unreleased Pentium-M.

2005-11-18T16:47:24+00:00

Reviewed by:	jkoshy

On x86 processors, turn off any 'INTERRUPT' capabilities on PMCs

2005-08-22T18:20:41+00:00

if the CPU does not have its local APIC enabled.

MFC after:	3 days

- Update the CPU version check to recognize P4/EMT64 CPUs. [1]

2005-07-03T16:33:22+00:00

- Allow libpmc(3) to support P4/EMT64 PMCs on the amd64 architecture
  and AMD K8 PMCs on the i386. [2]

Submitted by:	ps [1]
Pointy hat:	myself [2]
Approved by:	re (scottl)

MFP4:

2005-06-09T19:45:09+00:00

- Implement sampling modes and logging support in hwpmc(4).

- Separate MI and MD parts of hwpmc(4) and allow sharing of
  PMC implementations across different architectures.
  Add support for P4 (EMT64) style PMCs to the amd64 code.

- New pmcstat(8) options: -E (exit time counts) -W (counts
  every context switch), -R (print log file).

- pmc(3) API changes, improve our ability to keep ABI compatibility
  in the future.  Add more 'alias' names for commonly used events.

- bug fixes & documentation.