Add support for UART found in the Ingenic XBurst system on chips.

These CPUs has non-standard UART enable bit hidden in the UART FIFO
Control Register.

- Add support for Advantech PCI-1602 Rev. B1 and PCI-1603 cards. [1]
- Add a description of Advantech PCI-1602 Rev. A boards. [1]
- Properly set up REG_ACR also for PCI-1602 Rev. A based on what the
  Advantech-supplied Linux driver does.
- Additionally use the macros of <dev/ic/ns16550.h> to replace existing
  magic values and get rid of trivial comments.
- Fix the style of some comments.

PR:		205359 [1]
Submitted by:	Jan Mikkelsen (original patch) [1]

    r257282, r257332

  Wait for DesignWare UART transfers completion before accessing line control

  Enable UART busy detection handling for Armada XP - based board

  Enable SATA interface on Armada XP
  Run mvs SATA driver on Armada XP instead of old mv_sata

  Retire arm_remap_nocache() and the data and constants associated with it.

  Remove hard-coded mappings related to Armada XP support

  Fix-up DTB for Armada XP registers' base according to the actual settings

  Change Armada XP kernel load address to the u-boot's end address

  Remove not working and deprecated PJ4Bv6 support

  Switch off explicit broadcasting of the TLB flush operations for PJ4B CPU

  Add missing ARMv6 CPU functions to ARM Makefile

A10 uart is derived from Synopsys DesignWare uart and requires
to read Uart Status Register when IIR_BUSY has detected.
Also this change includes FDT check, where it checks device
specific properties defined in dts and sets the busy_detect variable.
broken_txfifo is also needed to be set in order to make it work for
A10 uart case.

Reviewed by: marcel@
Approved by: gonzo@

Defintions for cavium uart (do they belong here?)

- Move i8255 related defines into a separate file.

The QUICC engine is found on various Freescale parts including MPC85xx, and
provides multiple generic time-division serial channel resources, which are in
turn muxed/demuxed by the Serial Communications Controller (SCC).

Along with core QUICC/SCC functionality a uart(4)-compliant device driver is
provided which allows for serial ports over QUICC/SCC.

Approved by:	cognet (mentor)
Obtained from:	Juniper
MFp4:		e500