src/sys/dev/ic, branch upstream/11.1.0 FreeBSD source tree sys/dev: minor spelling fixes. 2016-05-03T03:41:25+00:00 Pedro F. Giffuni pfg@FreeBSD.org 2016-05-03T03:41:25+00:00 453130d9bfc1c6d68b366dfcb041689d69f81295 Most affect comments, very few have user-visible effects. 
Most affect comments, very few have user-visible effects.
- Add support for Advantech PCI-1602 Rev. B1 and PCI-1603 cards. [1] 2016-01-10T18:11:23+00:00 Marius Strobl marius@FreeBSD.org 2016-01-10T18:11:23+00:00 3deebd539b0a4a8cc136dc9adedf22ab84a9bc19 - Add a description of Advantech PCI-1602 Rev. A boards. [1] - Properly set up REG_ACR also for PCI-1602 Rev. A based on what the Advantech-supplied Linux driver does. - Additionally use the macros of <dev/ic/ns16550.h> to replace existing magic values and get rid of trivial comments. - Fix the style of some comments. PR: 205359 [1] Submitted by: Jan Mikkelsen (original patch) [1] 
- Add a description of Advantech PCI-1602 Rev. A boards. [1]
- Properly set up REG_ACR also for PCI-1602 Rev. A based on what the
  Advantech-supplied Linux driver does.
- Additionally use the macros of <dev/ic/ns16550.h> to replace existing
  magic values and get rid of trivial comments.
- Fix the style of some comments.

PR:		205359 [1]
Submitted by:	Jan Mikkelsen (original patch) [1]
This should have been GC'd 6 years ago when ar(4) was removed. 2015-02-17T05:07:38+00:00 Warner Losh imp@FreeBSD.org 2015-02-17T05:07:38+00:00 80bd9c96829b6414191cd040d89158bcf4522f6b 






Wait for DesignWare UART transfers completion before accessing line control
2013-10-26T17:24:59+00:00

Zbigniew Bodek
zbb@FreeBSD.org

2013-10-26T17:24:59+00:00

49e368ac48885954a96af27b73834f034c8dd01b

When using DW UART with BUSY detection it is necessary to wait
until all serial transfers are finished before manipulating the
line control. LCR will not be affected when UART is busy.
In addition, if Divisor Latch Access Bit is being set in order to
modify UART divisors:
1. We will get BUSY interrupt if interrupts are enabled.
2. Because LCR will not be affected the THR and (even worse) IER
   contents will be corrupted. This will lead to console hang.

Approved by:	cognet (mentor)





When using DW UART with BUSY detection it is necessary to wait
until all serial transfers are finished before manipulating the
line control. LCR will not be affected when UART is busy.
In addition, if Divisor Latch Access Bit is being set in order to
modify UART divisors:
1. We will get BUSY interrupt if interrupts are enabled.
2. Because LCR will not be affected the THR and (even worse) IER
   contents will be corrupted. This will lead to console hang.

Approved by:	cognet (mentor)







Add support for A10 uart.
2013-03-01T01:42:31+00:00

Ganbold Tsagaankhuu
ganbold@FreeBSD.org

2013-03-01T01:42:31+00:00

ac4adddf040f1010f08e284f71e1bb2f92b4d43a

A10 uart is derived from Synopsys DesignWare uart and requires
to read Uart Status Register when IIR_BUSY has detected.
Also this change includes FDT check, where it checks device
specific properties defined in dts and sets the busy_detect variable.
broken_txfifo is also needed to be set in order to make it work for
A10 uart case.

Reviewed by: marcel@
Approved by: gonzo@





A10 uart is derived from Synopsys DesignWare uart and requires
to read Uart Status Register when IIR_BUSY has detected.
Also this change includes FDT check, where it checks device
specific properties defined in dts and sets the busy_detect variable.
broken_txfifo is also needed to be set in order to make it work for
A10 uart case.

Reviewed by: marcel@
Approved by: gonzo@







Merge from projects/mips to head by hand:
2010-01-11T04:13:06+00:00

Warner Losh
imp@FreeBSD.org

2010-01-11T04:13:06+00:00

18f323353c3aa8b0add9ea0e1b434f9229621394

Defintions for cavium uart (do they belong here?)





Defintions for cavium uart (do they belong here?)







add %b formats for various registers
2009-06-21T19:17:22+00:00

Sam Leffler
sam@FreeBSD.org

2009-06-21T19:17:22+00:00

04ddfac3390b5b7fc9d57edf2ad2b7fb5c3e692c












- Cleanup i8251 related defines.
2008-09-07T04:35:04+00:00

Yoshihiro Takahashi
nyan@FreeBSD.org

2008-09-07T04:35:04+00:00

ebd2b744768169ad575024ce4c1033833a220c6d

- Move i8255 related defines into a separate file.





- Move i8255 related defines into a separate file.







unifdef PC98
2008-08-29T12:25:58+00:00

Yoshihiro Takahashi
nyan@FreeBSD.org

2008-08-29T12:25:58+00:00

5798cf97e910447c5dbee9d70706a276b163b5a4












Support for Freescale QUad Integrated Communications Controller.
2008-03-03T18:20:17+00:00

Rafal Jaworowski
raj@FreeBSD.org

2008-03-03T18:20:17+00:00

e1ef781113fba635a7fa4a979607261385971992

The QUICC engine is found on various Freescale parts including MPC85xx, and
provides multiple generic time-division serial channel resources, which are in
turn muxed/demuxed by the Serial Communications Controller (SCC).

Along with core QUICC/SCC functionality a uart(4)-compliant device driver is
provided which allows for serial ports over QUICC/SCC.

Approved by:	cognet (mentor)
Obtained from:	Juniper
MFp4:		e500





The QUICC engine is found on various Freescale parts including MPC85xx, and
provides multiple generic time-division serial channel resources, which are in
turn muxed/demuxed by the Serial Communications Controller (SCC).

Along with core QUICC/SCC functionality a uart(4)-compliant device driver is
provided which allows for serial ports over QUICC/SCC.

Approved by:	cognet (mentor)
Obtained from:	Juniper
MFp4:		e500