src/sys/dev/nctgpio, branch releng/14.3

sys: Remove $FreeBSD$: two-line .h pattern

2023-08-16T17:54:11+00:00

Remove /^\s*\*\n \*\s+\$FreeBSD\$$\n/

nctgpio: Enable all the 9 groups for NCT6116D and remove FIXMEs

2023-08-04T15:27:54+00:00

Reviewed by:	emaste
Pull Request:	https://github.com/freebsd/freebsd-src/pull/810

nctgpio: Populate the cache earlier

2023-07-01T17:19:54+00:00

Reviewed by: imp
Pull Request: https://github.com/freebsd/freebsd-src/pull/719

superio+nctgpio: Add support for new (weird) chips

2023-07-01T17:19:52+00:00

Add support for the following chips:
- Nuvoton NCT5585D
- Nuvoton NCT6796D-E
- Nuvoton NCT6779
- Nuvoton NCT6116D
- and Winbond 83627DHG

Reviewed by: imp
Pull Request: https://github.com/freebsd/freebsd-src/pull/719

superio+nctgpio: Prepare to support some new (weird) chips

2023-07-01T17:19:51+00:00

- Increase verbosity to direct i/o code path (iores != 0)
- Fix pin inversion configuration
- Allow forcing the use of indirect access channel via hint.gpio.0.flags=2
- Document the PREFER_INDIRECT_CHANNEL tunable in nctgpio(4)

Reviewed by: imp
Pull Request: https://github.com/freebsd/freebsd-src/pull/719

gpio: Remove unused devclass arguments to DRIVER_MODULE.

2022-05-09T19:22:01+00:00

nctgpio: improve performance (latency) of operation

2019-10-22T14:20:35+00:00

This change consists of two parts.

First, nctgpio now supports hardware access via an I/O port window if
it's configured by firmware.  For instance, PC Engines firmware
v4.10.0.2 does that.  This is faster than going through the Super I/O
configuration registers.

Second, nctgpio now caches values of bits that it controls.  For
example, the driver does not need to access the hardware to determine if
a pin is an output or an input, or a state of an output.  Also, the
driver makes use of the fact that the hardware preserves an output state
of a pin accross a switch to the input mode and back.

With this change I am able to use the 1-Wire bus over nctgpio whereas
previously the driver introduced too much latency to be compliant with
the relatively strict protocol timings.

superio0:  at port 0x2e-0x2f on isa0
gpio1:  at GPIO ldn 0x07 on superio0
pcib0: allocated type 4 (0x220-0x226) for rid 0 of gpio1
gpiobus1:  on gpio1
owc0:  at pin 4 on gpiobus1
ow0: <1 Wire Bus> on owc0
ow0: romid 28:b2:9e:45:92:10:02:34: no driver
ow_temp0:  romid 28:b2:9e:45:92:10:02:34 on ow0

MFC after:	4 weeks

move nctgpio to superio(4) bus

2019-10-16T14:42:49+00:00

This is where it logically belongs.
The change allows to drop a bunch of low lewel code.

Reviewed by:	gonzo
MFC after:	19 days
Differential Revision: https://reviews.freebsd.org/D21980

nctgpio: change default pin names to those used by the datasheet(s)

2019-07-01T15:43:48+00:00

That is, instead of the current GPIO00 - GPIO15 the names will be GPIO00
- GPIO07, GPIO10 - GPIO17.  The first digit is a GPIO "bank" / group
number and the second one is a pin number within the bank.  Alternative
view is that the pin names are changed from decimal numbering scheme to
octal one (as there are 8 pins per bank).

Discussed with:	cem, gonzo
MFC after:	2 weeks

nctgpio: add new device id for the GPIO chip in PCEngines APU3

2018-01-02T20:58:05+00:00

PR:		224512
Submitted by:	mike@sentex.net
MFC after:	2 weeks