A revised version, that fixes typos, clarifies some points that caused

EMAIL questions, corrects a serious error in the I/O port map, and adds
information on the recently released 32-bit superset Intel 82374 DMA
controller appearing in PCI (and EISA) systems.

I recommend this updated section be included in the 2.2.x tree ASAP.

As always, comments and corrections are welcome.

Frank Durda IV	uhclem%freebsd.org
or (checked more frequently) uhclem.freebsd%nemesis.lonestar.org
Change % to @, or your RFC-822-compliant mail transport will do it for you.

1 files changed, 207 insertions, 106 deletions

diff --git a/handbook/dma.sgml b/handbook/dma.sgml
index e7cbb29da5..13ac32e47d 100644
--- a/handbook/dma.sgml
+++ b/handbook/dma.sgml
@@ -1,4 +1,4 @@
-<!-- $Id: dma.sgml,v 1.8 1997-08-12 09:17:46 asami Exp $ -->
+<!-- $Id: dma.sgml,v 1.9 1997-10-09 22:51:31 uhclem Exp $ -->
 <!-- The FreeBSD Documentation Project -->
 
 <!--
@@ -11,8 +11,8 @@
 -->
   <sect><heading>DMA: What it Is and How it Works<label id="dma"></heading>
 
-    <p><em>Copyright &copy; 1995 &a.uhclem;, All Rights Reserved.<newline>
-	10 December 1996.</em>
+    <p><em>Copyright &copy; 1995,1997 &a.uhclem;, All Rights Reserved.<newline>
+	10 December 1996.  Last Update 8 October 1997.</em>
 
 <!-- Version 1(3) -->
 
@@ -63,26 +63,27 @@
 	CPU.</quote>
 
       In the PC architecture, each DMA channel is normally
-      activated only when the hardware that uses that DMA
+      activated only when the hardware that uses a given DMA channel
       requests a transfer by asserting the DRQ line for that
       channel.
 
 
     <sect1><heading>A Sample DMA transfer</heading>
 
-      <p>Here is an example of the steps that occur to cause a
-	DMA transfer.  In this example, the floppy disk
+      <p>Here is an example of the steps that occur to cause and perform
+	a DMA transfer.  In this example, the floppy disk
 	controller (FDC) has just read a byte from a diskette and
 	wants the DMA to place it in memory at location
 	0x00123456.  The process begins by the FDC asserting the
-	DRQ2 signal to alert the DMA controller.
+	DRQ2 signal (the DRQ line for DMA channel 2) to alert the DMA
+	controller.
 
 	The DMA controller will note that the DRQ2 signal is asserted.
 	The DMA controller will then make sure that DMA channel 2
-	has been programmed and is enabled.  The DMA controller
+	has been programmed and is unmasked (enabled).  The DMA controller
 	also makes sure that none of the other DMA channels are active
-	or have a higher priority.  Once these checks are
-	complete, the DMA asks the CPU to release the bus so that
+	or want to be active and have a higher priority.  Once these checks
+	are complete, the DMA asks the CPU to release the bus so that
 	the DMA may use the bus.  The DMA requests the bus by
 	asserting the HRQ signal which goes to the CPU.
 
@@ -124,8 +125,8 @@
 	has been transferred.
 
 	Since the DMA cycle only transfers a single byte at a
-	time, the FDC now drops the DRQ2 signal, so that the DMA
-	knows it is no longer needed.  The DMA will de-assert the
+	time, the FDC now drops the DRQ2 signal, so the DMA knows that
+	it is no longer needed.  The DMA will de-assert the
 	-DACK2 signal, so that the FDC knows it must stop placing
 	data on the bus.
 
@@ -144,28 +145,30 @@
 	For a typical floppy disk sector, the above process is
 	repeated 512 times, once for each byte.  Each time a byte
 	is transferred, the address register in the DMA is
-	incremented and the counter that shows how many bytes are
-	to be transferred is decremented.
+	incremented and the counter in the DMA that shows how many
+	bytes are to be transferred is decremented.
 
 	When the counter reaches zero, the DMA asserts the EOP
 	signal, which indicates that the counter has reached zero
 	and no more data will be transferred until the DMA
 	controller is reprogrammed by the CPU.  This event is
 	also called the Terminal Count (TC).  There is only one
-	EOP signal, because only one DMA channel can be active at
-	any instant.
+	EOP signal, and since only DMA channel can be active at
+	any instant, the DMA channel that is currently active must
+	be the DMA channel that just completed its task.
 
 	If a peripheral wants to generate an interrupt when the
 	transfer of a buffer is complete, it can test for its
-	-DACK signal and the EOP signal both being asserted at
+	-DACKn signal and the EOP signal both being asserted at
 	the same time.  When that happens, it means the DMA will not
 	transfer any more information for that peripheral without
 	intervention by the CPU.  The peripheral can then assert
 	one of the interrupt signals to get the processors'
-	attention.  The DMA chip itself is not capable of
-	generating an interrupt.  The peripheral and its
+	attention.  In the PC architecture, the DMA chip itself is not
+	capable of generating an interrupt.  The peripheral and its
 	associated hardware is responsible for generating any
-	interrupt that occurs.
+	interrupt that occurs.  Subsequently, it is possible to have
+	a peripheral that uses DMA but does not use interrupts.
 
 	It is important to understand that although the CPU
 	always releases the bus to the DMA when the DMA makes the
@@ -192,12 +195,12 @@
 	supported more than 64K of memory, something had to be
 	done to allow the DMA to read or write memory locations
 	above the 64K mark.  What IBM did to solve this problem
-	was to add a latch for each DMA channel that holds the
-	upper bits of the address to be read to or written from.
+	was to add an external data latch for each DMA channel that
+	holds the upper bits of the address to be read to or written from.
 	Whenever a DMA channel is active, the contents of that
 	latch are written to the address bus and kept there until
-	the DMA operation for the channel ends.  These latches
-	are called ``Page Registers''.
+	the DMA operation for the channel ends.  IBM called these latches
+	``Page Registers''.
 
 	So for our example above, the DMA would put the 0x3456
 	part of the address on the bus, and the Page Register for
@@ -207,26 +210,27 @@
 
 	Because the Page Register latch is independent of the DMA
 	chip, the area of memory to be read or written must not
-	span a 64K physical boundary.  If the DMA accesses memory
-	location 0xffff, after the transfer the DMA will then increment
-	the address register and the DMA will access the next byte at
-	location 0x0000, not 0x10000.  The results of letting this
-	happen are probably not intended.
+	span a 64K physical boundary.  For example, if the DMA accesses
+	memory location 0xffff, after that transfer the DMA will then
+	increment the address register and the DMA will access the next
+	byte at location 0x0000, not 0x10000.  The results of letting
+	this happen are probably not intended.
 
 	<quote><em>Note:</em> ``Physical'' 64K boundaries should
 	  not be confused with 8086-mode 64K ``Segments'', which
-	  are created by adding a segment register with an offset
-	  register.  Page Registers have no address overlap.</quote>
+	  are created by mathematically adding a segment register with an
+	  offset register.  Page Registers have no address overlap and
+	  are mathematically OR-ed together.</quote>
 
 	To further complicate matters, the external DMA address
 	latches on the PC/AT hold only eight bits, so that gives
 	us 8+16=24 bits, which means that the DMA can only point
 	at memory locations between 0 and 16Meg.  For newer
-	computers that allow more than 16Meg of memory, the
+	computers that allow more than 16Meg of memory, the standard
 	PC-compatible DMA cannot access memory locations above 16Meg.
 
 	To get around this restriction, operating systems will
-	reserve a buffer in an area below 16Meg that also does not
+	reserve a RAM buffer in an area below 16Meg that also does not
 	span a physical 64K boundary.  Then the DMA will be
 	programmed to transfer data from the peripheral and into that
 	buffer.  Once the DMA has moved the data into this buffer,
@@ -241,6 +245,11 @@
 	``Bounce Buffers''.  In the MS-DOS world, they are
 	sometimes called ``Smart Buffers''.
 
+	<quote><em>Note:</em> A new implementation of the 8237, called the
+	82374, allows 16 bits of page register to be specified, allows
+	access to the entire 32 bit address space, without the use of
+	bounce buffers.</quote>
+
 
     <sect1><heading>DMA Operational Modes and Settings</heading>
 
@@ -256,8 +265,8 @@
 	    immediately.  The peripheral will request the DMA
 	    each time it is ready for another transfer.
 
-	    The floppy disk controller only has a one-byte
-	    buffer, so it uses this mode.
+	    The standard PC-compatible floppy disk controller (NEC 765)
+	    only has a one-byte buffer, so it uses this mode.
 
 
 	  <tag>Block/Demand</tag> Once the DMA acquires the
@@ -272,8 +281,8 @@
 	    Block transfer is started, it runs until the transfer
 	    count reaches zero.  DRQ only needs to be asserted
 	    until -DACK is asserted.  Demand Mode will transfer
-	    one more bytes until DRQ is de-asserted and the DMA
-	    pauses the transfer and releases the bus back to the CPU.
+	    one more bytes until DRQ is de-asserted, at which point the DMA
+	    suspends the transfer and releases the bus back to the CPU.
 	    When DRQ is asserted later, the transfer resumes where
 	    it was suspended.
 
@@ -288,41 +297,42 @@
 	    to request the bus, but then the attached peripheral
 	    device is responsible for placing the addressing
 	    information on the bus instead of the DMA.  This is also
-	    known as ``Bus Mastering''.
+	    used to implement a technique known as ``Bus Mastering''.
 
 	    When a DMA channel in Cascade Mode receives control
 	    of the bus, the DMA does not place addresses and I/O
 	    control signals on the bus like the DMA normally does
 	    when it is active.  Instead, the DMA only asserts the
-	    -DACK signal for this channel.
+	    -DACK signal for the active DMA channel.
 
-	    At this point it is up to the device connected to that DMA
-	    channel to provide address and bus control signals.
+	    At this point it is up to the peripheral connected to that
+	    DMA channel to provide address and bus control signals.
 	    The peripheral has complete control over the system
 	    bus, and can do reads and/or writes to any address
 	    below 16Meg.  When the peripheral is finished with
 	    the bus, it de-asserts the DRQ line, and the DMA
-	    controller can return control to the CPU or to some
+	    controller can then return control to the CPU or to some
 	    other DMA channel.
 
-	    Cascade Mode can be used to chain multiple DMA
-	    controllers together, and this is exactly what DMA
-	    Channel 4 is used for in the PC.  When a peripheral
-	    requests the bus on DMA channels 0, 1, 2 or 3, the
-	    slave DMA controller asserts HLDREQ, but this wire is
-	    actually connected to DRQ4 on the primary DMA
-	    controller.  The primary DMA controller then requests
-	    the bus from the CPU using HLDREQ.  Once the bus is
-	    granted, -DACK4 is asserted, and that wire is
-	    actually connected to the HLDA signal on the slave
-	    DMA controller.  The slave DMA controller then
-	    transfers data for the DMA channel that requested it,
-	    or the slave DMA may grant the bus to a peripheral
-	    that wants to perform its own bus-mastering, such as
-	    a SCSI controller.
+	    Cascade Mode can be used to chain multiple DMA controllers
+	    together, and this is exactly what DMA Channel 4 is used
+	    for in the PC architecture.  When a peripheral requests
+	    the bus on DMA channels 0, 1, 2 or 3, the slave DMA
+	    controller asserts HLDREQ, but this wire is actually connected
+	    to DRQ4 on the primary DMA controller instead of to the CPU.
+	    The primary DMA controller, thinking it has work to do on
+	    Channel 4, requests the bus from the CPU using HLDREQ signal.
+	    Once the CPU grants the bus to the primary DMA controller, 
+	    -DACK4 is asserted, and that wire is actually connected to
+	    the HLDA signal on the slave DMA controller.  The slave DMA
+	    controller then transfers data for the DMA channel that
+	    requested it (0, 1, 2 or 3), or the slave DMA may grant the bus
+	    to a peripheral that wants to perform its own bus-mastering,
+	    such as a SCSI controller.
 
 	    Because of this wiring arrangement, only DMA channels
-	    0, 1, 2, 3, 5, 6 and 7 are usable on PC/AT systems.
+	    0, 1, 2, 3, 5, 6 and 7 are usable with peripherals on PC/AT
+	    systems.
 
 	    <quote><em>Note:</em> DMA channel 0 was reserved for
 	      refresh operations in early IBM PC computers, but
@@ -386,9 +396,9 @@
 
       <p>The DMA channel that is to be programmed should always
 	be ``masked'' before loading any settings.  This is because
-	the hardware might unexpectedly assert DRQ, and the DMA might
-	respond, even though not all of the parameters have been
-	loaded or updated.
+	the hardware might unexpectedly assert the DRQ for that channel,
+	and the DMA might respond, even though not all of the parameters
+	have been loaded or updated.
 
 	Once masked, the host must specify the direction of the
 	transfer (memory-to-I/O or I/O-to-memory), what mode of
@@ -408,13 +418,14 @@
 
 	Once all the settings are ready, the DMA channel can be
 	un-masked.  That DMA channel is now considered to be
-	``armed'', and will respond when DRQ is asserted.
+	``armed'', and will respond when the DRQ line for that channel
+	is asserted.
 
 	Refer to a hardware data book for precise programming
 	details for the 8237.  You will also need to refer to the
 	I/O port map for the PC system, which describes where
 	the DMA and Page Register ports are located.  A complete
-	table is located below.
+	port map table is located below.
 
 
     <sect1><heading>DMA Port Map</heading>
@@ -431,44 +442,44 @@
 <verb>
 0x00	write	Channel 0 starting address
 0x00	read	Channel 0 current address
-0x02	write	Channel 0 starting word count
-0x02	read	Channel 0 remaining word count
-
-0x04	write	Channel 1 starting address
-0x04	read	Channel 1 current address
-0x06	write	Channel 1 starting word count
-0x06	read	Channel 1 remaining word count
-
-0x08	write	Channel 2 starting address
-0x08	read	Channel 2 current address
-0x0a	write	Channel 2 starting word count
-0x0a	read	Channel 2 remaining word count
-
-0x0c	write	Channel 3 starting address
-0x0c	read	Channel 3 current address
-0x0e	write	Channel 3 starting word count
-0x0e	read	Channel 3 remaining word count
+0x01	write	Channel 0 starting word count
+0x01	read	Channel 0 remaining word count
+
+0x02	write	Channel 1 starting address
+0x02	read	Channel 1 current address
+0x03	write	Channel 1 starting word count
+0x03	read	Channel 1 remaining word count
+
+0x04	write	Channel 2 starting address
+0x04	read	Channel 2 current address
+0x05	write	Channel 2 starting word count
+0x05	read	Channel 2 remaining word count
+
+0x06	write	Channel 3 starting address
+0x06	read	Channel 3 current address
+0x07	write	Channel 3 starting word count
+0x07	read	Channel 3 remaining word count
 </verb>
 
 DMA Command Registers
 
 <verb>
-0x10	write	Command Register
-0x10	read	Status Register
-0x12	write	Request Register
-0x12	read	-
-0x14	write	Single Mask Register Bit
-0x14	read	-
-0x16	write	Mode Register
-0x16	read	-
-0x18	write	Clear LSB/MSB Flip-Flop
-0x18	read	-
-0x1a	write	Master Clear/Reset
-0x1a	read	Temporary Register
-0x1c	write	Clear Mask Register
-0x1c	read	-
-0x1e	write	Write All Mask Register Bits
-0x1e	read	-
+0x08	write	Command Register
+0x08	read	Status Register
+0x09	write	Request Register
+0x09	read	-
+0x0a	write	Single Mask Register Bit
+0x0a	read	-
+0x0b	write	Mode Register
+0x0b	read	-
+0x0c	write	Clear LSB/MSB Flip-Flop
+0x0c	read	-
+0x0d	write	Master Clear/Reset
+0x0d	read	Temporary Register (not available on newer versions)
+0x0e	write	Clear Mask Register
+0x0e	read	-
+0x0f	write	Write All Mask Register Bits
+0x0f	read	Read All Mask Register Bits (only in Intel 82374)
 </verb>
 
 <sect2><heading>0xc0 - 0xdf DMA Controller &num;2 (Channels 4, 5, 6 and 7)</heading>
@@ -511,25 +522,115 @@ DMA Command Registers
 0xd8	write	Clear LSB/MSB Flip-Flop
 0xd8	read	-
 0xda	write	Master Clear/Reset
-0xda	read	Temporary Register
+0xda	read	Temporary Register (not present in Intel 82374)
 0xdc	write	Clear Mask Register
 0xdc	read	-
 0xde	write	Write All Mask Register Bits
-0xde	read	-
+0xdf	read	Read All Mask Register Bits (only in Intel 82374)
 </verb>
 
 <sect2><heading>0x80 - 0x9f DMA Page Registers</heading>
 
 <p><verb>
-0x87	r/w	DMA Channel 0
-0x83	r/w	DMA Channel 1
-0x81	r/w	DMA Channel 2
-0x82	r/w	DMA Channel 3
+0x87	r/w	Channel 0 Low byte (23-16) page Register
+0x83	r/w	Channel 1 Low byte (23-16) page Register
+0x81	r/w	Channel 2 Low byte (23-16) page Register
+0x82	r/w	Channel 3 Low byte (23-16) page Register
+
+0x8b	r/w	Channel 5 Low byte (23-16) page Register
+0x89	r/w	Channel 6 Low byte (23-16) page Register
+0x8a	r/w	Channel 7 Low byte (23-16) page Register
+0x8f	r/w	Low byte page Refresh
+</verb>
 
-0x8b	r/w	DMA Channel 5
-0x89	r/w	DMA Channel 6
-0x8a	r/w	DMA Channel 7
+<sect2><heading>0x400 - 0x4ff 82374 Enhanced DMA Registers</heading>
+
+<p>
+The Intel 82374 EISA System Component (ESC) was introduced in early 1996
+and includes a DMA controller that provides a superset of 8237 functionality
+as well as other PC-compatible core peripheral components in a single
+package.  This chip is targeted at both EISA and PCI platforms, and provides
+modern DMA features like scatter-gather, ring buffers as well as direct
+access by the system DMA to all 32 bits of address space.  
+
+<p>
+If these features are used, code should also be included to provide similar
+functionality in the previous 16 years worth of PC-compatible computers.
+For compatibility reasons, some of the 82374 registers must be programmed
+<em>after</em> programming the traditional 8237 registers for each 
+transfer.   Writing to a traditional 8237 register forces the contents
+of some of the 82374 enhanced registers to zero to provide backward
+software compatibility.
+	
 
-0x8f		Refresh
+<p><verb>
+0x401	r/w	Channel 0 High byte (bits 23-16) word count
+0x403	r/w	Channel 1 High byte (bits 23-16) word count
+0x405	r/w	Channel 2 High byte (bits 23-16) word count
+0x407	r/w	Channel 3 High byte (bits 23-16) word count
+0x4c6	r/w	Channel 5 High byte (bits 23-16) word count
+0x4ca	r/w	Channel 6 High byte (bits 23-16) word count
+0x4ce	r/w	Channel 7 High byte (bits 23-16) word count
+
+0x487	r/w	Channel 0 High byte (bits 31-24) page Register
+0x483	r/w	Channel 1 High byte (bits 31-24) page Register
+0x481	r/w	Channel 2 High byte (bits 31-24) page Register
+0x482	r/w	Channel 3 High byte (bits 31-24) page Register
+0x48b	r/w	Channel 5 High byte (bits 31-24) page Register
+0x489	r/w	Channel 6 High byte (bits 31-24) page Register
+0x48a	r/w	Channel 6 High byte (bits 31-24) page Register
+0x48f	r/w	High byte page Refresh
+
+0x4e0	r/w	Channel 0 Stop Register (bits 7-2)
+0x4e1	r/w	Channel 0 Stop Register (bits 15-8)
+0x4e2	r/w	Channel 0 Stop Register (bits 23-16)
+0x4e4	r/w	Channel 1 Stop Register (bits 7-2)
+0x4e5	r/w	Channel 1 Stop Register (bits 15-8)
+0x4e6	r/w	Channel 1 Stop Register (bits 23-16)
+0x4e8	r/w	Channel 2 Stop Register (bits 7-2)
+0x4e9	r/w	Channel 2 Stop Register (bits 15-8)
+0x4ea	r/w	Channel 2 Stop Register (bits 23-16)
+0x4ec	r/w	Channel 3 Stop Register (bits 7-2)
+0x4ed	r/w	Channel 3 Stop Register (bits 15-8)
+0x4ee	r/w	Channel 3 Stop Register (bits 23-16)
+0x4f4	r/w	Channel 5 Stop Register (bits 7-2)
+0x4f5	r/w	Channel 5 Stop Register (bits 15-8)
+0x4f6	r/w	Channel 5 Stop Register (bits 23-16)
+0x4f8	r/w	Channel 6 Stop Register (bits 7-2)
+0x4f9	r/w	Channel 6 Stop Register (bits 15-8)
+0x4fa	r/w	Channel 6 Stop Register (bits 23-16)
+0x4fc	r/w	Channel 7 Stop Register (bits 7-2)
+0x4fd	r/w	Channel 7 Stop Register (bits 15-8)
+0x4fe	r/w	Channel 7 Stop Register (bits 23-16)
+
+0x40a	write	Channels 0-3 Chaining Mode Register
+0x40a	read	Channel Interrupt Status Register
+0x4d4	write	Channels 4-7 Chaining Mode Register
+0x4d4	read	Chaining Mode Status
+0x40c	read	Chain Buffer Expiration Control Register
+
+0x410	write	Channel 0 Scatter-Gather Command Register
+0x411	write	Channel 1 Scatter-Gather Command Register
+0x412	write	Channel 2 Scatter-Gather Command Register
+0x413	write	Channel 3 Scatter-Gather Command Register
+0x415	write	Channel 5 Scatter-Gather Command Register
+0x416	write	Channel 6 Scatter-Gather Command Register
+0x417	write	Channel 7 Scatter-Gather Command Register
+
+0x418	read	Channel 0 Scatter-Gather Status Register
+0x419	read	Channel 1 Scatter-Gather Status Register
+0x41a	read	Channel 2 Scatter-Gather Status Register
+0x41b	read	Channel 3 Scatter-Gather Status Register
+0x41d	read	Channel 5 Scatter-Gather Status Register
+0x41e	read	Channel 5 Scatter-Gather Status Register
+0x41f	read	Channel 7 Scatter-Gather Status Register
+
+0x420-0x423 r/w	Channel 0 Scatter-Gather Descripter Table Pointer Register
+0x424-0x427 r/w	Channel 1 Scatter-Gather Descripter Table Pointer Register
+0x428-0x42b r/w	Channel 2 Scatter-Gather Descripter Table Pointer Register
+0x42c-0x42f r/w	Channel 3 Scatter-Gather Descripter Table Pointer Register
+0x434-0x437 r/w	Channel 5 Scatter-Gather Descripter Table Pointer Register
+0x438-0x43b r/w	Channel 6 Scatter-Gather Descripter Table Pointer Register
+0x43c-0x43f r/w	Channel 7 Scatter-Gather Descripter Table Pointer Register
 </verb>