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| author | Yuri Victorovich <yuri@FreeBSD.org> | 2023-02-04 06:58:11 +0000 |
|---|---|---|
| committer | Yuri Victorovich <yuri@FreeBSD.org> | 2023-02-04 06:58:53 +0000 |
| commit | 0ad876d5fd2d1befbfa7f01ab6fa8f5279ff8ab1 (patch) | |
| tree | 407808ad87b6c02e9ce423c94b6057ca06cd8b2d | |
| parent | 3604fc3235289e9c35c6b94289d3db523f357aab (diff) | |
| download | ports-0ad876d5fd2d1befbfa7f01ab6fa8f5279ff8ab1.tar.gz ports-0ad876d5fd2d1befbfa7f01ab6fa8f5279ff8ab1.zip | |
cad/py-cocotb: New port: Coroutine based cosimulation library for writing VHDL and Verilog
| -rw-r--r-- | cad/Makefile | 1 | ||||
| -rw-r--r-- | cad/py-cocotb/Makefile | 40 | ||||
| -rw-r--r-- | cad/py-cocotb/distinfo | 3 | ||||
| -rw-r--r-- | cad/py-cocotb/pkg-descr | 5 |
4 files changed, 49 insertions, 0 deletions
diff --git a/cad/Makefile b/cad/Makefile index fa412f520987..7d15ad17a9ab 100644 --- a/cad/Makefile +++ b/cad/Makefile @@ -102,6 +102,7 @@ SUBDIR += pcb-rnd SUBDIR += pdnmesh SUBDIR += py-cadquery + SUBDIR += py-cocotb SUBDIR += py-cq-editor SUBDIR += py-edalize SUBDIR += py-ezdxf diff --git a/cad/py-cocotb/Makefile b/cad/py-cocotb/Makefile new file mode 100644 index 000000000000..a2168ec07d4d --- /dev/null +++ b/cad/py-cocotb/Makefile @@ -0,0 +1,40 @@ +PORTNAME= cocotb +DISTVERSIONPREFIX= v +DISTVERSION= 1.7.2 +CATEGORIES= cad python +PKGNAMEPREFIX= ${PYTHON_PKGNAMEPREFIX} + +MAINTAINER= yuri@FreeBSD.org +COMMENT= Coroutine based cosimulation library for writing VHDL and Verilog +WWW= https://www.cocotb.org/ + +LICENSE= BSD3CLAUSE +LICENSE_FILE= ${WRKSRC}/LICENSE + +BUILD_DEPENDS= ${PYTHON_PKGNAMEPREFIX}wheel>0:devel/py-wheel@${PY_FLAVOR} +RUN_DEPENDS= ${PYTHON_PKGNAMEPREFIX}find-libpython>0:devel/py-find-libpython@${PY_FLAVOR} \ + gtkwave:cad/gtkwave + +USES= python:3.6+ +USE_PYTHON= pep517 autoplist pytest # https://github.com/cocotb/cocotb/issues/3230 +USE_GITHUB= yes + +TEST_ENV= ${MAKE_ENV} PYTHONPATH=${STAGEDIR}${PYTHONPREFIX_SITELIBDIR} +TEST_WRKSRC= ${WRKSRC}/tests + +OPTIONS_DEFINE= IVERILOG VERILATOR # GHDL - TODO +OPTIONS_DEFAULT= IVERILOG VERILATOR + +IVERILOG_DESC= Iverilog dependency +IVERILOG_RUN_DEPENDS= iverilog:cad/iverilog + +VERILATOR_DESC= Verilator dependency +VERILATOR_RUN_DEPENDS= verilator:cad/verilator + +post-install: + @${STRIP_CMD} \ + ${STAGEDIR}${PYTHON_SITELIBDIR}/cocotb/simulator${PYTHON_EXT_SUFFIX}.so \ + ${STAGEDIR}${PYTHON_SITELIBDIR}/cocotb/libs/lib*.so \ + ${STAGEDIR}${PYTHON_SITELIBDIR}/cocotb/libs/libcocotbvpi_icarus.vpl + +.include <bsd.port.mk> diff --git a/cad/py-cocotb/distinfo b/cad/py-cocotb/distinfo new file mode 100644 index 000000000000..f7f52cba0128 --- /dev/null +++ b/cad/py-cocotb/distinfo @@ -0,0 +1,3 @@ +TIMESTAMP = 1675490974 +SHA256 (cocotb-cocotb-v1.7.2_GH0.tar.gz) = 2b72f25e91a8733abc9a49171adcf67d04670eb64bdc6be0d8ee653ac6b1d69f +SIZE (cocotb-cocotb-v1.7.2_GH0.tar.gz) = 641521 diff --git a/cad/py-cocotb/pkg-descr b/cad/py-cocotb/pkg-descr new file mode 100644 index 000000000000..de72cfe264b0 --- /dev/null +++ b/cad/py-cocotb/pkg-descr @@ -0,0 +1,5 @@ +cocotb is an open source coroutine-based cosimulation testbench environment +for verifying VHDL and SystemVerilog RTL using Python. + +cocotb lets you verify chips like software: productive, simulator-agnostic, +in Python. |