cad/yosys-systemverilog: New port: SystemVerilog support for Yosys

7 files changed, 208 insertions, 0 deletions

diff --git a/cad/Makefile b/cad/Makefile
index 48be6f53129f..d8269b0f165f 100644
--- a/cad/Makefile
+++ b/cad/Makefile
@@ -151,6 +151,7 @@
     SUBDIR += xcircuit
     SUBDIR += xyce
     SUBDIR += yosys
+    SUBDIR += yosys-systemverilog
     SUBDIR += z88
     SUBDIR += zcad
 
diff --git a/cad/yosys-systemverilog/Makefile b/cad/yosys-systemverilog/Makefile
new file mode 100644
index 000000000000..e9f4a7f48dd6
--- /dev/null
+++ b/cad/yosys-systemverilog/Makefile
@@ -0,0 +1,93 @@
+PORTNAME=	yosys-systemverilog
+DISTVERSION=	2023-06-05
+CATEGORIES=	cad
+PKGNAMEPREFIX=
+
+MAINTAINER=	yuri@FreeBSD.org
+COMMENT=	SystemVerilog support for Yosys
+WWW=		https://github.com/antmicro/yosys-systemverilog
+
+LICENSE=	APACHE20
+LICENSE_FILE=	${WRKSRC}/LICENSE
+
+BUILD_DEPENDS=	bash:shells/bash \
+		yosys>0:cad/yosys
+LIB_DEPENDS=	libcapnp.so:devel/capnproto \
+		libffi.so:devel/libffi \
+		libsurelog.so:cad/surelog \
+		libuhdm.so:cad/uhdm
+RUN_DEPENDS=	yosys>0:cad/yosys
+
+USES=		cabal gmake pkgconfig python:build readline tcl
+
+USE_CABAL=	alex-3.3.0.0 \
+		cmdargs-0.10.22 \
+		githash-0.1.6.3 \
+		happy-1.20.1.1 \
+		hashable-1.4.2.0_1 \
+		primitive-0.8.0.0 \
+		th-compat-0.1.4_2 \
+		vector-0.13.0.0_3 \
+		vector-stream-0.1.0.0_2
+SKIP_CABAL_PLIST=	yes
+# in order to update USE_CABAL run 'make local-cabal-configure local-make-use-cabal'
+
+USE_GITHUB=	yes
+GH_ACCOUNT=	antmicro
+GH_TAGNAME=	00c9bce-${DISTVERSION}
+GH_TUPLE=	chipsalliance:yosys-f4pga-plugins:56f957c:yosys_f4pga_plugins/yosys-f4pga-plugins \
+		zachjs:sv2v:6c4ee8f:sv2v/sv2v \
+		YosysHQ:yosys:c5e4eec:yosys/yosys
+
+MAKE_ENV=	DESTDIR=${DESTDIR} \
+		HOME=${WRKSRC}
+MAKE_ARGS=	YOSYS_PATH=${LOCALBASE} -j${MAKE_JOBS_NUMBER}
+
+BINARY_ALIAS=	python3=${PYTHON_CMD} \
+		install=${FILESDIR}/install.sh
+
+OPTIONS_DEFINE=		TCMALLOC
+OPTIONS_DEFAULT=	TCMALLOC # should be the same TCMALLOC default as in cad/yosys, cad/surelog, cad/uhdm because surelog's lib is used in the yosys plugin cad/yosys-systemverilog
+
+TCMALLOC_LDFLAGS=	`pkg-config --libs libtcmalloc`
+TCMALLOC_LIB_DEPENDS=	libtcmalloc.so:devel/google-perftools
+
+post-extract:
+	@${CP} ${WRKSRC_yosys}/passes/pmgen/pmgen.py ${WRKSRC}/yosys-f4pga-plugins
+
+local-cabal-configure: check-cabal
+	@cd ${WRKSRC}/sv2v && \
+		${SETENV} ${MAKE_ENV} ${CABAL_HOME_ENV} ${CABAL_CMD} build --dry-run --disable-benchmarks --disable-tests --flags="${CABAL_FLAGS}" ${CABAL_WITH_ARGS} ${CABAL_LTO_ARGS} ${BUILD_ARGS} exe:sv2v
+
+local-make-use-cabal: check-cabal2tuple
+	@${_CABAL2TUPLE_CMD} ${CABAL2TUPLE_ARGS} ${WRKSRC}/sv2v || (${ECHO_CMD} "Did you forget to make do-cabal-configure ?" ; exit 1)
+
+do-build:
+	# UHDM plugin
+	${ECHO} "==> Building the C part (yosys-f4pga-plugins)"
+	@cd ${WRKSRC}/yosys-f4pga-plugins && ${SETENV} ${MAKE_ENV} ${GMAKE} ${MAKE_ARGS} ${ALL_TARGET}
+	# sv2v
+	${ECHO} "==> Building the Haskell part (sv2v)"
+	cd ${WRKSRC}/sv2v && \
+		${LN} -fs ${CABAL_DEPSDIR} && \
+		${LN} -fs ../cabal.project.local && \
+		${SETENV} ${MAKE_ENV} ${CABAL_HOME_ENV} ${CABAL_CMD} build --offline --disable-benchmarks --disable-tests ${CABAL_WITH_ARGS} ${CABAL_LTO_ARGS} --flags "${CABAL_FLAGS}" ${BUILD_ARGS} exe:sv2v
+
+do-install:
+	# create directories
+	@${MKDIR} \
+		${STAGEDIR}${PREFIX}/share/yosys/plugins/fasm_extra_modules \
+		${STAGEDIR}${PREFIX}/share/yosys/quicklogic/pp3 \
+		${STAGEDIR}${PREFIX}/share/yosys/quicklogic/qlf_k6n10 \
+		${STAGEDIR}${PREFIX}/share/yosys/quicklogic/qlf_k6n10f \
+		${STAGEDIR}${PREFIX}/share/yosys/nexus
+	# UHDM plugin
+	cd ${WRKSRC}/yosys-f4pga-plugins && ${SETENV} ${MAKE_ENV} ${GMAKE} ${MAKE_ARGS} ${INSTALL_TARGET}
+	# sv2v
+	${INSTALL_PROGRAM} \
+		${WRKSRC}/sv2v/dist-newstyle/build/*-freebsd/ghc-*/sv2v-*/x/sv2v/build/sv2v/sv2v \
+		${STAGEDIR}${PREFIX}/bin
+	# strip binaries
+	${STRIP_CMD} ${STAGEDIR}${PREFIX}/share/yosys/plugins/*.so
+
+.include <bsd.port.mk>
diff --git a/cad/yosys-systemverilog/distinfo b/cad/yosys-systemverilog/distinfo
new file mode 100644
index 000000000000..b5f91e6485fd
--- /dev/null
+++ b/cad/yosys-systemverilog/distinfo
@@ -0,0 +1,35 @@
+TIMESTAMP = 1686074483
+SHA256 (cabal/alex-3.3.0.0/alex-3.3.0.0.tar.gz) = 810f8e85ea6b87c37cba10f7660d7f1aa0ba251c1275e3a18c312964bb329a63
+SIZE (cabal/alex-3.3.0.0/alex-3.3.0.0.tar.gz) = 86004
+SHA256 (cabal/cmdargs-0.10.22/cmdargs-0.10.22.tar.gz) = b8b12e7f8795cf13037bb062d453b86c788eae62558586f59e9419aabe6e9bef
+SIZE (cabal/cmdargs-0.10.22/cmdargs-0.10.22.tar.gz) = 65154
+SHA256 (cabal/githash-0.1.6.3/githash-0.1.6.3.tar.gz) = fcba79b60ef87bdd4976332e998589a62e1be012b932b543b49de5e0620eef1b
+SIZE (cabal/githash-0.1.6.3/githash-0.1.6.3.tar.gz) = 7617
+SHA256 (cabal/happy-1.20.1.1/happy-1.20.1.1.tar.gz) = 8b4e7dc5a6c5fd666f8f7163232931ab28746d0d17da8fa1cbd68be9e878881b
+SIZE (cabal/happy-1.20.1.1/happy-1.20.1.1.tar.gz) = 183409
+SHA256 (cabal/hashable-1.4.2.0/hashable-1.4.2.0.tar.gz) = 1b4000ea82b81f69d46d0af4152c10c6303873510738e24cfc4767760d30e3f8
+SIZE (cabal/hashable-1.4.2.0/hashable-1.4.2.0.tar.gz) = 25094
+SHA256 (cabal/hashable-1.4.2.0/revision/1.cabal) = 585792335d5541dba78fa8dfcb291a89cd5812a281825ff7a44afa296ab5d58a
+SIZE (cabal/hashable-1.4.2.0/revision/1.cabal) = 4520
+SHA256 (cabal/primitive-0.8.0.0/primitive-0.8.0.0.tar.gz) = 5553c21b4a789f9b591eed69e598cc58484c274af29250e517b5a8bcc62b995f
+SIZE (cabal/primitive-0.8.0.0/primitive-0.8.0.0.tar.gz) = 57222
+SHA256 (cabal/th-compat-0.1.4/th-compat-0.1.4.tar.gz) = d8f97ac14ab47b6b8a7b0fdb4ff95426322ec56badd01652ac15da4a44d4bab8
+SIZE (cabal/th-compat-0.1.4/th-compat-0.1.4.tar.gz) = 14838
+SHA256 (cabal/th-compat-0.1.4/revision/2.cabal) = e5ae7c083ef3a22248558f8451669bb1c55ea8090f5908b86b9033743c161730
+SIZE (cabal/th-compat-0.1.4/revision/2.cabal) = 3224
+SHA256 (cabal/vector-0.13.0.0/vector-0.13.0.0.tar.gz) = c5d3167d15e12f52e00879ddf304a591672a74e369cc47bc5c7fa1d5a8d15b4f
+SIZE (cabal/vector-0.13.0.0/vector-0.13.0.0.tar.gz) = 154509
+SHA256 (cabal/vector-0.13.0.0/revision/3.cabal) = fa5cac81a17a5af388716792e8b99c24b3b66770086756d0d8b23f8272a0244c
+SIZE (cabal/vector-0.13.0.0/revision/3.cabal) = 9112
+SHA256 (cabal/vector-stream-0.1.0.0/vector-stream-0.1.0.0.tar.gz) = a888210f6467f155090653734be5cc920406a07227e0d3adb59096716fdb806c
+SIZE (cabal/vector-stream-0.1.0.0/vector-stream-0.1.0.0.tar.gz) = 12377
+SHA256 (cabal/vector-stream-0.1.0.0/revision/2.cabal) = f5d6d5291cd1b5f2f063403593f1f5c8127d692c888eedeb3e1eb40497a88dca
+SIZE (cabal/vector-stream-0.1.0.0/revision/2.cabal) = 1404
+SHA256 (cabal/antmicro-yosys-systemverilog-2023-06-05-00c9bce-2023-06-05_GH0.tar.gz) = 7dbc3b1607a39478f77fd35689483b574cf7c0111dd262bc7ed7ea936e31a75f
+SIZE (cabal/antmicro-yosys-systemverilog-2023-06-05-00c9bce-2023-06-05_GH0.tar.gz) = 158127
+SHA256 (cabal/chipsalliance-yosys-f4pga-plugins-56f957c_GH0.tar.gz) = e2bf0adae00912e07524f2ecf5f6de3d395d283890652d38568175ad56d7bada
+SIZE (cabal/chipsalliance-yosys-f4pga-plugins-56f957c_GH0.tar.gz) = 2690136
+SHA256 (cabal/zachjs-sv2v-6c4ee8f_GH0.tar.gz) = b03955f19128d05c2a2c9d162b2b946fd23a220146abbc5b7847c83c3f937e90
+SIZE (cabal/zachjs-sv2v-6c4ee8f_GH0.tar.gz) = 279380
+SHA256 (cabal/YosysHQ-yosys-c5e4eec_GH0.tar.gz) = ad4b43d55d98d2cc6f4892c1af6b0770af994a51f0cf8d450029f2a404738b8a
+SIZE (cabal/YosysHQ-yosys-c5e4eec_GH0.tar.gz) = 2542646
diff --git a/cad/yosys-systemverilog/files/install.sh b/cad/yosys-systemverilog/files/install.sh
new file mode 100755
index 000000000000..7962e5c28942
--- /dev/null
+++ b/cad/yosys-systemverilog/files/install.sh
@@ -0,0 +1,14 @@
+#!/bin/sh
+
+##
+## workaround for
+## * https://github.com/chipsalliance/yosys-f4pga-plugins/issues/527
+##
+##
+
+if [ "$1" != "-D" ]; then
+	exit 1
+fi
+
+#/usr/bin/install -m 0644 $2 ${DESTDIR}$3
+/usr/bin/install $2 $3
diff --git a/cad/yosys-systemverilog/files/patch-sv2v_Makefile b/cad/yosys-systemverilog/files/patch-sv2v_Makefile
new file mode 100644
index 000000000000..1b36cb36f007
--- /dev/null
+++ b/cad/yosys-systemverilog/files/patch-sv2v_Makefile
@@ -0,0 +1,11 @@
+--- sv2v/Makefile.orig	2023-05-10 12:48:15 UTC
++++ sv2v/Makefile
+@@ -4,7 +4,7 @@ all: sv2v
+ 
+ sv2v:
+ 	mkdir -p bin
+-	stack install --install-ghc --local-bin-path bin
++	stack config set system-ghc --global true && stack build --system-ghc --no-install-ghc
+ 
+ clean:
+ 	stack clean
diff --git a/cad/yosys-systemverilog/pkg-descr b/cad/yosys-systemverilog/pkg-descr
new file mode 100644
index 000000000000..c7f034ecab6b
--- /dev/null
+++ b/cad/yosys-systemverilog/pkg-descr
@@ -0,0 +1,2 @@
+yosys-systemverilog is a YoSys add-on that contains all moving parts needed to
+get SystemVerilog support enabled in Yosys.
diff --git a/cad/yosys-systemverilog/pkg-plist b/cad/yosys-systemverilog/pkg-plist
new file mode 100644
index 000000000000..7ab2e58b7515
--- /dev/null
+++ b/cad/yosys-systemverilog/pkg-plist
@@ -0,0 +1,52 @@
+bin/sv2v
+share/yosys/nexus/dsp_rules.txt
+share/yosys/plugins/design_introspection.so
+share/yosys/plugins/dsp-ff.so
+share/yosys/plugins/fasm.so
+share/yosys/plugins/fasm_extra_modules/BANK.v
+share/yosys/plugins/integrateinv.so
+share/yosys/plugins/params.so
+share/yosys/plugins/ql-iob.so
+share/yosys/plugins/ql-qlf.so
+share/yosys/plugins/sdc.so
+share/yosys/plugins/systemverilog.so
+share/yosys/plugins/uhdm.so
+share/yosys/plugins/xdc.so
+share/yosys/quicklogic/pp3/abc9_map.v
+share/yosys/quicklogic/pp3/abc9_model.v
+share/yosys/quicklogic/pp3/abc9_unmap.v
+share/yosys/quicklogic/pp3/bram_init_32.vh
+share/yosys/quicklogic/pp3/bram_init_8_16.vh
+share/yosys/quicklogic/pp3/brams.txt
+share/yosys/quicklogic/pp3/brams_map.v
+share/yosys/quicklogic/pp3/brams_sim.v
+share/yosys/quicklogic/pp3/cells_map.v
+share/yosys/quicklogic/pp3/cells_sim.v
+share/yosys/quicklogic/pp3/ffs_map.v
+share/yosys/quicklogic/pp3/latches_map.v
+share/yosys/quicklogic/pp3/lut_map.v
+share/yosys/quicklogic/pp3/lutdefs.txt
+share/yosys/quicklogic/pp3/mult_sim.v
+share/yosys/quicklogic/pp3/qlal3_sim.v
+share/yosys/quicklogic/pp3/qlal4s3b_sim.v
+share/yosys/quicklogic/qlf_k6n10/arith_map.v
+share/yosys/quicklogic/qlf_k6n10/brams.txt
+share/yosys/quicklogic/qlf_k6n10/brams_map.v
+share/yosys/quicklogic/qlf_k6n10/cells_sim.v
+share/yosys/quicklogic/qlf_k6n10/dsp_map.v
+share/yosys/quicklogic/qlf_k6n10/ffs_map.v
+share/yosys/quicklogic/qlf_k6n10/lut_map.v
+share/yosys/quicklogic/qlf_k6n10f/TDP18K_FIFO.v
+share/yosys/quicklogic/qlf_k6n10f/arith_map.v
+share/yosys/quicklogic/qlf_k6n10f/brams.txt
+share/yosys/quicklogic/qlf_k6n10f/brams_final_map.v
+share/yosys/quicklogic/qlf_k6n10f/brams_map.v
+share/yosys/quicklogic/qlf_k6n10f/brams_sim.v
+share/yosys/quicklogic/qlf_k6n10f/cells_sim.v
+share/yosys/quicklogic/qlf_k6n10f/dsp_final_map.v
+share/yosys/quicklogic/qlf_k6n10f/dsp_map.v
+share/yosys/quicklogic/qlf_k6n10f/dsp_sim.v
+share/yosys/quicklogic/qlf_k6n10f/ffs_map.v
+share/yosys/quicklogic/qlf_k6n10f/primitives_sim.v
+share/yosys/quicklogic/qlf_k6n10f/sram1024x18.v
+share/yosys/quicklogic/qlf_k6n10f/ufifo_ctl.v