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-rw-r--r--cad/iverilog/Makefile23
1 files changed, 16 insertions, 7 deletions
diff --git a/cad/iverilog/Makefile b/cad/iverilog/Makefile
index e0286f9c952b..c1862a405bc1 100644
--- a/cad/iverilog/Makefile
+++ b/cad/iverilog/Makefile
@@ -1,19 +1,28 @@
-# Created by: Ying-Chieh Liao <ijliao@FreeBSD.org>
-
PORTNAME= iverilog
-PORTVERSION= 11.0
+DISTVERSIONPREFIX= v
+DISTVERSION= 12_0
+PORTREVISION= 1
CATEGORIES= cad
-MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v11/
-DISTNAME= verilog-${PORTVERSION}
-MAINTAINER= zeising@FreeBSD.org
+MAINTAINER= kbowling@FreeBSD.org
COMMENT= Verilog simulation and synthesis tool
+WWW= https://steveicarus.github.io/iverilog/
LICENSE= GPLv2
+BUILD_DEPENDS= autoconf:devel/autoconf \
+ gperf:devel/gperf
+
+USES= bison compiler:c++11-lang gmake readline
+
+USE_GITHUB= yes
+GH_ACCOUNT= steveicarus
+
GNU_CONFIGURE= yes
CONFIGURE_ARGS= --disable-suffix
+GNU_CONFIGURE_MANPREFIX= ${PREFIX}/share
-USES= bison compiler:c++11-lang gmake readline
+pre-configure:
+ @cd ${WRKSRC} && sh autoconf.sh
.include <bsd.port.mk>