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-rw-r--r--cad/iverilog/Makefile17
-rw-r--r--cad/iverilog/distinfo6
2 files changed, 8 insertions, 15 deletions
diff --git a/cad/iverilog/Makefile b/cad/iverilog/Makefile
index c1862a405bc1..7a2961825e9a 100644
--- a/cad/iverilog/Makefile
+++ b/cad/iverilog/Makefile
@@ -1,8 +1,9 @@
PORTNAME= iverilog
-DISTVERSIONPREFIX= v
-DISTVERSION= 12_0
-PORTREVISION= 1
+DISTVERSION= 12.0
+PORTREVISION= 2
CATEGORIES= cad
+MASTER_SITES= SF/${PORTNAME}/${PORTNAME}/${DISTVERSION}
+DISTNAME= verilog-${DISTVERSION}
MAINTAINER= kbowling@FreeBSD.org
COMMENT= Verilog simulation and synthesis tool
@@ -10,19 +11,11 @@ WWW= https://steveicarus.github.io/iverilog/
LICENSE= GPLv2
-BUILD_DEPENDS= autoconf:devel/autoconf \
- gperf:devel/gperf
+BUILD_DEPENDS= gperf:devel/gperf
USES= bison compiler:c++11-lang gmake readline
-USE_GITHUB= yes
-GH_ACCOUNT= steveicarus
-
GNU_CONFIGURE= yes
CONFIGURE_ARGS= --disable-suffix
-GNU_CONFIGURE_MANPREFIX= ${PREFIX}/share
-
-pre-configure:
- @cd ${WRKSRC} && sh autoconf.sh
.include <bsd.port.mk>
diff --git a/cad/iverilog/distinfo b/cad/iverilog/distinfo
index 13746659378b..c94c3b27a23c 100644
--- a/cad/iverilog/distinfo
+++ b/cad/iverilog/distinfo
@@ -1,3 +1,3 @@
-TIMESTAMP = 1681749176
-SHA256 (steveicarus-iverilog-v12_0_GH0.tar.gz) = a68cb1ef7c017ef090ebedb2bc3e39ef90ecc70a3400afb4aa94303bc3beaa7d
-SIZE (steveicarus-iverilog-v12_0_GH0.tar.gz) = 2995096
+TIMESTAMP = 1757814677
+SHA256 (verilog-12.0.tar.gz) = 03848551a9c5ec390fefcff1bbcca14765c7aa035ee85bc9cbcb0424e0149fd4
+SIZE (verilog-12.0.tar.gz) = 3334697