path: root/Bindings/pinctrl/intel,pinctrl-keembay.yaml

# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/intel,pinctrl-keembay.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Intel Keem Bay pin controller Device Tree Bindings

maintainers:
  - Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com>

description: |
  Intel Keem Bay SoC integrates a pin controller which enables control
  of pin directions, input/output values and configuration
  for a total of 80 pins.

properties:
  compatible:
    const: intel,keembay-pinctrl

  reg:
    maxItems: 2

  gpio-controller: true

  '#gpio-cells':
    const: 2

  ngpios:
    description: The number of GPIOs exposed.
    const: 80

  interrupts:
    description:
      Specifies the interrupt lines to be used by the controller.
      Each interrupt line is shared by upto 4 GPIO lines.
    maxItems: 8

  interrupt-controller: true

  '#interrupt-cells':
    const: 2

patternProperties:
  '^gpio@[0-9a-f]*$':
    type: object

    description:
      Child nodes can be specified to contain pin configuration information,
      which can then be utilized by pinctrl client devices.
      The following properties are supported.

    properties:
      pins:
        description: |
          The name(s) of the pins to be configured in the child node.
          Supported pin names are "GPIO0" up to "GPIO79".

      bias-disable: true

      bias-pull-down: true

      bias-pull-up: true

      drive-strength:
        description: IO pads drive strength in milli Ampere.
        enum: [2, 4, 8, 12]

      bias-bus-hold:
        type: boolean

      input-schmitt-enable:
        type: boolean

      slew-rate:
        description: GPIO slew rate control.
                      0 - Fast(~100MHz)
                      1 - Slow(~50MHz)
        enum: [0, 1]

additionalProperties: false

required:
  - compatible
  - reg
  - gpio-controller
  - ngpios
  - '#gpio-cells'
  - interrupts
  - interrupt-controller
  - '#interrupt-cells'

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    // Example 1
    gpio@0 {
        compatible = "intel,keembay-pinctrl";
        reg = <0x600b0000 0x88>,
              <0x600b0190 0x1ac>;
        gpio-controller;
        ngpios = <0x50>;
        #gpio-cells = <0x2>;
        interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-controller;
        #interrupt-cells = <2>;
    };

    // Example 2
    gpio@1 {
        compatible = "intel,keembay-pinctrl";
        reg = <0x600c0000 0x88>,
              <0x600c0190 0x1ac>;
        gpio-controller;
        ngpios = <0x50>;
        #gpio-cells = <0x2>;
        interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-controller;
        #interrupt-cells = <2>;
    };