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authorMitchell Horne <mhorne@FreeBSD.org>2021-04-01 13:19:43 +0000
committerMitchell Horne <mhorne@FreeBSD.org>2021-07-29 15:01:11 +0000
commitd876c5a052fb589f213d20da2c146e5471047044 (patch)
tree1ab87b9cd155a6f4952f31cd415d2f14f34a1f44
parenta2d252f89fbccae119c8401a6c9a89d8f088b765 (diff)
downloadsrc-d876c5a052fb589f213d20da2c146e5471047044.tar.gz
src-d876c5a052fb589f213d20da2c146e5471047044.zip
hwpmc_arm64: fill kern.hwpmc.cpuid
This will be used to detect supported pmu events. The expected format is the MIDR register with the revision and variant fields masked. See also: lib/libpmc/pmu-events/arch/arm64/mapfile.csv. MFC after: 2 weeks Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D30601 (cherry picked from commit 5867cccdc49df3e7eb3147d6516b488dd8384afe)
-rw-r--r--sys/dev/hwpmc/hwpmc_arm64.c13
1 files changed, 13 insertions, 0 deletions
diff --git a/sys/dev/hwpmc/hwpmc_arm64.c b/sys/dev/hwpmc/hwpmc_arm64.c
index ba98eaefcc9a..be26605bad51 100644
--- a/sys/dev/hwpmc/hwpmc_arm64.c
+++ b/sys/dev/hwpmc/hwpmc_arm64.c
@@ -505,6 +505,7 @@ pmc_arm64_initialize()
struct pmc_classdep *pcd;
int idcode, impcode;
int reg;
+ uint64_t midr;
reg = arm64_pmcr_read();
arm64_npmcs = (reg & PMCR_N_MASK) >> PMCR_N_SHIFT;
@@ -514,6 +515,18 @@ pmc_arm64_initialize()
PMCDBG1(MDP, INI, 1, "arm64-init npmcs=%d", arm64_npmcs);
/*
+ * Write the CPU model to kern.hwpmc.cpuid.
+ *
+ * We zero the variant and revision fields.
+ *
+ * TODO: how to handle differences between cores due to big.LITTLE?
+ * For now, just use MIDR from CPU 0.
+ */
+ midr = (uint64_t)(pcpu_find(0)->pc_midr);
+ midr &= ~(CPU_VAR_MASK | CPU_REV_MASK);
+ snprintf(pmc_cpuid, sizeof(pmc_cpuid), "0x%016lx", midr);
+
+ /*
* Allocate space for pointers to PMC HW descriptors and for
* the MDEP structure used by MI code.
*/