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authorEmmanuel Vadot <manu@FreeBSD.org>2018-02-09 22:33:22 +0000
committerEmmanuel Vadot <manu@FreeBSD.org>2018-02-09 22:33:22 +0000
commit16ae49e2bea5badc71c2265966ec2a9b0ba541dc (patch)
tree5ff3ed27eadaf4f2d05b771bc108bd500b3d8f48
parent550370858c61e6f7fe3832de73daa9cc25ba716a (diff)
downloadsrc-16ae49e2bea5badc71c2265966ec2a9b0ba541dc.tar.gz
src-16ae49e2bea5badc71c2265966ec2a9b0ba541dc.zip
Update our copies of the Device Tree Source to Linux 4.15vendor/device-tree/4.15
Notes
Notes: svn path=/vendor/device-tree/dist/; revision=329088 svn path=/vendor/device-tree/4.15/; revision=329090; tag=vendor/device-tree/4.15
-rw-r--r--Bindings/arm/actions.txt1
-rw-r--r--Bindings/arm/amlogic.txt8
-rw-r--r--Bindings/arm/amlogic/analog-top.txt20
-rw-r--r--Bindings/arm/amlogic/assist.txt17
-rw-r--r--Bindings/arm/amlogic/bootrom.txt17
-rw-r--r--Bindings/arm/amlogic/pmu.txt18
-rw-r--r--Bindings/arm/amlogic/smp-sram.txt32
-rw-r--r--Bindings/arm/bcm/brcm,brcmstb.txt6
-rw-r--r--Bindings/arm/bcm/brcm,hr2.txt14
-rw-r--r--Bindings/arm/ccn.txt2
-rw-r--r--Bindings/arm/cpus.txt2
-rw-r--r--Bindings/arm/mediatek/mediatek,apmixedsys.txt2
-rw-r--r--Bindings/arm/mediatek/mediatek,audsys.txt22
-rw-r--r--Bindings/arm/mediatek/mediatek,bdpsys.txt1
-rw-r--r--Bindings/arm/mediatek/mediatek,ethsys.txt1
-rw-r--r--Bindings/arm/mediatek/mediatek,hifsys.txt1
-rw-r--r--Bindings/arm/mediatek/mediatek,imgsys.txt1
-rw-r--r--Bindings/arm/mediatek/mediatek,infracfg.txt2
-rw-r--r--Bindings/arm/mediatek/mediatek,jpgdecsys.txt22
-rw-r--r--Bindings/arm/mediatek/mediatek,mcucfg.txt22
-rw-r--r--Bindings/arm/mediatek/mediatek,mfgcfg.txt22
-rw-r--r--Bindings/arm/mediatek/mediatek,mmsys.txt1
-rw-r--r--Bindings/arm/mediatek/mediatek,pciesys.txt22
-rw-r--r--Bindings/arm/mediatek/mediatek,pericfg.txt2
-rw-r--r--Bindings/arm/mediatek/mediatek,sgmiisys.txt22
-rw-r--r--Bindings/arm/mediatek/mediatek,ssusbsys.txt22
-rw-r--r--Bindings/arm/mediatek/mediatek,topckgen.txt2
-rw-r--r--Bindings/arm/mediatek/mediatek,vdecsys.txt1
-rw-r--r--Bindings/arm/mediatek/mediatek,vencsys.txt1
-rw-r--r--Bindings/arm/omap/crossbar.txt2
-rw-r--r--Bindings/arm/omap/ctrl.txt2
-rw-r--r--Bindings/arm/realtek.txt2
-rw-r--r--Bindings/arm/rockchip.txt4
-rw-r--r--Bindings/arm/samsung/pmu.txt3
-rw-r--r--Bindings/arm/samsung/samsung-boards.txt3
-rw-r--r--Bindings/arm/shmobile.txt16
-rw-r--r--Bindings/arm/sp810.txt2
-rw-r--r--Bindings/arm/spe-pmu.txt20
-rw-r--r--Bindings/arm/sunxi.txt2
-rw-r--r--Bindings/arm/tegra/nvidia,tegra20-mc.txt2
-rw-r--r--Bindings/arm/vexpress-sysreg.txt2
-rw-r--r--Bindings/ata/ahci-ceva.txt39
-rw-r--r--Bindings/ata/ahci-platform.txt2
-rw-r--r--Bindings/ata/imx-sata.txt2
-rw-r--r--Bindings/bus/imx-weim.txt2
-rw-r--r--Bindings/bus/sunxi-rsb.txt2
-rw-r--r--Bindings/bus/ti-sysc.txt93
-rw-r--r--Bindings/bus/ts-nbus.txt50
-rw-r--r--Bindings/clock/arm-syscon-icst.txt2
-rw-r--r--Bindings/clock/axi-clkgen.txt2
-rw-r--r--Bindings/clock/brcm,bcm2835-aux-clock.txt2
-rw-r--r--Bindings/clock/brcm,iproc-clocks.txt14
-rw-r--r--Bindings/clock/clk-exynos-audss.txt8
-rw-r--r--Bindings/clock/clk-s5pv210-audss.txt2
-rw-r--r--Bindings/clock/dove-divider-clock.txt2
-rw-r--r--Bindings/clock/exynos4-clock.txt45
-rw-r--r--Bindings/clock/exynos5250-clock.txt2
-rw-r--r--Bindings/clock/exynos5410-clock.txt2
-rw-r--r--Bindings/clock/exynos5420-clock.txt2
-rw-r--r--Bindings/clock/exynos5433-clock.txt16
-rw-r--r--Bindings/clock/exynos5440-clock.txt2
-rw-r--r--Bindings/clock/imx1-clock.txt4
-rw-r--r--Bindings/clock/imx6q-clock.txt4
-rw-r--r--Bindings/clock/maxim,max77686.txt4
-rw-r--r--Bindings/clock/qcom,rpmcc.txt11
-rw-r--r--Bindings/clock/renesas,cpg-mssr.txt5
-rw-r--r--Bindings/clock/renesas,rz-cpg-clocks.txt4
-rw-r--r--Bindings/clock/st/st,clkgen.txt2
-rw-r--r--Bindings/clock/sunxi-ccu.txt4
-rw-r--r--Bindings/clock/sunxi.txt16
-rw-r--r--Bindings/clock/ti,cdce706.txt2
-rw-r--r--Bindings/clock/ti-keystone-pllctrl.txt2
-rw-r--r--Bindings/clock/zx296702-clk.txt4
-rw-r--r--Bindings/common-properties.txt26
-rw-r--r--Bindings/crypto/fsl-sec4.txt4
-rw-r--r--Bindings/crypto/samsung,exynos-rng4.txt (renamed from Bindings/rng/samsung,exynos-rng4.txt)0
-rw-r--r--Bindings/crypto/sun4i-ss.txt2
-rw-r--r--Bindings/devfreq/event/rockchip-dfi.txt2
-rw-r--r--Bindings/display/atmel,lcdc.txt4
-rw-r--r--Bindings/display/bridge/adi,adv7511.txt4
-rw-r--r--Bindings/display/bridge/renesas,dw-hdmi.txt2
-rw-r--r--Bindings/display/bridge/sii9234.txt49
-rw-r--r--Bindings/display/etnaviv/etnaviv-drm.txt2
-rw-r--r--Bindings/display/faraday,tve200.txt54
-rw-r--r--Bindings/display/google,goldfish-fb.txt17
-rw-r--r--Bindings/display/imx/fsl-imx-drm.txt2
-rw-r--r--Bindings/display/imx/hdmi.txt4
-rw-r--r--Bindings/display/msm/dsi.txt36
-rw-r--r--Bindings/display/msm/edp.txt20
-rw-r--r--Bindings/display/msm/hdmi.txt8
-rw-r--r--Bindings/display/msm/mdp5.txt32
-rw-r--r--Bindings/display/panel/orisetech,otm8009a.txt21
-rw-r--r--Bindings/display/panel/raspberrypi,7inch-touchscreen.txt49
-rw-r--r--Bindings/display/panel/samsung,s6e63j0x03.txt24
-rw-r--r--Bindings/display/panel/seiko,43wvf1g.txt23
-rw-r--r--Bindings/display/panel/toshiba,lt089ac29000.txt8
-rw-r--r--Bindings/display/rockchip/rockchip-lvds.txt99
-rw-r--r--Bindings/display/simple-framebuffer.txt2
-rw-r--r--Bindings/display/sunxi/sun4i-drm.txt16
-rw-r--r--Bindings/display/tegra/nvidia,tegra20-host1x.txt4
-rw-r--r--Bindings/dma/qcom_hidma_mgmt.txt4
-rw-r--r--Bindings/dma/renesas,usb-dmac.txt2
-rw-r--r--Bindings/dma/sprd-dma.txt41
-rw-r--r--Bindings/dma/stm32-dma.txt6
-rw-r--r--Bindings/dma/stm32-dmamux.txt84
-rw-r--r--Bindings/dma/stm32-mdma.txt94
-rw-r--r--Bindings/dma/sun4i-dma.txt4
-rw-r--r--Bindings/dma/sun6i-dma.txt30
-rw-r--r--Bindings/dma/ti-edma.txt6
-rw-r--r--Bindings/dma/zxdma.txt4
-rw-r--r--Bindings/eeprom/at25.txt13
-rw-r--r--Bindings/eeprom/eeprom.txt2
-rw-r--r--Bindings/firmware/nvidia,tegra186-bpmp.txt2
-rw-r--r--Bindings/firmware/qcom,scm.txt2
-rw-r--r--Bindings/gpio/gpio-altera.txt2
-rw-r--r--Bindings/gpio/gpio-dsp-keystone.txt2
-rw-r--r--Bindings/gpio/gpio-max3191x.txt59
-rw-r--r--Bindings/gpio/gpio-pca953x.txt2
-rw-r--r--Bindings/gpio/gpio-tz1090-pdc.txt2
-rw-r--r--Bindings/gpio/gpio-tz1090.txt2
-rw-r--r--Bindings/gpio/gpio-uniphier.txt52
-rw-r--r--Bindings/gpio/renesas,gpio-rcar.txt2
-rw-r--r--Bindings/gpio/snps-dwapb-gpio.txt1
-rw-r--r--Bindings/gpu/arm,mali-utgard.txt16
-rw-r--r--Bindings/hsi/omap-ssi.txt13
-rw-r--r--Bindings/hwmon/gpio-fan.txt (renamed from Bindings/gpio/gpio-fan.txt)0
-rw-r--r--Bindings/hwmon/jc42.txt4
-rw-r--r--Bindings/hwmon/max1619.txt12
-rw-r--r--Bindings/hwmon/max31785.txt22
-rw-r--r--Bindings/i2c/i2c-aspeed.txt7
-rw-r--r--Bindings/i2c/i2c-axxia.txt2
-rw-r--r--Bindings/i2c/i2c-davinci.txt12
-rw-r--r--Bindings/i2c/i2c-gpio.txt32
-rw-r--r--Bindings/i2c/i2c-jz4780.txt2
-rw-r--r--Bindings/i2c/i2c-mux.txt4
-rw-r--r--Bindings/i2c/i2c-rcar.txt1
-rw-r--r--Bindings/i2c/i2c-sunxi-p2wi.txt2
-rw-r--r--Bindings/i2c/i2c.txt4
-rw-r--r--Bindings/iio/adc/mcp320x.txt14
-rw-r--r--Bindings/iio/adc/mt6577_auxadc.txt1
-rw-r--r--Bindings/iio/dac/ds4424.txt20
-rw-r--r--Bindings/iio/dac/ti-dac082s085.txt34
-rw-r--r--Bindings/iio/health/max30100.txt4
-rw-r--r--Bindings/iio/health/max30102.txt2
-rw-r--r--Bindings/iio/magnetometer/ak8974.txt2
-rw-r--r--Bindings/iio/magnetometer/ak8975.txt2
-rw-r--r--Bindings/iio/pressure/hp03.txt2
-rw-r--r--Bindings/iio/st-sensors.txt4
-rw-r--r--Bindings/input/gpio-mouse.txt32
-rw-r--r--Bindings/input/sun4i-lradc-keys.txt2
-rw-r--r--Bindings/input/touchscreen/bu21013.txt2
-rw-r--r--Bindings/input/touchscreen/egalax-ts.txt2
-rw-r--r--Bindings/input/touchscreen/exc3000.txt27
-rw-r--r--Bindings/input/touchscreen/goodix.txt3
-rw-r--r--Bindings/input/touchscreen/hideep.txt42
-rw-r--r--Bindings/input/touchscreen/imx6ul_tsc.txt2
-rw-r--r--Bindings/input/touchscreen/samsung,s6sy761.txt34
-rw-r--r--Bindings/interrupt-controller/allwinner,sunxi-nmi.txt2
-rw-r--r--Bindings/interrupt-controller/amlogic,meson-gpio-intc.txt36
-rw-r--r--Bindings/interrupt-controller/arm,gic-v3.txt4
-rw-r--r--Bindings/interrupt-controller/arm,gic.txt4
-rw-r--r--Bindings/interrupt-controller/brcm,l2-intc.txt3
-rw-r--r--Bindings/interrupt-controller/fsl,ls-scfg-msi.txt1
-rw-r--r--Bindings/interrupt-controller/img,meta-intc.txt2
-rw-r--r--Bindings/interrupt-controller/img,pdc-intc.txt2
-rw-r--r--Bindings/interrupt-controller/openrisc,ompic.txt22
-rw-r--r--Bindings/interrupt-controller/renesas,irqc.txt3
-rw-r--r--Bindings/interrupt-controller/socionext,synquacer-exiu.txt32
-rw-r--r--Bindings/interrupt-controller/st,spear3xx-shirq.txt2
-rw-r--r--Bindings/interrupt-controller/st,stm32-exti.txt4
-rw-r--r--Bindings/interrupt-controller/ti,keystone-irq.txt2
-rw-r--r--Bindings/iommu/qcom,iommu.txt2
-rw-r--r--Bindings/iommu/renesas,ipmmu-vmsa.txt2
-rw-r--r--Bindings/leds/register-bit-led.txt16
-rw-r--r--Bindings/mailbox/altera-mailbox.txt6
-rw-r--r--Bindings/mailbox/brcm,iproc-pdc-mbox.txt2
-rw-r--r--Bindings/mailbox/ti,message-manager.txt2
-rw-r--r--Bindings/marvell.txt4
-rw-r--r--Bindings/media/cec-gpio.txt32
-rw-r--r--Bindings/media/exynos5-gsc.txt11
-rw-r--r--Bindings/media/i2c/imx274.txt33
-rw-r--r--Bindings/media/i2c/nokia,smia.txt2
-rw-r--r--Bindings/media/i2c/tc358743.txt2
-rw-r--r--Bindings/media/img-ir-rev1.txt2
-rw-r--r--Bindings/media/mediatek-vcodec.txt2
-rw-r--r--Bindings/media/rcar_vin.txt2
-rw-r--r--Bindings/media/renesas,vsp1.txt2
-rw-r--r--Bindings/media/rockchip-rga.txt33
-rw-r--r--Bindings/media/samsung-fimc.txt2
-rw-r--r--Bindings/media/sh_mobile_ceu.txt2
-rw-r--r--Bindings/media/stih-cec.txt2
-rw-r--r--Bindings/media/stih407-c8sectpfe.txt2
-rw-r--r--Bindings/media/sunxi-ir.txt2
-rw-r--r--Bindings/media/tango-ir.txt21
-rw-r--r--Bindings/media/tegra-cec.txt27
-rw-r--r--Bindings/media/video-interfaces.txt34
-rw-r--r--Bindings/memory-controllers/brcm,dpfe-cpu.txt27
-rw-r--r--Bindings/memory-controllers/ti/emif.txt8
-rw-r--r--Bindings/mfd/arizona.txt40
-rw-r--r--Bindings/mfd/aspeed-scu.txt6
-rw-r--r--Bindings/mfd/brcm,iproc-cdru.txt16
-rw-r--r--Bindings/mfd/brcm,iproc-mhb.txt18
-rw-r--r--Bindings/mfd/max77686.txt2
-rw-r--r--Bindings/mfd/max77693.txt6
-rw-r--r--Bindings/mfd/max77802.txt2
-rw-r--r--Bindings/mfd/mc13xxx.txt1
-rw-r--r--Bindings/mfd/mfd.txt2
-rw-r--r--Bindings/mfd/sprd,sc27xx-pmic.txt40
-rw-r--r--Bindings/mfd/sun4i-gpadc.txt4
-rw-r--r--Bindings/mfd/sun6i-prcm.txt2
-rw-r--r--Bindings/mfd/syscon.txt2
-rw-r--r--Bindings/mfd/ti-keystone-devctrl.txt2
-rw-r--r--Bindings/mips/brcm/soc.txt153
-rw-r--r--Bindings/misc/brcm,kona-smc.txt2
-rw-r--r--Bindings/misc/ge-achc.txt26
-rw-r--r--Bindings/mmc/amlogic,meson-mx-sdio.txt54
-rw-r--r--Bindings/mmc/brcm,kona-sdhci.txt2
-rw-r--r--Bindings/mmc/brcm,sdhci-iproc.txt2
-rw-r--r--Bindings/mmc/mmc.txt5
-rw-r--r--Bindings/mmc/mtk-sd.txt18
-rw-r--r--Bindings/mmc/sdhci-fujitsu.txt2
-rw-r--r--Bindings/mmc/sdhci-msm.txt2
-rw-r--r--Bindings/mmc/sdhci-omap.txt16
-rw-r--r--Bindings/mmc/sdhci-st.txt4
-rw-r--r--Bindings/mmc/sunxi-mmc.txt4
-rw-r--r--Bindings/mmc/ti-omap-hsmmc.txt4
-rw-r--r--Bindings/mmc/tmio_mmc.txt70
-rw-r--r--Bindings/mtd/cadence-quadspi.txt7
-rw-r--r--Bindings/mtd/denali-nand.txt2
-rw-r--r--Bindings/mtd/gpmc-nor.txt6
-rw-r--r--Bindings/mtd/jedec,spi-nor.txt1
-rw-r--r--Bindings/mtd/mtk-nand.txt2
-rw-r--r--Bindings/mtd/mtk-quadspi.txt15
-rw-r--r--Bindings/mtd/pxa3xx-nand.txt4
-rw-r--r--Bindings/mtd/sunxi-nand.txt2
-rw-r--r--Bindings/net/allwinner,sun4i-emac.txt2
-rw-r--r--Bindings/net/allwinner,sun4i-mdio.txt4
-rw-r--r--Bindings/net/allwinner,sun7i-a20-gmac.txt2
-rw-r--r--Bindings/net/altera_tse.txt4
-rw-r--r--Bindings/net/bluetooth.txt5
-rw-r--r--Bindings/net/brcm,bcmgenet.txt2
-rw-r--r--Bindings/net/can/m_can.txt2
-rw-r--r--Bindings/net/can/sun4i_can.txt4
-rw-r--r--Bindings/net/dsa/lan9303.txt4
-rw-r--r--Bindings/net/dwmac-sun8i.txt207
-rw-r--r--Bindings/net/fsl-fec.txt13
-rw-r--r--Bindings/net/mdio.txt2
-rw-r--r--Bindings/net/renesas,ravb.txt4
-rw-r--r--Bindings/net/sh_eth.txt14
-rw-r--r--Bindings/net/socfpga-dwmac.txt2
-rw-r--r--Bindings/net/stmmac.txt2
-rw-r--r--Bindings/net/wireless/brcm,bcm43xx-fmac.txt2
-rw-r--r--Bindings/nios2/nios2.txt2
-rw-r--r--Bindings/nvmem/allwinner,sunxi-sid.txt5
-rw-r--r--Bindings/nvmem/amlogic-efuse.txt2
-rw-r--r--Bindings/nvmem/amlogic-meson-mx-efuse.txt22
-rw-r--r--Bindings/nvmem/brcm,ocotp.txt2
-rw-r--r--Bindings/nvmem/imx-ocotp.txt2
-rw-r--r--Bindings/nvmem/nvmem.txt2
-rw-r--r--Bindings/nvmem/qfprom.txt2
-rw-r--r--Bindings/nvmem/rockchip-efuse.txt1
-rw-r--r--Bindings/nvmem/snvs-lpgpr.txt20
-rw-r--r--Bindings/nvmem/uniphier-efuse.txt49
-rw-r--r--Bindings/openrisc/opencores/or1ksim.txt39
-rw-r--r--Bindings/pci/altera-pcie.txt2
-rw-r--r--Bindings/pci/designware-pcie-ecam.txt42
-rw-r--r--Bindings/pci/fsl,imx6q-pcie.txt2
-rw-r--r--Bindings/pci/hisilicon-histb-pcie.txt68
-rw-r--r--Bindings/pci/hisilicon-pcie.txt2
-rw-r--r--Bindings/pci/layerscape-pci.txt1
-rw-r--r--Bindings/pci/nvidia,tegra20-pcie.txt146
-rw-r--r--Bindings/pci/pci-rcar-gen2.txt10
-rw-r--r--Bindings/pci/v3-v360epc-pci.txt75
-rw-r--r--Bindings/phy/brcm,brcmstb-usb-phy.txt43
-rw-r--r--Bindings/phy/brcm,cygnus-pcie-phy.txt2
-rw-r--r--Bindings/phy/brcm-sata-phy.txt11
-rw-r--r--Bindings/phy/mxs-usb-phy.txt2
-rw-r--r--Bindings/phy/rcar-gen2-phy.txt7
-rw-r--r--Bindings/phy/rcar-gen3-phy-usb2.txt2
-rw-r--r--Bindings/phy/sun4i-usb-phy.txt2
-rw-r--r--Bindings/phy/sun9i-usb-phy.txt2
-rw-r--r--Bindings/pinctrl/allwinner,sunxi-pinctrl.txt2
-rw-r--r--Bindings/pinctrl/brcm,cygnus-pinmux.txt2
-rw-r--r--Bindings/pinctrl/cortina,gemini-pinctrl.txt10
-rw-r--r--Bindings/pinctrl/fsl,imx-pinctrl.txt4
-rw-r--r--Bindings/pinctrl/img,tz1090-pdc-pinctrl.txt4
-rw-r--r--Bindings/pinctrl/img,tz1090-pinctrl.txt4
-rw-r--r--Bindings/pinctrl/marvell,armada-37xx-pinctrl.txt4
-rw-r--r--Bindings/pinctrl/nvidia,tegra124-xusb-padctl.txt2
-rw-r--r--Bindings/pinctrl/pinctrl-atlas7.txt4
-rw-r--r--Bindings/pinctrl/pinctrl-bindings.txt4
-rw-r--r--Bindings/pinctrl/pinctrl-mcp23s08.txt (renamed from Bindings/gpio/gpio-mcp23s08.txt)59
-rw-r--r--Bindings/pinctrl/pinctrl-mt65xx.txt2
-rw-r--r--Bindings/pinctrl/pinctrl-sirf.txt2
-rw-r--r--Bindings/pinctrl/pinctrl-st.txt2
-rw-r--r--Bindings/pinctrl/qcom,msm8996-pinctrl.txt2
-rw-r--r--Bindings/pinctrl/qcom,pmic-gpio.txt2
-rw-r--r--Bindings/pinctrl/renesas,rza1-pinctrl.txt6
-rw-r--r--Bindings/pinctrl/rockchip,pinctrl.txt4
-rw-r--r--Bindings/pinctrl/st,stm32-pinctrl.txt22
-rw-r--r--Bindings/power/amlogic,meson-gx-pwrc.txt61
-rw-r--r--Bindings/power/fsl,imx-gpc.txt4
-rw-r--r--Bindings/power/renesas,apmu.txt1
-rw-r--r--Bindings/power/renesas,rcar-sysc.txt1
-rw-r--r--Bindings/power/reset/imx-snvs-poweroff.txt2
-rw-r--r--Bindings/power/reset/keystone-reset.txt4
-rw-r--r--Bindings/power/supply/sbs,sbs-manager.txt66
-rw-r--r--Bindings/power/ti-smartreflex.txt47
-rw-r--r--Bindings/powerpc/fsl/mcu-mpc8349emitx.txt2
-rw-r--r--Bindings/pwm/pwm-sun4i.txt2
-rw-r--r--Bindings/pwm/renesas,pwm-rcar.txt1
-rw-r--r--Bindings/regulator/da9211.txt82
-rw-r--r--Bindings/regulator/max77686.txt2
-rw-r--r--Bindings/regulator/max77802.txt2
-rw-r--r--Bindings/regulator/pfuze100.txt6
-rw-r--r--Bindings/regulator/qcom,spmi-regulator.txt13
-rw-r--r--Bindings/regulator/regulator.txt2
-rw-r--r--Bindings/remoteproc/qcom,q6v5.txt1
-rw-r--r--Bindings/reserved-memory/qcom,rmtfs-mem.txt51
-rw-r--r--Bindings/reset/allwinner,sunxi-clock-reset.txt2
-rw-r--r--Bindings/reset/fsl,imx-src.txt6
-rw-r--r--Bindings/reset/renesas,rst.txt1
-rw-r--r--Bindings/reset/snps,axs10x-reset.txt33
-rw-r--r--Bindings/reset/ti-syscon-reset.txt2
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-rw-r--r--src/arm64/amlogic/meson-gx.dtsi22
-rw-r--r--src/arm64/amlogic/meson-gxbb-nanopi-k2.dts14
-rw-r--r--src/arm64/amlogic/meson-gxbb-nexbox-a95x.dts31
-rw-r--r--src/arm64/amlogic/meson-gxbb-odroidc2.dts15
-rw-r--r--src/arm64/amlogic/meson-gxbb-p200.dts2
-rw-r--r--src/arm64/amlogic/meson-gxbb-p20x.dtsi2
-rw-r--r--src/arm64/amlogic/meson-gxbb-vega-s95.dtsi2
-rw-r--r--src/arm64/amlogic/meson-gxbb.dtsi22
-rw-r--r--src/arm64/amlogic/meson-gxl-s905d-p230.dts2
-rw-r--r--src/arm64/amlogic/meson-gxl-s905x-hwacom-amazetv.dts2
-rw-r--r--src/arm64/amlogic/meson-gxl-s905x-khadas-vim.dts8
-rw-r--r--src/arm64/amlogic/meson-gxl-s905x-libretech-cc.dts27
-rw-r--r--src/arm64/amlogic/meson-gxl-s905x-nexbox-a95x.dts2
-rw-r--r--src/arm64/amlogic/meson-gxl-s905x-p212.dtsi2
-rw-r--r--src/arm64/amlogic/meson-gxl.dtsi32
-rw-r--r--src/arm64/amlogic/meson-gxm-khadas-vim2.dts400
-rw-r--r--src/arm64/amlogic/meson-gxm-nexbox-a1.dts2
-rw-r--r--src/arm64/amlogic/meson-gxm-q200.dts2
-rw-r--r--src/arm64/amlogic/meson-gxm-rbox-pro.dts2
-rw-r--r--src/arm64/amlogic/meson-gxm-vega-s96.dts38
-rw-r--r--src/arm64/apm/apm-shadowcat.dtsi6
-rw-r--r--src/arm64/apm/apm-storm.dtsi4
-rw-r--r--src/arm64/arm/foundation-v8-gicv2.dtsi19
-rw-r--r--src/arm64/arm/foundation-v8-gicv3-psci.dts9
-rw-r--r--src/arm64/arm/foundation-v8-gicv3.dts25
-rw-r--r--src/arm64/arm/foundation-v8-gicv3.dtsi28
-rw-r--r--src/arm64/arm/foundation-v8-psci.dts9
-rw-r--r--src/arm64/arm/foundation-v8-psci.dtsi28
-rw-r--r--src/arm64/arm/foundation-v8-spin-table.dtsi25
-rw-r--r--src/arm64/arm/foundation-v8.dts16
-rw-r--r--src/arm64/arm/foundation-v8.dtsi30
-rw-r--r--src/arm64/arm/rtsm_ve-aemv8a.dts2
-rw-r--r--src/arm64/arm/rtsm_ve-motherboard.dtsi24
-rw-r--r--src/arm64/arm/vexpress-v2f-1xv7-ca53x2.dts2
-rw-r--r--src/arm64/broadcom/northstar2/ns2-xmc.dts2
-rw-r--r--src/arm64/broadcom/northstar2/ns2.dtsi4
-rw-r--r--src/arm64/broadcom/stingray/stingray-clock.dtsi12
-rw-r--r--src/arm64/broadcom/stingray/stingray-fs4.dtsi4
-rw-r--r--src/arm64/broadcom/stingray/stingray-pinctrl.dtsi4
-rw-r--r--src/arm64/broadcom/stingray/stingray-sata.dtsi32
-rw-r--r--src/arm64/broadcom/stingray/stingray.dtsi66
-rw-r--r--src/arm64/cavium/thunder-88xx.dts2
-rw-r--r--src/arm64/cavium/thunder-88xx.dtsi32
-rw-r--r--src/arm64/freescale/fsl-ls1012a-qds.dts33
-rw-r--r--src/arm64/freescale/fsl-ls1012a.dtsi51
-rw-r--r--src/arm64/freescale/fsl-ls1043a.dtsi11
-rw-r--r--src/arm64/freescale/fsl-ls1046a.dtsi86
-rw-r--r--src/arm64/freescale/fsl-ls1088a.dtsi88
-rw-r--r--src/arm64/freescale/fsl-ls2088a.dtsi4
-rw-r--r--src/arm64/freescale/fsl-ls208xa.dtsi7
-rw-r--r--src/arm64/hisilicon/hi3660-hikey960.dts319
-rw-r--r--src/arm64/hisilicon/hi3660.dtsi7
-rw-r--r--src/arm64/hisilicon/hi3798cv200-poplar.dts20
-rw-r--r--src/arm64/hisilicon/hi6220-coresight.dtsi381
-rw-r--r--src/arm64/hisilicon/hi6220.dtsi2
-rw-r--r--src/arm64/hisilicon/hip05-d02.dts2
-rw-r--r--src/arm64/hisilicon/hip06-d03.dts2
-rw-r--r--src/arm64/marvell/armada-3720-db.dts20
-rw-r--r--src/arm64/marvell/armada-3720-espressobin.dts12
-rw-r--r--src/arm64/marvell/armada-37xx.dtsi22
-rw-r--r--src/arm64/marvell/armada-7040-db.dts57
-rw-r--r--src/arm64/marvell/armada-70x0.dtsi14
-rw-r--r--src/arm64/marvell/armada-8040-db.dts59
-rw-r--r--src/arm64/marvell/armada-8040-mcbin.dts13
-rw-r--r--src/arm64/marvell/armada-8080-db.dts2
-rw-r--r--src/arm64/marvell/armada-ap806-dual.dtsi4
-rw-r--r--src/arm64/marvell/armada-ap806-quad.dtsi4
-rw-r--r--src/arm64/marvell/armada-ap806.dtsi11
-rw-r--r--src/arm64/marvell/armada-ap810-ap0-octa-core.dtsi4
-rw-r--r--src/arm64/marvell/armada-cp110-master.dtsi72
-rw-r--r--src/arm64/marvell/armada-cp110-slave.dtsi67
-rw-r--r--src/arm64/marvell/berlin4ct.dtsi6
-rw-r--r--src/arm64/mediatek/mt2712e.dtsi25
-rw-r--r--src/arm64/mediatek/mt8173.dtsi12
-rw-r--r--src/arm64/nvidia/tegra186-p2771-0000.dts24
-rw-r--r--src/arm64/nvidia/tegra186.dtsi214
-rw-r--r--src/arm64/qcom/apq8016-sbc.dtsi177
-rw-r--r--src/arm64/qcom/apq8096-db820c.dtsi32
-rw-r--r--src/arm64/qcom/msm8916.dtsi13
-rw-r--r--src/arm64/qcom/msm8996-pins.dtsi195
-rw-r--r--src/arm64/qcom/msm8996.dtsi191
-rw-r--r--src/arm64/realtek/rtd1295-mele-v9.dts31
-rw-r--r--src/arm64/realtek/rtd1295-probox2-ava.dts31
-rw-r--r--src/arm64/realtek/rtd1295-zidoo-x9s.dts6
-rw-r--r--src/arm64/realtek/rtd1295.dtsi62
-rw-r--r--src/arm64/realtek/rtd129x.dtsi72
-rw-r--r--src/arm64/renesas/r8a7795-es1-h3ulcb-kf.dts19
-rw-r--r--src/arm64/renesas/r8a7795-es1.dtsi2
-rw-r--r--src/arm64/renesas/r8a7795-h3ulcb-kf.dts19
-rw-r--r--src/arm64/renesas/r8a7795.dtsi31
-rw-r--r--src/arm64/renesas/r8a7796-m3ulcb-kf.dts19
-rw-r--r--src/arm64/renesas/r8a7796.dtsi53
-rw-r--r--src/arm64/renesas/r8a77970-eagle.dts57
-rw-r--r--src/arm64/renesas/r8a77970.dtsi382
-rw-r--r--src/arm64/renesas/r8a77995-draak.dts78
-rw-r--r--src/arm64/renesas/r8a77995.dtsi267
-rw-r--r--src/arm64/renesas/salvator-common.dtsi17
-rw-r--r--src/arm64/renesas/ulcb-kf.dtsi169
-rw-r--r--src/arm64/renesas/ulcb.dtsi10
-rw-r--r--src/arm64/rockchip/rk3328-evb.dts72
-rw-r--r--src/arm64/rockchip/rk3328-rock64.dts2
-rw-r--r--src/arm64/rockchip/rk3328.dtsi2
-rw-r--r--src/arm64/rockchip/rk3368.dtsi16
-rw-r--r--src/arm64/rockchip/rk3399-firefly.dts27
-rw-r--r--src/arm64/rockchip/rk3399-gru-kevin.dts4
-rw-r--r--src/arm64/rockchip/rk3399-gru.dtsi3
-rw-r--r--src/arm64/rockchip/rk3399-puma.dtsi11
-rw-r--r--src/arm64/rockchip/rk3399.dtsi19
-rw-r--r--src/arm64/socionext/uniphier-ld11-ref.dts10
-rw-r--r--src/arm64/socionext/uniphier-ld11.dtsi65
-rw-r--r--src/arm64/socionext/uniphier-ld20-ref.dts10
-rw-r--r--src/arm64/socionext/uniphier-ld20.dtsi105
-rw-r--r--src/arm64/socionext/uniphier-pxs3-ref.dts6
-rw-r--r--src/arm64/socionext/uniphier-pxs3.dtsi58
-rw-r--r--src/mips/brcm/bcm3368.dtsi2
-rw-r--r--src/mips/brcm/bcm63268-comtrend-vr-3032u.dts2
-rw-r--r--src/mips/brcm/bcm63268.dtsi2
-rw-r--r--src/mips/brcm/bcm6328.dtsi2
-rw-r--r--src/mips/brcm/bcm6358-neufbox4-sercomm.dts2
-rw-r--r--src/mips/brcm/bcm6358.dtsi2
-rw-r--r--src/mips/brcm/bcm6362.dtsi2
-rw-r--r--src/mips/brcm/bcm6368.dtsi2
-rw-r--r--src/mips/img/pistachio.dtsi1
-rw-r--r--src/mips/ingenic/jz4780.dtsi5
-rw-r--r--src/mips/ralink/rt3052_eval.dts2
-rw-r--r--src/mips/xilfpga/nexys4ddr.dts8
-rw-r--r--src/openrisc/or1ksim.dts7
-rw-r--r--src/openrisc/simple_smp.dts63
-rw-r--r--src/powerpc/acadia.dts2
1088 files changed, 33974 insertions, 16606 deletions
diff --git a/Bindings/arm/actions.txt b/Bindings/arm/actions.txt
index 3bc7ea575564..ced764a8549e 100644
--- a/Bindings/arm/actions.txt
+++ b/Bindings/arm/actions.txt
@@ -21,6 +21,7 @@ Boards:
Root node property compatible must contain, depending on board:
+ - Cubietech CubieBoard6: "cubietech,cubieboard6"
- LeMaker Guitar Base Board rev. B: "lemaker,guitar-bb-rev-b", "lemaker,guitar"
diff --git a/Bindings/arm/amlogic.txt b/Bindings/arm/amlogic.txt
index 4e4bc0bae597..f747f47922c5 100644
--- a/Bindings/arm/amlogic.txt
+++ b/Bindings/arm/amlogic.txt
@@ -41,6 +41,10 @@ Boards with the Amlogic Meson GXM S912 SoC shall have the following properties:
Required root node property:
compatible: "amlogic,s912", "amlogic,meson-gxm";
+Boards with the Amlogic Meson AXG A113D SoC shall have the following properties:
+ Required root node property:
+ compatible: "amlogic,a113d", "amlogic,meson-axg";
+
Board compatible values (alphabetically, grouped by SoC):
- "geniatech,atv1200" (Meson6)
@@ -71,8 +75,12 @@ Board compatible values (alphabetically, grouped by SoC):
- "amlogic,q200" (Meson gxm s912)
- "amlogic,q201" (Meson gxm s912)
+ - "khadas,vim2" (Meson gxm s912)
- "kingnovel,r-box-pro" (Meson gxm S912)
- "nexbox,a1" (Meson gxm s912)
+ - "tronsmart,vega-s96" (Meson gxm s912)
+
+ - "amlogic,s400" (Meson axg a113d)
Amlogic Meson Firmware registers Interface
------------------------------------------
diff --git a/Bindings/arm/amlogic/analog-top.txt b/Bindings/arm/amlogic/analog-top.txt
new file mode 100644
index 000000000000..101dc21014ec
--- /dev/null
+++ b/Bindings/arm/amlogic/analog-top.txt
@@ -0,0 +1,20 @@
+Amlogic Meson8 and Meson8b "analog top" registers:
+--------------------------------------------------
+
+The analog top registers contain information about the so-called
+"metal revision" (which encodes the "minor version") of the SoC.
+
+Required properties:
+- reg: the register range of the analog top registers
+- compatible: depending on the SoC this should be one of:
+ - "amlogic,meson8-analog-top"
+ - "amlogic,meson8b-analog-top"
+ along with "syscon"
+
+
+Example:
+
+ analog_top: analog-top@81a8 {
+ compatible = "amlogic,meson8-analog-top", "syscon";
+ reg = <0x81a8 0x14>;
+ };
diff --git a/Bindings/arm/amlogic/assist.txt b/Bindings/arm/amlogic/assist.txt
new file mode 100644
index 000000000000..7656812b67b9
--- /dev/null
+++ b/Bindings/arm/amlogic/assist.txt
@@ -0,0 +1,17 @@
+Amlogic Meson6/Meson8/Meson8b assist registers:
+-----------------------------------------------
+
+The assist registers contain basic information about the SoC,
+for example the encoded SoC part number.
+
+Required properties:
+- reg: the register range of the assist registers
+- compatible: should be "amlogic,meson-mx-assist" along with "syscon"
+
+
+Example:
+
+ assist: assist@7c00 {
+ compatible = "amlogic,meson-mx-assist", "syscon";
+ reg = <0x7c00 0x200>;
+ };
diff --git a/Bindings/arm/amlogic/bootrom.txt b/Bindings/arm/amlogic/bootrom.txt
new file mode 100644
index 000000000000..407e27f230ab
--- /dev/null
+++ b/Bindings/arm/amlogic/bootrom.txt
@@ -0,0 +1,17 @@
+Amlogic Meson6/Meson8/Meson8b bootrom:
+--------------------------------------
+
+The bootrom register area can be used to access SoC specific
+information, such as the "misc version".
+
+Required properties:
+- reg: the register range of the bootrom registers
+- compatible: should be "amlogic,meson-mx-bootrom" along with "syscon"
+
+
+Example:
+
+ bootrom: bootrom@d9040000 {
+ compatible = "amlogic,meson-mx-bootrom", "syscon";
+ reg = <0xd9040000 0x10000>;
+ };
diff --git a/Bindings/arm/amlogic/pmu.txt b/Bindings/arm/amlogic/pmu.txt
new file mode 100644
index 000000000000..72f8d08198b6
--- /dev/null
+++ b/Bindings/arm/amlogic/pmu.txt
@@ -0,0 +1,18 @@
+Amlogic Meson8 and Meson8b power-management-unit:
+-------------------------------------------------
+
+The pmu is used to turn off and on different power domains of the SoCs
+This includes the power to the CPU cores.
+
+Required node properties:
+- compatible value : depending on the SoC this should be one of:
+ "amlogic,meson8-pmu"
+ "amlogic,meson8b-pmu"
+- reg : physical base address and the size of the registers window
+
+Example:
+
+ pmu@c81000e4 {
+ compatible = "amlogic,meson8b-pmu", "syscon";
+ reg = <0xc81000e0 0x18>;
+ };
diff --git a/Bindings/arm/amlogic/smp-sram.txt b/Bindings/arm/amlogic/smp-sram.txt
new file mode 100644
index 000000000000..3473ddaadfac
--- /dev/null
+++ b/Bindings/arm/amlogic/smp-sram.txt
@@ -0,0 +1,32 @@
+Amlogic Meson8 and Meson8b SRAM for smp bringup:
+------------------------------------------------
+
+Amlogic's SMP-capable SoCs use part of the sram for the bringup of the cores.
+Once the core gets powered up it executes the code that is residing at a
+specific location.
+
+Therefore a reserved section sub-node has to be added to the mmio-sram
+declaration.
+
+Required sub-node properties:
+- compatible : depending on the SoC this should be one of:
+ "amlogic,meson8-smp-sram"
+ "amlogic,meson8b-smp-sram"
+
+The rest of the properties should follow the generic mmio-sram discription
+found in ../../misc/sram.txt
+
+Example:
+
+ sram: sram@d9000000 {
+ compatible = "mmio-sram";
+ reg = <0xd9000000 0x20000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xd9000000 0x20000>;
+
+ smp-sram@1ff80 {
+ compatible = "amlogic,meson8b-smp-sram";
+ reg = <0x1ff80 0x8>;
+ };
+ };
diff --git a/Bindings/arm/bcm/brcm,brcmstb.txt b/Bindings/arm/bcm/brcm,brcmstb.txt
index 0d0c1ae81bed..790e6b0b8306 100644
--- a/Bindings/arm/bcm/brcm,brcmstb.txt
+++ b/Bindings/arm/bcm/brcm,brcmstb.txt
@@ -164,6 +164,8 @@ Control registers for this memory controller's DDR PHY.
Required properties:
- compatible : should contain one of these
+ "brcm,brcmstb-ddr-phy-v71.1"
+ "brcm,brcmstb-ddr-phy-v72.0"
"brcm,brcmstb-ddr-phy-v225.1"
"brcm,brcmstb-ddr-phy-v240.1"
"brcm,brcmstb-ddr-phy-v240.2"
@@ -184,7 +186,9 @@ Sequencer DRAM parameters and control registers. Used for Self-Refresh
Power-Down (SRPD), among other things.
Required properties:
-- compatible : should contain "brcm,brcmstb-memc-ddr"
+- compatible : should contain one of these
+ "brcm,brcmstb-memc-ddr-rev-b.2.2"
+ "brcm,brcmstb-memc-ddr"
- reg : the MEMC DDR register range
Example:
diff --git a/Bindings/arm/bcm/brcm,hr2.txt b/Bindings/arm/bcm/brcm,hr2.txt
new file mode 100644
index 000000000000..a124c7fc4dcd
--- /dev/null
+++ b/Bindings/arm/bcm/brcm,hr2.txt
@@ -0,0 +1,14 @@
+Broadcom Hurricane 2 device tree bindings
+---------------------------------------
+
+Broadcom Hurricane 2 family of SoCs are used for switching control. These SoCs
+are based on Broadcom's iProc SoC architecture and feature a single core Cortex
+A9 ARM CPUs, DDR2/DDR3 memory, PCIe GEN-2, USB 2.0 and USB 3.0, serial and NAND
+flash and a PCIe attached integrated switching engine.
+
+Boards with Hurricane SoCs shall have the following properties:
+
+Required root node property:
+
+BCM53342
+compatible = "brcm,bcm53342", "brcm,hr2";
diff --git a/Bindings/arm/ccn.txt b/Bindings/arm/ccn.txt
index 29801456c9ee..43b5a71a5a9d 100644
--- a/Bindings/arm/ccn.txt
+++ b/Bindings/arm/ccn.txt
@@ -15,7 +15,7 @@ Required properties:
Example:
- ccn@0x2000000000 {
+ ccn@2000000000 {
compatible = "arm,ccn-504";
reg = <0x20 0x00000000 0 0x1000000>;
interrupts = <0 181 4>;
diff --git a/Bindings/arm/cpus.txt b/Bindings/arm/cpus.txt
index b92f12bd5244..a0009b72e9be 100644
--- a/Bindings/arm/cpus.txt
+++ b/Bindings/arm/cpus.txt
@@ -197,6 +197,8 @@ described below.
"actions,s500-smp"
"allwinner,sun6i-a31"
"allwinner,sun8i-a23"
+ "amlogic,meson8-smp"
+ "amlogic,meson8b-smp"
"arm,realview-smp"
"brcm,bcm11351-cpu-method"
"brcm,bcm23550"
diff --git a/Bindings/arm/mediatek/mediatek,apmixedsys.txt b/Bindings/arm/mediatek/mediatek,apmixedsys.txt
index cd977db7630c..b404d592ce58 100644
--- a/Bindings/arm/mediatek/mediatek,apmixedsys.txt
+++ b/Bindings/arm/mediatek/mediatek,apmixedsys.txt
@@ -7,7 +7,9 @@ Required Properties:
- compatible: Should be one of:
- "mediatek,mt2701-apmixedsys"
+ - "mediatek,mt2712-apmixedsys", "syscon"
- "mediatek,mt6797-apmixedsys"
+ - "mediatek,mt7622-apmixedsys"
- "mediatek,mt8135-apmixedsys"
- "mediatek,mt8173-apmixedsys"
- #clock-cells: Must be 1
diff --git a/Bindings/arm/mediatek/mediatek,audsys.txt b/Bindings/arm/mediatek/mediatek,audsys.txt
new file mode 100644
index 000000000000..9b8f578d5e19
--- /dev/null
+++ b/Bindings/arm/mediatek/mediatek,audsys.txt
@@ -0,0 +1,22 @@
+MediaTek AUDSYS controller
+============================
+
+The MediaTek AUDSYS controller provides various clocks to the system.
+
+Required Properties:
+
+- compatible: Should be one of:
+ - "mediatek,mt7622-audsys", "syscon"
+- #clock-cells: Must be 1
+
+The AUDSYS controller uses the common clk binding from
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
+
+Example:
+
+audsys: audsys@11220000 {
+ compatible = "mediatek,mt7622-audsys", "syscon";
+ reg = <0 0x11220000 0 0x1000>;
+ #clock-cells = <1>;
+};
diff --git a/Bindings/arm/mediatek/mediatek,bdpsys.txt b/Bindings/arm/mediatek/mediatek,bdpsys.txt
index 4137196dd686..4010e37c53a0 100644
--- a/Bindings/arm/mediatek/mediatek,bdpsys.txt
+++ b/Bindings/arm/mediatek/mediatek,bdpsys.txt
@@ -7,6 +7,7 @@ Required Properties:
- compatible: Should be:
- "mediatek,mt2701-bdpsys", "syscon"
+ - "mediatek,mt2712-bdpsys", "syscon"
- #clock-cells: Must be 1
The bdpsys controller uses the common clk binding from
diff --git a/Bindings/arm/mediatek/mediatek,ethsys.txt b/Bindings/arm/mediatek/mediatek,ethsys.txt
index 768f3a5bc055..7aa3fa167668 100644
--- a/Bindings/arm/mediatek/mediatek,ethsys.txt
+++ b/Bindings/arm/mediatek/mediatek,ethsys.txt
@@ -7,6 +7,7 @@ Required Properties:
- compatible: Should be:
- "mediatek,mt2701-ethsys", "syscon"
+ - "mediatek,mt7622-ethsys", "syscon"
- #clock-cells: Must be 1
The ethsys controller uses the common clk binding from
diff --git a/Bindings/arm/mediatek/mediatek,hifsys.txt b/Bindings/arm/mediatek/mediatek,hifsys.txt
index beed7b594cea..f5629d64cef2 100644
--- a/Bindings/arm/mediatek/mediatek,hifsys.txt
+++ b/Bindings/arm/mediatek/mediatek,hifsys.txt
@@ -8,6 +8,7 @@ Required Properties:
- compatible: Should be:
- "mediatek,mt2701-hifsys", "syscon"
+ - "mediatek,mt7622-hifsys", "syscon"
- #clock-cells: Must be 1
The hifsys controller uses the common clk binding from
diff --git a/Bindings/arm/mediatek/mediatek,imgsys.txt b/Bindings/arm/mediatek/mediatek,imgsys.txt
index 047b11ae5f45..868bd51a98be 100644
--- a/Bindings/arm/mediatek/mediatek,imgsys.txt
+++ b/Bindings/arm/mediatek/mediatek,imgsys.txt
@@ -7,6 +7,7 @@ Required Properties:
- compatible: Should be one of:
- "mediatek,mt2701-imgsys", "syscon"
+ - "mediatek,mt2712-imgsys", "syscon"
- "mediatek,mt6797-imgsys", "syscon"
- "mediatek,mt8173-imgsys", "syscon"
- #clock-cells: Must be 1
diff --git a/Bindings/arm/mediatek/mediatek,infracfg.txt b/Bindings/arm/mediatek/mediatek,infracfg.txt
index 58d58e2006b8..566f153f9f83 100644
--- a/Bindings/arm/mediatek/mediatek,infracfg.txt
+++ b/Bindings/arm/mediatek/mediatek,infracfg.txt
@@ -8,7 +8,9 @@ Required Properties:
- compatible: Should be one of:
- "mediatek,mt2701-infracfg", "syscon"
+ - "mediatek,mt2712-infracfg", "syscon"
- "mediatek,mt6797-infracfg", "syscon"
+ - "mediatek,mt7622-infracfg", "syscon"
- "mediatek,mt8135-infracfg", "syscon"
- "mediatek,mt8173-infracfg", "syscon"
- #clock-cells: Must be 1
diff --git a/Bindings/arm/mediatek/mediatek,jpgdecsys.txt b/Bindings/arm/mediatek/mediatek,jpgdecsys.txt
new file mode 100644
index 000000000000..2df799cd06a7
--- /dev/null
+++ b/Bindings/arm/mediatek/mediatek,jpgdecsys.txt
@@ -0,0 +1,22 @@
+Mediatek jpgdecsys controller
+============================
+
+The Mediatek jpgdecsys controller provides various clocks to the system.
+
+Required Properties:
+
+- compatible: Should be:
+ - "mediatek,mt2712-jpgdecsys", "syscon"
+- #clock-cells: Must be 1
+
+The jpgdecsys controller uses the common clk binding from
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
+
+Example:
+
+jpgdecsys: syscon@19000000 {
+ compatible = "mediatek,mt2712-jpgdecsys", "syscon";
+ reg = <0 0x19000000 0 0x1000>;
+ #clock-cells = <1>;
+};
diff --git a/Bindings/arm/mediatek/mediatek,mcucfg.txt b/Bindings/arm/mediatek/mediatek,mcucfg.txt
new file mode 100644
index 000000000000..b8fb03f3613e
--- /dev/null
+++ b/Bindings/arm/mediatek/mediatek,mcucfg.txt
@@ -0,0 +1,22 @@
+Mediatek mcucfg controller
+============================
+
+The Mediatek mcucfg controller provides various clocks to the system.
+
+Required Properties:
+
+- compatible: Should be one of:
+ - "mediatek,mt2712-mcucfg", "syscon"
+- #clock-cells: Must be 1
+
+The mcucfg controller uses the common clk binding from
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
+
+Example:
+
+mcucfg: syscon@10220000 {
+ compatible = "mediatek,mt2712-mcucfg", "syscon";
+ reg = <0 0x10220000 0 0x1000>;
+ #clock-cells = <1>;
+};
diff --git a/Bindings/arm/mediatek/mediatek,mfgcfg.txt b/Bindings/arm/mediatek/mediatek,mfgcfg.txt
new file mode 100644
index 000000000000..859e67b416d5
--- /dev/null
+++ b/Bindings/arm/mediatek/mediatek,mfgcfg.txt
@@ -0,0 +1,22 @@
+Mediatek mfgcfg controller
+============================
+
+The Mediatek mfgcfg controller provides various clocks to the system.
+
+Required Properties:
+
+- compatible: Should be one of:
+ - "mediatek,mt2712-mfgcfg", "syscon"
+- #clock-cells: Must be 1
+
+The mfgcfg controller uses the common clk binding from
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
+
+Example:
+
+mfgcfg: syscon@13000000 {
+ compatible = "mediatek,mt2712-mfgcfg", "syscon";
+ reg = <0 0x13000000 0 0x1000>;
+ #clock-cells = <1>;
+};
diff --git a/Bindings/arm/mediatek/mediatek,mmsys.txt b/Bindings/arm/mediatek/mediatek,mmsys.txt
index 70529e0b58e9..4eb8bbe15c01 100644
--- a/Bindings/arm/mediatek/mediatek,mmsys.txt
+++ b/Bindings/arm/mediatek/mediatek,mmsys.txt
@@ -7,6 +7,7 @@ Required Properties:
- compatible: Should be one of:
- "mediatek,mt2701-mmsys", "syscon"
+ - "mediatek,mt2712-mmsys", "syscon"
- "mediatek,mt6797-mmsys", "syscon"
- "mediatek,mt8173-mmsys", "syscon"
- #clock-cells: Must be 1
diff --git a/Bindings/arm/mediatek/mediatek,pciesys.txt b/Bindings/arm/mediatek/mediatek,pciesys.txt
new file mode 100644
index 000000000000..d5d5f1227665
--- /dev/null
+++ b/Bindings/arm/mediatek/mediatek,pciesys.txt
@@ -0,0 +1,22 @@
+MediaTek PCIESYS controller
+============================
+
+The MediaTek PCIESYS controller provides various clocks to the system.
+
+Required Properties:
+
+- compatible: Should be:
+ - "mediatek,mt7622-pciesys", "syscon"
+- #clock-cells: Must be 1
+
+The PCIESYS controller uses the common clk binding from
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
+
+Example:
+
+pciesys: pciesys@1a100800 {
+ compatible = "mediatek,mt7622-pciesys", "syscon";
+ reg = <0 0x1a100800 0 0x1000>;
+ #clock-cells = <1>;
+};
diff --git a/Bindings/arm/mediatek/mediatek,pericfg.txt b/Bindings/arm/mediatek/mediatek,pericfg.txt
index e494366782aa..fb58ca8c2770 100644
--- a/Bindings/arm/mediatek/mediatek,pericfg.txt
+++ b/Bindings/arm/mediatek/mediatek,pericfg.txt
@@ -8,6 +8,8 @@ Required Properties:
- compatible: Should be one of:
- "mediatek,mt2701-pericfg", "syscon"
+ - "mediatek,mt2712-pericfg", "syscon"
+ - "mediatek,mt7622-pericfg", "syscon"
- "mediatek,mt8135-pericfg", "syscon"
- "mediatek,mt8173-pericfg", "syscon"
- #clock-cells: Must be 1
diff --git a/Bindings/arm/mediatek/mediatek,sgmiisys.txt b/Bindings/arm/mediatek/mediatek,sgmiisys.txt
new file mode 100644
index 000000000000..d113b8e741f3
--- /dev/null
+++ b/Bindings/arm/mediatek/mediatek,sgmiisys.txt
@@ -0,0 +1,22 @@
+MediaTek SGMIISYS controller
+============================
+
+The MediaTek SGMIISYS controller provides various clocks to the system.
+
+Required Properties:
+
+- compatible: Should be:
+ - "mediatek,mt7622-sgmiisys", "syscon"
+- #clock-cells: Must be 1
+
+The SGMIISYS controller uses the common clk binding from
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
+
+Example:
+
+sgmiisys: sgmiisys@1b128000 {
+ compatible = "mediatek,mt7622-sgmiisys", "syscon";
+ reg = <0 0x1b128000 0 0x1000>;
+ #clock-cells = <1>;
+};
diff --git a/Bindings/arm/mediatek/mediatek,ssusbsys.txt b/Bindings/arm/mediatek/mediatek,ssusbsys.txt
new file mode 100644
index 000000000000..00760019da00
--- /dev/null
+++ b/Bindings/arm/mediatek/mediatek,ssusbsys.txt
@@ -0,0 +1,22 @@
+MediaTek SSUSBSYS controller
+============================
+
+The MediaTek SSUSBSYS controller provides various clocks to the system.
+
+Required Properties:
+
+- compatible: Should be:
+ - "mediatek,mt7622-ssusbsys", "syscon"
+- #clock-cells: Must be 1
+
+The SSUSBSYS controller uses the common clk binding from
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
+
+Example:
+
+ssusbsys: ssusbsys@1a000000 {
+ compatible = "mediatek,mt7622-ssusbsys", "syscon";
+ reg = <0 0x1a000000 0 0x1000>;
+ #clock-cells = <1>;
+};
diff --git a/Bindings/arm/mediatek/mediatek,topckgen.txt b/Bindings/arm/mediatek/mediatek,topckgen.txt
index ec93ecbb9f3c..24014a7e2332 100644
--- a/Bindings/arm/mediatek/mediatek,topckgen.txt
+++ b/Bindings/arm/mediatek/mediatek,topckgen.txt
@@ -7,7 +7,9 @@ Required Properties:
- compatible: Should be one of:
- "mediatek,mt2701-topckgen"
+ - "mediatek,mt2712-topckgen", "syscon"
- "mediatek,mt6797-topckgen"
+ - "mediatek,mt7622-topckgen"
- "mediatek,mt8135-topckgen"
- "mediatek,mt8173-topckgen"
- #clock-cells: Must be 1
diff --git a/Bindings/arm/mediatek/mediatek,vdecsys.txt b/Bindings/arm/mediatek/mediatek,vdecsys.txt
index d150104f928a..ea40d05089f8 100644
--- a/Bindings/arm/mediatek/mediatek,vdecsys.txt
+++ b/Bindings/arm/mediatek/mediatek,vdecsys.txt
@@ -7,6 +7,7 @@ Required Properties:
- compatible: Should be one of:
- "mediatek,mt2701-vdecsys", "syscon"
+ - "mediatek,mt2712-vdecsys", "syscon"
- "mediatek,mt6797-vdecsys", "syscon"
- "mediatek,mt8173-vdecsys", "syscon"
- #clock-cells: Must be 1
diff --git a/Bindings/arm/mediatek/mediatek,vencsys.txt b/Bindings/arm/mediatek/mediatek,vencsys.txt
index 8a93be643647..851545357e94 100644
--- a/Bindings/arm/mediatek/mediatek,vencsys.txt
+++ b/Bindings/arm/mediatek/mediatek,vencsys.txt
@@ -6,6 +6,7 @@ The Mediatek vencsys controller provides various clocks to the system.
Required Properties:
- compatible: Should be one of:
+ - "mediatek,mt2712-vencsys", "syscon"
- "mediatek,mt6797-vencsys", "syscon"
- "mediatek,mt8173-vencsys", "syscon"
- #clock-cells: Must be 1
diff --git a/Bindings/arm/omap/crossbar.txt b/Bindings/arm/omap/crossbar.txt
index bb5727ae004a..ecb360ed0e33 100644
--- a/Bindings/arm/omap/crossbar.txt
+++ b/Bindings/arm/omap/crossbar.txt
@@ -49,7 +49,7 @@ An interrupt consumer on an SoC using crossbar will use:
interrupts = <GIC_SPI request_number interrupt_level>
Example:
- device_x@0x4a023000 {
+ device_x@4a023000 {
/* Crossbar 8 used */
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
...
diff --git a/Bindings/arm/omap/ctrl.txt b/Bindings/arm/omap/ctrl.txt
index 3a4e5901ce31..ce8dabf8c0f9 100644
--- a/Bindings/arm/omap/ctrl.txt
+++ b/Bindings/arm/omap/ctrl.txt
@@ -21,6 +21,8 @@ Required properties:
"ti,omap3-scm"
"ti,omap4-scm-core"
"ti,omap4-scm-padconf-core"
+ "ti,omap4-scm-wkup"
+ "ti,omap4-scm-padconf-wkup"
"ti,omap5-scm-core"
"ti,omap5-scm-padconf-core"
"ti,dra7-scm-core"
diff --git a/Bindings/arm/realtek.txt b/Bindings/arm/realtek.txt
index 13d755787b4f..95839e19ae92 100644
--- a/Bindings/arm/realtek.txt
+++ b/Bindings/arm/realtek.txt
@@ -12,6 +12,8 @@ Required root node properties:
Root node property compatible must contain, depending on board:
+ - MeLE V9: "mele,v9"
+ - ProBox2 AVA: "probox2,ava"
- Zidoo X9S: "zidoo,x9s"
diff --git a/Bindings/arm/rockchip.txt b/Bindings/arm/rockchip.txt
index b003148e2945..326d24bca1a9 100644
--- a/Bindings/arm/rockchip.txt
+++ b/Bindings/arm/rockchip.txt
@@ -1,5 +1,9 @@
Rockchip platforms device tree bindings
---------------------------------------
+- Amarula Vyasa RK3288 board
+ Required root node properties:
+ - compatible = "amarula,vyasa-rk3288", "rockchip,rk3288";
+
- Asus Tinker board
Required root node properties:
- compatible = "asus,rk3288-tinker", "rockchip,rk3288";
diff --git a/Bindings/arm/samsung/pmu.txt b/Bindings/arm/samsung/pmu.txt
index bf5fc59a6938..779f5614bcee 100644
--- a/Bindings/arm/samsung/pmu.txt
+++ b/Bindings/arm/samsung/pmu.txt
@@ -4,7 +4,6 @@ Properties:
- compatible : should contain two values. First value must be one from following list:
- "samsung,exynos3250-pmu" - for Exynos3250 SoC,
- "samsung,exynos4210-pmu" - for Exynos4210 SoC,
- - "samsung,exynos4212-pmu" - for Exynos4212 SoC,
- "samsung,exynos4412-pmu" - for Exynos4412 SoC,
- "samsung,exynos5250-pmu" - for Exynos5250 SoC,
- "samsung,exynos5260-pmu" - for Exynos5260 SoC.
@@ -62,7 +61,7 @@ pmu_system_controller: system-controller@10040000 {
Example of clock consumer :
-usb3503: usb3503@08 {
+usb3503: usb3503@8 {
/* ... */
clock-names = "refclk";
clocks = <&pmu_system_controller 0>;
diff --git a/Bindings/arm/samsung/samsung-boards.txt b/Bindings/arm/samsung/samsung-boards.txt
index 3c551894f621..e13459618581 100644
--- a/Bindings/arm/samsung/samsung-boards.txt
+++ b/Bindings/arm/samsung/samsung-boards.txt
@@ -57,6 +57,7 @@ Required root node properties:
- "hardkernel,odroid-xu3-lite" - for Exynos5422-based Hardkernel
Odroid XU3 Lite board.
- "hardkernel,odroid-xu4" - for Exynos5422-based Hardkernel Odroid XU4.
+ - "hardkernel,odroid-hc1" - for Exynos5422-based Hardkernel Odroid HC1.
* Insignal
- "insignal,arndale" - for Exynos5250-based Insignal Arndale board.
@@ -71,7 +72,7 @@ Optional nodes:
- compatible: only "samsung,secure-firmware" is currently supported
- reg: address of non-secure SYSRAM used for communication with firmware
- firmware@0203F000 {
+ firmware@203F000 {
compatible = "samsung,secure-firmware";
reg = <0x0203F000 0x1000>;
};
diff --git a/Bindings/arm/shmobile.txt b/Bindings/arm/shmobile.txt
index ae75cb3b1331..020d758fc0c5 100644
--- a/Bindings/arm/shmobile.txt
+++ b/Bindings/arm/shmobile.txt
@@ -39,6 +39,8 @@ SoCs:
compatible = "renesas,r8a7795"
- R-Car M3-W (R8A77960)
compatible = "renesas,r8a7796"
+ - R-Car V3M (R8A77970)
+ compatible = "renesas,r8a77970"
- R-Car D3 (R8A77995)
compatible = "renesas,r8a77995"
@@ -57,6 +59,8 @@ Boards:
compatible = "renesas,bockw", "renesas,r8a7778"
- Draak (RTP0RC77995SEB0010S)
compatible = "renesas,draak", "renesas,r8a77995"
+ - Eagle (RTP0RC77970SEB0010S)
+ compatible = "renesas,eagle", "renesas,r8a77970"
- Genmai (RTK772100BC00000BR)
compatible = "renesas,genmai", "renesas,r7s72100"
- GR-Peach (X28A-M01-E/F)
@@ -65,7 +69,7 @@ Boards:
compatible = "renesas,gose", "renesas,r8a7793"
- H3ULCB (R-Car Starter Kit Premier, RTP0RC7795SKBX0010SA00 (H3 ES1.1))
H3ULCB (R-Car Starter Kit Premier, RTP0RC77951SKBX010SA00 (H3 ES2.0))
- compatible = "renesas,h3ulcb", "renesas,r8a7795";
+ compatible = "renesas,h3ulcb", "renesas,r8a7795"
- Henninger
compatible = "renesas,henninger", "renesas,r8a7791"
- iWave Systems RZ/G1E SODIMM SOM Development Platform (iW-RainboW-G22D)
@@ -76,6 +80,8 @@ Boards:
compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743"
- iWave Systems RZ/G1M Qseven System On Module (iW-RainboW-G20M-Qseven)
compatible = "iwave,g20m", "renesas,r8a7743"
+ - Kingfisher (SBEV-RCAR-KF-M03)
+ compatible = "shimafuji,kingfisher"
- Koelsch (RTP0RC7791SEB00010S)
compatible = "renesas,koelsch", "renesas,r8a7791"
- Kyoto Microcomputer Co. KZM-A9-Dual
@@ -85,7 +91,7 @@ Boards:
- Lager (RTP0RC7790SEB00010S)
compatible = "renesas,lager", "renesas,r8a7790"
- M3ULCB (R-Car Starter Kit Pro, RTP0RC7796SKBX0010SA09 (M3 ES1.0))
- compatible = "renesas,m3ulcb", "renesas,r8a7796";
+ compatible = "renesas,m3ulcb", "renesas,r8a7796"
- Marzen (R0P7779A00010S)
compatible = "renesas,marzen", "renesas,r8a7779"
- Porter (M2-LCDP)
@@ -93,11 +99,11 @@ Boards:
- RSKRZA1 (YR0K77210C000BE)
compatible = "renesas,rskrza1", "renesas,r7s72100"
- Salvator-X (RTP0RC7795SIPB0010S)
- compatible = "renesas,salvator-x", "renesas,r8a7795";
+ compatible = "renesas,salvator-x", "renesas,r8a7795"
- Salvator-X (RTP0RC7796SIPB0011S)
- compatible = "renesas,salvator-x", "renesas,r8a7796";
+ compatible = "renesas,salvator-x", "renesas,r8a7796"
- Salvator-XS (Salvator-X 2nd version, RTP0RC7795SIPB0012S)
- compatible = "renesas,salvator-xs", "renesas,r8a7795";
+ compatible = "renesas,salvator-xs", "renesas,r8a7795"
- SILK (RTP0RC7794LCB00011S)
compatible = "renesas,silk", "renesas,r8a7794"
- SK-RZG1E (YR8A77450S000BE)
diff --git a/Bindings/arm/sp810.txt b/Bindings/arm/sp810.txt
index 6808fb5dee40..1b2ab1ff5587 100644
--- a/Bindings/arm/sp810.txt
+++ b/Bindings/arm/sp810.txt
@@ -33,7 +33,7 @@ Required properties:
property with the highest frequency
Example:
- v2m_sysctl: sysctl@020000 {
+ v2m_sysctl: sysctl@20000 {
compatible = "arm,sp810", "arm,primecell";
reg = <0x020000 0x1000>;
clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
diff --git a/Bindings/arm/spe-pmu.txt b/Bindings/arm/spe-pmu.txt
new file mode 100644
index 000000000000..93372f2a7df9
--- /dev/null
+++ b/Bindings/arm/spe-pmu.txt
@@ -0,0 +1,20 @@
+* ARMv8.2 Statistical Profiling Extension (SPE) Performance Monitor Units (PMU)
+
+ARMv8.2 introduces the optional Statistical Profiling Extension for collecting
+performance sample data using an in-memory trace buffer.
+
+** SPE Required properties:
+
+- compatible : should be one of:
+ "arm,statistical-profiling-extension-v1"
+
+- interrupts : Exactly 1 PPI must be listed. For heterogeneous systems where
+ SPE is only supported on a subset of the CPUs, please consult
+ the arm,gic-v3 binding for details on describing a PPI partition.
+
+** Example:
+
+spe-pmu {
+ compatible = "arm,statistical-profiling-extension-v1";
+ interrupts = <GIC_PPI 05 IRQ_TYPE_LEVEL_HIGH &part1>;
+};
diff --git a/Bindings/arm/sunxi.txt b/Bindings/arm/sunxi.txt
index d2c46449b4eb..e4beec3d9ad3 100644
--- a/Bindings/arm/sunxi.txt
+++ b/Bindings/arm/sunxi.txt
@@ -14,6 +14,8 @@ using one of the following compatible strings:
allwinner,sun8i-a83t
allwinner,sun8i-h2-plus
allwinner,sun8i-h3
+ allwinner-sun8i-r40
+ allwinner,sun8i-v3s
allwinner,sun9i-a80
allwinner,sun50i-a64
nextthing,gr8
diff --git a/Bindings/arm/tegra/nvidia,tegra20-mc.txt b/Bindings/arm/tegra/nvidia,tegra20-mc.txt
index 866d93421eba..f9632bacbd04 100644
--- a/Bindings/arm/tegra/nvidia,tegra20-mc.txt
+++ b/Bindings/arm/tegra/nvidia,tegra20-mc.txt
@@ -8,7 +8,7 @@ Required properties:
- interrupts : Should contain MC General interrupt.
Example:
- memory-controller@0x7000f000 {
+ memory-controller@7000f000 {
compatible = "nvidia,tegra20-mc";
reg = <0x7000f000 0x024
0x7000f03c 0x3c4>;
diff --git a/Bindings/arm/vexpress-sysreg.txt b/Bindings/arm/vexpress-sysreg.txt
index 00318d083c9e..50095802fb4a 100644
--- a/Bindings/arm/vexpress-sysreg.txt
+++ b/Bindings/arm/vexpress-sysreg.txt
@@ -37,7 +37,7 @@ Example:
compatible = "arm,vexpress-sysreg";
reg = <0x10000000 0x1000>;
- v2m_led_gpios: sys_led@08 {
+ v2m_led_gpios: sys_led@8 {
compatible = "arm,vexpress-sysreg,sys_led";
gpio-controller;
#gpio-cells = <2>;
diff --git a/Bindings/ata/ahci-ceva.txt b/Bindings/ata/ahci-ceva.txt
index 7ca8b976c13a..7561cc4de371 100644
--- a/Bindings/ata/ahci-ceva.txt
+++ b/Bindings/ata/ahci-ceva.txt
@@ -5,6 +5,36 @@ Required properties:
- compatible: Compatibility string. Must be 'ceva,ahci-1v84'.
- clocks: Input clock specifier. Refer to common clock bindings.
- interrupts: Interrupt specifier. Refer to interrupt binding.
+ - ceva,p0-cominit-params: OOB timing value for COMINIT parameter for port 0.
+ - ceva,p1-cominit-params: OOB timing value for COMINIT parameter for port 1.
+ The fields for the above parameter must be as shown below:
+ ceva,pN-cominit-params = /bits/ 8 <CIBGMN CIBGMX CIBGN CINMP>;
+ CINMP : COMINIT Negate Minimum Period.
+ CIBGN : COMINIT Burst Gap Nominal.
+ CIBGMX: COMINIT Burst Gap Maximum.
+ CIBGMN: COMINIT Burst Gap Minimum.
+ - ceva,p0-comwake-params: OOB timing value for COMWAKE parameter for port 0.
+ - ceva,p1-comwake-params: OOB timing value for COMWAKE parameter for port 1.
+ The fields for the above parameter must be as shown below:
+ ceva,pN-comwake-params = /bits/ 8 <CWBGMN CWBGMX CWBGN CWNMP>;
+ CWBGMN: COMWAKE Burst Gap Minimum.
+ CWBGMX: COMWAKE Burst Gap Maximum.
+ CWBGN: COMWAKE Burst Gap Nominal.
+ CWNMP: COMWAKE Negate Minimum Period.
+ - ceva,p0-burst-params: Burst timing value for COM parameter for port 0.
+ - ceva,p1-burst-params: Burst timing value for COM parameter for port 1.
+ The fields for the above parameter must be as shown below:
+ ceva,pN-burst-params = /bits/ 8 <BMX BNM SFD PTST>;
+ BMX: COM Burst Maximum.
+ BNM: COM Burst Nominal.
+ SFD: Signal Failure Detection value.
+ PTST: Partial to Slumber timer value.
+ - ceva,p0-retry-params: Retry interval timing value for port 0.
+ - ceva,p1-retry-params: Retry interval timing value for port 1.
+ The fields for the above parameter must be as shown below:
+ ceva,pN-retry-params = /bits/ 16 <RIT RCT>;
+ RIT: Retry Interval Timer.
+ RCT: Rate Change Timer.
Optional properties:
- ceva,broken-gen2: limit to gen1 speed instead of gen2.
@@ -16,5 +46,14 @@ Examples:
interrupt-parent = <&gic>;
interrupts = <0 133 4>;
clocks = <&clkc SATA_CLK_ID>;
+ ceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
+ ceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
+ ceva,p0-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
+ ceva,p0-retry-params = /bits/ 16 <0x0216 0x7F06>;
+
+ ceva,p1-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
+ ceva,p1-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
+ ceva,p1-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
+ ceva,p1-retry-params = /bits/ 16 <0x0216 0x7F06>;
ceva,broken-gen2;
};
diff --git a/Bindings/ata/ahci-platform.txt b/Bindings/ata/ahci-platform.txt
index fedc213b5f1a..c760ecb81381 100644
--- a/Bindings/ata/ahci-platform.txt
+++ b/Bindings/ata/ahci-platform.txt
@@ -56,7 +56,7 @@ Examples:
interrupts = <115>;
};
- ahci: sata@01c18000 {
+ ahci: sata@1c18000 {
compatible = "allwinner,sun4i-a10-ahci";
reg = <0x01c18000 0x1000>;
interrupts = <56>;
diff --git a/Bindings/ata/imx-sata.txt b/Bindings/ata/imx-sata.txt
index fa511db18408..a3d14719e478 100644
--- a/Bindings/ata/imx-sata.txt
+++ b/Bindings/ata/imx-sata.txt
@@ -25,7 +25,7 @@ Optional properties:
Examples:
-sata@02200000 {
+sata@2200000 {
compatible = "fsl,imx6q-ahci";
reg = <0x02200000 0x4000>;
interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/Bindings/bus/imx-weim.txt b/Bindings/bus/imx-weim.txt
index 6630d842c7a3..683eaf3aed79 100644
--- a/Bindings/bus/imx-weim.txt
+++ b/Bindings/bus/imx-weim.txt
@@ -61,7 +61,7 @@ Timing property for child nodes. It is mandatory, not optional.
Example for an imx6q-sabreauto board, the NOR flash connected to the WEIM:
- weim: weim@021b8000 {
+ weim: weim@21b8000 {
compatible = "fsl,imx6q-weim";
reg = <0x021b8000 0x4000>;
clocks = <&clks 196>;
diff --git a/Bindings/bus/sunxi-rsb.txt b/Bindings/bus/sunxi-rsb.txt
index 3dd28343b6ce..eb3ed628c6f1 100644
--- a/Bindings/bus/sunxi-rsb.txt
+++ b/Bindings/bus/sunxi-rsb.txt
@@ -28,7 +28,7 @@ which can normally be found in the datasheet.
Example:
- rsb@01f03400 {
+ rsb@1f03400 {
compatible = "allwinner,sun8i-a23-rsb";
reg = <0x01f03400 0x400>;
interrupts = <0 39 4>;
diff --git a/Bindings/bus/ti-sysc.txt b/Bindings/bus/ti-sysc.txt
new file mode 100644
index 000000000000..fb1790e39398
--- /dev/null
+++ b/Bindings/bus/ti-sysc.txt
@@ -0,0 +1,93 @@
+Texas Instruments sysc interconnect target module wrapper binding
+
+Texas Instruments SoCs can have a generic interconnect target module
+hardware for devices connected to various interconnects such as L3
+interconnect (Arteris NoC) and L4 interconnect (Sonics s3220). The sysc
+is mostly used for interaction between module and PRCM. It participates
+in the OCP Disconnect Protocol but other than that is mostly independent
+of the interconnect.
+
+Each interconnect target module can have one or more devices connected to
+it. There is a set of control registers for managing interconnect target
+module clocks, idle modes and interconnect level resets for the module.
+
+These control registers are sprinkled into the unused register address
+space of the first child device IP block managed by the interconnect
+target module and typically are named REVISION, SYSCONFIG and SYSSTATUS.
+
+Required standard properties:
+
+- compatible shall be one of the following generic types:
+
+ "ti,sysc-omap2"
+ "ti,sysc-omap4"
+ "ti,sysc-omap4-simple"
+
+ or one of the following derivative types for hardware
+ needing special workarounds:
+
+ "ti,sysc-omap3430-sr"
+ "ti,sysc-omap3630-sr"
+ "ti,sysc-omap4-sr"
+ "ti,sysc-omap3-sham"
+ "ti,sysc-omap-aes"
+ "ti,sysc-mcasp"
+ "ti,sysc-usb-host-fs"
+
+- reg shall have register areas implemented for the interconnect
+ target module in question such as revision, sysc and syss
+
+- reg-names shall contain the register names implemented for the
+ interconnect target module in question such as
+ "rev, "sysc", and "syss"
+
+- ranges shall contain the interconnect target module IO range
+ available for one or more child device IP blocks managed
+ by the interconnect target module, the ranges may include
+ multiple ranges such as device L4 range for control and
+ parent L3 range for DMA access
+
+Optional properties:
+
+- clocks clock specifier for each name in the clock-names as
+ specified in the binding documentation for ti-clkctrl,
+ typically available for all interconnect targets on TI SoCs
+ based on omap4 except if it's read-only register in hwauto
+ mode as for example omap4 L4_CFG_CLKCTRL
+
+- clock-names should contain at least "fck", and optionally also "ick"
+ depending on the SoC and the interconnect target module
+
+- ti,hwmods optional TI interconnect module name to use legacy
+ hwmod platform data
+
+
+Example: Single instance of MUSB controller on omap4 using interconnect ranges
+using offsets from l4_cfg second segment (0x4a000000 + 0x80000 = 0x4a0ab000):
+
+ target-module@2b000 { /* 0x4a0ab000, ap 84 12.0 */
+ compatible = "ti,sysc-omap2";
+ ti,hwmods = "usb_otg_hs";
+ reg = <0x2b400 0x4>,
+ <0x2b404 0x4>,
+ <0x2b408 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x2b000 0x1000>;
+
+ usb_otg_hs: otg@0 {
+ compatible = "ti,omap4-musb";
+ reg = <0x0 0x7ff>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+ usb-phy = <&usb2_phy>;
+ ...
+ };
+ };
+
+Note that other SoCs, such as am335x can have multipe child devices. On am335x
+there are two MUSB instances, two USB PHY instances, and a single CPPI41 DMA
+instance as children of a single interconnet target module.
diff --git a/Bindings/bus/ts-nbus.txt b/Bindings/bus/ts-nbus.txt
new file mode 100644
index 000000000000..2a10d065b9fa
--- /dev/null
+++ b/Bindings/bus/ts-nbus.txt
@@ -0,0 +1,50 @@
+Technologic Systems NBUS
+
+The NBUS is a bus used to interface with peripherals in the Technologic
+Systems FPGA on the TS-4600 SoM.
+
+Required properties :
+ - compatible : "technologic,ts-nbus"
+ - #address-cells : must be 1
+ - #size-cells : must be 0
+ - pwms : The PWM bound to the FPGA
+ - ts,data-gpios : The 8 GPIO pins connected to the data lines on the FPGA
+ - ts,csn-gpios : The GPIO pin connected to the csn line on the FPGA
+ - ts,txrx-gpios : The GPIO pin connected to the txrx line on the FPGA
+ - ts,strobe-gpios : The GPIO pin connected to the stobe line on the FPGA
+ - ts,ale-gpios : The GPIO pin connected to the ale line on the FPGA
+ - ts,rdy-gpios : The GPIO pin connected to the rdy line on the FPGA
+
+Child nodes:
+
+The NBUS node can contain zero or more child nodes representing peripherals
+on the bus.
+
+Example:
+
+ nbus {
+ compatible = "technologic,ts-nbus";
+ pinctrl-0 = <&nbus_pins>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pwms = <&pwm 2 83>;
+ ts,data-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH
+ &gpio0 1 GPIO_ACTIVE_HIGH
+ &gpio0 2 GPIO_ACTIVE_HIGH
+ &gpio0 3 GPIO_ACTIVE_HIGH
+ &gpio0 4 GPIO_ACTIVE_HIGH
+ &gpio0 5 GPIO_ACTIVE_HIGH
+ &gpio0 6 GPIO_ACTIVE_HIGH
+ &gpio0 7 GPIO_ACTIVE_HIGH>;
+ ts,csn-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
+ ts,txrx-gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>;
+ ts,strobe-gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>;
+ ts,ale-gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
+ ts,rdy-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;
+
+ watchdog@2a {
+ compatible = "...";
+
+ /* ... */
+ };
+ };
diff --git a/Bindings/clock/arm-syscon-icst.txt b/Bindings/clock/arm-syscon-icst.txt
index 27468119fd94..4cd81742038f 100644
--- a/Bindings/clock/arm-syscon-icst.txt
+++ b/Bindings/clock/arm-syscon-icst.txt
@@ -59,7 +59,7 @@ syscon: syscon@10000000 {
compatible = "syscon";
reg = <0x10000000 0x1000>;
- oscclk0: osc0@0c {
+ oscclk0: osc0@c {
compatible = "arm,syscon-icst307";
#clock-cells = <0>;
lock-offset = <0x20>;
diff --git a/Bindings/clock/axi-clkgen.txt b/Bindings/clock/axi-clkgen.txt
index fb40da303d25..aca94fe9416f 100644
--- a/Bindings/clock/axi-clkgen.txt
+++ b/Bindings/clock/axi-clkgen.txt
@@ -17,7 +17,7 @@ Optional properties:
- clock-output-names : From common clock binding.
Example:
- clock@0xff000000 {
+ clock@ff000000 {
compatible = "adi,axi-clkgen";
#clock-cells = <0>;
reg = <0xff000000 0x1000>;
diff --git a/Bindings/clock/brcm,bcm2835-aux-clock.txt b/Bindings/clock/brcm,bcm2835-aux-clock.txt
index 7a837d2182ac..4acfc8f641b6 100644
--- a/Bindings/clock/brcm,bcm2835-aux-clock.txt
+++ b/Bindings/clock/brcm,bcm2835-aux-clock.txt
@@ -23,7 +23,7 @@ Example:
clocks = <&clk_osc>;
};
- aux: aux@0x7e215004 {
+ aux: aux@7e215004 {
compatible = "brcm,bcm2835-aux";
#clock-cells = <1>;
reg = <0x7e215000 0x8>;
diff --git a/Bindings/clock/brcm,iproc-clocks.txt b/Bindings/clock/brcm,iproc-clocks.txt
index f2c5f0e4a363..f8e4a93466cb 100644
--- a/Bindings/clock/brcm,iproc-clocks.txt
+++ b/Bindings/clock/brcm,iproc-clocks.txt
@@ -137,6 +137,20 @@ These clock IDs are defined in:
ch1_audio audiopll 2 BCM_CYGNUS_AUDIOPLL_CH1
ch2_audio audiopll 3 BCM_CYGNUS_AUDIOPLL_CH2
+Hurricane 2
+------
+PLL and leaf clock compatible strings for Hurricane 2 are:
+ "brcm,hr2-armpll"
+
+The following table defines the set of PLL/clock for Hurricane 2:
+
+ Clock Source Index ID
+ --- ----- ----- ---------
+ crystal N/A N/A N/A
+
+ armpll crystal N/A N/A
+
+
Northstar and Northstar Plus
------
PLL and leaf clock compatible strings for Northstar and Northstar Plus are:
diff --git a/Bindings/clock/clk-exynos-audss.txt b/Bindings/clock/clk-exynos-audss.txt
index 0c3d6015868d..6030afb10b5c 100644
--- a/Bindings/clock/clk-exynos-audss.txt
+++ b/Bindings/clock/clk-exynos-audss.txt
@@ -33,6 +33,12 @@ Required Properties:
- clock-names: Aliases for the above clocks. They should be "pll_ref",
"pll_in", "cdclk", "sclk_audio", and "sclk_pcm_in" respectively.
+Optional Properties:
+
+ - power-domains: a phandle to respective power domain node as described by
+ generic PM domain bindings (see power/power_domain.txt for more
+ information).
+
The following is the list of clocks generated by the controller. Each clock is
assigned an identifier and client nodes use this identifier to specify the
clock which they consume. Some of the clocks are available only on a particular
@@ -80,7 +86,7 @@ Example 3: I2S controller node that consumes the clock generated by the clock
controller. Refer to the standard clock bindings for information
about 'clocks' and 'clock-names' property.
-i2s0: i2s@03830000 {
+i2s0: i2s@3830000 {
compatible = "samsung,i2s-v5";
reg = <0x03830000 0x100>;
dmas = <&pdma0 10
diff --git a/Bindings/clock/clk-s5pv210-audss.txt b/Bindings/clock/clk-s5pv210-audss.txt
index 4fc869b69d4a..f6272dcd96f4 100644
--- a/Bindings/clock/clk-s5pv210-audss.txt
+++ b/Bindings/clock/clk-s5pv210-audss.txt
@@ -43,7 +43,7 @@ Example: I2S controller node that consumes the clock generated by the clock
controller. Refer to the standard clock bindings for information
about 'clocks' and 'clock-names' property.
- i2s0: i2s@03830000 {
+ i2s0: i2s@3830000 {
/* ... */
clock-names = "iis", "i2s_opclk0",
"i2s_opclk1";
diff --git a/Bindings/clock/dove-divider-clock.txt b/Bindings/clock/dove-divider-clock.txt
index e3eb0f657c5e..217871f483c0 100644
--- a/Bindings/clock/dove-divider-clock.txt
+++ b/Bindings/clock/dove-divider-clock.txt
@@ -21,7 +21,7 @@ Required properties:
a size of 8.
- #clock-cells : from common clock binding; shall be set to 1
-divider_clk: core-clock@0064 {
+divider_clk: core-clock@64 {
compatible = "marvell,dove-divider-clock";
reg = <0x0064 0x8>;
#clock-cells = <1>;
diff --git a/Bindings/clock/exynos4-clock.txt b/Bindings/clock/exynos4-clock.txt
index f5a5b19ed3b2..17bb11365354 100644
--- a/Bindings/clock/exynos4-clock.txt
+++ b/Bindings/clock/exynos4-clock.txt
@@ -24,7 +24,7 @@ tree sources.
Example 1: An example of a clock controller node is listed below.
- clock: clock-controller@0x10030000 {
+ clock: clock-controller@10030000 {
compatible = "samsung,exynos4210-clock";
reg = <0x10030000 0x20000>;
#clock-cells = <1>;
@@ -41,3 +41,46 @@ Example 2: UART controller node that consumes the clock generated by the clock
clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
clock-names = "uart", "clk_uart_baud0";
};
+
+Exynos4412 SoC contains some additional clocks for FIMC-ISP (Camera ISP)
+subsystem. Registers for those clocks are located in the ISP power domain.
+Because those registers are also located in a different memory region than
+the main clock controller, a separate clock controller has to be defined for
+handling them.
+
+Required Properties:
+
+- compatible: should be "samsung,exynos4412-isp-clock".
+
+- reg: physical base address of the ISP clock controller and length of memory
+ mapped region.
+
+- #clock-cells: should be 1.
+
+- clocks: list of the clock controller input clock identifiers,
+ from common clock bindings, should point to CLK_ACLK200 and
+ CLK_ACLK400_MCUISP clocks from the main clock controller.
+
+- clock-names: list of the clock controller input clock names,
+ as described in clock-bindings.txt, should be "aclk200" and
+ "aclk400_mcuisp".
+
+- power-domains: a phandle to ISP power domain node as described by
+ generic PM domain bindings.
+
+Example 3: The clock controllers bindings for Exynos4412 SoCs.
+
+ clock: clock-controller@10030000 {
+ compatible = "samsung,exynos4412-clock";
+ reg = <0x10030000 0x18000>;
+ #clock-cells = <1>;
+ };
+
+ isp_clock: clock-controller@10048000 {
+ compatible = "samsung,exynos4412-isp-clock";
+ reg = <0x10048000 0x1000>;
+ #clock-cells = <1>;
+ power-domains = <&pd_isp>;
+ clocks = <&clock CLK_ACLK200>, <&clock CLK_ACLK400_MCUISP>;
+ clock-names = "aclk200", "aclk400_mcuisp";
+ };
diff --git a/Bindings/clock/exynos5250-clock.txt b/Bindings/clock/exynos5250-clock.txt
index 536eacd1063f..aff266a12eeb 100644
--- a/Bindings/clock/exynos5250-clock.txt
+++ b/Bindings/clock/exynos5250-clock.txt
@@ -22,7 +22,7 @@ tree sources.
Example 1: An example of a clock controller node is listed below.
- clock: clock-controller@0x10010000 {
+ clock: clock-controller@10010000 {
compatible = "samsung,exynos5250-clock";
reg = <0x10010000 0x30000>;
#clock-cells = <1>;
diff --git a/Bindings/clock/exynos5410-clock.txt b/Bindings/clock/exynos5410-clock.txt
index 4527de3ea205..c68b0d29b3d0 100644
--- a/Bindings/clock/exynos5410-clock.txt
+++ b/Bindings/clock/exynos5410-clock.txt
@@ -30,7 +30,7 @@ Example 1: An example of a clock controller node is listed below.
#clock-cells = <0>;
};
- clock: clock-controller@0x10010000 {
+ clock: clock-controller@10010000 {
compatible = "samsung,exynos5410-clock";
reg = <0x10010000 0x30000>;
#clock-cells = <1>;
diff --git a/Bindings/clock/exynos5420-clock.txt b/Bindings/clock/exynos5420-clock.txt
index d54f42cf0440..717a7b1531c7 100644
--- a/Bindings/clock/exynos5420-clock.txt
+++ b/Bindings/clock/exynos5420-clock.txt
@@ -23,7 +23,7 @@ tree sources.
Example 1: An example of a clock controller node is listed below.
- clock: clock-controller@0x10010000 {
+ clock: clock-controller@10010000 {
compatible = "samsung,exynos5420-clock";
reg = <0x10010000 0x30000>;
#clock-cells = <1>;
diff --git a/Bindings/clock/exynos5433-clock.txt b/Bindings/clock/exynos5433-clock.txt
index fe885abc9cb4..c473dd38dd55 100644
--- a/Bindings/clock/exynos5433-clock.txt
+++ b/Bindings/clock/exynos5433-clock.txt
@@ -168,6 +168,11 @@ Required Properties:
- aclk_cam1_400
- aclk_cam1_552
+Optional properties:
+ - power-domains: a phandle to respective power domain node as described by
+ generic PM domain bindings (see power/power_domain.txt for more
+ information).
+
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume.
@@ -270,6 +275,7 @@ Example 2: Examples of clock controller nodes are listed below.
clocks = <&xxti>,
<&cmu_top CLK_ACLK_G2D_266>,
<&cmu_top CLK_ACLK_G2D_400>;
+ power-domains = <&pd_g2d>;
};
cmu_disp: clock-controller@13b90000 {
@@ -295,6 +301,7 @@ Example 2: Examples of clock controller nodes are listed below.
<&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
<&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>,
<&cmu_mif CLK_ACLK_DISP_333>;
+ power-domains = <&pd_disp>;
};
cmu_aud: clock-controller@114c0000 {
@@ -304,6 +311,7 @@ Example 2: Examples of clock controller nodes are listed below.
clock-names = "oscclk", "fout_aud_pll";
clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>;
+ power-domains = <&pd_aud>;
};
cmu_bus0: clock-controller@13600000 {
@@ -340,6 +348,7 @@ Example 2: Examples of clock controller nodes are listed below.
clock-names = "oscclk", "aclk_g3d_400";
clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>;
+ power-domains = <&pd_g3d>;
};
cmu_gscl: clock-controller@13cf0000 {
@@ -353,6 +362,7 @@ Example 2: Examples of clock controller nodes are listed below.
clocks = <&xxti>,
<&cmu_top CLK_ACLK_GSCL_111>,
<&cmu_top CLK_ACLK_GSCL_333>;
+ power-domains = <&pd_gscl>;
};
cmu_apollo: clock-controller@11900000 {
@@ -384,6 +394,7 @@ Example 2: Examples of clock controller nodes are listed below.
clocks = <&xxti>,
<&cmu_top CLK_SCLK_JPEG_MSCL>,
<&cmu_top CLK_ACLK_MSCL_400>;
+ power-domains = <&pd_mscl>;
};
cmu_mfc: clock-controller@15280000 {
@@ -393,6 +404,7 @@ Example 2: Examples of clock controller nodes are listed below.
clock-names = "oscclk", "aclk_mfc_400";
clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>;
+ power-domains = <&pd_mfc>;
};
cmu_hevc: clock-controller@14f80000 {
@@ -402,6 +414,7 @@ Example 2: Examples of clock controller nodes are listed below.
clock-names = "oscclk", "aclk_hevc_400";
clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>;
+ power-domains = <&pd_hevc>;
};
cmu_isp: clock-controller@146d0000 {
@@ -415,6 +428,7 @@ Example 2: Examples of clock controller nodes are listed below.
clocks = <&xxti>,
<&cmu_top CLK_ACLK_ISP_DIS_400>,
<&cmu_top CLK_ACLK_ISP_400>;
+ power-domains = <&pd_isp>;
};
cmu_cam0: clock-controller@120d0000 {
@@ -430,6 +444,7 @@ Example 2: Examples of clock controller nodes are listed below.
<&cmu_top CLK_ACLK_CAM0_333>,
<&cmu_top CLK_ACLK_CAM0_400>,
<&cmu_top CLK_ACLK_CAM0_552>;
+ power-domains = <&pd_cam0>;
};
cmu_cam1: clock-controller@145d0000 {
@@ -451,6 +466,7 @@ Example 2: Examples of clock controller nodes are listed below.
<&cmu_top CLK_ACLK_CAM1_333>,
<&cmu_top CLK_ACLK_CAM1_400>,
<&cmu_top CLK_ACLK_CAM1_552>;
+ power-domains = <&pd_cam1>;
};
Example 3: UART controller node that consumes the clock generated by the clock
diff --git a/Bindings/clock/exynos5440-clock.txt b/Bindings/clock/exynos5440-clock.txt
index 5f7005f73058..c7d227c31e95 100644
--- a/Bindings/clock/exynos5440-clock.txt
+++ b/Bindings/clock/exynos5440-clock.txt
@@ -21,7 +21,7 @@ tree sources.
Example: An example of a clock controller node is listed below.
- clock: clock-controller@0x10010000 {
+ clock: clock-controller@10010000 {
compatible = "samsung,exynos5440-clock";
reg = <0x160000 0x10000>;
#clock-cells = <1>;
diff --git a/Bindings/clock/imx1-clock.txt b/Bindings/clock/imx1-clock.txt
index b7adf4e3ea98..9823baf7acb6 100644
--- a/Bindings/clock/imx1-clock.txt
+++ b/Bindings/clock/imx1-clock.txt
@@ -10,13 +10,13 @@ ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx1-clock.h
for the full list of i.MX1 clock IDs.
Examples:
- clks: ccm@0021b000 {
+ clks: ccm@21b000 {
#clock-cells = <1>;
compatible = "fsl,imx1-ccm";
reg = <0x0021b000 0x1000>;
};
- pwm: pwm@00208000 {
+ pwm: pwm@208000 {
#pwm-cells = <2>;
compatible = "fsl,imx1-pwm";
reg = <0x00208000 0x1000>;
diff --git a/Bindings/clock/imx6q-clock.txt b/Bindings/clock/imx6q-clock.txt
index aa0a4d423ef5..a45ca67a9d5f 100644
--- a/Bindings/clock/imx6q-clock.txt
+++ b/Bindings/clock/imx6q-clock.txt
@@ -14,14 +14,14 @@ Examples:
#include <dt-bindings/clock/imx6qdl-clock.h>
-clks: ccm@020c4000 {
+clks: ccm@20c4000 {
compatible = "fsl,imx6q-ccm";
reg = <0x020c4000 0x4000>;
interrupts = <0 87 0x04 0 88 0x04>;
#clock-cells = <1>;
};
-uart1: serial@02020000 {
+uart1: serial@2020000 {
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x02020000 0x4000>;
interrupts = <0 26 0x04>;
diff --git a/Bindings/clock/maxim,max77686.txt b/Bindings/clock/maxim,max77686.txt
index 8398a3a5e106..3472b461ca93 100644
--- a/Bindings/clock/maxim,max77686.txt
+++ b/Bindings/clock/maxim,max77686.txt
@@ -46,7 +46,7 @@ Example:
/* ... */
Node of the MFD chip
- max77686: max77686@09 {
+ max77686: max77686@9 {
compatible = "maxim,max77686";
interrupt-parent = <&wakeup_eint>;
interrupts = <26 0>;
@@ -71,7 +71,7 @@ Example:
/* ... */
Node of the MFD chip
- max77802: max77802@09 {
+ max77802: max77802@9 {
compatible = "maxim,max77802";
interrupt-parent = <&wakeup_eint>;
interrupts = <26 0>;
diff --git a/Bindings/clock/qcom,rpmcc.txt b/Bindings/clock/qcom,rpmcc.txt
index a7235e9e1c97..4491d1c104aa 100644
--- a/Bindings/clock/qcom,rpmcc.txt
+++ b/Bindings/clock/qcom,rpmcc.txt
@@ -10,12 +10,23 @@ Required properties :
- compatible : shall contain only one of the following. The generic
compatible "qcom,rpmcc" should be also included.
+ "qcom,rpmcc-msm8660", "qcom,rpmcc"
+ "qcom,rpmcc-apq8060", "qcom,rpmcc"
"qcom,rpmcc-msm8916", "qcom,rpmcc"
"qcom,rpmcc-msm8974", "qcom,rpmcc"
"qcom,rpmcc-apq8064", "qcom,rpmcc"
+ "qcom,rpmcc-msm8996", "qcom,rpmcc"
- #clock-cells : shall contain 1
+The clock enumerators are defined in <dt-bindings/clock/qcom,rpmcc.h>
+and come in pairs: FOO_CLK followed by FOO_A_CLK. The latter clock
+is an "active" clock, which means that the consumer only care that the
+clock is available when the apps CPU subsystem is active, i.e. not
+suspended or in deep idle. If it is important that the clock keeps running
+during system suspend, you need to specify the non-active clock, the one
+not containing *_A_* in the enumerator name.
+
Example:
smd {
compatible = "qcom,smd";
diff --git a/Bindings/clock/renesas,cpg-mssr.txt b/Bindings/clock/renesas,cpg-mssr.txt
index 316e13686568..f1890d0777a6 100644
--- a/Bindings/clock/renesas,cpg-mssr.txt
+++ b/Bindings/clock/renesas,cpg-mssr.txt
@@ -22,6 +22,7 @@ Required Properties:
- "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2)
- "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
- "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)
+ - "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M)
- "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3)
- reg: Base address and length of the memory resource used by the CPG/MSSR
@@ -31,8 +32,8 @@ Required Properties:
clock-names
- clock-names: List of external parent clock names. Valid names are:
- "extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794,
- r8a7795, r8a7796, r8a77995)
- - "extalr" (r8a7795, r8a7796)
+ r8a7795, r8a7796, r8a77970, r8a77995)
+ - "extalr" (r8a7795, r8a7796, r8a77970)
- "usb_extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7793, r8a7794)
- #clock-cells: Must be 2
diff --git a/Bindings/clock/renesas,rz-cpg-clocks.txt b/Bindings/clock/renesas,rz-cpg-clocks.txt
index bb5d942075fb..8ff3e2774ed8 100644
--- a/Bindings/clock/renesas,rz-cpg-clocks.txt
+++ b/Bindings/clock/renesas,rz-cpg-clocks.txt
@@ -1,6 +1,6 @@
-* Renesas RZ Clock Pulse Generator (CPG)
+* Renesas RZ/A1 Clock Pulse Generator (CPG)
-The CPG generates core clocks for the RZ SoCs. It includes the PLL, variable
+The CPG generates core clocks for the RZ/A1 SoCs. It includes the PLL, variable
CPU and GPU clocks, and several fixed ratio dividers.
The CPG also provides a Clock Domain for SoC devices, in combination with the
CPG Module Stop (MSTP) Clocks.
diff --git a/Bindings/clock/st/st,clkgen.txt b/Bindings/clock/st/st,clkgen.txt
index c35390f60545..7364953d0d0b 100644
--- a/Bindings/clock/st/st,clkgen.txt
+++ b/Bindings/clock/st/st,clkgen.txt
@@ -42,7 +42,7 @@ Required properties:
Example:
- clockgen-a@090ff000 {
+ clockgen-a@90ff000 {
compatible = "st,clkgen-c32";
reg = <0x90ff000 0x1000>;
diff --git a/Bindings/clock/sunxi-ccu.txt b/Bindings/clock/sunxi-ccu.txt
index 7eda08eb8a1e..4ca21c3a6fc9 100644
--- a/Bindings/clock/sunxi-ccu.txt
+++ b/Bindings/clock/sunxi-ccu.txt
@@ -36,7 +36,7 @@ For the PRCM CCUs on A83T/H3/A64, two more clocks are needed:
- "iosc": the SoC's internal frequency oscillator
Example for generic CCU:
-ccu: clock@01c20000 {
+ccu: clock@1c20000 {
compatible = "allwinner,sun8i-h3-ccu";
reg = <0x01c20000 0x400>;
clocks = <&osc24M>, <&osc32k>;
@@ -46,7 +46,7 @@ ccu: clock@01c20000 {
};
Example for PRCM CCU:
-r_ccu: clock@01f01400 {
+r_ccu: clock@1f01400 {
compatible = "allwinner,sun50i-a64-r-ccu";
reg = <0x01f01400 0x100>;
clocks = <&osc24M>, <&osc32k>, <&iosc>, <&ccu CLK_PLL_PERIPH0>;
diff --git a/Bindings/clock/sunxi.txt b/Bindings/clock/sunxi.txt
index 8f7619d8c8d8..1a042e20b115 100644
--- a/Bindings/clock/sunxi.txt
+++ b/Bindings/clock/sunxi.txt
@@ -137,7 +137,7 @@ the address block, which is related to the overall mmc block.
For example:
-osc24M: clk@01c20050 {
+osc24M: clk@1c20050 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-osc-clk";
reg = <0x01c20050 0x4>;
@@ -145,7 +145,7 @@ osc24M: clk@01c20050 {
clock-output-names = "osc24M";
};
-pll1: clk@01c20000 {
+pll1: clk@1c20000 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-pll1-clk";
reg = <0x01c20000 0x4>;
@@ -153,7 +153,7 @@ pll1: clk@01c20000 {
clock-output-names = "pll1";
};
-pll5: clk@01c20020 {
+pll5: clk@1c20020 {
#clock-cells = <1>;
compatible = "allwinner,sun4i-pll5-clk";
reg = <0x01c20020 0x4>;
@@ -161,7 +161,7 @@ pll5: clk@01c20020 {
clock-output-names = "pll5_ddr", "pll5_other";
};
-pll6: clk@01c20028 {
+pll6: clk@1c20028 {
#clock-cells = <1>;
compatible = "allwinner,sun6i-a31-pll6-clk";
reg = <0x01c20028 0x4>;
@@ -169,7 +169,7 @@ pll6: clk@01c20028 {
clock-output-names = "pll6", "pll6x2";
};
-cpu: cpu@01c20054 {
+cpu: cpu@1c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-cpu-clk";
reg = <0x01c20054 0x4>;
@@ -177,7 +177,7 @@ cpu: cpu@01c20054 {
clock-output-names = "cpu";
};
-mmc0_clk: clk@01c20088 {
+mmc0_clk: clk@1c20088 {
#clock-cells = <1>;
compatible = "allwinner,sun4i-a10-mmc-clk";
reg = <0x01c20088 0x4>;
@@ -199,7 +199,7 @@ gmac_int_tx_clk: clk@3 {
clock-output-names = "gmac_int_tx";
};
-gmac_clk: clk@01c20164 {
+gmac_clk: clk@1c20164 {
#clock-cells = <0>;
compatible = "allwinner,sun7i-a20-gmac-clk";
reg = <0x01c20164 0x4>;
@@ -211,7 +211,7 @@ gmac_clk: clk@01c20164 {
clock-output-names = "gmac";
};
-mmc_config_clk: clk@01c13000 {
+mmc_config_clk: clk@1c13000 {
compatible = "allwinner,sun9i-a80-mmc-config-clk";
reg = <0x01c13000 0x10>;
clocks = <&ahb0_gates 8>;
diff --git a/Bindings/clock/ti,cdce706.txt b/Bindings/clock/ti,cdce706.txt
index 616836e7e1e2..959d96632f5d 100644
--- a/Bindings/clock/ti,cdce706.txt
+++ b/Bindings/clock/ti,cdce706.txt
@@ -25,7 +25,7 @@ Example:
};
};
...
- i2c0: i2c-master@0d090000 {
+ i2c0: i2c-master@d090000 {
...
cdce706: clock-synth@69 {
compatible = "ti,cdce706";
diff --git a/Bindings/clock/ti-keystone-pllctrl.txt b/Bindings/clock/ti-keystone-pllctrl.txt
index 3e6a81e99804..c35cb6c4af4d 100644
--- a/Bindings/clock/ti-keystone-pllctrl.txt
+++ b/Bindings/clock/ti-keystone-pllctrl.txt
@@ -14,7 +14,7 @@ Required properties:
Example:
-pllctrl: pll-controller@0x02310000 {
+pllctrl: pll-controller@02310000 {
compatible = "ti,keystone-pllctrl", "syscon";
reg = <0x02310000 0x200>;
};
diff --git a/Bindings/clock/zx296702-clk.txt b/Bindings/clock/zx296702-clk.txt
index e85ecb510d56..5c91c9e4f1be 100644
--- a/Bindings/clock/zx296702-clk.txt
+++ b/Bindings/clock/zx296702-clk.txt
@@ -20,13 +20,13 @@ ID in its "clocks" phandle cell. See include/dt-bindings/clock/zx296702-clock.h
for the full list of zx296702 clock IDs.
-topclk: topcrm@0x09800000 {
+topclk: topcrm@09800000 {
compatible = "zte,zx296702-topcrm-clk";
reg = <0x09800000 0x1000>;
#clock-cells = <1>;
};
-uart0: serial@0x09405000 {
+uart0: serial@09405000 {
compatible = "zte,zx296702-uart";
reg = <0x09405000 0x1000>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/Bindings/common-properties.txt b/Bindings/common-properties.txt
index 697714f8d75c..a3448bfa1c82 100644
--- a/Bindings/common-properties.txt
+++ b/Bindings/common-properties.txt
@@ -1,4 +1,8 @@
Common properties
+=================
+
+Endianness
+----------
The Devicetree Specification does not define any properties related to hardware
byteswapping, but endianness issues show up frequently in porting Linux to
@@ -58,3 +62,25 @@ dev: dev@40031000 {
...
little-endian;
};
+
+Daisy-chained devices
+---------------------
+
+Many serially-attached GPIO and IIO devices are daisy-chainable. To the
+host controller, a daisy-chain appears as a single device, but the number
+of inputs and outputs it provides is the sum of inputs and outputs provided
+by all of its devices. The driver needs to know how many devices the
+daisy-chain comprises to determine the amount of data exchanged, how many
+inputs and outputs to register and so on.
+
+Optional properties:
+ - #daisy-chained-devices: Number of devices in the daisy-chain (default is 1).
+
+Example:
+gpio@0 {
+ compatible = "name";
+ reg = <0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ #daisy-chained-devices = <3>;
+};
diff --git a/Bindings/crypto/fsl-sec4.txt b/Bindings/crypto/fsl-sec4.txt
index 7aef0eae58d4..76aec8a3724d 100644
--- a/Bindings/crypto/fsl-sec4.txt
+++ b/Bindings/crypto/fsl-sec4.txt
@@ -456,7 +456,7 @@ System ON/OFF key driver
Definition: this is phandle to the register map node.
EXAMPLE:
- snvs-pwrkey@0x020cc000 {
+ snvs-pwrkey@020cc000 {
compatible = "fsl,sec-v4.0-pwrkey";
regmap = <&snvs>;
interrupts = <0 4 0x4>
@@ -545,7 +545,7 @@ FULL EXAMPLE
interrupts = <93 2>;
};
- snvs-pwrkey@0x020cc000 {
+ snvs-pwrkey@020cc000 {
compatible = "fsl,sec-v4.0-pwrkey";
regmap = <&sec_mon>;
interrupts = <0 4 0x4>;
diff --git a/Bindings/rng/samsung,exynos-rng4.txt b/Bindings/crypto/samsung,exynos-rng4.txt
index 4ca8dd4d7e66..4ca8dd4d7e66 100644
--- a/Bindings/rng/samsung,exynos-rng4.txt
+++ b/Bindings/crypto/samsung,exynos-rng4.txt
diff --git a/Bindings/crypto/sun4i-ss.txt b/Bindings/crypto/sun4i-ss.txt
index 5d38e9b7033f..f2dc3d9bca92 100644
--- a/Bindings/crypto/sun4i-ss.txt
+++ b/Bindings/crypto/sun4i-ss.txt
@@ -14,7 +14,7 @@ Optional properties:
- reset-names : must contain "ahb"
Example:
- crypto: crypto-engine@01c15000 {
+ crypto: crypto-engine@1c15000 {
compatible = "allwinner,sun4i-a10-crypto";
reg = <0x01c15000 0x1000>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/Bindings/devfreq/event/rockchip-dfi.txt b/Bindings/devfreq/event/rockchip-dfi.txt
index 001dd63979a9..148191b0fc15 100644
--- a/Bindings/devfreq/event/rockchip-dfi.txt
+++ b/Bindings/devfreq/event/rockchip-dfi.txt
@@ -9,7 +9,7 @@ Required properties:
- clock-names : the name of clock used by the DFI, must be "pclk_ddr_mon";
Example:
- dfi: dfi@0xff630000 {
+ dfi: dfi@ff630000 {
compatible = "rockchip,rk3399-dfi";
reg = <0x00 0xff630000 0x00 0x4000>;
rockchip,pmu = <&pmugrf>;
diff --git a/Bindings/display/atmel,lcdc.txt b/Bindings/display/atmel,lcdc.txt
index 1a21202778ee..acb5a0132127 100644
--- a/Bindings/display/atmel,lcdc.txt
+++ b/Bindings/display/atmel,lcdc.txt
@@ -27,7 +27,7 @@ Optional properties:
Example:
- fb0: fb@0x00500000 {
+ fb0: fb@00500000 {
compatible = "atmel,at91sam9g45-lcdc";
reg = <0x00500000 0x1000>;
interrupts = <23 3 0>;
@@ -41,7 +41,7 @@ Example:
Example for fixed framebuffer memory:
- fb0: fb@0x00500000 {
+ fb0: fb@00500000 {
compatible = "atmel,at91sam9263-lcdc";
reg = <0x00700000 0x1000 0x70000000 0x200000>;
[...]
diff --git a/Bindings/display/bridge/adi,adv7511.txt b/Bindings/display/bridge/adi,adv7511.txt
index 06668bca7ffc..0047b1394c70 100644
--- a/Bindings/display/bridge/adi,adv7511.txt
+++ b/Bindings/display/bridge/adi,adv7511.txt
@@ -68,6 +68,8 @@ Optional properties:
- adi,disable-timing-generator: Only for ADV7533. Disables the internal timing
generator. The chip will rely on the sync signals in the DSI data lanes,
rather than generate its own timings for HDMI output.
+- clocks: from common clock binding: reference to the CEC clock.
+- clock-names: from common clock binding: must be "cec".
Required nodes:
@@ -89,6 +91,8 @@ Example
reg = <39>;
interrupt-parent = <&gpio3>;
interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
+ clocks = <&cec_clock>;
+ clock-names = "cec";
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
diff --git a/Bindings/display/bridge/renesas,dw-hdmi.txt b/Bindings/display/bridge/renesas,dw-hdmi.txt
index b1a8929c2536..3a72a103a18a 100644
--- a/Bindings/display/bridge/renesas,dw-hdmi.txt
+++ b/Bindings/display/bridge/renesas,dw-hdmi.txt
@@ -37,7 +37,7 @@ Optional properties:
Example:
- hdmi0: hdmi0@fead0000 {
+ hdmi0: hdmi@fead0000 {
compatible = "renesas,r8a7795-dw-hdmi";
reg = <0 0xfead0000 0 0x10000>;
interrupts = <0 389 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/Bindings/display/bridge/sii9234.txt b/Bindings/display/bridge/sii9234.txt
new file mode 100644
index 000000000000..88041ba23d56
--- /dev/null
+++ b/Bindings/display/bridge/sii9234.txt
@@ -0,0 +1,49 @@
+Silicon Image SiI9234 HDMI/MHL bridge bindings
+
+Required properties:
+ - compatible : "sil,sii9234".
+ - reg : I2C address for TPI interface, use 0x39
+ - avcc33-supply : MHL/USB Switch Supply Voltage (3.3V)
+ - iovcc18-supply : I/O Supply Voltage (1.8V)
+ - avcc12-supply : TMDS Analog Supply Voltage (1.2V)
+ - cvcc12-supply : Digital Core Supply Voltage (1.2V)
+ - interrupts, interrupt-parent: interrupt specifier of INT pin
+ - reset-gpios: gpio specifier of RESET pin (active low)
+ - video interfaces: Device node can contain two video interface port
+ nodes for HDMI encoder and connector according to [1].
+ - port@0 - MHL to HDMI
+ - port@1 - MHL to connector
+
+[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
+
+
+Example:
+ sii9234@39 {
+ compatible = "sil,sii9234";
+ reg = <0x39>;
+ avcc33-supply = <&vcc33mhl>;
+ iovcc18-supply = <&vcc18mhl>;
+ avcc12-supply = <&vsil12>;
+ cvcc12-supply = <&vsil12>;
+ reset-gpios = <&gpf3 4 GPIO_ACTIVE_LOW>;
+ interrupt-parent = <&gpf3>;
+ interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mhl_to_hdmi: endpoint {
+ remote-endpoint = <&hdmi_to_mhl>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ mhl_to_connector: endpoint {
+ remote-endpoint = <&connector_to_mhl>;
+ };
+ };
+ };
+ };
diff --git a/Bindings/display/etnaviv/etnaviv-drm.txt b/Bindings/display/etnaviv/etnaviv-drm.txt
index ed5e0a7894ad..05176f1ae108 100644
--- a/Bindings/display/etnaviv/etnaviv-drm.txt
+++ b/Bindings/display/etnaviv/etnaviv-drm.txt
@@ -42,7 +42,7 @@ Optional properties:
example:
-gpu_3d: gpu@00130000 {
+gpu_3d: gpu@130000 {
compatible = "vivante,gc";
reg = <0x00130000 0x4000>;
interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/Bindings/display/faraday,tve200.txt b/Bindings/display/faraday,tve200.txt
new file mode 100644
index 000000000000..82e3bc0b7485
--- /dev/null
+++ b/Bindings/display/faraday,tve200.txt
@@ -0,0 +1,54 @@
+* Faraday TV Encoder TVE200
+
+Required properties:
+
+- compatible: must be one of:
+ "faraday,tve200"
+ "cortina,gemini-tvc", "faraday,tve200"
+
+- reg: base address and size of the control registers block
+
+- interrupts: contains an interrupt specifier for the interrupt
+ line from the TVE200
+
+- clock-names: should contain "PCLK" for the clock line clocking the
+ silicon and "TVE" for the 27MHz clock to the video driver
+
+- clocks: contains phandle and clock specifier pairs for the entries
+ in the clock-names property. See
+ Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Optional properties:
+
+- resets: contains the reset line phandle for the block
+
+Required sub-nodes:
+
+- port: describes LCD panel signals, following the common binding
+ for video transmitter interfaces; see
+ Documentation/devicetree/bindings/media/video-interfaces.txt
+ This port should have the properties:
+ reg = <0>;
+ It should have one endpoint connected to a remote endpoint where
+ the display is connected.
+
+Example:
+
+display-controller@6a000000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "faraday,tve200";
+ reg = <0x6a000000 0x1000>;
+ interrupts = <13 IRQ_TYPE_EDGE_RISING>;
+ resets = <&syscon GEMINI_RESET_TVC>;
+ clocks = <&syscon GEMINI_CLK_GATE_TVC>,
+ <&syscon GEMINI_CLK_TVC>;
+ clock-names = "PCLK", "TVE";
+
+ port@0 {
+ reg = <0>;
+ display_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+};
diff --git a/Bindings/display/google,goldfish-fb.txt b/Bindings/display/google,goldfish-fb.txt
new file mode 100644
index 000000000000..751fa9f51e5d
--- /dev/null
+++ b/Bindings/display/google,goldfish-fb.txt
@@ -0,0 +1,17 @@
+Android Goldfish framebuffer
+
+Android Goldfish framebuffer device used by Android emulator.
+
+Required properties:
+
+- compatible : should contain "google,goldfish-fb"
+- reg : <registers mapping>
+- interrupts : <interrupt mapping>
+
+Example:
+
+ display-controller@1f008000 {
+ compatible = "google,goldfish-fb";
+ interrupts = <0x10>;
+ reg = <0x1f008000 0x100>;
+ };
diff --git a/Bindings/display/imx/fsl-imx-drm.txt b/Bindings/display/imx/fsl-imx-drm.txt
index f79854783c2c..5bf77f6dd19d 100644
--- a/Bindings/display/imx/fsl-imx-drm.txt
+++ b/Bindings/display/imx/fsl-imx-drm.txt
@@ -129,7 +129,7 @@ Optional properties:
example:
-display@di0 {
+disp0 {
compatible = "fsl,imx-parallel-display";
edid = [edid-data];
interface-pix-fmt = "rgb24";
diff --git a/Bindings/display/imx/hdmi.txt b/Bindings/display/imx/hdmi.txt
index 66a8f86e5d12..6d021e71c9cf 100644
--- a/Bindings/display/imx/hdmi.txt
+++ b/Bindings/display/imx/hdmi.txt
@@ -32,11 +32,11 @@ Optional properties
Example:
- gpr: iomuxc-gpr@020e0000 {
+ gpr: iomuxc-gpr@20e0000 {
/* ... */
};
- hdmi: hdmi@0120000 {
+ hdmi: hdmi@120000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6q-hdmi";
diff --git a/Bindings/display/msm/dsi.txt b/Bindings/display/msm/dsi.txt
index fa00e62e1cf6..a6671bd2c85a 100644
--- a/Bindings/display/msm/dsi.txt
+++ b/Bindings/display/msm/dsi.txt
@@ -13,16 +13,16 @@ Required properties:
- power-domains: Should be <&mmcc MDSS_GDSC>.
- clocks: Phandles to device clocks.
- clock-names: the following clocks are required:
- * "mdp_core_clk"
- * "iface_clk"
- * "bus_clk"
- * "core_mmss_clk"
- * "byte_clk"
- * "pixel_clk"
- * "core_clk"
+ * "mdp_core"
+ * "iface"
+ * "bus"
+ * "core_mmss"
+ * "byte"
+ * "pixel"
+ * "core"
For DSIv2, we need an additional clock:
- * "src_clk"
-- assigned-clocks: Parents of "byte_clk" and "pixel_clk" for the given platform.
+ * "src"
+- assigned-clocks: Parents of "byte" and "pixel" for the given platform.
- assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided
by a DSI PHY block. See [1] for details on clock bindings.
- vdd-supply: phandle to vdd regulator device node
@@ -101,7 +101,7 @@ Required properties:
- power-domains: Should be <&mmcc MDSS_GDSC>.
- clocks: Phandles to device clocks. See [1] for details on clock bindings.
- clock-names: the following clocks are required:
- * "iface_clk"
+ * "iface"
- vddio-supply: phandle to vdd-io regulator device node
Optional properties:
@@ -123,13 +123,13 @@ Example:
reg = <0xfd922800 0x200>;
power-domains = <&mmcc MDSS_GDSC>;
clock-names =
- "bus_clk",
- "byte_clk",
- "core_clk",
- "core_mmss_clk",
- "iface_clk",
- "mdp_core_clk",
- "pixel_clk";
+ "bus",
+ "byte",
+ "core",
+ "core_mmss",
+ "iface",
+ "mdp_core",
+ "pixel";
clocks =
<&mmcc MDSS_AXI_CLK>,
<&mmcc MDSS_BYTE0_CLK>,
@@ -207,7 +207,7 @@ Example:
reg = <0xfd922a00 0xd4>,
<0xfd922b00 0x2b0>,
<0xfd922d80 0x7b>;
- clock-names = "iface_clk";
+ clock-names = "iface";
clocks = <&mmcc MDSS_AHB_CLK>;
#clock-cells = <1>;
vddio-supply = <&pma8084_l12>;
diff --git a/Bindings/display/msm/edp.txt b/Bindings/display/msm/edp.txt
index e63032be5401..95ce19ca7bc5 100644
--- a/Bindings/display/msm/edp.txt
+++ b/Bindings/display/msm/edp.txt
@@ -12,11 +12,11 @@ Required properties:
- clocks: device clocks
See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
- clock-names: the following clocks are required:
- * "core_clk"
- * "iface_clk"
- * "mdp_core_clk"
- * "pixel_clk"
- * "link_clk"
+ * "core"
+ * "iface"
+ * "mdp_core"
+ * "pixel"
+ * "link"
- #clock-cells: The value should be 1.
- vdda-supply: phandle to vdda regulator device node
- lvl-vdd-supply: phandle to regulator device node which is used to supply power
@@ -41,11 +41,11 @@ Example:
interrupts = <12 0>;
power-domains = <&mmcc MDSS_GDSC>;
clock-names =
- "core_clk",
- "pixel_clk",
- "iface_clk",
- "link_clk",
- "mdp_core_clk";
+ "core",
+ "pixel",
+ "iface",
+ "link",
+ "mdp_core";
clocks =
<&mmcc MDSS_EDPAUX_CLK>,
<&mmcc MDSS_EDPPIXEL_CLK>,
diff --git a/Bindings/display/msm/hdmi.txt b/Bindings/display/msm/hdmi.txt
index 2d306f402d18..5f90a40da51b 100644
--- a/Bindings/display/msm/hdmi.txt
+++ b/Bindings/display/msm/hdmi.txt
@@ -64,9 +64,9 @@ Example:
interrupts = <GIC_SPI 79 0>;
power-domains = <&mmcc MDSS_GDSC>;
clock-names =
- "core_clk",
- "master_iface_clk",
- "slave_iface_clk";
+ "core",
+ "master_iface",
+ "slave_iface";
clocks =
<&mmcc HDMI_APP_CLK>,
<&mmcc HDMI_M_AHB_CLK>,
@@ -92,7 +92,7 @@ Example:
<0x4a00500 0x100>;
#phy-cells = <0>;
power-domains = <&mmcc MDSS_GDSC>;
- clock-names = "slave_iface_clk";
+ clock-names = "slave_iface";
clocks = <&mmcc HDMI_S_AHB_CLK>;
core-vdda-supply = <&pm8921_hdmi_mvs>;
};
diff --git a/Bindings/display/msm/mdp5.txt b/Bindings/display/msm/mdp5.txt
index 30c11ea83754..1b31977a68ba 100644
--- a/Bindings/display/msm/mdp5.txt
+++ b/Bindings/display/msm/mdp5.txt
@@ -22,16 +22,16 @@ Required properties:
Documentation/devicetree/bindings/power/power_domain.txt
- clocks: device clocks. See ../clocks/clock-bindings.txt for details.
- clock-names: the following clocks are required.
- * "iface_clk"
- * "bus_clk"
- * "vsync_clk"
+ * "iface"
+ * "bus"
+ * "vsync"
- #address-cells: number of address cells for the MDSS children. Should be 1.
- #size-cells: Should be 1.
- ranges: parent bus address space is the same as the child bus address space.
Optional properties:
- clock-names: the following clocks are optional:
- * "lut_clk"
+ * "lut"
MDP5:
Required properties:
@@ -45,10 +45,10 @@ Required properties:
through MDP block
- clocks: device clocks. See ../clocks/clock-bindings.txt for details.
- clock-names: the following clocks are required.
-- * "bus_clk"
-- * "iface_clk"
-- * "core_clk"
-- * "vsync_clk"
+- * "bus"
+- * "iface"
+- * "core"
+- * "vsync"
- ports: contains the list of output ports from MDP. These connect to interfaces
that are external to the MDP hardware, such as HDMI, DSI, EDP etc (LVDS is a
special case since it is a part of the MDP block itself).
@@ -77,7 +77,7 @@ Required properties:
Optional properties:
- clock-names: the following clocks are optional:
- * "lut_clk"
+ * "lut"
Example:
@@ -95,9 +95,9 @@ Example:
clocks = <&gcc GCC_MDSS_AHB_CLK>,
<&gcc GCC_MDSS_AXI_CLK>,
<&gcc GCC_MDSS_VSYNC_CLK>;
- clock-names = "iface_clk",
- "bus_clk",
- "vsync_clk"
+ clock-names = "iface",
+ "bus",
+ "vsync"
interrupts = <0 72 0>;
@@ -120,10 +120,10 @@ Example:
<&gcc GCC_MDSS_AXI_CLK>,
<&gcc GCC_MDSS_MDP_CLK>,
<&gcc GCC_MDSS_VSYNC_CLK>;
- clock-names = "iface_clk",
- "bus_clk",
- "core_clk",
- "vsync_clk";
+ clock-names = "iface",
+ "bus",
+ "core",
+ "vsync";
ports {
#address-cells = <1>;
diff --git a/Bindings/display/panel/orisetech,otm8009a.txt b/Bindings/display/panel/orisetech,otm8009a.txt
new file mode 100644
index 000000000000..6862028e7b2e
--- /dev/null
+++ b/Bindings/display/panel/orisetech,otm8009a.txt
@@ -0,0 +1,21 @@
+Orise Tech OTM8009A 3.97" 480x800 TFT LCD panel (MIPI-DSI video mode)
+
+The Orise Tech OTM8009A is a 3.97" 480x800 TFT LCD panel connected using
+a MIPI-DSI video interface. Its backlight is managed through the DSI link.
+
+Required properties:
+ - compatible: "orisetech,otm8009a"
+ - reg: the virtual channel number of a DSI peripheral
+
+Optional properties:
+ - reset-gpios: a GPIO spec for the reset pin (active low).
+
+Example:
+&dsi {
+ ...
+ panel@0 {
+ compatible = "orisetech,otm8009a";
+ reg = <0>;
+ reset-gpios = <&gpioh 7 GPIO_ACTIVE_LOW>;
+ };
+};
diff --git a/Bindings/display/panel/raspberrypi,7inch-touchscreen.txt b/Bindings/display/panel/raspberrypi,7inch-touchscreen.txt
new file mode 100644
index 000000000000..e9e19c059260
--- /dev/null
+++ b/Bindings/display/panel/raspberrypi,7inch-touchscreen.txt
@@ -0,0 +1,49 @@
+This binding covers the official 7" (800x480) Raspberry Pi touchscreen
+panel.
+
+This DSI panel contains:
+
+- TC358762 DSI->DPI bridge
+- Atmel microcontroller on I2C for power sequencing the DSI bridge and
+ controlling backlight
+- Touchscreen controller on I2C for touch input
+
+and this binding covers the DSI display parts but not its touch input.
+
+Required properties:
+- compatible: Must be "raspberrypi,7inch-touchscreen-panel"
+- reg: Must be "45"
+- port: See panel-common.txt
+
+Example:
+
+dsi1: dsi@7e700000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ <...>
+
+ port {
+ dsi_out_port: endpoint {
+ remote-endpoint = <&panel_dsi_port>;
+ };
+ };
+};
+
+i2c_dsi: i2c {
+ compatible = "i2c-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ gpios = <&gpio 28 0
+ &gpio 29 0>;
+
+ lcd@45 {
+ compatible = "raspberrypi,7inch-touchscreen-panel";
+ reg = <0x45>;
+
+ port {
+ panel_dsi_port: endpoint {
+ remote-endpoint = <&dsi_out_port>;
+ };
+ };
+ };
+};
diff --git a/Bindings/display/panel/samsung,s6e63j0x03.txt b/Bindings/display/panel/samsung,s6e63j0x03.txt
new file mode 100644
index 000000000000..3f1a8392af7f
--- /dev/null
+++ b/Bindings/display/panel/samsung,s6e63j0x03.txt
@@ -0,0 +1,24 @@
+Samsung S6E63J0X03 1.63" 320x320 AMOLED panel (interface: MIPI-DSI command mode)
+
+Required properties:
+ - compatible: "samsung,s6e63j0x03"
+ - reg: the virtual channel number of a DSI peripheral
+ - vdd3-supply: I/O voltage supply
+ - vci-supply: voltage supply for analog circuits
+ - reset-gpios: a GPIO spec for the reset pin (active low)
+ - te-gpios: a GPIO spec for the tearing effect synchronization signal
+ gpio pin (active high)
+
+Example:
+&dsi {
+ ...
+
+ panel@0 {
+ compatible = "samsung,s6e63j0x03";
+ reg = <0>;
+ vdd3-supply = <&ldo16_reg>;
+ vci-supply = <&ldo20_reg>;
+ reset-gpios = <&gpe0 1 GPIO_ACTIVE_LOW>;
+ te-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>;
+ };
+};
diff --git a/Bindings/display/panel/seiko,43wvf1g.txt b/Bindings/display/panel/seiko,43wvf1g.txt
new file mode 100644
index 000000000000..aae57ef36cdd
--- /dev/null
+++ b/Bindings/display/panel/seiko,43wvf1g.txt
@@ -0,0 +1,23 @@
+Seiko Instruments Inc. 4.3" WVGA (800 x RGB x 480) TFT with Touch-Panel
+
+Required properties:
+- compatible: should be "sii,43wvf1g".
+- "dvdd-supply": 3v3 digital regulator.
+- "avdd-supply": 5v analog regulator.
+
+Optional properties:
+- backlight: phandle for the backlight control.
+
+Example:
+
+ panel {
+ compatible = "sii,43wvf1g";
+ backlight = <&backlight_display>;
+ dvdd-supply = <&reg_lcd_3v3>;
+ avdd-supply = <&reg_lcd_5v>;
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&display_out>;
+ };
+ };
+ };
diff --git a/Bindings/display/panel/toshiba,lt089ac29000.txt b/Bindings/display/panel/toshiba,lt089ac29000.txt
new file mode 100644
index 000000000000..4c0caaf246c9
--- /dev/null
+++ b/Bindings/display/panel/toshiba,lt089ac29000.txt
@@ -0,0 +1,8 @@
+Toshiba 8.9" WXGA (1280x768) TFT LCD panel
+
+Required properties:
+- compatible: should be "toshiba,lt089ac29000.txt"
+- power-supply: as specified in the base binding
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/Bindings/display/rockchip/rockchip-lvds.txt b/Bindings/display/rockchip/rockchip-lvds.txt
new file mode 100644
index 000000000000..da6939efdb43
--- /dev/null
+++ b/Bindings/display/rockchip/rockchip-lvds.txt
@@ -0,0 +1,99 @@
+Rockchip RK3288 LVDS interface
+================================
+
+Required properties:
+- compatible: matching the soc type, one of
+ - "rockchip,rk3288-lvds";
+
+- reg: physical base address of the controller and length
+ of memory mapped region.
+- clocks: must include clock specifiers corresponding to entries in the
+ clock-names property.
+- clock-names: must contain "pclk_lvds"
+
+- avdd1v0-supply: regulator phandle for 1.0V analog power
+- avdd1v8-supply: regulator phandle for 1.8V analog power
+- avdd3v3-supply: regulator phandle for 3.3V analog power
+
+- rockchip,grf: phandle to the general register files syscon
+- rockchip,output: "rgb", "lvds" or "duallvds", This describes the output interface
+
+Optional properties:
+- pinctrl-names: must contain a "lcdc" entry.
+- pinctrl-0: pin control group to be used for this controller.
+
+Required nodes:
+
+The lvds has two video ports as described by
+ Documentation/devicetree/bindings/media/video-interfaces.txt
+Their connections are modeled using the OF graph bindings specified in
+ Documentation/devicetree/bindings/graph.txt.
+
+- video port 0 for the VOP input, the remote endpoint maybe vopb or vopl
+- video port 1 for either a panel or subsequent encoder
+
+the lvds panel described by
+ Documentation/devicetree/bindings/display/panel/simple-panel.txt
+
+Panel required properties:
+- ports for remote LVDS output
+
+Panel optional properties:
+- data-mapping: should be "vesa-24","jeida-24" or "jeida-18".
+This describes decribed by:
+ Documentation/devicetree/bindings/display/panel/panel-lvds.txt
+
+Example:
+
+lvds_panel: lvds-panel {
+ compatible = "auo,b101ean01";
+ enable-gpios = <&gpio7 21 GPIO_ACTIVE_HIGH>;
+ data-mapping = "jeida-24";
+
+ ports {
+ panel_in_lvds: endpoint {
+ remote-endpoint = <&lvds_out_panel>;
+ };
+ };
+};
+
+For Rockchip RK3288:
+
+ lvds: lvds@ff96c000 {
+ compatible = "rockchip,rk3288-lvds";
+ rockchip,grf = <&grf>;
+ reg = <0xff96c000 0x4000>;
+ clocks = <&cru PCLK_LVDS_PHY>;
+ clock-names = "pclk_lvds";
+ pinctrl-names = "lcdc";
+ pinctrl-0 = <&lcdc_ctl>;
+ avdd1v0-supply = <&vdd10_lcd>;
+ avdd1v8-supply = <&vcc18_lcd>;
+ avdd3v3-supply = <&vcca_33>;
+ rockchip,output = "rgb";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ lvds_in: port@0 {
+ reg = <0>;
+
+ lvds_in_vopb: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vopb_out_lvds>;
+ };
+ lvds_in_vopl: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vopl_out_lvds>;
+ };
+ };
+
+ lvds_out: port@1 {
+ reg = <1>;
+
+ lvds_out_panel: endpoint {
+ remote-endpoint = <&panel_in_lvds>;
+ };
+ };
+ };
+ };
diff --git a/Bindings/display/simple-framebuffer.txt b/Bindings/display/simple-framebuffer.txt
index 8c9e9f515c87..5a9ce511be88 100644
--- a/Bindings/display/simple-framebuffer.txt
+++ b/Bindings/display/simple-framebuffer.txt
@@ -78,7 +78,7 @@ chosen {
stdout-path = "display0";
};
-soc@01c00000 {
+soc@1c00000 {
lcdc0: lcdc@1c0c000 {
compatible = "allwinner,sun4i-a10-lcdc";
...
diff --git a/Bindings/display/sunxi/sun4i-drm.txt b/Bindings/display/sunxi/sun4i-drm.txt
index 92441086caba..50cc72ee1168 100644
--- a/Bindings/display/sunxi/sun4i-drm.txt
+++ b/Bindings/display/sunxi/sun4i-drm.txt
@@ -40,15 +40,19 @@ CEC. It is one end of the pipeline.
Required properties:
- compatible: value must be one of:
+ * allwinner,sun4i-a10-hdmi
* allwinner,sun5i-a10s-hdmi
+ * allwinner,sun6i-a31-hdmi
- reg: base address and size of memory-mapped region
- interrupts: interrupt associated to this IP
- clocks: phandles to the clocks feeding the HDMI encoder
* ahb: the HDMI interface clock
* mod: the HDMI module clock
+ * ddc: the HDMI ddc clock (A31 only)
* pll-0: the first video PLL
* pll-1: the second video PLL
- clock-names: the clock names mentioned above
+ - resets: phandle to the reset control for the HDMI encoder (A31 only)
- dmas: phandles to the DMA channels used by the HDMI encoder
* ddc-tx: The channel for DDC transmission
* ddc-rx: The channel for DDC reception
@@ -83,9 +87,11 @@ The TCON acts as a timing controller for RGB, LVDS and TV interfaces.
Required properties:
- compatible: value must be either:
+ * allwinner,sun4i-a10-tcon
* allwinner,sun5i-a13-tcon
* allwinner,sun6i-a31-tcon
* allwinner,sun6i-a31s-tcon
+ * allwinner,sun7i-a20-tcon
* allwinner,sun8i-a33-tcon
* allwinner,sun8i-v3s-tcon
- reg: base address and size of memory-mapped region
@@ -150,8 +156,10 @@ system.
Required properties:
- compatible: value must be one of:
+ * allwinner,sun4i-a10-display-backend
* allwinner,sun5i-a13-display-backend
* allwinner,sun6i-a31-display-backend
+ * allwinner,sun7i-a20-display-backend
* allwinner,sun8i-a33-display-backend
- reg: base address and size of the memory-mapped region.
- interrupts: interrupt associated to this IP
@@ -182,8 +190,10 @@ deinterlacing and color space conversion.
Required properties:
- compatible: value must be one of:
+ * allwinner,sun4i-a10-display-frontend
* allwinner,sun5i-a13-display-frontend
* allwinner,sun6i-a31-display-frontend
+ * allwinner,sun7i-a20-display-frontend
* allwinner,sun8i-a33-display-frontend
- reg: base address and size of the memory-mapped region.
- interrupts: interrupt associated to this IP
@@ -228,10 +238,12 @@ extra node.
Required properties:
- compatible: value must be one of:
+ * allwinner,sun4i-a10-display-engine
* allwinner,sun5i-a10s-display-engine
* allwinner,sun5i-a13-display-engine
* allwinner,sun6i-a31-display-engine
* allwinner,sun6i-a31s-display-engine
+ * allwinner,sun7i-a20-display-engine
* allwinner,sun8i-a33-display-engine
* allwinner,sun8i-v3s-display-engine
@@ -266,7 +278,7 @@ connector {
};
};
-hdmi: hdmi@01c16000 {
+hdmi: hdmi@1c16000 {
compatible = "allwinner,sun5i-a10s-hdmi";
reg = <0x01c16000 0x1000>;
interrupts = <58>;
@@ -305,7 +317,7 @@ hdmi: hdmi@01c16000 {
};
};
-tve0: tv-encoder@01c0a000 {
+tve0: tv-encoder@1c0a000 {
compatible = "allwinner,sun4i-a10-tv-encoder";
reg = <0x01c0a000 0x1000>;
clocks = <&ahb_gates 34>;
diff --git a/Bindings/display/tegra/nvidia,tegra20-host1x.txt b/Bindings/display/tegra/nvidia,tegra20-host1x.txt
index 74e1e8add5a1..844e0103fb0d 100644
--- a/Bindings/display/tegra/nvidia,tegra20-host1x.txt
+++ b/Bindings/display/tegra/nvidia,tegra20-host1x.txt
@@ -3,6 +3,10 @@ NVIDIA Tegra host1x
Required properties:
- compatible: "nvidia,tegra<chip>-host1x"
- reg: Physical base address and length of the controller's registers.
+ For pre-Tegra186, one entry describing the whole register area.
+ For Tegra186, one entry for each entry in reg-names:
+ "vm" - VM region assigned to Linux
+ "hypervisor" - Hypervisor region (only if Linux acts as hypervisor)
- interrupts: The interrupt outputs from the controller.
- #address-cells: The number of cells used to represent physical base addresses
in the host1x address space. Should be 1.
diff --git a/Bindings/dma/qcom_hidma_mgmt.txt b/Bindings/dma/qcom_hidma_mgmt.txt
index 55492c264d17..b3408cc57be6 100644
--- a/Bindings/dma/qcom_hidma_mgmt.txt
+++ b/Bindings/dma/qcom_hidma_mgmt.txt
@@ -73,7 +73,7 @@ Hypervisor OS configuration:
max-read-transactions = <31>;
channel-reset-timeout-cycles = <0x500>;
- hidma_24: dma-controller@0x5c050000 {
+ hidma_24: dma-controller@5c050000 {
compatible = "qcom,hidma-1.0";
reg = <0 0x5c050000 0x0 0x1000>,
<0 0x5c0b0000 0x0 0x1000>;
@@ -85,7 +85,7 @@ Hypervisor OS configuration:
Guest OS configuration:
- hidma_24: dma-controller@0x5c050000 {
+ hidma_24: dma-controller@5c050000 {
compatible = "qcom,hidma-1.0";
reg = <0 0x5c050000 0x0 0x1000>,
<0 0x5c0b0000 0x0 0x1000>;
diff --git a/Bindings/dma/renesas,usb-dmac.txt b/Bindings/dma/renesas,usb-dmac.txt
index 1be6941ac1e5..f3d1f151ba80 100644
--- a/Bindings/dma/renesas,usb-dmac.txt
+++ b/Bindings/dma/renesas,usb-dmac.txt
@@ -3,6 +3,8 @@
Required Properties:
-compatible: "renesas,<soctype>-usb-dmac", "renesas,usb-dmac" as fallback.
Examples with soctypes are:
+ - "renesas,r8a7743-usb-dmac" (RZ/G1M)
+ - "renesas,r8a7745-usb-dmac" (RZ/G1E)
- "renesas,r8a7790-usb-dmac" (R-Car H2)
- "renesas,r8a7791-usb-dmac" (R-Car M2-W)
- "renesas,r8a7793-usb-dmac" (R-Car M2-N)
diff --git a/Bindings/dma/sprd-dma.txt b/Bindings/dma/sprd-dma.txt
new file mode 100644
index 000000000000..7a10fea2e51b
--- /dev/null
+++ b/Bindings/dma/sprd-dma.txt
@@ -0,0 +1,41 @@
+* Spreadtrum DMA controller
+
+This binding follows the generic DMA bindings defined in dma.txt.
+
+Required properties:
+- compatible: Should be "sprd,sc9860-dma".
+- reg: Should contain DMA registers location and length.
+- interrupts: Should contain one interrupt shared by all channel.
+- #dma-cells: must be <1>. Used to represent the number of integer
+ cells in the dmas property of client device.
+- #dma-channels : Number of DMA channels supported. Should be 32.
+- clock-names: Should contain the clock of the DMA controller.
+- clocks: Should contain a clock specifier for each entry in clock-names.
+
+Example:
+
+Controller:
+apdma: dma-controller@20100000 {
+ compatible = "sprd,sc9860-dma";
+ reg = <0x20100000 0x4000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ #dma-channels = <32>;
+ clock-names = "enable";
+ clocks = <&clk_ap_ahb_gates 5>;
+};
+
+
+Client:
+DMA clients connected to the Spreadtrum DMA controller must use the format
+described in the dma.txt file, using a two-cell specifier for each channel.
+The two cells in order are:
+1. A phandle pointing to the DMA controller.
+2. The channel id.
+
+spi0: spi@70a00000{
+ ...
+ dma-names = "rx_chn", "tx_chn";
+ dmas = <&apdma 11>, <&apdma 12>;
+ ...
+};
diff --git a/Bindings/dma/stm32-dma.txt b/Bindings/dma/stm32-dma.txt
index 4408af693d0c..0b55718bf889 100644
--- a/Bindings/dma/stm32-dma.txt
+++ b/Bindings/dma/stm32-dma.txt
@@ -13,6 +13,7 @@ Required properties:
- #dma-cells : Must be <4>. See DMA client paragraph for more details.
Optional properties:
+- dma-requests : Number of DMA requests supported.
- resets: Reference to a reset controller asserting the DMA controller
- st,mem2mem: boolean; if defined, it indicates that the controller supports
memory-to-memory transfer
@@ -34,12 +35,13 @@ Example:
#dma-cells = <4>;
st,mem2mem;
resets = <&rcc 150>;
+ dma-requests = <8>;
};
* DMA client
DMA clients connected to the STM32 DMA controller must use the format
-described in the dma.txt file, using a five-cell specifier for each
+described in the dma.txt file, using a four-cell specifier for each
channel: a phandle to the DMA controller plus the following four integer cells:
1. The channel id
@@ -71,7 +73,7 @@ channel: a phandle to the DMA controller plus the following four integer cells:
Example:
usart1: serial@40011000 {
- compatible = "st,stm32-usart", "st,stm32-uart";
+ compatible = "st,stm32-uart";
reg = <0x40011000 0x400>;
interrupts = <37>;
clocks = <&clk_pclk2>;
diff --git a/Bindings/dma/stm32-dmamux.txt b/Bindings/dma/stm32-dmamux.txt
new file mode 100644
index 000000000000..1b893b235507
--- /dev/null
+++ b/Bindings/dma/stm32-dmamux.txt
@@ -0,0 +1,84 @@
+STM32 DMA MUX (DMA request router)
+
+Required properties:
+- compatible: "st,stm32h7-dmamux"
+- reg: Memory map for accessing module
+- #dma-cells: Should be set to <3>.
+ First parameter is request line number.
+ Second is DMA channel configuration
+ Third is Fifo threshold
+ For more details about the three cells, please see
+ stm32-dma.txt documentation binding file
+- dma-masters: Phandle pointing to the DMA controllers.
+ Several controllers are allowed. Only "st,stm32-dma" DMA
+ compatible are supported.
+
+Optional properties:
+- dma-channels : Number of DMA requests supported.
+- dma-requests : Number of DMAMUX requests supported.
+- resets: Reference to a reset controller asserting the DMA controller
+- clocks: Input clock of the DMAMUX instance.
+
+Example:
+
+/* DMA controller 1 */
+dma1: dma-controller@40020000 {
+ compatible = "st,stm32-dma";
+ reg = <0x40020000 0x400>;
+ interrupts = <11>,
+ <12>,
+ <13>,
+ <14>,
+ <15>,
+ <16>,
+ <17>,
+ <47>;
+ clocks = <&timer_clk>;
+ #dma-cells = <4>;
+ st,mem2mem;
+ resets = <&rcc 150>;
+ dma-channels = <8>;
+ dma-requests = <8>;
+};
+
+/* DMA controller 1 */
+dma2: dma@40020400 {
+ compatible = "st,stm32-dma";
+ reg = <0x40020400 0x400>;
+ interrupts = <56>,
+ <57>,
+ <58>,
+ <59>,
+ <60>,
+ <68>,
+ <69>,
+ <70>;
+ clocks = <&timer_clk>;
+ #dma-cells = <4>;
+ st,mem2mem;
+ resets = <&rcc 150>;
+ dma-channels = <8>;
+ dma-requests = <8>;
+};
+
+/* DMA mux */
+dmamux1: dma-router@40020800 {
+ compatible = "st,stm32h7-dmamux";
+ reg = <0x40020800 0x3c>;
+ #dma-cells = <3>;
+ dma-requests = <128>;
+ dma-channels = <16>;
+ dma-masters = <&dma1 &dma2>;
+ clocks = <&timer_clk>;
+};
+
+/* DMA client */
+usart1: serial@40011000 {
+ compatible = "st,stm32-usart", "st,stm32-uart";
+ reg = <0x40011000 0x400>;
+ interrupts = <37>;
+ clocks = <&timer_clk>;
+ dmas = <&dmamux1 41 0x414 0>,
+ <&dmamux1 42 0x414 0>;
+ dma-names = "rx", "tx";
+};
diff --git a/Bindings/dma/stm32-mdma.txt b/Bindings/dma/stm32-mdma.txt
new file mode 100644
index 000000000000..d18772d6bc65
--- /dev/null
+++ b/Bindings/dma/stm32-mdma.txt
@@ -0,0 +1,94 @@
+* STMicroelectronics STM32 MDMA controller
+
+The STM32 MDMA is a general-purpose direct memory access controller capable of
+supporting 64 independent DMA channels with 256 HW requests.
+
+Required properties:
+- compatible: Should be "st,stm32h7-mdma"
+- reg: Should contain MDMA registers location and length. This should include
+ all of the per-channel registers.
+- interrupts: Should contain the MDMA interrupt.
+- clocks: Should contain the input clock of the DMA instance.
+- resets: Reference to a reset controller asserting the DMA controller.
+- #dma-cells : Must be <5>. See DMA client paragraph for more details.
+
+Optional properties:
+- dma-channels: Number of DMA channels supported by the controller.
+- dma-requests: Number of DMA request signals supported by the controller.
+- st,ahb-addr-masks: Array of u32 mask to list memory devices addressed via
+ AHB bus.
+
+Example:
+
+ mdma1: dma@52000000 {
+ compatible = "st,stm32h7-mdma";
+ reg = <0x52000000 0x1000>;
+ interrupts = <122>;
+ clocks = <&timer_clk>;
+ resets = <&rcc 992>;
+ #dma-cells = <5>;
+ dma-channels = <16>;
+ dma-requests = <32>;
+ st,ahb-addr-masks = <0x20000000>, <0x00000000>;
+ };
+
+* DMA client
+
+DMA clients connected to the STM32 MDMA controller must use the format
+described in the dma.txt file, using a five-cell specifier for each channel:
+a phandle to the MDMA controller plus the following five integer cells:
+
+1. The request line number
+2. The priority level
+ 0x00: Low
+ 0x01: Medium
+ 0x10: High
+ 0x11: Very high
+3. A 32bit mask specifying the DMA channel configuration
+ -bit 0-1: Source increment mode
+ 0x00: Source address pointer is fixed
+ 0x10: Source address pointer is incremented after each data transfer
+ 0x11: Source address pointer is decremented after each data transfer
+ -bit 2-3: Destination increment mode
+ 0x00: Destination address pointer is fixed
+ 0x10: Destination address pointer is incremented after each data
+ transfer
+ 0x11: Destination address pointer is decremented after each data
+ transfer
+ -bit 8-9: Source increment offset size
+ 0x00: byte (8bit)
+ 0x01: half-word (16bit)
+ 0x10: word (32bit)
+ 0x11: double-word (64bit)
+ -bit 10-11: Destination increment offset size
+ 0x00: byte (8bit)
+ 0x01: half-word (16bit)
+ 0x10: word (32bit)
+ 0x11: double-word (64bit)
+-bit 25-18: The number of bytes to be transferred in a single transfer
+ (min = 1 byte, max = 128 bytes)
+-bit 29:28: Trigger Mode
+ 0x00: Each MDMA request triggers a buffer transfer (max 128 bytes)
+ 0x01: Each MDMA request triggers a block transfer (max 64K bytes)
+ 0x10: Each MDMA request triggers a repeated block transfer
+ 0x11: Each MDMA request triggers a linked list transfer
+4. A 32bit value specifying the register to be used to acknowledge the request
+ if no HW ack signal is used by the MDMA client
+5. A 32bit mask specifying the value to be written to acknowledge the request
+ if no HW ack signal is used by the MDMA client
+
+Example:
+
+ i2c4: i2c@5c002000 {
+ compatible = "st,stm32f7-i2c";
+ reg = <0x5c002000 0x400>;
+ interrupts = <95>,
+ <96>;
+ clocks = <&timer_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&mdma1 36 0x0 0x40008 0x0 0x0>,
+ <&mdma1 37 0x0 0x40002 0x0 0x0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
diff --git a/Bindings/dma/sun4i-dma.txt b/Bindings/dma/sun4i-dma.txt
index 3b484380c56a..8ad556aca70b 100644
--- a/Bindings/dma/sun4i-dma.txt
+++ b/Bindings/dma/sun4i-dma.txt
@@ -12,7 +12,7 @@ Required properties:
second cell holding the request line number.
Example:
- dma: dma-controller@01c02000 {
+ dma: dma-controller@1c02000 {
compatible = "allwinner,sun4i-a10-dma";
reg = <0x01c02000 0x1000>;
interrupts = <27>;
@@ -32,7 +32,7 @@ The three cells in order are:
3. The port ID as specified in the datasheet
Example:
- spi2: spi@01c17000 {
+ spi2: spi@1c17000 {
compatible = "allwinner,sun4i-a10-spi";
reg = <0x01c17000 0x1000>;
interrupts = <0 12 4>;
diff --git a/Bindings/dma/sun6i-dma.txt b/Bindings/dma/sun6i-dma.txt
index 98fbe1a5c6dd..7fccc20d8331 100644
--- a/Bindings/dma/sun6i-dma.txt
+++ b/Bindings/dma/sun6i-dma.txt
@@ -18,7 +18,7 @@ Required properties:
- #dma-cells : Should be 1, a single cell holding a line request number
Example:
- dma: dma-controller@01c02000 {
+ dma: dma-controller@1c02000 {
compatible = "allwinner,sun6i-a31-dma";
reg = <0x01c02000 0x1000>;
interrupts = <0 50 4>;
@@ -27,6 +27,32 @@ Example:
#dma-cells = <1>;
};
+------------------------------------------------------------------------------
+For A64 DMA controller:
+
+Required properties:
+- compatible: "allwinner,sun50i-a64-dma"
+- dma-channels: Number of DMA channels supported by the controller.
+ Refer to Documentation/devicetree/bindings/dma/dma.txt
+- all properties above, i.e. reg, interrupts, clocks, resets and #dma-cells
+
+Optional properties:
+- dma-requests: Number of DMA request signals supported by the controller.
+ Refer to Documentation/devicetree/bindings/dma/dma.txt
+
+Example:
+ dma: dma-controller@1c02000 {
+ compatible = "allwinner,sun50i-a64-dma";
+ reg = <0x01c02000 0x1000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_DMA>;
+ dma-channels = <8>;
+ dma-requests = <27>;
+ resets = <&ccu RST_BUS_DMA>;
+ #dma-cells = <1>;
+ };
+------------------------------------------------------------------------------
+
Clients:
DMA clients connected to the A31 DMA controller must use the format
@@ -38,7 +64,7 @@ The two cells in order are:
2. The port ID as specified in the datasheet
Example:
-spi2: spi@01c6a000 {
+spi2: spi@1c6a000 {
compatible = "allwinner,sun6i-a31-spi";
reg = <0x01c6a000 0x1000>;
interrupts = <0 67 4>;
diff --git a/Bindings/dma/ti-edma.txt b/Bindings/dma/ti-edma.txt
index 41f0c1a07c56..66026dcf53e1 100644
--- a/Bindings/dma/ti-edma.txt
+++ b/Bindings/dma/ti-edma.txt
@@ -142,7 +142,7 @@ mcasp0: mcasp@48038000 {
};
2.
-edma1: edma@02728000 {
+edma1: edma@2728000 {
compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc";
reg = <0x02728000 0x8000>;
reg-names = "edma3_cc";
@@ -165,13 +165,13 @@ edma1: edma@02728000 {
power-domains = <&k2g_pds 0x4f>;
};
-edma1_tptc0: tptc@027b0000 {
+edma1_tptc0: tptc@27b0000 {
compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc";
reg = <0x027b0000 0x400>;
power-domains = <&k2g_pds 0x4f>;
};
-edma1_tptc1: tptc@027b8000 {
+edma1_tptc1: tptc@27b8000 {
compatible = "ti, k2g-edma3-tptc", "ti,edma3-tptc";
reg = <0x027b8000 0x400>;
power-domains = <&k2g_pds 0x4f>;
diff --git a/Bindings/dma/zxdma.txt b/Bindings/dma/zxdma.txt
index 3207ceb04d0b..0ab80f69e566 100644
--- a/Bindings/dma/zxdma.txt
+++ b/Bindings/dma/zxdma.txt
@@ -13,7 +13,7 @@ Required properties:
Example:
Controller:
- dma: dma-controller@0x09c00000{
+ dma: dma-controller@09c00000{
compatible = "zte,zx296702-dma";
reg = <0x09c00000 0x1000>;
clocks = <&topclk ZX296702_DMA_ACLK>;
@@ -26,7 +26,7 @@ Controller:
Client:
Use specific request line passing from dmax
For example, spdif0 tx channel request line is 4
- spdif0: spdif0@0b004000 {
+ spdif0: spdif0@b004000 {
#sound-dai-cells = <0>;
compatible = "zte,zx296702-spdif";
reg = <0x0b004000 0x1000>;
diff --git a/Bindings/eeprom/at25.txt b/Bindings/eeprom/at25.txt
index 1d3447165c37..e823d90b802f 100644
--- a/Bindings/eeprom/at25.txt
+++ b/Bindings/eeprom/at25.txt
@@ -1,7 +1,12 @@
EEPROMs (SPI) compatible with Atmel at25.
Required properties:
-- compatible : "atmel,at25".
+- compatible : Should be "<vendor>,<type>", and generic value "atmel,at25".
+ Example "<vendor>,<type>" values:
+ "microchip,25lc040"
+ "st,m95m02"
+ "st,m95256"
+
- reg : chip select number
- spi-max-frequency : max spi frequency to use
- pagesize : size of the eeprom page
@@ -13,7 +18,7 @@ Optional properties:
- spi-cpol : SPI inverse clock polarity, as per spi-bus bindings.
- read-only : this parameter-less property disables writes to the eeprom
-Obsolete legacy properties are can be used in place of "size", "pagesize",
+Obsolete legacy properties can be used in place of "size", "pagesize",
"address-width", and "read-only":
- at25,byte-len : total eeprom size in bytes
- at25,addr-mode : addr-mode flags, as defined in include/linux/spi/eeprom.h
@@ -22,8 +27,8 @@ Obsolete legacy properties are can be used in place of "size", "pagesize",
Additional compatible properties are also allowed.
Example:
- at25@0 {
- compatible = "atmel,at25", "st,m95256";
+ eeprom@0 {
+ compatible = "st,m95256", "atmel,at25";
reg = <0>
spi-max-frequency = <5000000>;
spi-cpha;
diff --git a/Bindings/eeprom/eeprom.txt b/Bindings/eeprom/eeprom.txt
index afc04589eadf..27f2bc15298a 100644
--- a/Bindings/eeprom/eeprom.txt
+++ b/Bindings/eeprom/eeprom.txt
@@ -36,6 +36,8 @@ Optional properties:
- read-only: this parameterless property disables writes to the eeprom
+ - size: total eeprom size in bytes
+
Example:
eeprom@52 {
diff --git a/Bindings/firmware/nvidia,tegra186-bpmp.txt b/Bindings/firmware/nvidia,tegra186-bpmp.txt
index e821e16ad65b..0c10802c8327 100644
--- a/Bindings/firmware/nvidia,tegra186-bpmp.txt
+++ b/Bindings/firmware/nvidia,tegra186-bpmp.txt
@@ -66,7 +66,7 @@ See ".../sram/sram.txt" for the bindings.
Example:
-hsp_top0: hsp@03c00000 {
+hsp_top0: hsp@3c00000 {
...
#mbox-cells = <2>;
};
diff --git a/Bindings/firmware/qcom,scm.txt b/Bindings/firmware/qcom,scm.txt
index 20f26fbce875..7b40054be0d8 100644
--- a/Bindings/firmware/qcom,scm.txt
+++ b/Bindings/firmware/qcom,scm.txt
@@ -18,6 +18,8 @@ Required properties:
* Core, iface, and bus clocks required for "qcom,scm"
- clock-names: Must contain "core" for the core clock, "iface" for the interface
clock and "bus" for the bus clock per the requirements of the compatible.
+- qcom,dload-mode: phandle to the TCSR hardware block and offset of the
+ download mode control register (optional)
Example for MSM8916:
diff --git a/Bindings/gpio/gpio-altera.txt b/Bindings/gpio/gpio-altera.txt
index 826a7208ca93..146e554b3c67 100644
--- a/Bindings/gpio/gpio-altera.txt
+++ b/Bindings/gpio/gpio-altera.txt
@@ -30,7 +30,7 @@ Optional properties:
Example:
-gpio_altr: gpio@0xff200000 {
+gpio_altr: gpio@ff200000 {
compatible = "altr,pio-1.0";
reg = <0xff200000 0x10>;
interrupts = <0 45 4>;
diff --git a/Bindings/gpio/gpio-dsp-keystone.txt b/Bindings/gpio/gpio-dsp-keystone.txt
index 6c7e6c7302f5..0423699d74c7 100644
--- a/Bindings/gpio/gpio-dsp-keystone.txt
+++ b/Bindings/gpio/gpio-dsp-keystone.txt
@@ -25,7 +25,7 @@ Please refer to gpio.txt in this directory for details of the common GPIO
bindings used by client devices.
Example:
- dspgpio0: keystone_dsp_gpio@02620240 {
+ dspgpio0: keystone_dsp_gpio@2620240 {
compatible = "ti,keystone-dsp-gpio";
ti,syscon-dev = <&devctrl 0x240>;
gpio-controller;
diff --git a/Bindings/gpio/gpio-max3191x.txt b/Bindings/gpio/gpio-max3191x.txt
new file mode 100644
index 000000000000..b3a6444b8f45
--- /dev/null
+++ b/Bindings/gpio/gpio-max3191x.txt
@@ -0,0 +1,59 @@
+GPIO driver for Maxim MAX3191x industrial serializer
+
+Required properties:
+ - compatible: Must be one of:
+ "maxim,max31910"
+ "maxim,max31911"
+ "maxim,max31912"
+ "maxim,max31913"
+ "maxim,max31953"
+ "maxim,max31963"
+ - reg: Chip select number.
+ - gpio-controller: Marks the device node as a GPIO controller.
+ - #gpio-cells: Should be two. For consumer use see gpio.txt.
+
+Optional properties:
+ - #daisy-chained-devices:
+ Number of chips in the daisy-chain (default is 1).
+ - maxim,modesel-gpios: GPIO pins to configure modesel of each chip.
+ The number of GPIOs must equal "#daisy-chained-devices"
+ (if each chip is driven by a separate pin) or 1
+ (if all chips are wired to the same pin).
+ - maxim,fault-gpios: GPIO pins to read fault of each chip.
+ The number of GPIOs must equal "#daisy-chained-devices"
+ or 1.
+ - maxim,db0-gpios: GPIO pins to configure debounce of each chip.
+ The number of GPIOs must equal "#daisy-chained-devices"
+ or 1.
+ - maxim,db1-gpios: GPIO pins to configure debounce of each chip.
+ The number of GPIOs must equal "maxim,db0-gpios".
+ - maxim,modesel-8bit: Boolean whether the modesel pin of the chips is
+ pulled high (8-bit mode). Use this if the modesel pin
+ is hardwired and consequently "maxim,modesel-gpios"
+ cannot be specified. By default if neither this nor
+ "maxim,modesel-gpios" is given, the driver assumes
+ that modesel is pulled low (16-bit mode).
+ - maxim,ignore-undervoltage:
+ Boolean whether to ignore undervoltage alarms signaled
+ by the "maxim,fault-gpios" or by the status byte
+ (in 16-bit mode). Use this if the chips are powered
+ through 5VOUT instead of VCC24V, in which case they
+ will constantly signal undervoltage.
+
+For other required and optional properties of SPI slave nodes please refer to
+../spi/spi-bus.txt.
+
+Example:
+ gpio@0 {
+ compatible = "maxim,max31913";
+ reg = <0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ maxim,modesel-gpios = <&gpio2 23>;
+ maxim,fault-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>;
+ maxim,db0-gpios = <&gpio2 25>;
+ maxim,db1-gpios = <&gpio2 26>;
+
+ spi-max-frequency = <25000000>;
+ };
diff --git a/Bindings/gpio/gpio-pca953x.txt b/Bindings/gpio/gpio-pca953x.txt
index 7f57271df2bc..0d0158728f89 100644
--- a/Bindings/gpio/gpio-pca953x.txt
+++ b/Bindings/gpio/gpio-pca953x.txt
@@ -27,7 +27,7 @@ Required properties:
ti,tca6424
ti,tca9539
ti,tca9554
- onsemi,pca9654
+ onnn,pca9654
exar,xra1202
Optional properties:
diff --git a/Bindings/gpio/gpio-tz1090-pdc.txt b/Bindings/gpio/gpio-tz1090-pdc.txt
index 1fd98ffa8cb7..528f5ef5a893 100644
--- a/Bindings/gpio/gpio-tz1090-pdc.txt
+++ b/Bindings/gpio/gpio-tz1090-pdc.txt
@@ -30,7 +30,7 @@ Optional properties:
Example:
- pdc_gpios: gpio-controller@02006500 {
+ pdc_gpios: gpio-controller@2006500 {
gpio-controller;
#gpio-cells = <2>;
diff --git a/Bindings/gpio/gpio-tz1090.txt b/Bindings/gpio/gpio-tz1090.txt
index 174cdf309170..b05a90e0ab29 100644
--- a/Bindings/gpio/gpio-tz1090.txt
+++ b/Bindings/gpio/gpio-tz1090.txt
@@ -59,7 +59,7 @@ Required properties:
Example:
- gpios: gpio-controller@02005800 {
+ gpios: gpio-controller@2005800 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "img,tz1090-gpio";
diff --git a/Bindings/gpio/gpio-uniphier.txt b/Bindings/gpio/gpio-uniphier.txt
new file mode 100644
index 000000000000..fed9158dd913
--- /dev/null
+++ b/Bindings/gpio/gpio-uniphier.txt
@@ -0,0 +1,52 @@
+UniPhier GPIO controller
+
+Required properties:
+- compatible: Should be "socionext,uniphier-gpio".
+- reg: Specifies offset and length of the register set for the device.
+- gpio-controller: Marks the device node as a GPIO controller.
+- #gpio-cells: Should be 2. The first cell is the pin number and the second
+ cell is used to specify optional parameters.
+- interrupt-parent: Specifies the parent interrupt controller.
+- interrupt-controller: Marks the device node as an interrupt controller.
+- #interrupt-cells: Should be 2. The first cell defines the interrupt number.
+ The second cell bits[3:0] is used to specify trigger type as follows:
+ 1 = low-to-high edge triggered
+ 2 = high-to-low edge triggered
+ 4 = active high level-sensitive
+ 8 = active low level-sensitive
+ Valid combinations are 1, 2, 3, 4, 8.
+- ngpios: Specifies the number of GPIO lines.
+- gpio-ranges: Mapping to pin controller pins (as described in gpio.txt)
+- socionext,interrupt-ranges: Specifies an interrupt number mapping between
+ this GPIO controller and its interrupt parent, in the form of arbitrary
+ number of <child-interrupt-base parent-interrupt-base length> triplets.
+
+Optional properties:
+- gpio-ranges-group-names: Used for named gpio ranges (as described in gpio.txt)
+
+Example:
+ gpio: gpio@55000000 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000000 0x200>;
+ interrupt-parent = <&aidet>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 0 0>;
+ gpio-ranges-group-names = "gpio_range";
+ ngpios = <248>;
+ socionext,interrupt-ranges = <0 48 16>, <16 154 5>, <21 217 3>;
+ };
+
+Consumer Example:
+
+ sdhci0_pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio UNIPHIER_GPIO_PORT(29, 4) GPIO_ACTIVE_LOW>;
+ };
+
+Please note UNIPHIER_GPIO_PORT(29, 4) represents PORT294 in the SoC document.
+Unfortunately, only the one's place is octal in the port numbering. (That is,
+PORT 8, 9, 18, 19, 28, 29, ... are missing.) UNIPHIER_GPIO_PORT() is a helper
+macro to calculate 29 * 8 + 4.
diff --git a/Bindings/gpio/renesas,gpio-rcar.txt b/Bindings/gpio/renesas,gpio-rcar.txt
index 51c86f69995e..a7ac460ad657 100644
--- a/Bindings/gpio/renesas,gpio-rcar.txt
+++ b/Bindings/gpio/renesas,gpio-rcar.txt
@@ -14,6 +14,8 @@ Required Properties:
- "renesas,gpio-r8a7794": for R8A7794 (R-Car E2) compatible GPIO controller.
- "renesas,gpio-r8a7795": for R8A7795 (R-Car H3) compatible GPIO controller.
- "renesas,gpio-r8a7796": for R8A7796 (R-Car M3-W) compatible GPIO controller.
+ - "renesas,gpio-r8a77970": for R8A77970 (R-Car V3M) compatible GPIO controller.
+ - "renesas,gpio-r8a77995": for R8A77995 (R-Car D3) compatible GPIO controller.
- "renesas,rcar-gen1-gpio": for a generic R-Car Gen1 GPIO controller.
- "renesas,rcar-gen2-gpio": for a generic R-Car Gen2 or RZ/G1 GPIO controller.
- "renesas,rcar-gen3-gpio": for a generic R-Car Gen3 GPIO controller.
diff --git a/Bindings/gpio/snps-dwapb-gpio.txt b/Bindings/gpio/snps-dwapb-gpio.txt
index 4d6c8cdc8586..4a75da7051bd 100644
--- a/Bindings/gpio/snps-dwapb-gpio.txt
+++ b/Bindings/gpio/snps-dwapb-gpio.txt
@@ -29,6 +29,7 @@ controller.
- interrupts : The interrupt to the parent controller raised when GPIOs
generate the interrupts.
- snps,nr-gpios : The number of pins in the port, a single cell.
+- resets : Reset line for the controller.
Example:
diff --git a/Bindings/gpu/arm,mali-utgard.txt b/Bindings/gpu/arm,mali-utgard.txt
index b4ebd56d03f3..c6814d7cc2b2 100644
--- a/Bindings/gpu/arm,mali-utgard.txt
+++ b/Bindings/gpu/arm,mali-utgard.txt
@@ -13,6 +13,10 @@ Required properties:
+ allwinner,sun50i-h5-mali
+ amlogic,meson-gxbb-mali
+ amlogic,meson-gxl-mali
+ + rockchip,rk3036-mali
+ + rockchip,rk3066-mali
+ + rockchip,rk3188-mali
+ + rockchip,rk3228-mali
+ stericsson,db8500-mali
- reg: Physical base address and length of the GPU registers
@@ -40,10 +44,18 @@ Optional properties:
Memory region to allocate from, as defined in
Documentation/devicetree/bindi/reserved-memory/reserved-memory.txt
+ - mali-supply:
+ Phandle to regulator for the Mali device, as defined in
+ Documentation/devicetree/bindings/regulator/regulator.txt for details.
+
- operating-points-v2:
Operating Points for the GPU, as defined in
Documentation/devicetree/bindings/opp/opp.txt
+ - power-domains:
+ A power domain consumer specifier as defined in
+ Documentation/devicetree/bindings/power/power_domain.txt
+
Vendor-specific bindings
------------------------
@@ -63,6 +75,10 @@ to specify one more vendor-specific compatible, among:
Required properties:
* resets: phandle to the reset line for the GPU
+ - Rockchip variants:
+ Required properties:
+ * resets: phandle to the reset line for the GPU
+
- stericsson,db8500-mali
Required properties:
* interrupt-names and interrupts:
diff --git a/Bindings/hsi/omap-ssi.txt b/Bindings/hsi/omap-ssi.txt
index b8eca3c7810d..955e335e7e56 100644
--- a/Bindings/hsi/omap-ssi.txt
+++ b/Bindings/hsi/omap-ssi.txt
@@ -1,10 +1,12 @@
OMAP SSI controller bindings
-OMAP Synchronous Serial Interface (SSI) controller implements a legacy
-variant of MIPI's High Speed Synchronous Serial Interface (HSI).
+OMAP3's Synchronous Serial Interface (SSI) controller implements a
+legacy variant of MIPI's High Speed Synchronous Serial Interface (HSI),
+while the controller found inside OMAP4 is supposed to be fully compliant
+with the HSI standard.
Required properties:
-- compatible: Should include "ti,omap3-ssi".
+- compatible: Should include "ti,omap3-ssi" or "ti,omap4-hsi"
- reg-names: Contains the values "sys" and "gdd" (in this order).
- reg: Contains a matching register specifier for each entry
in reg-names.
@@ -27,6 +29,7 @@ Each port is represented as a sub-node of the ti,omap3-ssi device.
Required Port sub-node properties:
- compatible: Should be set to the following value
ti,omap3-ssi-port (applicable to OMAP34xx devices)
+ ti,omap4-hsi-port (applicable to OMAP44xx devices)
- reg-names: Contains the values "tx" and "rx" (in this order).
- reg: Contains a matching register specifier for each entry
in reg-names.
@@ -38,6 +41,10 @@ Required Port sub-node properties:
property. If it's missing the port will not be
enabled.
+Optional properties:
+- ti,hwmods: Shall contain TI interconnect module name if needed
+ by the SoC
+
Example for Nokia N900:
ssi-controller@48058000 {
diff --git a/Bindings/gpio/gpio-fan.txt b/Bindings/hwmon/gpio-fan.txt
index 439a7430fc68..439a7430fc68 100644
--- a/Bindings/gpio/gpio-fan.txt
+++ b/Bindings/hwmon/gpio-fan.txt
diff --git a/Bindings/hwmon/jc42.txt b/Bindings/hwmon/jc42.txt
index 07a250498fbb..f569db58f64a 100644
--- a/Bindings/hwmon/jc42.txt
+++ b/Bindings/hwmon/jc42.txt
@@ -34,6 +34,10 @@ Required properties:
- reg: I2C address
+Optional properties:
+- smbus-timeout-disable: When set, the smbus timeout function will be disabled.
+ This is not supported on all chips.
+
Example:
temp-sensor@1a {
diff --git a/Bindings/hwmon/max1619.txt b/Bindings/hwmon/max1619.txt
new file mode 100644
index 000000000000..c70dbbe1e56f
--- /dev/null
+++ b/Bindings/hwmon/max1619.txt
@@ -0,0 +1,12 @@
+Bindings for MAX1619 Temperature Sensor
+
+Required properties:
+- compatible : "maxim,max1619"
+- reg : I2C address, one of 0x18, 0x19, 0x1a, 0x29, 0x2a, 0x2b, 0x4c, or
+ 0x4d, 0x4e
+
+Example:
+ temp@4c {
+ compatible = "maxim,max1619";
+ reg = <0x4c>;
+ };
diff --git a/Bindings/hwmon/max31785.txt b/Bindings/hwmon/max31785.txt
new file mode 100644
index 000000000000..106e08c56aaa
--- /dev/null
+++ b/Bindings/hwmon/max31785.txt
@@ -0,0 +1,22 @@
+Bindings for the Maxim MAX31785 Intelligent Fan Controller
+==========================================================
+
+Reference:
+
+https://datasheets.maximintegrated.com/en/ds/MAX31785.pdf
+
+The Maxim MAX31785 is a PMBus device providing closed-loop, multi-channel fan
+management with temperature and remote voltage sensing. Various fan control
+features are provided, including PWM frequency control, temperature hysteresis,
+dual tachometer measurements, and fan health monitoring.
+
+Required properties:
+- compatible : One of "maxim,max31785" or "maxim,max31785a"
+- reg : I2C address, one of 0x52, 0x53, 0x54, 0x55.
+
+Example:
+
+ fans@52 {
+ compatible = "maxim,max31785";
+ reg = <0x52>;
+ };
diff --git a/Bindings/i2c/i2c-aspeed.txt b/Bindings/i2c/i2c-aspeed.txt
index bd6480b19535..e7106bfc1f13 100644
--- a/Bindings/i2c/i2c-aspeed.txt
+++ b/Bindings/i2c/i2c-aspeed.txt
@@ -7,7 +7,9 @@ Required Properties:
- compatible : should be "aspeed,ast2400-i2c-bus"
or "aspeed,ast2500-i2c-bus"
- clocks : root clock of bus, should reference the APB
- clock
+ clock in the second cell
+- resets : phandle to reset controller with the reset number in
+ the second cell
- interrupts : interrupt number
- interrupt-parent : interrupt controller for bus, should reference a
aspeed,ast2400-i2c-ic or aspeed,ast2500-i2c-ic
@@ -40,7 +42,8 @@ i2c {
#interrupt-cells = <1>;
reg = <0x40 0x40>;
compatible = "aspeed,ast2400-i2c-bus";
- clocks = <&clk_apb>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
bus-frequency = <100000>;
interrupts = <0>;
interrupt-parent = <&i2c_ic>;
diff --git a/Bindings/i2c/i2c-axxia.txt b/Bindings/i2c/i2c-axxia.txt
index 2296d782b4c2..7d53a2b79553 100644
--- a/Bindings/i2c/i2c-axxia.txt
+++ b/Bindings/i2c/i2c-axxia.txt
@@ -17,7 +17,7 @@ Optional properties :
Example :
-i2c@02010084000 {
+i2c@2010084000 {
compatible = "lsi,api2c";
device_type = "i2c";
#address-cells = <1>;
diff --git a/Bindings/i2c/i2c-davinci.txt b/Bindings/i2c/i2c-davinci.txt
index 5b123e0e4cc2..64e6e656c345 100644
--- a/Bindings/i2c/i2c-davinci.txt
+++ b/Bindings/i2c/i2c-davinci.txt
@@ -6,6 +6,18 @@ davinci/keystone i2c interface contains.
Required properties:
- compatible: "ti,davinci-i2c" or "ti,keystone-i2c";
- reg : Offset and length of the register set for the device
+- clocks: I2C functional clock phandle.
+ For 66AK2G this property should be set per binding,
+ Documentation/devicetree/bindings/clock/ti,sci-clk.txt
+
+SoC-specific Required Properties:
+
+The following are mandatory properties for Keystone 2 66AK2G SoCs only:
+
+- power-domains: Should contain a phandle to a PM domain provider node
+ and an args specifier containing the I2C device id
+ value. This property is as per the binding,
+ Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
Recommended properties :
- interrupts : standard interrupt property.
diff --git a/Bindings/i2c/i2c-gpio.txt b/Bindings/i2c/i2c-gpio.txt
index 4f8ec947c6bd..38a05562d1d2 100644
--- a/Bindings/i2c/i2c-gpio.txt
+++ b/Bindings/i2c/i2c-gpio.txt
@@ -2,25 +2,39 @@ Device-Tree bindings for i2c gpio driver
Required properties:
- compatible = "i2c-gpio";
- - gpios: sda and scl gpio
-
+ - sda-gpios: gpio used for the sda signal, this should be flagged as
+ active high using open drain with (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)
+ from <dt-bindings/gpio/gpio.h> since the signal is by definition
+ open drain.
+ - scl-gpios: gpio used for the scl signal, this should be flagged as
+ active high using open drain with (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)
+ from <dt-bindings/gpio/gpio.h> since the signal is by definition
+ open drain.
Optional properties:
- - i2c-gpio,sda-open-drain: sda as open drain
- - i2c-gpio,scl-open-drain: scl as open drain
- i2c-gpio,scl-output-only: scl as output only
- i2c-gpio,delay-us: delay between GPIO operations (may depend on each platform)
- i2c-gpio,timeout-ms: timeout to get data
+Deprecated properties, do not use in new device tree sources:
+ - gpios: sda and scl gpio, alternative for {sda,scl}-gpios
+ - i2c-gpio,sda-open-drain: this means that something outside of our
+ control has put the GPIO line used for SDA into open drain mode, and
+ that something is not the GPIO chip. It is essentially an
+ inconsistency flag.
+ - i2c-gpio,scl-open-drain: this means that something outside of our
+ control has put the GPIO line used for SCL into open drain mode, and
+ that something is not the GPIO chip. It is essentially an
+ inconsistency flag.
+
Example nodes:
+#include <dt-bindings/gpio/gpio.h>
+
i2c@0 {
compatible = "i2c-gpio";
- gpios = <&pioA 23 0 /* sda */
- &pioA 24 0 /* scl */
- >;
- i2c-gpio,sda-open-drain;
- i2c-gpio,scl-open-drain;
+ sda-gpios = <&pioA 23 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&pioA 24 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
i2c-gpio,delay-us = <2>; /* ~100 kHz */
#address-cells = <1>;
#size-cells = <0>;
diff --git a/Bindings/i2c/i2c-jz4780.txt b/Bindings/i2c/i2c-jz4780.txt
index 231e4cc4008c..d4a082acf92f 100644
--- a/Bindings/i2c/i2c-jz4780.txt
+++ b/Bindings/i2c/i2c-jz4780.txt
@@ -18,7 +18,7 @@ Optional properties:
Example
/ {
- i2c4: i2c4@0x10054000 {
+ i2c4: i2c4@10054000 {
compatible = "ingenic,jz4780-i2c";
reg = <0x10054000 0x1000>;
diff --git a/Bindings/i2c/i2c-mux.txt b/Bindings/i2c/i2c-mux.txt
index 212e6779dc5c..b38f58a1c878 100644
--- a/Bindings/i2c/i2c-mux.txt
+++ b/Bindings/i2c/i2c-mux.txt
@@ -6,10 +6,10 @@ multiplexer/switch will have one child node for each child bus.
Optional properties:
- #address-cells = <1>;
- This property is required is the i2c-mux child node does not exist.
+ This property is required if the i2c-mux child node does not exist.
- #size-cells = <0>;
- This property is required is the i2c-mux child node does not exist.
+ This property is required if the i2c-mux child node does not exist.
- i2c-mux
For i2c multiplexers/switches that have child nodes that are a mixture
diff --git a/Bindings/i2c/i2c-rcar.txt b/Bindings/i2c/i2c-rcar.txt
index cad39aee9f73..a777477e4547 100644
--- a/Bindings/i2c/i2c-rcar.txt
+++ b/Bindings/i2c/i2c-rcar.txt
@@ -13,6 +13,7 @@ Required properties:
"renesas,i2c-r8a7794" if the device is a part of a R8A7794 SoC.
"renesas,i2c-r8a7795" if the device is a part of a R8A7795 SoC.
"renesas,i2c-r8a7796" if the device is a part of a R8A7796 SoC.
+ "renesas,i2c-r8a77970" if the device is a part of a R8A77970 SoC.
"renesas,rcar-gen1-i2c" for a generic R-Car Gen1 compatible device.
"renesas,rcar-gen2-i2c" for a generic R-Car Gen2 or RZ/G1 compatible
device.
diff --git a/Bindings/i2c/i2c-sunxi-p2wi.txt b/Bindings/i2c/i2c-sunxi-p2wi.txt
index 6b765485af7d..49df0053347a 100644
--- a/Bindings/i2c/i2c-sunxi-p2wi.txt
+++ b/Bindings/i2c/i2c-sunxi-p2wi.txt
@@ -24,7 +24,7 @@ Slave device properties:
Example:
- p2wi@01f03400 {
+ p2wi@1f03400 {
compatible = "allwinner,sun6i-a31-p2wi";
reg = <0x01f03400 0x400>;
interrupts = <0 39 4>;
diff --git a/Bindings/i2c/i2c.txt b/Bindings/i2c/i2c.txt
index cee9d5055fa2..11263982470e 100644
--- a/Bindings/i2c/i2c.txt
+++ b/Bindings/i2c/i2c.txt
@@ -59,8 +59,8 @@ wants to support one of the below features, it should adapt the bindings below.
interrupts used by the device.
- interrupt-names
- "irq" and "wakeup" names are recognized by I2C core, other names are
- left to individual drivers.
+ "irq", "wakeup" and "smbus_alert" names are recognized by I2C core,
+ other names are left to individual drivers.
- host-notify
device uses SMBus host notify protocol instead of interrupt line.
diff --git a/Bindings/iio/adc/mcp320x.txt b/Bindings/iio/adc/mcp320x.txt
index bcd3ac8e6e0c..7d64753df949 100644
--- a/Bindings/iio/adc/mcp320x.txt
+++ b/Bindings/iio/adc/mcp320x.txt
@@ -29,15 +29,29 @@ Required properties:
"microchip,mcp3204"
"microchip,mcp3208"
"microchip,mcp3301"
+ "microchip,mcp3550-50"
+ "microchip,mcp3550-60"
+ "microchip,mcp3551"
+ "microchip,mcp3553"
NOTE: The use of the compatibles with no vendor prefix
is deprecated and only listed because old DT use them.
+ - spi-cpha, spi-cpol (boolean):
+ Either SPI mode (0,0) or (1,1) must be used, so specify
+ none or both of spi-cpha, spi-cpol. The MCP3550/1/3
+ is more efficient in mode (1,1) as only 3 instead of
+ 4 bytes need to be read from the ADC, but not all SPI
+ masters support it.
+
+ - vref-supply: Phandle to the external reference voltage supply.
+
Examples:
spi_controller {
mcp3x0x@0 {
compatible = "mcp3002";
reg = <0>;
spi-max-frequency = <1000000>;
+ vref-supply = <&vref_reg>;
};
};
diff --git a/Bindings/iio/adc/mt6577_auxadc.txt b/Bindings/iio/adc/mt6577_auxadc.txt
index 64dc4843c180..0df9befdaecc 100644
--- a/Bindings/iio/adc/mt6577_auxadc.txt
+++ b/Bindings/iio/adc/mt6577_auxadc.txt
@@ -12,6 +12,7 @@ for the Thermal Controller which holds a phandle to the AUXADC.
Required properties:
- compatible: Should be one of:
- "mediatek,mt2701-auxadc": For MT2701 family of SoCs
+ - "mediatek,mt2712-auxadc": For MT2712 family of SoCs
- "mediatek,mt7622-auxadc": For MT7622 family of SoCs
- "mediatek,mt8173-auxadc": For MT8173 family of SoCs
- reg: Address range of the AUXADC unit.
diff --git a/Bindings/iio/dac/ds4424.txt b/Bindings/iio/dac/ds4424.txt
new file mode 100644
index 000000000000..eaebbf8dab40
--- /dev/null
+++ b/Bindings/iio/dac/ds4424.txt
@@ -0,0 +1,20 @@
+Maxim Integrated DS4422/DS4424 7-bit Sink/Source Current DAC Device Driver
+
+Datasheet publicly available at:
+https://datasheets.maximintegrated.com/en/ds/DS4422-DS4424.pdf
+
+Required properties:
+ - compatible: Should be one of
+ maxim,ds4422
+ maxim,ds4424
+ - reg: Should contain the DAC I2C address
+
+Optional properties:
+ - vcc-supply: Power supply is optional. If not defined, driver will ignore it.
+
+Example:
+ ds4224@10 {
+ compatible = "maxim,ds4424";
+ reg = <0x10>; /* When A0, A1 pins are ground */
+ vcc-supply = <&vcc_3v3>;
+ };
diff --git a/Bindings/iio/dac/ti-dac082s085.txt b/Bindings/iio/dac/ti-dac082s085.txt
new file mode 100644
index 000000000000..9cb0e10df704
--- /dev/null
+++ b/Bindings/iio/dac/ti-dac082s085.txt
@@ -0,0 +1,34 @@
+Texas Instruments 8/10/12-bit 2/4-channel DAC driver
+
+Required properties:
+ - compatible: Must be one of:
+ "ti,dac082s085"
+ "ti,dac102s085"
+ "ti,dac122s085"
+ "ti,dac084s085"
+ "ti,dac104s085"
+ "ti,dac124s085"
+ - reg: Chip select number.
+ - spi-cpha, spi-cpol: SPI mode (0,1) or (1,0) must be used, so specify
+ either spi-cpha or spi-cpol (but not both).
+ - vref-supply: Phandle to the external reference voltage supply.
+
+For other required and optional properties of SPI slave nodes please refer to
+../../spi/spi-bus.txt.
+
+Example:
+ vref_2v5_reg: regulator-vref {
+ compatible = "regulator-fixed";
+ regulator-name = "2v5";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-always-on;
+ };
+
+ dac@0 {
+ compatible = "ti,dac082s085";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+ spi-cpol;
+ vref-supply = <&vref_2v5_reg>;
+ };
diff --git a/Bindings/iio/health/max30100.txt b/Bindings/iio/health/max30100.txt
index 295a9edfa4fd..8d8176459d09 100644
--- a/Bindings/iio/health/max30100.txt
+++ b/Bindings/iio/health/max30100.txt
@@ -20,9 +20,9 @@ Optional properties:
Example:
-max30100@057 {
+max30100@57 {
compatible = "maxim,max30100";
- reg = <57>;
+ reg = <0x57>;
maxim,led-current-microamp = <24000 50000>;
interrupt-parent = <&gpio1>;
interrupts = <16 2>;
diff --git a/Bindings/iio/health/max30102.txt b/Bindings/iio/health/max30102.txt
index c695e7cbeefb..8629c18b0e78 100644
--- a/Bindings/iio/health/max30102.txt
+++ b/Bindings/iio/health/max30102.txt
@@ -20,7 +20,7 @@ Optional properties:
Example:
-max30100@57 {
+max30102@57 {
compatible = "maxim,max30102";
reg = <0x57>;
maxim,red-led-current-microamp = <7000>;
diff --git a/Bindings/iio/magnetometer/ak8974.txt b/Bindings/iio/magnetometer/ak8974.txt
index 77d5aba1bd8c..baecc4a85197 100644
--- a/Bindings/iio/magnetometer/ak8974.txt
+++ b/Bindings/iio/magnetometer/ak8974.txt
@@ -19,7 +19,7 @@ Optional properties:
Example:
-ak8974@0f {
+ak8974@f {
compatible = "asahi-kasei,ak8974";
reg = <0x0f>;
avdd-supply = <&foo_reg>;
diff --git a/Bindings/iio/magnetometer/ak8975.txt b/Bindings/iio/magnetometer/ak8975.txt
index e1e7dd3259f6..aa67ceb0d4e0 100644
--- a/Bindings/iio/magnetometer/ak8975.txt
+++ b/Bindings/iio/magnetometer/ak8975.txt
@@ -13,7 +13,7 @@ Optional properties:
Example:
-ak8975@0c {
+ak8975@c {
compatible = "asahi-kasei,ak8975";
reg = <0x0c>;
gpios = <&gpj0 7 0>;
diff --git a/Bindings/iio/pressure/hp03.txt b/Bindings/iio/pressure/hp03.txt
index 54e7e70bcea5..831dbee7a5c3 100644
--- a/Bindings/iio/pressure/hp03.txt
+++ b/Bindings/iio/pressure/hp03.txt
@@ -10,7 +10,7 @@ Required properties:
Example:
-hp03@0x77 {
+hp03@77 {
compatible = "hoperf,hp03";
reg = <0x77>;
xclr-gpio = <&portc 0 0x0>;
diff --git a/Bindings/iio/st-sensors.txt b/Bindings/iio/st-sensors.txt
index 9ec6f5ce54fc..6f626f73417e 100644
--- a/Bindings/iio/st-sensors.txt
+++ b/Bindings/iio/st-sensors.txt
@@ -46,6 +46,8 @@ Accelerometers:
- st,h3lis331dl-accel
- st,lng2dm-accel
- st,lis3l02dq
+- st,lis2dw12
+- st,lis3dhh
Gyroscopes:
- st,l3g4200d-gyro
@@ -71,3 +73,5 @@ Pressure sensors:
- st,lps25h-press
- st,lps331ap-press
- st,lps22hb-press
+- st,lps33hw
+- st,lps35hw
diff --git a/Bindings/input/gpio-mouse.txt b/Bindings/input/gpio-mouse.txt
new file mode 100644
index 000000000000..519510a11af9
--- /dev/null
+++ b/Bindings/input/gpio-mouse.txt
@@ -0,0 +1,32 @@
+Device-Tree bindings for GPIO attached mice
+
+This simply uses standard GPIO handles to define a simple mouse connected
+to 5-7 GPIO lines.
+
+Required properties:
+ - compatible: must be "gpio-mouse"
+ - scan-interval-ms: The scanning interval in milliseconds
+ - up-gpios: GPIO line phandle to the line indicating "up"
+ - down-gpios: GPIO line phandle to the line indicating "down"
+ - left-gpios: GPIO line phandle to the line indicating "left"
+ - right-gpios: GPIO line phandle to the line indicating "right"
+
+Optional properties:
+ - button-left-gpios: GPIO line handle to the left mouse button
+ - button-middle-gpios: GPIO line handle to the middle mouse button
+ - button-right-gpios: GPIO line handle to the right mouse button
+Example:
+
+#include <dt-bindings/gpio/gpio.h>
+
+gpio-mouse {
+ compatible = "gpio-mouse";
+ scan-interval-ms = <50>;
+ up-gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
+ down-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
+ left-gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+ right-gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
+ button-left-gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
+ button-middle-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
+ button-right-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+};
diff --git a/Bindings/input/sun4i-lradc-keys.txt b/Bindings/input/sun4i-lradc-keys.txt
index 4357e498ef04..1458c3179a63 100644
--- a/Bindings/input/sun4i-lradc-keys.txt
+++ b/Bindings/input/sun4i-lradc-keys.txt
@@ -19,7 +19,7 @@ Example:
#include <dt-bindings/input/input.h>
- lradc: lradc@01c22800 {
+ lradc: lradc@1c22800 {
compatible = "allwinner,sun4i-a10-lradc-keys";
reg = <0x01c22800 0x100>;
interrupts = <31>;
diff --git a/Bindings/input/touchscreen/bu21013.txt b/Bindings/input/touchscreen/bu21013.txt
index ca5a2c86480c..56d835242af2 100644
--- a/Bindings/input/touchscreen/bu21013.txt
+++ b/Bindings/input/touchscreen/bu21013.txt
@@ -15,7 +15,7 @@ Optional properties:
Example:
i2c@80110000 {
- bu21013_tp@0x5c {
+ bu21013_tp@5c {
compatible = "rohm,bu21013_tp";
reg = <0x5c>;
touch-gpio = <&gpio2 20 0x4>;
diff --git a/Bindings/input/touchscreen/egalax-ts.txt b/Bindings/input/touchscreen/egalax-ts.txt
index 49fa14ed155c..298e3442f143 100644
--- a/Bindings/input/touchscreen/egalax-ts.txt
+++ b/Bindings/input/touchscreen/egalax-ts.txt
@@ -10,7 +10,7 @@ Required properties:
Example:
- egalax_ts@04 {
+ touchscreen@4 {
compatible = "eeti,egalax_ts";
reg = <0x04>;
interrupt-parent = <&gpio1>;
diff --git a/Bindings/input/touchscreen/exc3000.txt b/Bindings/input/touchscreen/exc3000.txt
new file mode 100644
index 000000000000..1dcff4a43eaa
--- /dev/null
+++ b/Bindings/input/touchscreen/exc3000.txt
@@ -0,0 +1,27 @@
+* EETI EXC3000 Multiple Touch Controller
+
+Required properties:
+- compatible: must be "eeti,exc3000"
+- reg: i2c slave address
+- interrupt-parent: the phandle for the interrupt controller
+- interrupts: touch controller interrupt
+- touchscreen-size-x: See touchscreen.txt
+- touchscreen-size-y: See touchscreen.txt
+
+Optional properties:
+- touchscreen-inverted-x: See touchscreen.txt
+- touchscreen-inverted-y: See touchscreen.txt
+- touchscreen-swapped-x-y: See touchscreen.txt
+
+Example:
+
+ touchscreen@2a {
+ compatible = "eeti,exc3000";
+ reg = <0x2a>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
+ touchscreen-size-x = <4096>;
+ touchscreen-size-y = <4096>;
+ touchscreen-inverted-x;
+ touchscreen-swapped-x-y;
+ };
diff --git a/Bindings/input/touchscreen/goodix.txt b/Bindings/input/touchscreen/goodix.txt
index c98757a69110..0c369d8ebcab 100644
--- a/Bindings/input/touchscreen/goodix.txt
+++ b/Bindings/input/touchscreen/goodix.txt
@@ -2,7 +2,8 @@ Device tree bindings for Goodix GT9xx series touchscreen controller
Required properties:
- - compatible : Should be "goodix,gt911"
+ - compatible : Should be "goodix,gt1151"
+ or "goodix,gt911"
or "goodix,gt9110"
or "goodix,gt912"
or "goodix,gt927"
diff --git a/Bindings/input/touchscreen/hideep.txt b/Bindings/input/touchscreen/hideep.txt
new file mode 100644
index 000000000000..121d9b7c79a2
--- /dev/null
+++ b/Bindings/input/touchscreen/hideep.txt
@@ -0,0 +1,42 @@
+* HiDeep Finger and Stylus touchscreen controller
+
+Required properties:
+- compatible : must be "hideep,hideep-ts"
+- reg : I2C slave address, (e.g. 0x6C).
+- interrupt-parent : Interrupt controller to which the chip is connected.
+- interrupts : Interrupt to which the chip is connected.
+
+Optional properties:
+- vdd-supply : It is the controller supply for controlling
+ main voltage(3.3V) through the regulator.
+- vid-supply : It is the controller supply for controlling
+ IO voltage(1.8V) through the regulator.
+- reset-gpios : Define for reset gpio pin.
+ It is to use for reset IC.
+- touchscreen-size-x : X axis size of touchscreen
+- touchscreen-size-y : Y axis size of touchscreen
+- linux,keycodes : Specifies an array of numeric keycode values to
+ be used for reporting button presses. The array can
+ contain up to 3 entries.
+
+Example:
+
+#include "dt-bindings/input/input.h"
+
+i2c@00000000 {
+
+ /* ... */
+
+ touchscreen@6c {
+ compatible = "hideep,hideep-ts";
+ reg = <0x6c>;
+ interrupt-parent = <&gpx1>;
+ interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+ vdd-supply = <&ldo15_reg>";
+ vid-supply = <&ldo18_reg>;
+ reset-gpios = <&gpx1 5 0>;
+ touchscreen-size-x = <1080>;
+ touchscreen-size-y = <1920>;
+ linux,keycodes = <KEY_HOME>, <KEY_MENU>, <KEY_BACK>;
+ };
+};
diff --git a/Bindings/input/touchscreen/imx6ul_tsc.txt b/Bindings/input/touchscreen/imx6ul_tsc.txt
index e67e58b61706..164915004424 100644
--- a/Bindings/input/touchscreen/imx6ul_tsc.txt
+++ b/Bindings/input/touchscreen/imx6ul_tsc.txt
@@ -21,7 +21,7 @@ Optional properties:
each read. Valid values are 1, 4, 8, 16 and 32.
Example:
- tsc: tsc@02040000 {
+ tsc: tsc@2040000 {
compatible = "fsl,imx6ul-tsc";
reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
diff --git a/Bindings/input/touchscreen/samsung,s6sy761.txt b/Bindings/input/touchscreen/samsung,s6sy761.txt
new file mode 100644
index 000000000000..d9b7c2ff611e
--- /dev/null
+++ b/Bindings/input/touchscreen/samsung,s6sy761.txt
@@ -0,0 +1,34 @@
+* Samsung S6SY761 touchscreen controller
+
+Required properties:
+- compatible : must be "samsung,s6sy761"
+- reg : I2C slave address, (e.g. 0x48)
+- interrupt-parent : the phandle to the interrupt controller which provides
+ the interrupt
+- interrupts : interrupt specification
+- avdd-supply : analogic power supply
+- vdd-supply : power supply
+
+Optional properties:
+- touchscreen-size-x : see touchscreen.txt. This property is embedded in the
+ device. If defined it forces a different x resolution.
+- touchscreen-size-y : see touchscreen.txt. This property is embedded in the
+ device. If defined it forces a different y resolution.
+
+Example:
+
+i2c@00000000 {
+
+ /* ... */
+
+ touchscreen@48 {
+ compatible = "samsung,s6sy761";
+ reg = <0x48>;
+ interrupt-parent = <&gpa1>;
+ interrupts = <1 IRQ_TYPE_NONE>;
+ avdd-supply = <&ldo30_reg>;
+ vdd-supply = <&ldo31_reg>;
+ touchscreen-size-x = <4096>;
+ touchscreen-size-y = <4096>;
+ };
+};
diff --git a/Bindings/interrupt-controller/allwinner,sunxi-nmi.txt b/Bindings/interrupt-controller/allwinner,sunxi-nmi.txt
index 4ae553eb333d..4903fb72d883 100644
--- a/Bindings/interrupt-controller/allwinner,sunxi-nmi.txt
+++ b/Bindings/interrupt-controller/allwinner,sunxi-nmi.txt
@@ -20,7 +20,7 @@ Required properties:
Example:
-sc-nmi-intc@01c00030 {
+sc-nmi-intc@1c00030 {
compatible = "allwinner,sun7i-a20-sc-nmi";
interrupt-controller;
#interrupt-cells = <2>;
diff --git a/Bindings/interrupt-controller/amlogic,meson-gpio-intc.txt b/Bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
new file mode 100644
index 000000000000..a83f9a5734ca
--- /dev/null
+++ b/Bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
@@ -0,0 +1,36 @@
+Amlogic meson GPIO interrupt controller
+
+Meson SoCs contains an interrupt controller which is able to watch the SoC
+pads and generate an interrupt on edge or level. The controller is essentially
+a 256 pads to 8 GIC interrupt multiplexer, with a filter block to select edge
+or level and polarity. It does not expose all 256 mux inputs because the
+documentation shows that the upper part is not mapped to any pad. The actual
+number of interrupt exposed depends on the SoC.
+
+Required properties:
+
+- compatible : must have "amlogic,meson8-gpio-intc” and either
+ “amlogic,meson8-gpio-intc” for meson8 SoCs (S802) or
+ “amlogic,meson8b-gpio-intc” for meson8b SoCs (S805) or
+ “amlogic,meson-gxbb-gpio-intc” for GXBB SoCs (S905) or
+ “amlogic,meson-gxl-gpio-intc” for GXL SoCs (S905X, S912)
+- interrupt-parent : a phandle to the GIC the interrupts are routed to.
+ Usually this is provided at the root level of the device tree as it is
+ common to most of the SoC.
+- reg : Specifies base physical address and size of the registers.
+- interrupt-controller : Identifies the node as an interrupt controller.
+- #interrupt-cells : Specifies the number of cells needed to encode an
+ interrupt source. The value must be 2.
+- meson,channel-interrupts: Array with the 8 upstream hwirq numbers. These
+ are the hwirqs used on the parent interrupt controller.
+
+Example:
+
+gpio_interrupt: interrupt-controller@9880 {
+ compatible = "amlogic,meson-gxbb-gpio-intc",
+ "amlogic,meson-gpio-intc";
+ reg = <0x0 0x9880 0x0 0x10>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ meson,channel-interrupts = <64 65 66 67 68 69 70 71>;
+};
diff --git a/Bindings/interrupt-controller/arm,gic-v3.txt b/Bindings/interrupt-controller/arm,gic-v3.txt
index 5eb108e180fa..0a57f2f4167d 100644
--- a/Bindings/interrupt-controller/arm,gic-v3.txt
+++ b/Bindings/interrupt-controller/arm,gic-v3.txt
@@ -75,6 +75,10 @@ These nodes must have the following properties:
- reg: Specifies the base physical address and size of the ITS
registers.
+Optional:
+- socionext,synquacer-pre-its: (u32, u32) tuple describing the untranslated
+ address and size of the pre-ITS window.
+
The main GIC node must contain the appropriate #address-cells,
#size-cells and ranges properties for the reg property of all ITS
nodes.
diff --git a/Bindings/interrupt-controller/arm,gic.txt b/Bindings/interrupt-controller/arm,gic.txt
index 560d8a727b8f..2f3244648646 100644
--- a/Bindings/interrupt-controller/arm,gic.txt
+++ b/Bindings/interrupt-controller/arm,gic.txt
@@ -155,7 +155,7 @@ Example:
<0x0 0xe112f000 0 0x02000>,
<0x0 0xe1140000 0 0x10000>,
<0x0 0xe1160000 0 0x10000>;
- v2m0: v2m@0x8000 {
+ v2m0: v2m@8000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0x80000 0 0x1000>;
@@ -163,7 +163,7 @@ Example:
....
- v2mN: v2m@0x9000 {
+ v2mN: v2m@9000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0x90000 0 0x1000>;
diff --git a/Bindings/interrupt-controller/brcm,l2-intc.txt b/Bindings/interrupt-controller/brcm,l2-intc.txt
index 448273a30a11..36df06c5c567 100644
--- a/Bindings/interrupt-controller/brcm,l2-intc.txt
+++ b/Bindings/interrupt-controller/brcm,l2-intc.txt
@@ -2,7 +2,8 @@ Broadcom Generic Level 2 Interrupt Controller
Required properties:
-- compatible: should be "brcm,l2-intc"
+- compatible: should be "brcm,l2-intc" for latched interrupt controllers
+ should be "brcm,bcm7271-l2-intc" for level interrupt controllers
- reg: specifies the base physical address and size of the registers
- interrupt-controller: identifies the node as an interrupt controller
- #interrupt-cells: specifies the number of cells needed to encode an
diff --git a/Bindings/interrupt-controller/fsl,ls-scfg-msi.txt b/Bindings/interrupt-controller/fsl,ls-scfg-msi.txt
index 49ccabbfa6f3..a4ff93d6b7f3 100644
--- a/Bindings/interrupt-controller/fsl,ls-scfg-msi.txt
+++ b/Bindings/interrupt-controller/fsl,ls-scfg-msi.txt
@@ -8,6 +8,7 @@ Required properties:
"fsl,ls1043a-msi"
"fsl,ls1046a-msi"
"fsl,ls1043a-v1.1-msi"
+ "fsl,ls1012a-msi"
- msi-controller: indicates that this is a PCIe MSI controller node
- reg: physical base address of the controller and length of memory mapped.
- interrupts: an interrupt to the parent interrupt controller.
diff --git a/Bindings/interrupt-controller/img,meta-intc.txt b/Bindings/interrupt-controller/img,meta-intc.txt
index 80994adab392..42431f44697f 100644
--- a/Bindings/interrupt-controller/img,meta-intc.txt
+++ b/Bindings/interrupt-controller/img,meta-intc.txt
@@ -71,7 +71,7 @@ Example 2:
* An interrupt generating device that is wired to a Meta external
* trigger block.
*/
- uart1: uart@0x02004c00 {
+ uart1: uart@02004c00 {
// Interrupt source '5' that is level-sensitive.
// Note that there are only two cells as specified in the
// interrupt parent's '#interrupt-cells' property.
diff --git a/Bindings/interrupt-controller/img,pdc-intc.txt b/Bindings/interrupt-controller/img,pdc-intc.txt
index a69118550344..5dc2a55ad811 100644
--- a/Bindings/interrupt-controller/img,pdc-intc.txt
+++ b/Bindings/interrupt-controller/img,pdc-intc.txt
@@ -51,7 +51,7 @@ Example 1:
/*
* TZ1090 PDC block
*/
- pdc: pdc@0x02006000 {
+ pdc: pdc@02006000 {
// This is an interrupt controller node.
interrupt-controller;
diff --git a/Bindings/interrupt-controller/openrisc,ompic.txt b/Bindings/interrupt-controller/openrisc,ompic.txt
new file mode 100644
index 000000000000..caec07cc7149
--- /dev/null
+++ b/Bindings/interrupt-controller/openrisc,ompic.txt
@@ -0,0 +1,22 @@
+Open Multi-Processor Interrupt Controller
+
+Required properties:
+
+- compatible : This should be "openrisc,ompic"
+- reg : Specifies base physical address and size of the register space. The
+ size is based on the number of cores the controller has been configured
+ to handle, this should be set to 8 bytes per cpu core.
+- interrupt-controller : Identifies the node as an interrupt controller.
+- #interrupt-cells : This should be set to 0 as this will not be an irq
+ parent.
+- interrupts : Specifies the interrupt line to which the ompic is wired.
+
+Example:
+
+ompic: interrupt-controller@98000000 {
+ compatible = "openrisc,ompic";
+ reg = <0x98000000 16>;
+ interrupt-controller;
+ #interrupt-cells = <0>;
+ interrupts = <1>;
+};
diff --git a/Bindings/interrupt-controller/renesas,irqc.txt b/Bindings/interrupt-controller/renesas,irqc.txt
index e3f052d8c11a..33c9a10fdc91 100644
--- a/Bindings/interrupt-controller/renesas,irqc.txt
+++ b/Bindings/interrupt-controller/renesas,irqc.txt
@@ -13,6 +13,9 @@ Required properties:
- "renesas,irqc-r8a7793" (R-Car M2-N)
- "renesas,irqc-r8a7794" (R-Car E2)
- "renesas,intc-ex-r8a7795" (R-Car H3)
+ - "renesas,intc-ex-r8a7796" (R-Car M3-W)
+ - "renesas,intc-ex-r8a77970" (R-Car V3M)
+ - "renesas,intc-ex-r8a77995" (R-Car D3)
- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in
interrupts.txt in this directory
- clocks: Must contain a reference to the functional clock.
diff --git a/Bindings/interrupt-controller/socionext,synquacer-exiu.txt b/Bindings/interrupt-controller/socionext,synquacer-exiu.txt
new file mode 100644
index 000000000000..8b2faefe29ca
--- /dev/null
+++ b/Bindings/interrupt-controller/socionext,synquacer-exiu.txt
@@ -0,0 +1,32 @@
+Socionext SynQuacer External Interrupt Unit (EXIU)
+
+The Socionext Synquacer SoC has an external interrupt unit (EXIU)
+that forwards a block of 32 configurable input lines to 32 adjacent
+level-high type GICv3 SPIs.
+
+Required properties:
+
+- compatible : Should be "socionext,synquacer-exiu".
+- reg : Specifies base physical address and size of the
+ control registers.
+- interrupt-controller : Identifies the node as an interrupt controller.
+- #interrupt-cells : Specifies the number of cells needed to encode an
+ interrupt source. The value must be 3.
+- interrupt-parent : phandle of the GIC these interrupts are routed to.
+- socionext,spi-base : The SPI number of the first SPI of the 32 adjacent
+ ones the EXIU forwards its interrups to.
+
+Notes:
+
+- Only SPIs can use the EXIU as an interrupt parent.
+
+Example:
+
+ exiu: interrupt-controller@510c0000 {
+ compatible = "socionext,synquacer-exiu";
+ reg = <0x0 0x510c0000 0x0 0x20>;
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <3>;
+ socionext,spi-base = <112>;
+ };
diff --git a/Bindings/interrupt-controller/st,spear3xx-shirq.txt b/Bindings/interrupt-controller/st,spear3xx-shirq.txt
index 715a013ed4bd..2ab0ea39867b 100644
--- a/Bindings/interrupt-controller/st,spear3xx-shirq.txt
+++ b/Bindings/interrupt-controller/st,spear3xx-shirq.txt
@@ -39,7 +39,7 @@ Example:
The following is an example from the SPEAr320 SoC dtsi file.
-shirq: interrupt-controller@0xb3000000 {
+shirq: interrupt-controller@b3000000 {
compatible = "st,spear320-shirq";
reg = <0xb3000000 0x1000>;
interrupts = <28 29 30 1>;
diff --git a/Bindings/interrupt-controller/st,stm32-exti.txt b/Bindings/interrupt-controller/st,stm32-exti.txt
index 6e7703d4ff5b..edf03f09244b 100644
--- a/Bindings/interrupt-controller/st,stm32-exti.txt
+++ b/Bindings/interrupt-controller/st,stm32-exti.txt
@@ -2,7 +2,9 @@ STM32 External Interrupt Controller
Required properties:
-- compatible: Should be "st,stm32-exti"
+- compatible: Should be:
+ "st,stm32-exti"
+ "st,stm32h7-exti"
- reg: Specifies base physical address and size of the registers
- interrupt-controller: Indentifies the node as an interrupt controller
- #interrupt-cells: Specifies the number of cells to encode an interrupt
diff --git a/Bindings/interrupt-controller/ti,keystone-irq.txt b/Bindings/interrupt-controller/ti,keystone-irq.txt
index d9bb106bdd16..5f94d7739d8d 100644
--- a/Bindings/interrupt-controller/ti,keystone-irq.txt
+++ b/Bindings/interrupt-controller/ti,keystone-irq.txt
@@ -20,7 +20,7 @@ Please refer to interrupts.txt in this directory for details of the common
Interrupt Controllers bindings used by client devices.
Example:
- kirq0: keystone_irq0@026202a0 {
+ kirq0: keystone_irq0@26202a0 {
compatible = "ti,keystone-irq";
ti,syscon-dev = <&devctrl 0x2a0>;
interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
diff --git a/Bindings/iommu/qcom,iommu.txt b/Bindings/iommu/qcom,iommu.txt
index b2641ceb2b40..059139abce35 100644
--- a/Bindings/iommu/qcom,iommu.txt
+++ b/Bindings/iommu/qcom,iommu.txt
@@ -115,7 +115,7 @@ to non-secure vs secure interrupt line.
iommus = <&apps_iommu 4>;
};
- gpu@01c00000 {
+ gpu@1c00000 {
...
iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
};
diff --git a/Bindings/iommu/renesas,ipmmu-vmsa.txt b/Bindings/iommu/renesas,ipmmu-vmsa.txt
index 3ed027cfca95..857df929a654 100644
--- a/Bindings/iommu/renesas,ipmmu-vmsa.txt
+++ b/Bindings/iommu/renesas,ipmmu-vmsa.txt
@@ -53,7 +53,7 @@ Example: R8A7791 IPMMU-MX and VSP1-D0 bus master
#iommu-cells = <1>;
};
- vsp1@fe928000 {
+ vsp@fe928000 {
...
iommus = <&ipmmu_mx 13>;
...
diff --git a/Bindings/leds/register-bit-led.txt b/Bindings/leds/register-bit-led.txt
index 59b56365f648..cf1ea403ba7a 100644
--- a/Bindings/leds/register-bit-led.txt
+++ b/Bindings/leds/register-bit-led.txt
@@ -32,7 +32,7 @@ syscon: syscon@10000000 {
compatible = "arm,realview-pb1176-syscon", "syscon";
reg = <0x10000000 0x1000>;
- led@08.0 {
+ led@8.0 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x01>;
@@ -40,7 +40,7 @@ syscon: syscon@10000000 {
linux,default-trigger = "heartbeat";
default-state = "on";
};
- led@08.1 {
+ led@8.1 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x02>;
@@ -48,7 +48,7 @@ syscon: syscon@10000000 {
linux,default-trigger = "mmc0";
default-state = "off";
};
- led@08.2 {
+ led@8.2 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x04>;
@@ -56,35 +56,35 @@ syscon: syscon@10000000 {
linux,default-trigger = "cpu0";
default-state = "off";
};
- led@08.3 {
+ led@8.3 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x08>;
label = "versatile:3";
default-state = "off";
};
- led@08.4 {
+ led@8.4 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x10>;
label = "versatile:4";
default-state = "off";
};
- led@08.5 {
+ led@8.5 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x20>;
label = "versatile:5";
default-state = "off";
};
- led@08.6 {
+ led@8.6 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x40>;
label = "versatile:6";
default-state = "off";
};
- led@08.7 {
+ led@8.7 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x80>;
diff --git a/Bindings/mailbox/altera-mailbox.txt b/Bindings/mailbox/altera-mailbox.txt
index c2619797ce0c..49cfc8c337c4 100644
--- a/Bindings/mailbox/altera-mailbox.txt
+++ b/Bindings/mailbox/altera-mailbox.txt
@@ -14,7 +14,7 @@ Optional properties:
depends on the interrupt controller parent.
Example:
- mbox_tx: mailbox@0x100 {
+ mbox_tx: mailbox@100 {
compatible = "altr,mailbox-1.0";
reg = <0x100 0x8>;
interrupt-parent = < &gic_0 >;
@@ -22,7 +22,7 @@ Example:
#mbox-cells = <1>;
};
- mbox_rx: mailbox@0x200 {
+ mbox_rx: mailbox@200 {
compatible = "altr,mailbox-1.0";
reg = <0x200 0x8>;
interrupt-parent = < &gic_0 >;
@@ -40,7 +40,7 @@ support only one channel).The equivalent "mbox-names" property value can be
used to give a name to the communication channel to be used by the client user.
Example:
- mclient0: mclient0@0x400 {
+ mclient0: mclient0@400 {
compatible = "client-1.0";
reg = <0x400 0x10>;
mbox-names = "mbox-tx", "mbox-rx";
diff --git a/Bindings/mailbox/brcm,iproc-pdc-mbox.txt b/Bindings/mailbox/brcm,iproc-pdc-mbox.txt
index 0f3ee81d92c2..9bcdf2087625 100644
--- a/Bindings/mailbox/brcm,iproc-pdc-mbox.txt
+++ b/Bindings/mailbox/brcm,iproc-pdc-mbox.txt
@@ -15,7 +15,7 @@ Optional properties:
- brcm,use-bcm-hdr: present if a BCM header precedes each frame.
Example:
- pdc0: iproc-pdc0@0x612c0000 {
+ pdc0: iproc-pdc0@612c0000 {
compatible = "brcm,iproc-pdc-mbox";
reg = <0 0x612c0000 0 0x445>; /* PDC FS0 regs */
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/Bindings/mailbox/ti,message-manager.txt b/Bindings/mailbox/ti,message-manager.txt
index b449d025049f..c3b55b3ede8a 100644
--- a/Bindings/mailbox/ti,message-manager.txt
+++ b/Bindings/mailbox/ti,message-manager.txt
@@ -29,7 +29,7 @@ Required properties:
Example(K2G):
------------
- msgmgr: msgmgr@02a00000 {
+ msgmgr: msgmgr@2a00000 {
compatible = "ti,k2g-message-manager";
#mbox-cells = <2>;
reg-names = "queue_proxy_region", "queue_state_debug_region";
diff --git a/Bindings/marvell.txt b/Bindings/marvell.txt
index ea2b16ced49b..7f722316458a 100644
--- a/Bindings/marvell.txt
+++ b/Bindings/marvell.txt
@@ -446,7 +446,7 @@ prefixed with the string "marvell,", for Marvell Technology Group Ltd.
that services interrupts for this device.
Example Discovery CPU Error node:
- cpu-error@0070 {
+ cpu-error@70 {
compatible = "marvell,mv64360-cpu-error";
reg = <0x70 0x10 0x128 0x28>;
interrupts = <3>;
@@ -466,7 +466,7 @@ prefixed with the string "marvell,", for Marvell Technology Group Ltd.
that services interrupts for this device.
Example Discovery SRAM Controller node:
- sram-ctrl@0380 {
+ sram-ctrl@380 {
compatible = "marvell,mv64360-sram-ctrl";
reg = <0x380 0x80>;
interrupts = <13>;
diff --git a/Bindings/media/cec-gpio.txt b/Bindings/media/cec-gpio.txt
new file mode 100644
index 000000000000..46a0bac8b3b9
--- /dev/null
+++ b/Bindings/media/cec-gpio.txt
@@ -0,0 +1,32 @@
+* HDMI CEC GPIO driver
+
+The HDMI CEC GPIO module supports CEC implementations where the CEC line
+is hooked up to a pull-up GPIO line and - optionally - the HPD line is
+hooked up to another GPIO line.
+
+Required properties:
+ - compatible: value must be "cec-gpio".
+ - cec-gpios: gpio that the CEC line is connected to. The line should be
+ tagged as open drain.
+
+If the CEC line is associated with an HDMI receiver/transmitter, then the
+following property is also required:
+
+ - hdmi-phandle - phandle to the HDMI controller, see also cec.txt.
+
+If the CEC line is not associated with an HDMI receiver/transmitter, then
+the following property is optional:
+
+ - hpd-gpios: gpio that the HPD line is connected to.
+
+Example for the Raspberry Pi 3 where the CEC line is connected to
+pin 26 aka BCM7 aka CE1 on the GPIO pin header and the HPD line is
+connected to pin 11 aka BCM17:
+
+#include <dt-bindings/gpio/gpio.h>
+
+cec-gpio {
+ compatible = "cec-gpio";
+ cec-gpios = <&gpio 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+ hpd-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
+};
diff --git a/Bindings/media/exynos5-gsc.txt b/Bindings/media/exynos5-gsc.txt
index 26ca25b6d264..bc963a6d305a 100644
--- a/Bindings/media/exynos5-gsc.txt
+++ b/Bindings/media/exynos5-gsc.txt
@@ -3,8 +3,11 @@
G-Scaler is used for scaling and color space conversion on EXYNOS5 SoCs.
Required properties:
-- compatible: should be "samsung,exynos5-gsc" (for Exynos 5250, 5420 and
- 5422 SoCs) or "samsung,exynos5433-gsc" (Exynos 5433)
+- compatible: should be one of
+ "samsung,exynos5250-gsc"
+ "samsung,exynos5420-gsc"
+ "samsung,exynos5433-gsc"
+ "samsung,exynos5-gsc" (deprecated)
- reg: should contain G-Scaler physical address location and length.
- interrupts: should contain G-Scaler interrupt number
@@ -14,8 +17,8 @@ Optional properties:
Example:
-gsc_0: gsc@0x13e00000 {
- compatible = "samsung,exynos5-gsc";
+gsc_0: gsc@13e00000 {
+ compatible = "samsung,exynos5250-gsc";
reg = <0x13e00000 0x1000>;
interrupts = <0 85 0>;
};
diff --git a/Bindings/media/i2c/imx274.txt b/Bindings/media/i2c/imx274.txt
new file mode 100644
index 000000000000..80f2e89568e1
--- /dev/null
+++ b/Bindings/media/i2c/imx274.txt
@@ -0,0 +1,33 @@
+* Sony 1/2.5-Inch 8.51Mp CMOS Digital Image Sensor
+
+The Sony imx274 is a 1/2.5-inch CMOS active pixel digital image sensor with
+an active array size of 3864H x 2202V. It is programmable through I2C
+interface. The I2C address is fixed to 0x1a as per sensor data sheet.
+Image data is sent through MIPI CSI-2, which is configured as 4 lanes
+at 1440 Mbps.
+
+
+Required Properties:
+- compatible: value should be "sony,imx274" for imx274 sensor
+- reg: I2C bus address of the device
+
+Optional Properties:
+- reset-gpios: Sensor reset GPIO
+
+The imx274 device node should contain one 'port' child node with
+an 'endpoint' subnode. For further reading on port node refer to
+Documentation/devicetree/bindings/media/video-interfaces.txt.
+
+Example:
+ sensor@1a {
+ compatible = "sony,imx274";
+ reg = <0x1a>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reset-gpios = <&gpio_sensor 0 0>;
+ port {
+ sensor_out: endpoint {
+ remote-endpoint = <&csiss_in>;
+ };
+ };
+ };
diff --git a/Bindings/media/i2c/nokia,smia.txt b/Bindings/media/i2c/nokia,smia.txt
index 855e1faf73e2..33f10a94c381 100644
--- a/Bindings/media/i2c/nokia,smia.txt
+++ b/Bindings/media/i2c/nokia,smia.txt
@@ -27,6 +27,8 @@ Optional properties
- nokia,nvm-size: The size of the NVM, in bytes. If the size is not given,
the NVM contents will not be read.
- reset-gpios: XSHUTDOWN GPIO
+- flash-leds: See ../video-interfaces.txt
+- lens-focus: See ../video-interfaces.txt
Endpoint node mandatory properties
diff --git a/Bindings/media/i2c/tc358743.txt b/Bindings/media/i2c/tc358743.txt
index 5218921629ed..49f8bcc2ea4d 100644
--- a/Bindings/media/i2c/tc358743.txt
+++ b/Bindings/media/i2c/tc358743.txt
@@ -27,7 +27,7 @@ Documentation/devicetree/bindings/media/video-interfaces.txt.
Example:
- tc358743@0f {
+ tc358743@f {
compatible = "toshiba,tc358743";
reg = <0x0f>;
clocks = <&hdmi_osc>;
diff --git a/Bindings/media/img-ir-rev1.txt b/Bindings/media/img-ir-rev1.txt
index 5434ce61b925..ed9ec52b77e0 100644
--- a/Bindings/media/img-ir-rev1.txt
+++ b/Bindings/media/img-ir-rev1.txt
@@ -25,7 +25,7 @@ Optional properties:
Example:
- ir@02006200 {
+ ir@2006200 {
compatible = "img,ir-rev1";
reg = <0x02006200 0x100>;
interrupts = <29 4>;
diff --git a/Bindings/media/mediatek-vcodec.txt b/Bindings/media/mediatek-vcodec.txt
index 46c15c54175d..2a615d84a682 100644
--- a/Bindings/media/mediatek-vcodec.txt
+++ b/Bindings/media/mediatek-vcodec.txt
@@ -68,7 +68,7 @@ vcodec_dec: vcodec@16000000 {
"vdec_bus_clk_src";
};
- vcodec_enc: vcodec@0x18002000 {
+ vcodec_enc: vcodec@18002000 {
compatible = "mediatek,mt8173-vcodec-enc";
reg = <0 0x18002000 0 0x1000>, /*VENC_SYS*/
<0 0x19002000 0 0x1000>; /*VENC_LT_SYS*/
diff --git a/Bindings/media/rcar_vin.txt b/Bindings/media/rcar_vin.txt
index 6e4ef8caf759..19357d0bbe65 100644
--- a/Bindings/media/rcar_vin.txt
+++ b/Bindings/media/rcar_vin.txt
@@ -44,7 +44,7 @@ Device node example
vin0 = &vin0;
};
- vin0: vin@0xe6ef0000 {
+ vin0: vin@e6ef0000 {
compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin";
clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
reg = <0 0xe6ef0000 0 0x1000>;
diff --git a/Bindings/media/renesas,vsp1.txt b/Bindings/media/renesas,vsp1.txt
index 9b695bcbf219..16427017cb45 100644
--- a/Bindings/media/renesas,vsp1.txt
+++ b/Bindings/media/renesas,vsp1.txt
@@ -22,7 +22,7 @@ Optional properties:
Example: R8A7790 (R-Car H2) VSP1-S node
- vsp1@fe928000 {
+ vsp@fe928000 {
compatible = "renesas,vsp1";
reg = <0 0xfe928000 0 0x8000>;
interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/Bindings/media/rockchip-rga.txt b/Bindings/media/rockchip-rga.txt
new file mode 100644
index 000000000000..fd5276abfad6
--- /dev/null
+++ b/Bindings/media/rockchip-rga.txt
@@ -0,0 +1,33 @@
+device-tree bindings for rockchip 2D raster graphic acceleration controller (RGA)
+
+RGA is a standalone 2D raster graphic acceleration unit. It accelerates 2D
+graphics operations, such as point/line drawing, image scaling, rotation,
+BitBLT, alpha blending and image blur/sharpness.
+
+Required properties:
+- compatible: value should be one of the following
+ "rockchip,rk3288-rga";
+ "rockchip,rk3399-rga";
+
+- interrupts: RGA interrupt specifier.
+
+- clocks: phandle to RGA sclk/hclk/aclk clocks
+
+- clock-names: should be "aclk", "hclk" and "sclk"
+
+- resets: Must contain an entry for each entry in reset-names.
+ See ../reset/reset.txt for details.
+- reset-names: should be "core", "axi" and "ahb"
+
+Example:
+SoC-specific DT entry:
+ rga: rga@ff680000 {
+ compatible = "rockchip,rk3399-rga";
+ reg = <0xff680000 0x10000>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
+ clock-names = "aclk", "hclk", "sclk";
+
+ resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
+ reset-names = "core, "axi", "ahb";
+ };
diff --git a/Bindings/media/samsung-fimc.txt b/Bindings/media/samsung-fimc.txt
index e4e15d8d7521..48c599dacbdf 100644
--- a/Bindings/media/samsung-fimc.txt
+++ b/Bindings/media/samsung-fimc.txt
@@ -138,7 +138,7 @@ Example:
};
/* MIPI CSI-2 bus IF sensor */
- s5c73m3: sensor@0x1a {
+ s5c73m3: sensor@1a {
compatible = "samsung,s5c73m3";
reg = <0x1a>;
vddio-supply = <...>;
diff --git a/Bindings/media/sh_mobile_ceu.txt b/Bindings/media/sh_mobile_ceu.txt
index 1ce4e46bcbb7..17a8e81ca0cc 100644
--- a/Bindings/media/sh_mobile_ceu.txt
+++ b/Bindings/media/sh_mobile_ceu.txt
@@ -8,7 +8,7 @@ Bindings, specific for the sh_mobile_ceu_camera.c driver:
Example:
-ceu0: ceu@0xfe910000 {
+ceu0: ceu@fe910000 {
compatible = "renesas,sh-mobile-ceu";
reg = <0xfe910000 0xa0>;
interrupt-parent = <&intcs>;
diff --git a/Bindings/media/stih-cec.txt b/Bindings/media/stih-cec.txt
index 8be2a040c6c6..ece0832fdeaf 100644
--- a/Bindings/media/stih-cec.txt
+++ b/Bindings/media/stih-cec.txt
@@ -13,7 +13,7 @@ Required properties:
Example for STIH407:
-sti-cec@094a087c {
+sti-cec@94a087c {
compatible = "st,stih-cec";
reg = <0x94a087c 0x64>;
clocks = <&clk_sysin>;
diff --git a/Bindings/media/stih407-c8sectpfe.txt b/Bindings/media/stih407-c8sectpfe.txt
index 6af3fc210ecc..c7888d6f6408 100644
--- a/Bindings/media/stih407-c8sectpfe.txt
+++ b/Bindings/media/stih407-c8sectpfe.txt
@@ -50,7 +50,7 @@ Example:
/* stih410 SoC b2120 + b2004a + stv0367-pll(NIMB) + stv0367-tda18212 (NIMA) DT example) */
- c8sectpfe@08a20000 {
+ c8sectpfe@8a20000 {
compatible = "st,stih407-c8sectpfe";
reg = <0x08a20000 0x10000>, <0x08a00000 0x4000>;
reg-names = "stfe", "stfe-ram";
diff --git a/Bindings/media/sunxi-ir.txt b/Bindings/media/sunxi-ir.txt
index 302a0b183cb8..91648c569b1e 100644
--- a/Bindings/media/sunxi-ir.txt
+++ b/Bindings/media/sunxi-ir.txt
@@ -14,7 +14,7 @@ Optional properties:
Example:
-ir0: ir@01c21800 {
+ir0: ir@1c21800 {
compatible = "allwinner,sun4i-a10-ir";
clocks = <&apb0_gates 6>, <&ir0_clk>;
clock-names = "apb", "ir";
diff --git a/Bindings/media/tango-ir.txt b/Bindings/media/tango-ir.txt
new file mode 100644
index 000000000000..a9f00c2bf897
--- /dev/null
+++ b/Bindings/media/tango-ir.txt
@@ -0,0 +1,21 @@
+Sigma Designs Tango IR NEC/RC-5/RC-6 decoder (SMP86xx and SMP87xx)
+
+Required properties:
+
+- compatible: "sigma,smp8642-ir"
+- reg: address/size of NEC+RC5 area, address/size of RC6 area
+- interrupts: spec for IR IRQ
+- clocks: spec for IR clock (typically the crystal oscillator)
+
+Optional properties:
+
+- linux,rc-map-name: see Documentation/devicetree/bindings/media/rc.txt
+
+Example:
+
+ ir@10518 {
+ compatible = "sigma,smp8642-ir";
+ reg = <0x10518 0x18>, <0x105e0 0x1c>;
+ interrupts = <21 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&xtal>;
+ };
diff --git a/Bindings/media/tegra-cec.txt b/Bindings/media/tegra-cec.txt
new file mode 100644
index 000000000000..c503f06f3b84
--- /dev/null
+++ b/Bindings/media/tegra-cec.txt
@@ -0,0 +1,27 @@
+* Tegra HDMI CEC hardware
+
+The HDMI CEC module is present in Tegra SoCs and its purpose is to
+handle communication between HDMI connected devices over the CEC bus.
+
+Required properties:
+ - compatible : value should be one of the following:
+ "nvidia,tegra114-cec"
+ "nvidia,tegra124-cec"
+ "nvidia,tegra210-cec"
+ - reg : Physical base address of the IP registers and length of memory
+ mapped region.
+ - interrupts : HDMI CEC interrupt number to the CPU.
+ - clocks : from common clock binding: handle to HDMI CEC clock.
+ - clock-names : from common clock binding: must contain "cec",
+ corresponding to the entry in the clocks property.
+ - hdmi-phandle : phandle to the HDMI controller, see also cec.txt.
+
+Example:
+
+cec@70015000 {
+ compatible = "nvidia,tegra124-cec";
+ reg = <0x0 0x70015000 0x0 0x00001000>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA124_CLK_CEC>;
+ clock-names = "cec";
+};
diff --git a/Bindings/media/video-interfaces.txt b/Bindings/media/video-interfaces.txt
index 852041a7480c..258b8dfddf48 100644
--- a/Bindings/media/video-interfaces.txt
+++ b/Bindings/media/video-interfaces.txt
@@ -55,6 +55,15 @@ divided into two separate ITU-R BT.656 8-bit busses. In such case bus-width
and data-shift properties can be used to assign physical data lines to each
endpoint node (logical bus).
+Documenting bindings for devices
+--------------------------------
+
+All required and optional bindings the device supports shall be explicitly
+documented in device DT binding documentation. This also includes port and
+endpoint nodes for the device, including unit-addresses and reg properties where
+relevant.
+
+Please also see Documentation/devicetree/bindings/graph.txt .
Required properties
-------------------
@@ -67,6 +76,16 @@ are required in a relevant parent node:
identifier, should be 1.
- #size-cells : should be zero.
+
+Optional properties
+-------------------
+
+- flash-leds: An array of phandles, each referring to a flash LED, a sub-node
+ of the LED driver device node.
+
+- lens-focus: A phandle to the node of the focus lens controller.
+
+
Optional endpoint properties
----------------------------
@@ -99,7 +118,10 @@ Optional endpoint properties
determines the logical lane number, while the value of an entry indicates
physical lane, e.g. for 2-lane MIPI CSI-2 bus we could have
"data-lanes = <1 2>;", assuming the clock lane is on hardware lane 0.
- This property is valid for serial busses only (e.g. MIPI CSI-2).
+ If the hardware does not support lane reordering, monotonically
+ incremented values shall be used from 0 or 1 onwards, depending on
+ whether or not there is also a clock lane. This property is valid for
+ serial busses only (e.g. MIPI CSI-2).
- clock-lanes: an array of physical clock lane indexes. Position of an entry
determines the logical lane number, while the value of an entry indicates
physical lane, e.g. for a MIPI CSI-2 bus we could have "clock-lanes = <0>;",
@@ -132,7 +154,7 @@ imx074 is linked to ceu0 through the MIPI CSI-2 receiver (csi2). ceu0 has a
'port' node which may indicate that at any time only one of the following data
pipelines can be active: ov772x -> ceu0 or imx074 -> csi2 -> ceu0.
- ceu0: ceu@0xfe910000 {
+ ceu0: ceu@fe910000 {
compatible = "renesas,sh-mobile-ceu";
reg = <0xfe910000 0xa0>;
interrupts = <0x880>;
@@ -171,9 +193,9 @@ pipelines can be active: ov772x -> ceu0 or imx074 -> csi2 -> ceu0.
};
};
- i2c0: i2c@0xfff20000 {
+ i2c0: i2c@fff20000 {
...
- ov772x_1: camera@0x21 {
+ ov772x_1: camera@21 {
compatible = "ovti,ov772x";
reg = <0x21>;
vddio-supply = <&regulator1>;
@@ -197,7 +219,7 @@ pipelines can be active: ov772x -> ceu0 or imx074 -> csi2 -> ceu0.
};
};
- imx074: camera@0x1a {
+ imx074: camera@1a {
compatible = "sony,imx074";
reg = <0x1a>;
vddio-supply = <&regulator1>;
@@ -217,7 +239,7 @@ pipelines can be active: ov772x -> ceu0 or imx074 -> csi2 -> ceu0.
};
};
- csi2: csi2@0xffc90000 {
+ csi2: csi2@ffc90000 {
compatible = "renesas,sh-mobile-csi2";
reg = <0xffc90000 0x1000>;
interrupts = <0x17a0>;
diff --git a/Bindings/memory-controllers/brcm,dpfe-cpu.txt b/Bindings/memory-controllers/brcm,dpfe-cpu.txt
new file mode 100644
index 000000000000..82d923ef413f
--- /dev/null
+++ b/Bindings/memory-controllers/brcm,dpfe-cpu.txt
@@ -0,0 +1,27 @@
+DDR PHY Front End (DPFE) for Broadcom STB
+=========================================
+
+DPFE and the DPFE firmware provide an interface for the host CPU to
+communicate with the DCPU, which resides inside the DDR PHY.
+
+There are three memory regions for interacting with the DCPU. These are
+specified in a single reg property.
+
+Required properties:
+ - compatible: must be "brcm,bcm7271-dpfe-cpu", "brcm,bcm7268-dpfe-cpu"
+ or "brcm,dpfe-cpu"
+ - reg: must reference three register ranges
+ - start address and length of the DCPU register space
+ - start address and length of the DCPU data memory space
+ - start address and length of the DCPU instruction memory space
+ - reg-names: must contain "dpfe-cpu", "dpfe-dmem", and "dpfe-imem";
+ they must be in the same order as the register declarations
+
+Example:
+ dpfe_cpu0: dpfe-cpu@f1132000 {
+ compatible = "brcm,bcm7271-dpfe-cpu", "brcm,dpfe-cpu";
+ reg = <0xf1132000 0x180
+ 0xf1134000 0x1000
+ 0xf1138000 0x4000>;
+ reg-names = "dpfe-cpu", "dpfe-dmem", "dpfe-imem";
+ };
diff --git a/Bindings/memory-controllers/ti/emif.txt b/Bindings/memory-controllers/ti/emif.txt
index 0db60470ebb6..152eeccbde1c 100644
--- a/Bindings/memory-controllers/ti/emif.txt
+++ b/Bindings/memory-controllers/ti/emif.txt
@@ -7,8 +7,10 @@ of the EMIF IP and memory parts attached to it.
Required properties:
- compatible : Should be of the form "ti,emif-<ip-rev>" where <ip-rev>
- is the IP revision of the specific EMIF instance.
- For am437x should be ti,emif-am4372.
+ is the IP revision of the specific EMIF instance. For newer controllers,
+ compatible should be one of the following:
+ "ti,emif-am3352"
+ "ti,emif-am4372"
- phy-type : <u32> indicating the DDR phy type. Following are the
allowed values
@@ -44,7 +46,7 @@ Optional properties:
Example:
-emif1: emif@0x4c000000 {
+emif1: emif@4c000000 {
compatible = "ti,emif-4d";
ti,hwmods = "emif2";
phy-type = <1>;
diff --git a/Bindings/mfd/arizona.txt b/Bindings/mfd/arizona.txt
index b37bdde5cfda..bdd017686ea5 100644
--- a/Bindings/mfd/arizona.txt
+++ b/Bindings/mfd/arizona.txt
@@ -65,45 +65,6 @@ Optional properties:
a value that is out of range for a 16 bit register then the chip default
will be used. If present exactly five values must be specified.
- - wlf,inmode : A list of INn_MODE register values, where n is the number
- of input signals. Valid values are 0 (Differential), 1 (Single-ended) and
- 2 (Digital Microphone). If absent, INn_MODE registers set to 0 by default.
- If present, values must be specified less than or equal to the number of
- input signals. If values less than the number of input signals, elements
- that have not been specified are set to 0 by default. Entries are:
- <IN1, IN2, IN3, IN4> (wm5102, wm5110, wm8280, wm8997)
- <IN1A, IN2A, IN1B, IN2B> (wm8998, wm1814)
- - wlf,out-mono : A list of boolean values indicating whether each output is
- mono or stereo. Position within the list indicates the output affected
- (eg. First entry in the list corresponds to output 1). A non-zero value
- indicates a mono output. If present, the number of values should be less
- than or equal to the number of outputs, if less values are supplied the
- additional outputs will be treated as stereo.
-
- - wlf,dmic-ref : DMIC reference voltage source for each input, can be
- selected from either MICVDD or one of the MICBIAS's, defines
- (ARIZONA_DMIC_xxxx) are provided in <dt-bindings/mfd/arizona.txt>. If
- present, the number of values should be less than or equal to the
- number of inputs, unspecified inputs will use the chip default.
-
- - wlf,max-channels-clocked : The maximum number of channels to be clocked on
- each AIF, useful for I2S systems with multiple data lines being mastered.
- Specify one cell for each AIF to be configured, specify zero for AIFs that
- should be handled normally.
- If present, number of cells must be less than or equal to the number of
- AIFs. If less than the number of AIFs, for cells that have not been
- specified the corresponding AIFs will be treated as default setting.
-
- - wlf,spk-fmt : PDM speaker data format, must contain 2 cells (OUT5 and OUT6).
- See the datasheet for values.
- The second cell is ignored for codecs that do not have OUT6 (wm5102, wm8997,
- wm8998, wm1814)
-
- - wlf,spk-mute : PDM speaker mute setting, must contain 2 cells (OUT5 and OUT6).
- See the datasheet for values.
- The second cell is ignored for codecs that do not have OUT6 (wm5102, wm8997,
- wm8998, wm1814)
-
- DCVDD-supply, MICVDD-supply : Power supplies, only need to be specified if
they are being externally supplied. As covered in
Documentation/devicetree/bindings/regulator/regulator.txt
@@ -112,6 +73,7 @@ Optional properties:
Also see child specific device properties:
Regulator - ../regulator/arizona-regulator.txt
Extcon - ../extcon/extcon-arizona.txt
+ Sound - ../sound/arizona.txt
Example:
diff --git a/Bindings/mfd/aspeed-scu.txt b/Bindings/mfd/aspeed-scu.txt
index 4fc5b83726d6..ce8cf0ec6279 100644
--- a/Bindings/mfd/aspeed-scu.txt
+++ b/Bindings/mfd/aspeed-scu.txt
@@ -9,10 +9,16 @@ Required properties:
"aspeed,g5-scu", "syscon", "simple-mfd"
- reg: contains the offset and length of the SCU memory region
+- #clock-cells: should be set to <1> - the system controller is also a
+ clock provider
+- #reset-cells: should be set to <1> - the system controller is also a
+ reset line provider
Example:
syscon: syscon@1e6e2000 {
compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd";
reg = <0x1e6e2000 0x1a8>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
};
diff --git a/Bindings/mfd/brcm,iproc-cdru.txt b/Bindings/mfd/brcm,iproc-cdru.txt
new file mode 100644
index 000000000000..82f82e069563
--- /dev/null
+++ b/Bindings/mfd/brcm,iproc-cdru.txt
@@ -0,0 +1,16 @@
+Broadcom iProc Chip Device Resource Unit (CDRU)
+
+Various Broadcom iProc SoCs have a set of registers that provide various
+chip specific device and resource configurations. This node allows access to
+these CDRU registers via syscon.
+
+Required properties:
+- compatible: should contain:
+ "brcm,sr-cdru", "syscon" for Stingray
+- reg: base address and range of the CDRU registers
+
+Example:
+ cdru: syscon@6641d000 {
+ compatible = "brcm,sr-cdru", "syscon";
+ reg = <0 0x6641d000 0 0x400>;
+ };
diff --git a/Bindings/mfd/brcm,iproc-mhb.txt b/Bindings/mfd/brcm,iproc-mhb.txt
new file mode 100644
index 000000000000..4421e9771b8a
--- /dev/null
+++ b/Bindings/mfd/brcm,iproc-mhb.txt
@@ -0,0 +1,18 @@
+Broadcom iProc Multi Host Bridge (MHB)
+
+Certain Broadcom iProc SoCs have a multi host bridge (MHB) block that controls
+the connection and configuration of 1) internal PCIe serdes; 2) PCIe endpoint
+interface; 3) access to the Nitro (network processing) engine
+
+This node allows access to these MHB registers via syscon.
+
+Required properties:
+- compatible: should contain:
+ "brcm,sr-mhb", "syscon" for Stingray
+- reg: base address and range of the MHB registers
+
+Example:
+ mhb: syscon@60401000 {
+ compatible = "brcm,sr-mhb", "syscon";
+ reg = <0 0x60401000 0 0x38c>;
+ };
diff --git a/Bindings/mfd/max77686.txt b/Bindings/mfd/max77686.txt
index 741e76688cf2..0f2587fa42cb 100644
--- a/Bindings/mfd/max77686.txt
+++ b/Bindings/mfd/max77686.txt
@@ -19,7 +19,7 @@ Required properties:
Example:
- max77686: pmic@09 {
+ max77686: pmic@9 {
compatible = "maxim,max77686";
interrupt-parent = <&wakeup_eint>;
interrupts = <26 0>;
diff --git a/Bindings/mfd/max77693.txt b/Bindings/mfd/max77693.txt
index 6a1ae3a2b77f..e6754974a745 100644
--- a/Bindings/mfd/max77693.txt
+++ b/Bindings/mfd/max77693.txt
@@ -127,6 +127,12 @@ Required properties for the LED child node:
Optional properties for the LED child node:
- label : see Documentation/devicetree/bindings/leds/common.txt
+Optional nodes:
+- max77693-muic :
+ Node used only by extcon consumers.
+ Required properties:
+ - compatible : "maxim,max77693-muic"
+
Example:
#include <dt-bindings/leds/common.h>
diff --git a/Bindings/mfd/max77802.txt b/Bindings/mfd/max77802.txt
index 51fc1a60caa5..f2f3fe75901c 100644
--- a/Bindings/mfd/max77802.txt
+++ b/Bindings/mfd/max77802.txt
@@ -18,7 +18,7 @@ Required properties:
Example:
- max77802: pmic@09 {
+ max77802: pmic@9 {
compatible = "maxim,max77802";
interrupt-parent = <&intc>;
interrupts = <26 IRQ_TYPE_NONE>;
diff --git a/Bindings/mfd/mc13xxx.txt b/Bindings/mfd/mc13xxx.txt
index 39ba4146769d..ac235fe385fc 100644
--- a/Bindings/mfd/mc13xxx.txt
+++ b/Bindings/mfd/mc13xxx.txt
@@ -113,7 +113,6 @@ MC13892 regulators:
Examples:
ecspi@70010000 { /* ECSPI1 */
- fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio4 24 0>, /* GPIO4_24 */
<&gpio4 25 0>; /* GPIO4_25 */
diff --git a/Bindings/mfd/mfd.txt b/Bindings/mfd/mfd.txt
index bcb6abb9d413..336c0495c8a3 100644
--- a/Bindings/mfd/mfd.txt
+++ b/Bindings/mfd/mfd.txt
@@ -41,7 +41,7 @@ foo@1000 {
compatible = "syscon", "simple-mfd";
reg = <0x01000 0x1000>;
- led@08.0 {
+ led@8.0 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x01>;
diff --git a/Bindings/mfd/sprd,sc27xx-pmic.txt b/Bindings/mfd/sprd,sc27xx-pmic.txt
new file mode 100644
index 000000000000..21b9a897fca5
--- /dev/null
+++ b/Bindings/mfd/sprd,sc27xx-pmic.txt
@@ -0,0 +1,40 @@
+Spreadtrum SC27xx Power Management Integrated Circuit (PMIC)
+
+The Spreadtrum SC27xx series PMICs contain SC2720, SC2721, SC2723, SC2730
+and SC2731. The Spreadtrum PMIC belonging to SC27xx series integrates all
+mobile handset power management, audio codec, battery management and user
+interface support function in a single chip. It has 6 major functional
+blocks:
+- DCDCs to support CPU, memory.
+- LDOs to support both internal and external requirement.
+- Battery management system, such as charger, fuel gauge.
+- Audio codec.
+- User interface function, such as indicator, flash LED and so on.
+- IC level interface, such as power on/off control, RTC and typec and so on.
+
+Required properties:
+- compatible: Should be one of the following:
+ "sprd,sc2720"
+ "sprd,sc2721"
+ "sprd,sc2723"
+ "sprd,sc2730"
+ "sprd,sc2731"
+- reg: The address of the device chip select, should be 0.
+- spi-max-frequency: Typically set to 26000000.
+- interrupts: The interrupt line the device is connected to.
+- interrupt-controller: Marks the device node as an interrupt controller.
+- #interrupt-cells: The number of cells to describe an PMIC IRQ, must be 2.
+- #address-cells: Child device offset number of cells, must be 1.
+- #size-cells: Child device size number of cells, must be 0.
+
+Example:
+pmic@0 {
+ compatible = "sprd,sc2731";
+ reg = <0>;
+ spi-max-frequency = <26000000>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+};
diff --git a/Bindings/mfd/sun4i-gpadc.txt b/Bindings/mfd/sun4i-gpadc.txt
index badff3611a98..86dd8191b04c 100644
--- a/Bindings/mfd/sun4i-gpadc.txt
+++ b/Bindings/mfd/sun4i-gpadc.txt
@@ -10,7 +10,7 @@ Required properties:
- #io-channel-cells: shall be 0,
Example:
- ths: ths@01c25000 {
+ ths: ths@1c25000 {
compatible = "allwinner,sun8i-a33-ths";
reg = <0x01c25000 0x100>;
#thermal-sensor-cells = <0>;
@@ -47,7 +47,7 @@ Optional properties:
Example:
- rtp: rtp@01c25000 {
+ rtp: rtp@1c25000 {
compatible = "allwinner,sun4i-a10-ts";
reg = <0x01c25000 0x100>;
interrupts = <29>;
diff --git a/Bindings/mfd/sun6i-prcm.txt b/Bindings/mfd/sun6i-prcm.txt
index 03c5a551da55..dd2c06540485 100644
--- a/Bindings/mfd/sun6i-prcm.txt
+++ b/Bindings/mfd/sun6i-prcm.txt
@@ -15,7 +15,7 @@ The prcm node may contain several subdevices definitions:
Example:
- prcm: prcm@01f01400 {
+ prcm: prcm@1f01400 {
compatible = "allwinner,sun6i-a31-prcm";
reg = <0x01f01400 0x200>;
diff --git a/Bindings/mfd/syscon.txt b/Bindings/mfd/syscon.txt
index 408f768686f1..8b92d4576c42 100644
--- a/Bindings/mfd/syscon.txt
+++ b/Bindings/mfd/syscon.txt
@@ -18,7 +18,7 @@ Optional property:
performed on the device.
Examples:
-gpr: iomuxc-gpr@020e0000 {
+gpr: iomuxc-gpr@20e0000 {
compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
reg = <0x020e0000 0x38>;
};
diff --git a/Bindings/mfd/ti-keystone-devctrl.txt b/Bindings/mfd/ti-keystone-devctrl.txt
index 20963c76b4bc..71a1f5963936 100644
--- a/Bindings/mfd/ti-keystone-devctrl.txt
+++ b/Bindings/mfd/ti-keystone-devctrl.txt
@@ -13,7 +13,7 @@ Required properties:
Example:
-devctrl: device-state-control@0x02620000 {
+devctrl: device-state-control@02620000 {
compatible = "ti,keystone-devctrl", "syscon";
reg = <0x02620000 0x1000>;
};
diff --git a/Bindings/mips/brcm/soc.txt b/Bindings/mips/brcm/soc.txt
index e4e1cd91fb1f..356c29789cf5 100644
--- a/Bindings/mips/brcm/soc.txt
+++ b/Bindings/mips/brcm/soc.txt
@@ -11,3 +11,156 @@ Required properties:
The experimental -viper variants are for running Linux on the 3384's
BMIPS4355 cable modem CPU instead of the BMIPS5000 application processor.
+
+Power management
+----------------
+
+For power management (particularly, S2/S3/S5 system suspend), the following SoC
+components are needed:
+
+= Always-On control block (AON CTRL)
+
+This hardware provides control registers for the "always-on" (even in low-power
+modes) hardware, such as the Power Management State Machine (PMSM).
+
+Required properties:
+- compatible : should be one of
+ "brcm,bcm7425-aon-ctrl"
+ "brcm,bcm7429-aon-ctrl"
+ "brcm,bcm7435-aon-ctrl" and
+ "brcm,brcmstb-aon-ctrl"
+- reg : the register start and length for the AON CTRL block
+
+Example:
+
+syscon@410000 {
+ compatible = "brcm,bcm7425-aon-ctrl", "brcm,brcmstb-aon-ctrl";
+ reg = <0x410000 0x400>;
+};
+
+= Memory controllers
+
+A Broadcom STB SoC typically has a number of independent memory controllers,
+each of which may have several associated hardware blocks, which are versioned
+independently (control registers, DDR PHYs, etc.). One might consider
+describing these controllers as a parent "memory controllers" block, which
+contains N sub-nodes (one for each controller in the system), each of which is
+associated with a number of hardware register resources (e.g., its PHY.
+
+== MEMC (MEMory Controller)
+
+Represents a single memory controller instance.
+
+Required properties:
+- compatible : should contain "brcm,brcmstb-memc" and "simple-bus"
+- ranges : should contain the child address in the parent address
+ space, must be 0 here, and the register start and length of
+ the entire memory controller (including all sub nodes: DDR PHY,
+ arbiter, etc.)
+- #address-cells : must be 1
+- #size-cells : must be 1
+
+Example:
+
+ memory-controller@0 {
+ compatible = "brcm,brcmstb-memc", "simple-bus";
+ ranges = <0x0 0x0 0xa000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ memc-arb@1000 {
+ ...
+ };
+
+ memc-ddr@2000 {
+ ...
+ };
+
+ ddr-phy@6000 {
+ ...
+ };
+ };
+
+Should contain subnodes for any of the following relevant hardware resources:
+
+== DDR PHY control
+
+Control registers for this memory controller's DDR PHY.
+
+Required properties:
+- compatible : should contain one of these
+ "brcm,brcmstb-ddr-phy-v64.5"
+ "brcm,brcmstb-ddr-phy"
+
+- reg : the DDR PHY register range and length
+
+Example:
+
+ ddr-phy@6000 {
+ compatible = "brcm,brcmstb-ddr-phy-v64.5";
+ reg = <0x6000 0xc8>;
+ };
+
+== DDR memory controller sequencer
+
+Control registers for this memory controller's DDR memory sequencer
+
+Required properties:
+- compatible : should contain one of these
+ "brcm,bcm7425-memc-ddr"
+ "brcm,bcm7429-memc-ddr"
+ "brcm,bcm7435-memc-ddr" and
+ "brcm,brcmstb-memc-ddr"
+
+- reg : the DDR sequencer register range and length
+
+Example:
+
+ memc-ddr@2000 {
+ compatible = "brcm,bcm7425-memc-ddr", "brcm,brcmstb-memc-ddr";
+ reg = <0x2000 0x300>;
+ };
+
+== MEMC Arbiter
+
+The memory controller arbiter is responsible for memory clients allocation
+(bandwidth, priorities etc.) and needs to have its contents restored during
+deep sleep states (S3).
+
+Required properties:
+
+- compatible : should contain one of these
+ "brcm,brcmstb-memc-arb-v10.0.0.0"
+ "brcm,brcmstb-memc-arb"
+
+- reg : the DDR Arbiter register range and length
+
+Example:
+
+ memc-arb@1000 {
+ compatible = "brcm,brcmstb-memc-arb-v10.0.0.0";
+ reg = <0x1000 0x248>;
+ };
+
+== Timers
+
+The Broadcom STB chips contain a timer block with several general purpose
+timers that can be used.
+
+Required properties:
+
+- compatible : should contain one of:
+ "brcm,bcm7425-timers"
+ "brcm,bcm7429-timers"
+ "brcm,bcm7435-timers and
+ "brcm,brcmstb-timers"
+- reg : the timers register range
+- interrupts : the interrupt line for this timer block
+
+Example:
+
+ timers: timer@4067c0 {
+ compatible = "brcm,bcm7425-timers", "brcm,brcmstb-timers";
+ reg = <0x4067c0 0x40>;
+ interrupts = <&periph_intc 19>;
+ };
diff --git a/Bindings/misc/brcm,kona-smc.txt b/Bindings/misc/brcm,kona-smc.txt
index 6c9f176f3571..05b47232ed9e 100644
--- a/Bindings/misc/brcm,kona-smc.txt
+++ b/Bindings/misc/brcm,kona-smc.txt
@@ -9,7 +9,7 @@ Required properties:
- reg : Location and size of bounce buffer
Example:
- smc@0x3404c000 {
+ smc@3404c000 {
compatible = "brcm,bcm11351-smc", "brcm,kona-smc";
reg = <0x3404c000 0x400>; //1 KiB in SRAM
};
diff --git a/Bindings/misc/ge-achc.txt b/Bindings/misc/ge-achc.txt
new file mode 100644
index 000000000000..77df94d7a32f
--- /dev/null
+++ b/Bindings/misc/ge-achc.txt
@@ -0,0 +1,26 @@
+* GE Healthcare USB Management Controller
+
+A device which handles data aquisition from compatible USB based peripherals.
+SPI is used for device management.
+
+Note: This device does not expose the peripherals as USB devices.
+
+Required properties:
+
+- compatible : Should be "ge,achc"
+
+Required SPI properties:
+
+- reg : Should be address of the device chip select within
+ the controller.
+
+- spi-max-frequency : Maximum SPI clocking speed of device in Hz, should be
+ 1MHz for the GE ACHC.
+
+Example:
+
+spidev0: spi@0 {
+ compatible = "ge,achc";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+};
diff --git a/Bindings/mmc/amlogic,meson-mx-sdio.txt b/Bindings/mmc/amlogic,meson-mx-sdio.txt
new file mode 100644
index 000000000000..8765c605e6bc
--- /dev/null
+++ b/Bindings/mmc/amlogic,meson-mx-sdio.txt
@@ -0,0 +1,54 @@
+* Amlogic Meson6, Meson8 and Meson8b SDIO/MMC controller
+
+The highspeed MMC host controller on Amlogic SoCs provides an interface
+for MMC, SD, SDIO and SDHC types of memory cards.
+
+Supported maximum speeds are the ones of the eMMC standard 4.41 as well
+as the speed of SD standard 2.0.
+
+The hardware provides an internal "mux" which allows up to three slots
+to be controlled. Only one slot can be accessed at a time.
+
+Required properties:
+ - compatible : must be one of
+ - "amlogic,meson8-sdio"
+ - "amlogic,meson8b-sdio"
+ along with the generic "amlogic,meson-mx-sdio"
+ - reg : mmc controller base registers
+ - interrupts : mmc controller interrupt
+ - #address-cells : must be 1
+ - size-cells : must be 0
+ - clocks : phandle to clock providers
+ - clock-names : must contain "core" and "clkin"
+
+Required child nodes:
+A node for each slot provided by the MMC controller is required.
+NOTE: due to a driver limitation currently only one slot (= child node)
+ is supported!
+
+Required properties on each child node (= slot):
+ - compatible : must be "mmc-slot" (see mmc.txt within this directory)
+ - reg : the slot (or "port") ID
+
+Optional properties on each child node (= slot):
+ - bus-width : must be 1 or 4 (8-bit bus is not supported)
+ - for cd and all other additional generic mmc parameters
+ please refer to mmc.txt within this directory
+
+Examples:
+ mmc@c1108c20 {
+ compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio";
+ reg = <0xc1108c20 0x20>;
+ interrupts = <0 28 1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
+ clock-names = "core", "clkin";
+
+ slot@1 {
+ compatible = "mmc-slot";
+ reg = <1>;
+
+ bus-width = <4>;
+ };
+ };
diff --git a/Bindings/mmc/brcm,kona-sdhci.txt b/Bindings/mmc/brcm,kona-sdhci.txt
index aaba2483b4ff..7f5dd83f5bd9 100644
--- a/Bindings/mmc/brcm,kona-sdhci.txt
+++ b/Bindings/mmc/brcm,kona-sdhci.txt
@@ -12,7 +12,7 @@ Refer to clocks/clock-bindings.txt for generic clock consumer properties.
Example:
-sdio2: sdio@0x3f1a0000 {
+sdio2: sdio@3f1a0000 {
compatible = "brcm,kona-sdhci";
reg = <0x3f1a0000 0x10000>;
clocks = <&sdio3_clk>;
diff --git a/Bindings/mmc/brcm,sdhci-iproc.txt b/Bindings/mmc/brcm,sdhci-iproc.txt
index 954561d09a8e..fa90d253dc7e 100644
--- a/Bindings/mmc/brcm,sdhci-iproc.txt
+++ b/Bindings/mmc/brcm,sdhci-iproc.txt
@@ -24,7 +24,7 @@ Optional properties:
Example:
-sdhci0: sdhci@0x18041000 {
+sdhci0: sdhci@18041000 {
compatible = "brcm,sdhci-iproc-cygnus";
reg = <0x18041000 0x100>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/Bindings/mmc/mmc.txt b/Bindings/mmc/mmc.txt
index b32ade645ad9..fb11ae8b3b72 100644
--- a/Bindings/mmc/mmc.txt
+++ b/Bindings/mmc/mmc.txt
@@ -53,6 +53,9 @@ Optional properties:
- no-sdio: controller is limited to send sdio cmd during initialization
- no-sd: controller is limited to send sd cmd during initialization
- no-mmc: controller is limited to send mmc cmd during initialization
+- fixed-emmc-driver-type: for non-removable eMMC, enforce this driver type.
+ The value <n> is the driver type as specified in the eMMC specification
+ (table 206 in spec version 5.1).
*NOTE* on CD and WP polarity. To use common for all SD/MMC host controllers line
polarity properties, we have to fix the meaning of the "normal" and "inverted"
@@ -143,7 +146,7 @@ sdhci@ab000000 {
Example with sdio function subnode:
-mmc3: mmc@01c12000 {
+mmc3: mmc@1c12000 {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/Bindings/mmc/mtk-sd.txt b/Bindings/mmc/mtk-sd.txt
index 4182ea36ca5b..72d2a734ab85 100644
--- a/Bindings/mmc/mtk-sd.txt
+++ b/Bindings/mmc/mtk-sd.txt
@@ -7,10 +7,18 @@ This file documents differences between the core properties in mmc.txt
and the properties used by the msdc driver.
Required properties:
-- compatible: Should be "mediatek,mt8173-mmc","mediatek,mt8135-mmc"
+- compatible: value should be either of the following.
+ "mediatek,mt8135-mmc": for mmc host ip compatible with mt8135
+ "mediatek,mt8173-mmc": for mmc host ip compatible with mt8173
+ "mediatek,mt2701-mmc": for mmc host ip compatible with mt2701
+ "mediatek,mt2712-mmc": for mmc host ip compatible with mt2712
+- reg: physical base address of the controller and length
- interrupts: Should contain MSDC interrupt number
-- clocks: MSDC source clock, HCLK
-- clock-names: "source", "hclk"
+- clocks: Should contain phandle for the clock feeding the MMC controller
+- clock-names: Should contain the following:
+ "source" - source clock (required)
+ "hclk" - HCLK which used for host (required)
+ "source_cg" - independent source clock gate (required for MT2712)
- pinctrl-names: should be "default", "state_uhs"
- pinctrl-0: should contain default/high speed pin ctrl
- pinctrl-1: should contain uhs mode pin ctrl
@@ -30,6 +38,10 @@ Optional properties:
- mediatek,hs400-cmd-resp-sel-rising: HS400 command response sample selection
If present,HS400 command responses are sampled on rising edges.
If not present,HS400 command responses are sampled on falling edges.
+- mediatek,latch-ck: Some SoCs do not support enhance_rx, need set correct latch-ck to avoid data crc
+ error caused by stop clock(fifo full)
+ Valid range = [0:0x7]. if not present, default value is 0.
+ applied to compatible "mediatek,mt2701-mmc".
Examples:
mmc0: mmc@11230000 {
diff --git a/Bindings/mmc/sdhci-fujitsu.txt b/Bindings/mmc/sdhci-fujitsu.txt
index de2c53cff4f1..3ee9263adf73 100644
--- a/Bindings/mmc/sdhci-fujitsu.txt
+++ b/Bindings/mmc/sdhci-fujitsu.txt
@@ -15,6 +15,8 @@ Required properties:
Optional properties:
- vqmmc-supply: phandle to the regulator device tree node, mentioned
as the VCCQ/VDD_IO supply in the eMMC/SD specs.
+- fujitsu,cmd-dat-delay-select: boolean property indicating that this host
+ requires the CMD_DAT_DELAY control to be enabled.
Example:
diff --git a/Bindings/mmc/sdhci-msm.txt b/Bindings/mmc/sdhci-msm.txt
index 0576264eab5e..bfdcdc4ccdff 100644
--- a/Bindings/mmc/sdhci-msm.txt
+++ b/Bindings/mmc/sdhci-msm.txt
@@ -18,6 +18,8 @@ Required properties:
"core" - SDC MMC clock (MCLK) (required)
"bus" - SDCC bus voter clock (optional)
"xo" - TCXO clock (optional)
+ "cal" - reference clock for RCLK delay calibration (optional)
+ "sleep" - sleep clock for RCLK delay calibration (optional)
Example:
diff --git a/Bindings/mmc/sdhci-omap.txt b/Bindings/mmc/sdhci-omap.txt
new file mode 100644
index 000000000000..51775a372c06
--- /dev/null
+++ b/Bindings/mmc/sdhci-omap.txt
@@ -0,0 +1,16 @@
+* TI OMAP SDHCI Controller
+
+Refer to mmc.txt for standard MMC bindings.
+
+Required properties:
+- compatible: Should be "ti,dra7-sdhci" for DRA7 and DRA72 controllers
+- ti,hwmods: Must be "mmc<n>", <n> is controller instance starting 1
+
+Example:
+ mmc1: mmc@4809c000 {
+ compatible = "ti,dra7-sdhci";
+ reg = <0x4809c000 0x400>;
+ ti,hwmods = "mmc1";
+ bus-width = <4>;
+ vmmc-supply = <&vmmc>; /* phandle to regulator node */
+ };
diff --git a/Bindings/mmc/sdhci-st.txt b/Bindings/mmc/sdhci-st.txt
index e35645598315..6b3d40ca395e 100644
--- a/Bindings/mmc/sdhci-st.txt
+++ b/Bindings/mmc/sdhci-st.txt
@@ -74,7 +74,7 @@ mmc0: sdhci@fe81e000 {
/* Example SD stih407 family configuration */
-mmc1: sdhci@09080000 {
+mmc1: sdhci@9080000 {
compatible = "st,sdhci-stih407", "st,sdhci";
reg = <0x09080000 0x7ff>;
reg-names = "mmc";
@@ -90,7 +90,7 @@ mmc1: sdhci@09080000 {
/* Example eMMC stih407 family configuration */
-mmc0: sdhci@09060000 {
+mmc0: sdhci@9060000 {
compatible = "st,sdhci-stih407", "st,sdhci";
reg = <0x09060000 0x7ff>, <0x9061008 0x20>;
reg-names = "mmc", "top-mmc-delay";
diff --git a/Bindings/mmc/sunxi-mmc.txt b/Bindings/mmc/sunxi-mmc.txt
index 63b57e2a10fb..132e0007d7d6 100644
--- a/Bindings/mmc/sunxi-mmc.txt
+++ b/Bindings/mmc/sunxi-mmc.txt
@@ -29,7 +29,7 @@ Optional properties:
Examples:
- Within .dtsi:
- mmc0: mmc@01c0f000 {
+ mmc0: mmc@1c0f000 {
compatible = "allwinner,sun5i-a13-mmc";
reg = <0x01c0f000 0x1000>;
clocks = <&ahb_gates 8>, <&mmc0_clk>, <&mmc0_output_clk>, <&mmc0_sample_clk>;
@@ -39,7 +39,7 @@ Examples:
};
- Within dts:
- mmc0: mmc@01c0f000 {
+ mmc0: mmc@1c0f000 {
pinctrl-names = "default", "default";
pinctrl-0 = <&mmc0_pins_a>;
pinctrl-1 = <&mmc0_cd_pin_reference_design>;
diff --git a/Bindings/mmc/ti-omap-hsmmc.txt b/Bindings/mmc/ti-omap-hsmmc.txt
index 3a4ac401e6f9..19f5508a7569 100644
--- a/Bindings/mmc/ti-omap-hsmmc.txt
+++ b/Bindings/mmc/ti-omap-hsmmc.txt
@@ -55,7 +55,7 @@ Examples:
[hwmod populated DMA resources]
- mmc1: mmc@0x4809c000 {
+ mmc1: mmc@4809c000 {
compatible = "ti,omap4-hsmmc";
reg = <0x4809c000 0x400>;
ti,hwmods = "mmc1";
@@ -67,7 +67,7 @@ Examples:
[generic DMA request binding]
- mmc1: mmc@0x4809c000 {
+ mmc1: mmc@4809c000 {
compatible = "ti,omap4-hsmmc";
reg = <0x4809c000 0x400>;
ti,hwmods = "mmc1";
diff --git a/Bindings/mmc/tmio_mmc.txt b/Bindings/mmc/tmio_mmc.txt
index 54ef642f23a0..3c6762430fd9 100644
--- a/Bindings/mmc/tmio_mmc.txt
+++ b/Bindings/mmc/tmio_mmc.txt
@@ -10,7 +10,7 @@ described in mmc.txt, can be used. Additionally the following tmio_mmc-specific
optional bindings can be used.
Required properties:
-- compatible: "renesas,sdhi-shmobile" - a generic sh-mobile SDHI unit
+- compatible: should contain one or more of the following:
"renesas,sdhi-sh73a0" - SDHI IP on SH73A0 SoC
"renesas,sdhi-r7s72100" - SDHI IP on R7S72100 SoC
"renesas,sdhi-r8a73a4" - SDHI IP on R8A73A4 SoC
@@ -26,6 +26,16 @@ Required properties:
"renesas,sdhi-r8a7794" - SDHI IP on R8A7794 SoC
"renesas,sdhi-r8a7795" - SDHI IP on R8A7795 SoC
"renesas,sdhi-r8a7796" - SDHI IP on R8A7796 SoC
+ "renesas,sdhi-shmobile" - a generic sh-mobile SDHI controller
+ "renesas,rcar-gen1-sdhi" - a generic R-Car Gen1 SDHI controller
+ "renesas,rcar-gen2-sdhi" - a generic R-Car Gen2 or RZ/G1
+ SDHI controller
+ "renesas,rcar-gen3-sdhi" - a generic R-Car Gen3 SDHI controller
+
+
+ When compatible with the generic version, nodes must list
+ the SoC-specific version corresponding to the platform
+ first followed by the generic version.
- clocks: Most controllers only have 1 clock source per channel. However, on
some variations of this controller, the internal card detection
@@ -43,3 +53,61 @@ Optional properties:
- pinctrl-names: should be "default", "state_uhs"
- pinctrl-0: should contain default/high speed pin ctrl
- pinctrl-1: should contain uhs mode pin ctrl
+
+Example: R8A7790 (R-Car H2) SDHI controller nodes
+
+ sdhi0: sd@ee100000 {
+ compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
+ reg = <0 0xee100000 0 0x328>;
+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 314>;
+ dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
+ <&dmac1 0xcd>, <&dmac1 0xce>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <195000000>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 314>;
+ status = "disabled";
+ };
+
+ sdhi1: sd@ee120000 {
+ compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
+ reg = <0 0xee120000 0 0x328>;
+ interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 313>;
+ dmas = <&dmac0 0xc9>, <&dmac0 0xca>,
+ <&dmac1 0xc9>, <&dmac1 0xca>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <195000000>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 313>;
+ status = "disabled";
+ };
+
+ sdhi2: sd@ee140000 {
+ compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
+ reg = <0 0xee140000 0 0x100>;
+ interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 312>;
+ dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
+ <&dmac1 0xc1>, <&dmac1 0xc2>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <97500000>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 312>;
+ status = "disabled";
+ };
+
+ sdhi3: sd@ee160000 {
+ compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
+ reg = <0 0xee160000 0 0x100>;
+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 311>;
+ dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
+ <&dmac1 0xd3>, <&dmac1 0xd4>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <97500000>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 311>;
+ status = "disabled";
+ };
diff --git a/Bindings/mtd/cadence-quadspi.txt b/Bindings/mtd/cadence-quadspi.txt
index f248056da24c..bb2075df9b38 100644
--- a/Bindings/mtd/cadence-quadspi.txt
+++ b/Bindings/mtd/cadence-quadspi.txt
@@ -1,7 +1,9 @@
* Cadence Quad SPI controller
Required properties:
-- compatible : Should be "cdns,qspi-nor".
+- compatible : should be one of the following:
+ Generic default - "cdns,qspi-nor".
+ For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor".
- reg : Contains two entries, each of which is a tuple consisting of a
physical address and length. The first entry is the address and
length of the controller register set. The second entry is the
@@ -14,6 +16,9 @@ Required properties:
Optional properties:
- cdns,is-decoded-cs : Flag to indicate whether decoder is used or not.
+- cdns,rclk-en : Flag to indicate that QSPI return clock is used to latch
+ the read data rather than the QSPI clock. Make sure that QSPI return
+ clock is populated on the board before using this property.
Optional subnodes:
Subnodes of the Cadence Quad SPI controller are spi slave nodes with additional
diff --git a/Bindings/mtd/denali-nand.txt b/Bindings/mtd/denali-nand.txt
index 504291d2e5c2..0ee8edb60efc 100644
--- a/Bindings/mtd/denali-nand.txt
+++ b/Bindings/mtd/denali-nand.txt
@@ -29,7 +29,7 @@ nand: nand@ff900000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "altr,socfpga-denali-nand";
- reg = <0xff900000 0x100000>, <0xffb80000 0x10000>;
+ reg = <0xff900000 0x20>, <0xffb80000 0x1000>;
reg-names = "nand_data", "denali_reg";
interrupts = <0 144 4>;
};
diff --git a/Bindings/mtd/gpmc-nor.txt b/Bindings/mtd/gpmc-nor.txt
index 131d3a74d0bd..c8567b40fe13 100644
--- a/Bindings/mtd/gpmc-nor.txt
+++ b/Bindings/mtd/gpmc-nor.txt
@@ -82,15 +82,15 @@ gpmc: gpmc@6e000000 {
label = "bootloader-nor";
reg = <0 0x40000>;
};
- partition@0x40000 {
+ partition@40000 {
label = "params-nor";
reg = <0x40000 0x40000>;
};
- partition@0x80000 {
+ partition@80000 {
label = "kernel-nor";
reg = <0x80000 0x200000>;
};
- partition@0x280000 {
+ partition@280000 {
label = "filesystem-nor";
reg = <0x240000 0x7d80000>;
};
diff --git a/Bindings/mtd/jedec,spi-nor.txt b/Bindings/mtd/jedec,spi-nor.txt
index 9ce35af8507c..956bb046e599 100644
--- a/Bindings/mtd/jedec,spi-nor.txt
+++ b/Bindings/mtd/jedec,spi-nor.txt
@@ -13,6 +13,7 @@ Required properties:
at25df321a
at25df641
at26df081a
+ mr25h128
mr25h256
mr25h10
mr25h40
diff --git a/Bindings/mtd/mtk-nand.txt b/Bindings/mtd/mtk-nand.txt
index dbf9e054c11c..0431841de781 100644
--- a/Bindings/mtd/mtk-nand.txt
+++ b/Bindings/mtd/mtk-nand.txt
@@ -131,7 +131,7 @@ Example:
read-only;
reg = <0x00000000 0x00400000>;
};
- android@0x00400000 {
+ android@00400000 {
label = "android";
reg = <0x00400000 0x12c00000>;
};
diff --git a/Bindings/mtd/mtk-quadspi.txt b/Bindings/mtd/mtk-quadspi.txt
index 840f9405dcf0..56d3668e2c50 100644
--- a/Bindings/mtd/mtk-quadspi.txt
+++ b/Bindings/mtd/mtk-quadspi.txt
@@ -1,13 +1,16 @@
* Serial NOR flash controller for MTK MT81xx (and similar)
Required properties:
-- compatible: The possible values are:
- "mediatek,mt2701-nor"
- "mediatek,mt7623-nor"
+- compatible: For mt8173, compatible should be "mediatek,mt8173-nor",
+ and it's the fallback compatible for other Soc.
+ For every other SoC, should contain both the SoC-specific compatible
+ string and "mediatek,mt8173-nor".
+ The possible values are:
+ "mediatek,mt2701-nor", "mediatek,mt8173-nor"
+ "mediatek,mt2712-nor", "mediatek,mt8173-nor"
+ "mediatek,mt7622-nor", "mediatek,mt8173-nor"
+ "mediatek,mt7623-nor", "mediatek,mt8173-nor"
"mediatek,mt8173-nor"
- For mt8173, compatible should be "mediatek,mt8173-nor".
- For every other SoC, should contain both the SoC-specific compatible string
- and "mediatek,mt8173-nor".
- reg: physical base address and length of the controller's register
- clocks: the phandle of the clocks needed by the nor controller
- clock-names: the names of the clocks
diff --git a/Bindings/mtd/pxa3xx-nand.txt b/Bindings/mtd/pxa3xx-nand.txt
index d9b655f11048..d4ee4da58463 100644
--- a/Bindings/mtd/pxa3xx-nand.txt
+++ b/Bindings/mtd/pxa3xx-nand.txt
@@ -5,9 +5,13 @@ Required properties:
- compatible: Should be set to one of the following:
marvell,pxa3xx-nand
marvell,armada370-nand
+ marvell,armada-8k-nand
- reg: The register base for the controller
- interrupts: The interrupt to map
- #address-cells: Set to <1> if the node includes partitions
+ - marvell,system-controller: Set to retrieve the syscon node that handles
+ NAND controller related registers (only required
+ with marvell,armada-8k-nand compatible).
Optional properties:
diff --git a/Bindings/mtd/sunxi-nand.txt b/Bindings/mtd/sunxi-nand.txt
index a37c67bcb43b..5e13a5cdff03 100644
--- a/Bindings/mtd/sunxi-nand.txt
+++ b/Bindings/mtd/sunxi-nand.txt
@@ -31,7 +31,7 @@ see Documentation/devicetree/bindings/mtd/nand.txt for generic bindings.
Examples:
-nfc: nand@01c03000 {
+nfc: nand@1c03000 {
compatible = "allwinner,sun4i-a10-nand";
reg = <0x01c03000 0x1000>;
interrupts = <0 37 1>;
diff --git a/Bindings/net/allwinner,sun4i-emac.txt b/Bindings/net/allwinner,sun4i-emac.txt
index 10640b17c866..e98118aef5f6 100644
--- a/Bindings/net/allwinner,sun4i-emac.txt
+++ b/Bindings/net/allwinner,sun4i-emac.txt
@@ -10,7 +10,7 @@ Required properties:
Example:
-emac: ethernet@01c0b000 {
+emac: ethernet@1c0b000 {
compatible = "allwinner,sun4i-a10-emac";
reg = <0x01c0b000 0x1000>;
interrupts = <55>;
diff --git a/Bindings/net/allwinner,sun4i-mdio.txt b/Bindings/net/allwinner,sun4i-mdio.txt
index 4ec56413779d..ab5b8613b0ef 100644
--- a/Bindings/net/allwinner,sun4i-mdio.txt
+++ b/Bindings/net/allwinner,sun4i-mdio.txt
@@ -9,7 +9,7 @@ Optional properties:
- phy-supply: phandle to a regulator if the PHY needs one
Example at the SoC level:
-mdio@01c0b080 {
+mdio@1c0b080 {
compatible = "allwinner,sun4i-a10-mdio";
reg = <0x01c0b080 0x14>;
#address-cells = <1>;
@@ -18,7 +18,7 @@ mdio@01c0b080 {
And at the board level:
-mdio@01c0b080 {
+mdio@1c0b080 {
phy-supply = <&reg_emac_3v3>;
phy0: ethernet-phy@0 {
diff --git a/Bindings/net/allwinner,sun7i-a20-gmac.txt b/Bindings/net/allwinner,sun7i-a20-gmac.txt
index ea4d752389a2..8b3f953656e3 100644
--- a/Bindings/net/allwinner,sun7i-a20-gmac.txt
+++ b/Bindings/net/allwinner,sun7i-a20-gmac.txt
@@ -15,7 +15,7 @@ Optional properties:
Examples:
- gmac: ethernet@01c50000 {
+ gmac: ethernet@1c50000 {
compatible = "allwinner,sun7i-a20-gmac";
reg = <0x01c50000 0x10000>,
<0x01c20164 0x4>;
diff --git a/Bindings/net/altera_tse.txt b/Bindings/net/altera_tse.txt
index a706297998e9..0e21df94a53f 100644
--- a/Bindings/net/altera_tse.txt
+++ b/Bindings/net/altera_tse.txt
@@ -52,7 +52,7 @@ Optional properties:
Example:
- tse_sub_0_eth_tse_0: ethernet@0x1,00000000 {
+ tse_sub_0_eth_tse_0: ethernet@1,00000000 {
compatible = "altr,tse-msgdma-1.0";
reg = <0x00000001 0x00000000 0x00000400>,
<0x00000001 0x00000460 0x00000020>,
@@ -90,7 +90,7 @@ Example:
};
};
- tse_sub_1_eth_tse_0: ethernet@0x1,00001000 {
+ tse_sub_1_eth_tse_0: ethernet@1,00001000 {
compatible = "altr,tse-msgdma-1.0";
reg = <0x00000001 0x00001000 0x00000400>,
<0x00000001 0x00001460 0x00000020>,
diff --git a/Bindings/net/bluetooth.txt b/Bindings/net/bluetooth.txt
new file mode 100644
index 000000000000..94797df751b8
--- /dev/null
+++ b/Bindings/net/bluetooth.txt
@@ -0,0 +1,5 @@
+The following properties are common to the Bluetooth controllers:
+
+- local-bd-address: array of 6 bytes, specifies the BD address that was
+ uniquely assigned to the Bluetooth device, formatted with least significant
+ byte first (little-endian).
diff --git a/Bindings/net/brcm,bcmgenet.txt b/Bindings/net/brcm,bcmgenet.txt
index 26c77d985faf..3956af1d30f3 100644
--- a/Bindings/net/brcm,bcmgenet.txt
+++ b/Bindings/net/brcm,bcmgenet.txt
@@ -109,7 +109,7 @@ ethernet@f0ba0000 {
reg = <0xf0ba0000 0xfc4c>;
interrupts = <0x0 0x18 0x0>, <0x0 0x19 0x0>;
- mdio@0e14 {
+ mdio@e14 {
compatible = "brcm,genet-mdio-v4";
#address-cells = <0x1>;
#size-cells = <0x0>;
diff --git a/Bindings/net/can/m_can.txt b/Bindings/net/can/m_can.txt
index 78138333ff7a..63e90421d029 100644
--- a/Bindings/net/can/m_can.txt
+++ b/Bindings/net/can/m_can.txt
@@ -45,7 +45,7 @@ Required properties:
Example:
SoC dtsi:
-m_can1: can@020e8000 {
+m_can1: can@20e8000 {
compatible = "bosch,m_can";
reg = <0x020e8000 0x4000>, <0x02298000 0x4000>;
reg-names = "m_can", "message_ram";
diff --git a/Bindings/net/can/sun4i_can.txt b/Bindings/net/can/sun4i_can.txt
index 84ed1909df76..f69845e6feaf 100644
--- a/Bindings/net/can/sun4i_can.txt
+++ b/Bindings/net/can/sun4i_can.txt
@@ -19,7 +19,7 @@ SoC common .dtsi file:
allwinner,pull = <0>;
};
...
- can0: can@01c2bc00 {
+ can0: can@1c2bc00 {
compatible = "allwinner,sun4i-a10-can";
reg = <0x01c2bc00 0x400>;
interrupts = <0 26 4>;
@@ -29,7 +29,7 @@ SoC common .dtsi file:
Board specific .dts file:
- can0: can@01c2bc00 {
+ can0: can@1c2bc00 {
pinctrl-names = "default";
pinctrl-0 = <&can0_pins_a>;
status = "okay";
diff --git a/Bindings/net/dsa/lan9303.txt b/Bindings/net/dsa/lan9303.txt
index 4448d063ddf6..464d6bf87605 100644
--- a/Bindings/net/dsa/lan9303.txt
+++ b/Bindings/net/dsa/lan9303.txt
@@ -52,7 +52,7 @@ I2C managed mode:
port@1 { /* external port 1 */
reg = <1>;
- label = "lan1;
+ label = "lan1";
};
port@2 { /* external port 2 */
@@ -89,7 +89,7 @@ MDIO managed mode:
port@1 { /* external port 1 */
reg = <1>;
- label = "lan1;
+ label = "lan1";
};
port@2 { /* external port 2 */
diff --git a/Bindings/net/dwmac-sun8i.txt b/Bindings/net/dwmac-sun8i.txt
new file mode 100644
index 000000000000..3d6d5fa0c4d5
--- /dev/null
+++ b/Bindings/net/dwmac-sun8i.txt
@@ -0,0 +1,207 @@
+* Allwinner sun8i GMAC ethernet controller
+
+This device is a platform glue layer for stmmac.
+Please see stmmac.txt for the other unchanged properties.
+
+Required properties:
+- compatible: must be one of the following string:
+ "allwinner,sun8i-a83t-emac"
+ "allwinner,sun8i-h3-emac"
+ "allwinner,sun8i-v3s-emac"
+ "allwinner,sun50i-a64-emac"
+- reg: address and length of the register for the device.
+- interrupts: interrupt for the device
+- interrupt-names: must be "macirq"
+- clocks: A phandle to the reference clock for this device
+- clock-names: must be "stmmaceth"
+- resets: A phandle to the reset control for this device
+- reset-names: must be "stmmaceth"
+- phy-mode: See ethernet.txt
+- phy-handle: See ethernet.txt
+- #address-cells: shall be 1
+- #size-cells: shall be 0
+- syscon: A phandle to the syscon of the SoC with one of the following
+ compatible string:
+ - allwinner,sun8i-h3-system-controller
+ - allwinner,sun8i-v3s-system-controller
+ - allwinner,sun50i-a64-system-controller
+ - allwinner,sun8i-a83t-system-controller
+
+Optional properties:
+- allwinner,tx-delay-ps: TX clock delay chain value in ps. Range value is 0-700. Default is 0)
+- allwinner,rx-delay-ps: RX clock delay chain value in ps. Range value is 0-3100. Default is 0)
+Both delay properties need to be a multiple of 100. They control the delay for
+external PHY.
+
+Optional properties for the following compatibles:
+ - "allwinner,sun8i-h3-emac",
+ - "allwinner,sun8i-v3s-emac":
+- allwinner,leds-active-low: EPHY LEDs are active low
+
+Required child node of emac:
+- mdio bus node: should be named mdio with compatible "snps,dwmac-mdio"
+
+Required properties of the mdio node:
+- #address-cells: shall be 1
+- #size-cells: shall be 0
+
+The device node referenced by "phy" or "phy-handle" must be a child node
+of the mdio node. See phy.txt for the generic PHY bindings.
+
+The following compatibles require that the emac node have a mdio-mux child
+node called "mdio-mux":
+ - "allwinner,sun8i-h3-emac"
+ - "allwinner,sun8i-v3s-emac":
+Required properties for the mdio-mux node:
+ - compatible = "allwinner,sun8i-h3-mdio-mux"
+ - mdio-parent-bus: a phandle to EMAC mdio
+ - one child mdio for the integrated mdio with the compatible
+ "allwinner,sun8i-h3-mdio-internal"
+ - one child mdio for the external mdio if present (V3s have none)
+Required properties for the mdio-mux children node:
+ - reg: 1 for internal MDIO bus, 2 for external MDIO bus
+
+The following compatibles require a PHY node representing the integrated
+PHY, under the integrated MDIO bus node if an mdio-mux node is used:
+ - "allwinner,sun8i-h3-emac",
+ - "allwinner,sun8i-v3s-emac":
+
+Additional information regarding generic multiplexer properties can be found
+at Documentation/devicetree/bindings/net/mdio-mux.txt
+
+Required properties of the integrated phy node:
+- clocks: a phandle to the reference clock for the EPHY
+- resets: a phandle to the reset control for the EPHY
+- Must be a child of the integrated mdio
+
+Example with integrated PHY:
+emac: ethernet@1c0b000 {
+ compatible = "allwinner,sun8i-h3-emac";
+ syscon = <&syscon>;
+ reg = <0x01c0b000 0x104>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ resets = <&ccu RST_BUS_EMAC>;
+ reset-names = "stmmaceth";
+ clocks = <&ccu CLK_BUS_EMAC>;
+ clock-names = "stmmaceth";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ };
+
+ mdio-mux {
+ compatible = "mdio-mux", "allwinner,sun8i-h3-mdio-mux";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mdio-parent-bus = <&mdio>;
+
+ int_mdio: mdio@1 {
+ compatible = "allwinner,sun8i-h3-mdio-internal";
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ int_mii_phy: ethernet-phy@1 {
+ reg = <1>;
+ clocks = <&ccu CLK_BUS_EPHY>;
+ resets = <&ccu RST_BUS_EPHY>;
+ phy-is-integrated;
+ };
+ };
+ ext_mdio: mdio@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+Example with external PHY:
+emac: ethernet@1c0b000 {
+ compatible = "allwinner,sun8i-h3-emac";
+ syscon = <&syscon>;
+ reg = <0x01c0b000 0x104>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ resets = <&ccu RST_BUS_EMAC>;
+ reset-names = "stmmaceth";
+ clocks = <&ccu CLK_BUS_EMAC>;
+ clock-names = "stmmaceth";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy-handle = <&ext_rgmii_phy>;
+ phy-mode = "rgmii";
+ allwinner,leds-active-low;
+
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ };
+
+ mdio-mux {
+ compatible = "allwinner,sun8i-h3-mdio-mux";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mdio-parent-bus = <&mdio>;
+
+ int_mdio: mdio@1 {
+ compatible = "allwinner,sun8i-h3-mdio-internal";
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ int_mii_phy: ethernet-phy@1 {
+ reg = <1>;
+ clocks = <&ccu CLK_BUS_EPHY>;
+ resets = <&ccu RST_BUS_EPHY>;
+ };
+ };
+ ext_mdio: mdio@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ext_rgmii_phy: ethernet-phy@1 {
+ reg = <1>;
+ };
+ }:
+ };
+};
+
+Example with SoC without integrated PHY
+
+emac: ethernet@1c0b000 {
+ compatible = "allwinner,sun8i-a83t-emac";
+ syscon = <&syscon>;
+ reg = <0x01c0b000 0x104>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ resets = <&ccu RST_BUS_EMAC>;
+ reset-names = "stmmaceth";
+ clocks = <&ccu CLK_BUS_EMAC>;
+ clock-names = "stmmaceth";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy-handle = <&ext_rgmii_phy>;
+ phy-mode = "rgmii";
+
+ mdio: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ext_rgmii_phy: ethernet-phy@1 {
+ reg = <1>;
+ };
+ };
+};
diff --git a/Bindings/net/fsl-fec.txt b/Bindings/net/fsl-fec.txt
index 6f55bdd52f8a..f0dc94409107 100644
--- a/Bindings/net/fsl-fec.txt
+++ b/Bindings/net/fsl-fec.txt
@@ -34,6 +34,19 @@ Optional properties:
- fsl,err006687-workaround-present: If present indicates that the system has
the hardware workaround for ERR006687 applied and does not need a software
workaround.
+ -interrupt-names: names of the interrupts listed in interrupts property in
+ the same order. The defaults if not specified are
+ __Number of interrupts__ __Default__
+ 1 "int0"
+ 2 "int0", "pps"
+ 3 "int0", "int1", "int2"
+ 4 "int0", "int1", "int2", "pps"
+ The order may be changed as long as they correspond to the interrupts
+ property. Currently, only i.mx7 uses "int1" and "int2". They correspond to
+ tx/rx queues 1 and 2. "int0" will be used for queue 0 and ENET_MII interrupts.
+ For imx6sx, "int0" handles all 3 queues and ENET_MII. "pps" is for the pulse
+ per second interrupt associated with 1588 precision time protocol(PTP).
+
Optional subnodes:
- mdio : specifies the mdio bus in the FEC, used as a container for phy nodes
diff --git a/Bindings/net/mdio.txt b/Bindings/net/mdio.txt
index 96a53f89aa6e..e3e1603f256c 100644
--- a/Bindings/net/mdio.txt
+++ b/Bindings/net/mdio.txt
@@ -18,7 +18,7 @@ Example :
This example shows these optional properties, plus other properties
required for the TI Davinci MDIO driver.
- davinci_mdio: ethernet@0x5c030000 {
+ davinci_mdio: ethernet@5c030000 {
compatible = "ti,davinci_mdio";
reg = <0x5c030000 0x1000>;
#address-cells = <1>;
diff --git a/Bindings/net/renesas,ravb.txt b/Bindings/net/renesas,ravb.txt
index 16723535e1aa..c902261893b9 100644
--- a/Bindings/net/renesas,ravb.txt
+++ b/Bindings/net/renesas,ravb.txt
@@ -17,6 +17,8 @@ Required properties:
- "renesas,etheravb-r8a7795" for the R8A7795 SoC.
- "renesas,etheravb-r8a7796" for the R8A7796 SoC.
+ - "renesas,etheravb-r8a77970" for the R8A77970 SoC.
+ - "renesas,etheravb-r8a77995" for the R8A77995 SoC.
- "renesas,etheravb-rcar-gen3" as a fallback for the above
R-Car Gen3 devices.
@@ -40,7 +42,7 @@ Optional properties:
- interrupt-parent: the phandle for the interrupt controller that services
interrupts for this device.
- interrupt-names: A list of interrupt names.
- For the R8A779[56] SoCs this property is mandatory;
+ For the R-Car Gen 3 SoCs this property is mandatory;
it should include one entry per channel, named "ch%u",
where %u is the channel number ranging from 0 to 24.
For other SoCs this property is optional; if present
diff --git a/Bindings/net/sh_eth.txt b/Bindings/net/sh_eth.txt
index 0115c85a2425..5172799a7f1a 100644
--- a/Bindings/net/sh_eth.txt
+++ b/Bindings/net/sh_eth.txt
@@ -4,7 +4,8 @@ This file provides information on what the device node for the SH EtherMAC
interface contains.
Required properties:
-- compatible: "renesas,gether-r8a7740" if the device is a part of R8A7740 SoC.
+- compatible: Must contain one or more of the following:
+ "renesas,gether-r8a7740" if the device is a part of R8A7740 SoC.
"renesas,ether-r8a7743" if the device is a part of R8A7743 SoC.
"renesas,ether-r8a7745" if the device is a part of R8A7745 SoC.
"renesas,ether-r8a7778" if the device is a part of R8A7778 SoC.
@@ -14,6 +15,14 @@ Required properties:
"renesas,ether-r8a7793" if the device is a part of R8A7793 SoC.
"renesas,ether-r8a7794" if the device is a part of R8A7794 SoC.
"renesas,ether-r7s72100" if the device is a part of R7S72100 SoC.
+ "renesas,rcar-gen1-ether" for a generic R-Car Gen1 device.
+ "renesas,rcar-gen2-ether" for a generic R-Car Gen2 or RZ/G1
+ device.
+
+ When compatible with the generic version, nodes must list
+ the SoC-specific version corresponding to the platform
+ first followed by the generic version.
+
- reg: offset and length of (1) the E-DMAC/feLic register block (required),
(2) the TSU register block (optional).
- interrupts: interrupt specifier for the sole interrupt.
@@ -36,7 +45,8 @@ Optional properties:
Example (Lager board):
ethernet@ee700000 {
- compatible = "renesas,ether-r8a7790";
+ compatible = "renesas,ether-r8a7790",
+ "renesas,rcar-gen2-ether";
reg = <0 0xee700000 0 0x400>;
interrupt-parent = <&gic>;
interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/Bindings/net/socfpga-dwmac.txt b/Bindings/net/socfpga-dwmac.txt
index b30d04b54ee9..17d6819669c8 100644
--- a/Bindings/net/socfpga-dwmac.txt
+++ b/Bindings/net/socfpga-dwmac.txt
@@ -28,7 +28,7 @@ Required properties:
Example:
-gmii_to_sgmii_converter: phy@0x100000240 {
+gmii_to_sgmii_converter: phy@100000240 {
compatible = "altr,gmii-to-sgmii-2.0";
reg = <0x00000001 0x00000240 0x00000008>,
<0x00000001 0x00000200 0x00000040>;
diff --git a/Bindings/net/stmmac.txt b/Bindings/net/stmmac.txt
index c3a7be6615c5..3a28a5d8857d 100644
--- a/Bindings/net/stmmac.txt
+++ b/Bindings/net/stmmac.txt
@@ -12,7 +12,7 @@ Required properties:
Valid interrupt names are:
- "macirq" (combined signal for various interrupt events)
- "eth_wake_irq" (the interrupt to manage the remote wake-up packet detection)
- - "eth_lpi" (the interrupt that occurs when Tx or Rx enters/exits LPI state)
+ - "eth_lpi" (the interrupt that occurs when Rx exits the LPI state)
- phy-mode: See ethernet.txt file in the same directory.
- snps,reset-gpio gpio number for phy reset.
- snps,reset-active-low boolean flag to indicate if phy reset is active low.
diff --git a/Bindings/net/wireless/brcm,bcm43xx-fmac.txt b/Bindings/net/wireless/brcm,bcm43xx-fmac.txt
index b2bd4704f859..86602f264dce 100644
--- a/Bindings/net/wireless/brcm,bcm43xx-fmac.txt
+++ b/Bindings/net/wireless/brcm,bcm43xx-fmac.txt
@@ -20,7 +20,7 @@ Optional properties:
Example:
-mmc3: mmc@01c12000 {
+mmc3: mmc@1c12000 {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/Bindings/nios2/nios2.txt b/Bindings/nios2/nios2.txt
index d6d0a94cb3bb..b95e831bcba3 100644
--- a/Bindings/nios2/nios2.txt
+++ b/Bindings/nios2/nios2.txt
@@ -36,7 +36,7 @@ Optional properties:
Example:
-cpu@0x0 {
+cpu@0 {
device_type = "cpu";
compatible = "altr,nios2-1.0";
reg = <0>;
diff --git a/Bindings/nvmem/allwinner,sunxi-sid.txt b/Bindings/nvmem/allwinner,sunxi-sid.txt
index ef06d061913c..d69543701d5d 100644
--- a/Bindings/nvmem/allwinner,sunxi-sid.txt
+++ b/Bindings/nvmem/allwinner,sunxi-sid.txt
@@ -5,6 +5,7 @@ Required properties:
"allwinner,sun4i-a10-sid"
"allwinner,sun7i-a20-sid"
"allwinner,sun8i-h3-sid"
+ "allwinner,sun50i-a64-sid"
- reg: Should contain registers location and length
@@ -13,13 +14,13 @@ Are child nodes of qfprom, bindings of which as described in
bindings/nvmem/nvmem.txt
Example for sun4i:
- sid@01c23800 {
+ sid@1c23800 {
compatible = "allwinner,sun4i-a10-sid";
reg = <0x01c23800 0x10>
};
Example for sun7i:
- sid@01c23800 {
+ sid@1c23800 {
compatible = "allwinner,sun7i-a20-sid";
reg = <0x01c23800 0x200>
};
diff --git a/Bindings/nvmem/amlogic-efuse.txt b/Bindings/nvmem/amlogic-efuse.txt
index fafd85bd67a6..e3298e18de26 100644
--- a/Bindings/nvmem/amlogic-efuse.txt
+++ b/Bindings/nvmem/amlogic-efuse.txt
@@ -1,4 +1,4 @@
-= Amlogic eFuse device tree bindings =
+= Amlogic Meson GX eFuse device tree bindings =
Required properties:
- compatible: should be "amlogic,meson-gxbb-efuse"
diff --git a/Bindings/nvmem/amlogic-meson-mx-efuse.txt b/Bindings/nvmem/amlogic-meson-mx-efuse.txt
new file mode 100644
index 000000000000..a3c63954a1a4
--- /dev/null
+++ b/Bindings/nvmem/amlogic-meson-mx-efuse.txt
@@ -0,0 +1,22 @@
+Amlogic Meson6/Meson8/Meson8b efuse
+
+Required Properties:
+- compatible: depending on the SoC this should be one of:
+ - "amlogic,meson6-efuse"
+ - "amlogic,meson8-efuse"
+ - "amlogic,meson8b-efuse"
+- reg: base address and size of the efuse registers
+- clocks: a reference to the efuse core gate clock
+- clock-names: must be "core"
+
+All properties and sub-nodes as well as the consumer bindings
+defined in nvmem.txt in this directory are also supported.
+
+
+Example:
+ efuse: nvmem@0 {
+ compatible = "amlogic,meson8-efuse";
+ reg = <0x0 0x2000>;
+ clocks = <&clkc CLKID_EFUSE>;
+ clock-names = "core";
+ };
diff --git a/Bindings/nvmem/brcm,ocotp.txt b/Bindings/nvmem/brcm,ocotp.txt
index 6462e12d8de6..0415265c215a 100644
--- a/Bindings/nvmem/brcm,ocotp.txt
+++ b/Bindings/nvmem/brcm,ocotp.txt
@@ -10,7 +10,7 @@ Required Properties:
Example:
-otp: otp@0301c800 {
+otp: otp@301c800 {
compatible = "brcm,ocotp";
reg = <0x0301c800 0x2c>;
brcm,ocotp-size = <2048>;
diff --git a/Bindings/nvmem/imx-ocotp.txt b/Bindings/nvmem/imx-ocotp.txt
index 70d791b03ea1..f162c72b4e36 100644
--- a/Bindings/nvmem/imx-ocotp.txt
+++ b/Bindings/nvmem/imx-ocotp.txt
@@ -19,7 +19,7 @@ Optional properties:
Example:
- ocotp: ocotp@021bc000 {
+ ocotp: ocotp@21bc000 {
compatible = "fsl,imx6q-ocotp", "syscon";
reg = <0x021bc000 0x4000>;
clocks = <&clks IMX6QDL_CLK_IIM>;
diff --git a/Bindings/nvmem/nvmem.txt b/Bindings/nvmem/nvmem.txt
index b52bc11e9597..fd06c09b822b 100644
--- a/Bindings/nvmem/nvmem.txt
+++ b/Bindings/nvmem/nvmem.txt
@@ -33,7 +33,7 @@ bits: Is pair of bit location and number of bits, which specifies offset
For example:
/* Provider */
- qfprom: qfprom@00700000 {
+ qfprom: qfprom@700000 {
...
/* Data cells */
diff --git a/Bindings/nvmem/qfprom.txt b/Bindings/nvmem/qfprom.txt
index 4ad68b7f5c18..26fe878d5c86 100644
--- a/Bindings/nvmem/qfprom.txt
+++ b/Bindings/nvmem/qfprom.txt
@@ -12,7 +12,7 @@ bindings/nvmem/nvmem.txt
Example:
- qfprom: qfprom@00700000 {
+ qfprom: qfprom@700000 {
compatible = "qcom,qfprom";
reg = <0x00700000 0x8000>;
...
diff --git a/Bindings/nvmem/rockchip-efuse.txt b/Bindings/nvmem/rockchip-efuse.txt
index 1ff02afdc55a..60bec4782806 100644
--- a/Bindings/nvmem/rockchip-efuse.txt
+++ b/Bindings/nvmem/rockchip-efuse.txt
@@ -6,6 +6,7 @@ Required properties:
- "rockchip,rk3188-efuse" - for RK3188 SoCs.
- "rockchip,rk3228-efuse" - for RK3228 SoCs.
- "rockchip,rk3288-efuse" - for RK3288 SoCs.
+ - "rockchip,rk3368-efuse" - for RK3368 SoCs.
- "rockchip,rk3399-efuse" - for RK3399 SoCs.
- reg: Should contain the registers location and exact eFuse size
- clocks: Should be the clock id of eFuse
diff --git a/Bindings/nvmem/snvs-lpgpr.txt b/Bindings/nvmem/snvs-lpgpr.txt
new file mode 100644
index 000000000000..20bc49b49799
--- /dev/null
+++ b/Bindings/nvmem/snvs-lpgpr.txt
@@ -0,0 +1,20 @@
+Device tree bindings for Low Power General Purpose Register found in i.MX6Q/D
+Secure Non-Volatile Storage.
+
+This DT node should be represented as a sub-node of a "syscon",
+"simple-mfd" node.
+
+Required properties:
+- compatible: should be one of the fallowing variants:
+ "fsl,imx6q-snvs-lpgpr" for Freescale i.MX6Q/D/DL/S
+ "fsl,imx6ul-snvs-lpgpr" for Freescale i.MX6UL
+
+Example:
+snvs: snvs@020cc000 {
+ compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
+ reg = <0x020cc000 0x4000>;
+
+ snvs_lpgpr: snvs-lpgpr {
+ compatible = "fsl,imx6q-snvs-lpgpr";
+ };
+};
diff --git a/Bindings/nvmem/uniphier-efuse.txt b/Bindings/nvmem/uniphier-efuse.txt
new file mode 100644
index 000000000000..eccf490d5a6d
--- /dev/null
+++ b/Bindings/nvmem/uniphier-efuse.txt
@@ -0,0 +1,49 @@
+= UniPhier eFuse device tree bindings =
+
+This UniPhier eFuse must be under soc-glue.
+
+Required properties:
+- compatible: should be "socionext,uniphier-efuse"
+- reg: should contain the register location and length
+
+= Data cells =
+Are child nodes of efuse, bindings of which as described in
+bindings/nvmem/nvmem.txt
+
+Example:
+
+ soc-glue@5f900000 {
+ compatible = "socionext,uniphier-ld20-soc-glue-debug",
+ "simple-mfd";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x5f900000 0x2000>;
+
+ efuse@100 {
+ compatible = "socionext,uniphier-efuse";
+ reg = <0x100 0x28>;
+ };
+
+ efuse@200 {
+ compatible = "socionext,uniphier-efuse";
+ reg = <0x200 0x68>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* Data cells */
+ usb_mon: usb-mon@54 {
+ reg = <0x54 0xc>;
+ };
+ };
+ };
+
+= Data consumers =
+Are device nodes which consume nvmem data cells.
+
+Example:
+
+ usb {
+ ...
+ nvmem-cells = <&usb_mon>;
+ nvmem-cell-names = "usb_mon";
+ }
diff --git a/Bindings/openrisc/opencores/or1ksim.txt b/Bindings/openrisc/opencores/or1ksim.txt
new file mode 100644
index 000000000000..4950c794ecbb
--- /dev/null
+++ b/Bindings/openrisc/opencores/or1ksim.txt
@@ -0,0 +1,39 @@
+OpenRISC Generic SoC
+====================
+
+Boards and FPGA SoC's which support the OpenRISC standard platform. The
+platform essentially follows the conventions of the OpenRISC architecture
+specification, however some aspects, such as the boot protocol have been defined
+by the Linux port.
+
+Required properties
+-------------------
+ - compatible: Must include "opencores,or1ksim"
+
+CPU nodes:
+----------
+A "cpus" node is required. Required properties:
+ - #address-cells: Must be 1.
+ - #size-cells: Must be 0.
+A CPU sub-node is also required for at least CPU 0. Since the topology may
+be probed via CPS, it is not necessary to specify secondary CPUs. Required
+properties:
+ - compatible: Must be "opencores,or1200-rtlsvn481".
+ - reg: CPU number.
+ - clock-frequency: The CPU clock frequency in Hz.
+Example:
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu@0 {
+ compatible = "opencores,or1200-rtlsvn481";
+ reg = <0>;
+ clock-frequency = <20000000>;
+ };
+ };
+
+
+Boot protocol
+-------------
+The bootloader may pass the following arguments to the kernel:
+ - r3: address of a flattened device-tree blob or 0x0.
diff --git a/Bindings/pci/altera-pcie.txt b/Bindings/pci/altera-pcie.txt
index 495880193adc..a1dc9366a8fc 100644
--- a/Bindings/pci/altera-pcie.txt
+++ b/Bindings/pci/altera-pcie.txt
@@ -25,7 +25,7 @@ Optional properties:
- bus-range: PCI bus numbers covered
Example
- pcie_0: pcie@0xc00000000 {
+ pcie_0: pcie@c00000000 {
compatible = "altr,pcie-root-port-1.0";
reg = <0xc0000000 0x20000000>,
<0xff220000 0x00004000>;
diff --git a/Bindings/pci/designware-pcie-ecam.txt b/Bindings/pci/designware-pcie-ecam.txt
new file mode 100644
index 000000000000..515b2f9542e5
--- /dev/null
+++ b/Bindings/pci/designware-pcie-ecam.txt
@@ -0,0 +1,42 @@
+* Synopsys DesignWare PCIe root complex in ECAM shift mode
+
+In some cases, firmware may already have configured the Synopsys DesignWare
+PCIe controller in RC mode with static ATU window mappings that cover all
+config, MMIO and I/O spaces in a [mostly] ECAM compatible fashion.
+In this case, there is no need for the OS to perform any low level setup
+of clocks, PHYs or device registers, nor is there any reason for the driver
+to reconfigure ATU windows for config and/or IO space accesses at runtime.
+
+In cases where the IP was synthesized with a minimum ATU window size of
+64 KB, it cannot be supported by the generic ECAM driver, because it
+requires special config space accessors that filter accesses to device #1
+and beyond on the first bus.
+
+Required properties:
+- compatible: "marvell,armada8k-pcie-ecam" or
+ "socionext,synquacer-pcie-ecam" or
+ "snps,dw-pcie-ecam" (must be preceded by a more specific match)
+
+Please refer to the binding document of "pci-host-ecam-generic" in the
+file host-generic-pci.txt for a description of the remaining required
+and optional properties.
+
+Example:
+
+ pcie1: pcie@7f000000 {
+ compatible = "socionext,synquacer-pcie-ecam", "snps,dw-pcie-ecam";
+ device_type = "pci";
+ reg = <0x0 0x7f000000 0x0 0xf00000>;
+ bus-range = <0x0 0xe>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x1000000 0x00 0x00010000 0x00 0x7ff00000 0x0 0x00010000>,
+ <0x2000000 0x00 0x70000000 0x00 0x70000000 0x0 0x0f000000>,
+ <0x3000000 0x3f 0x00000000 0x3f 0x00000000 0x1 0x00000000>;
+
+ #interrupt-cells = <0x1>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x0>;
+ interrupt-map = <0x0 0x0 0x0 0x0 &gic 0x0 0x0 0x0 182 0x4>;
+ msi-map = <0x0 &its 0x0 0x10000>;
+ dma-coherent;
+ };
diff --git a/Bindings/pci/fsl,imx6q-pcie.txt b/Bindings/pci/fsl,imx6q-pcie.txt
index 7b1e48bf172b..149d8f7f86b0 100644
--- a/Bindings/pci/fsl,imx6q-pcie.txt
+++ b/Bindings/pci/fsl,imx6q-pcie.txt
@@ -52,7 +52,7 @@ Additional required properties for imx7d-pcie:
Example:
- pcie@0x01000000 {
+ pcie@01000000 {
compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
reg = <0x01ffc000 0x04000>,
<0x01f00000 0x80000>;
diff --git a/Bindings/pci/hisilicon-histb-pcie.txt b/Bindings/pci/hisilicon-histb-pcie.txt
new file mode 100644
index 000000000000..c84bc027930b
--- /dev/null
+++ b/Bindings/pci/hisilicon-histb-pcie.txt
@@ -0,0 +1,68 @@
+HiSilicon STB PCIe host bridge DT description
+
+The HiSilicon STB PCIe host controller is based on the DesignWare PCIe core.
+It shares common functions with the DesignWare PCIe core driver and inherits
+common properties defined in
+Documentation/devicetree/bindings/pci/designware-pcie.txt.
+
+Additional properties are described here:
+
+Required properties
+- compatible: Should be one of the following strings:
+ "hisilicon,hi3798cv200-pcie"
+- reg: Should contain sysctl, rc_dbi, config registers location and length.
+- reg-names: Must include the following entries:
+ "control": control registers of PCIe controller;
+ "rc-dbi": configuration space of PCIe controller;
+ "config": configuration transaction space of PCIe controller.
+- bus-range: PCI bus numbers covered.
+- interrupts: MSI interrupt.
+- interrupt-names: Must include "msi" entries.
+- clocks: List of phandle and clock specifier pairs as listed in clock-names
+ property.
+- clock-name: Must include the following entries:
+ "aux": auxiliary gate clock;
+ "pipe": pipe gate clock;
+ "sys": sys gate clock;
+ "bus": bus gate clock.
+- resets: List of phandle and reset specifier pairs as listed in reset-names
+ property.
+- reset-names: Must include the following entries:
+ "soft": soft reset;
+ "sys": sys reset;
+ "bus": bus reset.
+
+Optional properties:
+- reset-gpios: The gpio to generate PCIe PERST# assert and deassert signal.
+- phys: List of phandle and phy mode specifier, should be 0.
+- phy-names: Must be "phy".
+
+Example:
+ pcie@f9860000 {
+ compatible = "hisilicon,hi3798cv200-pcie";
+ reg = <0xf9860000 0x1000>,
+ <0xf0000000 0x2000>,
+ <0xf2000000 0x01000000>;
+ reg-names = "control", "rc-dbi", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0 15>;
+ num-lanes = <1>;
+ ranges=<0x81000000 0 0 0xf4000000 0 0x00010000
+ 0x82000000 0 0xf3000000 0xf3000000 0 0x01000000>;
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg PCIE_AUX_CLK>,
+ <&crg PCIE_PIPE_CLK>,
+ <&crg PCIE_SYS_CLK>,
+ <&crg PCIE_BUS_CLK>;
+ clock-names = "aux", "pipe", "sys", "bus";
+ resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>;
+ reset-names = "soft", "sys", "bus";
+ phys = <&combphy1 PHY_TYPE_PCIE>;
+ phy-names = "phy";
+ };
diff --git a/Bindings/pci/hisilicon-pcie.txt b/Bindings/pci/hisilicon-pcie.txt
index bdb7ab39d2d7..7bf9df047a1e 100644
--- a/Bindings/pci/hisilicon-pcie.txt
+++ b/Bindings/pci/hisilicon-pcie.txt
@@ -21,7 +21,7 @@ Optional properties:
- dma-coherent: Present if DMA operations are coherent.
Hip05 Example (note that Hip06 is the same except compatible):
- pcie@0xb0080000 {
+ pcie@b0080000 {
compatible = "hisilicon,hip05-pcie", "snps,dw-pcie";
reg = <0 0xb0080000 0 0x10000>, <0x220 0x00000000 0 0x2000>;
reg-names = "rc_dbi", "config";
diff --git a/Bindings/pci/layerscape-pci.txt b/Bindings/pci/layerscape-pci.txt
index c0484da0f20d..66df1e81e0b8 100644
--- a/Bindings/pci/layerscape-pci.txt
+++ b/Bindings/pci/layerscape-pci.txt
@@ -18,6 +18,7 @@ Required properties:
"fsl,ls2088a-pcie"
"fsl,ls1088a-pcie"
"fsl,ls1046a-pcie"
+ "fsl,ls1012a-pcie"
- reg: base addresses and lengths of the PCIe controller register blocks.
- interrupts: A list of interrupt outputs of the controller. Must contain an
entry for each entry in the interrupt-names property.
diff --git a/Bindings/pci/nvidia,tegra20-pcie.txt b/Bindings/pci/nvidia,tegra20-pcie.txt
index 982a74ea6df9..145a4f04194f 100644
--- a/Bindings/pci/nvidia,tegra20-pcie.txt
+++ b/Bindings/pci/nvidia,tegra20-pcie.txt
@@ -1,10 +1,15 @@
NVIDIA Tegra PCIe controller
Required properties:
-- compatible: For Tegra20, must contain "nvidia,tegra20-pcie". For Tegra30,
- "nvidia,tegra30-pcie". For Tegra124, must contain "nvidia,tegra124-pcie".
- Otherwise, must contain "nvidia,<chip>-pcie", plus one of the above, where
- <chip> is tegra132 or tegra210.
+- compatible: Must be:
+ - "nvidia,tegra20-pcie": for Tegra20
+ - "nvidia,tegra30-pcie": for Tegra30
+ - "nvidia,tegra124-pcie": for Tegra124 and Tegra132
+ - "nvidia,tegra210-pcie": for Tegra210
+ - "nvidia,tegra186-pcie": for Tegra186
+- power-domains: To ungate power partition by BPMP powergate driver. Must
+ contain BPMP phandle and PCIe power partition ID. This is required only
+ for Tegra186.
- device_type: Must be "pci"
- reg: A list of physical base address and length for each set of controller
registers. Must contain an entry for each entry in the reg-names property.
@@ -124,6 +129,16 @@ Power supplies for Tegra210:
- vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must
supply 1.8 V.
+Power supplies for Tegra186:
+- Required:
+ - dvdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
+ - hvdd-pex-pll-supply: High-voltage supply for PLLE (shared with USB3). Must
+ supply 1.8 V.
+ - hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks.
+ Must supply 1.8 V.
+ - vddio-pexctl-aud-supply: Power supply for PCIe side band signals. Must
+ supply 1.8 V.
+
Root ports are defined as subnodes of the PCIe controller node.
Required properties:
@@ -255,7 +270,7 @@ Tegra30:
SoC DTSI:
- pcie-controller@00003000 {
+ pcie-controller@3000 {
compatible = "nvidia,tegra30-pcie";
device_type = "pci";
reg = <0x00003000 0x00000800 /* PADS registers */
@@ -334,7 +349,7 @@ SoC DTSI:
Board DTS:
- pcie-controller@00003000 {
+ pcie-controller@3000 {
status = "okay";
avdd-pexa-supply = <&ldo1_reg>;
@@ -360,7 +375,7 @@ Tegra124:
SoC DTSI:
- pcie-controller@01003000 {
+ pcie-controller@1003000 {
compatible = "nvidia,tegra124-pcie";
device_type = "pci";
reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
@@ -425,7 +440,7 @@ SoC DTSI:
Board DTS:
- pcie-controller@01003000 {
+ pcie-controller@1003000 {
status = "okay";
avddio-pex-supply = <&vdd_1v05_run>;
@@ -456,7 +471,7 @@ Tegra210:
SoC DTSI:
- pcie-controller@01003000 {
+ pcie-controller@1003000 {
compatible = "nvidia,tegra210-pcie";
device_type = "pci";
reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
@@ -521,7 +536,7 @@ SoC DTSI:
Board DTS:
- pcie-controller@01003000 {
+ pcie-controller@1003000 {
status = "okay";
avdd-pll-uerefe-supply = <&avdd_1v05_pll>;
@@ -546,3 +561,114 @@ Board DTS:
status = "okay";
};
};
+
+Tegra186:
+---------
+
+SoC DTSI:
+
+ pcie@10003000 {
+ compatible = "nvidia,tegra186-pcie";
+ power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
+ device_type = "pci";
+ reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */
+ 0x0 0x10003800 0x0 0x00000800 /* AFI registers */
+ 0x0 0x40000000 0x0 0x10000000>; /* configuration space */
+ reg-names = "pads", "afi", "cs";
+
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
+ interrupt-names = "intr", "msi";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+
+ bus-range = <0x00 0xff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */
+ 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */
+ 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */
+ 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */
+ 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */
+ 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */
+
+ clocks = <&bpmp TEGRA186_CLK_AFI>,
+ <&bpmp TEGRA186_CLK_PCIE>,
+ <&bpmp TEGRA186_CLK_PLLE>;
+ clock-names = "afi", "pex", "pll_e";
+
+ resets = <&bpmp TEGRA186_RESET_AFI>,
+ <&bpmp TEGRA186_RESET_PCIE>,
+ <&bpmp TEGRA186_RESET_PCIEXCLK>;
+ reset-names = "afi", "pex", "pcie_x";
+
+ status = "disabled";
+
+ pci@1,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;
+ reg = <0x000800 0 0 0 0>;
+ status = "disabled";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ nvidia,num-lanes = <2>;
+ };
+
+ pci@2,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;
+ reg = <0x001000 0 0 0 0>;
+ status = "disabled";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ nvidia,num-lanes = <1>;
+ };
+
+ pci@3,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;
+ reg = <0x001800 0 0 0 0>;
+ status = "disabled";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ nvidia,num-lanes = <1>;
+ };
+ };
+
+Board DTS:
+
+ pcie@10003000 {
+ status = "okay";
+
+ dvdd-pex-supply = <&vdd_pex>;
+ hvdd-pex-pll-supply = <&vdd_1v8>;
+ hvdd-pex-supply = <&vdd_1v8>;
+ vddio-pexctl-aud-supply = <&vdd_1v8>;
+
+ pci@1,0 {
+ nvidia,num-lanes = <4>;
+ status = "okay";
+ };
+
+ pci@2,0 {
+ nvidia,num-lanes = <0>;
+ status = "disabled";
+ };
+
+ pci@3,0 {
+ nvidia,num-lanes = <1>;
+ status = "disabled";
+ };
+ };
diff --git a/Bindings/pci/pci-rcar-gen2.txt b/Bindings/pci/pci-rcar-gen2.txt
index 3d038638612b..9fe7e12a7bf3 100644
--- a/Bindings/pci/pci-rcar-gen2.txt
+++ b/Bindings/pci/pci-rcar-gen2.txt
@@ -60,17 +60,15 @@ Example SoC configuration:
0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
- pci@0,1 {
+ usb@1,0 {
reg = <0x800 0 0 0 0>;
- device_type = "pci";
- phys = <&usbphy 0 0>;
+ phys = <&usb0 0>;
phy-names = "usb";
};
- pci@0,2 {
+ usb@2,0 {
reg = <0x1000 0 0 0 0>;
- device_type = "pci";
- phys = <&usbphy 0 0>;
+ phys = <&usb0 0>;
phy-names = "usb";
};
};
diff --git a/Bindings/pci/v3-v360epc-pci.txt b/Bindings/pci/v3-v360epc-pci.txt
index 30b364e504ba..11063293f761 100644
--- a/Bindings/pci/v3-v360epc-pci.txt
+++ b/Bindings/pci/v3-v360epc-pci.txt
@@ -2,14 +2,75 @@ V3 Semiconductor V360 EPC PCI bridge
This bridge is found in the ARM Integrator/AP (Application Platform)
-Integrator-specific notes:
+Required properties:
+- compatible: should be one of:
+ "v3,v360epc-pci"
+ "arm,integrator-ap-pci", "v3,v360epc-pci"
+- reg: should contain two register areas:
+ first the base address of the V3 host bridge controller, 64KB
+ second the configuration area register space, 16MB
+- interrupts: should contain a reference to the V3 error interrupt
+ as routed on the system.
+- bus-range: see pci.txt
+- ranges: this follows the standard PCI bindings in the IEEE Std
+ 1275-1994 (see pci.txt) with the following restriction:
+ - The non-prefetchable and prefetchable memory windows must
+ each be exactly 256MB (0x10000000) in size.
+ - The prefetchable memory window must be immediately adjacent
+ to the non-prefetcable memory window
+- dma-ranges: three ranges for the inbound memory region. The ranges must
+ be aligned to a 1MB boundary, and may be 1MB, 2MB, 4MB, 8MB, 16MB, 32MB,
+ 64MB, 128MB, 256MB, 512MB, 1GB or 2GB in size. The memory should be marked
+ as pre-fetchable. Two ranges are supported by the hardware.
-- syscon: should contain a link to the syscon device node (since
+Integrator-specific required properties:
+- syscon: should contain a link to the syscon device node, since
on the Integrator, some registers in the syscon are required to
- operate the V3).
+ operate the V3 host bridge.
-V360 EPC specific notes:
+Example:
-- reg: should contain the base address of the V3 adapter.
-- interrupts: should contain a reference to the V3 error interrupt
- as routed on the system.
+pci: pciv3@62000000 {
+ compatible = "arm,integrator-ap-pci", "v3,v360epc-pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0x62000000 0x10000>, <0x61000000 0x01000000>;
+ interrupt-parent = <&pic>;
+ interrupts = <17>; /* Bus error IRQ */
+ clocks = <&pciclk>;
+ bus-range = <0x00 0xff>;
+ ranges = 0x01000000 0 0x00000000 /* I/O space @00000000 */
+ 0x60000000 0 0x01000000 /* 16 MiB @ LB 60000000 */
+ 0x02000000 0 0x40000000 /* non-prefectable memory @40000000 */
+ 0x40000000 0 0x10000000 /* 256 MiB @ LB 40000000 1:1 */
+ 0x42000000 0 0x50000000 /* prefetchable memory @50000000 */
+ 0x50000000 0 0x10000000>; /* 256 MiB @ LB 50000000 1:1 */
+ dma-ranges = <0x02000000 0 0x20000000 /* EBI memory space */
+ 0x20000000 0 0x20000000 /* 512 MB @ LB 20000000 1:1 */
+ 0x02000000 0 0x80000000 /* Core module alias memory */
+ 0x80000000 0 0x40000000>; /* 1GB @ LB 80000000 */
+ interrupt-map-mask = <0xf800 0 0 0x7>;
+ interrupt-map = <
+ /* IDSEL 9 */
+ 0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */
+ 0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */
+ 0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */
+ 0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */
+ /* IDSEL 10 */
+ 0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */
+ 0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */
+ 0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */
+ 0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */
+ /* IDSEL 11 */
+ 0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */
+ 0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */
+ 0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */
+ 0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */
+ /* IDSEL 12 */
+ 0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */
+ 0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */
+ 0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */
+ 0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */
+ >;
+};
diff --git a/Bindings/phy/brcm,brcmstb-usb-phy.txt b/Bindings/phy/brcm,brcmstb-usb-phy.txt
new file mode 100644
index 000000000000..24a0d06acd1d
--- /dev/null
+++ b/Bindings/phy/brcm,brcmstb-usb-phy.txt
@@ -0,0 +1,43 @@
+Broadcom STB USB PHY
+
+Required properties:
+ - compatible: brcm,brcmstb-usb-phy
+ - reg: two offset and length pairs.
+ The first pair specifies a manditory set of memory mapped
+ registers used for general control of the PHY.
+ The second pair specifies optional registers used by some of
+ the SoCs that support USB 3.x
+ - #phy-cells: Shall be 1 as it expects one argument for setting
+ the type of the PHY. Possible values are:
+ - PHY_TYPE_USB2 for USB1.1/2.0 PHY
+ - PHY_TYPE_USB3 for USB3.x PHY
+
+Optional Properties:
+- clocks : clock phandles.
+- clock-names: String, clock name.
+- brcm,ipp: Boolean, Invert Port Power.
+ Possible values are: 0 (Don't invert), 1 (Invert)
+- brcm,ioc: Boolean, Invert Over Current detection.
+ Possible values are: 0 (Don't invert), 1 (Invert)
+NOTE: one or both of the following two properties must be set
+- brcm,has-xhci: Boolean indicating the phy has an XHCI phy.
+- brcm,has-eohci: Boolean indicating the phy has an EHCI/OHCI phy.
+- dr_mode: String, PHY Device mode.
+ Possible values are: "host", "peripheral ", "drd" or "typec-pd"
+ If this property is not defined, the phy will default to "host" mode.
+
+Example:
+
+usbphy_0: usb-phy@f0470200 {
+ reg = <0xf0470200 0xb8>,
+ <0xf0471940 0x6c0>;
+ compatible = "brcm,brcmstb-usb-phy";
+ #phy-cells = <1>;
+ dr_mode = "host"
+ brcm,ioc = <1>;
+ brcm,ipp = <1>;
+ brcm,has-xhci;
+ brcm,has-eohci;
+ clocks = <&usb20>, <&usb30>;
+ clock-names = "sw_usb", "sw_usb3";
+};
diff --git a/Bindings/phy/brcm,cygnus-pcie-phy.txt b/Bindings/phy/brcm,cygnus-pcie-phy.txt
index 761c4bc24a9b..10efff28b52b 100644
--- a/Bindings/phy/brcm,cygnus-pcie-phy.txt
+++ b/Bindings/phy/brcm,cygnus-pcie-phy.txt
@@ -15,7 +15,7 @@ Required properties For the child node:
- #phy-cells: must be 0
Example:
- pcie_phy: phy@0301d0a0 {
+ pcie_phy: phy@301d0a0 {
compatible = "brcm,cygnus-pcie-phy";
reg = <0x0301d0a0 0x14>;
diff --git a/Bindings/phy/brcm-sata-phy.txt b/Bindings/phy/brcm-sata-phy.txt
index 97977cd29a98..0aced97d8092 100644
--- a/Bindings/phy/brcm-sata-phy.txt
+++ b/Bindings/phy/brcm-sata-phy.txt
@@ -27,7 +27,16 @@ Sub-nodes optional properties:
This property is not applicable for "brcm,iproc-ns2-sata-phy",
"brcm,iproc-nsp-sata-phy" and "brcm,iproc-sr-sata-phy".
-Example:
+- brcm,rxaeq-mode: string that indicates the desired RX equalizer
+ mode, possible values are:
+ "off" (equivalent to not specifying the property)
+ "auto"
+ "manual" (brcm,rxaeq-value is used in that case)
+
+- brcm,rxaeq-value: when 'rxaeq-mode' is set to "manual", provides the RX
+ equalizer value that should be used. Allowed range is 0..63.
+
+Example
sata-phy@f0458100 {
compatible = "brcm,bcm7445-sata-phy", "brcm,phy-sata3";
reg = <0xf0458100 0x1e00>, <0xf045804c 0x10>;
diff --git a/Bindings/phy/mxs-usb-phy.txt b/Bindings/phy/mxs-usb-phy.txt
index 1d25b04cd05e..6ac98b3b5f57 100644
--- a/Bindings/phy/mxs-usb-phy.txt
+++ b/Bindings/phy/mxs-usb-phy.txt
@@ -23,7 +23,7 @@ Optional properties:
the 17.78mA TX reference current. Default: 100
Example:
-usbphy1: usbphy@020c9000 {
+usbphy1: usbphy@20c9000 {
compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
reg = <0x020c9000 0x1000>;
interrupts = <0 44 0x04>;
diff --git a/Bindings/phy/rcar-gen2-phy.txt b/Bindings/phy/rcar-gen2-phy.txt
index 91da947ae9b6..eeb9e1874ea6 100644
--- a/Bindings/phy/rcar-gen2-phy.txt
+++ b/Bindings/phy/rcar-gen2-phy.txt
@@ -4,10 +4,13 @@ This file provides information on what the device node for the R-Car generation
2 USB PHY contains.
Required properties:
-- compatible: "renesas,usb-phy-r8a7790" if the device is a part of R8A7790 SoC.
+- compatible: "renesas,usb-phy-r8a7743" if the device is a part of R8A7743 SoC.
+ "renesas,usb-phy-r8a7745" if the device is a part of R8A7745 SoC.
+ "renesas,usb-phy-r8a7790" if the device is a part of R8A7790 SoC.
"renesas,usb-phy-r8a7791" if the device is a part of R8A7791 SoC.
"renesas,usb-phy-r8a7794" if the device is a part of R8A7794 SoC.
- "renesas,rcar-gen2-usb-phy" for a generic R-Car Gen2 compatible device.
+ "renesas,rcar-gen2-usb-phy" for a generic R-Car Gen2 or
+ RZ/G1 compatible device.
When compatible with the generic version, nodes must list the
SoC-specific version corresponding to the platform first
diff --git a/Bindings/phy/rcar-gen3-phy-usb2.txt b/Bindings/phy/rcar-gen3-phy-usb2.txt
index ace9cce2704a..99b651b33110 100644
--- a/Bindings/phy/rcar-gen3-phy-usb2.txt
+++ b/Bindings/phy/rcar-gen3-phy-usb2.txt
@@ -8,6 +8,8 @@ Required properties:
SoC.
"renesas,usb2-phy-r8a7796" if the device is a part of an R8A7796
SoC.
+ "renesas,usb2-phy-r8a77995" if the device is a part of an
+ R8A77995 SoC.
"renesas,rcar-gen3-usb2-phy" for a generic R-Car Gen3 compatible device.
When compatible with the generic version, nodes must list the
diff --git a/Bindings/phy/sun4i-usb-phy.txt b/Bindings/phy/sun4i-usb-phy.txt
index cbc7847dbf6c..c1ce5a0a652e 100644
--- a/Bindings/phy/sun4i-usb-phy.txt
+++ b/Bindings/phy/sun4i-usb-phy.txt
@@ -45,7 +45,7 @@ Optional properties:
- usb3_vbus-supply : regulator phandle for controller usb3 vbus
Example:
- usbphy: phy@0x01c13400 {
+ usbphy: phy@01c13400 {
#phy-cells = <1>;
compatible = "allwinner,sun4i-a10-usb-phy";
/* phy base regs, phy1 pmu reg, phy2 pmu reg */
diff --git a/Bindings/phy/sun9i-usb-phy.txt b/Bindings/phy/sun9i-usb-phy.txt
index f9853156e311..64f7109aea1f 100644
--- a/Bindings/phy/sun9i-usb-phy.txt
+++ b/Bindings/phy/sun9i-usb-phy.txt
@@ -25,7 +25,7 @@ It is recommended to list all clocks and resets available.
The driver will only use those matching the phy_type.
Example:
- usbphy1: phy@00a01800 {
+ usbphy1: phy@a01800 {
compatible = "allwinner,sun9i-a80-usb-phy";
reg = <0x00a01800 0x4>;
clocks = <&usb_phy_clk 2>, <&usb_phy_clk 10>,
diff --git a/Bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index 6f2ec9af0de2..09789fdfa749 100644
--- a/Bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/Bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -89,7 +89,7 @@ Optional subnode-properties:
Examples:
-pio: pinctrl@01c20800 {
+pio: pinctrl@1c20800 {
compatible = "allwinner,sun5i-a13-pinctrl";
reg = <0x01c20800 0x400>;
#address-cells = <1>;
diff --git a/Bindings/pinctrl/brcm,cygnus-pinmux.txt b/Bindings/pinctrl/brcm,cygnus-pinmux.txt
index 3600d5c6c4d7..3914529a3214 100644
--- a/Bindings/pinctrl/brcm,cygnus-pinmux.txt
+++ b/Bindings/pinctrl/brcm,cygnus-pinmux.txt
@@ -25,7 +25,7 @@ Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
For example:
- pinmux: pinmux@0x0301d0c8 {
+ pinmux: pinmux@0301d0c8 {
compatible = "brcm,cygnus-pinmux";
reg = <0x0301d0c8 0x1b0>;
diff --git a/Bindings/pinctrl/cortina,gemini-pinctrl.txt b/Bindings/pinctrl/cortina,gemini-pinctrl.txt
index 61466c58faae..d857b67fab72 100644
--- a/Bindings/pinctrl/cortina,gemini-pinctrl.txt
+++ b/Bindings/pinctrl/cortina,gemini-pinctrl.txt
@@ -9,8 +9,14 @@ The pin controller node must be a subnode of the system controller node.
Required properties:
- compatible: "cortina,gemini-pinctrl"
-Subnodes of the pin controller contain pin control multiplexing set-up.
-Please refer to pinctrl-bindings.txt for generic pin multiplexing nodes.
+Subnodes of the pin controller contain pin control multiplexing set-up
+and pin configuration of individual pins.
+
+Please refer to pinctrl-bindings.txt for generic pin multiplexing nodes
+and generic pin config nodes.
+
+Supported configurations:
+- skew-delay is supported on the Ethernet pins
Example:
diff --git a/Bindings/pinctrl/fsl,imx-pinctrl.txt b/Bindings/pinctrl/fsl,imx-pinctrl.txt
index 42d74f8a1bcc..a1050b5982ec 100644
--- a/Bindings/pinctrl/fsl,imx-pinctrl.txt
+++ b/Bindings/pinctrl/fsl,imx-pinctrl.txt
@@ -58,14 +58,14 @@ Some requirements for using fsl,imx-pinctrl binding:
configurations by referring to the phandle of that pin configuration node.
Examples:
-usdhc@0219c000 { /* uSDHC4 */
+usdhc@219c000 { /* uSDHC4 */
non-removable;
vmmc-supply = <&reg_3p3v>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc4_1>;
};
-iomuxc@020e0000 {
+iomuxc@20e0000 {
compatible = "fsl,imx6q-iomuxc";
reg = <0x020e0000 0x4000>;
diff --git a/Bindings/pinctrl/img,tz1090-pdc-pinctrl.txt b/Bindings/pinctrl/img,tz1090-pdc-pinctrl.txt
index 51b943cc9770..cf9ccdff4455 100644
--- a/Bindings/pinctrl/img,tz1090-pdc-pinctrl.txt
+++ b/Bindings/pinctrl/img,tz1090-pdc-pinctrl.txt
@@ -89,7 +89,7 @@ Valid values for pin and group names are:
Example:
- pinctrl_pdc: pinctrl@02006500 {
+ pinctrl_pdc: pinctrl@2006500 {
#gpio-range-cells = <3>;
compatible = "img,tz1090-pdc-pinctrl";
reg = <0x02006500 0x100>;
@@ -121,7 +121,7 @@ Example board file extracts:
};
};
- ir: ir@02006200 {
+ ir: ir@2006200 {
pinctrl-names = "default";
pinctrl-0 = <&irmod_default>;
};
diff --git a/Bindings/pinctrl/img,tz1090-pinctrl.txt b/Bindings/pinctrl/img,tz1090-pinctrl.txt
index 509faa87ad0e..2dfd9a3fc1e4 100644
--- a/Bindings/pinctrl/img,tz1090-pinctrl.txt
+++ b/Bindings/pinctrl/img,tz1090-pinctrl.txt
@@ -197,7 +197,7 @@ Valid values for pin and group names are:
Example:
- pinctrl: pinctrl@02005800 {
+ pinctrl: pinctrl@2005800 {
#gpio-range-cells = <3>;
compatible = "img,tz1090-pinctrl";
reg = <0x02005800 0xe4>;
@@ -221,7 +221,7 @@ Example board file extract:
};
};
- uart@02004b00 {
+ uart@2004b00 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_default>;
};
diff --git a/Bindings/pinctrl/marvell,armada-37xx-pinctrl.txt b/Bindings/pinctrl/marvell,armada-37xx-pinctrl.txt
index f64060908d5a..c7c088d2dd50 100644
--- a/Bindings/pinctrl/marvell,armada-37xx-pinctrl.txt
+++ b/Bindings/pinctrl/marvell,armada-37xx-pinctrl.txt
@@ -97,8 +97,8 @@ group spi_quad
- pins 15-16
- functions spi, gpio
-group uart_2
- - pins 9-10
+group uart2
+ - pins 9-10 and 18-19
- functions uart, gpio
Available groups and functions for the South bridge:
diff --git a/Bindings/pinctrl/nvidia,tegra124-xusb-padctl.txt b/Bindings/pinctrl/nvidia,tegra124-xusb-padctl.txt
index 4048f43a9d29..02e971c39d81 100644
--- a/Bindings/pinctrl/nvidia,tegra124-xusb-padctl.txt
+++ b/Bindings/pinctrl/nvidia,tegra124-xusb-padctl.txt
@@ -97,7 +97,7 @@ SoC file extract:
Board file extract:
-------------------
- pcie-controller@01003000 {
+ pcie-controller@1003000 {
...
phys = <&padctl 0>;
diff --git a/Bindings/pinctrl/pinctrl-atlas7.txt b/Bindings/pinctrl/pinctrl-atlas7.txt
index eecf028ff485..bf9b07016c87 100644
--- a/Bindings/pinctrl/pinctrl-atlas7.txt
+++ b/Bindings/pinctrl/pinctrl-atlas7.txt
@@ -96,14 +96,14 @@ For example, pinctrl might have subnodes like the following:
For a specific board, if it wants to use sd1,
it can add the following to its board-specific .dts file.
-sd1: sd@0x12340000 {
+sd1: sd@12340000 {
pinctrl-names = "default";
pinctrl-0 = <&sd1_pmx0>;
}
or
-sd1: sd@0x12340000 {
+sd1: sd@12340000 {
pinctrl-names = "default";
pinctrl-0 = <&sd1_pmx1>;
}
diff --git a/Bindings/pinctrl/pinctrl-bindings.txt b/Bindings/pinctrl/pinctrl-bindings.txt
index 4483cc31e531..ad9bbbba36e9 100644
--- a/Bindings/pinctrl/pinctrl-bindings.txt
+++ b/Bindings/pinctrl/pinctrl-bindings.txt
@@ -271,6 +271,10 @@ output-high - set the pin to output mode with high level
sleep-hardware-state - indicate this is sleep related state which will be programmed
into the registers for the sleep state.
slew-rate - set the slew rate
+skew-delay - this affects the expected clock skew on input pins
+ and the delay before latching a value to an output
+ pin. Typically indicates how many double-inverters are
+ used to delay the signal.
For example:
diff --git a/Bindings/gpio/gpio-mcp23s08.txt b/Bindings/pinctrl/pinctrl-mcp23s08.txt
index c934106b10aa..9c451c20dda4 100644
--- a/Bindings/gpio/gpio-mcp23s08.txt
+++ b/Bindings/pinctrl/pinctrl-mcp23s08.txt
@@ -13,6 +13,7 @@ Required properties:
- "microchip,mcp23s18" for 16 GPIO SPI version
- "microchip,mcp23008" for 8 GPIO I2C version or
- "microchip,mcp23017" for 16 GPIO I2C version of the chip
+ - "microchip,mcp23018" for 16 GPIO I2C version
NOTE: Do not use the old mcp prefix any more. It is deprecated and will be
removed.
- #gpio-cells : Should be two.
@@ -81,3 +82,61 @@ gpiom1: gpio@0 {
reg = <0>;
spi-max-frequency = <1000000>;
};
+
+Pull-up configuration
+=====================
+
+If pins are used as output, they can also be configured with pull-ups. This is
+done with pinctrl.
+
+Please refer file <devicetree/bindings/pinctrl/pinctrl-bindings.txt>
+for details of the common pinctrl bindings used by client devices,
+including the meaning of the phrase "pin configuration node".
+
+Optional Pinmux properties:
+--------------------------
+Following properties are required if default setting of pins are required
+at boot.
+- pinctrl-names: A pinctrl state named per <pinctrl-binding.txt>.
+- pinctrl[0...n]: Properties to contain the phandle for pinctrl states per
+ <pinctrl-binding.txt>.
+
+The pin configurations are defined as child of the pinctrl states node. Each
+sub-node have following properties:
+
+Required properties:
+------------------
+- pins: List of pins. Valid values of pins properties are:
+ gpio0 ... gpio7 for the devices with 8 GPIO pins and
+ gpio0 ... gpio15 for the devices with 16 GPIO pins.
+
+Optional properties:
+-------------------
+The following optional property is defined in the pinmux DT binding document
+<pinctrl-bindings.txt>. Absence of this property will leave the configuration
+in its default state.
+ bias-pull-up
+
+Example with pinctrl to pull-up output pins:
+gpio21: gpio@21 {
+ compatible = "microchip,mcp23017";
+ gpio-controller;
+ #gpio-cells = <0x2>;
+ reg = <0x21>;
+ interrupt-parent = <&socgpio>;
+ interrupts = <0x17 0x8>;
+ interrupt-names = "mcp23017@21 irq";
+ interrupt-controller;
+ #interrupt-cells = <0x2>;
+ microchip,irq-mirror;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2cgpio0irq &gpio21pullups>;
+
+ gpio21pullups: pinmux {
+ pins = "gpio0", "gpio1", "gpio2", "gpio3",
+ "gpio4", "gpio5", "gpio6", "gpio7",
+ "gpio8", "gpio9", "gpio10", "gpio11",
+ "gpio12", "gpio13", "gpio14", "gpio15";
+ bias-pull-up;
+ };
+};
diff --git a/Bindings/pinctrl/pinctrl-mt65xx.txt b/Bindings/pinctrl/pinctrl-mt65xx.txt
index 37d744750579..231fa1db7c5e 100644
--- a/Bindings/pinctrl/pinctrl-mt65xx.txt
+++ b/Bindings/pinctrl/pinctrl-mt65xx.txt
@@ -86,7 +86,7 @@ Examples:
reg = <0 0x1020C020 0 0x1000>;
};
- pinctrl@01c20800 {
+ pinctrl@1c20800 {
compatible = "mediatek,mt8135-pinctrl";
reg = <0 0x1000B000 0 0x1000>;
mediatek,pctl-regmap = <&syscfg_pctl_a &syscfg_pctl_b>;
diff --git a/Bindings/pinctrl/pinctrl-sirf.txt b/Bindings/pinctrl/pinctrl-sirf.txt
index 5f55be59d914..f8420520e14b 100644
--- a/Bindings/pinctrl/pinctrl-sirf.txt
+++ b/Bindings/pinctrl/pinctrl-sirf.txt
@@ -41,7 +41,7 @@ For example, pinctrl might have subnodes like the following:
For a specific board, if it wants to use uart2 without hardware flow control,
it can add the following to its board-specific .dts file.
-uart2: uart@0xb0070000 {
+uart2: uart@b0070000 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_noflow_pins_a>;
}
diff --git a/Bindings/pinctrl/pinctrl-st.txt b/Bindings/pinctrl/pinctrl-st.txt
index 013c675b5b64..48b9be48af18 100644
--- a/Bindings/pinctrl/pinctrl-st.txt
+++ b/Bindings/pinctrl/pinctrl-st.txt
@@ -89,7 +89,7 @@ Example:
interrupt-names = "irqmux";
ranges = <0 0x09610000 0x6000>;
- pio0: gpio@09610000 {
+ pio0: gpio@9610000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
diff --git a/Bindings/pinctrl/qcom,msm8996-pinctrl.txt b/Bindings/pinctrl/qcom,msm8996-pinctrl.txt
index e312a71b2f94..aaf01e929eea 100644
--- a/Bindings/pinctrl/qcom,msm8996-pinctrl.txt
+++ b/Bindings/pinctrl/qcom,msm8996-pinctrl.txt
@@ -175,7 +175,7 @@ to specify in a pin configuration subnode:
Example:
- tlmm: pinctrl@01010000 {
+ tlmm: pinctrl@1010000 {
compatible = "qcom,msm8996-pinctrl";
reg = <0x01010000 0x300000>;
interrupts = <0 208 0>;
diff --git a/Bindings/pinctrl/qcom,pmic-gpio.txt b/Bindings/pinctrl/qcom,pmic-gpio.txt
index 5b12c57e7f02..5c25fcb29fb5 100644
--- a/Bindings/pinctrl/qcom,pmic-gpio.txt
+++ b/Bindings/pinctrl/qcom,pmic-gpio.txt
@@ -15,6 +15,7 @@ PMIC's from Qualcomm.
"qcom,pm8921-gpio"
"qcom,pm8941-gpio"
"qcom,pm8994-gpio"
+ "qcom,pmi8994-gpio"
"qcom,pma8084-gpio"
"qcom,pmi8994-gpio"
@@ -85,6 +86,7 @@ to specify in a pin configuration subnode:
gpio1-gpio44 for pm8921
gpio1-gpio36 for pm8941
gpio1-gpio22 for pm8994
+ gpio1-gpio10 for pmi8994
gpio1-gpio22 for pma8084
gpio1-gpio10 for pmi8994
diff --git a/Bindings/pinctrl/renesas,rza1-pinctrl.txt b/Bindings/pinctrl/renesas,rza1-pinctrl.txt
index 43e21474528a..fd3696eb36bf 100644
--- a/Bindings/pinctrl/renesas,rza1-pinctrl.txt
+++ b/Bindings/pinctrl/renesas,rza1-pinctrl.txt
@@ -12,8 +12,10 @@ Pin controller node
-------------------
Required properties:
- - compatible
- this shall be "renesas,r7s72100-ports".
+ - compatible: should be:
+ - "renesas,r7s72100-ports": for RZ/A1H
+ - "renesas,r7s72101-ports", "renesas,r7s72100-ports": for RZ/A1M
+ - "renesas,r7s72102-ports": for RZ/A1L
- reg
address base and length of the memory area where the pin controller
diff --git a/Bindings/pinctrl/rockchip,pinctrl.txt b/Bindings/pinctrl/rockchip,pinctrl.txt
index 4864e3a74de3..a01a3b8a2363 100644
--- a/Bindings/pinctrl/rockchip,pinctrl.txt
+++ b/Bindings/pinctrl/rockchip,pinctrl.txt
@@ -136,7 +136,7 @@ Example for rk3188:
#size-cells = <1>;
ranges;
- gpio0: gpio0@0x2000a000 {
+ gpio0: gpio0@2000a000 {
compatible = "rockchip,rk3188-gpio-bank0";
reg = <0x2000a000 0x100>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
@@ -149,7 +149,7 @@ Example for rk3188:
#interrupt-cells = <2>;
};
- gpio1: gpio1@0x2003c000 {
+ gpio1: gpio1@2003c000 {
compatible = "rockchip,gpio-bank";
reg = <0x2003c000 0x100>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/Bindings/pinctrl/st,stm32-pinctrl.txt b/Bindings/pinctrl/st,stm32-pinctrl.txt
index 33e3d3c47552..58c2a4c229db 100644
--- a/Bindings/pinctrl/st,stm32-pinctrl.txt
+++ b/Bindings/pinctrl/st,stm32-pinctrl.txt
@@ -143,6 +143,24 @@ Required properties:
* 16 : Alternate Function 15
* 17 : Analog
+ To simplify the usage, macro is available to generate "pinmux" field.
+ This macro is available here:
+ - include/dt-bindings/pinctrl/stm32-pinfunc.h
+
+ Some examples of using macro:
+ /* GPIO A9 set as alernate function 2 */
+ ... {
+ pinmux = <STM32_PINMUX('A', 9, AF2)>;
+ };
+ /* GPIO A9 set as GPIO */
+ ... {
+ pinmux = <STM32_PINMUX('A', 9, GPIO)>;
+ };
+ /* GPIO A9 set as analog */
+ ... {
+ pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+ };
+
Optional properties:
- GENERIC_PINCONFIG: is the generic pinconfig options to use.
Available options are:
@@ -165,13 +183,13 @@ pin-controller {
...
usart1_pins_a: usart1@0 {
pins1 {
- pinmux = <STM32F429_PA9_FUNC_USART1_TX>;
+ pinmux = <STM32_PINMUX('A', 9, AF7)>;
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
- pinmux = <STM32F429_PA10_FUNC_USART1_RX>;
+ pinmux = <STM32_PINMUX('A', 10, AF7)>;
bias-disable;
};
};
diff --git a/Bindings/power/amlogic,meson-gx-pwrc.txt b/Bindings/power/amlogic,meson-gx-pwrc.txt
new file mode 100644
index 000000000000..1cd050b4054c
--- /dev/null
+++ b/Bindings/power/amlogic,meson-gx-pwrc.txt
@@ -0,0 +1,61 @@
+Amlogic Meson Power Controller
+==============================
+
+The Amlogic Meson SoCs embeds an internal Power domain controller.
+
+VPU Power Domain
+----------------
+
+The Video Processing Unit power domain is controlled by this power controller,
+but the domain requires some external resources to meet the correct power
+sequences.
+The bindings must respect the power domain bindings as described in the file
+power_domain.txt
+
+Device Tree Bindings:
+---------------------
+
+Required properties:
+- compatible: should be "amlogic,meson-gx-pwrc-vpu" for the Meson GX SoCs
+- #power-domain-cells: should be 0
+- amlogic,hhi-sysctrl: phandle to the HHI sysctrl node
+- resets: phandles to the reset lines needed for this power demain sequence
+ as described in ../reset/reset.txt
+- clocks: from common clock binding: handle to VPU and VAPB clocks
+- clock-names: from common clock binding: must contain "vpu", "vapb"
+ corresponding to entry in the clocks property.
+
+Parent node should have the following properties :
+- compatible: "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd"
+- reg: base address and size of the AO system control register space.
+
+Example:
+-------
+
+ao_sysctrl: sys-ctrl@0 {
+ compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd";
+ reg = <0x0 0x0 0x0 0x100>;
+
+ pwrc_vpu: power-controller-vpu {
+ compatible = "amlogic,meson-gx-pwrc-vpu";
+ #power-domain-cells = <0>;
+ amlogic,hhi-sysctrl = <&sysctrl>;
+ resets = <&reset RESET_VIU>,
+ <&reset RESET_VENC>,
+ <&reset RESET_VCBUS>,
+ <&reset RESET_BT656>,
+ <&reset RESET_DVIN_RESET>,
+ <&reset RESET_RDMA>,
+ <&reset RESET_VENCI>,
+ <&reset RESET_VENCP>,
+ <&reset RESET_VDAC>,
+ <&reset RESET_VDI6>,
+ <&reset RESET_VENCL>,
+ <&reset RESET_VID_LOCK>;
+ clocks = <&clkc CLKID_VPU>,
+ <&clkc CLKID_VAPB>;
+ clock-names = "vpu", "vapb";
+ };
+};
+
+
diff --git a/Bindings/power/fsl,imx-gpc.txt b/Bindings/power/fsl,imx-gpc.txt
index 6c1498958d48..e371b262d709 100644
--- a/Bindings/power/fsl,imx-gpc.txt
+++ b/Bindings/power/fsl,imx-gpc.txt
@@ -40,7 +40,7 @@ Optional properties:
Example:
- gpc: gpc@020dc000 {
+ gpc: gpc@20dc000 {
compatible = "fsl,imx6q-gpc";
reg = <0x020dc000 0x4000>;
interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
@@ -80,7 +80,7 @@ that is a phandle pointing to the power domain the device belongs to.
Example of a device that is part of the PU power domain:
- vpu: vpu@02040000 {
+ vpu: vpu@2040000 {
reg = <0x02040000 0x3c000>;
/* ... */
power-domains = <&pd_pu>;
diff --git a/Bindings/power/renesas,apmu.txt b/Bindings/power/renesas,apmu.txt
index af21502e939c..f747f95eee58 100644
--- a/Bindings/power/renesas,apmu.txt
+++ b/Bindings/power/renesas,apmu.txt
@@ -8,6 +8,7 @@ Required properties:
- compatible: Should be "renesas,<soctype>-apmu", "renesas,apmu" as fallback.
Examples with soctypes are:
- "renesas,r8a7743-apmu" (RZ/G1M)
+ - "renesas,r8a7745-apmu" (RZ/G1E)
- "renesas,r8a7790-apmu" (R-Car H2)
- "renesas,r8a7791-apmu" (R-Car M2-W)
- "renesas,r8a7792-apmu" (R-Car V2H)
diff --git a/Bindings/power/renesas,rcar-sysc.txt b/Bindings/power/renesas,rcar-sysc.txt
index 98cc8c09d02d..8690f10426a3 100644
--- a/Bindings/power/renesas,rcar-sysc.txt
+++ b/Bindings/power/renesas,rcar-sysc.txt
@@ -17,6 +17,7 @@ Required properties:
- "renesas,r8a7794-sysc" (R-Car E2)
- "renesas,r8a7795-sysc" (R-Car H3)
- "renesas,r8a7796-sysc" (R-Car M3-W)
+ - "renesas,r8a77970-sysc" (R-Car V3M)
- "renesas,r8a77995-sysc" (R-Car D3)
- reg: Address start and address range for the device.
- #power-domain-cells: Must be 1.
diff --git a/Bindings/power/reset/imx-snvs-poweroff.txt b/Bindings/power/reset/imx-snvs-poweroff.txt
index dc7c9bad63ea..1b81fcd9fb72 100644
--- a/Bindings/power/reset/imx-snvs-poweroff.txt
+++ b/Bindings/power/reset/imx-snvs-poweroff.txt
@@ -10,7 +10,7 @@ Required Properties:
-reg: Specifies the physical address of the SNVS_LPCR register
Example:
- snvs@020cc000 {
+ snvs@20cc000 {
compatible = "fsl,sec-v4.0-mon", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
diff --git a/Bindings/power/reset/keystone-reset.txt b/Bindings/power/reset/keystone-reset.txt
index c82f12e2d85c..c5c03789ed1e 100644
--- a/Bindings/power/reset/keystone-reset.txt
+++ b/Bindings/power/reset/keystone-reset.txt
@@ -37,12 +37,12 @@ Example 1:
Setup keystone reset so that in case software reset or
WDT0 is triggered it issues hard reset for SoC.
-pllctrl: pll-controller@02310000 {
+pllctrl: pll-controller@2310000 {
compatible = "ti,keystone-pllctrl", "syscon";
reg = <0x02310000 0x200>;
};
-devctrl: device-state-control@02620000 {
+devctrl: device-state-control@2620000 {
compatible = "ti,keystone-devctrl", "syscon";
reg = <0x02620000 0x1000>;
};
diff --git a/Bindings/power/supply/sbs,sbs-manager.txt b/Bindings/power/supply/sbs,sbs-manager.txt
new file mode 100644
index 000000000000..4b2195571a49
--- /dev/null
+++ b/Bindings/power/supply/sbs,sbs-manager.txt
@@ -0,0 +1,66 @@
+Binding for sbs-manager
+
+Required properties:
+- compatible: "<vendor>,<part-number>", "sbs,sbs-charger" as fallback. The part
+ number compatible string might be used in order to take care of vendor
+ specific registers.
+- reg: integer, i2c address of the device. Should be <0xa>.
+Optional properties:
+- gpio-controller: Marks the port as GPIO controller.
+ See "gpio-specifier" in .../devicetree/bindings/gpio/gpio.txt.
+- #gpio-cells: Should be <2>. The first cell is the pin number, the second cell
+ is used to specify optional parameters:
+ See "gpio-specifier" in .../devicetree/bindings/gpio/gpio.txt.
+
+From OS view the device is basically an i2c-mux used to communicate with up to
+four smart battery devices at address 0xb. The driver actually implements this
+behaviour. So standard i2c-mux nodes can be used to register up to four slave
+batteries. Channels will be numerated starting from 1 to 4.
+
+Example:
+
+batman@a {
+ compatible = "lltc,ltc1760", "sbs,sbs-manager";
+ reg = <0x0a>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ battery@b {
+ compatible = "ti,bq2060", "sbs,sbs-battery";
+ reg = <0x0b>;
+ sbs,battery-detect-gpios = <&batman 1 1>;
+ };
+ };
+
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+
+ battery@b {
+ compatible = "ti,bq2060", "sbs,sbs-battery";
+ reg = <0x0b>;
+ sbs,battery-detect-gpios = <&batman 2 1>;
+ };
+ };
+
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+
+ battery@b {
+ compatible = "ti,bq2060", "sbs,sbs-battery";
+ reg = <0x0b>;
+ sbs,battery-detect-gpios = <&batman 3 1>;
+ };
+ };
+};
diff --git a/Bindings/power/ti-smartreflex.txt b/Bindings/power/ti-smartreflex.txt
new file mode 100644
index 000000000000..9780957c9115
--- /dev/null
+++ b/Bindings/power/ti-smartreflex.txt
@@ -0,0 +1,47 @@
+Texas Instruments SmartReflex binding
+
+SmartReflex is used to set and adjust the SoC operating points.
+
+
+Required properties:
+
+compatible: Shall be one of the following:
+ "ti,omap3-smartreflex-core"
+ "ti,omap3-smartreflex-iva"
+ "ti,omap4-smartreflex-core"
+ "ti,omap4-smartreflex-mpu"
+ "ti,omap4-smartreflex-iva"
+
+reg: Shall contain the device instance IO range
+
+interrupts: Shall contain the device instance interrupt
+
+
+Optional properties:
+
+ti,hwmods: Shall contain the TI interconnect module name if needed
+ by the SoC
+
+
+Example:
+
+ smartreflex_iva: smartreflex@4a0db000 {
+ compatible = "ti,omap4-smartreflex-iva";
+ reg = <0x4a0db000 0x80>;
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "smartreflex_iva";
+ };
+
+ smartreflex_core: smartreflex@4a0dd000 {
+ compatible = "ti,omap4-smartreflex-core";
+ reg = <0x4a0dd000 0x80>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "smartreflex_core";
+ };
+
+ smartreflex_mpu: smartreflex@4a0d9000 {
+ compatible = "ti,omap4-smartreflex-mpu";
+ reg = <0x4a0d9000 0x80>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "smartreflex_mpu";
+ };
diff --git a/Bindings/powerpc/fsl/mcu-mpc8349emitx.txt b/Bindings/powerpc/fsl/mcu-mpc8349emitx.txt
index 0f766333b6eb..37f91fa57654 100644
--- a/Bindings/powerpc/fsl/mcu-mpc8349emitx.txt
+++ b/Bindings/powerpc/fsl/mcu-mpc8349emitx.txt
@@ -8,7 +8,7 @@ Required properties:
Example:
-mcu@0a {
+mcu@a {
#gpio-cells = <2>;
compatible = "fsl,mc9s08qg8-mpc8349emitx",
"fsl,mcu-mpc8349emitx";
diff --git a/Bindings/pwm/pwm-sun4i.txt b/Bindings/pwm/pwm-sun4i.txt
index c5171660eaf9..51ff54c8b8ef 100644
--- a/Bindings/pwm/pwm-sun4i.txt
+++ b/Bindings/pwm/pwm-sun4i.txt
@@ -14,7 +14,7 @@ Required properties:
Example:
- pwm: pwm@01c20e00 {
+ pwm: pwm@1c20e00 {
compatible = "allwinner,sun7i-a20-pwm";
reg = <0x01c20e00 0xc>;
clocks = <&osc24M>;
diff --git a/Bindings/pwm/renesas,pwm-rcar.txt b/Bindings/pwm/renesas,pwm-rcar.txt
index 7e94b802395d..74c118015980 100644
--- a/Bindings/pwm/renesas,pwm-rcar.txt
+++ b/Bindings/pwm/renesas,pwm-rcar.txt
@@ -9,6 +9,7 @@ Required Properties:
- "renesas,pwm-r8a7794": for R-Car E2
- "renesas,pwm-r8a7795": for R-Car H3
- "renesas,pwm-r8a7796": for R-Car M3-W
+ - "renesas,pwm-r8a77995": for R-Car D3
- reg: base address and length of the registers block for the PWM.
- #pwm-cells: should be 2. See pwm.txt in this directory for a description of
the cells format.
diff --git a/Bindings/regulator/da9211.txt b/Bindings/regulator/da9211.txt
index 0f2a6f8fcafd..27717e816e71 100644
--- a/Bindings/regulator/da9211.txt
+++ b/Bindings/regulator/da9211.txt
@@ -1,8 +1,9 @@
-* Dialog Semiconductor DA9211/DA9212/DA9213/DA9214/DA9215 Voltage Regulator
+* Dialog Semiconductor DA9211/DA9212/DA9213/DA9223/DA9214/DA9224/DA9215/DA9225
+ Voltage Regulator
Required properties:
-- compatible: "dlg,da9211" or "dlg,da9212" or "dlg,da9213"
- or "dlg,da9214" or "dlg,da9215"
+- compatible: "dlg,da9211" or "dlg,da9212" or "dlg,da9213" or "dlg,da9223"
+ or "dlg,da9214" or "dlg,da9224" or "dlg,da9215" or "dlg,da9225"
- reg: I2C slave address, usually 0x68.
- interrupts: the interrupt outputs of the controller
- regulators: A node that houses a sub-node for each regulator within the
@@ -16,7 +17,6 @@ Optional properties:
- Any optional property defined in regulator.txt
Example 1) DA9211
-
pmic: da9211@68 {
compatible = "dlg,da9211";
reg = <0x68>;
@@ -35,7 +35,6 @@ Example 1) DA9211
};
Example 2) DA9212
-
pmic: da9212@68 {
compatible = "dlg,da9212";
reg = <0x68>;
@@ -79,7 +78,25 @@ Example 3) DA9213
};
};
-Example 4) DA9214
+Example 4) DA9223
+ pmic: da9223@68 {
+ compatible = "dlg,da9223";
+ reg = <0x68>;
+ interrupts = <3 27>;
+
+ regulators {
+ BUCKA {
+ regulator-name = "VBUCKA";
+ regulator-min-microvolt = < 300000>;
+ regulator-max-microvolt = <1570000>;
+ regulator-min-microamp = <3000000>;
+ regulator-max-microamp = <6000000>;
+ enable-gpios = <&gpio 27 0>;
+ };
+ };
+ };
+
+Example 5) DA9214
pmic: da9214@68 {
compatible = "dlg,da9214";
reg = <0x68>;
@@ -105,7 +122,33 @@ Example 4) DA9214
};
};
-Example 5) DA9215
+Example 6) DA9224
+ pmic: da9224@68 {
+ compatible = "dlg,da9224";
+ reg = <0x68>;
+ interrupts = <3 27>;
+
+ regulators {
+ BUCKA {
+ regulator-name = "VBUCKA";
+ regulator-min-microvolt = < 300000>;
+ regulator-max-microvolt = <1570000>;
+ regulator-min-microamp = <3000000>;
+ regulator-max-microamp = <6000000>;
+ enable-gpios = <&gpio 27 0>;
+ };
+ BUCKB {
+ regulator-name = "VBUCKB";
+ regulator-min-microvolt = < 300000>;
+ regulator-max-microvolt = <1570000>;
+ regulator-min-microamp = <3000000>;
+ regulator-max-microamp = <6000000>;
+ enable-gpios = <&gpio 17 0>;
+ };
+ };
+ };
+
+Example 7) DA9215
pmic: da9215@68 {
compatible = "dlg,da9215";
reg = <0x68>;
@@ -131,3 +174,28 @@ Example 5) DA9215
};
};
+Example 8) DA9225
+ pmic: da9225@68 {
+ compatible = "dlg,da9225";
+ reg = <0x68>;
+ interrupts = <3 27>;
+
+ regulators {
+ BUCKA {
+ regulator-name = "VBUCKA";
+ regulator-min-microvolt = < 300000>;
+ regulator-max-microvolt = <1570000>;
+ regulator-min-microamp = <4000000>;
+ regulator-max-microamp = <7000000>;
+ enable-gpios = <&gpio 27 0>;
+ };
+ BUCKB {
+ regulator-name = "VBUCKB";
+ regulator-min-microvolt = < 300000>;
+ regulator-max-microvolt = <1570000>;
+ regulator-min-microamp = <4000000>;
+ regulator-max-microamp = <7000000>;
+ enable-gpios = <&gpio 17 0>;
+ };
+ };
+ };
diff --git a/Bindings/regulator/max77686.txt b/Bindings/regulator/max77686.txt
index 0dded64d89d3..e9f7578ca09a 100644
--- a/Bindings/regulator/max77686.txt
+++ b/Bindings/regulator/max77686.txt
@@ -40,7 +40,7 @@ to get matched with their hardware counterparts as follow:
Example:
- max77686: pmic@09 {
+ max77686: pmic@9 {
compatible = "maxim,max77686";
interrupt-parent = <&wakeup_eint>;
interrupts = <26 IRQ_TYPE_NONE>;
diff --git a/Bindings/regulator/max77802.txt b/Bindings/regulator/max77802.txt
index 879e98d3b9aa..b82943d83677 100644
--- a/Bindings/regulator/max77802.txt
+++ b/Bindings/regulator/max77802.txt
@@ -71,7 +71,7 @@ has not been disabled for that state using "regulator-off-in-suspend".
Example:
- max77802@09 {
+ max77802@9 {
compatible = "maxim,max77802";
interrupt-parent = <&wakeup_eint>;
interrupts = <26 0>;
diff --git a/Bindings/regulator/pfuze100.txt b/Bindings/regulator/pfuze100.txt
index 444c47831a40..c6dd3f5e485b 100644
--- a/Bindings/regulator/pfuze100.txt
+++ b/Bindings/regulator/pfuze100.txt
@@ -21,7 +21,7 @@ Each regulator is defined using the standard binding for regulators.
Example 1: PFUZE100
- pmic: pfuze100@08 {
+ pmic: pfuze100@8 {
compatible = "fsl,pfuze100";
reg = <0x08>;
@@ -122,7 +122,7 @@ Example 1: PFUZE100
Example 2: PFUZE200
- pmic: pfuze200@08 {
+ pmic: pfuze200@8 {
compatible = "fsl,pfuze200";
reg = <0x08>;
@@ -216,7 +216,7 @@ Example 2: PFUZE200
Example 3: PFUZE3000
- pmic: pfuze3000@08 {
+ pmic: pfuze3000@8 {
compatible = "fsl,pfuze3000";
reg = <0x08>;
diff --git a/Bindings/regulator/qcom,spmi-regulator.txt b/Bindings/regulator/qcom,spmi-regulator.txt
index 0fa3b0fac129..57d2c65899df 100644
--- a/Bindings/regulator/qcom,spmi-regulator.txt
+++ b/Bindings/regulator/qcom,spmi-regulator.txt
@@ -8,6 +8,7 @@ Qualcomm SPMI Regulators
"qcom,pm8916-regulators"
"qcom,pm8941-regulators"
"qcom,pm8994-regulators"
+ "qcom,pmi8994-regulators"
- interrupts:
Usage: optional
@@ -100,6 +101,15 @@ Qualcomm SPMI Regulators
Definition: Reference to regulator supplying the input pin, as
described in the data sheet.
+- vdd_s1-supply:
+- vdd_s2-supply:
+- vdd_s3-supply:
+- vdd_l1-supply:
+ Usage: optional (pmi8994 only)
+ Value type: <phandle>
+ Definition: Reference to regulator supplying the input pin, as
+ described in the data sheet.
+
The regulator node houses sub-nodes for each regulator within the device. Each
sub-node is identified using the node's name, with valid values listed for each
@@ -122,6 +132,9 @@ pm8994:
l6, l7, l8, l9, l10, l11, l12, l13, l14, l15, l16, l17, l18, l19, l20,
l21, l22, l23, l24, l25, l26, l27, l28, l29, l30, l31, l32, lvs1, lvs2
+pmi8994:
+ s1, s2, s3, l1
+
The content of each sub-node is defined by the standard binding for regulators -
see regulator.txt - with additional custom properties described below:
diff --git a/Bindings/regulator/regulator.txt b/Bindings/regulator/regulator.txt
index 378f6dc8b8bd..3cbf56ce66ea 100644
--- a/Bindings/regulator/regulator.txt
+++ b/Bindings/regulator/regulator.txt
@@ -107,7 +107,7 @@ regulators (twl_reg1 and twl_reg2),
...
};
- mmc: mmc@0x0 {
+ mmc: mmc@0 {
...
...
vmmc-supply = <&twl_reg1>;
diff --git a/Bindings/remoteproc/qcom,q6v5.txt b/Bindings/remoteproc/qcom,q6v5.txt
index 7ff3f7903f26..00d3d58a102f 100644
--- a/Bindings/remoteproc/qcom,q6v5.txt
+++ b/Bindings/remoteproc/qcom,q6v5.txt
@@ -10,6 +10,7 @@ on the Qualcomm Hexagon core.
"qcom,q6v5-pil",
"qcom,msm8916-mss-pil",
"qcom,msm8974-mss-pil"
+ "qcom,msm8996-mss-pil"
- reg:
Usage: required
diff --git a/Bindings/reserved-memory/qcom,rmtfs-mem.txt b/Bindings/reserved-memory/qcom,rmtfs-mem.txt
new file mode 100644
index 000000000000..8562ba1dce69
--- /dev/null
+++ b/Bindings/reserved-memory/qcom,rmtfs-mem.txt
@@ -0,0 +1,51 @@
+Qualcomm Remote File System Memory binding
+
+This binding describes the Qualcomm remote filesystem memory, which serves the
+purpose of describing the shared memory region used for remote processors to
+access block device data using the Remote Filesystem protocol.
+
+- compatible:
+ Usage: required
+ Value type: <stringlist>
+ Definition: must be:
+ "qcom,rmtfs-mem"
+
+- reg:
+ Usage: required for static allocation
+ Value type: <prop-encoded-array>
+ Definition: must specify base address and size of the memory region,
+ as described in reserved-memory.txt
+
+- size:
+ Usage: required for dynamic allocation
+ Value type: <prop-encoded-array>
+ Definition: must specify a size of the memory region, as described in
+ reserved-memory.txt
+
+- qcom,client-id:
+ Usage: required
+ Value type: <u32>
+ Definition: identifier of the client to use this region for buffers.
+
+- qcom,vmid:
+ Usage: optional
+ Val