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authorEmmanuel Vadot <manu@FreeBSD.org>2017-06-20 02:28:15 +0000
committerEmmanuel Vadot <manu@FreeBSD.org>2017-06-20 02:28:15 +0000
commit8fdc67f730291b64de002bf95d19ae75e058b8ce (patch)
tree7168a4d1758594b7d9d103004964d3ab4a44d2a3
parentff018dbf5bb142aa83bd955e5b6c55d66e9e9c1e (diff)
downloadsrc-8fdc67f730291b64de002bf95d19ae75e058b8ce.tar.gz
src-8fdc67f730291b64de002bf95d19ae75e058b8ce.zip
Update the DTS file from Linux 4.11vendor/device-tree/4.11
Notes
Notes: svn path=/vendor/device-tree/dist/; revision=320128 svn path=/vendor/device-tree/4.11/; revision=320129; tag=vendor/device-tree/4.11
-rw-r--r--Bindings/arm/amlogic.txt2
-rw-r--r--Bindings/arm/arch_timer.txt6
-rw-r--r--Bindings/arm/axentia.txt19
-rw-r--r--Bindings/arm/bcm/ns2.txt9
-rw-r--r--Bindings/arm/cpus.txt2
-rw-r--r--Bindings/arm/davinci.txt4
-rw-r--r--Bindings/arm/fsl.txt20
-rw-r--r--Bindings/arm/hisilicon/hisilicon.txt4
-rw-r--r--Bindings/arm/marvell/98dx3236-resume-ctrl.txt16
-rw-r--r--Bindings/arm/marvell/98dx3236.txt23
-rw-r--r--Bindings/arm/marvell/cp110-system-controller0.txt6
-rw-r--r--Bindings/arm/omap/omap.txt3
-rw-r--r--Bindings/arm/shmobile.txt2
-rw-r--r--Bindings/arm/sunxi.txt1
-rw-r--r--Bindings/ata/ahci-da850.txt18
-rw-r--r--Bindings/ata/brcm,sata-brcmstb.txt36
-rw-r--r--Bindings/bus/qcom,ebi2.txt6
-rw-r--r--Bindings/clock/brcm,bcm2835-cprman.txt15
-rw-r--r--Bindings/clock/exynos4415-clock.txt38
-rw-r--r--Bindings/clock/hi3519-crg.txt46
-rw-r--r--Bindings/clock/hi3660-clock.txt42
-rw-r--r--Bindings/clock/idt,versaclock5.txt65
-rw-r--r--Bindings/clock/maxim,max77802.txt44
-rw-r--r--Bindings/clock/mvebu-corediv-clock.txt1
-rw-r--r--Bindings/clock/mvebu-cpu-clock.txt1
-rw-r--r--Bindings/clock/mvebu-gated-clock.txt2
-rw-r--r--Bindings/clock/qcom,rpmcc.txt1
-rw-r--r--Bindings/clock/qoriq-clock.txt1
-rw-r--r--Bindings/clock/renesas,cpg-mssr.txt6
-rw-r--r--Bindings/clock/rockchip,rk3328-cru.txt57
-rw-r--r--Bindings/clock/rockchip,rk3399-cru.txt6
-rw-r--r--Bindings/clock/st,stm32-rcc.txt37
-rw-r--r--Bindings/clock/st/st,clkgen-divmux.txt49
-rw-r--r--Bindings/clock/st/st,clkgen-prediv.txt36
-rw-r--r--Bindings/clock/st/st,clkgen-vcc.txt61
-rw-r--r--Bindings/clock/stericsson,abx500.txt20
-rw-r--r--Bindings/clock/sun9i-de.txt28
-rw-r--r--Bindings/clock/sun9i-usb.txt24
-rw-r--r--Bindings/clock/sunxi-ccu.txt2
-rw-r--r--Bindings/clock/ti,cdce925.txt15
-rw-r--r--Bindings/clock/zx296718-clk.txt3
-rw-r--r--Bindings/cpufreq/ti-cpufreq.txt128
-rw-r--r--Bindings/crypto/brcm,spu-crypto.txt22
-rw-r--r--Bindings/crypto/mediatek-crypto.txt27
-rw-r--r--Bindings/devfreq/exynos-bus.txt14
-rw-r--r--Bindings/display/arm,pl11x.txt2
-rw-r--r--Bindings/display/brcm,bcm-vc4.txt35
-rw-r--r--Bindings/display/bridge/adi,adv7511.txt12
-rw-r--r--Bindings/display/bridge/analogix_dp.txt2
-rw-r--r--Bindings/display/bridge/anx7814.txt (renamed from Bindings/video/bridge/anx7814.txt)0
-rw-r--r--Bindings/display/bridge/dw_hdmi.txt85
-rw-r--r--Bindings/display/bridge/sil-sii8620.txt (renamed from Bindings/video/bridge/sil-sii8620.txt)0
-rw-r--r--Bindings/display/bridge/ti,ths8135.txt46
-rw-r--r--Bindings/display/cirrus,clps711x-fb.txt2
-rw-r--r--Bindings/display/exynos/exynos7-decon.txt4
-rw-r--r--Bindings/display/exynos/exynos_dsim.txt1
-rw-r--r--Bindings/display/exynos/samsung-fimd.txt3
-rw-r--r--Bindings/display/hisilicon/hisi-ade.txt2
-rw-r--r--Bindings/display/imx/fsl,imx-fb.txt2
-rw-r--r--Bindings/display/imx/hdmi.txt51
-rw-r--r--Bindings/display/imx/ldb.txt2
-rw-r--r--Bindings/display/mediatek/mediatek,disp.txt2
-rw-r--r--Bindings/display/msm/dsi.txt2
-rw-r--r--Bindings/display/msm/edp.txt2
-rw-r--r--Bindings/display/msm/gpu.txt38
-rw-r--r--Bindings/display/msm/hdmi.txt2
-rw-r--r--Bindings/display/msm/mdp.txt59
-rw-r--r--Bindings/display/multi-inno,mi0283qt.txt27
-rw-r--r--Bindings/display/panel/boe,nv101wxmn51.txt7
-rw-r--r--Bindings/display/panel/netron-dy,e231732.txt7
-rw-r--r--Bindings/display/panel/panel-dpi.txt2
-rw-r--r--Bindings/display/panel/panel.txt4
-rw-r--r--Bindings/display/panel/samsung,ld9040.txt2
-rw-r--r--Bindings/display/panel/samsung,s6e8aa0.txt2
-rw-r--r--Bindings/display/panel/tianma,tm070jdhg30.txt7
-rw-r--r--Bindings/display/rockchip/analogix_dp-rockchip.txt2
-rw-r--r--Bindings/display/rockchip/dw_hdmi-rockchip.txt43
-rw-r--r--Bindings/display/ssd1307fb.txt5
-rw-r--r--Bindings/display/ti/ti,tfp410.txt41
-rw-r--r--Bindings/display/tilcdc/panel.txt2
-rw-r--r--Bindings/display/zte,vou.txt15
-rw-r--r--Bindings/dma/stm32-dma.txt5
-rw-r--r--Bindings/dma/xilinx/xilinx_vdma.txt107
-rw-r--r--Bindings/eeprom/eeprom.txt2
-rw-r--r--Bindings/gpio/cortina,gemini-gpio.txt24
-rw-r--r--Bindings/gpio/gpio-pca953x.txt4
-rw-r--r--Bindings/gpio/gpio-sx150x.txt41
-rw-r--r--Bindings/gpio/gpio-tps65086.txt16
-rw-r--r--Bindings/gpio/gpio.txt8
-rw-r--r--Bindings/gpu/arm,mali-utgard.txt81
-rw-r--r--Bindings/hwmon/adc128d818.txt38
-rw-r--r--Bindings/hwmon/lm70.txt1
-rw-r--r--Bindings/hwmon/lm90.txt6
-rw-r--r--Bindings/hwmon/sht15.txt19
-rw-r--r--Bindings/hwmon/stts751.txt15
-rw-r--r--Bindings/i2c/i2c-mux-pca954x.txt14
-rw-r--r--Bindings/i2c/i2c-sh_mobile.txt1
-rw-r--r--Bindings/i2c/i2c-stm32.txt33
-rw-r--r--Bindings/i2c/nvidia,tegra186-bpmp-i2c.txt42
-rw-r--r--Bindings/i2c/trivial-devices.txt1
-rw-r--r--Bindings/iio/accel/lis302.txt2
-rw-r--r--Bindings/iio/adc/amlogic,meson-saradc.txt32
-rw-r--r--Bindings/iio/adc/avia-hx711.txt18
-rw-r--r--Bindings/iio/adc/max11100.txt18
-rw-r--r--Bindings/iio/adc/qcom,pm8xxx-xoadc.txt149
-rw-r--r--Bindings/iio/adc/renesas,gyroadc.txt99
-rw-r--r--Bindings/iio/adc/st,stm32-adc.txt7
-rw-r--r--Bindings/iio/adc/ti-ads7950.txt23
-rw-r--r--Bindings/iio/imu/bmi160.txt36
-rw-r--r--Bindings/iio/imu/st_lsm6dsx.txt26
-rw-r--r--Bindings/iio/light/cm3605.txt41
-rw-r--r--Bindings/iio/potentiometer/max5481.txt23
-rw-r--r--Bindings/iio/st-sensors.txt2
-rw-r--r--Bindings/iio/temperature/tmp007.txt35
-rw-r--r--Bindings/iio/timer/stm32-timer-trigger.txt23
-rw-r--r--Bindings/input/cypress,tm2-touchkey.txt27
-rw-r--r--Bindings/input/mpr121-touchkey.txt30
-rw-r--r--Bindings/input/pwm-beeper.txt16
-rw-r--r--Bindings/input/touchscreen/focaltech-ft6236.txt35
-rw-r--r--Bindings/input/touchscreen/zet6223.txt32
-rw-r--r--Bindings/interrupt-controller/arm,gic.txt2
-rw-r--r--Bindings/interrupt-controller/cortina,gemini-interrupt-controller.txt22
-rw-r--r--Bindings/interrupt-controller/snps,archs-idu-intc.txt24
-rw-r--r--Bindings/iommu/arm,smmu.txt10
-rw-r--r--Bindings/ipmi.txt25
-rw-r--r--Bindings/leds/common.txt28
-rw-r--r--Bindings/leds/irled/spi-ir-led.txt29
-rw-r--r--Bindings/media/fsl-vdoa.txt21
-rw-r--r--Bindings/media/gpio-ir-receiver.txt3
-rw-r--r--Bindings/media/hix5hd2-ir.txt2
-rw-r--r--Bindings/media/i2c/toshiba,et8ek8.txt48
-rw-r--r--Bindings/media/meson-ir.txt3
-rw-r--r--Bindings/media/mtk-cir.txt24
-rw-r--r--Bindings/media/rc.txt117
-rw-r--r--Bindings/media/st,st-delta.txt17
-rw-r--r--Bindings/media/sunxi-ir.txt2
-rw-r--r--Bindings/media/ti,da850-vpif.txt83
-rw-r--r--Bindings/mfd/as3722.txt3
-rw-r--r--Bindings/mfd/aspeed-gfx.txt17
-rw-r--r--Bindings/mfd/aspeed-lpc.txt137
-rw-r--r--Bindings/mfd/mfd.txt12
-rw-r--r--Bindings/mfd/motorola-cpcap.txt31
-rw-r--r--Bindings/mfd/mt6397.txt4
-rw-r--r--Bindings/mfd/omap-usb-host.txt4
-rw-r--r--Bindings/mfd/qcom-rpm.txt2
-rw-r--r--Bindings/mfd/stm32-timers.txt46
-rw-r--r--Bindings/mips/img/pistachio-marduk.txt10
-rw-r--r--Bindings/misc/atmel-ssc.txt2
-rw-r--r--Bindings/misc/idt_89hpesx.txt44
-rw-r--r--Bindings/mmc/amlogic,meson-gx.txt2
-rw-r--r--Bindings/mmc/brcm,bcm2835-sdhci.txt18
-rw-r--r--Bindings/mmc/mmc-pwrseq-sd8787.txt16
-rw-r--r--Bindings/mmc/mmc.txt1
-rw-r--r--Bindings/mmc/rockchip-dw-mshc.txt2
-rw-r--r--Bindings/mmc/sdhci-st.txt2
-rw-r--r--Bindings/mmc/sdhci.txt2
-rw-r--r--Bindings/mmc/sunxi-mmc.txt1
-rw-r--r--Bindings/mmc/synopsys-dw-mshc.txt15
-rw-r--r--Bindings/mmc/tmio_mmc.txt13
-rw-r--r--Bindings/mmc/zx-dw-mshc.txt33
-rw-r--r--Bindings/mtd/aspeed-smc.txt51
-rw-r--r--Bindings/mtd/common.txt15
-rw-r--r--Bindings/mtd/cortina,gemini-flash.txt24
-rw-r--r--Bindings/mtd/jedec,spi-nor.txt2
-rw-r--r--Bindings/mtd/mtk-quadspi.txt8
-rw-r--r--Bindings/net/brcm,bcm7445-switch-v4.0.txt10
-rw-r--r--Bindings/net/brcm,systemport.txt5
-rw-r--r--Bindings/net/btusb.txt43
-rw-r--r--Bindings/net/cpsw.txt3
-rw-r--r--Bindings/net/dsa/dsa.txt20
-rw-r--r--Bindings/net/dsa/marvell.txt93
-rw-r--r--Bindings/net/ethernet.txt3
-rw-r--r--Bindings/net/marvell,prestera.txt50
-rw-r--r--Bindings/net/marvell-armada-370-neta.txt2
-rw-r--r--Bindings/net/marvell-bt-8xxx.txt (renamed from Bindings/net/marvell-bt-sd8xxx.txt)46
-rw-r--r--Bindings/net/marvell-pp2.txt4
-rw-r--r--Bindings/net/meson-dwmac.txt16
-rw-r--r--Bindings/net/mscc-phy-vsc8531.txt10
-rw-r--r--Bindings/net/phy.txt4
-rw-r--r--Bindings/net/rockchip-dwmac.txt1
-rw-r--r--Bindings/net/snps,dwc-qos-ethernet.txt3
-rw-r--r--Bindings/net/stmmac.txt3
-rw-r--r--Bindings/net/wireless/ieee80211.txt24
-rw-r--r--Bindings/net/wireless/marvell-8xxx.txt7
-rw-r--r--Bindings/net/wireless/marvell-sd8xxx.txt63
-rw-r--r--Bindings/nvmem/imx-ocotp.txt6
-rw-r--r--Bindings/opp/opp.txt46
-rw-r--r--Bindings/pci/hisilicon-pcie.txt43
-rw-r--r--Bindings/pci/mvebu-pci.txt3
-rw-r--r--Bindings/pci/pci-iommu.txt6
-rw-r--r--Bindings/pci/rcar-pci.txt1
-rw-r--r--Bindings/pci/rockchip-pcie.txt2
-rw-r--r--Bindings/pci/samsung,exynos5440-pcie.txt29
-rw-r--r--Bindings/phy/qcom,usb-hs-phy.txt84
-rw-r--r--Bindings/phy/qcom,usb-hsic-phy.txt65
-rw-r--r--Bindings/phy/samsung-phy.txt17
-rw-r--r--Bindings/phy/sun4i-usb-phy.txt1
-rw-r--r--Bindings/pinctrl/allwinner,sunxi-pinctrl.txt3
-rw-r--r--Bindings/pinctrl/fsl,imx7d-pinctrl.txt2
-rw-r--r--Bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt46
-rw-r--r--Bindings/pinctrl/marvell,kirkwood-pinctrl.txt20
-rw-r--r--Bindings/pinctrl/pinctrl-aspeed.txt131
-rw-r--r--Bindings/pinctrl/samsung-pinctrl.txt1
-rw-r--r--Bindings/pinctrl/st,stm32-pinctrl.txt59
-rw-r--r--Bindings/pinctrl/ti,iodelay.txt47
-rw-r--r--Bindings/power/act8945a-charger.txt35
-rw-r--r--Bindings/power/bq2415x.txt47
-rw-r--r--Bindings/power/bq24257.txt64
-rw-r--r--Bindings/power/bq25890.txt46
-rw-r--r--Bindings/power/da9150-charger.txt26
-rw-r--r--Bindings/power/da9150-fg.txt23
-rw-r--r--Bindings/power/isp1704.txt17
-rw-r--r--Bindings/power/ltc2941.txt27
-rw-r--r--Bindings/power/pd-samsung.txt7
-rw-r--r--Bindings/power/qcom,coincell-charger.txt48
-rw-r--r--Bindings/power/reset/gpio-poweroff.txt10
-rw-r--r--Bindings/power/reset/qnap-poweroff.txt3
-rw-r--r--Bindings/power/rt9455_charger.txt48
-rw-r--r--Bindings/power/rx51-battery.txt25
-rw-r--r--Bindings/power/supply/axp20x_ac_power.txt22
-rw-r--r--Bindings/power/supply/axp20x_usb_power.txt5
-rw-r--r--Bindings/power/supply/bq27xxx.txt36
-rw-r--r--Bindings/power/supply/qcom_smbb.txt19
-rw-r--r--Bindings/power/supply/sbs_sbs-charger.txt23
-rw-r--r--Bindings/power/supply/ti,bq24735.txt8
-rw-r--r--Bindings/power/twl-charger.txt30
-rw-r--r--Bindings/power_supply/ab8500/btemp.txt16
-rw-r--r--Bindings/power_supply/ab8500/chargalg.txt16
-rw-r--r--Bindings/power_supply/ab8500/charger.txt25
-rw-r--r--Bindings/power_supply/ab8500/fg.txt58
-rw-r--r--Bindings/power_supply/axp20x_usb_power.txt34
-rw-r--r--Bindings/power_supply/axxia-reset.txt20
-rw-r--r--Bindings/power_supply/charger-manager.txt81
-rw-r--r--Bindings/power_supply/gpio-charger.txt27
-rw-r--r--Bindings/power_supply/imx-snvs-poweroff.txt23
-rw-r--r--Bindings/power_supply/lp8727_charger.txt44
-rw-r--r--Bindings/power_supply/max17042_battery.txt31
-rw-r--r--Bindings/power_supply/max8925_batter.txt18
-rw-r--r--Bindings/power_supply/maxim,max14656.txt25
-rw-r--r--Bindings/power_supply/msm-poweroff.txt17
-rw-r--r--Bindings/power_supply/olpc_battery.txt5
-rw-r--r--Bindings/power_supply/power_supply.txt23
-rw-r--r--Bindings/power_supply/qcom_smbb.txt131
-rw-r--r--Bindings/power_supply/qnap-poweroff.txt16
-rw-r--r--Bindings/power_supply/restart-poweroff.txt8
-rw-r--r--Bindings/power_supply/sbs_sbs-battery.txt23
-rw-r--r--Bindings/power_supply/ti,bq24735.txt35
-rw-r--r--Bindings/power_supply/tps65090.txt17
-rw-r--r--Bindings/power_supply/tps65217_charger.txt12
-rw-r--r--Bindings/powerpc/4xx/emac.txt62
-rw-r--r--Bindings/powerpc/fsl/cpm_qe/cpm.txt67
-rw-r--r--Bindings/powerpc/fsl/cpm_qe/cpm/brg.txt21
-rw-r--r--Bindings/powerpc/fsl/cpm_qe/cpm/i2c.txt41
-rw-r--r--Bindings/powerpc/fsl/cpm_qe/cpm/pic.txt18
-rw-r--r--Bindings/powerpc/fsl/cpm_qe/cpm/usb.txt15
-rw-r--r--Bindings/powerpc/fsl/cpm_qe/gpio.txt38
-rw-r--r--Bindings/powerpc/fsl/cpm_qe/network.txt43
-rw-r--r--Bindings/powerpc/fsl/cpm_qe/qe.txt115
-rw-r--r--Bindings/powerpc/fsl/cpm_qe/qe/firmware.txt24
-rw-r--r--Bindings/powerpc/fsl/cpm_qe/qe/par_io.txt51
-rw-r--r--Bindings/powerpc/fsl/cpm_qe/qe/pincfg.txt57
-rw-r--r--Bindings/powerpc/fsl/cpm_qe/qe/ucc.txt70
-rw-r--r--Bindings/powerpc/fsl/cpm_qe/qe/usb.txt37
-rw-r--r--Bindings/powerpc/fsl/cpm_qe/serial.txt32
-rw-r--r--Bindings/powerpc/fsl/guts.txt41
-rw-r--r--Bindings/powerpc/fsl/l2cache.txt42
-rw-r--r--Bindings/powerpc/fsl/mem-ctrlr.txt27
-rw-r--r--Bindings/powerpc/opal/power-mgt.txt118
-rw-r--r--Bindings/pwm/imx-pwm.txt6
-rw-r--r--Bindings/pwm/pwm-stm32.txt35
-rw-r--r--Bindings/regulator/anatop-regulator.txt1
-rw-r--r--Bindings/regulator/cpcap-regulator.txt34
-rw-r--r--Bindings/regulator/gpio-regulator.txt2
-rw-r--r--Bindings/regulator/qcom,smd-rpm-regulator.txt56
-rw-r--r--Bindings/regulator/ti-abb-regulator.txt2
-rw-r--r--Bindings/remoteproc/qcom,adsp.txt41
-rw-r--r--Bindings/remoteproc/qcom,q6v5.txt4
-rw-r--r--Bindings/reset/brcm,bcm21664-resetmgr.txt14
-rw-r--r--Bindings/reset/hisilicon,hi3660-reset.txt43
-rw-r--r--Bindings/reset/ti-syscon-reset.txt8
-rw-r--r--Bindings/reset/uniphier-reset.txt47
-rw-r--r--Bindings/reset/zte,zx2967-reset.txt20
-rw-r--r--Bindings/rng/omap_rng.txt3
-rw-r--r--Bindings/rtc/armada-380-rtc.txt8
-rw-r--r--Bindings/rtc/cortina,gemini.txt14
-rw-r--r--Bindings/rtc/imxdi-rtc.txt5
-rw-r--r--Bindings/rtc/maxim,ds3231.txt3
-rw-r--r--Bindings/rtc/pcf8563.txt3
-rw-r--r--Bindings/rtc/st,stm32-rtc.txt27
-rw-r--r--Bindings/rtc/sun6i-rtc.txt10
-rw-r--r--Bindings/serial/8250.txt1
-rw-r--r--Bindings/serial/fsl-imx-uart.txt4
-rw-r--r--Bindings/serial/serial.txt3
-rw-r--r--Bindings/serial/slave-device.txt36
-rw-r--r--Bindings/soc/fsl/qman-portals.txt20
-rw-r--r--Bindings/soc/mediatek/auxadc.txt21
-rw-r--r--Bindings/soc/rockchip/grf.txt8
-rw-r--r--Bindings/soc/rockchip/power_domain.txt3
-rw-r--r--Bindings/soc/zte/pd-2967xx.txt19
-rw-r--r--Bindings/sound/axentia,tse850-pcm5142.txt11
-rw-r--r--Bindings/sound/es8328.txt2
-rw-r--r--Bindings/sound/mt2701-afe-pcm.txt2
-rw-r--r--Bindings/sound/nau8540.txt16
-rw-r--r--Bindings/sound/renesas,rsrc-card.txt75
-rw-r--r--Bindings/sound/rockchip,rk3288-hdmi-analog.txt36
-rw-r--r--Bindings/sound/rockchip-i2s.txt4
-rw-r--r--Bindings/sound/samsung,odroidx2-max98090.txt35
-rw-r--r--Bindings/sound/sun4i-codec.txt2
-rw-r--r--Bindings/sound/sun4i-i2s.txt9
-rw-r--r--Bindings/sound/sun8i-a33-codec.txt63
-rw-r--r--Bindings/sound/sunxi,sun4i-spdif.txt1
-rw-r--r--Bindings/sound/zte,zx-i2s.txt14
-rw-r--r--Bindings/spi/spi-lantiq-ssc.txt29
-rw-r--r--Bindings/spi/spi-rockchip.txt7
-rw-r--r--Bindings/sram/sram.txt6
-rw-r--r--Bindings/thermal/qoriq-thermal.txt7
-rw-r--r--Bindings/thermal/rcar-gen3-thermal.txt56
-rw-r--r--Bindings/thermal/zx2967-thermal.txt116
-rw-r--r--Bindings/timer/cortina,gemini-timer.txt22
-rw-r--r--Bindings/timer/ezchip,nps400-timer.txt15
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-rw-r--r--src/arm/sun8i-v3s-licheepi-zero.dts (renamed from src/arm/uniphier-ph1-ld4-ref.dts)70
-rw-r--r--src/arm/sun8i-v3s.dtsi309
-rw-r--r--src/arm/sun9i-a80-cubieboard4.dts23
-rw-r--r--src/arm/sun9i-a80-optimus.dts41
-rw-r--r--src/arm/sun9i-a80.dtsi470
-rw-r--r--src/arm/sunxi-common-regulators.dtsi24
-rw-r--r--src/arm/tango4-common.dtsi46
-rw-r--r--src/arm/tango4-vantage-1172.dts5
-rw-r--r--src/arm/tegra124-apalis-eval.dts10
-rw-r--r--src/arm/tegra124-apalis.dtsi61
-rw-r--r--src/arm/tegra124-nyan-big.dts26
-rw-r--r--src/arm/tegra124-nyan-blaze.dts28
-rw-r--r--src/arm/tegra124-nyan.dtsi5
-rw-r--r--src/arm/tegra20-paz00.dts1
-rw-r--r--src/arm/tegra20-trimslice.dts1
-rw-r--r--src/arm/uniphier-common32.dtsi144
-rw-r--r--src/arm/uniphier-ph1-ld4.dtsi186
-rw-r--r--src/arm/uniphier-ph1-pro4.dtsi204
-rw-r--r--src/arm/uniphier-ph1-pro5.dtsi198
-rw-r--r--src/arm/uniphier-ph1-sld3.dtsi260
-rw-r--r--src/arm/uniphier-ph1-sld8.dtsi185
-rw-r--r--src/arm/uniphier-pinctrl.dtsi18
-rw-r--r--src/arm/uniphier-proxstream2.dtsi209
-rw-r--r--src/arm/vf-colibri-eval-v3.dtsi10
-rw-r--r--src/arm/vf-colibri.dtsi10
-rw-r--r--src/arm/vf500-colibri-eval-v3.dts10
-rw-r--r--src/arm/vf500-colibri.dtsi10
-rw-r--r--src/arm/vf500.dtsi10
-rw-r--r--src/arm/vf610-colibri-eval-v3.dts10
-rw-r--r--src/arm/vf610-colibri.dtsi10
-rw-r--r--src/arm/vf610-twr.dts10
-rw-r--r--src/arm/vf610-zii-dev-rev-b.dts334
-rw-r--r--src/arm/vf610-zii-dev-rev-c.dts416
-rw-r--r--src/arm/vf610-zii-dev.dtsi383
-rw-r--r--src/arm/vf610.dtsi10
-rw-r--r--src/arm/vf610m4-colibri.dts10
-rw-r--r--src/arm/vf610m4-cosmic.dts10
-rw-r--r--src/arm/vf610m4.dtsi10
-rw-r--r--src/arm/vfxxx.dtsi10
-rw-r--r--src/arm64/allwinner/sun50i-a64-bananapi-m64.dts (renamed from src/arm/uniphier-ph1-pro4-ace.dts)91
-rw-r--r--src/arm64/allwinner/sun50i-a64-pine64.dts43
-rw-r--r--src/arm64/allwinner/sun50i-a64.dtsi139
-rw-r--r--src/arm64/amlogic/meson-gx.dtsi68
-rw-r--r--src/arm64/amlogic/meson-gxbb-p200.dts50
-rw-r--r--src/arm64/amlogic/meson-gxbb-vega-s95.dtsi11
-rw-r--r--src/arm64/amlogic/meson-gxbb-wetek-hub.dts66
-rw-r--r--src/arm64/amlogic/meson-gxbb-wetek-play2.dts94
-rw-r--r--src/arm64/amlogic/meson-gxbb.dtsi128
-rw-r--r--src/arm64/amlogic/meson-gxl-s905x-nexbox-a95x.dts (renamed from src/arm64/amlogic/meson-gxl-nexbox-a95x.dts)0
-rw-r--r--src/arm64/amlogic/meson-gxl.dtsi78
-rw-r--r--src/arm64/amlogic/meson-gxm-q200.dts (renamed from src/arm64/amlogic/meson-gxm-s912-q200.dts)0
-rw-r--r--src/arm64/amlogic/meson-gxm-q201.dts (renamed from src/arm64/amlogic/meson-gxm-s912-q201.dts)0
-rw-r--r--src/arm64/amlogic/meson-gxm.dtsi14
-rw-r--r--src/arm64/arm/juno-base.dtsi56
-rw-r--r--src/arm64/arm/juno-clocks.dtsi3
-rw-r--r--src/arm64/arm/juno-cs-r1r2.dtsi100
-rw-r--r--src/arm64/arm/juno-motherboard.dtsi7
-rw-r--r--src/arm64/arm/juno-r1.dts16
-rw-r--r--src/arm64/arm/juno-r2.dts16
-rw-r--r--src/arm64/arm/juno.dts27
-rw-r--r--src/arm64/broadcom/bcm2835-rpi.dtsi5
-rw-r--r--src/arm64/broadcom/bcm283x.dtsi8
-rw-r--r--src/arm64/broadcom/ns2-svk.dts4
-rw-r--r--src/arm64/broadcom/ns2-xmc.dts191
-rw-r--r--src/arm64/broadcom/ns2.dtsi134
-rw-r--r--src/arm64/exynos/exynos5433-bus.dtsi197
-rw-r--r--src/arm64/exynos/exynos5433-pinctrl.dtsi373
-rw-r--r--src/arm64/exynos/exynos5433-tm2-common.dtsi1191
-rw-r--r--src/arm64/exynos/exynos5433-tm2.dts1087
-rw-r--r--src/arm64/exynos/exynos5433-tm2e.dts42
-rw-r--r--src/arm64/exynos/exynos5433.dtsi123
-rw-r--r--src/arm64/exynos/exynos7-espresso.dts49
-rw-r--r--src/arm64/exynos/exynos7-pinctrl.dtsi302
-rw-r--r--src/arm64/exynos/exynos7.dtsi34
-rw-r--r--src/arm64/freescale/fsl-ls1012a-frdm.dts115
-rw-r--r--src/arm64/freescale/fsl-ls1012a-qds.dts128
-rw-r--r--src/arm64/freescale/fsl-ls1012a-rdb.dts59
-rw-r--r--src/arm64/freescale/fsl-ls1012a.dtsi247
-rw-r--r--src/arm64/freescale/fsl-ls1046a.dtsi80
-rw-r--r--src/arm64/freescale/fsl-ls2080a-rdb.dts1
-rw-r--r--src/arm64/hisilicon/hi3660-hikey960.dts33
-rw-r--r--src/arm64/hisilicon/hi3660.dtsi160
-rw-r--r--src/arm64/hisilicon/hip05_hns.dtsi180
-rw-r--r--src/arm64/marvell/armada-371x.dtsi10
-rw-r--r--src/arm64/marvell/armada-3720-db.dts44
-rw-r--r--src/arm64/marvell/armada-3720-espressobin.dts76
-rw-r--r--src/arm64/marvell/armada-372x.dtsi10
-rw-r--r--src/arm64/marvell/armada-37xx.dtsi39
-rw-r--r--src/arm64/marvell/armada-8040-mcbin.dts138
-rw-r--r--src/arm64/marvell/armada-cp110-master.dtsi5
-rw-r--r--src/arm64/marvell/armada-cp110-slave.dtsi5
-rw-r--r--src/arm64/mediatek/mt8173.dtsi19
-rw-r--r--src/arm64/nvidia/tegra186.dtsi86
-rw-r--r--src/arm64/qcom/apq8016-sbc-pmic-pins.dtsi13
-rw-r--r--src/arm64/qcom/apq8016-sbc-soc-pins.dtsi13
-rw-r--r--src/arm64/qcom/apq8016-sbc.dtsi32
-rw-r--r--src/arm64/qcom/apq8096-db820c-pmic-pins.dtsi14
-rw-r--r--src/arm64/qcom/apq8096-db820c.dtsi19
-rw-r--r--src/arm64/qcom/msm8916-pins.dtsi13
-rw-r--r--src/arm64/qcom/msm8916.dtsi315
-rw-r--r--src/arm64/qcom/msm8996.dtsi6
-rw-r--r--src/arm64/renesas/r8a7795-h3ulcb.dts2
-rw-r--r--src/arm64/renesas/r8a7795-salvator-x.dts2
-rw-r--r--src/arm64/renesas/r8a7795.dtsi314
-rw-r--r--src/arm64/renesas/r8a7796-salvator-x.dts37
-rw-r--r--src/arm64/renesas/r8a7796.dtsi245
-rw-r--r--src/arm64/rockchip/rk3368-evb.dtsi10
-rw-r--r--src/arm64/rockchip/rk3368-geekbox.dts10
-rw-r--r--src/arm64/rockchip/rk3368-orion-r68-meta.dts14
-rw-r--r--src/arm64/rockchip/rk3368-px5-evb.dts10
-rw-r--r--src/arm64/rockchip/rk3368-r88.dts16
-rw-r--r--src/arm64/rockchip/rk3399-evb.dts8
-rw-r--r--src/arm64/rockchip/rk3399.dtsi41
-rw-r--r--src/arm64/socionext/uniphier-ld11.dtsi21
-rw-r--r--src/arm64/socionext/uniphier-ld20.dtsi10
-rw-r--r--src/arm64/socionext/uniphier-ph1-ld20-ref.dts87
-rw-r--r--src/arm64/socionext/uniphier-ph1-ld20.dtsi283
-rw-r--r--src/arm64/socionext/uniphier-pinctrl.dtsi18
-rw-r--r--src/arm64/zte/zx296718.dtsi39
-rw-r--r--src/mips/brcm/bcm7125.dtsi49
-rw-r--r--src/mips/brcm/bcm7346.dtsi43
-rw-r--r--src/mips/brcm/bcm7358.dtsi43
-rw-r--r--src/mips/brcm/bcm7360.dtsi43
-rw-r--r--src/mips/brcm/bcm7362.dtsi43
-rw-r--r--src/mips/brcm/bcm7420.dtsi49
-rw-r--r--src/mips/brcm/bcm7425.dtsi43
-rw-r--r--src/mips/brcm/bcm7435.dtsi43
-rw-r--r--src/mips/brcm/bcm96358nb4ser.dts46
-rw-r--r--src/mips/brcm/bcm97125cbmb.dts4
-rw-r--r--src/mips/brcm/bcm97346dbsmb.dts4
-rw-r--r--src/mips/brcm/bcm97358svmb.dts36
-rw-r--r--src/mips/brcm/bcm97360svmb.dts36
-rw-r--r--src/mips/brcm/bcm97362svmb.dts4
-rw-r--r--src/mips/brcm/bcm97420c.dts4
-rw-r--r--src/mips/brcm/bcm97425svmb.dts36
-rw-r--r--src/mips/brcm/bcm97435svmb.dts4
-rw-r--r--src/mips/img/pistachio.dtsi924
-rw-r--r--src/mips/img/pistachio_marduk.dts163
-rw-r--r--src/mips/xilfpga/nexys4ddr.dts63
-rw-r--r--src/powerpc/fsl/kmcent2.dts303
-rw-r--r--src/powerpc/fsl/kmcoge4.dts4
-rw-r--r--src/powerpc/fsl/mpc8569mds.dts2
-rw-r--r--src/powerpc/fsl/t1023si-post.dtsi4
-rw-r--r--src/powerpc/fsl/t1040si-post.dtsi4
-rw-r--r--src/powerpc/fsl/t2081si-post.dtsi1
1082 files changed, 32156 insertions, 20798 deletions
diff --git a/Bindings/arm/amlogic.txt b/Bindings/arm/amlogic.txt
index 9b2b41ab6817..c246cd2730d9 100644
--- a/Bindings/arm/amlogic.txt
+++ b/Bindings/arm/amlogic.txt
@@ -40,6 +40,8 @@ Board compatible values:
- "hardkernel,odroid-c2" (Meson gxbb)
- "amlogic,p200" (Meson gxbb)
- "amlogic,p201" (Meson gxbb)
+ - "wetek,hub" (Meson gxbb)
+ - "wetek,play2" (Meson gxbb)
- "amlogic,p212" (Meson gxl s905x)
- "amlogic,p230" (Meson gxl s905d)
- "amlogic,p231" (Meson gxl s905d)
diff --git a/Bindings/arm/arch_timer.txt b/Bindings/arm/arch_timer.txt
index ad440a2b8051..e926aea1147d 100644
--- a/Bindings/arm/arch_timer.txt
+++ b/Bindings/arm/arch_timer.txt
@@ -31,6 +31,12 @@ to deliver its interrupts via SPIs.
This also affects writes to the tval register, due to the implicit
counter read.
+- hisilicon,erratum-161010101 : A boolean property. Indicates the
+ presence of Hisilicon erratum 161010101, which says that reading the
+ counters is unreliable in some cases, and reads may return a value 32
+ beyond the correct value. This also affects writes to the tval
+ registers, due to the implicit counter read.
+
** Optional properties:
- arm,cpu-registers-not-fw-configured : Firmware does not initialize
diff --git a/Bindings/arm/axentia.txt b/Bindings/arm/axentia.txt
new file mode 100644
index 000000000000..ea3fb96ae465
--- /dev/null
+++ b/Bindings/arm/axentia.txt
@@ -0,0 +1,19 @@
+Device tree bindings for Axentia ARM devices
+============================================
+
+Linea CPU module
+----------------
+
+Required root node properties:
+compatible = "axentia,linea",
+ "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5";
+and following the rules from atmel-at91.txt for a sama5d31 SoC.
+
+
+TSE-850 v3 board
+----------------
+
+Required root node properties:
+compatible = "axentia,tse850v3", "axentia,linea",
+ "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5";
+and following the rules from above for the axentia,linea CPU module.
diff --git a/Bindings/arm/bcm/ns2.txt b/Bindings/arm/bcm/ns2.txt
deleted file mode 100644
index 35f056f4a1c3..000000000000
--- a/Bindings/arm/bcm/ns2.txt
+++ /dev/null
@@ -1,9 +0,0 @@
-Broadcom North Star 2 (NS2) device tree bindings
-------------------------------------------------
-
-Boards with NS2 shall have the following properties:
-
-Required root node property:
-
-NS2 SVK board
-compatible = "brcm,ns2-svk", "brcm,ns2";
diff --git a/Bindings/arm/cpus.txt b/Bindings/arm/cpus.txt
index a1bcfeed5f24..698ad1f097fa 100644
--- a/Bindings/arm/cpus.txt
+++ b/Bindings/arm/cpus.txt
@@ -158,6 +158,7 @@ nodes to be present and contain the properties described below.
"arm,cortex-a53"
"arm,cortex-a57"
"arm,cortex-a72"
+ "arm,cortex-a73"
"arm,cortex-m0"
"arm,cortex-m0+"
"arm,cortex-m1"
@@ -202,6 +203,7 @@ nodes to be present and contain the properties described below.
"marvell,armada-380-smp"
"marvell,armada-390-smp"
"marvell,armada-xp-smp"
+ "marvell,98dx3236-smp"
"mediatek,mt6589-smp"
"mediatek,mt81xx-tz-smp"
"qcom,gcc-msm8660"
diff --git a/Bindings/arm/davinci.txt b/Bindings/arm/davinci.txt
index f0841ce725b5..715622c36260 100644
--- a/Bindings/arm/davinci.txt
+++ b/Bindings/arm/davinci.txt
@@ -13,6 +13,10 @@ EnBW AM1808 based CMC board
Required root node properties:
- compatible = "enbw,cmc", "ti,da850;
+LEGO MINDSTORMS EV3 (AM1808 based)
+Required root node properties:
+ - compatible = "lego,ev3", "ti,da850";
+
Generic DaVinci Boards
----------------------
diff --git a/Bindings/arm/fsl.txt b/Bindings/arm/fsl.txt
index d6ee9c6e1dbb..c9c567ae227f 100644
--- a/Bindings/arm/fsl.txt
+++ b/Bindings/arm/fsl.txt
@@ -108,7 +108,7 @@ status.
- compatible: Should contain a chip-specific compatible string,
Chip-specific strings are of the form "fsl,<chip>-scfg",
The following <chip>s are known to be supported:
- ls1021a, ls1043a, ls1046a, ls2080a.
+ ls1012a, ls1021a, ls1043a, ls1046a, ls2080a.
- reg: should contain base address and length of SCFG memory-mapped registers
@@ -126,7 +126,7 @@ core start address and release the secondary core from holdoff and startup.
- compatible: Should contain a chip-specific compatible string,
Chip-specific strings are of the form "fsl,<chip>-dcfg",
The following <chip>s are known to be supported:
- ls1021a, ls1043a, ls1046a, ls2080a.
+ ls1012a, ls1021a, ls1043a, ls1046a, ls2080a.
- reg : should contain base address and length of DCFG memory-mapped registers
@@ -139,6 +139,22 @@ Example:
Freescale ARMv8 based Layerscape SoC family Device Tree Bindings
----------------------------------------------------------------
+LS1012A SoC
+Required root node properties:
+ - compatible = "fsl,ls1012a";
+
+LS1012A ARMv8 based RDB Board
+Required root node properties:
+ - compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
+
+LS1012A ARMv8 based FRDM Board
+Required root node properties:
+ - compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
+
+LS1012A ARMv8 based QDS Board
+Required root node properties:
+ - compatible = "fsl,ls1012a-qds", "fsl,ls1012a";
+
LS1043A SoC
Required root node properties:
- compatible = "fsl,ls1043a";
diff --git a/Bindings/arm/hisilicon/hisilicon.txt b/Bindings/arm/hisilicon/hisilicon.txt
index 7df79a715611..f1c1e21a8110 100644
--- a/Bindings/arm/hisilicon/hisilicon.txt
+++ b/Bindings/arm/hisilicon/hisilicon.txt
@@ -1,5 +1,9 @@
Hisilicon Platforms Device Tree Bindings
----------------------------------------------------
+Hi3660 SoC
+Required root node properties:
+ - compatible = "hisilicon,hi3660";
+
Hi4511 Board
Required root node properties:
- compatible = "hisilicon,hi3620-hi4511";
diff --git a/Bindings/arm/marvell/98dx3236-resume-ctrl.txt b/Bindings/arm/marvell/98dx3236-resume-ctrl.txt
new file mode 100644
index 000000000000..26eb9d3aa630
--- /dev/null
+++ b/Bindings/arm/marvell/98dx3236-resume-ctrl.txt
@@ -0,0 +1,16 @@
+Resume Control
+--------------
+Available on Marvell SOCs: 98DX3336 and 98DX4251
+
+Required properties:
+
+- compatible: must be "marvell,98dx3336-resume-ctrl"
+
+- reg: Should contain resume control registers location and length
+
+Example:
+
+resume@20980 {
+ compatible = "marvell,98dx3336-resume-ctrl";
+ reg = <0x20980 0x10>;
+};
diff --git a/Bindings/arm/marvell/98dx3236.txt b/Bindings/arm/marvell/98dx3236.txt
new file mode 100644
index 000000000000..64e8c73fc5ab
--- /dev/null
+++ b/Bindings/arm/marvell/98dx3236.txt
@@ -0,0 +1,23 @@
+Marvell 98DX3236, 98DX3336 and 98DX4251 Platforms Device Tree Bindings
+----------------------------------------------------------------------
+
+Boards with a SoC of the Marvell 98DX3236, 98DX3336 and 98DX4251 families
+shall have the following property:
+
+Required root node property:
+
+compatible: must contain "marvell,armadaxp-98dx3236"
+
+In addition, boards using the Marvell 98DX3336 SoC shall have the
+following property:
+
+Required root node property:
+
+compatible: must contain "marvell,armadaxp-98dx3336"
+
+In addition, boards using the Marvell 98DX4251 SoC shall have the
+following property:
+
+Required root node property:
+
+compatible: must contain "marvell,armadaxp-98dx4251"
diff --git a/Bindings/arm/marvell/cp110-system-controller0.txt b/Bindings/arm/marvell/cp110-system-controller0.txt
index 30c546900b60..07dbb358182c 100644
--- a/Bindings/arm/marvell/cp110-system-controller0.txt
+++ b/Bindings/arm/marvell/cp110-system-controller0.txt
@@ -45,7 +45,7 @@ The following clocks are available:
- 1 15 SATA
- 1 16 SATA USB
- 1 17 Main
- - 1 18 SD/MMC
+ - 1 18 SD/MMC/GOP
- 1 21 Slow IO (SPI, NOR, BootROM, I2C, UART)
- 1 22 USB3H0
- 1 23 USB3H1
@@ -65,7 +65,7 @@ Required properties:
"cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio",
"cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "none",
"cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata",
- "cpm-sata-usb", "cpm-main", "cpm-sd-mmc", "none", "none", "cpm-slow-io",
+ "cpm-sata-usb", "cpm-main", "cpm-sd-mmc-gop", "none", "none", "cpm-slow-io",
"cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", "cpm-eip197";
Example:
@@ -78,6 +78,6 @@ Example:
gate-clock-output-names = "cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio",
"cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "none",
"cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata",
- "cpm-sata-usb", "cpm-main", "cpm-sd-mmc", "none", "none", "cpm-slow-io",
+ "cpm-sata-usb", "cpm-main", "cpm-sd-mmc-gop", "none", "none", "cpm-slow-io",
"cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", "cpm-eip197";
};
diff --git a/Bindings/arm/omap/omap.txt b/Bindings/arm/omap/omap.txt
index 05f95c3ed7d4..8219b2c6bb29 100644
--- a/Bindings/arm/omap/omap.txt
+++ b/Bindings/arm/omap/omap.txt
@@ -151,6 +151,9 @@ Boards:
- AM335X SBC-T335 : single board computer, built around the Sitara AM3352/4
compatible = "compulab,sbc-t335", "compulab,cm-t335", "ti,am33xx"
+- AM335X phyCORE-AM335x: Development kit
+ compatible = "phytec,am335x-pcm-953", "phytec,am335x-phycore-som", "ti,am33xx"
+
- OMAP5 EVM : Evaluation Module
compatible = "ti,omap5-evm", "ti,omap5"
diff --git a/Bindings/arm/shmobile.txt b/Bindings/arm/shmobile.txt
index 253bf9b86690..c9502634316d 100644
--- a/Bindings/arm/shmobile.txt
+++ b/Bindings/arm/shmobile.txt
@@ -75,7 +75,7 @@ Boards:
compatible = "renesas,rskrza1", "renesas,r7s72100"
- Salvator-X (RTP0RC7795SIPB0010S)
compatible = "renesas,salvator-x", "renesas,r8a7795";
- - Salvator-X
+ - Salvator-X (RTP0RC7796SIPB0011S)
compatible = "renesas,salvator-x", "renesas,r8a7796";
- SILK (RTP0RC7794LCB00011S)
compatible = "renesas,silk", "renesas,r8a7794"
diff --git a/Bindings/arm/sunxi.txt b/Bindings/arm/sunxi.txt
index 4d6467cc2aa2..d2c46449b4eb 100644
--- a/Bindings/arm/sunxi.txt
+++ b/Bindings/arm/sunxi.txt
@@ -12,6 +12,7 @@ using one of the following compatible strings:
allwinner,sun8i-a23
allwinner,sun8i-a33
allwinner,sun8i-a83t
+ allwinner,sun8i-h2-plus
allwinner,sun8i-h3
allwinner,sun9i-a80
allwinner,sun50i-a64
diff --git a/Bindings/ata/ahci-da850.txt b/Bindings/ata/ahci-da850.txt
new file mode 100644
index 000000000000..5f8193417725
--- /dev/null
+++ b/Bindings/ata/ahci-da850.txt
@@ -0,0 +1,18 @@
+Device tree binding for the TI DA850 AHCI SATA Controller
+---------------------------------------------------------
+
+Required properties:
+ - compatible: must be "ti,da850-ahci"
+ - reg: physical base addresses and sizes of the two register regions
+ used by the controller: the register map as defined by the
+ AHCI 1.1 standard and the Power Down Control Register (PWRDN)
+ for enabling/disabling the SATA clock receiver
+ - interrupts: interrupt specifier (refer to the interrupt binding)
+
+Example:
+
+ sata: sata@218000 {
+ compatible = "ti,da850-ahci";
+ reg = <0x218000 0x2000>, <0x22c018 0x4>;
+ interrupts = <67>;
+ };
diff --git a/Bindings/ata/brcm,sata-brcmstb.txt b/Bindings/ata/brcm,sata-brcmstb.txt
deleted file mode 100644
index 60872838f1ad..000000000000
--- a/Bindings/ata/brcm,sata-brcmstb.txt
+++ /dev/null
@@ -1,36 +0,0 @@
-* Broadcom SATA3 AHCI Controller for STB
-
-SATA nodes are defined to describe on-chip Serial ATA controllers.
-Each SATA controller should have its own node.
-
-Required properties:
-- compatible : should be one or more of
- "brcm,bcm7425-ahci"
- "brcm,bcm7445-ahci"
- "brcm,sata3-ahci"
-- reg : register mappings for AHCI and SATA_TOP_CTRL
-- reg-names : "ahci" and "top-ctrl"
-- interrupts : interrupt mapping for SATA IRQ
-
-Also see ahci-platform.txt.
-
-Example:
-
- sata@f045a000 {
- compatible = "brcm,bcm7445-ahci", "brcm,sata3-ahci";
- reg = <0xf045a000 0xa9c>, <0xf0458040 0x24>;
- reg-names = "ahci", "top-ctrl";
- interrupts = <0 30 0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- sata0: sata-port@0 {
- reg = <0>;
- phys = <&sata_phy 0>;
- };
-
- sata1: sata-port@1 {
- reg = <1>;
- phys = <&sata_phy 1>;
- };
- };
diff --git a/Bindings/bus/qcom,ebi2.txt b/Bindings/bus/qcom,ebi2.txt
index 920681f552db..5a7d567f6833 100644
--- a/Bindings/bus/qcom,ebi2.txt
+++ b/Bindings/bus/qcom,ebi2.txt
@@ -51,7 +51,7 @@ Required properties:
- compatible: should be one of:
"qcom,msm8660-ebi2"
"qcom,apq8060-ebi2"
-- #address-cells: shoule be <2>: the first cell is the chipselect,
+- #address-cells: should be <2>: the first cell is the chipselect,
the second cell is the offset inside the memory range
- #size-cells: should be <1>
- ranges: should be set to:
@@ -64,7 +64,7 @@ Required properties:
- reg: two ranges of registers: EBI2 config and XMEM config areas
- reg-names: should be "ebi2", "xmem"
- clocks: two clocks, EBI_2X and EBI
-- clock-names: shoule be "ebi2x", "ebi2"
+- clock-names: should be "ebi2x", "ebi2"
Optional subnodes:
- Nodes inside the EBI2 will be considered device nodes.
@@ -100,7 +100,7 @@ Optional properties arrays for FAST chip selects:
assertion, with respect to the cycle where ADV (address valid) is asserted.
2 means 2 cycles between ADV and OE. Valid values 0, 1, 2 or 3.
- qcom,xmem-read-hold-cycles: the length in cycles of the first segment of a
- read transfer. For a single read trandfer this will be the time from CS
+ read transfer. For a single read transfer this will be the time from CS
assertion to OE assertion. Valid values 0 thru 15.
diff --git a/Bindings/clock/brcm,bcm2835-cprman.txt b/Bindings/clock/brcm,bcm2835-cprman.txt
index e56a1df3a9d3..dd906db34b32 100644
--- a/Bindings/clock/brcm,bcm2835-cprman.txt
+++ b/Bindings/clock/brcm,bcm2835-cprman.txt
@@ -16,7 +16,20 @@ Required properties:
- #clock-cells: Should be <1>. The permitted clock-specifier values can be
found in include/dt-bindings/clock/bcm2835.h
- reg: Specifies base physical address and size of the registers
-- clocks: The external oscillator clock phandle
+- clocks: phandles to the parent clocks used as input to the module, in
+ the following order:
+
+ - External oscillator
+ - DSI0 byte clock
+ - DSI0 DDR2 clock
+ - DSI0 DDR clock
+ - DSI1 byte clock
+ - DSI1 DDR2 clock
+ - DSI1 DDR clock
+
+ Only external oscillator is required. The DSI clocks may
+ not be present, in which case their children will be
+ unusable.
Example:
diff --git a/Bindings/clock/exynos4415-clock.txt b/Bindings/clock/exynos4415-clock.txt
deleted file mode 100644
index 847d98bae8cf..000000000000
--- a/Bindings/clock/exynos4415-clock.txt
+++ /dev/null
@@ -1,38 +0,0 @@
-* Samsung Exynos4415 Clock Controller
-
-The Exynos4415 clock controller generates and supplies clock to various
-consumer devices within the Exynos4415 SoC.
-
-Required properties:
-
-- compatible: should be one of the following:
- - "samsung,exynos4415-cmu" - for the main system clocks controller
- (CMU_LEFTBUS, CMU_RIGHTBUS, CMU_TOP, CMU_CPU clock domains).
- - "samsung,exynos4415-cmu-dmc" - for the Exynos4415 SoC DRAM Memory
- Controller (DMC) domain clock controller.
-
-- reg: physical base address of the controller and length of memory mapped
- region.
-
-- #clock-cells: should be 1.
-
-Each clock is assigned an identifier and client nodes can use this identifier
-to specify the clock which they consume.
-
-All available clocks are defined as preprocessor macros in
-dt-bindings/clock/exynos4415.h header and can be used in device
-tree sources.
-
-Example 1: An example of a clock controller node is listed below.
-
- cmu: clock-controller@10030000 {
- compatible = "samsung,exynos4415-cmu";
- reg = <0x10030000 0x18000>;
- #clock-cells = <1>;
- };
-
- cmu-dmc: clock-controller@105C0000 {
- compatible = "samsung,exynos4415-cmu-dmc";
- reg = <0x105C0000 0x3000>;
- #clock-cells = <1>;
- };
diff --git a/Bindings/clock/hi3519-crg.txt b/Bindings/clock/hi3519-crg.txt
deleted file mode 100644
index acd1f235d548..000000000000
--- a/Bindings/clock/hi3519-crg.txt
+++ /dev/null
@@ -1,46 +0,0 @@
-* Hisilicon Hi3519 Clock and Reset Generator(CRG)
-
-The Hi3519 CRG module provides clock and reset signals to various
-controllers within the SoC.
-
-This binding uses the following bindings:
- Documentation/devicetree/bindings/clock/clock-bindings.txt
- Documentation/devicetree/bindings/reset/reset.txt
-
-Required Properties:
-
-- compatible: should be one of the following.
- - "hisilicon,hi3519-crg" - controller compatible with Hi3519 SoC.
-
-- reg: physical base address of the controller and length of memory mapped
- region.
-
-- #clock-cells: should be 1.
-
-Each clock is assigned an identifier and client nodes use this identifier
-to specify the clock which they consume.
-
-All these identifier could be found in <dt-bindings/clock/hi3519-clock.h>.
-
-- #reset-cells: should be 2.
-
-A reset signal can be controlled by writing a bit register in the CRG module.
-The reset specifier consists of two cells. The first cell represents the
-register offset relative to the base address. The second cell represents the
-bit index in the register.
-
-Example: CRG nodes
-CRG: clock-reset-controller@12010000 {
- compatible = "hisilicon,hi3519-crg";
- reg = <0x12010000 0x10000>;
- #clock-cells = <1>;
- #reset-cells = <2>;
-};
-
-Example: consumer nodes
-i2c0: i2c@12110000 {
- compatible = "hisilicon,hi3519-i2c";
- reg = <0x12110000 0x1000>;
- clocks = <&CRG HI3519_I2C0_RST>;
- resets = <&CRG 0xe4 0>;
-};
diff --git a/Bindings/clock/hi3660-clock.txt b/Bindings/clock/hi3660-clock.txt
new file mode 100644
index 000000000000..cc9b86c35758
--- /dev/null
+++ b/Bindings/clock/hi3660-clock.txt
@@ -0,0 +1,42 @@
+* Hisilicon Hi3660 Clock Controller
+
+The Hi3660 clock controller generates and supplies clock to various
+controllers within the Hi3660 SoC.
+
+Required Properties:
+
+- compatible: the compatible should be one of the following strings to
+ indicate the clock controller functionality.
+
+ - "hisilicon,hi3660-crgctrl"
+ - "hisilicon,hi3660-pctrl"
+ - "hisilicon,hi3660-pmuctrl"
+ - "hisilicon,hi3660-sctrl"
+ - "hisilicon,hi3660-iomcu"
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+Each clock is assigned an identifier and client nodes use this identifier
+to specify the clock which they consume.
+
+All these identifier could be found in <dt-bindings/clock/hi3660-clock.h>.
+
+Examples:
+ crg_ctrl: clock-controller@fff35000 {
+ compatible = "hisilicon,hi3660-crgctrl", "syscon";
+ reg = <0x0 0xfff35000 0x0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ uart0: serial@fdf02000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0xfdf02000 0x0 0x1000>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>,
+ <&crg_ctrl HI3660_PCLK>;
+ clock-names = "uartclk", "apb_pclk";
+ status = "disabled";
+ };
diff --git a/Bindings/clock/idt,versaclock5.txt b/Bindings/clock/idt,versaclock5.txt
new file mode 100644
index 000000000000..87e9c47a89a3
--- /dev/null
+++ b/Bindings/clock/idt,versaclock5.txt
@@ -0,0 +1,65 @@
+Binding for IDT VersaClock5 programmable i2c clock generator.
+
+The IDT VersaClock5 are programmable i2c clock generators providing
+from 3 to 12 output clocks.
+
+==I2C device node==
+
+Required properties:
+- compatible: shall be one of "idt,5p49v5923" , "idt,5p49v5933".
+- reg: i2c device address, shall be 0x68 or 0x6a.
+- #clock-cells: from common clock binding; shall be set to 1.
+- clocks: from common clock binding; list of parent clock handles,
+ - 5p49v5923: (required) either or both of XTAL or CLKIN
+ reference clock.
+ - 5p49v5933: (optional) property not present (internal
+ Xtal used) or CLKIN reference
+ clock.
+- clock-names: from common clock binding; clock input names, can be
+ - 5p49v5923: (required) either or both of "xin", "clkin".
+ - 5p49v5933: (optional) property not present or "clkin".
+
+==Mapping between clock specifier and physical pins==
+
+When referencing the provided clock in the DT using phandle and
+clock specifier, the following mapping applies:
+
+5P49V5923:
+ 0 -- OUT0_SEL_I2CB
+ 1 -- OUT1
+ 2 -- OUT2
+
+5P49V5933:
+ 0 -- OUT0_SEL_I2CB
+ 1 -- OUT1
+ 2 -- OUT4
+
+==Example==
+
+/* 25MHz reference crystal */
+ref25: ref25m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+};
+
+i2c-master-node {
+
+ /* IDT 5P49V5923 i2c clock generator */
+ vc5: clock-generator@6a {
+ compatible = "idt,5p49v5923";
+ reg = <0x6a>;
+ #clock-cells = <1>;
+
+ /* Connect XIN input to 25MHz reference */
+ clocks = <&ref25m>;
+ clock-names = "xin";
+ };
+};
+
+/* Consumer referencing the 5P49V5923 pin OUT1 */
+consumer {
+ ...
+ clocks = <&vc5 1>;
+ ...
+}
diff --git a/Bindings/clock/maxim,max77802.txt b/Bindings/clock/maxim,max77802.txt
deleted file mode 100644
index c6dc7835f06c..000000000000
--- a/Bindings/clock/maxim,max77802.txt
+++ /dev/null
@@ -1,44 +0,0 @@
-Binding for Maxim MAX77802 32k clock generator block
-
-This is a part of device tree bindings of MAX77802 multi-function device.
-More information can be found in bindings/mfd/max77802.txt file.
-
-The MAX77802 contains two 32.768khz clock outputs that can be controlled
-(gated/ungated) over I2C.
-
-Following properties should be present in main device node of the MFD chip.
-
-Required properties:
-- #clock-cells: From common clock binding; shall be set to 1.
-
-Optional properties:
-- clock-output-names: From common clock binding.
-
-Each clock is assigned an identifier and client nodes can use this identifier
-to specify the clock which they consume. Following indices are allowed:
- - 0: 32khz_ap clock,
- - 1: 32khz_cp clock.
-
-Clocks are defined as preprocessor macros in dt-bindings/clock/maxim,max77802.h
-header and can be used in device tree sources.
-
-Example: Node of the MFD chip
-
- max77802: max77802@09 {
- compatible = "maxim,max77802";
- interrupt-parent = <&wakeup_eint>;
- interrupts = <26 0>;
- reg = <0x09>;
- #clock-cells = <1>;
-
- /* ... */
- };
-
-Example: Clock consumer node
-
- foo@0 {
- compatible = "bar,foo";
- /* ... */
- clock-names = "my-clock";
- clocks = <&max77802 MAX77802_CLK_32K_AP>;
- };
diff --git a/Bindings/clock/mvebu-corediv-clock.txt b/Bindings/clock/mvebu-corediv-clock.txt
index 520562a7dc2a..c7b4e3a6b2c6 100644
--- a/Bindings/clock/mvebu-corediv-clock.txt
+++ b/Bindings/clock/mvebu-corediv-clock.txt
@@ -7,6 +7,7 @@ Required properties:
- compatible : must be "marvell,armada-370-corediv-clock",
"marvell,armada-375-corediv-clock",
"marvell,armada-380-corediv-clock",
+ "marvell,mv98dx3236-corediv-clock",
- reg : must be the register address of Core Divider control register
- #clock-cells : from common clock binding; shall be set to 1
diff --git a/Bindings/clock/mvebu-cpu-clock.txt b/Bindings/clock/mvebu-cpu-clock.txt
index 99c214660bdc..7f28506eaee7 100644
--- a/Bindings/clock/mvebu-cpu-clock.txt
+++ b/Bindings/clock/mvebu-cpu-clock.txt
@@ -3,6 +3,7 @@ Device Tree Clock bindings for cpu clock of Marvell EBU platforms
Required properties:
- compatible : shall be one of the following:
"marvell,armada-xp-cpu-clock" - cpu clocks for Armada XP
+ "marvell,mv98dx3236-cpu-clock" - cpu clocks for 98DX3236 SoC
- reg : Address and length of the clock complex register set, followed
by address and length of the PMU DFS registers
- #clock-cells : should be set to 1.
diff --git a/Bindings/clock/mvebu-gated-clock.txt b/Bindings/clock/mvebu-gated-clock.txt
index cb8542d910b3..5142efc8099d 100644
--- a/Bindings/clock/mvebu-gated-clock.txt
+++ b/Bindings/clock/mvebu-gated-clock.txt
@@ -117,7 +117,7 @@ ID Clock Peripheral
25 tdm Time Division Mplx
28 xor1 XOR DMA 1
29 sata1lnk
-30 sata1 SATA Host 0
+30 sata1 SATA Host 1
The following is a list of provided IDs for Dove:
ID Clock Peripheral
diff --git a/Bindings/clock/qcom,rpmcc.txt b/Bindings/clock/qcom,rpmcc.txt
index 87d3714b956a..a7235e9e1c97 100644
--- a/Bindings/clock/qcom,rpmcc.txt
+++ b/Bindings/clock/qcom,rpmcc.txt
@@ -11,6 +11,7 @@ Required properties :
compatible "qcom,rpmcc" should be also included.
"qcom,rpmcc-msm8916", "qcom,rpmcc"
+ "qcom,rpmcc-msm8974", "qcom,rpmcc"
"qcom,rpmcc-apq8064", "qcom,rpmcc"
- #clock-cells : shall contain 1
diff --git a/Bindings/clock/qoriq-clock.txt b/Bindings/clock/qoriq-clock.txt
index df9cb5ac5f72..aa3526f229a7 100644
--- a/Bindings/clock/qoriq-clock.txt
+++ b/Bindings/clock/qoriq-clock.txt
@@ -31,6 +31,7 @@ Required properties:
* "fsl,t4240-clockgen"
* "fsl,b4420-clockgen"
* "fsl,b4860-clockgen"
+ * "fsl,ls1012a-clockgen"
* "fsl,ls1021a-clockgen"
* "fsl,ls1043a-clockgen"
* "fsl,ls1046a-clockgen"
diff --git a/Bindings/clock/renesas,cpg-mssr.txt b/Bindings/clock/renesas,cpg-mssr.txt
index c46919412953..f4f944d81308 100644
--- a/Bindings/clock/renesas,cpg-mssr.txt
+++ b/Bindings/clock/renesas,cpg-mssr.txt
@@ -42,6 +42,10 @@ Required Properties:
Domain bindings in
Documentation/devicetree/bindings/power/power_domain.txt.
+ - #reset-cells: Must be 1
+ - The single reset specifier cell must be the module number, as defined
+ in the datasheet.
+
Examples
--------
@@ -55,6 +59,7 @@ Examples
clock-names = "extal", "extalr";
#clock-cells = <2>;
#power-domain-cells = <0>;
+ #reset-cells = <1>;
};
@@ -69,5 +74,6 @@ Examples
dmas = <&dmac1 0x13>, <&dmac1 0x12>;
dma-names = "tx", "rx";
power-domains = <&cpg>;
+ resets = <&cpg 310>;
status = "disabled";
};
diff --git a/Bindings/clock/rockchip,rk3328-cru.txt b/Bindings/clock/rockchip,rk3328-cru.txt
new file mode 100644
index 000000000000..e71c675ba5da
--- /dev/null
+++ b/Bindings/clock/rockchip,rk3328-cru.txt
@@ -0,0 +1,57 @@
+* Rockchip RK3328 Clock and Reset Unit
+
+The RK3328 clock controller generates and supplies clock to various
+controllers within the SoC and also implements a reset controller for SoC
+peripherals.
+
+Required Properties:
+
+- compatible: should be "rockchip,rk3328-cru"
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- #clock-cells: should be 1.
+- #reset-cells: should be 1.
+
+Optional Properties:
+
+- rockchip,grf: phandle to the syscon managing the "general register files"
+ If missing pll rates are not changeable, due to the missing pll lock status.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. All available clocks are defined as
+preprocessor macros in the dt-bindings/clock/rk3328-cru.h headers and can be
+used in device tree sources. Similar macros exist for the reset sources in
+these files.
+
+External clocks:
+
+There are several clocks that are generated outside the SoC. It is expected
+that they are defined using standard clock bindings with following
+clock-output-names:
+ - "xin24m" - crystal input - required,
+ - "clkin_i2s" - external I2S clock - optional,
+ - "gmac_clkin" - external GMAC clock - optional
+ - "phy_50m_out" - output clock of the pll in the mac phy
+
+Example: Clock controller node:
+
+ cru: clock-controller@ff440000 {
+ compatible = "rockchip,rk3328-cru";
+ reg = <0x0 0xff440000 0x0 0x1000>;
+ rockchip,grf = <&grf>;
+
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+Example: UART controller node that consumes the clock generated by the clock
+ controller:
+
+ uart0: serial@ff120000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0xff120000 0x100>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&cru SCLK_UART0>;
+ };
diff --git a/Bindings/clock/rockchip,rk3399-cru.txt b/Bindings/clock/rockchip,rk3399-cru.txt
index 3888dd33fcbd..3bc56fae90ac 100644
--- a/Bindings/clock/rockchip,rk3399-cru.txt
+++ b/Bindings/clock/rockchip,rk3399-cru.txt
@@ -13,6 +13,12 @@ Required Properties:
- #clock-cells: should be 1.
- #reset-cells: should be 1.
+Optional Properties:
+
+- rockchip,grf: phandle to the syscon managing the "general register files".
+ It is used for GRF muxes, if missing any muxes present in the GRF will not
+ be available.
+
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All available clocks are defined as
preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be
diff --git a/Bindings/clock/st,stm32-rcc.txt b/Bindings/clock/st,stm32-rcc.txt
index 0532d815dae3..b240121d2ac9 100644
--- a/Bindings/clock/st,stm32-rcc.txt
+++ b/Bindings/clock/st,stm32-rcc.txt
@@ -10,6 +10,7 @@ Required properties:
- compatible: Should be:
"st,stm32f42xx-rcc"
"st,stm32f469-rcc"
+ "st,stm32f746-rcc"
- reg: should be register base and length as documented in the
datasheet
- #reset-cells: 1, see below
@@ -17,6 +18,9 @@ Required properties:
property, containing a phandle to the clock device node, an index selecting
between gated clocks and other clocks and an index specifying the clock to
use.
+- clocks: External oscillator clock phandle
+ - high speed external clock signal (HSE)
+ - external I2S clock (I2S_CKIN)
Example:
@@ -25,6 +29,7 @@ Example:
#clock-cells = <2>
compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
reg = <0x40023800 0x400>;
+ clocks = <&clk_hse>, <&clk_i2s_ckin>;
};
Specifying gated clocks
@@ -66,6 +71,38 @@ The secondary index is bound with the following magic numbers:
0 SYSTICK
1 FCLK
+ 2 CLK_LSI (low-power clock source)
+ 3 CLK_LSE (generated from a 32.768 kHz low-speed external
+ crystal or ceramic resonator)
+ 4 CLK_HSE_RTC (HSE division factor for RTC clock)
+ 5 CLK_RTC (real-time clock)
+ 6 PLL_VCO_I2S (vco frequency of I2S pll)
+ 7 PLL_VCO_SAI (vco frequency of SAI pll)
+ 8 CLK_LCD (LCD-TFT)
+ 9 CLK_I2S (I2S clocks)
+ 10 CLK_SAI1 (audio clocks)
+ 11 CLK_SAI2
+ 12 CLK_I2SQ_PDIV (post divisor of pll i2s q divisor)
+ 13 CLK_SAIQ_PDIV (post divisor of pll sai q divisor)
+
+ 14 CLK_HSI (Internal ocscillator clock)
+ 15 CLK_SYSCLK (System Clock)
+ 16 CLK_HDMI_CEC (HDMI-CEC clock)
+ 17 CLK_SPDIF (SPDIF-Rx clock)
+ 18 CLK_USART1 (U(s)arts clocks)
+ 19 CLK_USART2
+ 20 CLK_USART3
+ 21 CLK_UART4
+ 22 CLK_UART5
+ 23 CLK_USART6
+ 24 CLK_UART7
+ 25 CLK_UART8
+ 26 CLK_I2C1 (I2S clocks)
+ 27 CLK_I2C2
+ 28 CLK_I2C3
+ 29 CLK_I2C4
+ 30 CLK_LPTIMER (LPTimer1 clock)
+)
Example:
diff --git a/Bindings/clock/st/st,clkgen-divmux.txt b/Bindings/clock/st/st,clkgen-divmux.txt
deleted file mode 100644
index 6247652044a0..000000000000
--- a/Bindings/clock/st/st,clkgen-divmux.txt
+++ /dev/null
@@ -1,49 +0,0 @@
-Binding for a ST divider and multiplexer clock driver.
-
-This binding uses the common clock binding[1].
-Base address is located to the parent node. See clock binding[2]
-
-[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-[2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
-
-Required properties:
-
-- compatible : shall be:
- "st,clkgena-divmux-c65-hs", "st,clkgena-divmux"
- "st,clkgena-divmux-c65-ls", "st,clkgena-divmux"
- "st,clkgena-divmux-c32-odf0", "st,clkgena-divmux"
- "st,clkgena-divmux-c32-odf1", "st,clkgena-divmux"
- "st,clkgena-divmux-c32-odf2", "st,clkgena-divmux"
- "st,clkgena-divmux-c32-odf3", "st,clkgena-divmux"
-
-- #clock-cells : From common clock binding; shall be set to 1.
-
-- clocks : From common clock binding
-
-- clock-output-names : From common clock binding.
-
-Example:
-
- clockgen-a@fd345000 {
- reg = <0xfd345000 0xb50>;
-
- clk_m_a1_div1: clk-m-a1-div1 {
- #clock-cells = <1>;
- compatible = "st,clkgena-divmux-c32-odf1",
- "st,clkgena-divmux";
-
- clocks = <&clk_m_a1_osc_prediv>,
- <&clk_m_a1_pll0 1>, /* PLL0 PHI1 */
- <&clk_m_a1_pll1 1>; /* PLL1 PHI1 */
-
- clock-output-names = "clk-m-rx-icn-ts",
- "clk-m-rx-icn-vdp-0",
- "", /* unused */
- "clk-m-prv-t1-bus",
- "clk-m-icn-reg-12",
- "clk-m-icn-reg-10",
- "", /* unused */
- "clk-m-icn-st231";
- };
- };
-
diff --git a/Bindings/clock/st/st,clkgen-prediv.txt b/Bindings/clock/st/st,clkgen-prediv.txt
deleted file mode 100644
index 604766c2619e..000000000000
--- a/Bindings/clock/st/st,clkgen-prediv.txt
+++ /dev/null
@@ -1,36 +0,0 @@
-Binding for a ST pre-divider clock driver.
-
-This binding uses the common clock binding[1].
-Base address is located to the parent node. See clock binding[2]
-
-[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-[2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
-
-Required properties:
-
-- compatible : shall be:
- "st,clkgena-prediv-c65", "st,clkgena-prediv"
- "st,clkgena-prediv-c32", "st,clkgena-prediv"
-
-- #clock-cells : From common clock binding; shall be set to 0.
-
-- clocks : From common clock binding
-
-- clock-output-names : From common clock binding.
-
-Example:
-
- clockgen-a@fd345000 {
- reg = <0xfd345000 0xb50>;
-
- clk_m_a2_osc_prediv: clk-m-a2-osc-prediv {
- #clock-cells = <0>;
- compatible = "st,clkgena-prediv-c32",
- "st,clkgena-prediv";
-
- clocks = <&clk_sysin>;
-
- clock-output-names = "clk-m-a2-osc-prediv";
- };
- };
-
diff --git a/Bindings/clock/st/st,clkgen-vcc.txt b/Bindings/clock/st/st,clkgen-vcc.txt
deleted file mode 100644
index 109b3eddcb17..000000000000
--- a/Bindings/clock/st/st,clkgen-vcc.txt
+++ /dev/null
@@ -1,61 +0,0 @@
-Binding for a type of STMicroelectronics clock crossbar (VCC).
-
-The crossbar can take up to 4 input clocks and control up to 16
-output clocks. Not all inputs or outputs have to be in use in a
-particular instantiation. Each output can be individually enabled,
-select any of the input clocks and apply a divide (by 1,2,4 or 8) to
-that selected clock.
-
-This binding uses the common clock binding[1].
-
-[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-
-Required properties:
-
-- compatible : shall be:
- "st,stih416-clkgenc", "st,vcc"
- "st,stih416-clkgenf", "st,vcc"
-
-- #clock-cells : from common clock binding; shall be set to 1.
-
-- reg : A Base address and length of the register set.
-
-- clocks : from common clock binding
-
-- clock-output-names : From common clock binding. The block has 16
- clock outputs but not all of them in a specific instance
- have to be used in the SoC. If a clock name is left as
- an empty string then no clock will be created for the
- output associated with that string index. If fewer than
- 16 strings are provided then no clocks will be created
- for the remaining outputs.
-
-Example:
-
- clockgen_c_vcc: clockgen-c-vcc@0xfe8308ac {
- #clock-cells = <1>;
- compatible = "st,stih416-clkgenc", "st,clkgen-vcc";
- reg = <0xfe8308ac 12>;
-
- clocks = <&clk_s_vcc_hd>,
- <&clockgen_c 1>,
- <&clk_s_tmds_fromphy>,
- <&clockgen_c 2>;
-
- clock-output-names = "clk-s-pix-hdmi",
- "clk-s-pix-dvo",
- "clk-s-out-dvo",
- "clk-s-pix-hd",
- "clk-s-hddac",
- "clk-s-denc",
- "clk-s-sddac",
- "clk-s-pix-main",
- "clk-s-pix-aux",
- "clk-s-stfe-frc-0",
- "clk-s-ref-mcru",
- "clk-s-slave-mcru",
- "clk-s-tmds-hdmi",
- "clk-s-hdmi-reject-pll",
- "clk-s-thsens";
- };
-
diff --git a/Bindings/clock/stericsson,abx500.txt b/Bindings/clock/stericsson,abx500.txt
new file mode 100644
index 000000000000..dbaa886b223e
--- /dev/null
+++ b/Bindings/clock/stericsson,abx500.txt
@@ -0,0 +1,20 @@
+Clock bindings for ST-Ericsson ABx500 clocks
+
+Required properties :
+- compatible : shall contain the following:
+ "stericsson,ab8500-clk"
+- #clock-cells should be <1>
+
+The ABx500 clocks need to be placed as a subnode of an AB8500
+device node, see mfd/ab8500.txt
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/ste-ab8500.h header and can be used in device
+tree sources.
+
+Example:
+
+clock-controller {
+ compatible = "stericsson,ab8500-clk";
+ #clock-cells = <1>;
+};
diff --git a/Bindings/clock/sun9i-de.txt b/Bindings/clock/sun9i-de.txt
new file mode 100644
index 000000000000..fb18f327b97a
--- /dev/null
+++ b/Bindings/clock/sun9i-de.txt
@@ -0,0 +1,28 @@
+Allwinner A80 Display Engine Clock Control Binding
+--------------------------------------------------
+
+Required properties :
+- compatible: must contain one of the following compatibles:
+ - "allwinner,sun9i-a80-de-clks"
+
+- reg: Must contain the registers base address and length
+- clocks: phandle to the clocks feeding the display engine subsystem.
+ Three are needed:
+ - "mod": the display engine module clock
+ - "dram": the DRAM bus clock for the system
+ - "bus": the bus clock for the whole display engine subsystem
+- clock-names: Must contain the clock names described just above
+- resets: phandle to the reset control for the display engine subsystem.
+- #clock-cells : must contain 1
+- #reset-cells : must contain 1
+
+Example:
+de_clocks: clock@3000000 {
+ compatible = "allwinner,sun9i-a80-de-clks";
+ reg = <0x03000000 0x30>;
+ clocks = <&ccu CLK_DE>, <&ccu CLK_SDRAM>, <&ccu CLK_BUS_DE>;
+ clock-names = "mod", "dram", "bus";
+ resets = <&ccu RST_BUS_DE>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+};
diff --git a/Bindings/clock/sun9i-usb.txt b/Bindings/clock/sun9i-usb.txt
new file mode 100644
index 000000000000..3564bd4f2a20
--- /dev/null
+++ b/Bindings/clock/sun9i-usb.txt
@@ -0,0 +1,24 @@
+Allwinner A80 USB Clock Control Binding
+---------------------------------------
+
+Required properties :
+- compatible: must contain one of the following compatibles:
+ - "allwinner,sun9i-a80-usb-clocks"
+
+- reg: Must contain the registers base address and length
+- clocks: phandle to the clocks feeding the USB subsystem. Two are needed:
+ - "bus": the bus clock for the whole USB subsystem
+ - "hosc": the high frequency oscillator (usually at 24MHz)
+- clock-names: Must contain the clock names described just above
+- #clock-cells : must contain 1
+- #reset-cells : must contain 1
+
+Example:
+usb_clocks: clock@a08000 {
+ compatible = "allwinner,sun9i-a80-usb-clks";
+ reg = <0x00a08000 0x8>;
+ clocks = <&ccu CLK_BUS_USB>, <&osc24M>;
+ clock-names = "bus", "hosc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+};
diff --git a/Bindings/clock/sunxi-ccu.txt b/Bindings/clock/sunxi-ccu.txt
index 74d44a4273f2..bae5668cf427 100644
--- a/Bindings/clock/sunxi-ccu.txt
+++ b/Bindings/clock/sunxi-ccu.txt
@@ -7,6 +7,8 @@ Required properties :
- "allwinner,sun8i-a23-ccu"
- "allwinner,sun8i-a33-ccu"
- "allwinner,sun8i-h3-ccu"
+ - "allwinner,sun8i-v3s-ccu"
+ - "allwinner,sun9i-a80-ccu"
- "allwinner,sun50i-a64-ccu"
- reg: Must contain the registers base address and length
diff --git a/Bindings/clock/ti,cdce925.txt b/Bindings/clock/ti,cdce925.txt
index 4c7669ad681b..0d01f2d5cc36 100644
--- a/Bindings/clock/ti,cdce925.txt
+++ b/Bindings/clock/ti,cdce925.txt
@@ -1,15 +1,22 @@
-Binding for TO CDCE925 programmable I2C clock synthesizers.
+Binding for TI CDCE913/925/937/949 programmable I2C clock synthesizers.
Reference
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-[2] http://www.ti.com/product/cdce925
+[2] http://www.ti.com/product/cdce913
+[3] http://www.ti.com/product/cdce925
+[4] http://www.ti.com/product/cdce937
+[5] http://www.ti.com/product/cdce949
The driver provides clock sources for each output Y1 through Y5.
Required properties:
- - compatible: Shall be "ti,cdce925"
+ - compatible: Shall be one of the following:
+ - "ti,cdce913": 1-PLL, 3 Outputs
+ - "ti,cdce925": 2-PLL, 5 Outputs
+ - "ti,cdce937": 3-PLL, 7 Outputs
+ - "ti,cdce949": 4-PLL, 9 Outputs
- reg: I2C device address.
- clocks: Points to a fixed parent clock that provides the input frequency.
- #clock-cells: From common clock bindings: Shall be 1.
@@ -18,7 +25,7 @@ Optional properties:
- xtal-load-pf: Crystal load-capacitor value to fine-tune performance on a
board, or to compensate for external influences.
-For both PLL1 and PLL2 an optional child node can be used to specify spread
+For all PLL1, PLL2, ... an optional child node can be used to specify spread
spectrum clocking parameters for a board.
- spread-spectrum: SSC mode as defined in the data sheet.
- spread-spectrum-center: Use "centered" mode instead of "max" mode. When
diff --git a/Bindings/clock/zx296718-clk.txt b/Bindings/clock/zx296718-clk.txt
index 8c18b7b237bf..4ad703808407 100644
--- a/Bindings/clock/zx296718-clk.txt
+++ b/Bindings/clock/zx296718-clk.txt
@@ -13,6 +13,9 @@ Required properties:
"zte,zx296718-lsp1crm":
zx296718 device level clock selection and gating
+ "zte,zx296718-audiocrm":
+ zx296718 audio clock selection, divider and gating
+
- reg: Address and length of the register set
The clock consumer should specify the desired clock by having the clock
diff --git a/Bindings/cpufreq/ti-cpufreq.txt b/Bindings/cpufreq/ti-cpufreq.txt
new file mode 100644
index 000000000000..ba0e15ad5bd9
--- /dev/null
+++ b/Bindings/cpufreq/ti-cpufreq.txt
@@ -0,0 +1,128 @@
+TI CPUFreq and OPP bindings
+================================
+
+Certain TI SoCs, like those in the am335x, am437x, am57xx, and dra7xx
+families support different OPPs depending on the silicon variant in use.
+The ti-cpufreq driver can use revision and an efuse value from the SoC to
+provide the OPP framework with supported hardware information. This is
+used to determine which OPPs from the operating-points-v2 table get enabled
+when it is parsed by the OPP framework.
+
+Required properties:
+--------------------
+In 'cpus' nodes:
+- operating-points-v2: Phandle to the operating-points-v2 table to use.
+
+In 'operating-points-v2' table:
+- compatible: Should be
+ - 'operating-points-v2-ti-cpu' for am335x, am43xx, and dra7xx/am57xx SoCs
+- syscon: A phandle pointing to a syscon node representing the control module
+ register space of the SoC.
+
+Optional properties:
+--------------------
+For each opp entry in 'operating-points-v2' table:
+- opp-supported-hw: Two bitfields indicating:
+ 1. Which revision of the SoC the OPP is supported by
+ 2. Which eFuse bits indicate this OPP is available
+
+ A bitwise AND is performed against these values and if any bit
+ matches, the OPP gets enabled.
+
+Example:
+--------
+
+/* From arch/arm/boot/dts/am33xx.dtsi */
+cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu@0 {
+ compatible = "arm,cortex-a8";
+ device_type = "cpu";
+ reg = <0>;
+
+ operating-points-v2 = <&cpu0_opp_table>;
+
+ clocks = <&dpll_mpu_ck>;
+ clock-names = "cpu";
+
+ clock-latency = <300000>; /* From omap-cpufreq driver */
+ };
+};
+
+/*
+ * cpu0 has different OPPs depending on SoC revision and some on revisions
+ * 0x2 and 0x4 have eFuse bits that indicate if they are available or not
+ */
+cpu0_opp_table: opp-table {
+ compatible = "operating-points-v2-ti-cpu";
+ syscon = <&scm_conf>;
+
+ /*
+ * The three following nodes are marked with opp-suspend
+ * because they can not be enabled simultaneously on a
+ * single SoC.
+ */
+ opp50@300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <950000 931000 969000>;
+ opp-supported-hw = <0x06 0x0010>;
+ opp-suspend;
+ };
+
+ opp100@275000000 {
+ opp-hz = /bits/ 64 <275000000>;
+ opp-microvolt = <1100000 1078000 1122000>;
+ opp-supported-hw = <0x01 0x00FF>;
+ opp-suspend;
+ };
+
+ opp100@300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <1100000 1078000 1122000>;
+ opp-supported-hw = <0x06 0x0020>;
+ opp-suspend;
+ };
+
+ opp100@500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <1100000 1078000 1122000>;
+ opp-supported-hw = <0x01 0xFFFF>;
+ };
+
+ opp100@600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <1100000 1078000 1122000>;
+ opp-supported-hw = <0x06 0x0040>;
+ };
+
+ opp120@600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <1200000 1176000 1224000>;
+ opp-supported-hw = <0x01 0xFFFF>;
+ };
+
+ opp120@720000000 {
+ opp-hz = /bits/ 64 <720000000>;
+ opp-microvolt = <1200000 1176000 1224000>;
+ opp-supported-hw = <0x06 0x0080>;
+ };
+
+ oppturbo@720000000 {
+ opp-hz = /bits/ 64 <720000000>;
+ opp-microvolt = <1260000 1234800 1285200>;
+ opp-supported-hw = <0x01 0xFFFF>;
+ };
+
+ oppturbo@800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <1260000 1234800 1285200>;
+ opp-supported-hw = <0x06 0x0100>;
+ };
+
+ oppnitro@1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <1325000 1298500 1351500>;
+ opp-supported-hw = <0x04 0x0200>;
+ };
+};
diff --git a/Bindings/crypto/brcm,spu-crypto.txt b/Bindings/crypto/brcm,spu-crypto.txt
new file mode 100644
index 000000000000..29b6007568eb
--- /dev/null
+++ b/Bindings/crypto/brcm,spu-crypto.txt
@@ -0,0 +1,22 @@
+The Broadcom Secure Processing Unit (SPU) hardware supports symmetric
+cryptographic offload for Broadcom SoCs. A SoC may have multiple SPU hardware
+blocks.
+
+Required properties:
+- compatible: Should be one of the following:
+ brcm,spum-crypto - for devices with SPU-M hardware
+ brcm,spu2-crypto - for devices with SPU2 hardware
+ brcm,spu2-v2-crypto - for devices with enhanced SPU2 hardware features like SHA3
+ and Rabin Fingerprint support
+ brcm,spum-nsp-crypto - for the Northstar Plus variant of the SPU-M hardware
+
+- reg: Should contain SPU registers location and length.
+- mboxes: The mailbox channel to be used to communicate with the SPU.
+ Mailbox channels correspond to DMA rings on the device.
+
+Example:
+ crypto@612d0000 {
+ compatible = "brcm,spum-crypto";
+ reg = <0 0x612d0000 0 0x900>;
+ mboxes = <&pdc0 0>;
+ };
diff --git a/Bindings/crypto/mediatek-crypto.txt b/Bindings/crypto/mediatek-crypto.txt
new file mode 100644
index 000000000000..c204725e5873
--- /dev/null
+++ b/Bindings/crypto/mediatek-crypto.txt
@@ -0,0 +1,27 @@
+MediaTek cryptographic accelerators
+
+Required properties:
+- compatible: Should be "mediatek,eip97-crypto"
+- reg: Address and length of the register set for the device
+- interrupts: Should contain the five crypto engines interrupts in numeric
+ order. These are global system and four descriptor rings.
+- clocks: the clock used by the core
+- clock-names: the names of the clock listed in the clocks property. These are
+ "ethif", "cryp"
+- power-domains: Must contain a reference to the PM domain.
+
+
+Example:
+ crypto: crypto@1b240000 {
+ compatible = "mediatek,eip97-crypto";
+ reg = <0 0x1b240000 0 0x20000>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
+ <&ethsys CLK_ETHSYS_CRYPTO>;
+ clock-names = "ethif","cryp";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
+ };
diff --git a/Bindings/devfreq/exynos-bus.txt b/Bindings/devfreq/exynos-bus.txt
index d3ec8e676b6b..d085ef90d27c 100644
--- a/Bindings/devfreq/exynos-bus.txt
+++ b/Bindings/devfreq/exynos-bus.txt
@@ -123,6 +123,20 @@ Detailed correlation between sub-blocks and power line according to Exynos SoC:
|--- FSYS
|--- FSYS2
+- In case of Exynos5433, there is VDD_INT power line as following:
+ VDD_INT |--- G2D (parent device)
+ |--- MSCL
+ |--- GSCL
+ |--- JPEG
+ |--- MFC
+ |--- HEVC
+ |--- BUS0
+ |--- BUS1
+ |--- BUS2
+ |--- PERIS (Fixed clock rate)
+ |--- PERIC (Fixed clock rate)
+ |--- FSYS (Fixed clock rate)
+
Example1:
Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to
power line (regulator). The MIF (Memory Interface) AXI bus is used to
diff --git a/Bindings/display/arm,pl11x.txt b/Bindings/display/arm,pl11x.txt
index 3e3039a8a253..ef89ab46b2c9 100644
--- a/Bindings/display/arm,pl11x.txt
+++ b/Bindings/display/arm,pl11x.txt
@@ -22,7 +22,7 @@ Required properties:
- clocks: contains phandle and clock specifier pairs for the entries
in the clock-names property. See
- Documentation/devicetree/binding/clock/clock-bindings.txt
+ Documentation/devicetree/bindings/clock/clock-bindings.txt
Optional properties:
diff --git a/Bindings/display/brcm,bcm-vc4.txt b/Bindings/display/brcm,bcm-vc4.txt
index e2768703ac2b..34c7fddcea39 100644
--- a/Bindings/display/brcm,bcm-vc4.txt
+++ b/Bindings/display/brcm,bcm-vc4.txt
@@ -56,6 +56,18 @@ Required properties for V3D:
- interrupts: The interrupt number
See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
+Required properties for DSI:
+- compatible: Should be "brcm,bcm2835-dsi0" or "brcm,bcm2835-dsi1"
+- reg: Physical base address and length of the DSI block's registers
+- interrupts: The interrupt number
+ See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
+- clocks: a) phy: The DSI PLL clock feeding the DSI analog PHY
+ b) escape: The DSI ESC clock from CPRMAN
+ c) pixel: The DSI pixel clock from CPRMAN
+- clock-output-names:
+ The 3 clocks output from the DSI analog PHY: dsi[01]_byte,
+ dsi[01]_ddr2, and dsi[01]_ddr
+
[1] Documentation/devicetree/bindings/media/video-interfaces.txt
Example:
@@ -99,6 +111,29 @@ dpi: dpi@7e208000 {
};
};
+dsi1: dsi@7e700000 {
+ compatible = "brcm,bcm2835-dsi1";
+ reg = <0x7e700000 0x8c>;
+ interrupts = <2 12>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <1>;
+
+ clocks = <&clocks BCM2835_PLLD_DSI1>,
+ <&clocks BCM2835_CLOCK_DSI1E>,
+ <&clocks BCM2835_CLOCK_DSI1P>;
+ clock-names = "phy", "escape", "pixel";
+
+ clock-output-names = "dsi1_byte", "dsi1_ddr2", "dsi1_ddr";
+
+ pitouchscreen: panel@0 {
+ compatible = "raspberrypi,touchscreen";
+ reg = <0>;
+
+ <...>
+ };
+};
+
vec: vec@7e806000 {
compatible = "brcm,bcm2835-vec";
reg = <0x7e806000 0x1000>;
diff --git a/Bindings/display/bridge/adi,adv7511.txt b/Bindings/display/bridge/adi,adv7511.txt
index 6532a59c9b43..00ea670b8c4d 100644
--- a/Bindings/display/bridge/adi,adv7511.txt
+++ b/Bindings/display/bridge/adi,adv7511.txt
@@ -38,10 +38,22 @@ The following input format properties are required except in "rgb 1x" and
- adi,input-justification: The input bit justification ("left", "evenly",
"right").
+- avdd-supply: A 1.8V supply that powers up the AVDD pin on the chip.
+- dvdd-supply: A 1.8V supply that powers up the DVDD pin on the chip.
+- pvdd-supply: A 1.8V supply that powers up the PVDD pin on the chip.
+- dvdd-3v-supply: A 3.3V supply that powers up the pin called DVDD_3V
+ on the chip.
+- bgvdd-supply: A 1.8V supply that powers up the BGVDD pin. This is
+ needed only for ADV7511.
+
The following properties are required for ADV7533:
- adi,dsi-lanes: Number of DSI data lanes connected to the DSI host. It should
be one of 1, 2, 3 or 4.
+- a2vdd-supply: 1.8V supply that powers up the A2VDD pin on the chip.
+- v3p3-supply: A 3.3V supply that powers up the V3P3 pin on the chip.
+- v1p2-supply: A supply that powers up the V1P2 pin on the chip. It can be
+ either 1.2V or 1.8V.
Optional properties:
diff --git a/Bindings/display/bridge/analogix_dp.txt b/Bindings/display/bridge/analogix_dp.txt
index 4a0f4f7682ad..0c7473dd0e51 100644
--- a/Bindings/display/bridge/analogix_dp.txt
+++ b/Bindings/display/bridge/analogix_dp.txt
@@ -33,7 +33,7 @@ Optional properties for dp-controller:
in Documentation/devicetree/bindings/media/video-interfaces.txt,
please refer to the SoC specific binding document:
* Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
- * Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
+ * Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
-------------------------------------------------------------------------------
diff --git a/Bindings/video/bridge/anx7814.txt b/Bindings/display/bridge/anx7814.txt
index b2a22c28c9b3..b2a22c28c9b3 100644
--- a/Bindings/video/bridge/anx7814.txt
+++ b/Bindings/display/bridge/anx7814.txt
diff --git a/Bindings/display/bridge/dw_hdmi.txt b/Bindings/display/bridge/dw_hdmi.txt
index 5e9a84d6e5f1..33bf981fbe33 100644
--- a/Bindings/display/bridge/dw_hdmi.txt
+++ b/Bindings/display/bridge/dw_hdmi.txt
@@ -1,52 +1,33 @@
-DesignWare HDMI bridge bindings
-
-Required properties:
-- compatible: platform specific such as:
- * "snps,dw-hdmi-tx"
- * "fsl,imx6q-hdmi"
- * "fsl,imx6dl-hdmi"
- * "rockchip,rk3288-dw-hdmi"
-- reg: Physical base address and length of the controller's registers.
-- interrupts: The HDMI interrupt number
-- clocks, clock-names : must have the phandles to the HDMI iahb and isfr clocks,
- as described in Documentation/devicetree/bindings/clock/clock-bindings.txt,
- the clocks are soc specific, the clock-names should be "iahb", "isfr"
--port@[X]: SoC specific port nodes with endpoint definitions as defined
- in Documentation/devicetree/bindings/media/video-interfaces.txt,
- please refer to the SoC specific binding document:
- * Documentation/devicetree/bindings/display/imx/hdmi.txt
- * Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
-
-Optional properties
-- reg-io-width: the width of the reg:1,4, default set to 1 if not present
-- ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing,
- if the property is omitted, a functionally reduced I2C bus
- controller on DW HDMI is probed
-- clocks, clock-names: phandle to the HDMI CEC clock, name should be "cec"
-
-Example:
- hdmi: hdmi@0120000 {
- compatible = "fsl,imx6q-hdmi";
- reg = <0x00120000 0x9000>;
- interrupts = <0 115 0x04>;
- gpr = <&gpr>;
- clocks = <&clks 123>, <&clks 124>;
- clock-names = "iahb", "isfr";
- ddc-i2c-bus = <&i2c2>;
-
- port@0 {
- reg = <0>;
-
- hdmi_mux_0: endpoint {
- remote-endpoint = <&ipu1_di0_hdmi>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- hdmi_mux_1: endpoint {
- remote-endpoint = <&ipu1_di1_hdmi>;
- };
- };
- };
+Synopsys DesignWare HDMI TX Encoder
+===================================
+
+This document defines device tree properties for the Synopsys DesignWare HDMI
+TX Encoder (DWC HDMI TX). It doesn't constitue a device tree binding
+specification by itself but is meant to be referenced by platform-specific
+device tree bindings.
+
+When referenced from platform device tree bindings the properties defined in
+this document are defined as follows. The platform device tree bindings are
+responsible for defining whether each property is required or optional.
+
+- reg: Memory mapped base address and length of the DWC HDMI TX registers.
+
+- reg-io-width: Width of the registers specified by the reg property. The
+ value is expressed in bytes and must be equal to 1 or 4 if specified. The
+ register width defaults to 1 if the property is not present.
+
+- interrupts: Reference to the DWC HDMI TX interrupt.
+
+- clocks: References to all the clocks specified in the clock-names property
+ as specified in Documentation/devicetree/bindings/clock/clock-bindings.txt.
+
+- clock-names: The DWC HDMI TX uses the following clocks.
+
+ - "iahb" is the bus clock for either AHB and APB (mandatory).
+ - "isfr" is the internal register configuration clock (mandatory).
+ - "cec" is the HDMI CEC controller main clock (optional).
+
+- ports: The connectivity of the DWC HDMI TX with the rest of the system is
+ expressed in using ports as specified in the device graph bindings defined
+ in Documentation/devicetree/bindings/graph.txt. The numbering of the ports
+ is platform-specific.
diff --git a/Bindings/video/bridge/sil-sii8620.txt b/Bindings/display/bridge/sil-sii8620.txt
index 9409d9c6a260..9409d9c6a260 100644
--- a/Bindings/video/bridge/sil-sii8620.txt
+++ b/Bindings/display/bridge/sil-sii8620.txt
diff --git a/Bindings/display/bridge/ti,ths8135.txt b/Bindings/display/bridge/ti,ths8135.txt
new file mode 100644
index 000000000000..6ec1a880ac18
--- /dev/null
+++ b/Bindings/display/bridge/ti,ths8135.txt
@@ -0,0 +1,46 @@
+THS8135 Video DAC
+-----------------
+
+This is the binding for Texas Instruments THS8135 Video DAC bridge.
+
+Required properties:
+
+- compatible: Must be "ti,ths8135"
+
+Required nodes:
+
+This device has two video ports. Their connections are modelled using the OF
+graph bindings specified in Documentation/devicetree/bindings/graph.txt.
+
+- Video port 0 for RGB input
+- Video port 1 for VGA output
+
+Example
+-------
+
+vga-bridge {
+ compatible = "ti,ths8135";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ vga_bridge_in: endpoint {
+ remote-endpoint = <&lcdc_out_vga>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ vga_bridge_out: endpoint {
+ remote-endpoint = <&vga_con_in>;
+ };
+ };
+ };
+};
diff --git a/Bindings/display/cirrus,clps711x-fb.txt b/Bindings/display/cirrus,clps711x-fb.txt
index e9c65746e2f1..b0e506610400 100644
--- a/Bindings/display/cirrus,clps711x-fb.txt
+++ b/Bindings/display/cirrus,clps711x-fb.txt
@@ -6,7 +6,7 @@ Required properties:
location and size of the framebuffer memory.
- clocks : phandle + clock specifier pair of the FB reference clock.
- display : phandle to a display node as described in
- Documentation/devicetree/bindings/display/display-timing.txt.
+ Documentation/devicetree/bindings/display/panel/display-timing.txt.
Additionally, the display node has to define properties:
- bits-per-pixel: Bits per pixel.
- ac-prescale : LCD AC bias frequency. This frequency is the required
diff --git a/Bindings/display/exynos/exynos7-decon.txt b/Bindings/display/exynos/exynos7-decon.txt
index 3938caacf11c..9e2e7f6f7609 100644
--- a/Bindings/display/exynos/exynos7-decon.txt
+++ b/Bindings/display/exynos/exynos7-decon.txt
@@ -33,12 +33,12 @@ Required properties:
- i80-if-timings: timing configuration for lcd i80 interface support.
Optional Properties:
-- samsung,power-domain: a phandle to DECON power domain node.
+- power-domains: a phandle to DECON power domain node.
- display-timings: timing settings for DECON, as described in document [1].
Can be used in case timings cannot be provided otherwise
or to override timings provided by the panel.
-[1]: Documentation/devicetree/bindings/display/display-timing.txt
+[1]: Documentation/devicetree/bindings/display/panel/display-timing.txt
Example:
diff --git a/Bindings/display/exynos/exynos_dsim.txt b/Bindings/display/exynos/exynos_dsim.txt
index a78265993665..ca5204b3bc21 100644
--- a/Bindings/display/exynos/exynos_dsim.txt
+++ b/Bindings/display/exynos/exynos_dsim.txt
@@ -4,7 +4,6 @@ Required properties:
- compatible: value should be one of the following
"samsung,exynos3250-mipi-dsi" /* for Exynos3250/3472 SoCs */
"samsung,exynos4210-mipi-dsi" /* for Exynos4 SoCs */
- "samsung,exynos4415-mipi-dsi" /* for Exynos4415 SoC */
"samsung,exynos5410-mipi-dsi" /* for Exynos5410/5420/5440 SoCs */
"samsung,exynos5422-mipi-dsi" /* for Exynos5422/5800 SoCs */
"samsung,exynos5433-mipi-dsi" /* for Exynos5433 SoCs */
diff --git a/Bindings/display/exynos/samsung-fimd.txt b/Bindings/display/exynos/samsung-fimd.txt
index c7c6b9af87ac..5837402c3ade 100644
--- a/Bindings/display/exynos/samsung-fimd.txt
+++ b/Bindings/display/exynos/samsung-fimd.txt
@@ -11,7 +11,6 @@ Required properties:
"samsung,s5pv210-fimd"; /* for S5PV210 SoC */
"samsung,exynos3250-fimd"; /* for Exynos3250/3472 SoCs */
"samsung,exynos4210-fimd"; /* for Exynos4 SoCs */
- "samsung,exynos4415-fimd"; /* for Exynos4415 SoC */
"samsung,exynos5250-fimd"; /* for Exynos5250 SoCs */
"samsung,exynos5420-fimd"; /* for Exynos5420/5422/5800 SoCs */
@@ -83,7 +82,7 @@ in [2]. The following are properties specific to those nodes:
3 - for parallel output,
4 - for write-back interface
-[1]: Documentation/devicetree/bindings/display/display-timing.txt
+[1]: Documentation/devicetree/bindings/display/panel/display-timing.txt
[2]: Documentation/devicetree/bindings/media/video-interfaces.txt
Example:
diff --git a/Bindings/display/hisilicon/hisi-ade.txt b/Bindings/display/hisilicon/hisi-ade.txt
index 38dc9d60eef8..305a0e72a900 100644
--- a/Bindings/display/hisilicon/hisi-ade.txt
+++ b/Bindings/display/hisilicon/hisi-ade.txt
@@ -16,7 +16,7 @@ Required properties:
"clk_ade_core" for the ADE core clock.
"clk_codec_jpeg" for the media NOC QoS clock, which use the same clock with
jpeg codec.
- "clk_ade_pix" for the ADE pixel clok.
+ "clk_ade_pix" for the ADE pixel clock.
- assigned-clocks: Should contain "clk_ade_core" and "clk_codec_jpeg" clocks'
phandle + clock-specifier pairs.
- assigned-clock-rates: clock rates, one for each entry in assigned-clocks.
diff --git a/Bindings/display/imx/fsl,imx-fb.txt b/Bindings/display/imx/fsl,imx-fb.txt
index 00d5f8ea7ec6..7a5c0e204c8e 100644
--- a/Bindings/display/imx/fsl,imx-fb.txt
+++ b/Bindings/display/imx/fsl,imx-fb.txt
@@ -9,7 +9,7 @@ Required properties:
Required nodes:
- display: Phandle to a display node as described in
- Documentation/devicetree/bindings/display/display-timing.txt
+ Documentation/devicetree/bindings/display/panel/display-timing.txt
Additional, the display node has to define properties:
- bits-per-pixel: Bits per pixel
- fsl,pcr: LCDC PCR value
diff --git a/Bindings/display/imx/hdmi.txt b/Bindings/display/imx/hdmi.txt
index 1b756cf9afb0..66a8f86e5d12 100644
--- a/Bindings/display/imx/hdmi.txt
+++ b/Bindings/display/imx/hdmi.txt
@@ -1,29 +1,36 @@
-Device-Tree bindings for HDMI Transmitter
+Freescale i.MX6 DWC HDMI TX Encoder
+===================================
-HDMI Transmitter
-================
+The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
+with a companion PHY IP.
+
+These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
+Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
+following device-specific properties.
-The HDMI Transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
-with accompanying PHY IP.
Required properties:
- - #address-cells : should be <1>
- - #size-cells : should be <0>
- - compatible : should be "fsl,imx6q-hdmi" or "fsl,imx6dl-hdmi".
- - gpr : should be <&gpr>.
- The phandle points to the iomuxc-gpr region containing the HDMI
- multiplexer control register.
- - clocks, clock-names : phandles to the HDMI iahb and isrf clocks, as described
- in Documentation/devicetree/bindings/clock/clock-bindings.txt and
- Documentation/devicetree/bindings/clock/imx6q-clock.txt.
- - port@[0-4]: Up to four port nodes with endpoint definitions as defined in
- Documentation/devicetree/bindings/media/video-interfaces.txt,
- corresponding to the four inputs to the HDMI multiplexer.
-
-Optional properties:
- - ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
-
-example:
+
+- compatible : Shall be one of "fsl,imx6q-hdmi" or "fsl,imx6dl-hdmi".
+- reg: See dw_hdmi.txt.
+- interrupts: HDMI interrupt number
+- clocks: See dw_hdmi.txt.
+- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
+- ports: See dw_hdmi.txt. The DWC HDMI shall have between one and four ports,
+ numbered 0 to 3, corresponding to the four inputs of the HDMI multiplexer.
+ Each port shall have a single endpoint.
+- gpr : Shall contain a phandle to the iomuxc-gpr region containing the HDMI
+ multiplexer control register.
+
+Optional properties
+
+- ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master
+ or the functionally-reduced I2C master contained in the DWC HDMI. When
+ connected to a system I2C master this property contains a phandle to that
+ I2C master controller.
+
+
+Example:
gpr: iomuxc-gpr@020e0000 {
/* ... */
diff --git a/Bindings/display/imx/ldb.txt b/Bindings/display/imx/ldb.txt
index a407462c885e..38c637fa39dd 100644
--- a/Bindings/display/imx/ldb.txt
+++ b/Bindings/display/imx/ldb.txt
@@ -64,7 +64,7 @@ Required properties:
Optional properties (required if display-timings are used):
- ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
- display-timings : A node that describes the display timings as defined in
- Documentation/devicetree/bindings/display/display-timing.txt.
+ Documentation/devicetree/bindings/display/panel/display-timing.txt.
- fsl,data-mapping : should be "spwg" or "jeida"
This describes how the color bits are laid out in the
serialized LVDS signal.
diff --git a/Bindings/display/mediatek/mediatek,disp.txt b/Bindings/display/mediatek/mediatek,disp.txt
index db6e77edbea8..708f5664a316 100644
--- a/Bindings/display/mediatek/mediatek,disp.txt
+++ b/Bindings/display/mediatek/mediatek,disp.txt
@@ -55,7 +55,7 @@ Required properties (DMA function blocks):
"mediatek,<chip>-disp-rdma"
"mediatek,<chip>-disp-wdma"
- larb: Should contain a phandle pointing to the local arbiter device as defined
- in Documentation/devicetree/bindings/soc/mediatek/mediatek,smi-larb.txt
+ in Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
- iommus: Should point to the respective IOMMU block with master port as
argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
for details.
diff --git a/Bindings/display/msm/dsi.txt b/Bindings/display/msm/dsi.txt
index 6b1cab17f52d..fa00e62e1cf6 100644
--- a/Bindings/display/msm/dsi.txt
+++ b/Bindings/display/msm/dsi.txt
@@ -108,7 +108,7 @@ Optional properties:
- qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY
regulator is wanted.
-[1] Documentation/devicetree/bindings/clocks/clock-bindings.txt
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/graph.txt
[3] Documentation/devicetree/bindings/media/video-interfaces.txt
[4] Documentation/devicetree/bindings/display/panel/
diff --git a/Bindings/display/msm/edp.txt b/Bindings/display/msm/edp.txt
index 3a20f6ea5898..e63032be5401 100644
--- a/Bindings/display/msm/edp.txt
+++ b/Bindings/display/msm/edp.txt
@@ -10,7 +10,7 @@ Required properties:
- interrupts: The interrupt signal from the eDP block.
- power-domains: Should be <&mmcc MDSS_GDSC>.
- clocks: device clocks
- See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.
+ See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
- clock-names: the following clocks are required:
* "core_clk"
* "iface_clk"
diff --git a/Bindings/display/msm/gpu.txt b/Bindings/display/msm/gpu.txt
index 67d0a58dbb77..43fac0fe09bb 100644
--- a/Bindings/display/msm/gpu.txt
+++ b/Bindings/display/msm/gpu.txt
@@ -1,23 +1,19 @@
Qualcomm adreno/snapdragon GPU
Required properties:
-- compatible: "qcom,adreno-3xx"
+- compatible: "qcom,adreno-XYZ.W", "qcom,adreno"
+ for example: "qcom,adreno-306.0", "qcom,adreno"
+ Note that you need to list the less specific "qcom,adreno" (since this
+ is what the device is matched on), in addition to the more specific
+ with the chip-id.
- reg: Physical base address and length of the controller's registers.
- interrupts: The interrupt signal from the gpu.
- clocks: device clocks
See ../clocks/clock-bindings.txt for details.
- clock-names: the following clocks are required:
- * "core_clk"
- * "iface_clk"
- * "mem_iface_clk"
-- qcom,chipid: gpu chip-id. Note this may become optional for future
- devices if we can reliably read the chipid from hw
-- qcom,gpu-pwrlevels: list of operating points
- - compatible: "qcom,gpu-pwrlevels"
- - for each qcom,gpu-pwrlevel:
- - qcom,gpu-freq: requested gpu clock speed
- - NOTE: downstream android driver defines additional parameters to
- configure memory bandwidth scaling per OPP.
+ * "core"
+ * "iface"
+ * "mem_iface"
Example:
@@ -25,28 +21,18 @@ Example:
...
gpu: qcom,kgsl-3d0@4300000 {
- compatible = "qcom,adreno-3xx";
+ compatible = "qcom,adreno-320.2", "qcom,adreno";
reg = <0x04300000 0x20000>;
reg-names = "kgsl_3d0_reg_memory";
interrupts = <GIC_SPI 80 0>;
interrupt-names = "kgsl_3d0_irq";
clock-names =
- "core_clk",
- "iface_clk",
- "mem_iface_clk";
+ "core",
+ "iface",
+ "mem_iface";
clocks =
<&mmcc GFX3D_CLK>,
<&mmcc GFX3D_AHB_CLK>,
<&mmcc MMSS_IMEM_AHB_CLK>;
- qcom,chipid = <0x03020100>;
- qcom,gpu-pwrlevels {
- compatible = "qcom,gpu-pwrlevels";
- qcom,gpu-pwrlevel@0 {
- qcom,gpu-freq = <450000000>;
- };
- qcom,gpu-pwrlevel@1 {
- qcom,gpu-freq = <27000000>;
- };
- };
};
};
diff --git a/Bindings/display/msm/hdmi.txt b/Bindings/display/msm/hdmi.txt
index 2ad578984fcf..2d306f402d18 100644
--- a/Bindings/display/msm/hdmi.txt
+++ b/Bindings/display/msm/hdmi.txt
@@ -49,7 +49,7 @@ Required properties:
* "hdmi_tx_l4"
- power-domains: Should be <&mmcc MDSS_GDSC>.
- clocks: device clocks
- See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.
+ See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
- core-vdda-supply: phandle to vdda regulator device node
Example:
diff --git a/Bindings/display/msm/mdp.txt b/Bindings/display/msm/mdp.txt
deleted file mode 100644
index a214f6cd0363..000000000000
--- a/Bindings/display/msm/mdp.txt
+++ /dev/null
@@ -1,59 +0,0 @@
-Qualcomm adreno/snapdragon display controller
-
-Required properties:
-- compatible:
- * "qcom,mdp4" - mdp4
- * "qcom,mdp5" - mdp5
-- reg: Physical base address and length of the controller's registers.
-- interrupts: The interrupt signal from the display controller.
-- connectors: array of phandles for output device(s)
-- clocks: device clocks
- See ../clocks/clock-bindings.txt for details.
-- clock-names: the following clocks are required.
- For MDP4:
- * "core_clk"
- * "iface_clk"
- * "lut_clk"
- * "src_clk"
- * "hdmi_clk"
- * "mdp_clk"
- For MDP5:
- * "bus_clk"
- * "iface_clk"
- * "core_clk_src"
- * "core_clk"
- * "lut_clk" (some MDP5 versions may not need this)
- * "vsync_clk"
-
-Optional properties:
-- gpus: phandle for gpu device
-- clock-names: the following clocks are optional:
- * "lut_clk"
-
-Example:
-
-/ {
- ...
-
- mdp: qcom,mdp@5100000 {
- compatible = "qcom,mdp4";
- reg = <0x05100000 0xf0000>;
- interrupts = <GIC_SPI 75 0>;
- connectors = <&hdmi>;
- gpus = <&gpu>;
- clock-names =
- "core_clk",
- "iface_clk",
- "lut_clk",
- "src_clk",
- "hdmi_clk",
- "mdp_clk";
- clocks =
- <&mmcc MDP_SRC>,
- <&mmcc MDP_AHB_CLK>,
- <&mmcc MDP_LUT_CLK>,
- <&mmcc TV_SRC>,
- <&mmcc HDMI_TV_CLK>,
- <&mmcc MDP_TV_CLK>;
- };
-};
diff --git a/Bindings/display/multi-inno,mi0283qt.txt b/Bindings/display/multi-inno,mi0283qt.txt
new file mode 100644
index 000000000000..eed48c3d4875
--- /dev/null
+++ b/Bindings/display/multi-inno,mi0283qt.txt
@@ -0,0 +1,27 @@
+Multi-Inno MI0283QT display panel
+
+Required properties:
+- compatible: "multi-inno,mi0283qt".
+
+The node for this driver must be a child node of a SPI controller, hence
+all mandatory properties described in ../spi/spi-bus.txt must be specified.
+
+Optional properties:
+- dc-gpios: D/C pin. The presence/absence of this GPIO determines
+ the panel interface mode (IM[3:0] pins):
+ - present: IM=x110 4-wire 8-bit data serial interface
+ - absent: IM=x101 3-wire 9-bit data serial interface
+- reset-gpios: Reset pin
+- power-supply: A regulator node for the supply voltage.
+- backlight: phandle of the backlight device attached to the panel
+- rotation: panel rotation in degrees counter clockwise (0,90,180,270)
+
+Example:
+ mi0283qt@0{
+ compatible = "multi-inno,mi0283qt";
+ reg = <0>;
+ spi-max-frequency = <32000000>;
+ rotation = <90>;
+ dc-gpios = <&gpio 25 0>;
+ backlight = <&backlight>;
+ };
diff --git a/Bindings/display/panel/boe,nv101wxmn51.txt b/Bindings/display/panel/boe,nv101wxmn51.txt
new file mode 100644
index 000000000000..b258d6a91ec6
--- /dev/null
+++ b/Bindings/display/panel/boe,nv101wxmn51.txt
@@ -0,0 +1,7 @@
+BOE OPTOELECTRONICS TECHNOLOGY 10.1" WXGA TFT LCD panel
+
+Required properties:
+- compatible: should be "boe,nv101wxmn51"
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/Bindings/display/panel/netron-dy,e231732.txt b/Bindings/display/panel/netron-dy,e231732.txt
new file mode 100644
index 000000000000..c6d06b5eab51
--- /dev/null
+++ b/Bindings/display/panel/netron-dy,e231732.txt
@@ -0,0 +1,7 @@
+Netron-DY E231732 7.0" WSVGA TFT LCD panel
+
+Required properties:
+- compatible: should be "netron-dy,e231732"
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/Bindings/display/panel/panel-dpi.txt b/Bindings/display/panel/panel-dpi.txt
index b52ac52757df..d4add13e592d 100644
--- a/Bindings/display/panel/panel-dpi.txt
+++ b/Bindings/display/panel/panel-dpi.txt
@@ -12,7 +12,7 @@ Optional properties:
Required nodes:
- "panel-timing" containing video timings
- (Documentation/devicetree/bindings/display/display-timing.txt)
+ (Documentation/devicetree/bindings/display/panel/display-timing.txt)
- Video port for DPI input
Example
diff --git a/Bindings/display/panel/panel.txt b/Bindings/display/panel/panel.txt
new file mode 100644
index 000000000000..e2e6867852b8
--- /dev/null
+++ b/Bindings/display/panel/panel.txt
@@ -0,0 +1,4 @@
+Common display properties
+-------------------------
+
+- rotation: Display rotation in degrees counter clockwise (0,90,180,270)
diff --git a/Bindings/display/panel/samsung,ld9040.txt b/Bindings/display/panel/samsung,ld9040.txt
index fc595d9b985b..354d4d1df4ff 100644
--- a/Bindings/display/panel/samsung,ld9040.txt
+++ b/Bindings/display/panel/samsung,ld9040.txt
@@ -20,7 +20,7 @@ The device node can contain one 'port' child node with one child
'endpoint' node, according to the bindings defined in [3]. This
node should describe panel's video bus.
-[1]: Documentation/devicetree/bindings/display/display-timing.txt
+[1]: Documentation/devicetree/bindings/display/panel/display-timing.txt
[2]: Documentation/devicetree/bindings/spi/spi-bus.txt
[3]: Documentation/devicetree/bindings/media/video-interfaces.txt
diff --git a/Bindings/display/panel/samsung,s6e8aa0.txt b/Bindings/display/panel/samsung,s6e8aa0.txt
index 25701c81b5e0..9e766c5f86da 100644
--- a/Bindings/display/panel/samsung,s6e8aa0.txt
+++ b/Bindings/display/panel/samsung,s6e8aa0.txt
@@ -21,7 +21,7 @@ The device node can contain one 'port' child node with one child
'endpoint' node, according to the bindings defined in [2]. This
node should describe panel's video bus.
-[1]: Documentation/devicetree/bindings/display/display-timing.txt
+[1]: Documentation/devicetree/bindings/display/panel/display-timing.txt
[2]: Documentation/devicetree/bindings/media/video-interfaces.txt
Example:
diff --git a/Bindings/display/panel/tianma,tm070jdhg30.txt b/Bindings/display/panel/tianma,tm070jdhg30.txt
new file mode 100644
index 000000000000..eb9501a82e25
--- /dev/null
+++ b/Bindings/display/panel/tianma,tm070jdhg30.txt
@@ -0,0 +1,7 @@
+Tianma Micro-electronics TM070JDHG30 7.0" WXGA TFT LCD panel
+
+Required properties:
+- compatible: should be "tianma,tm070jdhg30"
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/Bindings/display/rockchip/analogix_dp-rockchip.txt b/Bindings/display/rockchip/analogix_dp-rockchip.txt
index 01cced1c2a18..47665a12786f 100644
--- a/Bindings/display/rockchip/analogix_dp-rockchip.txt
+++ b/Bindings/display/rockchip/analogix_dp-rockchip.txt
@@ -35,7 +35,7 @@ Optional property for different chips:
Required elements: "grf"
For the below properties, please refer to Analogix DP binding document:
- * Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
+ * Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
- phys (required)
- phy-names (required)
- hpd-gpios (optional)
diff --git a/Bindings/display/rockchip/dw_hdmi-rockchip.txt b/Bindings/display/rockchip/dw_hdmi-rockchip.txt
index 668091f27674..046076c6b277 100644
--- a/Bindings/display/rockchip/dw_hdmi-rockchip.txt
+++ b/Bindings/display/rockchip/dw_hdmi-rockchip.txt
@@ -1,24 +1,39 @@
-Rockchip specific extensions to the Synopsys Designware HDMI
-================================
+Rockchip DWC HDMI TX Encoder
+============================
+
+The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
+with a companion PHY IP.
+
+These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
+Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
+following device-specific properties.
+
Required properties:
-- compatible: "rockchip,rk3288-dw-hdmi";
-- reg: Physical base address and length of the controller's registers.
-- clocks: phandle to hdmi iahb and isfr clocks.
-- clock-names: should be "iahb" "isfr"
-- rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
+
+- compatible: Shall contain "rockchip,rk3288-dw-hdmi".
+- reg: See dw_hdmi.txt.
+- reg-io-width: See dw_hdmi.txt. Shall be 4.
- interrupts: HDMI interrupt number
-- ports: contain a port node with endpoint definitions as defined in
- Documentation/devicetree/bindings/media/video-interfaces.txt. For
- vopb,set the reg = <0> and set the reg = <1> for vopl.
-- reg-io-width: the width of the reg:1,4, the value should be 4 on
- rk3288 platform
+- clocks: See dw_hdmi.txt.
+- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
+- ports: See dw_hdmi.txt. The DWC HDMI shall have a single port numbered 0
+ corresponding to the video input of the controller. The port shall have two
+ endpoints, numbered 0 and 1, connected respectively to the vopb and vopl.
+- rockchip,grf: Shall reference the GRF to mux vopl/vopb.
Optional properties
-- ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
-- clocks, clock-names: phandle to the HDMI CEC clock, name should be "cec"
+
+- ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master
+ or the functionally-reduced I2C master contained in the DWC HDMI. When
+ connected to a system I2C master this property contains a phandle to that
+ I2C master controller.
+- clock-names: See dw_hdmi.txt. The "cec" clock is optional.
+- clock-names: May contain "cec" as defined in dw_hdmi.txt.
+
Example:
+
hdmi: hdmi@ff980000 {
compatible = "rockchip,rk3288-dw-hdmi";
reg = <0xff980000 0x20000>;
diff --git a/Bindings/display/ssd1307fb.txt b/Bindings/display/ssd1307fb.txt
index eb31ed47a283..209d931ef16c 100644
--- a/Bindings/display/ssd1307fb.txt
+++ b/Bindings/display/ssd1307fb.txt
@@ -8,14 +8,15 @@ Required properties:
0x3c or 0x3d
- pwm: Should contain the pwm to use according to the OF device tree PWM
specification [0]. Only required for the ssd1307.
- - reset-gpios: Should contain the GPIO used to reset the OLED display
- solomon,height: Height in pixel of the screen driven by the controller
- solomon,width: Width in pixel of the screen driven by the controller
- solomon,page-offset: Offset of pages (band of 8 pixels) that the screen is
mapped to.
Optional properties:
- - reset-active-low: Is the reset gpio is active on physical low?
+ - reset-gpios: The GPIO used to reset the OLED display, if available. See
+ Documentation/devicetree/bindings/gpio/gpio.txt for details.
+ - vbat-supply: The supply for VBAT
- solomon,segment-no-remap: Display needs normal (non-inverted) data column
to segment mapping
- solomon,com-seq: Display uses sequential COM pin configuration
diff --git a/Bindings/display/ti/ti,tfp410.txt b/Bindings/display/ti/ti,tfp410.txt
deleted file mode 100644
index 2cbe32a3d0bb..000000000000
--- a/Bindings/display/ti/ti,tfp410.txt
+++ /dev/null
@@ -1,41 +0,0 @@
-TFP410 DPI to DVI encoder
-=========================
-
-Required properties:
-- compatible: "ti,tfp410"
-
-Optional properties:
-- powerdown-gpios: power-down gpio
-
-Required nodes:
-- Video port 0 for DPI input
-- Video port 1 for DVI output
-
-Example
--------
-
-tfp410: encoder@0 {
- compatible = "ti,tfp410";
- powerdown-gpios = <&twl_gpio 2 GPIO_ACTIVE_LOW>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- tfp410_in: endpoint@0 {
- remote-endpoint = <&dpi_out>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- tfp410_out: endpoint@0 {
- remote-endpoint = <&dvi_connector_in>;
- };
- };
- };
-};
diff --git a/Bindings/display/tilcdc/panel.txt b/Bindings/display/tilcdc/panel.txt
index f20b31cdc59a..808216310ea2 100644
--- a/Bindings/display/tilcdc/panel.txt
+++ b/Bindings/display/tilcdc/panel.txt
@@ -15,7 +15,7 @@ Required properties:
- display-timings: typical videomode of lcd panel. Multiple video modes
can be listed if the panel supports multiple timings, but the 'native-mode'
should be the preferred/default resolution. Refer to
- Documentation/devicetree/bindings/display/display-timing.txt for display
+ Documentation/devicetree/bindings/display/panel/display-timing.txt for display
timing binding details.
Optional properties:
diff --git a/Bindings/display/zte,vou.txt b/Bindings/display/zte,vou.txt
index 740e5bd2e4f7..9c356284232b 100644
--- a/Bindings/display/zte,vou.txt
+++ b/Bindings/display/zte,vou.txt
@@ -49,6 +49,15 @@ Required properties:
"osc_clk"
"xclk"
+* TV Encoder output device
+
+Required properties:
+ - compatible: should be "zte,zx296718-tvenc"
+ - reg: Physical base address and length of the TVENC device IO region
+ - zte,tvenc-power-control: the phandle to SYSCTRL block followed by two
+ integer cells. The first cell is the offset of SYSCTRL register used
+ to control TV Encoder DAC power, and the second cell is the bit mask.
+
Example:
vou: vou@1440000 {
@@ -81,4 +90,10 @@ vou: vou@1440000 {
<&topcrm HDMI_XCLK>;
clock-names = "osc_cec", "osc_clk", "xclk";
};
+
+ tvenc: tvenc@2000 {
+ compatible = "zte,zx296718-tvenc";
+ reg = <0x2000 0x1000>;
+ zte,tvenc-power-control = <&sysctrl 0x170 0x10>;
+ };
};
diff --git a/Bindings/dma/stm32-dma.txt b/Bindings/dma/stm32-dma.txt
index 70cd13f1588a..4408af693d0c 100644
--- a/Bindings/dma/stm32-dma.txt
+++ b/Bindings/dma/stm32-dma.txt
@@ -40,8 +40,7 @@ Example:
DMA clients connected to the STM32 DMA controller must use the format
described in the dma.txt file, using a five-cell specifier for each
-channel: a phandle plus four integer cells.
-The four cells in order are:
+channel: a phandle to the DMA controller plus the following four integer cells:
1. The channel id
2. The request line number
@@ -61,7 +60,7 @@ The four cells in order are:
0x1: medium
0x2: high
0x3: very high
-5. A 32bit mask specifying the DMA FIFO threshold configuration which are device
+4. A 32bit mask specifying the DMA FIFO threshold configuration which are device
dependent:
-bit 0-1: Fifo threshold
0x0: 1/4 full FIFO
diff --git a/Bindings/dma/xilinx/xilinx_vdma.txt b/Bindings/dma/xilinx/xilinx_vdma.txt
deleted file mode 100644
index a1f2683c49bf..000000000000
--- a/Bindings/dma/xilinx/xilinx_vdma.txt
+++ /dev/null
@@ -1,107 +0,0 @@
-Xilinx AXI VDMA engine, it does transfers between memory and video devices.
-It can be configured to have one channel or two channels. If configured
-as two channels, one is to transmit to the video device and another is
-to receive from the video device.
-
-Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream
-target devices. It can be configured to have one channel or two channels.
-If configured as two channels, one is to transmit to the device and another
-is to receive from the device.
-
-Xilinx AXI CDMA engine, it does transfers between memory-mapped source
-address and a memory-mapped destination address.
-
-Required properties:
-- compatible: Should be "xlnx,axi-vdma-1.00.a" or "xlnx,axi-dma-1.00.a" or
- "xlnx,axi-cdma-1.00.a""
-- #dma-cells: Should be <1>, see "dmas" property below
-- reg: Should contain VDMA registers location and length.
-- xlnx,addrwidth: Should be the vdma addressing size in bits(ex: 32 bits).
-- dma-ranges: Should be as the following <dma_addr cpu_addr max_len>.
-- dma-channel child node: Should have at least one channel and can have up to
- two channels per device. This node specifies the properties of each
- DMA channel (see child node properties below).
-- clocks: Input clock specifier. Refer to common clock bindings.
-- clock-names: List of input clocks
- For VDMA:
- Required elements: "s_axi_lite_aclk"
- Optional elements: "m_axi_mm2s_aclk" "m_axi_s2mm_aclk",
- "m_axis_mm2s_aclk", "s_axis_s2mm_aclk"
- For CDMA:
- Required elements: "s_axi_lite_aclk", "m_axi_aclk"
- FOR AXIDMA:
- Required elements: "s_axi_lite_aclk"
- Optional elements: "m_axi_mm2s_aclk", "m_axi_s2mm_aclk",
- "m_axi_sg_aclk"
-
-Required properties for VDMA:
-- xlnx,num-fstores: Should be the number of framebuffers as configured in h/w.
-
-Optional properties:
-- xlnx,include-sg: Tells configured for Scatter-mode in
- the hardware.
-Optional properties for VDMA:
-- xlnx,flush-fsync: Tells which channel to Flush on Frame sync.
- It takes following values:
- {1}, flush both channels
- {2}, flush mm2s channel
- {3}, flush s2mm channel
-
-Required child node properties:
-- compatible: It should be either "xlnx,axi-vdma-mm2s-channel" or
- "xlnx,axi-vdma-s2mm-channel".
-- interrupts: Should contain per channel VDMA interrupts.
-- xlnx,datawidth: Should contain the stream data width, take values
- {32,64...1024}.
-
-Optional child node properties:
-- xlnx,include-dre: Tells hardware is configured for Data
- Realignment Engine.
-Optional child node properties for VDMA:
-- xlnx,genlock-mode: Tells Genlock synchronization is
- enabled/disabled in hardware.
-
-Example:
-++++++++
-
-axi_vdma_0: axivdma@40030000 {
- compatible = "xlnx,axi-vdma-1.00.a";
- #dma_cells = <1>;
- reg = < 0x40030000 0x10000 >;
- dma-ranges = <0x00000000 0x00000000 0x40000000>;
- xlnx,num-fstores = <0x8>;
- xlnx,flush-fsync = <0x1>;
- xlnx,addrwidth = <0x20>;
- clocks = <&clk 0>, <&clk 1>, <&clk 2>, <&clk 3>, <&clk 4>;
- clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk",
- "m_axis_mm2s_aclk", "s_axis_s2mm_aclk";
- dma-channel@40030000 {
- compatible = "xlnx,axi-vdma-mm2s-channel";
- interrupts = < 0 54 4 >;
- xlnx,datawidth = <0x40>;
- } ;
- dma-channel@40030030 {
- compatible = "xlnx,axi-vdma-s2mm-channel";
- interrupts = < 0 53 4 >;
- xlnx,datawidth = <0x40>;
- } ;
-} ;
-
-
-* DMA client
-
-Required properties:
-- dmas: a list of <[Video DMA device phandle] [Channel ID]> pairs,
- where Channel ID is '0' for write/tx and '1' for read/rx
- channel.
-- dma-names: a list of DMA channel names, one per "dmas" entry
-
-Example:
-++++++++
-
-vdmatest_0: vdmatest@0 {
- compatible ="xlnx,axi-vdma-test-1.00.a";
- dmas = <&axi_vdma_0 0
- &axi_vdma_0 1>;
- dma-names = "vdma0", "vdma1";
-} ;
diff --git a/Bindings/eeprom/eeprom.txt b/Bindings/eeprom/eeprom.txt
index 735bc94444bb..5696eb508e95 100644
--- a/Bindings/eeprom/eeprom.txt
+++ b/Bindings/eeprom/eeprom.txt
@@ -10,6 +10,8 @@ Required properties:
"catalyst,24c32"
+ "microchip,24c128"
+
"ramtron,24c64"
"renesas,r1ex24002"
diff --git a/Bindings/gpio/cortina,gemini-gpio.txt b/Bindings/gpio/cortina,gemini-gpio.txt
new file mode 100644
index 000000000000..5c9246c054e5
--- /dev/null
+++ b/Bindings/gpio/cortina,gemini-gpio.txt
@@ -0,0 +1,24 @@
+Cortina Systems Gemini GPIO Controller
+
+Required properties:
+
+- compatible : Must be "cortina,gemini-gpio"
+- reg : Should contain registers location and length
+- interrupts : Should contain the interrupt line for the GPIO block
+- gpio-controller : marks this as a GPIO controller
+- #gpio-cells : Should be 2, see gpio/gpio.txt
+- interrupt-controller : marks this as an interrupt controller
+- #interrupt-cells : a standard two-cell interrupt flag, see
+ interrupt-controller/interrupts.txt
+
+Example:
+
+gpio@4d000000 {
+ compatible = "cortina,gemini-gpio";
+ reg = <0x4d000000 0x100>;
+ interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+};
diff --git a/Bindings/gpio/gpio-pca953x.txt b/Bindings/gpio/gpio-pca953x.txt
index 08dd15f89ba9..e63935710011 100644
--- a/Bindings/gpio/gpio-pca953x.txt
+++ b/Bindings/gpio/gpio-pca953x.txt
@@ -29,6 +29,10 @@ Required properties:
onsemi,pca9654
exar,xra1202
+Optional properties:
+ - reset-gpios: GPIO specification for the RESET input. This is an
+ active low signal to the PCA953x.
+
Example:
diff --git a/Bindings/gpio/gpio-sx150x.txt b/Bindings/gpio/gpio-sx150x.txt
deleted file mode 100644
index c809acb9c71b..000000000000
--- a/Bindings/gpio/gpio-sx150x.txt
+++ /dev/null
@@ -1,41 +0,0 @@
-SEMTECH SX150x GPIO expander bindings
-
-
-Required properties:
-
-- compatible: should be "semtech,sx1506q",
- "semtech,sx1508q",
- "semtech,sx1509q",
- "semtech,sx1502q".
-
-- reg: The I2C slave address for this device.
-
-- interrupt-parent: phandle of the parent interrupt controller.
-
-- interrupts: Interrupt specifier for the controllers interrupt.
-
-- #gpio-cells: Should be 2. The first cell is the GPIO number and the
- second cell is used to specify optional parameters:
- bit 0: polarity (0: normal, 1: inverted)
-
-- gpio-controller: Marks the device as a GPIO controller.
-
-- interrupt-controller: Marks the device as a interrupt controller.
-
-The GPIO expander can optionally be used as an interrupt controller, in
-which case it uses the default two cell specifier as described in
-Documentation/devicetree/bindings/interrupt-controller/interrupts.txt.
-
-Example:
-
- i2c_gpio_expander@20{
- #gpio-cells = <2>;
- #interrupt-cells = <2>;
- compatible = "semtech,sx1506q";
- reg = <0x20>;
- interrupt-parent = <&gpio_1>;
- interrupts = <16 0>;
-
- gpio-controller;
- interrupt-controller;
- };
diff --git a/Bindings/gpio/gpio-tps65086.txt b/Bindings/gpio/gpio-tps65086.txt
deleted file mode 100644
index ba051074bedc..000000000000
--- a/Bindings/gpio/gpio-tps65086.txt
+++ /dev/null
@@ -1,16 +0,0 @@
-* TPS65086 GPO Controller bindings
-
-Required properties:
- - compatible : Should be "ti,tps65086-gpio".
- - gpio-controller : Marks the device node as a GPIO Controller.
- - #gpio-cells : Should be two. The first cell is the pin number
- and the second cell is used to specify flags.
- See ../gpio/gpio.txt for possible values.
-
-Example:
-
- gpio4: gpio {
- compatible = "ti,tps65086-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- };
diff --git a/Bindings/gpio/gpio.txt b/Bindings/gpio/gpio.txt
index 68d28f62a6f4..84ede036f73d 100644
--- a/Bindings/gpio/gpio.txt
+++ b/Bindings/gpio/gpio.txt
@@ -187,10 +187,10 @@ gpio-controller's driver probe function.
Each GPIO hog definition is represented as a child node of the GPIO controller.
Required properties:
-- gpio-hog: A property specifying that this child node represent a GPIO hog.
-- gpios: Store the GPIO information (id, flags, ...). Shall contain the
- number of cells specified in its parent node (GPIO controller
- node).
+- gpio-hog: A property specifying that this child node represents a GPIO hog.
+- gpios: Store the GPIO information (id, flags, ...) for each GPIO to
+ affect. Shall contain an integer multiple of the number of cells
+ specified in its parent node (GPIO controller node).
Only one of the following properties scanned in the order shown below.
This means that when multiple properties are present they will be searched
in the order presented below and the first match is taken as the intended
diff --git a/Bindings/gpu/arm,mali-utgard.txt b/Bindings/gpu/arm,mali-utgard.txt
new file mode 100644
index 000000000000..476f5ea6c627
--- /dev/null
+++ b/Bindings/gpu/arm,mali-utgard.txt
@@ -0,0 +1,81 @@
+ARM Mali Utgard GPU
+===================
+
+Required properties:
+ - compatible
+ * Must be one of the following:
+ + "arm,mali-300"
+ + "arm,mali-400"
+ + "arm,mali-450"
+ * And, optionally, one of the vendor specific compatible:
+ + allwinner,sun4i-a10-mali
+ + allwinner,sun7i-a20-mali
+ + amlogic,meson-gxbb-mali
+ + amlogic,meson-gxl-mali
+ + stericsson,db8500-mali
+
+ - reg: Physical base address and length of the GPU registers
+
+ - interrupts: an entry for each entry in interrupt-names.
+ See ../interrupt-controller/interrupts.txt for details.
+
+ - interrupt-names:
+ * ppX: Pixel Processor X interrupt (X from 0 to 7)
+ * ppmmuX: Pixel Processor X MMU interrupt (X from 0 to 7)
+ * pp: Pixel Processor broadcast interrupt (mali-450 only)
+ * gp: Geometry Processor interrupt
+ * gpmmu: Geometry Processor MMU interrupt
+
+ - clocks: an entry for each entry in clock-names
+ - clock-names:
+ * bus: bus clock for the GPU
+ * core: clock driving the GPU itself
+
+Optional properties:
+ - interrupt-names and interrupts:
+ * pmu: Power Management Unit interrupt, if implemented in hardware
+
+Vendor-specific bindings
+------------------------
+
+The Mali GPU is integrated very differently from one SoC to
+another. In order to accomodate those differences, you have the option
+to specify one more vendor-specific compatible, among:
+
+ - allwinner,sun4i-a10-mali
+ Required properties:
+ * resets: phandle to the reset line for the GPU
+
+ - allwinner,sun7i-a20-mali
+ Required properties:
+ * resets: phandle to the reset line for the GPU
+
+ - stericsson,db8500-mali
+ Required properties:
+ * interrupt-names and interrupts:
+ + combined: combined interrupt of all of the above lines
+
+Example:
+
+mali: gpu@1c40000 {
+ compatible = "allwinner,sun7i-a20-mali", "arm,mali-400";
+ reg = <0x01c40000 0x10000>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gp",
+ "gpmmu",
+ "pp0",
+ "ppmmu0",
+ "pp1",
+ "ppmmu1",
+ "pmu";
+ clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
+ clock-names = "bus", "core";
+ resets = <&ccu RST_BUS_GPU>;
+};
+
diff --git a/Bindings/hwmon/adc128d818.txt b/Bindings/hwmon/adc128d818.txt
new file mode 100644
index 000000000000..08bab0e94d25
--- /dev/null
+++ b/Bindings/hwmon/adc128d818.txt
@@ -0,0 +1,38 @@
+TI ADC128D818 ADC System Monitor With Temperature Sensor
+--------------------------------------------------------
+
+Operation modes:
+
+ - Mode 0: 7 single-ended voltage readings (IN0-IN6),
+ 1 temperature reading (internal)
+ - Mode 1: 8 single-ended voltage readings (IN0-IN7),
+ no temperature
+ - Mode 2: 4 pseudo-differential voltage readings
+ (IN0-IN1, IN3-IN2, IN4-IN5, IN7-IN6),
+ 1 temperature reading (internal)
+ - Mode 3: 4 single-ended voltage readings (IN0-IN3),
+ 2 pseudo-differential voltage readings
+ (IN4-IN5, IN7-IN6),
+ 1 temperature reading (internal)
+
+If no operation mode is configured via device tree, the driver keeps the
+currently active chip operation mode (default is mode 0).
+
+
+Required node properties:
+
+ - compatible: must be set to "ti,adc128d818"
+ - reg: I2C address of the device
+
+Optional node properties:
+
+ - ti,mode: Operation mode (see above).
+
+
+Example (operation mode 2):
+
+ adc128d818@1d {
+ compatible = "ti,adc128d818";
+ reg = <0x1d>;
+ ti,mode = <2>;
+ };
diff --git a/Bindings/hwmon/lm70.txt b/Bindings/hwmon/lm70.txt
index e7fd921aa4f1..ea417a0d32af 100644
--- a/Bindings/hwmon/lm70.txt
+++ b/Bindings/hwmon/lm70.txt
@@ -4,6 +4,7 @@ Required properties:
- compatible: one of
"ti,lm70"
"ti,tmp121"
+ "ti,tmp122"
"ti,lm71"
"ti,lm74"
diff --git a/Bindings/hwmon/lm90.txt b/Bindings/hwmon/lm90.txt
index e8632486b9ef..97581266e329 100644
--- a/Bindings/hwmon/lm90.txt
+++ b/Bindings/hwmon/lm90.txt
@@ -33,6 +33,11 @@ Optional properties:
LM90 "-ALERT" pin output.
See interrupt-controller/interrupts.txt for the format.
+- #thermal-sensor-cells: should be set to 1. See thermal/thermal.txt for
+ details. See <include/dt-bindings/thermal/lm90.h> for the
+ definition of the local, remote and 2nd remote sensor index
+ constants.
+
Example LM90 node:
temp-sensor {
@@ -41,4 +46,5 @@ temp-sensor {
vcc-supply = <&palmas_ldo6_reg>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(O, 4) IRQ_TYPE_LEVEL_LOW>;
+ #thermal-sensor-cells = <1>;
}
diff --git a/Bindings/hwmon/sht15.txt b/Bindings/hwmon/sht15.txt
new file mode 100644
index 000000000000..6a80277cc426
--- /dev/null
+++ b/Bindings/hwmon/sht15.txt
@@ -0,0 +1,19 @@
+Sensirion SHT15 Humidity and Temperature Sensor
+
+Required properties:
+
+ - "compatible": must be "sensirion,sht15".
+ - "data-gpios": GPIO connected to the data line.
+ - "clk-gpios": GPIO connected to the clock line.
+ - "vcc-supply": regulator that drives the VCC pin.
+
+Example:
+
+ sensor {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sensor>;
+ compatible = "sensirion,sht15";
+ clk-gpios = <&gpio4 12 0>;
+ data-gpios = <&gpio4 13 0>;
+ vcc-supply = <&reg_sht15>;
+ };
diff --git a/Bindings/hwmon/stts751.txt b/Bindings/hwmon/stts751.txt
new file mode 100644
index 000000000000..3ee1dc30e72f
--- /dev/null
+++ b/Bindings/hwmon/stts751.txt
@@ -0,0 +1,15 @@
+* STTS751 thermometer.
+
+Required node properties:
+- compatible: "stts751"
+- reg: I2C bus address of the device
+
+Optional properties:
+- smbus-timeout-disable: when set, the smbus timeout function will be disabled
+
+Example stts751 node:
+
+temp-sensor {
+ compatible = "stts751";
+ reg = <0x48>;
+}
diff --git a/Bindings/i2c/i2c-mux-pca954x.txt b/Bindings/i2c/i2c-mux-pca954x.txt
index cf53d5fba20a..aa097045a10e 100644
--- a/Bindings/i2c/i2c-mux-pca954x.txt
+++ b/Bindings/i2c/i2c-mux-pca954x.txt
@@ -19,7 +19,14 @@ Optional Properties:
- i2c-mux-idle-disconnect: Boolean; if defined, forces mux to disconnect all
children in idle state. This is necessary for example, if there are several
multiplexers on the bus and the devices behind them use same I2C addresses.
-
+ - interrupt-parent: Phandle for the interrupt controller that services
+ interrupts for this device.
+ - interrupts: Interrupt mapping for IRQ.
+ - interrupt-controller: Marks the device node as an interrupt controller.
+ - #interrupt-cells : Should be two.
+ - first cell is the pin number
+ - second cell is used to specify flags.
+ See also Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
Example:
@@ -29,6 +36,11 @@ Example:
#size-cells = <0>;
reg = <0x74>;
+ interrupt-parent = <&ipic>;
+ interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/Bindings/i2c/i2c-sh_mobile.txt b/Bindings/i2c/i2c-sh_mobile.txt
index 7716acc55dec..ae9c2a735f39 100644
--- a/Bindings/i2c/i2c-sh_mobile.txt
+++ b/Bindings/i2c/i2c-sh_mobile.txt
@@ -10,6 +10,7 @@ Required properties:
- "renesas,iic-r8a7793" (R-Car M2-N)
- "renesas,iic-r8a7794" (R-Car E2)
- "renesas,iic-r8a7795" (R-Car H3)
+ - "renesas,iic-r8a7796" (R-Car M3-W)
- "renesas,iic-sh73a0" (SH-Mobile AG5)
- "renesas,rcar-gen2-iic" (generic R-Car Gen2 compatible device)
- "renesas,rcar-gen3-iic" (generic R-Car Gen3 compatible device)
diff --git a/Bindings/i2c/i2c-stm32.txt b/Bindings/i2c/i2c-stm32.txt
new file mode 100644
index 000000000000..78eaf7b718ed
--- /dev/null
+++ b/Bindings/i2c/i2c-stm32.txt
@@ -0,0 +1,33 @@
+* I2C controller embedded in STMicroelectronics STM32 I2C platform
+
+Required properties :
+- compatible : Must be "st,stm32f4-i2c"
+- reg : Offset and length of the register set for the device
+- interrupts : Must contain the interrupt id for I2C event and then the
+ interrupt id for I2C error.
+- resets: Must contain the phandle to the reset controller.
+- clocks: Must contain the input clock of the I2C instance.
+- A pinctrl state named "default" must be defined to set pins in mode of
+ operation for I2C transfer
+- #address-cells = <1>;
+- #size-cells = <0>;
+
+Optional properties :
+- clock-frequency : Desired I2C bus clock frequency in Hz. If not specified,
+ the default 100 kHz frequency will be used. As only Normal and Fast modes
+ are supported, possible values are 100000 and 400000.
+
+Example :
+
+ i2c@40005400 {
+ compatible = "st,stm32f4-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x40005400 0x400>;
+ interrupts = <31>,
+ <32>;
+ resets = <&rcc 277>;
+ clocks = <&rcc 0 149>;
+ pinctrl-0 = <&i2c1_sda_pin>, <&i2c1_scl_pin>;
+ pinctrl-names = "default";
+ };
diff --git a/Bindings/i2c/nvidia,tegra186-bpmp-i2c.txt b/Bindings/i2c/nvidia,tegra186-bpmp-i2c.txt
new file mode 100644
index 000000000000..ab240e10debc
--- /dev/null
+++ b/Bindings/i2c/nvidia,tegra186-bpmp-i2c.txt
@@ -0,0 +1,42 @@
+NVIDIA Tegra186 BPMP I2C controller
+
+In Tegra186, the BPMP (Boot and Power Management Processor) owns certain HW
+devices, such as the I2C controller for the power management I2C bus. Software
+running on other CPUs must perform IPC to the BPMP in order to execute
+transactions on that I2C bus. This binding describes an I2C bus that is
+accessed in such a fashion.
+
+The BPMP I2C node must be located directly inside the main BPMP node. See
+../firmware/nvidia,tegra186-bpmp.txt for details of the BPMP binding.
+
+This node represents an I2C controller. See ../i2c/i2c.txt for details of the
+core I2C binding.
+
+Required properties:
+- compatible:
+ Array of strings.
+ One of:
+ - "nvidia,tegra186-bpmp-i2c".
+- #address-cells: Address cells for I2C device address.
+ Single-cell integer.
+ Must be <1>.
+- #size-cells:
+ Single-cell integer.
+ Must be <0>.
+- nvidia,bpmp-bus-id:
+ Single-cell integer.
+ Indicates the I2C bus number this DT node represent, as defined by the
+ BPMP firmware.
+
+Example:
+
+bpmp {
+ ...
+
+ i2c {
+ compatible = "nvidia,tegra186-bpmp-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ nvidia,bpmp-bus-id = <5>;
+ };
+};
diff --git a/Bindings/i2c/trivial-devices.txt b/Bindings/i2c/trivial-devices.txt
index cdd7b48826c3..ad10fbe61562 100644
--- a/Bindings/i2c/trivial-devices.txt
+++ b/Bindings/i2c/trivial-devices.txt
@@ -36,6 +36,7 @@ dallas,ds1775 Tiny Digital Thermometer and Thermostat
dallas,ds3232 Extremely Accurate I²C RTC with Integrated Crystal and SRAM
dallas,ds4510 CPU Supervisor with Nonvolatile Memory and Programmable I/O
dallas,ds75 Digital Thermometer and Thermostat
+devantech,srf08 Devantech SRF08 ultrasonic ranger
dlg,da9053 DA9053: flexible system level PMIC with multicore support
dlg,da9063 DA9063: system PMIC for quad-core application processors
domintech,dmard09 DMARD09: 3-axis Accelerometer
diff --git a/Bindings/iio/accel/lis302.txt b/Bindings/iio/accel/lis302.txt
index 2a19bff9693f..dfdce67826ba 100644
--- a/Bindings/iio/accel/lis302.txt
+++ b/Bindings/iio/accel/lis302.txt
@@ -5,7 +5,7 @@ that apply in on the generic device (independent from the bus).
Required properties for the SPI bindings:
- - compatible: should be set to "st,lis3lv02d_spi"
+ - compatible: should be set to "st,lis3lv02d-spi"
- reg: the chipselect index
- spi-max-frequency: maximal bus speed, should be set to 1000000 unless
constrained by external circuitry
diff --git a/Bindings/iio/adc/amlogic,meson-saradc.txt b/Bindings/iio/adc/amlogic,meson-saradc.txt
new file mode 100644
index 000000000000..f9e3ff2c656e
--- /dev/null
+++ b/Bindings/iio/adc/amlogic,meson-saradc.txt
@@ -0,0 +1,32 @@
+* Amlogic Meson SAR (Successive Approximation Register) A/D converter
+
+Required properties:
+- compatible: depending on the SoC this should be one of:
+ - "amlogic,meson-gxbb-saradc" for GXBB
+ - "amlogic,meson-gxl-saradc" for GXL
+ - "amlogic,meson-gxm-saradc" for GXM
+ along with the generic "amlogic,meson-saradc"
+- reg: the physical base address and length of the registers
+- clocks: phandle and clock identifier (see clock-names)
+- clock-names: mandatory clocks:
+ - "clkin" for the reference clock (typically XTAL)
+ - "core" for the SAR ADC core clock
+ optional clocks:
+ - "sana" for the analog clock
+ - "adc_clk" for the ADC (sampling) clock
+ - "adc_sel" for the ADC (sampling) clock mux
+- vref-supply: the regulator supply for the ADC reference voltage
+- #io-channel-cells: must be 1, see ../iio-bindings.txt
+
+Example:
+ saradc: adc@8680 {
+ compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
+ #io-channel-cells = <1>;
+ reg = <0x0 0x8680 0x0 0x34>;
+ clocks = <&xtal>,
+ <&clkc CLKID_SAR_ADC>,
+ <&clkc CLKID_SANA>,
+ <&clkc CLKID_SAR_ADC_CLK>,
+ <&clkc CLKID_SAR_ADC_SEL>;
+ clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
+ };
diff --git a/Bindings/iio/adc/avia-hx711.txt b/Bindings/iio/adc/avia-hx711.txt
new file mode 100644
index 000000000000..b3629405f568
--- /dev/null
+++ b/Bindings/iio/adc/avia-hx711.txt
@@ -0,0 +1,18 @@
+* AVIA HX711 ADC chip for weight cells
+ Bit-banging driver
+
+Required properties:
+ - compatible: Should be "avia,hx711"
+ - sck-gpios: Definition of the GPIO for the clock
+ - dout-gpios: Definition of the GPIO for data-out
+ See Documentation/devicetree/bindings/gpio/gpio.txt
+ - avdd-supply: Definition of the regulator used as analog supply
+
+Example:
+weight@0 {
+ compatible = "avia,hx711";
+ sck-gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>;
+ dout-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
+ avdd-suppy = <&avdd>;
+};
+
diff --git a/Bindings/iio/adc/max11100.txt b/Bindings/iio/adc/max11100.txt
new file mode 100644
index 000000000000..b7f7177b8aca
--- /dev/null
+++ b/Bindings/iio/adc/max11100.txt
@@ -0,0 +1,18 @@
+* Maxim max11100 Analog to Digital Converter (ADC)
+
+Required properties:
+ - compatible: Should be "maxim,max11100"
+ - reg: the adc unit address
+ - vref-supply: phandle to the regulator that provides reference voltage
+
+Optional properties:
+ - spi-max-frequency: SPI maximum frequency
+
+Example:
+
+max11100: adc@0 {
+ compatible = "maxim,max11100";
+ reg = <0>;
+ vref-supply = <&adc0_vref>;
+ spi-max-frequency = <240000>;
+};
diff --git a/Bindings/iio/adc/qcom,pm8xxx-xoadc.txt b/Bindings/iio/adc/qcom,pm8xxx-xoadc.txt
new file mode 100644
index 000000000000..53cd146d8096
--- /dev/null
+++ b/Bindings/iio/adc/qcom,pm8xxx-xoadc.txt
@@ -0,0 +1,149 @@
+Qualcomm's PM8xxx voltage XOADC
+
+The Qualcomm PM8xxx PMICs contain a HK/XO ADC (Housekeeping/Crystal
+oscillator ADC) encompassing PM8018, PM8038, PM8058 and PM8921.
+
+Required properties:
+
+- compatible: should be one of:
+ "qcom,pm8018-adc"
+ "qcom,pm8038-adc"
+ "qcom,pm8058-adc"
+ "qcom,pm8921-adc"
+
+- reg: should contain the ADC base address in the PMIC, typically
+ 0x197.
+
+- xoadc-ref-supply: should reference a regulator that can supply
+ a reference voltage on demand. The reference voltage may vary
+ with PMIC variant but is typically something like 2.2 or 1.8V.
+
+The following required properties are standard for IO channels, see
+iio-bindings.txt for more details:
+
+- #address-cells: should be set to <1>
+
+- #size-cells: should be set to <0>
+
+- #io-channel-cells: should be set to <1>
+
+- interrupts: should refer to the parent PMIC interrupt controller
+ and reference the proper ADC interrupt.
+
+Required subnodes:
+
+The ADC channels are configured as subnodes of the ADC. Since some of
+them are used for calibrating the ADC, these nodes are compulsory:
+
+adc-channel@c {
+ reg = <0x0c>;
+};
+
+adc-channel@d {
+ reg = <0x0d>;
+};
+
+adc-channel@f {
+ reg = <0x0f>;
+};
+
+These three nodes are used for absolute and ratiometric calibration
+and only need to have these reg values: they are by hardware definition
+1:1 ratio converters that sample 625, 1250 and 0 milliV and create
+an interpolation calibration for all other ADCs.
+
+Optional subnodes: any channels other than channel 0x0c, 0x0d and
+0x0f are optional.
+
+Required channel node properties:
+
+- reg: should contain the hardware channel number in the range
+ 0 .. 0x0f (4 bits). The hardware only supports 16 channels.
+
+Optional channel node properties:
+
+- qcom,decimation:
+ Value type: <u32>
+ Definition: This parameter is used to decrease the ADC sampling rate.
+ Quicker measurements can be made by reducing the decimation ratio.
+ Valid values are 512, 1024, 2048, 4096.
+ If the property is not found, a default value of 512 will be used.
+
+- qcom,ratiometric:
+ Value type: <u32>
+ Definition: Channel calibration type. If this property is specified
+ VADC will use a special voltage references for channel
+ calibration. The available references are specified in the
+ as a u32 value setting (see below) and it is compulsory
+ to also specify this reference if ratiometric calibration
+ is selected.
+
+ If the property is not found, the channel will be
+ calibrated with the 0.625V and 1.25V reference channels, also
+ known as an absolute calibration.
+ The reference voltage pairs when using ratiometric calibration:
+ 0 = XO_IN/XOADC_GND
+ 1 = PMIC_IN/XOADC_GND
+ 2 = PMIC_IN/BMS_CSP
+ 3 (invalid)
+ 4 = XOADC_GND/XOADC_GND
+ 5 = XOADC_VREF/XOADC_GND
+
+Example:
+
+xoadc: xoadc@197 {
+ compatible = "qcom,pm8058-adc";
+ reg = <0x197>;
+ interrupt-parent = <&pm8058>;
+ interrupts = <76 1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+
+ vcoin: adc-channel@0 {
+ reg = <0x00>;
+ };
+ vbat: adc-channel@1 {
+ reg = <0x01>;
+ };
+ dcin: adc-channel@2 {
+ reg = <0x02>;
+ };
+ ichg: adc-channel@3 {
+ reg = <0x03>;
+ };
+ vph_pwr: adc-channel@4 {
+ reg = <0x04>;
+ };
+ usb_vbus: adc-channel@a {
+ reg = <0x0a>;
+ };
+ die_temp: adc-channel@b {
+ reg = <0x0b>;
+ };
+ ref_625mv: adc-channel@c {
+ reg = <0x0c>;
+ };
+ ref_1250mv: adc-channel@d {
+ reg = <0x0d>;
+ };
+ ref_325mv: adc-channel@e {
+ reg = <0x0e>;
+ };
+ ref_muxoff: adc-channel@f {
+ reg = <0x0f>;
+ };
+};
+
+
+/* IIO client node */
+iio-hwmon {
+ compatible = "iio-hwmon";
+ io-channels = <&xoadc 0x01>, /* Battery */
+ <&xoadc 0x02>, /* DC in (charger) */
+ <&xoadc 0x04>, /* VPH the main system voltage */
+ <&xoadc 0x0b>, /* Die temperature */
+ <&xoadc 0x0c>, /* Reference voltage 1.25V */
+ <&xoadc 0x0d>, /* Reference voltage 0.625V */
+ <&xoadc 0x0e>; /* Reference voltage 0.325V */
+};
diff --git a/Bindings/iio/adc/renesas,gyroadc.txt b/Bindings/iio/adc/renesas,gyroadc.txt
new file mode 100644
index 000000000000..f5b0adae6010
--- /dev/null
+++ b/Bindings/iio/adc/renesas,gyroadc.txt
@@ -0,0 +1,99 @@
+* Renesas RCar GyroADC device driver
+
+The GyroADC block is a reduced SPI block with up to 8 chipselect lines,
+which supports the SPI protocol of a selected few SPI ADCs. The SPI ADCs
+are sampled by the GyroADC block in a round-robin fashion and the result
+presented in the GyroADC registers.
+
+Required properties:
+- compatible: Should be "<soc-specific>", "renesas,rcar-gyroadc".
+ The <soc-specific> should be one of:
+ renesas,r8a7791-gyroadc - for the GyroADC block present
+ in r8a7791 SoC
+ renesas,r8a7792-gyroadc - for the GyroADC with interrupt
+ block present in r8a7792 SoC
+- reg: Address and length of the register set for the device
+- clocks: References to all the clocks specified in the clock-names
+ property as specified in
+ Documentation/devicetree/bindings/clock/clock-bindings.txt.
+- clock-names: Shall contain "fck" and "if". The "fck" is the GyroADC block
+ clock, the "if" is the interface clock.
+- power-domains: Must contain a reference to the PM domain, if available.
+- #address-cells: Should be <1> (setting for the subnodes) for all ADCs
+ except for "fujitsu,mb88101a". Should be <0> (setting for
+ only subnode) for "fujitsu,mb88101a".
+- #size-cells: Should be <0> (setting for the subnodes)
+
+Sub-nodes:
+You must define subnode(s) which select the connected ADC type and reference
+voltage for the GyroADC channels.
+
+Required properties for subnodes:
+- compatible: Should be either of:
+ "fujitsu,mb88101a"
+ - Fujitsu MB88101A compatible mode,
+ 12bit sampling, up to 4 channels can be sampled in
+ round-robin fashion. One Fujitsu chip supplies four
+ GyroADC channels with data as it contains four ADCs
+ on the chip and thus for 4-channel operation, single
+ MB88101A is required. The Cx chipselect lines of the
+ MB88101A connect directly to two CHS lines of the
+ GyroADC, no demuxer is required. The data out line
+ of each MB88101A connects to a shared input pin of
+ the GyroADC.
+ "ti,adcs7476" or "ti,adc121" or "adi,ad7476"
+ - TI ADCS7476 / TI ADC121 / ADI AD7476 compatible mode,
+ 15bit sampling, up to 8 channels can be sampled in
+ round-robin fashion. One TI/ADI chip supplies single
+ ADC channel with data, thus for 8-channel operation,
+ 8 chips are required. A 3:8 chipselect demuxer is
+ required to connect the nCS line of the TI/ADI chips
+ to the GyroADC, while MISO line of each TI/ADI ADC
+ connects to a shared input pin of the GyroADC.
+ "maxim,max1162" or "maxim,max11100"
+ - Maxim MAX1162 / Maxim MAX11100 compatible mode,
+ 16bit sampling, up to 8 channels can be sampled in
+ round-robin fashion. One Maxim chip supplies single
+ ADC channel with data, thus for 8-channel operation,
+ 8 chips are required. A 3:8 chipselect demuxer is
+ required to connect the nCS line of the MAX chips
+ to the GyroADC, while MISO line of each Maxim ADC
+ connects to a shared input pin of the GyroADC.
+- reg: Should be the number of the analog input. Should be present
+ for all ADCs except "fujitsu,mb88101a".
+- vref-supply: Reference to the channel reference voltage regulator.
+
+Example:
+ vref_max1162: regulator-vref-max1162 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "MAX1162 Vref";
+ regulator-min-microvolt = <4096000>;
+ regulator-max-microvolt = <4096000>;
+ };
+
+ adc@e6e54000 {
+ compatible = "renesas,r8a7791-gyroadc", "renesas,rcar-gyroadc";
+ reg = <0 0xe6e54000 0 64>;
+ clocks = <&mstp9_clks R8A7791_CLK_GYROADC>, <&clk_65m>;
+ clock-names = "fck", "if";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+
+ pinctrl-0 = <&adc_pins>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ reg = <0>;
+ compatible = "maxim,max1162";
+ vref-supply = <&vref_max1162>;
+ };
+
+ adc@1 {
+ reg = <1>;
+ compatible = "maxim,max1162";
+ vref-supply = <&vref_max1162>;
+ };
+ };
diff --git a/Bindings/iio/adc/st,stm32-adc.txt b/Bindings/iio/adc/st,stm32-adc.txt
index 49ed82e89870..5dfc88ec24a4 100644
--- a/Bindings/iio/adc/st,stm32-adc.txt
+++ b/Bindings/iio/adc/st,stm32-adc.txt
@@ -53,6 +53,11 @@ Required properties:
- #io-channel-cells = <1>: See the IIO bindings section "IIO consumers" in
Documentation/devicetree/bindings/iio/iio-bindings.txt
+Optional properties:
+- dmas: Phandle to dma channel for this ADC instance.
+ See ../../dma/dma.txt for details.
+- dma-names: Must be "rx" when dmas property is being used.
+
Example:
adc: adc@40012000 {
compatible = "st,stm32f4-adc-core";
@@ -77,6 +82,8 @@ Example:
interrupt-parent = <&adc>;
interrupts = <0>;
st,adc-channels = <8>;
+ dmas = <&dma2 0 0 0x400 0x0>;
+ dma-names = "rx";
};
...
other adc child nodes follow...
diff --git a/Bindings/iio/adc/ti-ads7950.txt b/Bindings/iio/adc/ti-ads7950.txt
new file mode 100644
index 000000000000..e77a6f7e1001
--- /dev/null
+++ b/Bindings/iio/adc/ti-ads7950.txt
@@ -0,0 +1,23 @@
+* Texas Instruments ADS7950 family of A/DC chips
+
+Required properties:
+ - compatible: Must be one of "ti,ads7950", "ti,ads7951", "ti,ads7952",
+ "ti,ads7953", "ti,ads7954", "ti,ads7955", "ti,ads7956", "ti,ads7957",
+ "ti,ads7958", "ti,ads7959", "ti,ads7960", or "ti,ads7961"
+ - reg: SPI chip select number for the device
+ - #io-channel-cells: Must be 1 as per ../iio-bindings.txt
+ - vref-supply: phandle to a regulator node that supplies the 2.5V or 5V
+ reference voltage
+
+Recommended properties:
+ - spi-max-frequency: Definition as per
+ Documentation/devicetree/bindings/spi/spi-bus.txt
+
+Example:
+adc@0 {
+ compatible = "ti,ads7957";
+ reg = <0>;
+ #io-channel-cells = <1>;
+ vref-supply = <&refin_supply>;
+ spi-max-frequency = <10000000>;
+};
diff --git a/Bindings/iio/imu/bmi160.txt b/Bindings/iio/imu/bmi160.txt
new file mode 100644
index 000000000000..ae0112c7debc
--- /dev/null
+++ b/Bindings/iio/imu/bmi160.txt
@@ -0,0 +1,36 @@
+Bosch BMI160 - Inertial Measurement Unit with Accelerometer, Gyroscope
+and externally connectable Magnetometer
+
+https://www.bosch-sensortec.com/bst/products/all_products/bmi160
+
+Required properties:
+ - compatible : should be "bosch,bmi160"
+ - reg : the I2C address or SPI chip select number of the sensor
+ - spi-max-frequency : set maximum clock frequency (only for SPI)
+
+Optional properties:
+ - interrupt-parent : should be the phandle of the interrupt controller
+ - interrupts : interrupt mapping for IRQ, must be IRQ_TYPE_LEVEL_LOW
+ - interrupt-names : set to "INT1" if INT1 pin should be used as interrupt
+ input, set to "INT2" if INT2 pin should be used instead
+
+Examples:
+
+bmi160@68 {
+ compatible = "bosch,bmi160";
+ reg = <0x68>;
+
+ interrupt-parent = <&gpio4>;
+ interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "INT1";
+};
+
+bmi160@0 {
+ compatible = "bosch,bmi160";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+
+ interrupt-parent = <&gpio2>;
+ interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "INT2";
+};
diff --git a/Bindings/iio/imu/st_lsm6dsx.txt b/Bindings/iio/imu/st_lsm6dsx.txt
new file mode 100644
index 000000000000..cf81afdf7803
--- /dev/null
+++ b/Bindings/iio/imu/st_lsm6dsx.txt
@@ -0,0 +1,26 @@
+* ST_LSM6DSx driver for STM 6-axis (acc + gyro) imu Mems sensors
+
+Required properties:
+- compatible: must be one of:
+ "st,lsm6ds3"
+ "st,lsm6dsm"
+- reg: i2c address of the sensor / spi cs line
+
+Optional properties:
+- st,drdy-int-pin: the pin on the package that will be used to signal
+ "data ready" (valid values: 1 or 2).
+- interrupt-parent: should be the phandle for the interrupt controller
+- interrupts: interrupt mapping for IRQ. It should be configured with
+ flags IRQ_TYPE_LEVEL_HIGH or IRQ_TYPE_EDGE_RISING.
+
+ Refer to interrupt-controller/interrupts.txt for generic interrupt
+ client node bindings.
+
+Example:
+
+lsm6dsm@6b {
+ compatible = "st,lsm6dsm";
+ reg = <0x6b>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <0 IRQ_TYPE_EDGE_RISING>;
+};
diff --git a/Bindings/iio/light/cm3605.txt b/Bindings/iio/light/cm3605.txt
new file mode 100644
index 000000000000..56331a79f9ab
--- /dev/null
+++ b/Bindings/iio/light/cm3605.txt
@@ -0,0 +1,41 @@
+Capella Microsystems CM3605
+Ambient Light and Short Distance Proximity Sensor
+
+The CM3605 is an entirely analog part which however require quite a bit of
+software logic to interface a host operating system.
+
+This ALS and proximity sensor was one of the very first deployed in mobile
+handsets, notably it is used in the very first Nexus One Android phone from
+2010.
+
+Required properties:
+- compatible: must be: "capella,cm3605"
+- aset-gpios: GPIO line controlling the ASET line (drive low
+ to activate the ALS, should be flagged GPIO_ACTIVE_LOW)
+- interrupts: the IRQ line (such as a GPIO) that is connected to
+ the POUT (proximity sensor out) line. The edge detection must
+ be set to IRQ_TYPE_EDGE_BOTH so as to detect movements toward
+ and away from the proximity sensor.
+- io-channels: the ADC channel used for converting the voltage from
+ AOUT to a digital representation.
+- io-channel-names: must be "aout"
+
+Optional properties:
+- vdd-supply: regulator supplying VDD power to the component.
+- capella,aset-resistance-ohms: the sensitivity calibration resistance,
+ in Ohms. Valid values are: 50000, 100000, 300000 and 600000,
+ as these are the resistance values that we are supplied with
+ calibration curves for. If not supplied, 100 kOhm will be assumed
+ but it is strongly recommended to supply this.
+
+Example:
+
+cm3605 {
+ compatible = "capella,cm3605";
+ vdd-supply = <&foo_reg>;
+ aset-gpios = <&foo_gpio 1 GPIO_ACTIVE_LOW>;
+ capella,aset-resistance-ohms = <100000>;
+ interrupts = <1 IRQ_TYPE_EDGE_BOTH>;
+ io-channels = <&adc 0x01>;
+ io-channel-names = "aout";
+};
diff --git a/Bindings/iio/potentiometer/max5481.txt b/Bindings/iio/potentiometer/max5481.txt
new file mode 100644
index 000000000000..6a91b106e076
--- /dev/null
+++ b/Bindings/iio/potentiometer/max5481.txt
@@ -0,0 +1,23 @@
+* Maxim Linear-Taper Digital Potentiometer MAX5481-MAX5484
+
+The node for this driver must be a child node of a SPI controller, hence
+all mandatory properties described in
+
+ Documentation/devicetree/bindings/spi/spi-bus.txt
+
+must be specified.
+
+Required properties:
+ - compatible: Must be one of the following, depending on the
+ model:
+ "maxim,max5481"
+ "maxim,max5482"
+ "maxim,max5483"
+ "maxim,max5484"
+
+Example:
+max548x: max548x@0 {
+ compatible = "maxim,max5482";
+ spi-max-frequency = <7000000>;
+ reg = <0>; /* chip-select */
+};
diff --git a/Bindings/iio/st-sensors.txt b/Bindings/iio/st-sensors.txt
index c040c9ad1889..eaa8fbba34e2 100644
--- a/Bindings/iio/st-sensors.txt
+++ b/Bindings/iio/st-sensors.txt
@@ -27,6 +27,8 @@ standard bindings from pinctrl/pinctrl-bindings.txt.
Valid compatible strings:
Accelerometers:
+- st,lis3lv02d (deprecated, use st,lis3lv02dl-accel)
+- st,lis302dl-spi (deprecated, use st,lis3lv02dl-accel)
- st,lis3lv02dl-accel
- st,lsm303dlh-accel
- st,lsm303dlhc-accel
diff --git a/Bindings/iio/temperature/tmp007.txt b/Bindings/iio/temperature/tmp007.txt
new file mode 100644
index 000000000000..b63aba91ef03
--- /dev/null
+++ b/Bindings/iio/temperature/tmp007.txt
@@ -0,0 +1,35 @@
+* TI TMP007 - IR thermopile sensor with integrated math engine
+
+Link to datasheet: http://www.ti.com/lit/ds/symlink/tmp007.pdf
+
+Required properties:
+
+ - compatible: should be "ti,tmp007"
+ - reg: the I2C address of the sensor (changeable via ADR pins)
+ ------------------------------
+ |ADR1 | ADR0 | Device Address|
+ ------------------------------
+ 0 0 0x40
+ 0 1 0x41
+ 0 SDA 0x42
+ 0 SCL 0x43
+ 1 0 0x44
+ 1 1 0x45
+ 1 SDA 0x46
+ 1 SCL 0x47
+
+Optional properties:
+
+ - interrupt-parent: should be the phandle for the interrupt controller
+
+ - interrupts: interrupt mapping for GPIO IRQ (level active low)
+
+Example:
+
+tmp007@40 {
+ compatible = "ti,tmp007";
+ reg = <0x40>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <5 0x08>;
+};
+
diff --git a/Bindings/iio/timer/stm32-timer-trigger.txt b/Bindings/iio/timer/stm32-timer-trigger.txt
new file mode 100644
index 000000000000..55a653d15303
--- /dev/null
+++ b/Bindings/iio/timer/stm32-timer-trigger.txt
@@ -0,0 +1,23 @@
+STMicroelectronics STM32 Timers IIO timer bindings
+
+Must be a sub-node of an STM32 Timers device tree node.
+See ../mfd/stm32-timers.txt for details about the parent node.
+
+Required parameters:
+- compatible: Must be "st,stm32-timer-trigger".
+- reg: Identify trigger hardware block.
+
+Example:
+ timers@40010000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40010000 0x400>;
+ clocks = <&rcc 0 160>;
+ clock-names = "clk_int";
+
+ timer@0 {
+ compatible = "st,stm32-timer-trigger";
+ reg = <0>;
+ };
+ };
diff --git a/Bindings/input/cypress,tm2-touchkey.txt b/Bindings/input/cypress,tm2-touchkey.txt
new file mode 100644
index 000000000000..635f62c756ee
--- /dev/null
+++ b/Bindings/input/cypress,tm2-touchkey.txt
@@ -0,0 +1,27 @@
+Samsung tm2-touchkey
+
+Required properties:
+- compatible: must be "cypress,tm2-touchkey"
+- reg: I2C address of the chip.
+- interrupt-parent: a phandle for the interrupt controller (see interrupt
+ binding[0]).
+- interrupts: interrupt to which the chip is connected (see interrupt
+ binding[0]).
+- vcc-supply : internal regulator output. 1.8V
+- vdd-supply : power supply for IC 3.3V
+
+[0]: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
+
+Example:
+ &i2c0 {
+ /* ... */
+
+ touchkey@20 {
+ compatible = "cypress,tm2-touchkey";
+ reg = <0x20>;
+ interrupt-parent = <&gpa3>;
+ interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
+ vcc-supply=<&ldo32_reg>;
+ vdd-supply=<&ldo33_reg>;
+ };
+ };
diff --git a/Bindings/input/mpr121-touchkey.txt b/Bindings/input/mpr121-touchkey.txt
new file mode 100644
index 000000000000..b7c61ee5841b
--- /dev/null
+++ b/Bindings/input/mpr121-touchkey.txt
@@ -0,0 +1,30 @@
+* Freescale MPR121 Controllor
+
+Required Properties:
+- compatible: Should be "fsl,mpr121-touchkey"
+- reg: The I2C slave address of the device.
+- interrupts: The interrupt number to the cpu.
+- vdd-supply: Phandle to the Vdd power supply.
+- linux,keycodes: Specifies an array of numeric keycode values to
+ be used for reporting button presses. The array can
+ contain up to 12 entries.
+
+Optional Properties:
+- wakeup-source: Use any event on keypad as wakeup event.
+- autorepeat: Enable autorepeat feature.
+
+Example:
+
+#include "dt-bindings/input/input.h"
+
+ touchkey: mpr121@5a {
+ compatible = "fsl,mpr121-touchkey";
+ reg = <0x5a>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <28 2>;
+ autorepeat;
+ vdd-supply = <&ldo4_reg>;
+ linux,keycodes = <KEY_0>, <KEY_1>, <KEY_2>, <KEY_3>,
+ <KEY_4> <KEY_5>, <KEY_6>, <KEY_7>,
+ <KEY_8>, <KEY_9>, <KEY_A>, <KEY_B>;
+ };
diff --git a/Bindings/input/pwm-beeper.txt b/Bindings/input/pwm-beeper.txt
index be332ae4f2d6..529408b4431a 100644
--- a/Bindings/input/pwm-beeper.txt
+++ b/Bindings/input/pwm-beeper.txt
@@ -5,3 +5,19 @@ Registers a PWM device as beeper.
Required properties:
- compatible: should be "pwm-beeper"
- pwms: phandle to the physical PWM device
+
+Optional properties:
+- amp-supply: phandle to a regulator that acts as an amplifier for the beeper
+
+Example:
+
+beeper_amp: amplifier {
+ compatible = "fixed-regulator";
+ gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
+};
+
+beeper {
+ compatible = "pwm-beeper";
+ pwms = <&pwm0>;
+ amp-supply = <&beeper_amp>;
+};
diff --git a/Bindings/input/touchscreen/focaltech-ft6236.txt b/Bindings/input/touchscreen/focaltech-ft6236.txt
deleted file mode 100644
index 777521da3da5..000000000000
--- a/Bindings/input/touchscreen/focaltech-ft6236.txt
+++ /dev/null
@@ -1,35 +0,0 @@
-* FocalTech FT6236 I2C touchscreen controller
-
-Required properties:
- - compatible : "focaltech,ft6236"
- - reg : I2C slave address of the chip (0x38)
- - interrupt-parent : a phandle pointing to the interrupt controller
- serving the interrupt for this chip
- - interrupts : interrupt specification for the touch controller
- interrupt
- - reset-gpios : GPIO specification for the RSTN input
- - touchscreen-size-x : horizontal resolution of touchscreen (in pixels)
- - touchscreen-size-y : vertical resolution of touchscreen (in pixels)
-
-Optional properties:
- - touchscreen-fuzz-x : horizontal noise value of the absolute input
- device (in pixels)
- - touchscreen-fuzz-y : vertical noise value of the absolute input
- device (in pixels)
- - touchscreen-inverted-x : X axis is inverted (boolean)
- - touchscreen-inverted-y : Y axis is inverted (boolean)
- - touchscreen-swapped-x-y: X and Y axis are swapped (boolean)
- Swapping is done after inverting the axis
-
-Example:
-
- ft6x06@38 {
- compatible = "focaltech,ft6236";
- reg = <0x38>;
- interrupt-parent = <&gpio>;
- interrupts = <23 2>;
- touchscreen-size-x = <320>;
- touchscreen-size-y = <480>;
- touchscreen-inverted-x;
- touchscreen-swapped-x-y;
- };
diff --git a/Bindings/input/touchscreen/zet6223.txt b/Bindings/input/touchscreen/zet6223.txt
new file mode 100644
index 000000000000..fe6a1feef703
--- /dev/null
+++ b/Bindings/input/touchscreen/zet6223.txt
@@ -0,0 +1,32 @@
+Zeitec ZET6223 I2C touchscreen controller
+
+Required properties:
+- compatible : "zeitec,zet6223"
+- reg : I2C slave address of the chip (0x76)
+- interrupt-parent : a phandle pointing to the interrupt controller
+ serving the interrupt for this chip
+- interrupts : interrupt specification for the zet6223 interrupt
+
+Optional properties:
+
+- vio-supply : Specification for VIO supply (1.8V or 3.3V,
+ depending on system interface needs).
+- vcc-supply : Specification for 3.3V VCC supply.
+- touchscreen-size-x : See touchscreen.txt
+- touchscreen-size-y : See touchscreen.txt
+- touchscreen-inverted-x : See touchscreen.txt
+- touchscreen-inverted-y : See touchscreen.txt
+- touchscreen-swapped-x-y : See touchscreen.txt
+
+Example:
+
+i2c@00000000 {
+
+ zet6223: touchscreen@76 {
+ compatible = "zeitec,zet6223";
+ reg = <0x76>;
+ interrupt-parent = <&pio>;
+ interrupts = <6 11 IRQ_TYPE_EDGE_FALLING>
+ };
+
+};
diff --git a/Bindings/interrupt-controller/arm,gic.txt b/Bindings/interrupt-controller/arm,gic.txt
index 5393e2a45a42..560d8a727b8f 100644
--- a/Bindings/interrupt-controller/arm,gic.txt
+++ b/Bindings/interrupt-controller/arm,gic.txt
@@ -111,7 +111,7 @@ Example:
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x2c001000 0x1000>,
- <0x2c002000 0x1000>,
+ <0x2c002000 0x2000>,
<0x2c004000 0x2000>,
<0x2c006000 0x2000>;
interrupts = <1 9 0xf04>;
diff --git a/Bindings/interrupt-controller/cortina,gemini-interrupt-controller.txt b/Bindings/interrupt-controller/cortina,gemini-interrupt-controller.txt
new file mode 100644
index 000000000000..97c1167fa533
--- /dev/null
+++ b/Bindings/interrupt-controller/cortina,gemini-interrupt-controller.txt
@@ -0,0 +1,22 @@
+* Cortina Systems Gemini interrupt controller
+
+This interrupt controller is found on the Gemini SoCs.
+
+Required properties:
+- compatible: must be "cortina,gemini-interrupt-controller"
+- reg: The register bank for the interrupt controller.
+- interrupt-controller: Identifies the node as an interrupt controller
+- #interrupt-cells: The number of cells to define the interrupts.
+ Must be 2 as the controller can specify level or rising edge
+ IRQs. The bindings follows the standard binding for controllers
+ with two cells specified in
+ interrupt-controller/interrupts.txt
+
+Example:
+
+interrupt-controller@48000000 {
+ compatible = "cortina,gemini-interrupt-controller";
+ reg = <0x48000000 0x1000>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+};
diff --git a/Bindings/interrupt-controller/snps,archs-idu-intc.txt b/Bindings/interrupt-controller/snps,archs-idu-intc.txt
index 944657684d73..8b46a34e05f1 100644
--- a/Bindings/interrupt-controller/snps,archs-idu-intc.txt
+++ b/Bindings/interrupt-controller/snps,archs-idu-intc.txt
@@ -8,15 +8,11 @@ Properties:
- compatible: "snps,archs-idu-intc"
- interrupt-controller: This is an interrupt controller.
- interrupt-parent: <reference to parent core intc>
-- #interrupt-cells: Must be <2>.
-- interrupts: <...> specifies the upstream core irqs
+- #interrupt-cells: Must be <1>.
- First cell specifies the "common" IRQ from peripheral to IDU
- Second cell specifies the irq distribution mode to cores
- 0=Round Robin; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
-
- The second cell in interrupts property is deprecated and may be ignored by
- the kernel.
+ Value of the cell specifies the "common" IRQ from peripheral to IDU. Number N
+ of the particular interrupt line of IDU corresponds to the line N+24 of the
+ core interrupt controller.
intc accessed via the special ARC AUX register interface, hence "reg" property
is not specified.
@@ -32,18 +28,10 @@ Example:
compatible = "snps,archs-idu-intc";
interrupt-controller;
interrupt-parent = <&core_intc>;
-
- /*
- * <hwirq distribution>
- * distribution: 0=RR; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3
- */
- #interrupt-cells = <2>;
-
- /* upstream core irqs: downstream these are "COMMON" irq 0,1.. */
- interrupts = <24 25 26 27 28 29 30 31>;
+ #interrupt-cells = <1>;
};
some_device: serial@c0fc1000 {
interrupt-parent = <&idu_intc>;
- interrupts = <0 0>; /* upstream idu IRQ #24, Round Robin */
+ interrupts = <0>; /* upstream idu IRQ #24 */
};
diff --git a/Bindings/iommu/arm,smmu.txt b/Bindings/iommu/arm,smmu.txt
index e862d1485205..6cdf32d037fc 100644
--- a/Bindings/iommu/arm,smmu.txt
+++ b/Bindings/iommu/arm,smmu.txt
@@ -36,15 +36,15 @@ conditions.
combined interrupt, it must be listed multiple times.
- #iommu-cells : See Documentation/devicetree/bindings/iommu/iommu.txt
- for details. With a value of 1, each "iommus" entry
+ for details. With a value of 1, each IOMMU specifier
represents a distinct stream ID emitted by that device
into the relevant SMMU.
SMMUs with stream matching support and complex masters
- may use a value of 2, where the second cell represents
- an SMR mask to combine with the ID in the first cell.
- Care must be taken to ensure the set of matched IDs
- does not result in conflicts.
+ may use a value of 2, where the second cell of the
+ IOMMU specifier represents an SMR mask to combine with
+ the ID in the first cell. Care must be taken to ensure
+ the set of matched IDs does not result in conflicts.
** System MMU optional properties:
diff --git a/Bindings/ipmi.txt b/Bindings/ipmi.txt
deleted file mode 100644
index d5f1a877ed3e..000000000000
--- a/Bindings/ipmi.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-IPMI device
-
-Required properties:
-- compatible: should be one of ipmi-kcs, ipmi-smic, or ipmi-bt
-- device_type: should be ipmi
-- reg: Address and length of the register set for the device
-
-Optional properties:
-- interrupts: The interrupt for the device. Without this the interface
- is polled.
-- reg-size - The size of the register. Defaults to 1
-- reg-spacing - The number of bytes between register starts. Defaults to 1
-- reg-shift - The amount to shift the registers to the right to get the data
- into bit zero.
-
-Example:
-
-smic@fff3a000 {
- compatible = "ipmi-smic";
- device_type = "ipmi";
- reg = <0xfff3a000 0x1000>;
- interrupts = <0 24 4>;
- reg-size = <4>;
- reg-spacing = <4>;
-};
diff --git a/Bindings/leds/common.txt b/Bindings/leds/common.txt
index 696be5792625..24b656014089 100644
--- a/Bindings/leds/common.txt
+++ b/Bindings/leds/common.txt
@@ -61,16 +61,24 @@ property can be omitted.
Examples:
-system-status {
- label = "Status";
- linux,default-trigger = "heartbeat";
- ...
+gpio-leds {
+ compatible = "gpio-leds";
+
+ system-status {
+ label = "Status";
+ linux,default-trigger = "heartbeat";
+ gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
+ };
};
-camera-flash {
- label = "Flash";
- led-sources = <0>, <1>;
- led-max-microamp = <50000>;
- flash-max-microamp = <320000>;
- flash-max-timeout-us = <500000>;
+max77693-led {
+ compatible = "maxim,max77693-led";
+
+ camera-flash {
+ label = "Flash";
+ led-sources = <0>, <1>;
+ led-max-microamp = <50000>;
+ flash-max-microamp = <320000>;
+ flash-max-timeout-us = <500000>;
+ };
};
diff --git a/Bindings/leds/irled/spi-ir-led.txt b/Bindings/leds/irled/spi-ir-led.txt
new file mode 100644
index 000000000000..896b6997cf30
--- /dev/null
+++ b/Bindings/leds/irled/spi-ir-led.txt
@@ -0,0 +1,29 @@
+Device tree bindings for IR LED connected through SPI bus which is used as
+remote controller.
+
+The IR LED switch is connected to the MOSI line of the SPI device and the data
+are delivered thourgh that.
+
+Required properties:
+ - compatible: should be "ir-spi-led".
+
+Optional properties:
+ - duty-cycle: 8 bit balue that represents the percentage of one period
+ in which the signal is active. It can be 50, 60, 70, 75, 80 or 90.
+ - led-active-low: boolean value that specifies whether the output is
+ negated with a NOT gate.
+ - power-supply: specifies the power source. It can either be a regulator
+ or a gpio which enables a regulator, i.e. a regulator-fixed as
+ described in
+ Documentation/devicetree/bindings/regulator/fixed-regulator.txt
+
+Example:
+
+ irled@0 {
+ compatible = "ir-spi-led";
+ reg = <0x0>;
+ spi-max-frequency = <5000000>;
+ power-supply = <&vdd_led>;
+ led-active-low;
+ duty-cycle = /bits/ 8 <60>;
+ };
diff --git a/Bindings/media/fsl-vdoa.txt b/Bindings/media/fsl-vdoa.txt
new file mode 100644
index 000000000000..6c5628530bb7
--- /dev/null
+++ b/Bindings/media/fsl-vdoa.txt
@@ -0,0 +1,21 @@
+Freescale Video Data Order Adapter
+==================================
+
+The Video Data Order Adapter (VDOA) is present on the i.MX6q. Its sole purpose
+is to reorder video data from the macroblock tiled order produced by the CODA
+960 VPU to the conventional raster-scan order for scanout.
+
+Required properties:
+- compatible: must be "fsl,imx6q-vdoa"
+- reg: the register base and size for the device registers
+- interrupts: the VDOA interrupt
+- clocks: the vdoa clock
+
+Example:
+
+vdoa@21e4000 {
+ compatible = "fsl,imx6q-vdoa";
+ reg = <0x021e4000 0x4000>;
+ interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_VDOA>;
+};
diff --git a/Bindings/media/gpio-ir-receiver.txt b/Bindings/media/gpio-ir-receiver.txt
index 56e726ef4bf2..58261fb7b408 100644
--- a/Bindings/media/gpio-ir-receiver.txt
+++ b/Bindings/media/gpio-ir-receiver.txt
@@ -5,7 +5,8 @@ Required properties:
- gpios: specifies GPIO used for IR signal reception.
Optional properties:
- - linux,rc-map-name: Linux specific remote control map name.
+ - linux,rc-map-name: see rc.txt file in the same
+ directory.
Example node:
diff --git a/Bindings/media/hix5hd2-ir.txt b/Bindings/media/hix5hd2-ir.txt
index 54e1bede6244..13ebc0fac9ea 100644
--- a/Bindings/media/hix5hd2-ir.txt
+++ b/Bindings/media/hix5hd2-ir.txt
@@ -10,7 +10,7 @@ Required properties:
- clocks: clock phandle and specifier pair.
Optional properties:
- - linux,rc-map-name : Remote control map name.
+ - linux,rc-map-name: see rc.txt file in the same directory.
- hisilicon,power-syscon: DEPRECATED. Don't use this in new dts files.
Provide correct clocks instead.
diff --git a/Bindings/media/i2c/toshiba,et8ek8.txt b/Bindings/media/i2c/toshiba,et8ek8.txt
new file mode 100644
index 000000000000..0b7b6a4d84ff
--- /dev/null
+++ b/Bindings/media/i2c/toshiba,et8ek8.txt
@@ -0,0 +1,48 @@
+Toshiba et8ek8 5MP sensor
+
+Toshiba et8ek8 5MP sensor is an image sensor found in Nokia N900 device
+
+More detailed documentation can be found in
+Documentation/devicetree/bindings/media/video-interfaces.txt .
+
+
+Mandatory properties
+--------------------
+
+- compatible: "toshiba,et8ek8"
+- reg: I2C address (0x3e, or an alternative address)
+- vana-supply: Analogue voltage supply (VANA), 2.8 volts
+- clocks: External clock to the sensor
+- clock-frequency: Frequency of the external clock to the sensor. Camera
+ driver will set this frequency on the external clock. The clock frequency is
+ a pre-determined frequency known to be suitable to the board.
+- reset-gpios: XSHUTDOWN GPIO. The XSHUTDOWN signal is active low. The sensor
+ is in hardware standby mode when the signal is in the low state.
+
+
+Endpoint node mandatory properties
+----------------------------------
+
+- remote-endpoint: A phandle to the bus receiver's endpoint node.
+
+
+Example
+-------
+
+&i2c3 {
+ clock-frequency = <400000>;
+
+ cam1: camera@3e {
+ compatible = "toshiba,et8ek8";
+ reg = <0x3e>;
+ vana-supply = <&vaux4>;
+ clocks = <&isp 0>;
+ clock-frequency = <9600000>;
+ reset-gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* 102 */
+ port {
+ csi_cam1: endpoint {
+ remote-endpoint = <&csi_out1>;
+ };
+ };
+ };
+};
diff --git a/Bindings/media/meson-ir.txt b/Bindings/media/meson-ir.txt
index e7e3f3c4fc8f..efd9d29a8f10 100644
--- a/Bindings/media/meson-ir.txt
+++ b/Bindings/media/meson-ir.txt
@@ -8,6 +8,9 @@ Required properties:
- reg : physical base address and length of the device registers
- interrupts : a single specifier for the interrupt from the device
+Optional properties:
+ - linux,rc-map-name: see rc.txt file in the same directory.
+
Example:
ir-receiver@c8100480 {
diff --git a/Bindings/media/mtk-cir.txt b/Bindings/media/mtk-cir.txt
new file mode 100644
index 000000000000..2be2005577d6
--- /dev/null
+++ b/Bindings/media/mtk-cir.txt
@@ -0,0 +1,24 @@
+Device-Tree bindings for Mediatek consumer IR controller
+found in Mediatek SoC family
+
+Required properties:
+- compatible : "mediatek,mt7623-cir"
+- clocks : list of clock specifiers, corresponding to
+ entries in clock-names property;
+- clock-names : should contain "clk" entries;
+- interrupts : should contain IR IRQ number;
+- reg : should contain IO map address for IR.
+
+Optional properties:
+- linux,rc-map-name : see rc.txt file in the same directory.
+
+Example:
+
+cir: cir@10013000 {
+ compatible = "mediatek,mt7623-cir";
+ reg = <0 0x10013000 0 0x1000>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_INFRA_IRRX>;
+ clock-names = "clk";
+ linux,rc-map-name = "rc-rc6-mce";
+};
diff --git a/Bindings/media/rc.txt b/Bindings/media/rc.txt
new file mode 100644
index 000000000000..d3e7a012bfda
--- /dev/null
+++ b/Bindings/media/rc.txt
@@ -0,0 +1,117 @@
+The following properties are common to the infrared remote controllers:
+
+- linux,rc-map-name: string, specifies the scancode/key mapping table
+ defined in-kernel for the remote controller. Support values are:
+ * "rc-adstech-dvb-t-pci"
+ * "rc-alink-dtu-m"
+ * "rc-anysee"
+ * "rc-apac-viewcomp"
+ * "rc-asus-pc39"
+ * "rc-asus-ps3-100"
+ * "rc-ati-tv-wonder-hd-600"
+ * "rc-ati-x10"
+ * "rc-avermedia-a16d"
+ * "rc-avermedia-cardbus"
+ * "rc-avermedia-dvbt"
+ * "rc-avermedia-m135a"
+ * "rc-avermedia-m733a-rm-k6"
+ * "rc-avermedia-rm-ks"
+ * "rc-avermedia"
+ * "rc-avertv-303"
+ * "rc-azurewave-ad-tu700"
+ * "rc-behold-columbus"
+ * "rc-behold"
+ * "rc-budget-ci-old"
+ * "rc-cec"
+ * "rc-cinergy-1400"
+ * "rc-cinergy"
+ * "rc-delock-61959"
+ * "rc-dib0700-nec"
+ * "rc-dib0700-rc5"
+ * "rc-digitalnow-tinytwin"
+ * "rc-digittrade"
+ * "rc-dm1105-nec"
+ * "rc-dntv-live-dvbt-pro"
+ * "rc-dntv-live-dvb-t"
+ * "rc-dtt200u"
+ * "rc-dvbsky"
+ * "rc-empty"
+ * "rc-em-terratec"
+ * "rc-encore-enltv2"
+ * "rc-encore-enltv-fm53"
+ * "rc-encore-enltv"
+ * "rc-evga-indtube"
+ * "rc-eztv"
+ * "rc-flydvb"
+ * "rc-flyvideo"
+ * "rc-fusionhdtv-mce"
+ * "rc-gadmei-rm008z"
+ * "rc-geekbox"
+ * "rc-genius-tvgo-a11mce"
+ * "rc-gotview7135"
+ * "rc-hauppauge"
+ * "rc-imon-mce"
+ * "rc-imon-pad"
+ * "rc-iodata-bctv7e"
+ * "rc-it913x-v1"
+ * "rc-it913x-v2"
+ * "rc-kaiomy"
+ * "rc-kworld-315u"
+ * "rc-kworld-pc150u"
+ * "rc-kworld-plus-tv-analog"
+ * "rc-leadtek-y04g0051"
+ * "rc-lirc"
+ * "rc-lme2510"
+ * "rc-manli"
+ * "rc-medion-x10"
+ * "rc-medion-x10-digitainer"
+ * "rc-medion-x10-or2x"
+ * "rc-msi-digivox-ii"
+ * "rc-msi-digivox-iii"
+ * "rc-msi-tvanywhere-plus"
+ * "rc-msi-tvanywhere"
+ * "rc-nebula"
+ * "rc-nec-terratec-cinergy-xs"
+ * "rc-norwood"
+ * "rc-npgtech"
+ * "rc-pctv-sedna"
+ * "rc-pinnacle-color"
+ * "rc-pinnacle-grey"
+ * "rc-pinnacle-pctv-hd"
+ * "rc-pixelview-new"
+ * "rc-pixelview"
+ * "rc-pixelview-002t"
+ * "rc-pixelview-mk12"
+ * "rc-powercolor-real-angel"
+ * "rc-proteus-2309"
+ * "rc-purpletv"
+ * "rc-pv951"
+ * "rc-hauppauge"
+ * "rc-rc5-tv"
+ * "rc-rc6-mce"
+ * "rc-real-audio-220-32-keys"
+ * "rc-reddo"
+ * "rc-snapstream-firefly"
+ * "rc-streamzap"
+ * "rc-tbs-nec"
+ * "rc-technisat-ts35"
+ * "rc-technisat-usb2"
+ * "rc-terratec-cinergy-c-pci"
+ * "rc-terratec-cinergy-s2-hd"
+ * "rc-terratec-cinergy-xs"
+ * "rc-terratec-slim"
+ * "rc-terratec-slim-2"
+ * "rc-tevii-nec"
+ * "rc-tivo"
+ * "rc-total-media-in-hand"
+ * "rc-total-media-in-hand-02"
+ * "rc-trekstor"
+ * "rc-tt-1500"
+ * "rc-twinhan-dtv-cab-ci"
+ * "rc-twinhan1027"
+ * "rc-videomate-k100"
+ * "rc-videomate-s350"
+ * "rc-videomate-tv-pvr"
+ * "rc-winfast"
+ * "rc-winfast-usbii-deluxe"
+ * "rc-su3000"
diff --git a/Bindings/media/st,st-delta.txt b/Bindings/media/st,st-delta.txt
new file mode 100644
index 000000000000..a538ab30a617
--- /dev/null
+++ b/Bindings/media/st,st-delta.txt
@@ -0,0 +1,17 @@
+* STMicroelectronics DELTA multi-format video decoder
+
+Required properties:
+- compatible: should be "st,st-delta".
+- clocks: from common clock binding: handle hardware IP needed clocks, the
+ number of clocks may depend on the SoC type.
+ See ../clock/clock-bindings.txt for details.
+- clock-names: names of the clocks listed in clocks property in the same order.
+
+Example:
+ delta0 {
+ compatible = "st,st-delta";
+ clock-names = "delta", "delta-st231", "delta-flash-promip";
+ clocks = <&clk_s_c0_flexgen CLK_VID_DMU>,
+ <&clk_s_c0_flexgen CLK_ST231_DMU>,
+ <&clk_s_c0_flexgen CLK_FLASH_PROMIP>;
+ };
diff --git a/Bindings/media/sunxi-ir.txt b/Bindings/media/sunxi-ir.txt
index 1811a067c72c..302a0b183cb8 100644
--- a/Bindings/media/sunxi-ir.txt
+++ b/Bindings/media/sunxi-ir.txt
@@ -9,7 +9,7 @@ Required properties:
- reg : should contain IO map address for IR.
Optional properties:
-- linux,rc-map-name : Remote control map name.
+- linux,rc-map-name: see rc.txt file in the same directory.
- resets : phandle + reset specifier pair
Example:
diff --git a/Bindings/media/ti,da850-vpif.txt b/Bindings/media/ti,da850-vpif.txt
new file mode 100644
index 000000000000..6d25d7f23d26
--- /dev/null
+++ b/Bindings/media/ti,da850-vpif.txt
@@ -0,0 +1,83 @@
+Texas Instruments VPIF
+----------------------
+
+The TI Video Port InterFace (VPIF) is the primary component for video
+capture and display on the DA850/AM18x family of TI DaVinci/Sitara
+SoCs.
+
+TI Document reference: SPRUH82C, Chapter 35
+http://www.ti.com/lit/pdf/spruh82
+
+Required properties:
+- compatible: must be "ti,da850-vpif"
+- reg: physical base address and length of the registers set for the device;
+- interrupts: should contain IRQ line for the VPIF
+
+Video Capture:
+
+VPIF has a 16-bit parallel bus input, supporting 2 8-bit channels or a
+single 16-bit channel. It should contain at least one port child node
+with child 'endpoint' node. Please refer to the bindings defined in
+Documentation/devicetree/bindings/media/video-interfaces.txt.
+
+Example using 2 8-bit input channels, one of which is connected to an
+I2C-connected TVP5147 decoder:
+
+ vpif: vpif@217000 {
+ compatible = "ti,da850-vpif";
+ reg = <0x217000 0x1000>;
+ interrupts = <92>;
+
+ port {
+ vpif_ch0: endpoint@0 {
+ reg = <0>;
+ bus-width = <8>;
+ remote-endpoint = <&composite>;
+ };
+
+ vpif_ch1: endpoint@1 {
+ reg = <1>;
+ bus-width = <8>;
+ data-shift = <8>;
+ };
+ };
+ };
+
+[ ... ]
+
+&i2c0 {
+
+ tvp5147@5d {
+ compatible = "ti,tvp5147";
+ reg = <0x5d>;
+ status = "okay";
+
+ port {
+ composite: endpoint {
+ hsync-active = <1>;
+ vsync-active = <1>;
+ pclk-sample = <0>;
+
+ /* VPIF channel 0 (lower 8-bits) */
+ remote-endpoint = <&vpif_ch0>;
+ bus-width = <8>;
+ };
+ };
+ };
+};
+
+
+Alternatively, an example when the bus is configured as a single
+16-bit input (e.g. for raw-capture mode):
+
+ vpif: vpif@217000 {
+ compatible = "ti,da850-vpif";
+ reg = <0x217000 0x1000>;
+ interrupts = <92>;
+
+ port {
+ vpif_ch0: endpoint {
+ bus-width = <16>;
+ };
+ };
+ };
diff --git a/Bindings/mfd/as3722.txt b/Bindings/mfd/as3722.txt
index 4f64b2a73169..0b2a6099aa20 100644
--- a/Bindings/mfd/as3722.txt
+++ b/Bindings/mfd/as3722.txt
@@ -122,8 +122,7 @@ Following are properties of regulator subnode.
Power-off:
=========
-AS3722 supports the system power off by turning off all its rail. This
-is provided through pm_power_off.
+AS3722 supports the system power off by turning off all its rails.
The device node should have the following properties to enable this
functionality
ams,system-power-controller: Boolean, to enable the power off functionality
diff --git a/Bindings/mfd/aspeed-gfx.txt b/Bindings/mfd/aspeed-gfx.txt
new file mode 100644
index 000000000000..aea5370efd97
--- /dev/null
+++ b/Bindings/mfd/aspeed-gfx.txt
@@ -0,0 +1,17 @@
+* Device tree bindings for Aspeed SoC Display Controller (GFX)
+
+The Aspeed SoC Display Controller primarily does as its name suggests, but also
+participates in pinmux requests on the g5 SoCs. It is therefore considered a
+syscon device.
+
+Required properties:
+- compatible: "aspeed,ast2500-gfx", "syscon"
+- reg: contains offset/length value of the GFX memory
+ region.
+
+Example:
+
+gfx: display@1e6e6000 {
+ compatible = "aspeed,ast2500-gfx", "syscon";
+ reg = <0x1e6e6000 0x1000>;
+};
diff --git a/Bindings/mfd/aspeed-lpc.txt b/Bindings/mfd/aspeed-lpc.txt
new file mode 100644
index 000000000000..514d82ced95b
--- /dev/null
+++ b/Bindings/mfd/aspeed-lpc.txt
@@ -0,0 +1,137 @@
+======================================================================
+Device tree bindings for the Aspeed Low Pin Count (LPC) Bus Controller
+======================================================================
+
+The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
+peripheral devices, replacing the use of the ISA bus in the age of PCI[0]. The
+primary use case of the Aspeed LPC controller is as a slave on the bus
+(typically in a Baseboard Management Controller SoC), but under certain
+conditions it can also take the role of bus master.
+
+The LPC controller is represented as a multi-function device to account for the
+mix of functionality it provides. The principle split is between the register
+layout at the start of the I/O space which is, to quote the Aspeed datasheet,
+"basically compatible with the [LPC registers from the] popular BMC controller
+H8S/2168[1]", and everything else, where everything else is an eclectic
+collection of functions with a esoteric register layout. "Everything else",
+here labeled the "host" portion of the controller, includes, but is not limited
+to:
+
+* An IPMI Block Transfer[2] Controller
+
+* An LPC Host Controller: Manages LPC functions such as host vs slave mode, the
+ physical properties of some LPC pins, configuration of serial IRQs, and
+ APB-to-LPC bridging amonst other functions.
+
+* An LPC Host Interface Controller: Manages functions exposed to the host such
+ as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
+ management and bus snoop configuration.
+
+* A set of SuperIO[3] scratch registers: Enables implementation of e.g. custom
+ hardware management protocols for handover between the host and baseboard
+ management controller.
+
+Additionally the state of the LPC controller influences the pinmux
+configuration, therefore the host portion of the controller is exposed as a
+syscon as a means to arbitrate access.
+
+[0] http://www.intel.com/design/chipsets/industry/25128901.pdf
+[1] https://www.renesas.com/en-sg/doc/products/mpumcu/001/rej09b0078_h8s2168.pdf?key=7c88837454702128622bee53acbda8f4
+[2] http://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/ipmi-second-gen-interface-spec-v2-rev1-1.pdf
+[3] https://en.wikipedia.org/wiki/Super_I/O
+
+Required properties
+===================
+
+- compatible: One of:
+ "aspeed,ast2400-lpc", "simple-mfd"
+ "aspeed,ast2500-lpc", "simple-mfd"
+
+- reg: contains the physical address and length values of the Aspeed
+ LPC memory region.
+
+- #address-cells: <1>
+- #size-cells: <1>
+- ranges: Maps 0 to the physical address and length of the LPC memory
+ region
+
+Required LPC Child nodes
+========================
+
+BMC Node
+--------
+
+- compatible: One of:
+ "aspeed,ast2400-lpc-bmc"
+ "aspeed,ast2500-lpc-bmc"
+
+- reg: contains the physical address and length values of the
+ H8S/2168-compatible LPC controller memory region
+
+Host Node
+---------
+
+- compatible: One of:
+ "aspeed,ast2400-lpc-host", "simple-mfd", "syscon"
+ "aspeed,ast2500-lpc-host", "simple-mfd", "syscon"
+
+- reg: contains the address and length values of the host-related
+ register space for the Aspeed LPC controller
+
+- #address-cells: <1>
+- #size-cells: <1>
+- ranges: Maps 0 to the address and length of the host-related LPC memory
+ region
+
+Example:
+
+lpc: lpc@1e789000 {
+ compatible = "aspeed,ast2500-lpc", "simple-mfd";
+ reg = <0x1e789000 0x1000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x1e789000 0x1000>;
+
+ lpc_bmc: lpc-bmc@0 {
+ compatible = "aspeed,ast2500-lpc-bmc";
+ reg = <0x0 0x80>;
+ };
+
+ lpc_host: lpc-host@80 {
+ compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
+ reg = <0x80 0x1e0>;
+ reg-io-width = <4>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x80 0x1e0>;
+ };
+};
+
+Host Node Children
+==================
+
+LPC Host Controller
+-------------------
+
+The Aspeed LPC Host Controller configures the Low Pin Count (LPC) bus behaviour
+between the host and the baseboard management controller. The registers exist
+in the "host" portion of the Aspeed LPC controller, which must be the parent of
+the LPC host controller node.
+
+Required properties:
+
+- compatible: One of:
+ "aspeed,ast2400-lhc";
+ "aspeed,ast2500-lhc";
+
+- reg: contains offset/length values of the LHC memory regions. In the
+ AST2400 and AST2500 there are two regions.
+
+Example:
+
+lhc: lhc@20 {
+ compatible = "aspeed,ast2500-lhc";
+ reg = <0x20 0x24 0x48 0x8>;
+};
diff --git a/Bindings/mfd/mfd.txt b/Bindings/mfd/mfd.txt
index af9d6931a1a2..bcb6abb9d413 100644
--- a/Bindings/mfd/mfd.txt
+++ b/Bindings/mfd/mfd.txt
@@ -19,12 +19,22 @@ Optional properties:
- compatible : "simple-mfd" - this signifies that the operating system should
consider all subnodes of the MFD device as separate devices akin to how
- "simple-bus" inidicates when to see subnodes as children for a simple
+ "simple-bus" indicates when to see subnodes as children for a simple
memory-mapped bus. For more complex devices, when the nexus driver has to
probe registers to figure out what child devices exist etc, this should not
be used. In the latter case the child devices will be determined by the
operating system.
+- ranges: Describes the address mapping relationship to the parent. Should set
+ the child's base address to 0, the physical address within parent's address
+ space, and the length of the address map.
+
+- #address-cells: Specifies the number of cells used to represent physical base
+ addresses. Must be present if ranges is used.
+
+- #size-cells: Specifies the number of cells used to represent the size of an
+ address. Must be present if ranges is used.
+
Example:
foo@1000 {
diff --git a/Bindings/mfd/motorola-cpcap.txt b/Bindings/mfd/motorola-cpcap.txt
new file mode 100644
index 000000000000..15bc885f9df4
--- /dev/null
+++ b/Bindings/mfd/motorola-cpcap.txt
@@ -0,0 +1,31 @@
+Motorola CPCAP PMIC device tree binding
+
+Required properties:
+- compatible : One or both of "motorola,cpcap" or "ste,6556002"
+- reg : SPI chip select
+- interrupt-parent : The parent interrupt controller
+- interrupts : The interrupt line the device is connected to
+- interrupt-controller : Marks the device node as an interrupt controller
+- #interrupt-cells : The number of cells to describe an IRQ, should be 2
+- #address-cells : Child device offset number of cells, should be 1
+- #size-cells : Child device size number of cells, should be 0
+- spi-max-frequency : Typically set to 3000000
+- spi-cs-high : SPI chip select direction
+
+Example:
+
+&mcspi1 {
+ cpcap: pmic@0 {
+ compatible = "motorola,cpcap", "ste,6556002";
+ reg = <0>; /* cs0 */
+ interrupt-parent = <&gpio1>;
+ interrupts = <7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ spi-max-frequency = <3000000>;
+ spi-cs-high;
+ };
+};
+
diff --git a/Bindings/mfd/mt6397.txt b/Bindings/mfd/mt6397.txt
index 949c85f8d02c..c568d52af5af 100644
--- a/Bindings/mfd/mt6397.txt
+++ b/Bindings/mfd/mt6397.txt
@@ -34,6 +34,10 @@ Optional subnodes:
- clk
Required properties:
- compatible: "mediatek,mt6397-clk"
+- led
+ Required properties:
+ - compatible: "mediatek,mt6323-led"
+ see Documentation/devicetree/bindings/leds/leds-mt6323.txt
Example:
pwrap: pwrap@1000f000 {
diff --git a/Bindings/mfd/omap-usb-host.txt b/Bindings/mfd/omap-usb-host.txt
index 4721b2d521e4..aa1eaa59581b 100644
--- a/Bindings/mfd/omap-usb-host.txt
+++ b/Bindings/mfd/omap-usb-host.txt
@@ -64,8 +64,8 @@ Required properties if child node exists:
Properties for children:
The OMAP HS USB Host subsystem contains EHCI and OHCI controllers.
-See Documentation/devicetree/bindings/usb/omap-ehci.txt and
-omap3-ohci.txt
+See Documentation/devicetree/bindings/usb/ehci-omap.txt and
+Documentation/devicetree/bindings/usb/ohci-omap3.txt.
Example for OMAP4:
diff --git a/Bindings/mfd/qcom-rpm.txt b/Bindings/mfd/qcom-rpm.txt
index 485bc59fcc48..3c91ad430eea 100644
--- a/Bindings/mfd/qcom-rpm.txt
+++ b/Bindings/mfd/qcom-rpm.txt
@@ -234,7 +234,7 @@ see regulator.txt - with additional custom properties described below:
- qcom,switch-mode-frequency:
Usage: required
Value type: <u32>
- Definition: Frequency (Hz) of the swith mode power supply;
+ Definition: Frequency (Hz) of the switch mode power supply;
must be one of:
19200000, 9600000, 6400000, 4800000, 3840000, 3200000,
2740000, 2400000, 2130000, 1920000, 1750000, 1600000,
diff --git a/Bindings/mfd/stm32-timers.txt b/Bindings/mfd/stm32-timers.txt
new file mode 100644
index 000000000000..bbd083f5600a
--- /dev/null
+++ b/Bindings/mfd/stm32-timers.txt
@@ -0,0 +1,46 @@
+STM32 Timers driver bindings
+
+This IP provides 3 types of timer along with PWM functionality:
+- advanced-control timers consist of a 16-bit auto-reload counter driven by a programmable
+ prescaler, break input feature, PWM outputs and complementary PWM ouputs channels.
+- general-purpose timers consist of a 16-bit or 32-bit auto-reload counter driven by a
+ programmable prescaler and PWM outputs.
+- basic timers consist of a 16-bit auto-reload counter driven by a programmable prescaler.
+
+Required parameters:
+- compatible: must be "st,stm32-timers"
+
+- reg: Physical base address and length of the controller's
+ registers.
+- clock-names: Set to "int".
+- clocks: Phandle to the clock used by the timer module.
+ For Clk properties, please refer to ../clock/clock-bindings.txt
+
+Optional parameters:
+- resets: Phandle to the parent reset controller.
+ See ../reset/st,stm32-rcc.txt
+
+Optional subnodes:
+- pwm: See ../pwm/pwm-stm32.txt
+- timer: See ../iio/timer/stm32-timer-trigger.txt
+
+Example:
+ timers@40010000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40010000 0x400>;
+ clocks = <&rcc 0 160>;
+ clock-names = "clk_int";
+
+ pwm {
+ compatible = "st,stm32-pwm";
+ pinctrl-0 = <&pwm1_pins>;
+ pinctrl-names = "default";
+ };
+
+ timer@0 {
+ compatible = "st,stm32-timer-trigger";
+ reg = <0>;
+ };
+ };
diff --git a/Bindings/mips/img/pistachio-marduk.txt b/Bindings/mips/img/pistachio-marduk.txt
new file mode 100644
index 000000000000..2d5126d529a2
--- /dev/null
+++ b/Bindings/mips/img/pistachio-marduk.txt
@@ -0,0 +1,10 @@
+Imagination Technologies' Pistachio SoC based Marduk Board
+==========================================================
+
+Compatible string must be "img,pistachio-marduk", "img,pistachio"
+
+Hardware and other related documentation is available at
+https://docs.creatordev.io/ci40/
+
+It is also known as Creator Ci40. Marduk is legacy name and will
+be there for decades.
diff --git a/Bindings/misc/atmel-ssc.txt b/Bindings/misc/atmel-ssc.txt
index efc98ea1f23d..f8629bb73945 100644
--- a/Bindings/misc/atmel-ssc.txt
+++ b/Bindings/misc/atmel-ssc.txt
@@ -24,6 +24,8 @@ Optional properties:
this parameter to choose where the clock from.
- By default the clock is from TK pin, if the clock from RK pin, this
property is needed.
+ - #sound-dai-cells: Should contain <0>.
+ - This property makes the SSC into an automatically registered DAI.
Examples:
- PDC transfer:
diff --git a/Bindings/misc/idt_89hpesx.txt b/Bindings/misc/idt_89hpesx.txt
new file mode 100644
index 000000000000..b9093b79ab7d
--- /dev/null
+++ b/Bindings/misc/idt_89hpesx.txt
@@ -0,0 +1,44 @@
+EEPROM / CSR SMBus-slave interface of IDT 89HPESx devices
+
+Required properties:
+ - compatible : should be "<manufacturer>,<type>"
+ Basically there is only one manufacturer: idt, but some
+ compatible devices may be produced in future. Following devices
+ are supported: 89hpes8nt2, 89hpes12nt3, 89hpes24nt6ag2,
+ 89hpes32nt8ag2, 89hpes32nt8bg2, 89hpes12nt12g2, 89hpes16nt16g2,
+ 89hpes24nt24g2, 89hpes32nt24ag2, 89hpes32nt24bg2;
+ 89hpes12n3, 89hpes12n3a, 89hpes24n3, 89hpes24n3a;
+ 89hpes32h8, 89hpes32h8g2, 89hpes48h12, 89hpes48h12g2,
+ 89hpes48h12ag2, 89hpes16h16, 89hpes22h16, 89hpes22h16g2,
+ 89hpes34h16, 89hpes34h16g2, 89hpes64h16, 89hpes64h16g2,
+ 89hpes64h16ag2;
+ 89hpes12t3g2, 89hpes24t3g2, 89hpes16t4, 89hpes4t4g2,
+ 89hpes10t4g2, 89hpes16t4g2, 89hpes16t4ag2, 89hpes5t5,
+ 89hpes6t5, 89hpes8t5, 89hpes8t5a, 89hpes24t6, 89hpes6t6g2,
+ 89hpes24t6g2, 89hpes16t7, 89hpes32t8, 89hpes32t8g2,
+ 89hpes48t12, 89hpes48t12g2.
+ - reg : I2C address of the IDT 89HPESx device.
+
+Optionally there can be EEPROM-compatible subnode:
+ - compatible: There are five EEPROM devices supported: 24c32, 24c64, 24c128,
+ 24c256 and 24c512 differed by size.
+ - reg: Custom address of EEPROM device (If not specified IDT 89HPESx
+ (optional) device will try to communicate with EEPROM sited by default
+ address - 0x50)
+ - read-only : Parameterless property disables writes to the EEPROM
+ (optional)
+
+Example:
+ idt@60 {
+ compatible = "idt,89hpes32nt8ag2";
+ reg = <0x74>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeprom@50 {
+ compatible = "onsemi,24c64";
+ reg = <0x50>;
+ read-only;
+ };
+ };
+
diff --git a/Bindings/mmc/amlogic,meson-gx.txt b/Bindings/mmc/amlogic,meson-gx.txt
index 7f95ec400863..50bf611a4d2c 100644
--- a/Bindings/mmc/amlogic,meson-gx.txt
+++ b/Bindings/mmc/amlogic,meson-gx.txt
@@ -17,7 +17,7 @@ Required properties:
"core" - Main peripheral bus clock
"clkin0" - Parent clock of internal mux
"clkin1" - Other parent clock of internal mux
- The driver has an interal mux clock which switches between clkin0 and clkin1 depending on the
+ The driver has an internal mux clock which switches between clkin0 and clkin1 depending on the
clock rate requested by the MMC core.
Example:
diff --git a/Bindings/mmc/brcm,bcm2835-sdhci.txt b/Bindings/mmc/brcm,bcm2835-sdhci.txt
deleted file mode 100644
index 59476fbdbfa1..000000000000
--- a/Bindings/mmc/brcm,bcm2835-sdhci.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-Broadcom BCM2835 SDHCI controller
-
-This file documents differences between the core properties described
-by mmc.txt and the properties that represent the BCM2835 controller.
-
-Required properties:
-- compatible : Should be "brcm,bcm2835-sdhci".
-- clocks : The clock feeding the SDHCI controller.
-
-Example:
-
-sdhci: sdhci {
- compatible = "brcm,bcm2835-sdhci";
- reg = <0x7e300000 0x100>;
- interrupts = <2 30>;
- clocks = <&clk_mmc>;
- bus-width = <4>;
-};
diff --git a/Bindings/mmc/mmc-pwrseq-sd8787.txt b/Bindings/mmc/mmc-pwrseq-sd8787.txt
new file mode 100644
index 000000000000..22e9340e4ba2
--- /dev/null
+++ b/Bindings/mmc/mmc-pwrseq-sd8787.txt
@@ -0,0 +1,16 @@
+* Marvell SD8787 power sequence provider
+
+Required properties:
+- compatible: must be "mmc-pwrseq-sd8787".
+- powerdown-gpios: contains a power down GPIO specifier with the
+ default active state
+- reset-gpios: contains a reset GPIO specifier with the default
+ active state
+
+Example:
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-sd8787";
+ powerdown-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&twl_gpio 1 GPIO_ACTIVE_LOW>;
+ }
diff --git a/Bindings/mmc/mmc.txt b/Bindings/mmc/mmc.txt
index 8a377827695b..c7f4a0ec48ed 100644
--- a/Bindings/mmc/mmc.txt
+++ b/Bindings/mmc/mmc.txt
@@ -40,6 +40,7 @@ Optional properties:
- cap-mmc-hw-reset: eMMC hardware reset is supported
- cap-sdio-irq: enable SDIO IRQ signalling on this interface
- full-pwr-cycle: full power cycle of the card is supported
+- mmc-ddr-3_3v: eMMC high-speed DDR mode(3.3V I/O) is supported
- mmc-ddr-1_8v: eMMC high-speed DDR mode(1.8V I/O) is supported
- mmc-ddr-1_2v: eMMC high-speed DDR mode(1.2V I/O) is supported
- mmc-hs200-1_8v: eMMC HS200 mode(1.8V I/O) is supported
diff --git a/Bindings/mmc/rockchip-dw-mshc.txt b/Bindings/mmc/rockchip-dw-mshc.txt
index ea9c1c9607f6..520d61dad6dd 100644
--- a/Bindings/mmc/rockchip-dw-mshc.txt
+++ b/Bindings/mmc/rockchip-dw-mshc.txt
@@ -13,7 +13,7 @@ Required Properties:
- "rockchip,rk2928-dw-mshc": for Rockchip RK2928 and following,
before RK3288
- "rockchip,rk3288-dw-mshc": for Rockchip RK3288
- - "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK1108
+ - "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RV1108
- "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3036
- "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3368
- "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3399
diff --git a/Bindings/mmc/sdhci-st.txt b/Bindings/mmc/sdhci-st.txt
index 3cd4c43a3260..230fd696eb92 100644
--- a/Bindings/mmc/sdhci-st.txt
+++ b/Bindings/mmc/sdhci-st.txt
@@ -38,7 +38,7 @@ Optional properties:
- bus-width: Number of data lines.
See: Documentation/devicetree/bindings/mmc/mmc.txt.
-- max-frequency: Can be 200MHz, 100Mz or 50MHz (default) and used for
+- max-frequency: Can be 200MHz, 100MHz or 50MHz (default) and used for
configuring the CCONFIG3 in the mmcss.
See: Documentation/devicetree/bindings/mmc/mmc.txt.
diff --git a/Bindings/mmc/sdhci.txt b/Bindings/mmc/sdhci.txt
index 1c95a1a555c3..0e9923a64024 100644
--- a/Bindings/mmc/sdhci.txt
+++ b/Bindings/mmc/sdhci.txt
@@ -5,7 +5,7 @@ host controllers refer to the mmc[1] bindings.
Optional properties:
- sdhci-caps-mask: The sdhci capabilities register is incorrect. This 64bit
- property corresponds to the bits in the sdhci capabilty register. If the bit
+ property corresponds to the bits in the sdhci capability register. If the bit
is on in the mask then the bit is incorrect in the register and should be
turned off, before applying sdhci-caps.
- sdhci-caps: The sdhci capabilities register is incorrect. This 64bit
diff --git a/Bindings/mmc/sunxi-mmc.txt b/Bindings/mmc/sunxi-mmc.txt
index 55cdd804cdba..7d53a799f140 100644
--- a/Bindings/mmc/sunxi-mmc.txt
+++ b/Bindings/mmc/sunxi-mmc.txt
@@ -13,6 +13,7 @@ Required properties:
* "allwinner,sun5i-a13-mmc"
* "allwinner,sun7i-a20-mmc"
* "allwinner,sun9i-a80-mmc"
+ * "allwinner,sun50i-a64-emmc"
* "allwinner,sun50i-a64-mmc"
- reg : mmc controller base registers
- clocks : a list with 4 phandle + clock specifier pairs
diff --git a/Bindings/mmc/synopsys-dw-mshc.txt b/Bindings/mmc/synopsys-dw-mshc.txt
index 7fd17c3da116..9cb55ca57461 100644
--- a/Bindings/mmc/synopsys-dw-mshc.txt
+++ b/Bindings/mmc/synopsys-dw-mshc.txt
@@ -16,7 +16,7 @@ Required Properties:
each child-node representing a supported slot. There should be atleast one
child node representing a card slot. The name of the child node representing
the slot is recommended to be slot@n where n is the unique number of the slot
- connnected to the controller. The following are optional properties which
+ connected to the controller. The following are optional properties which
can be included in the slot child node.
* reg: specifies the physical slot number. The valid values of this
@@ -75,6 +75,17 @@ Optional properties:
* card-detect-delay: Delay in milli-seconds before detecting card after card
insert event. The default value is 0.
+* data-addr: Override fifo address with value provided by DT. The default FIFO reg
+ offset is assumed as 0x100 (version < 0x240A) and 0x200(version >= 0x240A) by
+ driver. If the controller does not follow this rule, please use this property
+ to set fifo address in device tree.
+
+* fifo-watermark-aligned: Data done irq is expected if data length is less than
+ watermark in PIO mode. But fifo watermark is requested to be aligned with data
+ length in some SoC so that TX/RX irq can be generated with data done irq. Add this
+ watermark quirk to mark this requirement and force fifo watermark setting
+ accordingly.
+
* vmmc-supply: The phandle to the regulator to use for vmmc. If this is
specified we'll defer probe until we can find this regulator.
@@ -102,6 +113,8 @@ board specific portions as listed below.
interrupts = <0 75 0>;
#address-cells = <1>;
#size-cells = <0>;
+ data-addr = <0x200>;
+ fifo-watermark-aligned;
resets = <&rst 20>;
reset-names = "reset";
};
diff --git a/Bindings/mmc/tmio_mmc.txt b/Bindings/mmc/tmio_mmc.txt
index a1650edfd2b7..4fd8b7acc510 100644
--- a/Bindings/mmc/tmio_mmc.txt
+++ b/Bindings/mmc/tmio_mmc.txt
@@ -25,6 +25,19 @@ Required properties:
"renesas,sdhi-r8a7795" - SDHI IP on R8A7795 SoC
"renesas,sdhi-r8a7796" - SDHI IP on R8A7796 SoC
+- clocks: Most controllers only have 1 clock source per channel. However, on
+ some variations of this controller, the internal card detection
+ logic that exists in this controller is sectioned off to be run by a
+ separate second clock source to allow the main core clock to be turned
+ off to save power.
+ If 2 clocks are specified by the hardware, you must name them as
+ "core" and "cd". If the controller only has 1 clock, naming is not
+ required.
+ Below is the number clocks for each supported SoC:
+ 1: SH73A0, R8A73A4, R8A7740, R8A7778, R8A7779, R8A7790
+ R8A7791, R8A7792, R8A7793, R8A7794, R8A7795, R8A7796
+ 2: R7S72100
+
Optional properties:
- toshiba,mmc-wrprotect-disable: write-protect detection is unavailable
- pinctrl-names: should be "default", "state_uhs"
diff --git a/Bindings/mmc/zx-dw-mshc.txt b/Bindings/mmc/zx-dw-mshc.txt
new file mode 100644
index 000000000000..eaade0e5adeb
--- /dev/null
+++ b/Bindings/mmc/zx-dw-mshc.txt
@@ -0,0 +1,33 @@
+* ZTE specific extensions to the Synopsys Designware Mobile Storage
+ Host Controller
+
+The Synopsys designware mobile storage host controller is used to interface
+a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
+differences between the core Synopsys dw mshc controller properties described
+by synopsys-dw-mshc.txt and the properties used by the ZTE specific
+extensions to the Synopsys Designware Mobile Storage Host Controller.
+
+Required Properties:
+
+* compatible: should be
+ - "zte,zx296718-dw-mshc": for ZX SoCs
+
+Example:
+
+ mmc1: mmc@1110000 {
+ compatible = "zte,zx296718-dw-mshc";
+ reg = <0x01110000 0x1000>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ fifo-depth = <32>;
+ data-addr = <0x200>;
+ fifo-watermark-aligned;
+ bus-width = <4>;
+ clock-frequency = <50000000>;
+ clocks = <&topcrm SD0_AHB>, <&topcrm SD0_WCLK>;
+ clock-names = "biu", "ciu";
+ num-slots = <1>;
+ max-frequency = <50000000>;
+ cap-sdio-irq;
+ cap-sd-highspeed;
+ status = "disabled";
+ };
diff --git a/Bindings/mtd/aspeed-smc.txt b/Bindings/mtd/aspeed-smc.txt
new file mode 100644
index 000000000000..49f6528ef547
--- /dev/null
+++ b/Bindings/mtd/aspeed-smc.txt
@@ -0,0 +1,51 @@
+* Aspeed Firmware Memory controller
+* Aspeed SPI Flash Memory Controller
+
+The Firmware Memory Controller in the Aspeed AST2500 SoC supports
+three chip selects, two of which are always of SPI type and the third
+can be SPI or NOR type flash. These bindings only describe SPI.
+
+The two SPI flash memory controllers in the AST2500 each support two
+chip selects.
+
+Required properties:
+ - compatible : Should be one of
+ "aspeed,ast2400-fmc" for the AST2400 Firmware Memory Controller
+ "aspeed,ast2400-spi" for the AST2400 SPI Flash memory Controller
+ "aspeed,ast2500-fmc" for the AST2500 Firmware Memory Controller
+ "aspeed,ast2500-spi" for the AST2500 SPI flash memory controllers
+
+ - reg : the first contains the control register location and length,
+ the second contains the memory window mapping address and length
+ - #address-cells : must be 1 corresponding to chip select child binding
+ - #size-cells : must be 0 corresponding to chip select child binding
+
+Optional properties:
+ - interrupts : Should contain the interrupt for the dma device if an
+ FMC
+
+The child nodes are the SPI flash modules which must have a compatible
+property as specified in bindings/mtd/jedec,spi-nor.txt
+
+Optionally, the child node can contain properties for SPI mode (may be
+ignored):
+ - spi-max-frequency - max frequency of spi bus
+
+
+Example:
+fmc: fmc@1e620000 {
+ compatible = "aspeed,ast2500-fmc";
+ reg = < 0x1e620000 0x94
+ 0x20000000 0x02000000 >;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <19>;
+ flash@0 {
+ reg = < 0 >;
+ compatible = "jedec,spi-nor";
+ /* spi-max-frequency = <>; */
+ /* m25p,fast-read; */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+};
diff --git a/Bindings/mtd/common.txt b/Bindings/mtd/common.txt
new file mode 100644
index 000000000000..fc068b923d7a
--- /dev/null
+++ b/Bindings/mtd/common.txt
@@ -0,0 +1,15 @@
+* Common properties of all MTD devices
+
+Optional properties:
+- label: user-defined MTD device name. Can be used to assign user
+ friendly names to MTD devices (instead of the flash model or flash
+ controller based name) in order to ease flash device identification
+ and/or describe what they are used for.
+
+Example:
+
+ flash@0 {
+ label = "System-firmware";
+
+ /* flash type specific properties */
+ };
diff --git a/Bindings/mtd/cortina,gemini-flash.txt b/Bindings/mtd/cortina,gemini-flash.txt
new file mode 100644
index 000000000000..3fa1b34d69ad
--- /dev/null
+++ b/Bindings/mtd/cortina,gemini-flash.txt
@@ -0,0 +1,24 @@
+Flash device on Cortina Systems Gemini SoC
+
+This flash is regular CFI compatible (Intel or AMD extended) flash chips with
+some special bits that can be controlled by the machine's system controller.
+
+Required properties:
+- compatible : must be "cortina,gemini-flash", "cfi-flash";
+- reg : memory address for the flash chip
+- syscon : must be a phandle to the system controller
+- bank-width : width in bytes of flash interface, should be <2>
+
+For the rest of the properties, see mtd-physmap.txt.
+
+The device tree may optionally contain sub-nodes describing partitions of the
+address space. See partition.txt for more detail.
+
+Example:
+
+flash@30000000 {
+ compatible = "cortina,gemini-flash", "cfi-flash";
+ reg = <0x30000000 0x01000000>;
+ syscon = <&syscon>;
+ bank-width = <2>;
+};
diff --git a/Bindings/mtd/jedec,spi-nor.txt b/Bindings/mtd/jedec,spi-nor.txt
index 2c91c03e7eb0..3e920ec5c4d3 100644
--- a/Bindings/mtd/jedec,spi-nor.txt
+++ b/Bindings/mtd/jedec,spi-nor.txt
@@ -14,6 +14,8 @@ Required properties:
at25df641
at26df081a
mr25h256
+ mr25h10
+ mr25h40
mx25l4005a
mx25l1606e
mx25l6405d
diff --git a/Bindings/mtd/mtk-quadspi.txt b/Bindings/mtd/mtk-quadspi.txt
index fb314f09861b..5ded66ad7aef 100644
--- a/Bindings/mtd/mtk-quadspi.txt
+++ b/Bindings/mtd/mtk-quadspi.txt
@@ -1,7 +1,13 @@
* Serial NOR flash controller for MTK MT81xx (and similar)
Required properties:
-- compatible: should be "mediatek,mt8173-nor";
+- compatible: The possible values are:
+ "mediatek,mt2701-nor"
+ "mediatek,mt7623-nor"
+ "mediatek,mt8173-nor"
+ For mt8173, compatible should be "mediatek,mt8173-nor".
+ For every other SoC, should contain both the SoC-specific compatible string
+ and "mediatek,mt8173-nor".
- reg: physical base address and length of the controller's register
- clocks: the phandle of the clocks needed by the nor controller
- clock-names: the names of the clocks
diff --git a/Bindings/net/brcm,bcm7445-switch-v4.0.txt b/Bindings/net/brcm,bcm7445-switch-v4.0.txt
index fb40891ee606..9a734d808aa7 100644
--- a/Bindings/net/brcm,bcm7445-switch-v4.0.txt
+++ b/Bindings/net/brcm,bcm7445-switch-v4.0.txt
@@ -2,7 +2,7 @@
Required properties:
-- compatible: should be "brcm,bcm7445-switch-v4.0"
+- compatible: should be "brcm,bcm7445-switch-v4.0" or "brcm,bcm7278-switch-v4.0"
- reg: addresses and length of the register sets for the device, must be 6
pairs of register addresses and lengths
- interrupts: interrupts for the devices, must be two interrupts
@@ -41,6 +41,13 @@ Optional properties:
Admission Control Block supports reporting the number of packets in-flight in a
switch queue
+Port subnodes:
+
+Optional properties:
+
+- brcm,use-bcm-hdr: boolean property, if present, indicates that the switch
+ port has Broadcom tags enabled (per-packet metadata)
+
Example:
switch_top@f0b00000 {
@@ -114,6 +121,7 @@ switch_top@f0b00000 {
port@0 {
label = "gphy";
reg = <0>;
+ brcm,use-bcm-hdr;
};
...
};
diff --git a/Bindings/net/brcm,systemport.txt b/Bindings/net/brcm,systemport.txt
index 877da34145b0..83f29e0e11ba 100644
--- a/Bindings/net/brcm,systemport.txt
+++ b/Bindings/net/brcm,systemport.txt
@@ -1,7 +1,10 @@
* Broadcom BCM7xxx Ethernet Systemport Controller (SYSTEMPORT)
Required properties:
-- compatible: should be one of "brcm,systemport-v1.00" or "brcm,systemport"
+- compatible: should be one of:
+ "brcm,systemport-v1.00"
+ "brcm,systemportlite-v1.00" or
+ "brcm,systemport"
- reg: address and length of the register set for the device.
- interrupts: interrupts for the device, first cell must be for the rx
interrupts, and the second cell should be for the transmit queues. An
diff --git a/Bindings/net/btusb.txt b/Bindings/net/btusb.txt
new file mode 100644
index 000000000000..01fa2d4188d4
--- /dev/null
+++ b/Bindings/net/btusb.txt
@@ -0,0 +1,43 @@
+Generic Bluetooth controller over USB (btusb driver)
+---------------------------------------------------
+
+Required properties:
+
+ - compatible : should comply with the format "usbVID,PID" specified in
+ Documentation/devicetree/bindings/usb/usb-device.txt
+ At the time of writing, the only OF supported devices
+ (more may be added later) are:
+
+ "usb1286,204e" (Marvell 8997)
+
+Also, vendors that use btusb may have device additional properties, e.g:
+Documentation/devicetree/bindings/net/marvell-bt-8xxx.txt
+
+Optional properties:
+
+ - interrupt-parent: phandle of the parent interrupt controller
+ - interrupt-names: (see below)
+ - interrupts : The interrupt specified by the name "wakeup" is the interrupt
+ that shall be used for out-of-band wake-on-bt. Driver will
+ request this interrupt for wakeup. During system suspend, the
+ irq will be enabled so that the bluetooth chip can wakeup host
+ platform out of band. During system resume, the irq will be
+ disabled to make sure unnecessary interrupt is not received.
+
+Example:
+
+Following example uses irq pin number 3 of gpio0 for out of band wake-on-bt:
+
+&usb_host1_ehci {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mvl_bt1: bt@1 {
+ compatible = "usb1286,204e";
+ reg = <1>;
+ interrupt-parent = <&gpio0>;
+ interrupt-name = "wakeup";
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
diff --git a/Bindings/net/cpsw.txt b/Bindings/net/cpsw.txt
index ebda7c93453a..7cc15c96ea95 100644
--- a/Bindings/net/cpsw.txt
+++ b/Bindings/net/cpsw.txt
@@ -23,7 +23,6 @@ Required properties:
Optional properties:
- ti,hwmods : Must be "cpgmac0"
-- no_bd_ram : Must be 0 or 1
- dual_emac : Specifies Switch to act as Dual EMAC
- syscon : Phandle to the system control device node, which is
the control module device of the am33x
@@ -70,7 +69,6 @@ Examples:
cpdma_channels = <8>;
ale_entries = <1024>;
bd_ram_size = <0x2000>;
- no_bd_ram = <0>;
rx_descs = <64>;
mac_control = <0x20>;
slaves = <2>;
@@ -99,7 +97,6 @@ Examples:
cpdma_channels = <8>;
ale_entries = <1024>;
bd_ram_size = <0x2000>;
- no_bd_ram = <0>;
rx_descs = <64>;
mac_control = <0x20>;
slaves = <2>;
diff --git a/Bindings/net/dsa/dsa.txt b/Bindings/net/dsa/dsa.txt
index a4a570fb2494..cfe8f64eca4f 100644
--- a/Bindings/net/dsa/dsa.txt
+++ b/Bindings/net/dsa/dsa.txt
@@ -34,13 +34,9 @@ Required properties:
Each port children node must have the following mandatory properties:
- reg : Describes the port address in the switch
-- label : Describes the label associated with this port, which
- will become the netdev name. Special labels are
- "cpu" to indicate a CPU port and "dsa" to
- indicate an uplink/downlink port between switches in
- the cluster.
-A port labelled "dsa" has the following mandatory property:
+An uplink/downlink port between switches in the cluster has the following
+mandatory property:
- link : Should be a list of phandles to other switch's DSA
port. This port is used as the outgoing port
@@ -48,12 +44,17 @@ A port labelled "dsa" has the following mandatory property:
information must be given, not just the one hop
routes to neighbouring switches.
-A port labelled "cpu" has the following mandatory property:
+A CPU port has the following mandatory property:
- ethernet : Should be a phandle to a valid Ethernet device node.
This host device is what the switch port is
connected to.
+A user port has the following optional property:
+
+- label : Describes the label associated with this port, which
+ will become the netdev name.
+
Port child nodes may also contain the following optional standardised
properties, described in binding documents:
@@ -107,7 +108,6 @@ linked into one DSA cluster.
switch0port5: port@5 {
reg = <5>;
- label = "dsa";
phy-mode = "rgmii-txid";
link = <&switch1port6
&switch2port9>;
@@ -119,7 +119,6 @@ linked into one DSA cluster.
port@6 {
reg = <6>;
- label = "cpu";
ethernet = <&fec1>;
fixed-link {
speed = <100>;
@@ -165,7 +164,6 @@ linked into one DSA cluster.
switch1port5: port@5 {
reg = <5>;
- label = "dsa";
link = <&switch2port9>;
phy-mode = "rgmii-txid";
fixed-link {
@@ -176,7 +174,6 @@ linked into one DSA cluster.
switch1port6: port@6 {
reg = <6>;
- label = "dsa";
phy-mode = "rgmii-txid";
link = <&switch0port5>;
fixed-link {
@@ -255,7 +252,6 @@ linked into one DSA cluster.
switch2port9: port@9 {
reg = <9>;
- label = "dsa";
phy-mode = "rgmii-txid";
link = <&switch1port5
&switch0port5>;
diff --git a/Bindings/net/dsa/marvell.txt b/Bindings/net/dsa/marvell.txt
index b3dd6b40e0de..7ef9dbb08957 100644
--- a/Bindings/net/dsa/marvell.txt
+++ b/Bindings/net/dsa/marvell.txt
@@ -14,9 +14,9 @@ The properties described here are those specific to Marvell devices.
Additional required and optional properties can be found in dsa.txt.
Required properties:
-- compatible : Should be one of "marvell,mv88e6085" or
- "marvell,mv88e6190"
-- reg : Address on the MII bus for the switch.
+- compatible : Should be one of "marvell,mv88e6085" or
+ "marvell,mv88e6190"
+- reg : Address on the MII bus for the switch.
Optional properties:
@@ -26,30 +26,67 @@ Optional properties:
- interrupt-controller : Indicates the switch is itself an interrupt
controller. This is used for the PHY interrupts.
#interrupt-cells = <2> : Controller uses two cells, number and flag
-- mdio : container of PHY and devices on the switches MDIO
- bus
+- mdio : Container of PHY and devices on the switches MDIO
+ bus.
+- mdio? : Container of PHYs and devices on the external MDIO
+ bus. The node must contains a compatible string of
+ "marvell,mv88e6xxx-mdio-external"
+
Example:
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
- interrupt-parent = <&gpio0>;
- interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
- interrupt-controller;
- #interrupt-cells = <2>;
-
- switch0: switch@0 {
- compatible = "marvell,mv88e6085";
- reg = <0>;
- reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
- };
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
- switch1phy0: switch1phy0@0 {
- reg = <0>;
- interrupt-parent = <&switch0>;
- interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
- };
- };
- };
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ switch0: switch@0 {
+ compatible = "marvell,mv88e6085";
+ reg = <0>;
+ reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
+ };
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ switch1phy0: switch1phy0@0 {
+ reg = <0>;
+ interrupt-parent = <&switch0>;
+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+ };
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ switch0: switch@0 {
+ compatible = "marvell,mv88e6390";
+ reg = <0>;
+ reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
+ };
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ switch1phy0: switch1phy0@0 {
+ reg = <0>;
+ interrupt-parent = <&switch0>;
+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ mdio1 {
+ compatible = "marvell,mv88e6xxx-mdio-external";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ switch1phy9: switch1phy0@9 {
+ reg = <9>;
+ };
+ };
+ };
diff --git a/Bindings/net/ethernet.txt b/Bindings/net/ethernet.txt
index 05150957ecfd..3a6916909d90 100644
--- a/Bindings/net/ethernet.txt
+++ b/Bindings/net/ethernet.txt
@@ -29,6 +29,9 @@ The following properties are common to the Ethernet controllers:
* "smii"
* "xgmii"
* "trgmii"
+ * "2000base-x",
+ * "2500base-x",
+ * "rxaui"
- phy-connection-type: the same as "phy-mode" property but described in ePAPR;
- phy-handle: phandle, specifies a reference to a node representing a PHY
device; this property is described in ePAPR and so preferred;
diff --git a/Bindings/net/marvell,prestera.txt b/Bindings/net/marvell,prestera.txt
new file mode 100644
index 000000000000..5fbab29718e8
--- /dev/null
+++ b/Bindings/net/marvell,prestera.txt
@@ -0,0 +1,50 @@
+Marvell Prestera Switch Chip bindings
+-------------------------------------
+
+Required properties:
+- compatible: one of the following
+ "marvell,prestera-98dx3236",
+ "marvell,prestera-98dx3336",
+ "marvell,prestera-98dx4251",
+- reg: address and length of the register set for the device.
+- interrupts: interrupt for the device
+
+Optional properties:
+- dfx: phandle reference to the "DFX Server" node
+
+Example:
+
+switch {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>;
+
+ packet-processor@0 {
+ compatible = "marvell,prestera-98dx3236";
+ reg = <0 0x4000000>;
+ interrupts = <33>, <34>, <35>;
+ dfx = <&dfx>;
+ };
+};
+
+DFX Server bindings
+-------------------
+
+Required properties:
+- compatible: must be "marvell,dfx-server"
+- reg: address and length of the register set for the device.
+
+Example:
+
+dfx-registers {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
+
+ dfx: dfx@0 {
+ compatible = "marvell,dfx-server";
+ reg = <0 0x100000>;
+ };
+};
diff --git a/Bindings/net/marvell-armada-370-neta.txt b/Bindings/net/marvell-armada-370-neta.txt
index 7aa840c8768d..ae4234ca4ee4 100644
--- a/Bindings/net/marvell-armada-370-neta.txt
+++ b/Bindings/net/marvell-armada-370-neta.txt
@@ -1,7 +1,7 @@
* Marvell Armada 370 / Armada XP / Armada 3700 Ethernet Controller (NETA)
Required properties:
-- compatible: could be one of the followings
+- compatible: could be one of the following:
"marvell,armada-370-neta"
"marvell,armada-xp-neta"
"marvell,armada-3700-neta"
diff --git a/Bindings/net/marvell-bt-sd8xxx.txt b/Bindings/net/marvell-bt-8xxx.txt
index 6a9a63cb0543..9be1059ff03f 100644
--- a/Bindings/net/marvell-bt-sd8xxx.txt
+++ b/Bindings/net/marvell-bt-8xxx.txt
@@ -1,16 +1,21 @@
-Marvell 8897/8997 (sd8897/sd8997) bluetooth SDIO devices
+Marvell 8897/8997 (sd8897/sd8997) bluetooth devices (SDIO or USB based)
------
+The 8997 devices supports multiple interfaces. When used on SDIO interfaces,
+the btmrvl driver is used and when used on USB interface, the btusb driver is
+used.
Required properties:
- compatible : should be one of the following:
- * "marvell,sd8897-bt"
- * "marvell,sd8997-bt"
+ * "marvell,sd8897-bt" (for SDIO)
+ * "marvell,sd8997-bt" (for SDIO)
+ * "usb1286,204e" (for USB)
Optional properties:
- marvell,cal-data: Calibration data downloaded to the device during
initialization. This is an array of 28 values(u8).
+ This is only applicable to SDIO devices.
- marvell,wakeup-pin: It represents wakeup pin number of the bluetooth chip.
firmware will use the pin to wakeup host system (u16).
@@ -18,10 +23,15 @@ Optional properties:
platform. The value will be configured to firmware. This
is needed to work chip's sleep feature as expected (u16).
- interrupt-parent: phandle of the parent interrupt controller
- - interrupts : interrupt pin number to the cpu. Driver will request an irq based
- on this interrupt number. During system suspend, the irq will be
- enabled so that the bluetooth chip can wakeup host platform under
- certain condition. During system resume, the irq will be disabled
+ - interrupt-names: Used only for USB based devices (See below)
+ - interrupts : specifies the interrupt pin number to the cpu. For SDIO, the
+ driver will use the first interrupt specified in the interrupt
+ array. For USB based devices, the driver will use the interrupt
+ named "wakeup" from the interrupt-names and interrupt arrays.
+ The driver will request an irq based on this interrupt number.
+ During system suspend, the irq will be enabled so that the
+ bluetooth chip can wakeup host platform under certain
+ conditions. During system resume, the irq will be disabled
to make sure unnecessary interrupt is not received.
Example:
@@ -29,7 +39,9 @@ Example:
IRQ pin 119 is used as system wakeup source interrupt.
wakeup pin 13 and gap 100ms are configured so that firmware can wakeup host
using this device side pin and wakeup latency.
-calibration data is also available in below example.
+
+Example for SDIO device follows (calibration data is also available in
+below example).
&mmc3 {
status = "okay";
@@ -54,3 +66,21 @@ calibration data is also available in below example.
marvell,wakeup-gap-ms = /bits/ 16 <0x64>;
};
};
+
+Example for USB device:
+
+&usb_host1_ohci {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mvl_bt1: bt@1 {
+ compatible = "usb1286,204e";
+ reg = <1>;
+ interrupt-parent = <&gpio0>;
+ interrupt-names = "wakeup";
+ interrupts = <119 IRQ_TYPE_LEVEL_LOW>;
+ marvell,wakeup-pin = /bits/ 16 <0x0d>;
+ marvell,wakeup-gap-ms = /bits/ 16 <0x64>;
+ };
+};
diff --git a/Bindings/net/marvell-pp2.txt b/Bindings/net/marvell-pp2.txt
index aa4f4230bfd7..4754364df4c6 100644
--- a/Bindings/net/marvell-pp2.txt
+++ b/Bindings/net/marvell-pp2.txt
@@ -27,9 +27,7 @@ Optional properties (port):
- marvell,loopback: port is loopback mode
- phy: a phandle to a phy node defining the PHY address (as the reg
- property, a single integer). Note: if this property isn't present,
- then fixed link is assumed, and the 'fixed-link' property is
- mandatory.
+ property, a single integer).
Example:
diff --git a/Bindings/net/meson-dwmac.txt b/Bindings/net/meson-dwmac.txt
index 89e62ddc69ca..0703ad3f3c1e 100644
--- a/Bindings/net/meson-dwmac.txt
+++ b/Bindings/net/meson-dwmac.txt
@@ -25,6 +25,22 @@ Required properties on Meson8b and newer:
- "clkin0" - first parent clock of the internal mux
- "clkin1" - second parent clock of the internal mux
+Optional properties on Meson8b and newer:
+- amlogic,tx-delay-ns: The internal RGMII TX clock delay (provided
+ by this driver) in nanoseconds. Allowed values
+ are: 0ns, 2ns, 4ns, 6ns.
+ When phy-mode is set to "rgmii" then the TX
+ delay should be explicitly configured. When
+ not configured a fallback of 2ns is used.
+ When the phy-mode is set to either "rgmii-id"
+ or "rgmii-txid" the TX clock delay is already
+ provided by the PHY. In that case this
+ property should be set to 0ns (which disables
+ the TX clock delay in the MAC to prevent the
+ clock from going off because both PHY and MAC
+ are adding a delay).
+ Any configuration is ignored when the phy-mode
+ is set to "rmii".
Example for Meson6:
diff --git a/Bindings/net/mscc-phy-vsc8531.txt b/Bindings/net/mscc-phy-vsc8531.txt
index bdefefc66594..0eedabe22cc3 100644
--- a/Bindings/net/mscc-phy-vsc8531.txt
+++ b/Bindings/net/mscc-phy-vsc8531.txt
@@ -27,6 +27,14 @@ Optional properties:
'vddmac'.
Default value is 0%.
Ref: Table:1 - Edge rate change (below).
+- vsc8531,led-0-mode : LED mode. Specify how the LED[0] should behave.
+ Allowed values are define in
+ "include/dt-bindings/net/mscc-phy-vsc8531.h".
+ Default value is VSC8531_LINK_1000_ACTIVITY (1).
+- vsc8531,led-1-mode : LED mode. Specify how the LED[1] should behave.
+ Allowed values are define in
+ "include/dt-bindings/net/mscc-phy-vsc8531.h".
+ Default value is VSC8531_LINK_100_ACTIVITY (2).
Table: 1 - Edge rate change
----------------------------------------------------------------|
@@ -60,4 +68,6 @@ Example:
compatible = "ethernet-phy-id0007.0570";
vsc8531,vddmac = <3300>;
vsc8531,edge-slowdown = <7>;
+ vsc8531,led-0-mode = <LINK_1000_ACTIVITY>;
+ vsc8531,led-1-mode = <LINK_100_ACTIVITY>;
};
diff --git a/Bindings/net/phy.txt b/Bindings/net/phy.txt
index fb5056b22685..b55857696fc3 100644
--- a/Bindings/net/phy.txt
+++ b/Bindings/net/phy.txt
@@ -39,6 +39,10 @@ Optional Properties:
- enet-phy-lane-swap: If set, indicates the PHY will swap the TX/RX lanes to
compensate for the board being designed with the lanes swapped.
+- enet-phy-lane-no-swap: If set, indicates that PHY will disable swap of the
+ TX/RX lanes. This property allows the PHY to work correcly after e.g. wrong
+ bootstrap configuration caused by issues in PCB layout design.
+
- eee-broken-100tx:
- eee-broken-1000t:
- eee-broken-10gt:
diff --git a/Bindings/net/rockchip-dwmac.txt b/Bindings/net/rockchip-dwmac.txt
index 95383c5131fc..8f427550720a 100644
--- a/Bindings/net/rockchip-dwmac.txt
+++ b/Bindings/net/rockchip-dwmac.txt
@@ -6,6 +6,7 @@ Required properties:
- compatible: should be "rockchip,<name>-gamc"
"rockchip,rk3228-gmac": found on RK322x SoCs
"rockchip,rk3288-gmac": found on RK3288 SoCs
+ "rockchip,rk3328-gmac": found on RK3328 SoCs
"rockchip,rk3366-gmac": found on RK3366 SoCs
"rockchip,rk3368-gmac": found on RK3368 SoCs
"rockchip,rk3399-gmac": found on RK3399 SoCs
diff --git a/Bindings/net/snps,dwc-qos-ethernet.txt b/Bindings/net/snps,dwc-qos-ethernet.txt
index d93f71ce8346..21d27aa4c68c 100644
--- a/Bindings/net/snps,dwc-qos-ethernet.txt
+++ b/Bindings/net/snps,dwc-qos-ethernet.txt
@@ -1,5 +1,8 @@
* Synopsys DWC Ethernet QoS IP version 4.10 driver (GMAC)
+This binding is deprecated, but it continues to be supported, but new
+features should be preferably added to the stmmac binding document.
+
This binding supports the Synopsys Designware Ethernet QoS (Quality Of Service)
IP block. The IP supports multiple options for bus type, clocking and reset
structure, and feature list. Consequently, a number of properties and list
diff --git a/Bindings/net/stmmac.txt b/Bindings/net/stmmac.txt
index 128da752fec9..d3bfc2b30fb5 100644
--- a/Bindings/net/stmmac.txt
+++ b/Bindings/net/stmmac.txt
@@ -49,6 +49,8 @@ Optional properties:
- snps,force_sf_dma_mode Force DMA to use the Store and Forward
mode for both tx and rx. This flag is
ignored if force_thresh_dma_mode is set.
+- snps,en-tx-lpi-clockgating Enable gating of the MAC TX clock during
+ TX low-power mode
- snps,multicast-filter-bins: Number of multicast filter hash bins
supported by this device instance
- snps,perfect-filter-entries: Number of perfect filter entries supported
@@ -65,7 +67,6 @@ Optional properties:
- snps,wr_osr_lmt: max write outstanding req. limit
- snps,rd_osr_lmt: max read outstanding req. limit
- snps,kbbe: do not cross 1KiB boundary.
- - snps,axi_all: align address
- snps,blen: this is a vector of supported burst length.
- snps,fb: fixed-burst
- snps,mb: mixed-burst
diff --git a/Bindings/net/wireless/ieee80211.txt b/Bindings/net/wireless/ieee80211.txt
new file mode 100644
index 000000000000..f6442b1397f5
--- /dev/null
+++ b/Bindings/net/wireless/ieee80211.txt
@@ -0,0 +1,24 @@
+Common IEEE 802.11 properties
+
+This provides documentation of common properties that are valid for all wireless
+devices.
+
+Optional properties:
+ - ieee80211-freq-limit : list of supported frequency ranges in KHz. This can be
+ used for devices that in a given config support less channels than
+ normally. It may happen chipset supports a wide wireless band but it is
+ limited to some part of it due to used antennas or power amplifier.
+ An example case for this can be tri-band wireless router with two
+ identical chipsets used for two different 5 GHz subbands. Using them
+ incorrectly could not work or decrease performance noticeably.
+
+Example:
+
+pcie@0,0 {
+ reg = <0x0000 0 0 0 0>;
+ wifi@0,0 {
+ reg = <0x0000 0 0 0 0>;
+ ieee80211-freq-limit = <2402000 2482000>,
+ <5170000 5250000>;
+ };
+};
diff --git a/Bindings/net/wireless/marvell-8xxx.txt b/Bindings/net/wireless/marvell-8xxx.txt
index 980b16df74c3..0854451ff91d 100644
--- a/Bindings/net/wireless/marvell-8xxx.txt
+++ b/Bindings/net/wireless/marvell-8xxx.txt
@@ -1,4 +1,4 @@
-Marvell 8897/8997 (sd8897/sd8997/pcie8997) SDIO/PCIE devices
+Marvell 8787/8897/8997 (sd8787/sd8897/sd8997/pcie8997) SDIO/PCIE devices
------
This node provides properties for controlling the Marvell SDIO/PCIE wireless device.
@@ -8,6 +8,7 @@ connects the device to the system.
Required properties:
- compatible : should be one of the following:
+ * "marvell,sd8787"
* "marvell,sd8897"
* "marvell,sd8997"
* "pci11ab,2b42"
@@ -34,6 +35,9 @@ Optional properties:
so that the wifi chip can wakeup host platform under certain condition.
during system resume, the irq will be disabled to make sure
unnecessary interrupt is not received.
+ - vmmc-supply: a phandle of a regulator, supplying VCC to the card
+ - mmc-pwrseq: phandle to the MMC power sequence node. See "mmc-pwrseq-*"
+ for documentation of MMC power sequence bindings.
Example:
@@ -46,6 +50,7 @@ so that firmware can wakeup host using this device side pin.
&mmc3 {
status = "okay";
vmmc-supply = <&wlan_en_reg>;
+ mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
cap-power-off-card;
keep-power-in-suspend;
diff --git a/Bindings/net/wireless/marvell-sd8xxx.txt b/Bindings/net/wireless/marvell-sd8xxx.txt
deleted file mode 100644
index c421aba0a5bc..000000000000
--- a/Bindings/net/wireless/marvell-sd8xxx.txt
+++ /dev/null
@@ -1,63 +0,0 @@
-Marvell 8897/8997 (sd8897/sd8997) SDIO devices
-------
-
-This node provides properties for controlling the marvell sdio wireless device.
-The node is expected to be specified as a child node to the SDIO controller that
-connects the device to the system.
-
-Required properties:
-
- - compatible : should be one of the following:
- * "marvell,sd8897"
- * "marvell,sd8997"
-
-Optional properties:
-
- - marvell,caldata* : A series of properties with marvell,caldata prefix,
- represent calibration data downloaded to the device during
- initialization. This is an array of unsigned 8-bit values.
- the properties should follow below property name and
- corresponding array length:
- "marvell,caldata-txpwrlimit-2g" (length = 566).
- "marvell,caldata-txpwrlimit-5g-sub0" (length = 502).
- "marvell,caldata-txpwrlimit-5g-sub1" (length = 688).
- "marvell,caldata-txpwrlimit-5g-sub2" (length = 750).
- "marvell,caldata-txpwrlimit-5g-sub3" (length = 502).
- - marvell,wakeup-pin : a wakeup pin number of wifi chip which will be configured
- to firmware. Firmware will wakeup the host using this pin
- during suspend/resume.
- - interrupt-parent: phandle of the parent interrupt controller
- - interrupts : interrupt pin number to the cpu. driver will request an irq based on
- this interrupt number. during system suspend, the irq will be enabled
- so that the wifi chip can wakeup host platform under certain condition.
- during system resume, the irq will be disabled to make sure
- unnecessary interrupt is not received.
-
-Example:
-
-Tx power limit calibration data is configured in below example.
-The calibration data is an array of unsigned values, the length
-can vary between hw versions.
-IRQ pin 38 is used as system wakeup source interrupt. wakeup pin 3 is configured
-so that firmware can wakeup host using this device side pin.
-
-&mmc3 {
- status = "okay";
- vmmc-supply = <&wlan_en_reg>;
- bus-width = <4>;
- cap-power-off-card;
- keep-power-in-suspend;
-
- #address-cells = <1>;
- #size-cells = <0>;
- mwifiex: wifi@1 {
- compatible = "marvell,sd8897";
- reg = <1>;
- interrupt-parent = <&pio>;
- interrupts = <38 IRQ_TYPE_LEVEL_LOW>;
-
- marvell,caldata_00_txpwrlimit_2g_cfg_set = /bits/ 8 <
- 0x01 0x00 0x06 0x00 0x08 0x02 0x89 0x01>;
- marvell,wakeup-pin = <3>;
- };
-};
diff --git a/Bindings/nvmem/imx-ocotp.txt b/Bindings/nvmem/imx-ocotp.txt
index 383d5889e95a..966a72ecc6bd 100644
--- a/Bindings/nvmem/imx-ocotp.txt
+++ b/Bindings/nvmem/imx-ocotp.txt
@@ -1,13 +1,15 @@
Freescale i.MX6 On-Chip OTP Controller (OCOTP) device tree bindings
This binding represents the on-chip eFuse OTP controller found on
-i.MX6Q/D, i.MX6DL/S, i.MX6SL, and i.MX6SX SoCs.
+i.MX6Q/D, i.MX6DL/S, i.MX6SL, i.MX6SX and i.MX6UL SoCs.
Required properties:
- compatible: should be one of
"fsl,imx6q-ocotp" (i.MX6Q/D/DL/S),
"fsl,imx6sl-ocotp" (i.MX6SL), or
- "fsl,imx6sx-ocotp" (i.MX6SX), followed by "syscon".
+ "fsl,imx6sx-ocotp" (i.MX6SX),
+ "fsl,imx6ul-ocotp" (i.MX6UL),
+ followed by "syscon".
- reg: Should contain the register base and length.
- clocks: Should contain a phandle pointing to the gated peripheral clock.
diff --git a/Bindings/opp/opp.txt b/Bindings/opp/opp.txt
index 9f5ca4457b5f..63725498bd20 100644
--- a/Bindings/opp/opp.txt
+++ b/Bindings/opp/opp.txt
@@ -136,7 +136,7 @@ Optional properties:
larger OPP table, based on what version of the hardware we are running on. We
still can't have multiple nodes with the same opp-hz value in OPP table.
- It's an user defined array containing a hierarchy of hardware version numbers,
+ It's a user defined array containing a hierarchy of hardware version numbers,
supported by the OPP. For example: a platform with hierarchy of three levels
of versions (A, B and C), this field should be like <X Y Z>, where X
corresponds to Version hierarchy A, Y corresponds to version hierarchy B and Z
@@ -188,14 +188,14 @@ Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states together.
opp@1000000000 {
opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <970000 975000 985000>;
+ opp-microvolt = <975000 970000 985000>;
opp-microamp = <70000>;
clock-latency-ns = <300000>;
opp-suspend;
};
opp@1100000000 {
opp-hz = /bits/ 64 <1100000000>;
- opp-microvolt = <980000 1000000 1010000>;
+ opp-microvolt = <1000000 980000 1010000>;
opp-microamp = <80000>;
clock-latency-ns = <310000>;
};
@@ -267,14 +267,14 @@ independently.
opp@1000000000 {
opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <970000 975000 985000>;
+ opp-microvolt = <975000 970000 985000>;
opp-microamp = <70000>;
clock-latency-ns = <300000>;
opp-suspend;
};
opp@1100000000 {
opp-hz = /bits/ 64 <1100000000>;
- opp-microvolt = <980000 1000000 1010000>;
+ opp-microvolt = <1000000 980000 1010000>;
opp-microamp = <80000>;
clock-latency-ns = <310000>;
};
@@ -343,14 +343,14 @@ DVFS state together.
opp@1000000000 {
opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <970000 975000 985000>;
+ opp-microvolt = <975000 970000 985000>;
opp-microamp = <70000>;
clock-latency-ns = <300000>;
opp-suspend;
};
opp@1100000000 {
opp-hz = /bits/ 64 <1100000000>;
- opp-microvolt = <980000 1000000 1010000>;
+ opp-microvolt = <1000000 980000 1010000>;
opp-microamp = <80000>;
clock-latency-ns = <310000>;
};
@@ -369,7 +369,7 @@ DVFS state together.
opp@1300000000 {
opp-hz = /bits/ 64 <1300000000>;
- opp-microvolt = <1045000 1050000 1055000>;
+ opp-microvolt = <1050000 1045000 1055000>;
opp-microamp = <95000>;
clock-latency-ns = <400000>;
opp-suspend;
@@ -382,7 +382,7 @@ DVFS state together.
};
opp@1500000000 {
opp-hz = /bits/ 64 <1500000000>;
- opp-microvolt = <1010000 1100000 1110000>;
+ opp-microvolt = <1100000 1010000 1110000>;
opp-microamp = <95000>;
clock-latency-ns = <400000>;
turbo-mode;
@@ -424,9 +424,9 @@ Example 4: Handling multiple regulators
opp@1000000000 {
opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <970000 975000 985000>, /* Supply 0 */
- <960000 965000 975000>, /* Supply 1 */
- <960000 965000 975000>; /* Supply 2 */
+ opp-microvolt = <975000 970000 985000>, /* Supply 0 */
+ <965000 960000 975000>, /* Supply 1 */
+ <965000 960000 975000>; /* Supply 2 */
opp-microamp = <70000>, /* Supply 0 */
<70000>, /* Supply 1 */
<70000>; /* Supply 2 */
@@ -437,9 +437,9 @@ Example 4: Handling multiple regulators
opp@1000000000 {
opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <970000 975000 985000>, /* Supply 0 */
- <960000 965000 975000>, /* Supply 1 */
- <960000 965000 975000>; /* Supply 2 */
+ opp-microvolt = <975000 970000 985000>, /* Supply 0 */
+ <965000 960000 975000>, /* Supply 1 */
+ <965000 960000 975000>; /* Supply 2 */
opp-microamp = <70000>, /* Supply 0 */
<0>, /* Supply 1 doesn't need this */
<70000>; /* Supply 2 */
@@ -474,7 +474,7 @@ Example 5: opp-supported-hw
*/
opp-supported-hw = <0xF 0xFFFFFFFF 0xFFFFFFFF>
opp-hz = /bits/ 64 <600000000>;
- opp-microvolt = <900000 915000 925000>;
+ opp-microvolt = <915000 900000 925000>;
...
};
@@ -487,7 +487,7 @@ Example 5: opp-supported-hw
*/
opp-supported-hw = <0x20 0xff0000ff 0x0000f4f0>
opp-hz = /bits/ 64 <800000000>;
- opp-microvolt = <900000 915000 925000>;
+ opp-microvolt = <915000 900000 925000>;
...
};
};
@@ -512,18 +512,18 @@ Example 6: opp-microvolt-<name>, opp-microamp-<name>:
opp@1000000000 {
opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt-slow = <900000 915000 925000>;
- opp-microvolt-fast = <970000 975000 985000>;
+ opp-microvolt-slow = <915000 900000 925000>;
+ opp-microvolt-fast = <975000 970000 985000>;
opp-microamp-slow = <70000>;
opp-microamp-fast = <71000>;
};
opp@1200000000 {
opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt-slow = <900000 915000 925000>, /* Supply vcc0 */
- <910000 925000 935000>; /* Supply vcc1 */
- opp-microvolt-fast = <970000 975000 985000>, /* Supply vcc0 */
- <960000 965000 975000>; /* Supply vcc1 */
+ opp-microvolt-slow = <915000 900000 925000>, /* Supply vcc0 */
+ <925000 910000 935000>; /* Supply vcc1 */
+ opp-microvolt-fast = <975000 970000 985000>, /* Supply vcc0 */
+ <965000 960000 975000>; /* Supply vcc1 */
opp-microamp = <70000>; /* Will be used for both slow/fast */
};
};
diff --git a/Bindings/pci/hisilicon-pcie.txt b/Bindings/pci/hisilicon-pcie.txt
index 59c2f47aa303..a339dbb15493 100644
--- a/Bindings/pci/hisilicon-pcie.txt
+++ b/Bindings/pci/hisilicon-pcie.txt
@@ -42,3 +42,46 @@ Hip05 Example (note that Hip06 is the same except compatible):
0x0 0 0 4 &mbigen_pcie 4 13>;
status = "ok";
};
+
+HiSilicon Hip06/Hip07 PCIe host bridge DT (almost-ECAM) description.
+
+Some BIOSes place the host controller in a mode where it is ECAM
+compliant for all devices other than the root complex. In such cases,
+the host controller should be described as below.
+
+The properties and their meanings are identical to those described in
+host-generic-pci.txt except as listed below.
+
+Properties of the host controller node that differ from
+host-generic-pci.txt:
+
+- compatible : Must be "hisilicon,hip06-pcie-ecam", or
+ "hisilicon,hip07-pcie-ecam"
+
+- reg : Two entries: First the ECAM configuration space for any
+ other bus underneath the root bus. Second, the base
+ and size of the HiSilicon host bridge registers include
+ the RC's own config space.
+
+Example:
+ pcie0: pcie@a0090000 {
+ compatible = "hisilicon,hip06-pcie-ecam";
+ reg = <0 0xb0000000 0 0x2000000>, /* ECAM configuration space */
+ <0 0xa0090000 0 0x10000>; /* host bridge registers */
+ bus-range = <0 31>;
+ msi-map = <0x0000 &its_dsa 0x0000 0x2000>;
+ msi-map-mask = <0xffff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ dma-coherent;
+ ranges = <0x02000000 0 0xb2000000 0x0 0xb2000000 0 0x5ff0000
+ 0x01000000 0 0 0 0xb7ff0000 0 0x10000>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <0x0 0 0 1 &mbigen_pcie0 650 4
+ 0x0 0 0 2 &mbigen_pcie0 650 4
+ 0x0 0 0 3 &mbigen_pcie0 650 4
+ 0x0 0 0 4 &mbigen_pcie0 650 4>;
+ status = "ok";
+ };
diff --git a/Bindings/pci/mvebu-pci.txt b/Bindings/pci/mvebu-pci.txt
index 08c716b2c6b6..2de6f65ecfb1 100644
--- a/Bindings/pci/mvebu-pci.txt
+++ b/Bindings/pci/mvebu-pci.txt
@@ -78,7 +78,8 @@ and the following optional properties:
multiple lanes. If this property is not found, we assume that the
value is 0.
- reset-gpios: optional gpio to PERST#
-- reset-delay-us: delay in us to wait after reset de-assertion
+- reset-delay-us: delay in us to wait after reset de-assertion, if not
+ specified will default to 100ms, as required by the PCIe specification.
Example:
diff --git a/Bindings/pci/pci-iommu.txt b/Bindings/pci/pci-iommu.txt
index 56c829621b9a..0def586fdcdf 100644
--- a/Bindings/pci/pci-iommu.txt
+++ b/Bindings/pci/pci-iommu.txt
@@ -32,17 +32,17 @@ PCI root complex
Optional properties
-------------------
-- iommu-map: Maps a Requester ID to an IOMMU and associated iommu-specifier
+- iommu-map: Maps a Requester ID to an IOMMU and associated IOMMU specifier
data.
The property is an arbitrary number of tuples of
(rid-base,iommu,iommu-base,length).
Any RID r in the interval [rid-base, rid-base + length) is associated with
- the listed IOMMU, with the iommu-specifier (r - rid-base + iommu-base).
+ the listed IOMMU, with the IOMMU specifier (r - rid-base + iommu-base).
- iommu-map-mask: A mask to be applied to each Requester ID prior to being
- mapped to an iommu-specifier per the iommu-map property.
+ mapped to an IOMMU specifier per the iommu-map property.
Example (1)
diff --git a/Bindings/pci/rcar-pci.txt b/Bindings/pci/rcar-pci.txt
index eee518db90b9..34712d6fd253 100644
--- a/Bindings/pci/rcar-pci.txt
+++ b/Bindings/pci/rcar-pci.txt
@@ -6,6 +6,7 @@ compatible: "renesas,pcie-r8a7779" for the R8A7779 SoC;
"renesas,pcie-r8a7791" for the R8A7791 SoC;
"renesas,pcie-r8a7793" for the R8A7793 SoC;
"renesas,pcie-r8a7795" for the R8A7795 SoC;
+ "renesas,pcie-r8a7796" for the R8A7796 SoC;
"renesas,pcie-rcar-gen2" for a generic R-Car Gen2 compatible device.
"renesas,pcie-rcar-gen3" for a generic R-Car Gen3 compatible device.
diff --git a/Bindings/pci/rockchip-pcie.txt b/Bindings/pci/rockchip-pcie.txt
index 71aeda1ca055..1453a734c2f5 100644
--- a/Bindings/pci/rockchip-pcie.txt
+++ b/Bindings/pci/rockchip-pcie.txt
@@ -43,6 +43,8 @@ Required properties:
- interrupt-map-mask and interrupt-map: standard PCI properties
Optional Property:
+- aspm-no-l0s: RC won't support ASPM L0s. This property is needed if
+ using 24MHz OSC for RC's PHY.
- ep-gpios: contain the entry for pre-reset gpio
- num-lanes: number of lanes to use
- vpcie3v3-supply: The phandle to the 3.3v regulator to use for PCIe.
diff --git a/Bindings/pci/samsung,exynos5440-pcie.txt b/Bindings/pci/samsung,exynos5440-pcie.txt
index 4f9d23d2ed67..7d3b09474657 100644
--- a/Bindings/pci/samsung,exynos5440-pcie.txt
+++ b/Bindings/pci/samsung,exynos5440-pcie.txt
@@ -7,8 +7,19 @@ Required properties:
- compatible: "samsung,exynos5440-pcie"
- reg: base addresses and lengths of the pcie controller,
the phy controller, additional register for the phy controller.
+ (Registers for the phy controller are DEPRECATED.
+ Use the PHY framework.)
+- reg-names : First name should be set to "elbi".
+ And use the "config" instead of getting the confgiruation address space
+ from "ranges".
+ NOTE: When use the "config" property, reg-names must be set.
- interrupts: A list of interrupt outputs for level interrupt,
pulse interrupt, special interrupt.
+- phys: From PHY binding. Phandle for the Generic PHY.
+ Refer to Documentation/devicetree/bindings/phy/samsung-phy.txt
+
+Other common properties refer to
+ Documentation/devicetree/binding/pci/designware-pcie.txt
Example:
@@ -54,6 +65,24 @@ SoC specific DT Entry:
num-lanes = <4>;
};
+With using PHY framework:
+ pcie_phy0: pcie-phy@270000 {
+ ...
+ reg = <0x270000 0x1000>, <0x271000 0x40>;
+ reg-names = "phy", "block";
+ ...
+ };
+
+ pcie@290000 {
+ ...
+ reg = <0x290000 0x1000>, <0x40000000 0x1000>;
+ reg-names = "elbi", "config";
+ phys = <&pcie_phy0>;
+ ranges = <0x81000000 0 0 0x60001000 0 0x00010000
+ 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>;
+ ...
+ };
+
Board specific DT Entry:
pcie@290000 {
diff --git a/Bindings/phy/qcom,usb-hs-phy.txt b/Bindings/phy/qcom,usb-hs-phy.txt
new file mode 100644
index 000000000000..b3b75c1e6285
--- /dev/null
+++ b/Bindings/phy/qcom,usb-hs-phy.txt
@@ -0,0 +1,84 @@
+Qualcomm's USB HS PHY
+
+PROPERTIES
+
+- compatible:
+ Usage: required
+ Value type: <string>
+ Definition: Should contain "qcom,usb-hs-phy" and more specifically one of the
+ following:
+
+ "qcom,usb-hs-phy-apq8064"
+ "qcom,usb-hs-phy-msm8916"
+ "qcom,usb-hs-phy-msm8974"
+
+- #phy-cells:
+ Usage: required
+ Value type: <u32>
+ Definition: Should contain 0
+
+- clocks:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: Should contain clock specifier for the reference and sleep
+ clocks
+
+- clock-names:
+ Usage: required
+ Value type: <stringlist>
+ Definition: Should contain "ref" and "sleep" for the reference and sleep
+ clocks respectively
+
+- resets:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: Should contain the phy and POR resets
+
+- reset-names:
+ Usage: required
+ Value type: <stringlist>
+ Definition: Should contain "phy" and "por" for the phy and POR resets
+ respectively
+
+- v3p3-supply:
+ Usage: required
+ Value type: <phandle>
+ Definition: Should contain a reference to the 3.3V supply
+
+- v1p8-supply:
+ Usage: required
+ Value type: <phandle>
+ Definition: Should contain a reference to the 1.8V supply
+
+- extcon:
+ Usage: optional
+ Value type: <prop-encoded-array>
+ Definition: Should contain the vbus extcon
+
+- qcom,init-seq:
+ Usage: optional
+ Value type: <u8 array>
+ Definition: Should contain a sequence of ULPI address and value pairs to
+ program into the ULPI_EXT_VENDOR_SPECIFIC area. This is related
+ to Device Mode Eye Diagram test. The addresses are offsets
+ from the ULPI_EXT_VENDOR_SPECIFIC address, for example,
+ <0x1 0x53> would mean "write the value 0x53 to address 0x81".
+
+EXAMPLE
+
+otg: usb-controller {
+ ulpi {
+ phy {
+ compatible = "qcom,usb-hs-phy-msm8974", "qcom,usb-hs-phy";
+ #phy-cells = <0>;
+ clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
+ clock-names = "ref", "sleep";
+ resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>;
+ reset-names = "phy", "por";
+ v3p3-supply = <&pm8941_l24>;
+ v1p8-supply = <&pm8941_l6>;
+ extcon = <&smbb>;
+ qcom,init-seq = /bits/ 8 <0x1 0x63>;
+ };
+ };
+};
diff --git a/Bindings/phy/qcom,usb-hsic-phy.txt b/Bindings/phy/qcom,usb-hsic-phy.txt
new file mode 100644
index 000000000000..3c7cb2be4b12
--- /dev/null
+++ b/Bindings/phy/qcom,usb-hsic-phy.txt
@@ -0,0 +1,65 @@
+Qualcomm's USB HSIC PHY
+
+PROPERTIES
+
+- compatible:
+ Usage: required
+ Value type: <string>
+ Definition: Should contain "qcom,usb-hsic-phy" and more specifically one of the
+ following:
+
+ "qcom,usb-hsic-phy-mdm9615"
+ "qcom,usb-hsic-phy-msm8974"
+
+- #phy-cells:
+ Usage: required
+ Value type: <u32>
+ Definition: Should contain 0
+
+- clocks:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: Should contain clock specifier for phy, calibration and
+ a calibration sleep clock
+
+- clock-names:
+ Usage: required
+ Value type: <stringlist>
+ Definition: Should contain "phy, "cal" and "cal_sleep"
+
+- pinctrl-names:
+ Usage: required
+ Value type: <stringlist>
+ Definition: Should contain "init" and "default" in that order
+
+- pinctrl-0:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: List of pinctrl settings to apply to keep HSIC pins in a glitch
+ free state
+
+- pinctrl-1:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: List of pinctrl settings to apply to mux out the HSIC pins
+
+EXAMPLE
+
+usb-controller {
+ ulpi {
+ phy {
+ compatible = "qcom,usb-hsic-phy-msm8974",
+ "qcom,usb-hsic-phy";
+ #phy-cells = <0>;
+ pinctrl-names = "init", "default";
+ pinctrl-0 = <&hsic_sleep>;
+ pinctrl-1 = <&hsic_default>;
+ clocks = <&gcc GCC_USB_HSIC_CLK>,
+ <&gcc GCC_USB_HSIC_IO_CAL_CLK>,
+ <&gcc GCC_USB_HSIC_IO_CAL_SLEEP_CLK>;
+ clock-names = "phy", "cal", "cal_sleep";
+ assigned-clocks = <&gcc GCC_USB_HSIC_IO_CAL_CLK>;
+ assigned-clock-rates = <960000>;
+ };
+ };
+};
diff --git a/Bindings/phy/samsung-phy.txt b/Bindings/phy/samsung-phy.txt
index 9872ba8546bd..ab80bfe31cb3 100644
--- a/Bindings/phy/samsung-phy.txt
+++ b/Bindings/phy/samsung-phy.txt
@@ -191,3 +191,20 @@ Example:
usbdrdphy0 = &usb3_phy0;
usbdrdphy1 = &usb3_phy1;
};
+
+Samsung Exynos SoC series PCIe PHY controller
+--------------------------------------------------
+Required properties:
+- compatible : Should be set to "samsung,exynos5440-pcie-phy"
+- #phy-cells : Must be zero
+- reg : a register used by phy driver.
+ - First is for phy register, second is for block register.
+- reg-names : Must be set to "phy" and "block".
+
+Example:
+ pcie_phy0: pcie-phy@270000 {
+ #phy-cells = <0>;
+ compatible = "samsung,exynos5440-pcie-phy";
+ reg = <0x270000 0x1000>, <0x271000 0x40>;
+ reg-names = "phy", "block";
+ };
diff --git a/Bindings/phy/sun4i-usb-phy.txt b/Bindings/phy/sun4i-usb-phy.txt
index 287150db6db4..e42334258185 100644
--- a/Bindings/phy/sun4i-usb-phy.txt
+++ b/Bindings/phy/sun4i-usb-phy.txt
@@ -10,6 +10,7 @@ Required properties:
* allwinner,sun8i-a23-usb-phy
* allwinner,sun8i-a33-usb-phy
* allwinner,sun8i-h3-usb-phy
+ * allwinner,sun8i-v3s-usb-phy
* allwinner,sun50i-a64-usb-phy
- reg : a list of offset + length pairs
- reg-names :
diff --git a/Bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index de1378b4efad..2fd688c8dbdb 100644
--- a/Bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/Bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -6,7 +6,7 @@ the first two functions being GPIO in and out. The configuration on
the pins includes drive strength and pull-up.
Required properties:
-- compatible: Should be one of the followings (depending on you SoC):
+- compatible: Should be one of the following (depending on your SoC):
"allwinner,sun4i-a10-pinctrl"
"allwinner,sun5i-a10s-pinctrl"
"allwinner,sun5i-a13-pinctrl"
@@ -23,6 +23,7 @@ Required properties:
"allwinner,sun8i-h3-pinctrl"
"allwinner,sun8i-h3-r-pinctrl"
"allwinner,sun50i-a64-pinctrl"
+ "allwinner,sun50i-h5-r-pinctrl"
"nextthing,gr8-pinctrl"
- reg: Should contain the register physical address and length for the
diff --git a/Bindings/pinctrl/fsl,imx7d-pinctrl.txt b/Bindings/pinctrl/fsl,imx7d-pinctrl.txt
index 457b2c68d47b..8c5d27c5b562 100644
--- a/Bindings/pinctrl/fsl,imx7d-pinctrl.txt
+++ b/Bindings/pinctrl/fsl,imx7d-pinctrl.txt
@@ -19,7 +19,7 @@ iomuxc: iomuxc@30330000 {
reg = <0x30330000 0x10000>;
};
-Pheriparials using pads from iomuxc-lpsr support low state retention power
+Peripherals using pads from iomuxc-lpsr support low state retention power
state, under LPSR mode GPIO's state of pads are retain.
Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
diff --git a/Bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt b/Bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
new file mode 100644
index 000000000000..97aef67ee769
--- /dev/null
+++ b/Bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
@@ -0,0 +1,46 @@
+* Marvell 98dx3236 pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage
+
+Required properties:
+- compatible: "marvell,98dx3236-pinctrl" or "marvell,98dx4251-pinctrl"
+- reg: register specifier of MPP registers
+
+This driver supports all 98dx3236, 98dx3336 and 98dx4251 variants
+
+name pins functions
+================================================================================
+mpp0 0 gpo, spi0(mosi), dev(ad8)
+mpp1 1 gpio, spi0(miso), dev(ad9)
+mpp2 2 gpo, spi0(sck), dev(ad10)
+mpp3 3 gpio, spi0(cs0), dev(ad11)
+mpp4 4 gpio, spi0(cs1), smi(mdc), dev(cs0)
+mpp5 5 gpio, pex(rsto), sd0(cmd), dev(bootcs)
+mpp6 6 gpo, sd0(clk), dev(a2)
+mpp7 7 gpio, sd0(d0), dev(ale0)
+mpp8 8 gpio, sd0(d1), dev(ale1)
+mpp9 9 gpio, sd0(d2), dev(ready0)
+mpp10 10 gpio, sd0(d3), dev(ad12)
+mpp11 11 gpio, uart1(rxd), uart0(cts), dev(ad13)
+mpp12 12 gpo, uart1(txd), uart0(rts), dev(ad14)
+mpp13 13 gpio, intr(out), dev(ad15)
+mpp14 14 gpio, i2c0(sck)
+mpp15 15 gpio, i2c0(sda)
+mpp16 16 gpo, dev(oe)
+mpp17 17 gpo, dev(clkout)
+mpp18 18 gpio, uart1(txd)
+mpp19 19 gpio, uart1(rxd), dev(rb)
+mpp20 20 gpo, dev(we0)
+mpp21 21 gpo, dev(ad0)
+mpp22 22 gpo, dev(ad1)
+mpp23 23 gpo, dev(ad2)
+mpp24 24 gpo, dev(ad3)
+mpp25 25 gpo, dev(ad4)
+mpp26 26 gpo, dev(ad5)
+mpp27 27 gpo, dev(ad6)
+mpp28 28 gpo, dev(ad7)
+mpp29 29 gpo, dev(a0)
+mpp30 30 gpo, dev(a1)
+mpp31 31 gpio, slv_smi(mdc), smi(mdc), dev(we1)
+mpp32 32 gpio, slv_smi(mdio), smi(mdio), dev(cs1)
diff --git a/Bindings/pinctrl/marvell,kirkwood-pinctrl.txt b/Bindings/pinctrl/marvell,kirkwood-pinctrl.txt
index 730444a9a4de..6c0ea155b708 100644
--- a/Bindings/pinctrl/marvell,kirkwood-pinctrl.txt
+++ b/Bindings/pinctrl/marvell,kirkwood-pinctrl.txt
@@ -44,16 +44,16 @@ mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs)
mpp17 17 gpio, sdio(d3)
mpp18 18 gpo, nand(io0)
mpp19 19 gpo, nand(io1)
-mpp20 20 gpio, mii(rxerr)
-mpp21 21 gpio, audio(spdifi)
-mpp22 22 gpio, audio(spdifo)
-mpp23 23 gpio, audio(rmclk)
-mpp24 24 gpio, audio(bclk)
-mpp25 25 gpio, audio(sdo)
-mpp26 26 gpio, audio(lrclk)
-mpp27 27 gpio, audio(mclk)
-mpp28 28 gpio, audio(sdi)
-mpp29 29 gpio, audio(extclk)
+mpp35 35 gpio, mii(rxerr)
+mpp36 36 gpio, audio(spdifi)
+mpp37 37 gpio, audio(spdifo)
+mpp38 38 gpio, audio(rmclk)
+mpp39 39 gpio, audio(bclk)
+mpp40 40 gpio, audio(sdo)
+mpp41 41 gpio, audio(lrclk)
+mpp42 42 gpio, audio(mclk)
+mpp43 43 gpio, audio(sdi)
+mpp44 44 gpio, audio(extclk)
* Marvell Kirkwood 88f6190
diff --git a/Bindings/pinctrl/pinctrl-aspeed.txt b/Bindings/pinctrl/pinctrl-aspeed.txt
index 2ad18c4ea55c..b98e6f030da8 100644
--- a/Bindings/pinctrl/pinctrl-aspeed.txt
+++ b/Bindings/pinctrl/pinctrl-aspeed.txt
@@ -1,25 +1,38 @@
+======================
Aspeed Pin Controllers
-----------------------
+======================
The Aspeed SoCs vary in functionality inside a generation but have a common mux
device register layout.
-Required properties:
-- compatible : Should be any one of the following:
- "aspeed,ast2400-pinctrl"
- "aspeed,g4-pinctrl"
- "aspeed,ast2500-pinctrl"
- "aspeed,g5-pinctrl"
+Required properties for g4:
+- compatible : Should be one of the following:
+ "aspeed,ast2400-pinctrl"
+ "aspeed,g4-pinctrl"
-The pin controller node should be a child of a syscon node with the required
+Required properties for g5:
+- compatible : Should be one of the following:
+ "aspeed,ast2500-pinctrl"
+ "aspeed,g5-pinctrl"
+
+- aspeed,external-nodes: A cell of phandles to external controller nodes:
+ 0: compatible with "aspeed,ast2500-gfx", "syscon"
+ 1: compatible with "aspeed,ast2500-lhc", "syscon"
+
+The pin controller node should be the child of a syscon node with the required
property:
-- compatible: "syscon", "simple-mfd"
+
+- compatible : Should be one of the following:
+ "aspeed,ast2400-scu", "syscon", "simple-mfd"
+ "aspeed,g4-scu", "syscon", "simple-mfd"
+ "aspeed,ast2500-scu", "syscon", "simple-mfd"
+ "aspeed,g5-scu", "syscon", "simple-mfd"
Refer to the the bindings described in
Documentation/devicetree/bindings/mfd/syscon.txt
Subnode Format
---------------
+==============
The required properties of child nodes are (as defined in pinctrl-bindings):
- function
@@ -31,26 +44,43 @@ supported:
aspeed,ast2400-pinctrl, aspeed,g4-pinctrl:
-ACPI BMCINT DDCCLK DDCDAT FLACK FLBUSY FLWP GPID0 GPIE0 GPIE2 GPIE4 GPIE6 I2C10
-I2C11 I2C12 I2C13 I2C3 I2C4 I2C5 I2C6 I2C7 I2C8 I2C9 LPCPD LPCPME LPCSMI MDIO1
-MDIO2 NCTS1 NCTS3 NCTS4 NDCD1 NDCD3 NDCD4 NDSR1 NDSR3 NDTR1 NDTR3 NRI1 NRI3
-NRI4 NRTS1 NRTS3 PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 RGMII1 RMII1 ROM16
-ROM8 ROMCS1 ROMCS2 ROMCS3 ROMCS4 RXD1 RXD3 RXD4 SD1 SGPMI SIOPBI SIOPBO TIMER3
-TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD3 TXD4 UART6 VGAHS VGAVS VPI18 VPI24 VPI30
-VPO12 VPO24
+ACPI ADC0 ADC1 ADC10 ADC11 ADC12 ADC13 ADC14 ADC15 ADC2 ADC3 ADC4 ADC5 ADC6
+ADC7 ADC8 ADC9 BMCINT DDCCLK DDCDAT EXTRST FLACK FLBUSY FLWP GPID GPID0 GPID2
+GPID4 GPID6 GPIE0 GPIE2 GPIE4 GPIE6 I2C10 I2C11 I2C12 I2C13 I2C14 I2C3 I2C4
+I2C5 I2C6 I2C7 I2C8 I2C9 LPCPD LPCPME LPCRST LPCSMI MAC1LINK MAC2LINK MDIO1
+MDIO2 NCTS1 NCTS2 NCTS3 NCTS4 NDCD1 NDCD2 NDCD3 NDCD4 NDSR1 NDSR2 NDSR3 NDSR4
+NDTR1 NDTR2 NDTR3 NDTR4 NDTS4 NRI1 NRI2 NRI3 NRI4 NRTS1 NRTS2 NRTS3 OSCCLK PWM0
+PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 RGMII1 RGMII2 RMII1 RMII2 ROM16 ROM8 ROMCS1
+ROMCS2 ROMCS3 ROMCS4 RXD1 RXD2 RXD3 RXD4 SALT1 SALT2 SALT3 SALT4 SD1 SD2 SGPMCK
+SGPMI SGPMLD SGPMO SGPSCK SGPSI0 SGPSI1 SGPSLD SIOONCTRL SIOPBI SIOPBO SIOPWREQ
+SIOPWRGD SIOS3 SIOS5 SIOSCI SPI1 SPI1DEBUG SPI1PASSTHRU SPICS1 TIMER3 TIMER4
+TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2 TXD3 TXD4 UART6 USBCKI VGABIOS_ROM VGAHS
+VGAVS VPI18 VPI24 VPI30 VPO12 VPO24 WDTRST1 WDTRST2
aspeed,ast2500-pinctrl, aspeed,g5-pinctrl:
-GPID0 GPID2 GPIE0 I2C10 I2C11 I2C12 I2C13 I2C14 I2C3 I2C4 I2C5 I2C6 I2C7 I2C8
-I2C9 MAC1LINK MDIO1 MDIO2 OSCCLK PEWAKE PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7
-RGMII1 RGMII2 RMII1 RMII2 SD1 SPI1 SPI1DEBUG SPI1PASSTHRU TIMER4 TIMER5 TIMER6
-TIMER7 TIMER8 VGABIOSROM
-
-
-Examples:
+ACPI ADC0 ADC1 ADC10 ADC11 ADC12 ADC13 ADC14 ADC15 ADC2 ADC3 ADC4 ADC5 ADC6
+ADC7 ADC8 ADC9 BMCINT DDCCLK DDCDAT ESPI FWSPICS1 FWSPICS2 GPID0 GPID2 GPID4
+GPID6 GPIE0 GPIE2 GPIE4 GPIE6 I2C10 I2C11 I2C12 I2C13 I2C14 I2C3 I2C4 I2C5 I2C6
+I2C7 I2C8 I2C9 LAD0 LAD1 LAD2 LAD3 LCLK LFRAME LPCHC LPCPD LPCPLUS LPCPME
+LPCRST LPCSMI LSIRQ MAC1LINK MAC2LINK MDIO1 MDIO2 NCTS1 NCTS2 NCTS3 NCTS4 NDCD1
+NDCD2 NDCD3 NDCD4 NDSR1 NDSR2 NDSR3 NDSR4 NDTR1 NDTR2 NDTR3 NDTR4 NRI1 NRI2
+NRI3 NRI4 NRTS1 NRTS2 NRTS3 NRTS4 OSCCLK PEWAKE PNOR PWM0 PWM1 PWM2 PWM3 PWM4
+PWM5 PWM6 PWM7 RGMII1 RGMII2 RMII1 RMII2 RXD1 RXD2 RXD3 RXD4 SALT1 SALT10
+SALT11 SALT12 SALT13 SALT14 SALT2 SALT3 SALT4 SALT5 SALT6 SALT7 SALT8 SALT9
+SCL1 SCL2 SD1 SD2 SDA1 SDA2 SGPS1 SGPS2 SIOONCTRL SIOPBI SIOPBO SIOPWREQ
+SIOPWRGD SIOS3 SIOS5 SIOSCI SPI1 SPI1CS1 SPI1DEBUG SPI1PASSTHRU SPI2CK SPI2CS0
+SPI2CS1 SPI2MISO SPI2MOSI TIMER3 TIMER4 TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2
+TXD3 TXD4 UART6 USBCKI VGABIOSROM VGAHS VGAVS VPI24 VPO WDTRST1 WDTRST2
+
+Examples
+========
+
+g4 Example
+----------
syscon: scu@1e6e2000 {
- compatible = "syscon", "simple-mfd";
+ compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd";
reg = <0x1e6e2000 0x1a8>;
pinctrl: pinctrl {
@@ -63,5 +93,56 @@ syscon: scu@1e6e2000 {
};
};
+g5 Example
+----------
+
+ahb {
+ apb {
+ syscon: scu@1e6e2000 {
+ compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd";
+ reg = <0x1e6e2000 0x1a8>;
+
+ pinctrl: pinctrl {
+ compatible = "aspeed,g5-pinctrl";
+ aspeed,external-nodes = <&gfx &lhc>;
+
+ pinctrl_i2c3_default: i2c3_default {
+ function = "I2C3";
+ groups = "I2C3";
+ };
+ };
+ };
+
+ gfx: display@1e6e6000 {
+ compatible = "aspeed,ast2500-gfx", "syscon";
+ reg = <0x1e6e6000 0x1000>;
+ };
+ };
+
+ lpc: lpc@1e789000 {
+ compatible = "aspeed,ast2500-lpc", "simple-mfd";
+ reg = <0x1e789000 0x1000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x1e789000 0x1000>;
+
+ lpc_host: lpc-host@80 {
+ compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
+ reg = <0x80 0x1e0>;
+ reg-io-width = <4>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x80 0x1e0>;
+
+ lhc: lhc@20 {
+ compatible = "aspeed,ast2500-lhc";
+ reg = <0x20 0x24 0x48 0x8>;
+ };
+ };
+ };
+};
+
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices.
diff --git a/Bindings/pinctrl/samsung-pinctrl.txt b/Bindings/pinctrl/samsung-pinctrl.txt
index 1baf19eecabf..5e00a21de2bf 100644
--- a/Bindings/pinctrl/samsung-pinctrl.txt
+++ b/Bindings/pinctrl/samsung-pinctrl.txt
@@ -13,6 +13,7 @@ Required Properties:
- "samsung,s3c2450-pinctrl": for S3C2450-compatible pin-controller,
- "samsung,s3c64xx-pinctrl": for S3C64xx-compatible pin-controller,
- "samsung,s5pv210-pinctrl": for S5PV210-compatible pin-controller,
+ - "samsung,exynos3250-pinctrl": for Exynos3250 compatible pin-controller.
- "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller.
- "samsung,exynos4x12-pinctrl": for Exynos4x12 compatible pin-controller.
- "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller.
diff --git a/Bindings/pinctrl/st,stm32-pinctrl.txt b/Bindings/pinctrl/st,stm32-pinctrl.txt
index b24583aa34c3..eac20aa33907 100644
--- a/Bindings/pinctrl/st,stm32-pinctrl.txt
+++ b/Bindings/pinctrl/st,stm32-pinctrl.txt
@@ -8,8 +8,9 @@ controllers onto these pads.
Pin controller node:
Required properies:
- compatible: value should be one of the following:
- (a) "st,stm32f429-pinctrl"
- (b) "st,stm32f746-pinctrl"
+ "st,stm32f429-pinctrl"
+ "st,stm32f746-pinctrl"
+ "st,stm32h743-pinctrl"
- #address-cells: The value of this property must be 1
- #size-cells : The value of this property must be 1
- ranges : defines mapping between pin controller node (parent) to
@@ -37,8 +38,23 @@ Optional properties:
- st,syscfg: Should be phandle/offset pair. The phandle to the syscon node
which includes IRQ mux selection register, and the offset of the IRQ mux
selection register.
+ - ngpios: Number of gpios in a bank (to use if bank gpio numbers is less
+ than 16).
+ - gpio-ranges: Define a dedicated mapping between a pin-controller and
+ a gpio controller. Format is <&phandle a b c> with:
+ -(phandle): phandle of pin-controller.
+ -(a): gpio base offset in range.
+ -(b): pin base offset in range.
+ -(c): gpio count in range
+ This entry has to be used either if there are holes inside a bank:
+ GPIOB0/B1/B2/B14/B15 (see example 2)
+ or if banks are not contiguous:
+ GPIOA/B/C/E...
+ NOTE: If "gpio-ranges" is used for a gpio controller, all gpio-controller
+ have to use a "gpio-ranges" entry.
+ More details in Documentation/devicetree/bindings/gpio/gpio.txt.
-Example:
+Example 1:
#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
...
@@ -60,6 +76,43 @@ Example:
pin-functions nodes follow...
};
+Example 2:
+#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
+...
+
+ pinctrl: pin-controller {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stm32f429-pinctrl";
+ ranges = <0 0x40020000 0x3000>;
+ pins-are-numbered;
+
+ gpioa: gpio@40020000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x0 0x400>;
+ resets = <&reset_ahb1 0>;
+ st,bank-name = "GPIOA";
+ gpio-ranges = <&pinctrl 0 0 16>;
+ };
+
+ gpiob: gpio@40020400 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x0 0x400>;
+ resets = <&reset_ahb1 0>;
+ st,bank-name = "GPIOB";
+ ngpios = 4;
+ gpio-ranges = <&pinctrl 0 16 3>,
+ <&pinctrl 14 30 2>;
+ };
+
+
+ ...
+ pin-functions nodes follow...
+ };
+
+
Contents of function subnode node:
----------------------------------
Subnode format
diff --git a/Bindings/pinctrl/ti,iodelay.txt b/Bindings/pinctrl/ti,iodelay.txt
new file mode 100644
index 000000000000..c3ed1232b6a3
--- /dev/null
+++ b/Bindings/pinctrl/ti,iodelay.txt
@@ -0,0 +1,47 @@
+* Pin configuration for TI IODELAY controller
+
+TI dra7 based SoCs such as am57xx have a controller for setting the IO delay
+for each pin. For most part the IO delay values are programmed by the bootloader,
+but some pins need to be configured dynamically by the kernel such as the
+MMC pins.
+
+Required Properties:
+
+ - compatible: Must be "ti,dra7-iodelay"
+ - reg: Base address and length of the memory resource used
+ - #address-cells: Number of address cells
+ - #size-cells: Size of cells
+ - #pinctrl-cells: Number of pinctrl cells, must be 2. See also
+ Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
+
+Example
+-------
+
+In the SoC specific dtsi file:
+
+ dra7_iodelay_core: padconf@4844a000 {
+ compatible = "ti,dra7-iodelay";
+ reg = <0x4844a000 0x0d1c>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #pinctrl-cells = <2>;
+ };
+
+In board-specific file:
+
+&dra7_iodelay_core {
+ mmc2_iodelay_3v3_conf: mmc2_iodelay_3v3_conf {
+ pinctrl-pin-array = <
+ 0x18c A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A19_IN */
+ 0x1a4 A_DELAY_PS(265) G_DELAY_PS(360) /* CFG_GPMC_A20_IN */
+ 0x1b0 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A21_IN */
+ 0x1bc A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A22_IN */
+ 0x1c8 A_DELAY_PS(287) G_DELAY_PS(420) /* CFG_GPMC_A23_IN */
+ 0x1d4 A_DELAY_PS(144) G_DELAY_PS(240) /* CFG_GPMC_A24_IN */
+ 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */
+ 0x1ec A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A26_IN */
+ 0x1f8 A_DELAY_PS(120) G_DELAY_PS(180) /* CFG_GPMC_A27_IN */
+ 0x360 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_IN */
+ >;
+ };
+};
diff --git a/Bindings/power/act8945a-charger.txt b/Bindings/power/act8945a-charger.txt
deleted file mode 100644
index bea254c9d136..000000000000
--- a/Bindings/power/act8945a-charger.txt
+++ /dev/null
@@ -1,35 +0,0 @@
-Device-Tree bindings for charger of Active-semi ACT8945A Multi-Function Device
-
-Required properties:
- - compatible: "active-semi,act8945a", please refer to ../mfd/act8945a.txt.
- - active-semi,chglev-gpios: charge current level phandle with args
- as described in ../gpio/gpio.txt.
-
-Optional properties:
- - active-semi,check-battery-temperature: boolean to check the battery
- temperature or not.
- - active-semi,input-voltage-threshold-microvolt: unit: mV;
- Specifies the charger's input over-voltage threshold value;
- The value can be: 6600, 7000, 7500, 8000; default: 6600
- - active-semi,precondition-timeout: unit: minutes;
- Specifies the charger's PRECONDITION safety timer setting value;
- The value can be: 40, 60, 80, 0; If 0, it means to disable this timer;
- default: 40.
- - active-semi,total-timeout: unit: hours;
- Specifies the charger's total safety timer setting value;
- The value can be: 3, 4, 5, 0; If 0, it means to disable this timer;
- default: 3.
-
-Example:
- pmic@5b {
- compatible = "active-semi,act8945a";
- reg = <0x5b>;
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_charger_chglev>;
- active-semi,chglev-gpios = <&pioA 12 GPIO_ACTIVE_HIGH>;
- active-semi,input-voltage-threshold-microvolt = <6600>;
- active-semi,precondition-timeout = <40>;
- active-semi,total-timeout = <3>;
- };
diff --git a/Bindings/power/bq2415x.txt b/Bindings/power/bq2415x.txt
deleted file mode 100644
index d0327f0b59ad..000000000000
--- a/Bindings/power/bq2415x.txt
+++ /dev/null
@@ -1,47 +0,0 @@
-Binding for TI bq2415x Li-Ion Charger
-
-Required properties:
-- compatible: Should contain one of the following:
- * "ti,bq24150"
- * "ti,bq24150"
- * "ti,bq24150a"
- * "ti,bq24151"
- * "ti,bq24151a"
- * "ti,bq24152"
- * "ti,bq24153"
- * "ti,bq24153a"
- * "ti,bq24155"
- * "ti,bq24156"
- * "ti,bq24156a"
- * "ti,bq24158"
-- reg: integer, i2c address of the device.
-- ti,current-limit: integer, initial maximum current charger can pull
- from power supply in mA.
-- ti,weak-battery-voltage: integer, weak battery voltage threshold in mV.
- The chip will use slow precharge if battery voltage
- is below this value.
-- ti,battery-regulation-voltage: integer, maximum charging voltage in mV.
-- ti,charge-current: integer, maximum charging current in mA.
-- ti,termination-current: integer, charge will be terminated when current in
- constant-voltage phase drops below this value (in mA).
-- ti,resistor-sense: integer, value of sensing resistor in milliohm.
-
-Optional properties:
-- ti,usb-charger-detection: phandle to usb charger detection device.
- (required for auto mode)
-
-Example from Nokia N900:
-
-bq24150a {
- compatible = "ti,bq24150a";
- reg = <0x6b>;
-
- ti,current-limit = <100>;
- ti,weak-battery-voltage = <3400>;
- ti,battery-regulation-voltage = <4200>;
- ti,charge-current = <650>;
- ti,termination-current = <100>;
- ti,resistor-sense = <68>;
-
- ti,usb-charger-detection = <&isp1704>;
-};
diff --git a/Bindings/power/bq24257.txt b/Bindings/power/bq24257.txt
deleted file mode 100644
index d693702c9c1e..000000000000
--- a/Bindings/power/bq24257.txt
+++ /dev/null
@@ -1,64 +0,0 @@
-Binding for TI bq24250/bq24251/bq24257 Li-Ion Charger
-
-Required properties:
-- compatible: Should contain one of the following:
- * "ti,bq24250"
- * "ti,bq24251"
- * "ti,bq24257"
-- reg: integer, i2c address of the device.
-- interrupt-parent: Should be the phandle for the interrupt controller. Use in
- conjunction with "interrupts".
-- interrupts: Interrupt mapping for GPIO IRQ (configure for both edges). Use in
- conjunction with "interrupt-parent".
-- ti,battery-regulation-voltage: integer, maximum charging voltage in uV.
-- ti,charge-current: integer, maximum charging current in uA.
-- ti,termination-current: integer, charge will be terminated when current in
- constant-voltage phase drops below this value (in uA).
-
-Optional properties:
-- pg-gpios: GPIO used for connecting the bq2425x device PG (Power Good) pin.
- This pin is not available on all devices however it should be used if
- possible as this is the recommended way to obtain the charger's input PG
- state. If this pin is not specified a software-based approach for PG
- detection is used.
-- ti,current-limit: The maximum current to be drawn from the charger's input
- (in uA). If this property is not specified, the input limit current is
- set automatically using USB D+/D- signal based charger type detection.
- If the hardware does not support the D+/D- based detection, a default
- of 500,000 is used (=500mA) instead.
-- ti,ovp-voltage: Configures the over voltage protection voltage (in uV). If
- not specified a default of 6,5000,000 (=6.5V) is used.
-- ti,in-dpm-voltage: Configures the threshold input voltage for the dynamic
- power path management (in uV). If not specified a default of 4,360,000
- (=4.36V) is used.
-
-Example:
-
-bq24257 {
- compatible = "ti,bq24257";
- reg = <0x6a>;
- interrupt-parent = <&gpio1>;
- interrupts = <16 IRQ_TYPE_EDGE_BOTH>;
-
- pg-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
-
- ti,battery-regulation-voltage = <4200000>;
- ti,charge-current = <1000000>;
- ti,termination-current = <50000>;
-};
-
-Example:
-
-bq24250 {
- compatible = "ti,bq24250";
- reg = <0x6a>;
- interrupt-parent = <&gpio1>;
- interrupts = <16 IRQ_TYPE_EDGE_BOTH>;
-
- ti,battery-regulation-voltage = <4200000>;
- ti,charge-current = <500000>;
- ti,termination-current = <50000>;
- ti,current-limit = <900000>;
- ti,ovp-voltage = <9500000>;
- ti,in-dpm-voltage = <4440000>;
-};
diff --git a/Bindings/power/bq25890.txt b/Bindings/power/bq25890.txt
deleted file mode 100644
index c9dd17d142ad..000000000000
--- a/Bindings/power/bq25890.txt
+++ /dev/null
@@ -1,46 +0,0 @@
-Binding for TI bq25890 Li-Ion Charger
-
-Required properties:
-- compatible: Should contain one of the following:
- * "ti,bq25890"
-- reg: integer, i2c address of the device.
-- ti,battery-regulation-voltage: integer, maximum charging voltage (in uV);
-- ti,charge-current: integer, maximum charging current (in uA);
-- ti,termination-current: integer, charge will be terminated when current in
- constant-voltage phase drops below this value (in uA);
-- ti,precharge-current: integer, maximum charge current during precharge
- phase (in uA);
-- ti,minimum-sys-voltage: integer, when battery is charging and it is below
- minimum system voltage, the system will be regulated above
- minimum-sys-voltage setting (in uV);
-- ti,boost-voltage: integer, VBUS voltage level in boost mode (in uV);
-- ti,boost-max-current: integer, maximum allowed current draw in boost mode
- (in uA).
-
-Optional properties:
-- ti,boost-low-freq: boolean, if present boost mode frequency will be 500kHz,
- otherwise 1.5MHz;
-- ti,use-ilim-pin: boolean, if present the ILIM resistor will be used and the
- input current will be the lower between the resistor setting and the IINLIM
- register setting;
-- ti,thermal-regulation-threshold: integer, temperature above which the charge
- current is lowered, to avoid overheating (in degrees Celsius). If omitted,
- the default setting will be used (120 degrees);
-
-Example:
-
-bq25890 {
- compatible = "ti,bq25890";
- reg = <0x6a>;
-
- ti,battery-regulation-voltage = <4200000>;
- ti,charge-current = <1000000>;
- ti,termination-current = <50000>;
- ti,precharge-current = <128000>;
- ti,minimum-sys-voltage = <3600000>;
- ti,boost-voltage = <5000000>;
- ti,boost-max-current = <1000000>;
-
- ti,use-ilim-pin;
- ti,thermal-regulation-threshold = <120>;
-};
diff --git a/Bindings/power/da9150-charger.txt b/Bindings/power/da9150-charger.txt
deleted file mode 100644
index f3906663c454..000000000000
--- a/Bindings/power/da9150-charger.txt
+++ /dev/null
@@ -1,26 +0,0 @@
-Dialog Semiconductor DA9150 Charger Power Supply bindings
-
-Required properties:
-- compatible: "dlg,da9150-charger" for DA9150 Charger Power Supply
-
-Optional properties:
-- io-channels: List of phandle and IIO specifier pairs
-- io-channel-names: List of channel names used by charger
- ["CHAN_IBUS", "CHAN_VBUS", "CHAN_TJUNC", "CHAN_VBAT"]
- (See Documentation/devicetree/bindings/iio/iio-bindings.txt for further info)
-
-
-Example:
-
- da9150-charger {
- compatible = "dlg,da9150-charger";
-
- io-channels = <&gpadc 0>,
- <&gpadc 2>,
- <&gpadc 8>,
- <&gpadc 5>;
- io-channel-names = "CHAN_IBUS",
- "CHAN_VBUS",
- "CHAN_TJUNC",
- "CHAN_VBAT";
- };
diff --git a/Bindings/power/da9150-fg.txt b/Bindings/power/da9150-fg.txt
deleted file mode 100644
index 00236fe3ea31..000000000000
--- a/Bindings/power/da9150-fg.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-Dialog Semiconductor DA9150 Fuel-Gauge Power Supply bindings
-
-Required properties:
-- compatible: "dlg,da9150-fuel-gauge" for DA9150 Fuel-Gauge Power Supply
-
-Optional properties:
-- dlg,update-interval: Interval time (milliseconds) between battery level checks.
-- dlg,warn-soc-level: Battery discharge level (%) where warning event raised.
- [1 - 100]
-- dlg,crit-soc-level: Battery discharge level (%) where critical event raised.
- This value should be lower than the warning level.
- [1 - 100]
-
-
-Example:
-
- fuel-gauge {
- compatible = "dlg,da9150-fuel-gauge";
-
- dlg,update-interval = <10000>;
- dlg,warn-soc-level = /bits/ 8 <15>;
- dlg,crit-soc-level = /bits/ 8 <5>;
- };
diff --git a/Bindings/power/isp1704.txt b/Bindings/power/isp1704.txt
deleted file mode 100644
index fa3596907967..000000000000
--- a/Bindings/power/isp1704.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-Binding for NXP ISP1704 USB Charger Detection
-
-Required properties:
-- compatible: Should contain one of the following:
- * "nxp,isp1704"
-- nxp,enable-gpio: Should contain a phandle + gpio-specifier
- to the GPIO pin connected to the chip's enable pin.
-- usb-phy: Should contain a phandle to the USB PHY
- the ISP1704 is connected to.
-
-Example:
-
-isp1704 {
- compatible = "nxp,isp1704";
- nxp,enable-gpio = <&gpio3 3 GPIO_ACTIVE_LOW>;
- usb-phy = <&usb2_phy>;
-};
diff --git a/Bindings/power/ltc2941.txt b/Bindings/power/ltc2941.txt
deleted file mode 100644
index ea42ae12d924..000000000000
--- a/Bindings/power/ltc2941.txt
+++ /dev/null
@@ -1,27 +0,0 @@
-binding for LTC2941 and LTC2943 battery gauges
-
-Both the LTC2941 and LTC2943 measure battery capacity.
-The LTC2943 is compatible with the LTC2941, it adds voltage and
-temperature monitoring, and uses a slightly different conversion
-formula for the charge counter.
-
-Required properties:
-- compatible: Should contain "ltc2941" or "ltc2943" which also indicates the
- type of I2C chip attached.
-- reg: The 7-bit I2C address.
-- lltc,resistor-sense: The sense resistor value in milli-ohms. Can be a 32-bit
- negative value when the battery has been connected to the wrong end of the
- resistor.
-- lltc,prescaler-exponent: The prescaler exponent as explained in the datasheet.
- This determines the range and accuracy of the gauge. The value is programmed
- into the chip only if it differs from the current setting. The setting is
- lost when the battery is disconnected.
-
-Example from the Topic Miami Florida board:
-
- fuelgauge: ltc2943@64 {
- compatible = "ltc2943";
- reg = <0x64>;
- lltc,resistor-sense = <15>;
- lltc,prescaler-exponent = <5>; /* 2^(2*5) = 1024 */
- };
diff --git a/Bindings/power/pd-samsung.txt b/Bindings/power/pd-samsung.txt
index 4e947372a693..549f7dee9b9d 100644
--- a/Bindings/power/pd-samsung.txt
+++ b/Bindings/power/pd-samsung.txt
@@ -6,12 +6,15 @@ to gate power to one or more peripherals on the processor.
Required Properties:
- compatible: should be one of the following.
* samsung,exynos4210-pd - for exynos4210 type power domain.
+ * samsung,exynos5433-pd - for exynos5433 type power domain.
- reg: physical base address of the controller and length of memory mapped
region.
- #power-domain-cells: number of cells in power domain specifier;
must be 0.
Optional Properties:
+- label: Human readable string with domain name. Will be visible in userspace
+ to let user to distinguish between multiple domains in SoC.
- clocks: List of clock handles. The parent clocks of the input clocks to the
devices in this power domain are set to oscclk before power gating
and restored back after powering on a domain. This is required for
@@ -20,7 +23,7 @@ Optional Properties:
- clock-names: The following clocks can be specified:
- oscclk: Oscillator clock.
- clkN: Input clocks to the devices in this power domain. These clocks
- will be reparented to oscclk before swithing power domain off.
+ will be reparented to oscclk before switching power domain off.
Their original parent will be brought back after turning on
the domain. Maximum of 4 clocks (N = 0 to 3) are supported.
- asbN: Clocks required by asynchronous bridges (ASB) present in
@@ -38,6 +41,7 @@ Example:
compatible = "samsung,exynos4210-pd";
reg = <0x10023C00 0x10>;
#power-domain-cells = <0>;
+ label = "LCD0";
};
mfc_pd: power-domain@10044060 {
@@ -46,6 +50,7 @@ Example:
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_USER_ACLK333>;
clock-names = "oscclk", "clk0";
#power-domain-cells = <0>;
+ label = "MFC";
};
See Documentation/devicetree/bindings/power/power_domain.txt for description
diff --git a/Bindings/power/qcom,coincell-charger.txt b/Bindings/power/qcom,coincell-charger.txt
deleted file mode 100644
index 747899223262..000000000000
--- a/Bindings/power/qcom,coincell-charger.txt
+++ /dev/null
@@ -1,48 +0,0 @@
-Qualcomm Coincell Charger:
-
-The hardware block controls charging for a coincell or capacitor that is
-used to provide power backup for certain features of the power management
-IC (PMIC)
-
-- compatible:
- Usage: required
- Value type: <string>
- Definition: must be: "qcom,pm8941-coincell"
-
-- reg:
- Usage: required
- Value type: <u32>
- Definition: base address of the coincell charger registers
-
-- qcom,rset-ohms:
- Usage: required
- Value type: <u32>
- Definition: resistance (in ohms) for current-limiting resistor
- must be one of: 800, 1200, 1700, 2100
-
-- qcom,vset-millivolts:
- Usage: required
- Value type: <u32>
- Definition: voltage (in millivolts) to apply for charging
- must be one of: 2500, 3000, 3100, 3200
-
-- qcom,charger-disable:
- Usage: optional
- Value type: <boolean>
- Definition: defining this property disables charging
-
-This charger is a sub-node of one of the 8941 PMIC blocks, and is specified
-as a child node in DTS of that node. See ../mfd/qcom,spmi-pmic.txt and
-../mfd/qcom-pm8xxx.txt
-
-Example:
-
- pm8941@0 {
- coincell@2800 {
- compatible = "qcom,pm8941-coincell";
- reg = <0x2800>;
-
- qcom,rset-ohms = <2100>;
- qcom,vset-millivolts = <3000>;
- };
- };
diff --git a/Bindings/power/reset/gpio-poweroff.txt b/Bindings/power/reset/gpio-poweroff.txt
index d4eab9227ea4..e62d53d844cc 100644
--- a/Bindings/power/reset/gpio-poweroff.txt
+++ b/Bindings/power/reset/gpio-poweroff.txt
@@ -2,12 +2,12 @@ Driver a GPIO line that can be used to turn the power off.
The driver supports both level triggered and edge triggered power off.
At driver load time, the driver will request the given gpio line and
-install a pm_power_off handler. If the optional properties 'input' is
-not found, the GPIO line will be driven in the inactive
+install a handler to power off the system. If the optional properties
+'input' is not found, the GPIO line will be driven in the inactive
state. Otherwise its configured as an input.
-When the pm_power_off is called, the gpio is configured as an output,
-and drive active, so triggering a level triggered power off
+When the power-off handler is called, the gpio is configured as an
+output, and drive active, so triggering a level triggered power off
condition. This will also cause an inactive->active edge condition, so
triggering positive edge triggered power off. After a delay of 100ms,
the GPIO is set to inactive, thus causing an active->inactive edge,
@@ -24,7 +24,7 @@ Required properties:
Optional properties:
- input : Initially configure the GPIO line as an input. Only reconfigure
- it to an output when the pm_power_off function is called. If this optional
+ it to an output when the power-off handler is called. If this optional
property is not specified, the GPIO is initialized as an output in its
inactive state.
diff --git a/Bindings/power/reset/qnap-poweroff.txt b/Bindings/power/reset/qnap-poweroff.txt
index af25e77c0e0c..c363d7173129 100644
--- a/Bindings/power/reset/qnap-poweroff.txt
+++ b/Bindings/power/reset/qnap-poweroff.txt
@@ -3,8 +3,7 @@
QNAP NAS devices have a microcontroller controlling the main power
supply. This microcontroller is connected to UART1 of the Kirkwood and
Orion5x SoCs. Sending the character 'A', at 19200 baud, tells the
-microcontroller to turn the power off. This driver adds a handler to
-pm_power_off which is called to turn the power off.
+microcontroller to turn the power off.
Synology NAS devices use a similar scheme, but a different baud rate,
9600, and a different character, '1'.
diff --git a/Bindings/power/rt9455_charger.txt b/Bindings/power/rt9455_charger.txt
deleted file mode 100644
index 5d9ad5cf2c5a..000000000000
--- a/Bindings/power/rt9455_charger.txt
+++ /dev/null
@@ -1,48 +0,0 @@
-Binding for Richtek rt9455 battery charger
-
-Required properties:
-- compatible: it should contain one of the following:
- "richtek,rt9455".
-- reg: integer, i2c address of the device.
-- interrupt-parent: the phandle for the interrupt controller that
- services interrupts for this device.
-- interrupts: interrupt mapping for GPIO IRQ, it should be
- configured with IRQ_TYPE_LEVEL_LOW flag.
-- richtek,output-charge-current: integer, output current from the charger to the
- battery, in uA.
-- richtek,end-of-charge-percentage: integer, percent of the output charge current.
- When the current in constant-voltage phase drops
- below output_charge_current x end-of-charge-percentage,
- charge is terminated.
-- richtek,battery-regulation-voltage: integer, maximum battery voltage in uV.
-- richtek,boost-output-voltage: integer, maximum voltage provided to consumer
- devices, when the charger is in boost mode, in uV.
-
-Optional properties:
-- richtek,min-input-voltage-regulation: integer, input voltage level in uV, used to
- decrease voltage level when the over current
- of the input power source occurs.
- This prevents input voltage drop due to insufficient
- current provided by the power source.
- Default: 4500000 uV (4.5V)
-- richtek,avg-input-current-regulation: integer, input current value in uA drained by the
- charger from the power source.
- Default: 500000 uA (500mA)
-
-Example:
-
-rt9455@22 {
- compatible = "richtek,rt9455";
- reg = <0x22>;
-
- interrupt-parent = <&gpio1>;
- interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
-
- richtek,output-charge-current = <500000>;
- richtek,end-of-charge-percentage = <10>;
- richtek,battery-regulation-voltage = <4200000>;
- richtek,boost-output-voltage = <5050000>;
-
- richtek,min-input-voltage-regulation = <4500000>;
- richtek,avg-input-current-regulation = <500000>;
-};
diff --git a/Bindings/power/rx51-battery.txt b/Bindings/power/rx51-battery.txt
deleted file mode 100644
index 90438453db58..000000000000
--- a/Bindings/power/rx51-battery.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-Binding for Nokia N900 battery
-
-The Nokia N900 battery status can be read via the TWL4030's A/D converter.
-
-Required properties:
-- compatible: Should contain one of the following:
- * "nokia,n900-battery"
-- io-channels: Should contain IIO channel specifiers
- for each element in io-channel-names.
-- io-channel-names: Should contain the following values:
- * "temp" - The ADC channel for temperature reading
- * "bsi" - The ADC channel for battery size identification
- * "vbat" - The ADC channel to measure the battery voltage
-
-Example from Nokia N900:
-
-battery: n900-battery {
- compatible = "nokia,n900-battery";
- io-channels = <&twl4030_madc 0>,
- <&twl4030_madc 4>,
- <&twl4030_madc 12>;
- io-channel-names = "temp",
- "bsi",
- "vbat";
-};
diff --git a/Bindings/power/supply/axp20x_ac_power.txt b/Bindings/power/supply/axp20x_ac_power.txt
new file mode 100644
index 000000000000..826e8a879121
--- /dev/null
+++ b/Bindings/power/supply/axp20x_ac_power.txt
@@ -0,0 +1,22 @@
+AXP20X and AXP22X PMICs' AC power supply
+
+Required Properties:
+ - compatible: One of:
+ "x-powers,axp202-ac-power-supply"
+ "x-powers,axp221-ac-power-supply"
+
+This node is a subnode of the axp20x PMIC.
+
+The AXP20X can read the current current and voltage supplied by AC by
+reading ADC channels from the AXP20X ADC.
+
+The AXP22X is only able to tell if an AC power supply is present and
+usable.
+
+Example:
+
+&axp209 {
+ ac_power_supply: ac-power-supply {
+ compatible = "x-powers,axp202-ac-power-supply";
+ };
+};
diff --git a/Bindings/power/supply/axp20x_usb_power.txt b/Bindings/power/supply/axp20x_usb_power.txt
index f1d7beec45bf..ba8d35f66cbe 100644
--- a/Bindings/power/supply/axp20x_usb_power.txt
+++ b/Bindings/power/supply/axp20x_usb_power.txt
@@ -3,6 +3,11 @@ AXP20x USB power supply
Required Properties:
-compatible: One of: "x-powers,axp202-usb-power-supply"
"x-powers,axp221-usb-power-supply"
+ "x-powers,axp223-usb-power-supply"
+
+The AXP223 PMIC shares most of its behaviour with the AXP221 but has slight
+variations such as the former being able to set the VBUS power supply max
+current to 100mA, unlike the latter.
This node is a subnode of the axp20x PMIC.
diff --git a/Bindings/power/supply/bq27xxx.txt b/Bindings/power/supply/bq27xxx.txt
new file mode 100644
index 000000000000..b0c95ef63e68
--- /dev/null
+++ b/Bindings/power/supply/bq27xxx.txt
@@ -0,0 +1,36 @@
+Binding for TI BQ27XXX fuel gauge family
+
+Required properties:
+- compatible: Should contain one of the following:
+ * "ti,bq27200" - BQ27200
+ * "ti,bq27210" - BQ27210
+ * "ti,bq27500" - deprecated, use revision specific property below
+ * "ti,bq27510" - deprecated, use revision specific property below
+ * "ti,bq27520" - deprecated, use revision specific property below
+ * "ti,bq27500-1" - BQ27500/1
+ * "ti,bq27510g1" - BQ27510-g1
+ * "ti,bq27510g2" - BQ27510-g2
+ * "ti,bq27510g3" - BQ27510-g3
+ * "ti,bq27520g1" - BQ27520-g1
+ * "ti,bq27520g2" - BQ27520-g2
+ * "ti,bq27520g3" - BQ27520-g3
+ * "ti,bq27520g4" - BQ27520-g4
+ * "ti,bq27530" - BQ27530
+ * "ti,bq27531" - BQ27531
+ * "ti,bq27541" - BQ27541
+ * "ti,bq27542" - BQ27542
+ * "ti,bq27546" - BQ27546
+ * "ti,bq27742" - BQ27742
+ * "ti,bq27545" - BQ27545
+ * "ti,bq27421" - BQ27421
+ * "ti,bq27425" - BQ27425
+ * "ti,bq27441" - BQ27441
+ * "ti,bq27621" - BQ27621
+- reg: integer, i2c address of the device.
+
+Example:
+
+bq27510g3 {
+ compatible = "ti,bq27510g3";
+ reg = <0x55>;
+};
diff --git a/Bindings/power/supply/qcom_smbb.txt b/Bindings/power/supply/qcom_smbb.txt
index 65b88fac854b..06f8a5ddb68e 100644
--- a/Bindings/power/supply/qcom_smbb.txt
+++ b/Bindings/power/supply/qcom_smbb.txt
@@ -105,6 +105,22 @@ PROPERTIES
regulation must be done externally to fully comply with
the JEITA safety guidelines if this flag is set.
+- usb_otg_in-supply:
+ Usage: optional
+ Value type: <phandle>
+ Description: Reference to the regulator supplying power to the USB_OTG_IN
+ pin.
+
+child nodes:
+- otg-vbus:
+ Usage: optional
+ Description: This node defines a regulator used to control the direction
+ of VBUS voltage - specifically: whether to supply voltage
+ to VBUS for host mode operation of the OTG port, or allow
+ input voltage from external VBUS for charging. In the
+ hardware, the supply for this regulator comes from
+ usb_otg_in-supply.
+
EXAMPLE
charger@1000 {
compatible = "qcom,pm8941-charger";
@@ -128,4 +144,7 @@ charger@1000 {
qcom,fast-charge-current-limit = <1000000>;
qcom,dc-charge-current-limit = <1000000>;
+ usb_otg_in-supply = <&pm8941_5vs1>;
+
+ otg-vbus {};
};
diff --git a/Bindings/power/supply/sbs_sbs-charger.txt b/Bindings/power/supply/sbs_sbs-charger.txt
new file mode 100644
index 000000000000..a3719623a94f
--- /dev/null
+++ b/Bindings/power/supply/sbs_sbs-charger.txt
@@ -0,0 +1,23 @@
+SBS sbs-charger
+~~~~~~~~~~
+
+Required properties:
+ - compatible: "<vendor>,<part-number>", "sbs,sbs-charger" as fallback. The part
+ number compatible string might be used in order to take care of vendor
+ specific registers.
+
+Optional properties:
+- interrupt-parent: Should be the phandle for the interrupt controller. Use in
+ conjunction with "interrupts".
+- interrupts: Interrupt mapping for GPIO IRQ. Use in conjunction with
+ "interrupt-parent". If an interrupt is not provided the driver will switch
+ automatically to polling.
+
+Example:
+
+ ltc4100@9 {
+ compatible = "lltc,ltc4100", "sbs,sbs-charger";
+ reg = <0x9>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+ };
diff --git a/Bindings/power/supply/ti,bq24735.txt b/Bindings/power/supply/ti,bq24735.txt
index 3bf55757ceec..de45e1a2a4d9 100644
--- a/Bindings/power/supply/ti,bq24735.txt
+++ b/Bindings/power/supply/ti,bq24735.txt
@@ -8,8 +8,10 @@ Optional properties :
- interrupts : Specify the interrupt to be used to trigger when the AC
adapter is either plugged in or removed.
- ti,ac-detect-gpios : This GPIO is optionally used to read the AC adapter
- presence. This is a Host GPIO that is configured as an input and
- connected to the bq24735.
+ status. This is a Host GPIO that is configured as an input and connected
+ to the ACOK pin on the bq24735. Note: for backwards compatibility reasons,
+ the GPIO must be active on AC adapter absence despite ACOK being active
+ (high) on AC adapter presence.
- ti,charge-current : Used to control and set the charging current. This value
must be between 128mA and 8.128A with a 64mA step resolution. The POR value
is 0x0000h. This number is in mA (e.g. 8192), see spec for more information
@@ -25,6 +27,8 @@ Optional properties :
- ti,external-control : Indicates that the charger is configured externally
and that the host should not attempt to enable/disable charging or set the
charge voltage/current.
+ - poll-interval : In case 'interrupts' is not specified, poll AC adapter
+ presence with this interval (milliseconds).
Example:
diff --git a/Bindings/power/twl-charger.txt b/Bindings/power/twl-charger.txt
deleted file mode 100644
index 3b4ea1b73b38..000000000000
--- a/Bindings/power/twl-charger.txt
+++ /dev/null
@@ -1,30 +0,0 @@
-TWL BCI (Battery Charger Interface)
-
-The battery charger needs to interact with the USB phy in order
-to know when charging is permissible, and when there is a connection
-or disconnection.
-
-The choice of phy cannot be configured at a hardware level, so there
-is no value in explicit configuration in device-tree. Rather
-if there is a sibling of the BCI node which is compatible with
-"ti,twl4030-usb", then that is used to determine when and how
-use USB power for charging.
-
-Required properties:
-- compatible:
- - "ti,twl4030-bci"
-- interrupts: two interrupt lines from the TWL SIH (secondary
- interrupt handler) - interrupts 9 and 2.
-
-Optional properties:
-- ti,bb-uvolt: microvolts for charging the backup battery.
-- ti,bb-uamp: microamps for charging the backup battery.
-
-Examples:
-
-bci {
- compatible = "ti,twl4030-bci";
- interrupts = <9>, <2>;
- ti,bb-uvolt = <3200000>;
- ti,bb-uamp = <150>;
-};
diff --git a/Bindings/power_supply/ab8500/btemp.txt b/Bindings/power_supply/ab8500/btemp.txt
deleted file mode 100644
index 0ba1bcc7f33a..000000000000
--- a/Bindings/power_supply/ab8500/btemp.txt
+++ /dev/null
@@ -1,16 +0,0 @@
-=== AB8500 Battery Temperature Monitor Driver ===
-
-The properties below describes the node for btemp driver.
-
-Required Properties:
-- compatible = Shall be: "stericsson,ab8500-btemp"
-- battery = Shall be battery specific information
-
- Example:
- ab8500_btemp {
- compatible = "stericsson,ab8500-btemp";
- battery = <&ab8500_battery>;
- };
-
-For information on battery specific node, Ref:
-Documentation/devicetree/bindings/power_supply/ab8500/fg.txt
diff --git a/Bindings/power_supply/ab8500/chargalg.txt b/Bindings/power_supply/ab8500/chargalg.txt
deleted file mode 100644
index ef5328371122..000000000000
--- a/Bindings/power_supply/ab8500/chargalg.txt
+++ /dev/null
@@ -1,16 +0,0 @@
-=== AB8500 Charging Algorithm Driver ===
-
-The properties below describes the node for chargalg driver.
-
-Required Properties:
-- compatible = Shall be: "stericsson,ab8500-chargalg"
-- battery = Shall be battery specific information
-
-Example:
-ab8500_chargalg {
- compatible = "stericsson,ab8500-chargalg";
- battery = <&ab8500_battery>;
-};
-
-For information on battery specific node, Ref:
-Documentation/devicetree/bindings/power_supply/ab8500/fg.txt
diff --git a/Bindings/power_supply/ab8500/charger.txt b/Bindings/power_supply/ab8500/charger.txt
deleted file mode 100644
index 6bdbb08ea9e0..000000000000
--- a/Bindings/power_supply/ab8500/charger.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-=== AB8500 Charger Driver ===
-
-Required Properties:
-- compatible = Shall be "stericsson,ab8500-charger"
-- battery = Shall be battery specific information
- Example:
- ab8500_charger {
- compatible = "stericsson,ab8500-charger";
- battery = <&ab8500_battery>;
- };
-
-- vddadc-supply: Supply for USB and Main charger
- Example:
- ab8500-charger {
- vddadc-supply = <&ab8500_ldo_tvout_reg>;
- }
-- autopower_cfg:
- Boolean value depicting the presence of 'automatic poweron after powerloss'
- Example:
- ab8500-charger {
- autopower_cfg;
- };
-
-For information on battery specific node, Ref:
-Documentation/devicetree/bindings/power_supply/ab8500/fg.txt
diff --git a/Bindings/power_supply/ab8500/fg.txt b/Bindings/power_supply/ab8500/fg.txt
deleted file mode 100644
index ccafcb9112fb..000000000000
--- a/Bindings/power_supply/ab8500/fg.txt
+++ /dev/null
@@ -1,58 +0,0 @@
-=== AB8500 Fuel Gauge Driver ===
-
-AB8500 is a mixed signal multimedia and power management
-device comprising: power and energy-management-module,
-wall-charger, usb-charger, audio codec, general purpose adc,
-tvout, clock management and sim card interface.
-
-Fuelgauge support is part of energy-management-modules, other
-components of this module are:
-main-charger, usb-combo-charger and battery-temperature-monitoring.
-
-The properties below describes the node for fuelgauge driver.
-
-Required Properties:
-- compatible = This shall be: "stericsson,ab8500-fg"
-- battery = Shall be battery specific information
- Example:
- ab8500_fg {
- compatible = "stericsson,ab8500-fg";
- battery = <&ab8500_battery>;
- };
-
-dependent node:
- ab8500_battery: ab8500_battery {
- };
- This node will provide information on 'thermistor interface' and
- 'battery technology type' used.
-
-Properties of this node are:
-thermistor-on-batctrl:
- A boolean value indicating thermistor interface to battery
-
- Note:
- 'btemp' and 'batctrl' are the pins interfaced for battery temperature
- measurement, 'btemp' signal is used when NTC(negative temperature
- coefficient) resister is interfaced external to battery whereas
- 'batctrl' pin is used when NTC resister is internal to battery.
-
- Example:
- ab8500_battery: ab8500_battery {
- thermistor-on-batctrl;
- };
- indicates: NTC resister is internal to battery, 'batctrl' is used
- for thermal measurement.
-
- The absence of property 'thermal-on-batctrl' indicates
- NTC resister is external to battery and 'btemp' signal is used
- for thermal measurement.
-
-battery-type:
- This shall be the battery manufacturing technology type,
- allowed types are:
- "UNKNOWN" "NiMH" "LION" "LIPO" "LiFe" "NiCd" "LiMn"
- Example:
- ab8500_battery: ab8500_battery {
- stericsson,battery-type = "LIPO";
- }
-
diff --git a/Bindings/power_supply/axp20x_usb_power.txt b/Bindings/power_supply/axp20x_usb_power.txt
deleted file mode 100644
index 862f4a49dc49..000000000000
--- a/Bindings/power_supply/axp20x_usb_power.txt
+++ /dev/null
@@ -1,34 +0,0 @@
-AXP20x USB power supply
-
-Required Properties:
--compatible: "x-powers,axp202-usb-power-supply"
-
-This node is a subnode of the axp20x PMIC.
-
-Example:
-
-axp209: pmic@34 {
- compatible = "x-powers,axp209";
- reg = <0x34>;
- interrupt-parent = <&nmi_intc>;
- interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
- interrupt-controller;
- #interrupt-cells = <1>;
-
- regulators {
- x-powers,dcdc-freq = <1500>;
-
- vdd_cpu: dcdc2 {
- regulator-always-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1450000>;
- regulator-name = "vdd-cpu";
- };
-
- ...
- };
-
- usb-power-supply: usb-power-supply {
- compatible = "x-powers,axp202-usb-power-supply";
- };
-};
diff --git a/Bindings/power_supply/axxia-reset.txt b/Bindings/power_supply/axxia-reset.txt
deleted file mode 100644
index 47e720d249d2..000000000000
--- a/Bindings/power_supply/axxia-reset.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-Axxia Restart Driver
-
-This driver can do reset of the Axxia SoC. It uses the registers in the syscon
-block to initiate a chip reset.
-
-Required Properties:
- -compatible: "lsi,axm55xx-reset"
- -syscon: phandle to the syscon node.
-
-Example:
-
- syscon: syscon@2010030000 {
- compatible = "lsi,axxia-syscon", "syscon";
- reg = <0x20 0x10030000 0 0x2000>;
- };
-
- reset: reset@2010031000 {
- compatible = "lsi,axm55xx-reset";
- syscon = <&syscon>;
- };
diff --git a/Bindings/power_supply/charger-manager.txt b/Bindings/power_supply/charger-manager.txt
deleted file mode 100644
index ec4fe9de3137..000000000000
--- a/Bindings/power_supply/charger-manager.txt
+++ /dev/null
@@ -1,81 +0,0 @@
-charger-manager bindings
-~~~~~~~~~~~~~~~~~~~~~~~~
-
-Required properties :
- - compatible : "charger-manager"
- - <>-supply : for regulator consumer
- - cm-num-chargers : number of chargers
- - cm-chargers : name of chargers
- - cm-fuel-gauge : name of battery fuel gauge
- - subnode <regulator> :
- - cm-regulator-name : name of charger regulator
- - subnode <cable> :
- - cm-cable-name : name of charger cable
- - cm-cable-extcon : name of extcon dev
-(optional) - cm-cable-min : minimum current of cable
-(optional) - cm-cable-max : maximum current of cable
-
-Optional properties :
- - cm-name : charger manager's name (default : "battery")
- - cm-poll-mode : polling mode (enum polling_modes)
- - cm-poll-interval : polling interval
- - cm-battery-stat : battery status (enum data_source)
- - cm-fullbatt-* : data for full battery checking
- - cm-thermal-zone : name of external thermometer's thermal zone
- - cm-battery-* : threshold battery temperature for charging
- -cold : critical cold temperature of battery for charging
- -cold-in-minus : flag that cold temperature is in minus degrees
- -hot : critical hot temperature of battery for charging
- -temp-diff : temperature difference to allow recharging
- - cm-dis/charging-max = limits of charging duration
-
-Example :
- charger-manager@0 {
- compatible = "charger-manager";
- chg-reg-supply = <&charger_regulator>;
-
- cm-name = "battery";
- /* Always polling ON : 30s */
- cm-poll-mode = <1>;
- cm-poll-interval = <30000>;
-
- cm-fullbatt-vchkdrop-ms = <30000>;
- cm-fullbatt-vchkdrop-volt = <150000>;
- cm-fullbatt-soc = <100>;
-
- cm-battery-stat = <3>;
-
- cm-num-chargers = <3>;
- cm-chargers = "charger0", "charger1", "charger2";
-
- cm-fuel-gauge = "fuelgauge0";
-
- cm-thermal-zone = "thermal_zone.1"
- /* in deci centigrade */
- cm-battery-cold = <50>;
- cm-battery-cold-in-minus;
- cm-battery-hot = <800>;
- cm-battery-temp-diff = <100>;
-
- /* Allow charging for 5hr */
- cm-charging-max = <18000000>;
- /* Allow discharging for 2hr */
- cm-discharging-max = <7200000>;
-
- regulator@0 {
- cm-regulator-name = "chg-reg";
- cable@0 {
- cm-cable-name = "USB";
- cm-cable-extcon = "extcon-dev.0";
- cm-cable-min = <475000>;
- cm-cable-max = <500000>;
- };
- cable@1 {
- cm-cable-name = "TA";
- cm-cable-extcon = "extcon-dev.0";
- cm-cable-min = <650000>;
- cm-cable-max = <675000>;
- };
- };
-
- };
diff --git a/Bindings/power_supply/gpio-charger.txt b/Bindings/power_supply/gpio-charger.txt
deleted file mode 100644
index adbb5dc5b6e9..000000000000
--- a/Bindings/power_supply/gpio-charger.txt
+++ /dev/null
@@ -1,27 +0,0 @@
-gpio-charger
-
-Required properties :
- - compatible : "gpio-charger"
- - gpios : GPIO indicating the charger presence.
- See GPIO binding in bindings/gpio/gpio.txt .
- - charger-type : power supply type, one of
- unknown
- battery
- ups
- mains
- usb-sdp (USB standard downstream port)
- usb-dcp (USB dedicated charging port)
- usb-cdp (USB charging downstream port)
- usb-aca (USB accessory charger adapter)
-
-Example:
-
- usb_charger: charger {
- compatible = "gpio-charger";
- charger-type = "usb-sdp";
- gpios = <&gpf0 2 0 0 0>;
- }
-
- battery {
- power-supplies = <&usb_charger>;
- };
diff --git a/Bindings/power_supply/imx-snvs-poweroff.txt b/Bindings/power_supply/imx-snvs-poweroff.txt
deleted file mode 100644
index dc7c9bad63ea..000000000000
--- a/Bindings/power_supply/imx-snvs-poweroff.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-i.mx6 Poweroff Driver
-
-SNVS_LPCR in SNVS module can power off the whole system by pull
-PMIC_ON_REQ low if PMIC_ON_REQ is connected with external PMIC.
-If you don't want to use PMIC_ON_REQ as power on/off control,
-please set status='disabled' to disable this driver.
-
-Required Properties:
--compatible: "fsl,sec-v4.0-poweroff"
--reg: Specifies the physical address of the SNVS_LPCR register
-
-Example:
- snvs@020cc000 {
- compatible = "fsl,sec-v4.0-mon", "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x020cc000 0x4000>;
- .....
- snvs_poweroff: snvs-poweroff@38 {
- compatible = "fsl,sec-v4.0-poweroff";
- reg = <0x38 0x4>;
- };
- }
diff --git a/Bindings/power_supply/lp8727_charger.txt b/Bindings/power_supply/lp8727_charger.txt
deleted file mode 100644
index 2246bc5c874b..000000000000
--- a/Bindings/power_supply/lp8727_charger.txt
+++ /dev/null
@@ -1,44 +0,0 @@
-Binding for TI/National Semiconductor LP8727 Charger
-
-Required properties:
-- compatible: "ti,lp8727"
-- reg: I2C slave address 27h
-
-Optional properties:
-- interrupt-parent: interrupt controller node (see interrupt binding[0])
-- interrupts: interrupt specifier (see interrupt binding[0])
-- debounce-ms: interrupt debounce time. (u32)
-
-AC and USB charging parameters
-- charger-type: "ac" or "usb" (string)
-- eoc-level: value of 'enum lp8727_eoc_level' (u8)
-- charging-current: value of 'enum lp8727_ichg' (u8)
-
-[0]: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
-
-Example)
-
-lp8727@27 {
- compatible = "ti,lp8727";
- reg = <0x27>;
-
- /* GPIO 134 is used for LP8728 interrupt pin */
- interrupt-parent = <&gpio5>; /* base = 128 */
- interrupts = <6 0x2>; /* offset = 6, falling edge type */
-
- debounce-ms = <300>;
-
- /* AC charger: 5% EOC and 500mA charging current */
- ac {
- charger-type = "ac";
- eoc-level = /bits/ 8 <0>;
- charging-current = /bits/ 8 <4>;
- };
-
- /* USB charger: 10% EOC and 400mA charging current */
- usb {
- charger-type = "usb";
- eoc-level = /bits/ 8 <1>;
- charging-current = /bits/ 8 <2>;
- };
-};
diff --git a/Bindings/power_supply/max17042_battery.txt b/Bindings/power_supply/max17042_battery.txt
deleted file mode 100644
index 3f3894aaeebc..000000000000
--- a/Bindings/power_supply/max17042_battery.txt
+++ /dev/null
@@ -1,31 +0,0 @@
-max17042_battery
-~~~~~~~~~~~~~~~~
-
-Required properties :
- - compatible : "maxim,max17042"
-
-Optional properties :
- - maxim,rsns-microohm : Resistance of rsns resistor in micro Ohms
- (datasheet-recommended value is 10000).
- Defining this property enables current-sense functionality.
-
-Optional threshold properties :
- If skipped the condition won't be reported.
- - maxim,cold-temp : Temperature threshold to report battery
- as cold (in tenths of degree Celsius).
- - maxim,over-heat-temp : Temperature threshold to report battery
- as over heated (in tenths of degree Celsius).
- - maxim,dead-volt : Voltage threshold to report battery
- as dead (in mV).
- - maxim,over-volt : Voltage threshold to report battery
- as over voltage (in mV).
-
-Example:
-
- battery-charger@36 {
- compatible = "maxim,max17042";
- reg = <0x36>;
- maxim,rsns-microohm = <10000>;
- maxim,over-heat-temp = <600>;
- maxim,over-volt = <4300>;
- };
diff --git a/Bindings/power_supply/max8925_batter.txt b/Bindings/power_supply/max8925_batter.txt
deleted file mode 100644
index d7e3e0c0f71d..000000000000
--- a/Bindings/power_supply/max8925_batter.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-max8925-battery bindings
-~~~~~~~~~~~~~~~~
-
-Optional properties :
- - batt-detect: whether support battery detect
- - topoff-threshold: set charging current in topoff mode
- - fast-charge: set charging current in fast mode
- - no-temp-support: whether support temperature protection detect
- - no-insert-detect: whether support insert detect
-
-Example:
- charger {
- batt-detect = <0>;
- topoff-threshold = <1>;
- fast-charge = <7>;
- no-temp-support = <0>;
- no-insert-detect = <0>;
- };
diff --git a/Bindings/power_supply/maxim,max14656.txt b/Bindings/power_supply/maxim,max14656.txt
new file mode 100644
index 000000000000..e03e85ae6572
--- /dev/null
+++ b/Bindings/power_supply/maxim,max14656.txt
@@ -0,0 +1,25 @@
+Maxim MAX14656 / AL32 USB Charger Detector
+
+Required properties :
+- compatible : "maxim,max14656";
+- reg: i2c slave address
+- interrupt-parent: the phandle for the interrupt controller
+- interrupts: interrupt line
+
+Example:
+
+&i2c2 {
+ clock-frequency = <50000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ max14656@35 {
+ compatible = "maxim,max14656";
+ reg = <0x35>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_charger_detect>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <26 IRQ_TYPE_LEVEL_HIGH>;
+ };
+};
diff --git a/Bindings/power_supply/msm-poweroff.txt b/Bindings/power_supply/msm-poweroff.txt
deleted file mode 100644
index ce44ad357565..000000000000
--- a/Bindings/power_supply/msm-poweroff.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-MSM Restart Driver
-
-A power supply hold (ps-hold) bit is set to power the msm chipsets.
-Clearing that bit allows us to restart/poweroff. The difference
-between poweroff and restart is determined by unique power manager IC
-settings.
-
-Required Properties:
--compatible: "qcom,pshold"
--reg: Specifies the physical address of the ps-hold register
-
-Example:
-
- restart@fc4ab000 {
- compatible = "qcom,pshold";
- reg = <0xfc4ab000 0x4>;
- };
diff --git a/Bindings/power_supply/olpc_battery.txt b/Bindings/power_supply/olpc_battery.txt
deleted file mode 100644
index c8901b3992d9..000000000000
--- a/Bindings/power_supply/olpc_battery.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-OLPC battery
-~~~~~~~~~~~~
-
-Required properties:
- - compatible : "olpc,xo1-battery"
diff --git a/Bindings/power_supply/power_supply.txt b/Bindings/power_supply/power_supply.txt
deleted file mode 100644
index 8391bfa0edac..000000000000
--- a/Bindings/power_supply/power_supply.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-Power Supply Core Support
-
-Optional Properties:
- - power-supplies : This property is added to a supply in order to list the
- devices which supply it power, referenced by their phandles.
-
-Example:
-
- usb-charger: power@e {
- compatible = "some,usb-charger";
- ...
- };
-
- ac-charger: power@c {
- compatible = "some,ac-charger";
- ...
- };
-
- battery@b {
- compatible = "some,battery";
- ...
- power-supplies = <&usb-charger>, <&ac-charger>;
- };
diff --git a/Bindings/power_supply/qcom_smbb.txt b/Bindings/power_supply/qcom_smbb.txt
deleted file mode 100644
index 65b88fac854b..000000000000
--- a/Bindings/power_supply/qcom_smbb.txt
+++ /dev/null
@@ -1,131 +0,0 @@
-Qualcomm Switch-Mode Battery Charger and Boost
-
-PROPERTIES
-- compatible:
- Usage: required
- Value type: <stringlist>
- Description: Must be one of:
- - "qcom,pm8941-charger"
-
-- reg:
- Usage: required
- Value type: <prop-encoded-array>
- Description: Base address of registers for SMBB block
-
-- interrupts:
- Usage: required
- Value type: <prop-encoded-array>
- Description: The format of the specifier is defined by the binding document
- describing the node's interrupt parent. Must contain one
- specifier for each of the following interrupts, in order:
- - charge done
- - charge fast mode
- - charge trickle mode
- - battery temperature ok
- - battery present
- - charger disconnected
- - USB-in valid
- - DC-in valid
-
-- interrupt-names:
- Usage: required
- Value type: <stringlist>
- Description: Must contain the following list, strictly ordered:
- "chg-done",
- "chg-fast",
- "chg-trkl",
- "bat-temp-ok",
- "bat-present",
- "chg-gone",
- "usb-valid",
- "dc-valid"
-
-- qcom,fast-charge-current-limit:
- Usage: optional (default: 1A, or pre-configured value)
- Value type: <u32>; uA; range [100mA : 3A]
- Description: Maximum charge current; May be clamped to safety limits.
-
-- qcom,fast-charge-low-threshold-voltage:
- Usage: optional (default: 3.2V, or pre-configured value)
- Value type: <u32>; uV; range [2.1V : 3.6V]
- Description: Battery voltage limit above which fast charging may operate;
- Below this value linear or switch-mode auto-trickle-charging
- will operate.
-
-- qcom,fast-charge-high-threshold-voltage:
- Usage: optional (default: 4.2V, or pre-configured value)
- Value type: <u32>; uV; range [3.24V : 5V]
- Description: Battery voltage limit below which fast charging may operate;
- The fast charger will attempt to charge the battery to this
- voltage. May be clamped to safety limits.
-
-- qcom,fast-charge-safe-voltage:
- Usage: optional (default: 4.2V, or pre-configured value)
- Value type: <u32>; uV; range [3.24V : 5V]
- Description: Maximum safe battery voltage; May be pre-set by bootloader, in
- which case, setting this will harmlessly fail. The property
- 'fast-charge-high-watermark' will be clamped by this value.
-
-- qcom,fast-charge-safe-current:
- Usage: optional (default: 1A, or pre-configured value)
- Value type: <u32>; uA; range [100mA : 3A]
- Description: Maximum safe battery charge current; May pre-set by bootloader,
- in which case, setting this will harmlessly fail. The property
- 'qcom,fast-charge-current-limit' will be clamped by this value.
-
-- qcom,auto-recharge-threshold-voltage:
- Usage: optional (default: 4.1V, or pre-configured value)
- Value type: <u32>; uV; range [3.24V : 5V]
- Description: Battery voltage limit below which auto-recharge functionality
- will restart charging after end-of-charge; The high cutoff
- limit for auto-recharge is 5% above this value.
-
-- qcom,minimum-input-voltage:
- Usage: optional (default: 4.3V, or pre-configured value)
- Value type: <u32>; uV; range [4.2V : 9.6V]
- Description: Input voltage level above which charging may operate
-
-- qcom,dc-current-limit:
- Usage: optional (default: 100mA, or pre-configured value)
- Value type: <u32>; uA; range [100mA : 2.5A]
- Description: Default DC charge current limit
-
-- qcom,disable-dc:
- Usage: optional (default: false)
- Value type: boolean: <u32> or <empty>
- Description: Disable DC charger
-
-- qcom,jeita-extended-temp-range:
- Usage: optional (default: false)
- Value type: boolean: <u32> or <empty>
- Description: Enable JEITA extended temperature range; This does *not*
- adjust the maximum charge voltage or current in the extended
- temperature range. It only allows charging when the battery
- is in the extended temperature range. Voltage/current
- regulation must be done externally to fully comply with
- the JEITA safety guidelines if this flag is set.
-
-EXAMPLE
-charger@1000 {
- compatible = "qcom,pm8941-charger";
- reg = <0x1000 0x700>;
- interrupts = <0x0 0x10 7 IRQ_TYPE_EDGE_BOTH>,
- <0x0 0x10 5 IRQ_TYPE_EDGE_BOTH>,
- <0x0 0x10 4 IRQ_TYPE_EDGE_BOTH>,
- <0x0 0x12 1 IRQ_TYPE_EDGE_BOTH>,
- <0x0 0x12 0 IRQ_TYPE_EDGE_BOTH>,
- <0x0 0x13 2 IRQ_TYPE_EDGE_BOTH>,
- <0x0 0x13 1 IRQ_TYPE_EDGE_BOTH>,
- <0x0 0x14 1 IRQ_TYPE_EDGE_BOTH>;
- interrupt-names = "chg-done",
- "chg-fast",
- "chg-trkl",
- "bat-temp-ok",
- "bat-present",
- "chg-gone",
- "usb-valid",
- "dc-valid";
-
- qcom,fast-charge-current-limit = <1000000>;
- qcom,dc-charge-current-limit = <1000000>;
-};
diff --git a/Bindings/power_supply/qnap-poweroff.txt b/Bindings/power_supply/qnap-poweroff.txt
deleted file mode 100644
index af25e77c0e0c..000000000000
--- a/Bindings/power_supply/qnap-poweroff.txt
+++ /dev/null
@@ -1,16 +0,0 @@
-* QNAP Power Off
-
-QNAP NAS devices have a microcontroller controlling the main power
-supply. This microcontroller is connected to UART1 of the Kirkwood and
-Orion5x SoCs. Sending the character 'A', at 19200 baud, tells the
-microcontroller to turn the power off. This driver adds a handler to
-pm_power_off which is called to turn the power off.
-
-Synology NAS devices use a similar scheme, but a different baud rate,
-9600, and a different character, '1'.
-
-Required Properties:
-- compatible: Should be "qnap,power-off" or "synology,power-off"
-
-- reg: Address and length of the register set for UART1
-- clocks: tclk clock
diff --git a/Bindings/power_supply/restart-poweroff.txt b/Bindings/power_supply/restart-poweroff.txt
deleted file mode 100644
index 5776e684afda..000000000000
--- a/Bindings/power_supply/restart-poweroff.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-* Restart Power Off
-
-Buffalo Linkstation LS-XHL and LS-CHLv2, and other devices power off
-by restarting and letting u-boot keep hold of the machine until the
-user presses a button.
-
-Required Properties:
-- compatible: Should be "restart-poweroff"
diff --git a/Bindings/power_supply/sbs_sbs-battery.txt b/Bindings/power_supply/sbs_sbs-battery.txt
deleted file mode 100644
index c40e8926facf..000000000000
--- a/Bindings/power_supply/sbs_sbs-battery.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-SBS sbs-battery
-~~~~~~~~~~
-
-Required properties :
- - compatible : "sbs,sbs-battery"
-
-Optional properties :
- - sbs,i2c-retry-count : The number of times to retry i2c transactions on i2c
- IO failure.
- - sbs,poll-retry-count : The number of times to try looking for new status
- after an external change notification.
- - sbs,battery-detect-gpios : The gpio which signals battery detection and
- a flag specifying its polarity.
-
-Example:
-
- bq20z75@b {
- compatible = "sbs,sbs-battery";
- reg = < 0xb >;
- sbs,i2c-retry-count = <2>;
- sbs,poll-retry-count = <10>;
- sbs,battery-detect-gpios = <&gpio-controller 122 1>;
- }
diff --git a/Bindings/power_supply/ti,bq24735.txt b/Bindings/power_supply/ti,bq24735.txt
deleted file mode 100644
index 3bf55757ceec..000000000000
--- a/Bindings/power_supply/ti,bq24735.txt
+++ /dev/null
@@ -1,35 +0,0 @@
-TI BQ24735 Charge Controller
-~~~~~~~~~~
-
-Required properties :
- - compatible : "ti,bq24735"
-
-Optional properties :
- - interrupts : Specify the interrupt to be used to trigger when the AC
- adapter is either plugged in or removed.
- - ti,ac-detect-gpios : This GPIO is optionally used to read the AC adapter
- presence. This is a Host GPIO that is configured as an input and
- connected to the bq24735.
- - ti,charge-current : Used to control and set the charging current. This value
- must be between 128mA and 8.128A with a 64mA step resolution. The POR value
- is 0x0000h. This number is in mA (e.g. 8192), see spec for more information
- about the ChargeCurrent (0x14h) register.
- - ti,charge-voltage : Used to control and set the charging voltage. This value
- must be between 1.024V and 19.2V with a 16mV step resolution. The POR value
- is 0x0000h. This number is in mV (e.g. 19200), see spec for more information
- about the ChargeVoltage (0x15h) register.
- - ti,input-current : Used to control and set the charger input current. This
- value must be between 128mA and 8.064A with a 128mA step resolution. The
- POR value is 0x1000h. This number is in mA (e.g. 8064), see the spec for
- more information about the InputCurrent (0x3fh) register.
- - ti,external-control : Indicates that the charger is configured externally
- and that the host should not attempt to enable/disable charging or set the
- charge voltage/current.
-
-Example:
-
- bq24735@9 {
- compatible = "ti,bq24735";
- reg = <0x9>;
- ti,ac-detect-gpios = <&gpio 72 0x1>;
- }
diff --git a/Bindings/power_supply/tps65090.txt b/Bindings/power_supply/tps65090.txt
deleted file mode 100644
index 8e5e0d3910df..000000000000
--- a/Bindings/power_supply/tps65090.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-TPS65090 Frontend PMU with Switchmode Charger
-
-Required Properties:
--compatible: "ti,tps65090-charger"
-
-Optional Properties:
--ti,enable-low-current-chrg: Enables charging when a low current is detected
- while the default logic is to stop charging.
-
-This node is a subnode of the tps65090 PMIC.
-
-Example:
-
- tps65090-charger {
- compatible = "ti,tps65090-charger";
- ti,enable-low-current-chrg;
- };
diff --git a/Bindings/power_supply/tps65217_charger.txt b/Bindings/power_supply/tps65217_charger.txt
deleted file mode 100644
index 98d131acee95..000000000000
--- a/Bindings/power_supply/tps65217_charger.txt
+++ /dev/null
@@ -1,12 +0,0 @@
-TPS65217 Charger
-
-Required Properties:
--compatible: "ti,tps65217-charger"
-
-This node is a subnode of the tps65217 PMIC.
-
-Example:
-
- tps65217-charger {
- compatible = "ti,tps65090-charger";
- };
diff --git a/Bindings/powerpc/4xx/emac.txt b/Bindings/powerpc/4xx/emac.txt
index 712baf6c3e24..44b842b6ca15 100644
--- a/Bindings/powerpc/4xx/emac.txt
+++ b/Bindings/powerpc/4xx/emac.txt
@@ -71,6 +71,9 @@
For Axon it can be absent, though my current driver
doesn't handle phy-address yet so for now, keep
0x00ffffff in it.
+ - phy-handle : Used to describe configurations where a external PHY
+ is used. Please refer to:
+ Documentation/devicetree/bindings/net/ethernet.txt
- rx-fifo-size-gige : 1 cell, Rx fifo size in bytes for 1000 Mb/sec
operations (if absent the value is the same as
rx-fifo-size). For Axon, either absent or 2048.
@@ -81,8 +84,22 @@
offload, phandle of the TAH device node.
- tah-channel : 1 cell, optional. If appropriate, channel used on the
TAH engine.
+ - fixed-link : Fixed-link subnode describing a link to a non-MDIO
+ managed entity. See
+ Documentation/devicetree/bindings/net/fixed-link.txt
+ for details.
+ - mdio subnode : When the EMAC has a phy connected to its local
+ mdio, which us supported by the kernel's network
+ PHY library in drivers/net/phy, there must be device
+ tree subnode with the following required properties:
+ - #address-cells: Must be <1>.
+ - #size-cells: Must be <0>.
- Example:
+ For PHY definitions: Please refer to
+ Documentation/devicetree/bindings/net/phy.txt and
+ Documentation/devicetree/bindings/net/ethernet.txt
+
+ Examples:
EMAC0: ethernet@40000800 {
device_type = "network";
@@ -104,6 +121,48 @@
zmii-channel = <0>;
};
+ EMAC1: ethernet@ef600c00 {
+ device_type = "network";
+ compatible = "ibm,emac-apm821xx", "ibm,emac4sync";
+ interrupt-parent = <&EMAC1>;
+ interrupts = <0 1>;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-map = <0 &UIC2 0x10 IRQ_TYPE_LEVEL_HIGH /* Status */
+ 1 &UIC2 0x14 IRQ_TYPE_LEVEL_HIGH /* Wake */>;
+ reg = <0xef600c00 0x000000c4>;
+ local-mac-address = [000000000000]; /* Filled in by U-Boot */
+ mal-device = <&MAL0>;
+ mal-tx-channel = <0>;
+ mal-rx-channel = <0>;
+ cell-index = <0>;
+ max-frame-size = <9000>;
+ rx-fifo-size = <16384>;
+ tx-fifo-size = <2048>;
+ fifo-entry-size = <10>;
+ phy-mode = "rgmii";
+ phy-handle = <&phy0>;
+ phy-map = <0x00000000>;
+ rgmii-device = <&RGMII0>;
+ rgmii-channel = <0>;
+ tah-device = <&TAH0>;
+ tah-channel = <0>;
+ has-inverted-stacr-oc;
+ has-new-stacr-staopc;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+ };
+ };
+
+
ii) McMAL node
Required properties:
@@ -145,4 +204,3 @@
- revision : as provided by the RGMII new version register if
available.
For Axon: 0x0000012a
-
diff --git a/Bindings/powerpc/fsl/cpm_qe/cpm.txt b/Bindings/powerpc/fsl/cpm_qe/cpm.txt
deleted file mode 100644
index 160c752484b4..000000000000
--- a/Bindings/powerpc/fsl/cpm_qe/cpm.txt
+++ /dev/null
@@ -1,67 +0,0 @@
-* Freescale Communications Processor Module
-
-NOTE: This is an interim binding, and will likely change slightly,
-as more devices are supported. The QE bindings especially are
-incomplete.
-
-* Root CPM node
-
-Properties:
-- compatible : "fsl,cpm1", "fsl,cpm2", or "fsl,qe".
-- reg : A 48-byte region beginning with CPCR.
-
-Example:
- cpm@119c0 {
- #address-cells = <1>;
- #size-cells = <1>;
- #interrupt-cells = <2>;
- compatible = "fsl,mpc8272-cpm", "fsl,cpm2";
- reg = <119c0 30>;
- }
-
-* Properties common to multiple CPM/QE devices
-
-- fsl,cpm-command : This value is ORed with the opcode and command flag
- to specify the device on which a CPM command operates.
-
-- fsl,cpm-brg : Indicates which baud rate generator the device
- is associated with. If absent, an unused BRG
- should be dynamically allocated. If zero, the
- device uses an external clock rather than a BRG.
-
-- reg : Unless otherwise specified, the first resource represents the
- scc/fcc/ucc registers, and the second represents the device's
- parameter RAM region (if it has one).
-
-* Multi-User RAM (MURAM)
-
-The multi-user/dual-ported RAM is expressed as a bus under the CPM node.
-
-Ranges must be set up subject to the following restrictions:
-
-- Children's reg nodes must be offsets from the start of all muram, even
- if the user-data area does not begin at zero.
-- If multiple range entries are used, the difference between the parent
- address and the child address must be the same in all, so that a single
- mapping can cover them all while maintaining the ability to determine
- CPM-side offsets with pointer subtraction. It is recommended that
- multiple range entries not be used.
-- A child address of zero must be translatable, even if no reg resources
- contain it.
-
-A child "data" node must exist, compatible with "fsl,cpm-muram-data", to
-indicate the portion of muram that is usable by the OS for arbitrary
-purposes. The data node may have an arbitrary number of reg resources,
-all of which contribute to the allocatable muram pool.
-
-Example, based on mpc8272:
- muram@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0 10000>;
-
- data@0 {
- compatible = "fsl,cpm-muram-data";
- reg = <0 2000 9800 800>;
- };
- };
diff --git a/Bindings/powerpc/fsl/cpm_qe/cpm/brg.txt b/Bindings/powerpc/fsl/cpm_qe/cpm/brg.txt
deleted file mode 100644
index 4c7d45eaf025..000000000000
--- a/Bindings/powerpc/fsl/cpm_qe/cpm/brg.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-* Baud Rate Generators
-
-Currently defined compatibles:
-fsl,cpm-brg
-fsl,cpm1-brg
-fsl,cpm2-brg
-
-Properties:
-- reg : There may be an arbitrary number of reg resources; BRG
- numbers are assigned to these in order.
-- clock-frequency : Specifies the base frequency driving
- the BRG.
-
-Example:
- brg@119f0 {
- compatible = "fsl,mpc8272-brg",
- "fsl,cpm2-brg",
- "fsl,cpm-brg";
- reg = <119f0 10 115f0 10>;
- clock-frequency = <d#25000000>;
- };
diff --git a/Bindings/powerpc/fsl/cpm_qe/cpm/i2c.txt b/Bindings/powerpc/fsl/cpm_qe/cpm/i2c.txt
deleted file mode 100644
index 87bc6048667e..000000000000
--- a/Bindings/powerpc/fsl/cpm_qe/cpm/i2c.txt
+++ /dev/null
@@ -1,41 +0,0 @@
-* I2C
-
-The I2C controller is expressed as a bus under the CPM node.
-
-Properties:
-- compatible : "fsl,cpm1-i2c", "fsl,cpm2-i2c"
-- reg : On CPM2 devices, the second resource doesn't specify the I2C
- Parameter RAM itself, but the I2C_BASE field of the CPM2 Parameter RAM
- (typically 0x8afc 0x2).
-- #address-cells : Should be one. The cell is the i2c device address with
- the r/w bit set to zero.
-- #size-cells : Should be zero.
-- clock-frequency : Can be used to set the i2c clock frequency. If
- unspecified, a default frequency of 60kHz is being used.
-The following two properties are deprecated. They are only used by legacy
-i2c drivers to find the bus to probe:
-- linux,i2c-index : Can be used to hard code an i2c bus number. By default,
- the bus number is dynamically assigned by the i2c core.
-- linux,i2c-class : Can be used to override the i2c class. The class is used
- by legacy i2c device drivers to find a bus in a specific context like
- system management, video or sound. By default, I2C_CLASS_HWMON (1) is
- being used. The definition of the classes can be found in
- include/i2c/i2c.h
-
-Example, based on mpc823:
-
- i2c@860 {
- compatible = "fsl,mpc823-i2c",
- "fsl,cpm1-i2c";
- reg = <0x860 0x20 0x3c80 0x30>;
- interrupts = <16>;
- interrupt-parent = <&CPM_PIC>;
- fsl,cpm-command = <0x10>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- rtc@68 {
- compatible = "dallas,ds1307";
- reg = <0x68>;
- };
- };
diff --git a/Bindings/powerpc/fsl/cpm_qe/cpm/pic.txt b/Bindings/powerpc/fsl/cpm_qe/cpm/pic.txt
deleted file mode 100644
index 8e3ee1681618..000000000000
--- a/Bindings/powerpc/fsl/cpm_qe/cpm/pic.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-* Interrupt Controllers
-
-Currently defined compatibles:
-- fsl,cpm1-pic
- - only one interrupt cell
-- fsl,pq1-pic
-- fsl,cpm2-pic
- - second interrupt cell is level/sense:
- - 2 is falling edge
- - 8 is active low
-
-Example:
- interrupt-controller@10c00 {
- #interrupt-cells = <2>;
- interrupt-controller;
- reg = <10c00 80>;
- compatible = "mpc8272-pic", "fsl,cpm2-pic";
- };
diff --git a/Bindings/powerpc/fsl/cpm_qe/cpm/usb.txt b/Bindings/powerpc/fsl/cpm_qe/cpm/usb.txt
deleted file mode 100644
index 74bfda4bb824..000000000000
--- a/Bindings/powerpc/fsl/cpm_qe/cpm/usb.txt
+++ /dev/null
@@ -1,15 +0,0 @@
-* USB (Universal Serial Bus Controller)
-
-Properties:
-- compatible : "fsl,cpm1-usb", "fsl,cpm2-usb", "fsl,qe-usb"
-
-Example:
- usb@11bc0 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,cpm2-usb";
- reg = <11b60 18 8b00 100>;
- interrupts = <b 8>;
- interrupt-parent = <&PIC>;
- fsl,cpm-command = <2e600000>;
- };
diff --git a/Bindings/powerpc/fsl/cpm_qe/gpio.txt