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authorAndrew Turner <andrew@FreeBSD.org>2016-07-27 10:33:45 +0000
committerAndrew Turner <andrew@FreeBSD.org>2016-07-27 10:33:45 +0000
commitc7716441be3a4a48aa7b7cdf69a15625c1cd8ef5 (patch)
tree2a59dacd09463974e72f84b0e05f237b0ba3f57b
parent235ad806ee815395bce54dc1b0ce1c06cd29b44a (diff)
downloadsrc-c7716441be3a4a48aa7b7cdf69a15625c1cd8ef5.tar.gz
src-c7716441be3a4a48aa7b7cdf69a15625c1cd8ef5.zip
Import the updated devicetree files fromvendor/device-tree/devicetree-965f3718
Notes
Notes: svn path=/vendor/device-tree/dist/; revision=303380 svn path=/vendor/device-tree/devicetree-965f3718/; revision=303381; tag=vendor/device-tree/devicetree-965f3718
-rw-r--r--Bindings/arc/archs-pct.txt2
-rw-r--r--Bindings/arc/eznps.txt7
-rw-r--r--Bindings/arc/pct.txt2
-rw-r--r--Bindings/arm/altera/socfpga-eccmgr.txt99
-rw-r--r--Bindings/arm/amlogic.txt10
-rw-r--r--Bindings/arm/arm-boards13
-rw-r--r--Bindings/arm/atmel-at91.txt65
-rw-r--r--Bindings/arm/axis.txt29
-rw-r--r--Bindings/arm/bcm/brcm,vulcan-soc.txt10
-rw-r--r--Bindings/arm/cci.txt4
-rw-r--r--Bindings/arm/coresight.txt28
-rw-r--r--Bindings/arm/cpus.txt5
-rw-r--r--Bindings/arm/fsl.txt4
-rw-r--r--Bindings/arm/fw-cfg.txt38
-rw-r--r--Bindings/arm/hisilicon/hisilicon.txt20
-rw-r--r--Bindings/arm/keystone/keystone.txt5
-rw-r--r--Bindings/arm/l2c2x0.txt6
-rw-r--r--Bindings/arm/marvell/ap806-system-controller.txt35
-rw-r--r--Bindings/arm/marvell/armada-370-xp-pmsu.txt (renamed from Bindings/arm/armada-370-xp-pmsu.txt)0
-rw-r--r--Bindings/arm/marvell/armada-370-xp.txt (renamed from Bindings/arm/armada-370-xp.txt)0
-rw-r--r--Bindings/arm/marvell/armada-375.txt (renamed from Bindings/arm/armada-375.txt)0
-rw-r--r--Bindings/arm/marvell/armada-37xx.txt16
-rw-r--r--Bindings/arm/marvell/armada-380-mpcore-soc-ctrl.txt (renamed from Bindings/arm/armada-380-mpcore-soc-ctrl.txt)0
-rw-r--r--Bindings/arm/marvell/armada-38x.txt (renamed from Bindings/arm/armada-38x.txt)0
-rw-r--r--Bindings/arm/marvell/armada-39x.txt (renamed from Bindings/arm/armada-39x.txt)0
-rw-r--r--Bindings/arm/marvell/armada-7k-8k.txt24
-rw-r--r--Bindings/arm/marvell/armada-cpu-reset.txt (renamed from Bindings/arm/armada-cpu-reset.txt)0
-rw-r--r--Bindings/arm/marvell/coherency-fabric.txt (renamed from Bindings/arm/coherency-fabric.txt)0
-rw-r--r--Bindings/arm/marvell/cp110-system-controller0.txt83
-rw-r--r--Bindings/arm/marvell/kirkwood.txt (renamed from Bindings/arm/kirkwood.txt)0
-rw-r--r--Bindings/arm/marvell/marvell,berlin.txt (renamed from Bindings/arm/marvell,berlin.txt)0
-rw-r--r--Bindings/arm/marvell/marvell,dove.txt (renamed from Bindings/arm/marvell,dove.txt)0
-rw-r--r--Bindings/arm/marvell/marvell,kirkwood.txt (renamed from Bindings/arm/marvell,kirkwood.txt)7
-rw-r--r--Bindings/arm/marvell/mvebu-cpu-config.txt (renamed from Bindings/arm/mvebu-cpu-config.txt)0
-rw-r--r--Bindings/arm/marvell/mvebu-system-controller.txt (renamed from Bindings/arm/mvebu-system-controller.txt)0
-rw-r--r--Bindings/arm/mediatek.txt4
-rw-r--r--Bindings/arm/nxp/lpc32xx.txt (renamed from Bindings/arm/lpc32xx.txt)0
-rw-r--r--Bindings/arm/omap/crossbar.txt3
-rw-r--r--Bindings/arm/omap/omap.txt9
-rw-r--r--Bindings/arm/oxnas.txt9
-rw-r--r--Bindings/arm/pmu.txt12
-rw-r--r--Bindings/arm/qcom.txt51
-rw-r--r--Bindings/arm/rockchip.txt14
-rw-r--r--Bindings/arm/samsung/samsung-boards.txt2
-rw-r--r--Bindings/arm/spear-misc.txt2
-rw-r--r--Bindings/arm/sunxi.txt1
-rw-r--r--Bindings/arm/tegra/nvidia,tegra20-pmc.txt92
-rw-r--r--Bindings/arm/ux500/boards.txt2
-rw-r--r--Bindings/ata/ahci-platform.txt6
-rw-r--r--Bindings/ata/nvidia,tegra124-ahci.txt (renamed from Bindings/ata/tegra-sata.txt)0
-rw-r--r--Bindings/btmrvl.txt29
-rw-r--r--Bindings/clock/artpec6.txt41
-rw-r--r--Bindings/clock/axi-clkgen.txt5
-rw-r--r--Bindings/clock/axs10x-i2s-pll-clock.txt25
-rw-r--r--Bindings/clock/brcm,iproc-clocks.txt6
-rw-r--r--Bindings/clock/hi3519-crg.txt46
-rw-r--r--Bindings/clock/imx35-clock.txt1
-rw-r--r--Bindings/clock/lpc1850-creg-clk.txt52
-rw-r--r--Bindings/clock/microchip,pic32.txt39
-rw-r--r--Bindings/clock/nvidia,tegra124-dfll.txt2
-rw-r--r--Bindings/clock/oxnas,stdclk.txt35
-rw-r--r--Bindings/clock/qca,ath79-pll.txt6
-rw-r--r--Bindings/clock/qcom,gcc.txt1
-rw-r--r--Bindings/clock/renesas,cpg-mssr.txt2
-rw-r--r--Bindings/clock/rockchip,rk3036-cru.txt2
-rw-r--r--Bindings/clock/rockchip,rk3188-cru.txt2
-rw-r--r--Bindings/clock/rockchip,rk3288-cru.txt2
-rw-r--r--Bindings/clock/rockchip,rk3399-cru.txt62
-rw-r--r--Bindings/clock/st/st,clkgen.txt2
-rw-r--r--Bindings/clock/sunxi.txt10
-rw-r--r--Bindings/clock/ti/adpll.txt41
-rw-r--r--Bindings/clock/xgene.txt2
-rw-r--r--Bindings/cpufreq/nvidia,tegra124-cpufreq.txt (renamed from Bindings/cpufreq/tegra124-cpufreq.txt)0
-rw-r--r--Bindings/crypto/fsl-imx-scc.txt21
-rw-r--r--Bindings/crypto/samsung-sss.txt6
-rw-r--r--Bindings/devfreq/event/exynos-nocp.txt26
-rw-r--r--Bindings/devfreq/exynos-bus.txt409
-rw-r--r--Bindings/display/arm,hdlcd.txt79
-rw-r--r--Bindings/display/brcm,bcm-vc4.txt48
-rw-r--r--Bindings/display/bridge/analogix_dp.txt52
-rw-r--r--Bindings/display/exynos/exynos5433-decon.txt5
-rw-r--r--Bindings/display/exynos/exynos_dp.txt93
-rw-r--r--Bindings/display/exynos/exynos_dsim.txt3
-rw-r--r--Bindings/display/exynos/exynos_hdmi.txt27
-rw-r--r--Bindings/display/exynos/samsung-fimd.txt3
-rw-r--r--Bindings/display/fsl,dcu.txt15
-rw-r--r--Bindings/display/fsl,tcon.txt18
-rw-r--r--Bindings/display/hisilicon/dw-dsi.txt72
-rw-r--r--Bindings/display/hisilicon/hisi-ade.txt64
-rw-r--r--Bindings/display/imx/ldb.txt1
-rw-r--r--Bindings/display/mediatek/mediatek,disp.txt203
-rw-r--r--Bindings/display/mediatek/mediatek,dpi.txt35
-rw-r--r--Bindings/display/mediatek/mediatek,dsi.txt60
-rw-r--r--Bindings/display/msm/dsi.txt32
-rw-r--r--Bindings/display/msm/hdmi.txt46
-rw-r--r--Bindings/display/panel/innolux,at070tn92.txt7
-rw-r--r--Bindings/display/panel/lg,lp120up1.txt7
-rw-r--r--Bindings/display/panel/olimex,lcd-olinuxino-43-ts.txt7
-rw-r--r--Bindings/display/panel/ontat,yx700wv03.txt7
-rw-r--r--Bindings/display/panel/tpk,f07a-0102.txt8
-rw-r--r--Bindings/display/panel/tpk,f10a-0102.txt8
-rw-r--r--Bindings/display/panel/urt,umsh-8596md.txt16
-rw-r--r--Bindings/display/renesas,du.txt16
-rw-r--r--Bindings/display/rockchip/analogix_dp-rockchip.txt92
-rw-r--r--Bindings/display/rockchip/inno_hdmi-rockchip.txt50
-rw-r--r--Bindings/display/snps,arcpgu.txt35
-rw-r--r--Bindings/display/sunxi/sun4i-drm.txt258
-rw-r--r--Bindings/dma/arm-pl330.txt1
-rw-r--r--Bindings/dma/brcm,bcm2835-dma.txt26
-rw-r--r--Bindings/dma/fsl-imx-sdma.txt27
-rw-r--r--Bindings/dma/mmp-dma.txt2
-rw-r--r--Bindings/dma/mv-xor.txt5
-rw-r--r--Bindings/dma/nvidia,tegra20-apbdma.txt (renamed from Bindings/dma/tegra20-apbdma.txt)0
-rw-r--r--Bindings/dma/nvidia,tegra210-adma.txt55
-rw-r--r--Bindings/dma/qcom_bam_dma.txt2
-rw-r--r--Bindings/dma/qcom_hidma_mgmt.txt89
-rw-r--r--Bindings/dma/snps-dma.txt11
-rw-r--r--Bindings/dma/xilinx/xilinx_dma.txt2
-rw-r--r--Bindings/dma/xilinx/xilinx_vdma.txt36
-rw-r--r--Bindings/edac/apm-xgene-edac.txt10
-rw-r--r--Bindings/goldfish/audio.txt17
-rw-r--r--Bindings/goldfish/battery.txt17
-rw-r--r--Bindings/goldfish/events.txt17
-rw-r--r--Bindings/goldfish/pipe.txt17
-rw-r--r--Bindings/goldfish/tty.txt17
-rw-r--r--Bindings/gpio/gpio-74x164.txt4
-rw-r--r--Bindings/gpio/gpio-altera.txt4
-rw-r--r--Bindings/gpio/gpio-mcp23s08.txt4
-rw-r--r--Bindings/gpio/gpio-mpc8xxx.txt20
-rw-r--r--Bindings/gpio/gpio-pisosr.txt34
-rw-r--r--Bindings/gpio/gpio-ts4800.txt20
-rw-r--r--Bindings/gpio/gpio-xgene-sb.txt47
-rw-r--r--Bindings/gpio/gpio-xlp.txt3
-rw-r--r--Bindings/gpio/gpio.txt26
-rw-r--r--Bindings/gpio/ibm,ppc4xx-gpio.txt24
-rw-r--r--Bindings/gpio/microchip,pic32-gpio.txt49
-rw-r--r--Bindings/gpio/nvidia,tegra186-gpio.txt161
-rw-r--r--Bindings/gpio/wd,mbl-gpio.txt38
-rw-r--r--Bindings/gpu/nvidia,gk20a.txt37
-rw-r--r--Bindings/hsi/nokia-modem.txt12
-rw-r--r--Bindings/hwmon/ina2xx.txt1
-rw-r--r--Bindings/hwmon/ltc2978.txt1
-rw-r--r--Bindings/hwmon/nsa320-mcu.txt20
-rw-r--r--Bindings/hwmon/ntc_thermistor.txt1
-rw-r--r--Bindings/i2c/i2c-arb-gpio-challenge.txt4
-rw-r--r--Bindings/i2c/i2c-demux-pinctrl.txt136
-rw-r--r--Bindings/i2c/i2c-imx.txt2
-rw-r--r--Bindings/i2c/i2c-mux-gpio.txt6
-rw-r--r--Bindings/i2c/i2c-mux-pinctrl.txt4
-rw-r--r--Bindings/i2c/i2c-mux-reg.txt6
-rw-r--r--Bindings/i2c/i2c-octeon.txt6
-rw-r--r--Bindings/i2c/i2c-rcar.txt5
-rw-r--r--Bindings/i2c/i2c-rk3x.txt4
-rw-r--r--Bindings/i2c/i2c-sirf.txt2
-rw-r--r--Bindings/i2c/i2c-xiic.txt3
-rw-r--r--Bindings/iio/accel/mma8452.txt5
-rw-r--r--Bindings/iio/adc/at91-sama5d2_adc.txt28
-rw-r--r--Bindings/iio/adc/fsl,imx25-gcq.txt58
-rw-r--r--Bindings/iio/adc/lpc1850-adc.txt21
-rw-r--r--Bindings/iio/adc/mcp3422.txt1
-rw-r--r--Bindings/iio/adc/mxs-lradc.txt (renamed from Bindings/staging/iio/adc/mxs-lradc.txt)0
-rw-r--r--Bindings/iio/adc/rockchip-saradc.txt6
-rw-r--r--Bindings/iio/adc/ti-adc0832.txt19
-rw-r--r--Bindings/iio/chemical/atlas,ph-sm.txt22
-rw-r--r--Bindings/iio/dac/ad5592r.txt155
-rw-r--r--Bindings/iio/dac/lpc1850-dac.txt20
-rw-r--r--Bindings/iio/dac/vf610-dac.txt20
-rw-r--r--Bindings/iio/health/afe4403.txt34
-rw-r--r--Bindings/iio/health/afe4404.txt30
-rw-r--r--Bindings/iio/health/max30100.txt8
-rw-r--r--Bindings/iio/iio-bindings.txt2
-rw-r--r--Bindings/iio/imu/inv_mpu6050.txt13
-rw-r--r--Bindings/iio/light/opt3001.txt26
-rw-r--r--Bindings/iio/magnetometer/ak8975.txt12
-rw-r--r--Bindings/iio/potentiometer/ds1803.txt21
-rw-r--r--Bindings/iio/potentiometer/mcp4131.txt84
-rw-r--r--Bindings/iio/pressure/hp03.txt17
-rw-r--r--Bindings/iio/pressure/ms5611.txt19
-rw-r--r--Bindings/iio/st-sensors.txt6
-rw-r--r--Bindings/input/ads7846.txt2
-rw-r--r--Bindings/input/gpio-keys.txt10
-rw-r--r--Bindings/input/rmi4/rmi_2d_sensor.txt56
-rw-r--r--Bindings/input/rmi4/rmi_f01.txt39
-rw-r--r--Bindings/input/rmi4/rmi_i2c.txt53
-rw-r--r--Bindings/input/rmi4/rmi_spi.txt57
-rw-r--r--Bindings/input/rotary-encoder.txt2
-rw-r--r--Bindings/input/touchscreen/ad7879.txt53
-rw-r--r--Bindings/input/touchscreen/brcm,iproc-touchscreen.txt23
-rw-r--r--Bindings/input/touchscreen/cyttsp.txt95
-rw-r--r--Bindings/input/touchscreen/fsl-mx25-tcq.txt35
-rw-r--r--Bindings/input/touchscreen/touchscreen.txt2
-rw-r--r--Bindings/interrupt-controller/al,alpine-msix.txt26
-rw-r--r--Bindings/interrupt-controller/arm,gic-v3.txt37
-rw-r--r--Bindings/interrupt-controller/arm,gic.txt1
-rw-r--r--Bindings/interrupt-controller/arm,versatile-fpga-irq.txt2
-rw-r--r--Bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt4
-rw-r--r--Bindings/interrupt-controller/brcm,bcm6345-l1-intc.txt57
-rw-r--r--Bindings/interrupt-controller/ezchip,nps400-ic.txt17
-rw-r--r--Bindings/interrupt-controller/fsl,ls-scfg-msi.txt30
-rw-r--r--Bindings/interrupt-controller/hisilicon,mbigen-v2.txt22
-rw-r--r--Bindings/interrupt-controller/marvell,odmi-controller.txt44
-rw-r--r--Bindings/interrupt-controller/mediatek,sysirq.txt3
-rw-r--r--Bindings/interrupt-controller/mips-gic.txt7
-rw-r--r--Bindings/interrupt-controller/nvidia,tegra20-ictlr.txt (renamed from Bindings/interrupt-controller/nvidia,tegra-ictlr.txt)0
-rw-r--r--Bindings/interrupt-controller/nxp,lpc3220-mic.txt70
-rw-r--r--Bindings/interrupt-controller/sigma,smp8642-intc.txt49
-rw-r--r--Bindings/interrupt-controller/ti,omap4-wugen-mpu4
-rw-r--r--Bindings/iommu/arm,smmu.txt1
-rw-r--r--Bindings/iommu/mediatek,iommu.txt68
-rw-r--r--Bindings/iommu/renesas,ipmmu-vmsa.txt15
-rw-r--r--Bindings/iommu/samsung,sysmmu.txt22
-rw-r--r--Bindings/leds/common.txt3
-rw-r--r--Bindings/leds/leds-gpio.txt2
-rw-r--r--Bindings/leds/leds-is31fl32xx.txt52
-rw-r--r--Bindings/mailbox/hisilicon,hi6220-mailbox.txt74
-rw-r--r--Bindings/mailbox/rockchip-mailbox.txt32
-rw-r--r--Bindings/mailbox/sti-mailbox.txt2
-rw-r--r--Bindings/mailbox/ti,message-manager.txt50
-rw-r--r--Bindings/mailbox/xgene-slimpro-mailbox.txt35
-rw-r--r--Bindings/media/i2c/adv7180.txt29
-rw-r--r--Bindings/media/i2c/mt9v032.txt2
-rw-r--r--Bindings/media/i2c/tvp5150.txt45
-rw-r--r--Bindings/media/rcar_vin.txt13
-rw-r--r--Bindings/media/renesas,jpu.txt13
-rw-r--r--Bindings/media/renesas,vsp1.txt34
-rw-r--r--Bindings/media/ti-cal.txt72
-rw-r--r--Bindings/media/xilinx/video.txt2
-rw-r--r--Bindings/memory-controllers/exynos-srom.txt79
-rw-r--r--Bindings/memory-controllers/mediatek,smi-common.txt24
-rw-r--r--Bindings/memory-controllers/mediatek,smi-larb.txt25
-rw-r--r--Bindings/memory-controllers/nvidia,tegra124-emc.txt (renamed from Bindings/memory-controllers/tegra-emc.txt)4
-rw-r--r--Bindings/memory-controllers/nvidia,tegra30-mc.txt (renamed from Bindings/memory-controllers/nvidia,tegra-mc.txt)6
-rw-r--r--Bindings/memory-controllers/omap-gpmc.txt (renamed from Bindings/bus/ti-gpmc.txt)22
-rw-r--r--Bindings/mfd/act8945a.txt76
-rw-r--r--Bindings/mfd/arizona.txt2
-rw-r--r--Bindings/mfd/axp20x.txt36
-rw-r--r--Bindings/mfd/fsl-imx25-tsadc.txt47
-rw-r--r--Bindings/mfd/hisilicon,hi655x.txt27
-rw-r--r--Bindings/mfd/max77620.txt143
-rw-r--r--Bindings/mfd/mt6397.txt10
-rw-r--r--Bindings/mfd/qcom-rpm.txt4
-rw-r--r--Bindings/mfd/tps65086.txt55
-rw-r--r--Bindings/mfd/tps65912.txt50
-rw-r--r--Bindings/mips/brcm/soc.txt3
-rw-r--r--Bindings/mips/cavium/ciu3.txt27
-rw-r--r--Bindings/mips/cavium/sata-uctl.txt42
-rw-r--r--Bindings/mips/cpu_irq.txt2
-rw-r--r--Bindings/misc/eeprom-93xx46.txt25
-rw-r--r--Bindings/misc/fsl,qoriq-mc.txt81
-rw-r--r--Bindings/mmc/arasan,sdhci.txt20
-rw-r--r--Bindings/mmc/brcm,sdhci-iproc.txt5
-rw-r--r--Bindings/mmc/microchip,sdhci-pic32.txt29
-rw-r--r--Bindings/mmc/mmc-pwrseq-emmc.txt2
-rw-r--r--Bindings/mmc/rockchip-dw-mshc.txt3
-rw-r--r--Bindings/mmc/sdhci-st.txt4
-rw-r--r--Bindings/mmc/tmio_mmc.txt4
-rw-r--r--Bindings/mmc/usdhi6rol0.txt6
-rw-r--r--Bindings/mtd/arm-versatile.txt20
-rw-r--r--Bindings/mtd/atmel-nand.txt31
-rw-r--r--Bindings/mtd/brcm,brcmnand.txt3
-rw-r--r--Bindings/mtd/fsl-quadspi.txt6
-rw-r--r--Bindings/mtd/gpmc-nand.txt19
-rw-r--r--Bindings/mtd/nand.txt46
-rw-r--r--Bindings/mtd/qcom_nandc.txt86
-rw-r--r--Bindings/net/apm-xgene-enet.txt2
-rw-r--r--Bindings/net/arc_emac.txt7
-rw-r--r--Bindings/net/brcm,bcmgenet.txt4
-rw-r--r--Bindings/net/can/ifi_canfd.txt15
-rw-r--r--Bindings/net/can/rcar_can.txt22
-rw-r--r--Bindings/net/can/sja1000.txt3
-rw-r--r--Bindings/net/cavium-mdio.txt61
-rw-r--r--Bindings/net/cpsw.txt6
-rw-r--r--Bindings/net/dsa/dsa.txt2
-rw-r--r--Bindings/net/dsa/marvell.txt35
-rw-r--r--Bindings/net/emac_rockchip.txt8
-rw-r--r--Bindings/net/fsl-fec.txt3
-rw-r--r--Bindings/net/hisilicon-hns-dsaf.txt62
-rw-r--r--Bindings/net/hisilicon-hns-nic.txt39
-rw-r--r--Bindings/net/macb.txt2
-rw-r--r--Bindings/net/marvell-armada-370-neta.txt26
-rw-r--r--Bindings/net/marvell-bt-sd8xxx.txt56
-rw-r--r--Bindings/net/marvell-neta-bm.txt49
-rw-r--r--Bindings/net/mdio-mux-gpio.txt8
-rw-r--r--Bindings/net/mdio-mux.txt8
-rw-r--r--Bindings/net/mediatek-net.txt80
-rw-r--r--Bindings/net/micrel-ks8995.txt20
-rw-r--r--Bindings/net/microchip,enc28j60.txt59
-rw-r--r--Bindings/net/nfc/pn533-i2c.txt31
-rw-r--r--Bindings/net/phy.txt6
-rw-r--r--Bindings/net/renesas,ravb.txt4
-rw-r--r--Bindings/net/stmmac.txt56
-rw-r--r--Bindings/net/ti,dp83867.txt2
-rw-r--r--Bindings/net/wireless/marvell-sd8xxx.txt63
-rw-r--r--Bindings/net/wireless/qcom,ath10k.txt102
-rw-r--r--Bindings/net/wireless/ti,wlcore,spi.txt36
-rw-r--r--Bindings/numa.txt275
-rw-r--r--Bindings/nvmem/lpc1857-eeprom.txt28
-rw-r--r--Bindings/nvmem/mtk-efuse.txt36
-rw-r--r--Bindings/opp/opp.txt2
-rw-r--r--Bindings/pci/designware-pcie.txt17
-rw-r--r--Bindings/pci/fsl,imx6q-pcie.txt25
-rw-r--r--Bindings/pci/hisilicon-pcie.txt12
-rw-r--r--Bindings/pci/layerscape-pci.txt2
-rw-r--r--Bindings/pci/nvidia,tegra20-pcie.txt224
-rw-r--r--Bindings/pci/pci-armada8k.txt38
-rw-r--r--Bindings/pci/pci-keystone.txt1
-rw-r--r--Bindings/pci/pci-rcar-gen2.txt1
-rw-r--r--Bindings/pci/pci-thunder-ecam.txt30
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-rw-r--r--src/arm64/rockchip/rk3368.dtsi92
-rw-r--r--src/arm64/rockchip/rk3399-evb.dts (renamed from src/arm64/rockchip/rk3368-thermal.dtsi)124
-rw-r--r--src/arm64/rockchip/rk3399.dtsi1013
-rw-r--r--src/arm64/socionext/uniphier-ph1-ld20-ref.dts (renamed from src/arm64/socionext/uniphier-ph1-ld10-ref.dts)18
-rw-r--r--src/arm64/socionext/uniphier-ph1-ld20.dtsi (renamed from src/arm64/socionext/uniphier-ph1-ld10.dtsi)47
-rw-r--r--src/arm64/socionext/uniphier-pinctrl.dtsi15
-rw-r--r--src/arm64/socionext/uniphier-ref-daughter.dtsi50
-rw-r--r--src/arm64/socionext/uniphier-support-card.dtsi6
-rw-r--r--src/arm64/xilinx/zynqmp-ep108-clk.dtsi88
-rw-r--r--src/arm64/xilinx/zynqmp-ep108.dts1
-rw-r--r--src/arm64/xilinx/zynqmp.dtsi61
-rw-r--r--src/mips/brcm/bcm6328.dtsi51
-rw-r--r--src/mips/brcm/bcm6358.dtsi130
-rw-r--r--src/mips/brcm/bcm6368.dtsi34
-rw-r--r--src/mips/brcm/bcm7125.dtsi70
-rw-r--r--src/mips/brcm/bcm7346.dtsi7
-rw-r--r--src/mips/brcm/bcm7358.dtsi3
-rw-r--r--src/mips/brcm/bcm7360.dtsi43
-rw-r--r--src/mips/brcm/bcm7362.dtsi7
-rw-r--r--src/mips/brcm/bcm7420.dtsi78
-rw-r--r--src/mips/brcm/bcm7425.dtsi101
-rw-r--r--src/mips/brcm/bcm7435.dtsi144
-rw-r--r--src/mips/brcm/bcm96358nb4ser.dts46
-rw-r--r--src/mips/brcm/bcm96368mvwg.dts4
-rw-r--r--src/mips/brcm/bcm97125cbmb.dts24
-rw-r--r--src/mips/brcm/bcm97360svmb.dts8
-rw-r--r--src/mips/brcm/bcm97420c.dts28
-rw-r--r--src/mips/brcm/bcm97425svmb.dts28
-rw-r--r--src/mips/brcm/bcm97435svmb.dts38
-rw-r--r--src/mips/cavium-octeon/dlink_dsr-1000n.dts78
-rw-r--r--src/mips/cavium-octeon/octeon_3xxx.dts205
-rw-r--r--src/mips/cavium-octeon/octeon_3xxx.dtsi231
-rw-r--r--src/mips/cavium-octeon/ubnt_e100.dts59
-rw-r--r--src/mips/ingenic/jz4740.dtsi16
-rw-r--r--src/mips/lantiq/easy50712.dts2
-rw-r--r--src/mips/pic32/pic32mzda-clk.dtsi236
-rw-r--r--src/mips/pic32/pic32mzda.dtsi63
-rw-r--r--src/mips/pic32/pic32mzda_sk.dts5
-rw-r--r--src/mips/qca/ar9132.dtsi19
-rw-r--r--src/mips/qca/ar9132_tl_wr1043nd_v1.dts100
-rw-r--r--src/mips/qca/ar9331.dtsi155
-rw-r--r--src/mips/qca/ar9331_dpt_module.dts78
-rw-r--r--src/mips/qca/ar9331_dragino_ms14.dts102
-rw-r--r--src/mips/qca/ar9331_omega.dts78
-rw-r--r--src/mips/qca/ar9331_tl_mr3020.dts118
-rw-r--r--src/mips/ralink/mt7620a.dtsi2
-rw-r--r--src/mips/ralink/rt2880.dtsi2
-rw-r--r--src/mips/ralink/rt3050.dtsi2
-rw-r--r--src/mips/ralink/rt3883.dtsi2
-rw-r--r--src/mips/xilfpga/nexys4ddr.dts2
1295 files changed, 74819 insertions, 12132 deletions
diff --git a/Bindings/arc/archs-pct.txt b/Bindings/arc/archs-pct.txt
index 1ae98b87c640..e4b9dcee6d41 100644
--- a/Bindings/arc/archs-pct.txt
+++ b/Bindings/arc/archs-pct.txt
@@ -2,7 +2,7 @@
The ARC HS can be configured with a pipeline performance monitor for counting
CPU and cache events like cache misses and hits. Like conventional PCT there
-are 100+ hardware conditions dynamically mapped to upto 32 counters.
+are 100+ hardware conditions dynamically mapped to up to 32 counters.
It also supports overflow interrupts.
Required properties:
diff --git a/Bindings/arc/eznps.txt b/Bindings/arc/eznps.txt
new file mode 100644
index 000000000000..1aa50c640678
--- /dev/null
+++ b/Bindings/arc/eznps.txt
@@ -0,0 +1,7 @@
+EZchip NPS Network Processor Platforms Device Tree Bindings
+---------------------------------------------------------------------------
+
+Appliance main board with NPS400 ASIC.
+
+Required root node properties:
+ - compatible = "ezchip,arc-nps";
diff --git a/Bindings/arc/pct.txt b/Bindings/arc/pct.txt
index 7b9588444f20..4e874d9a38a6 100644
--- a/Bindings/arc/pct.txt
+++ b/Bindings/arc/pct.txt
@@ -2,7 +2,7 @@
The ARC700 can be configured with a pipeline performance monitor for counting
CPU and cache events like cache misses and hits. Like conventional PCT there
-are 100+ hardware conditions dynamically mapped to upto 32 counters
+are 100+ hardware conditions dynamically mapped to up to 32 counters
Note that:
* The ARC 700 PCT does not support interrupts; although HW events may be
diff --git a/Bindings/arm/altera/socfpga-eccmgr.txt b/Bindings/arm/altera/socfpga-eccmgr.txt
new file mode 100644
index 000000000000..5a6b16070a33
--- /dev/null
+++ b/Bindings/arm/altera/socfpga-eccmgr.txt
@@ -0,0 +1,99 @@
+Altera SoCFPGA ECC Manager
+This driver uses the EDAC framework to implement the SOCFPGA ECC Manager.
+The ECC Manager counts and corrects single bit errors and counts/handles
+double bit errors which are uncorrectable.
+
+Cyclone5 and Arria5 ECC Manager
+Required Properties:
+- compatible : Should be "altr,socfpga-ecc-manager"
+- #address-cells: must be 1
+- #size-cells: must be 1
+- ranges : standard definition, should translate from local addresses
+
+Subcomponents:
+
+L2 Cache ECC
+Required Properties:
+- compatible : Should be "altr,socfpga-l2-ecc"
+- reg : Address and size for ECC error interrupt clear registers.
+- interrupts : Should be single bit error interrupt, then double bit error
+ interrupt. Note the rising edge type.
+
+On Chip RAM ECC
+Required Properties:
+- compatible : Should be "altr,socfpga-ocram-ecc"
+- reg : Address and size for ECC error interrupt clear registers.
+- iram : phandle to On-Chip RAM definition.
+- interrupts : Should be single bit error interrupt, then double bit error
+ interrupt. Note the rising edge type.
+
+Example:
+
+ eccmgr: eccmgr@ffd08140 {
+ compatible = "altr,socfpga-ecc-manager";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ l2-ecc@ffd08140 {
+ compatible = "altr,socfpga-l2-ecc";
+ reg = <0xffd08140 0x4>;
+ interrupts = <0 36 1>, <0 37 1>;
+ };
+
+ ocram-ecc@ffd08144 {
+ compatible = "altr,socfpga-ocram-ecc";
+ reg = <0xffd08144 0x4>;
+ iram = <&ocram>;
+ interrupts = <0 178 1>, <0 179 1>;
+ };
+ };
+
+Arria10 SoCFPGA ECC Manager
+The Arria10 SoC ECC Manager handles the IRQs for each peripheral
+in a shared register instead of individual IRQs like the Cyclone5
+and Arria5. Therefore the device tree is different as well.
+
+Required Properties:
+- compatible : Should be "altr,socfpga-a10-ecc-manager"
+- altr,sysgr-syscon : phandle to Arria10 System Manager Block
+ containing the ECC manager registers.
+- #address-cells: must be 1
+- #size-cells: must be 1
+- interrupts : Should be single bit error interrupt, then double bit error
+ interrupt. Note the rising edge type.
+- ranges : standard definition, should translate from local addresses
+
+Subcomponents:
+
+L2 Cache ECC
+Required Properties:
+- compatible : Should be "altr,socfpga-a10-l2-ecc"
+- reg : Address and size for ECC error interrupt clear registers.
+
+On-Chip RAM ECC
+Required Properties:
+- compatible : Should be "altr,socfpga-a10-ocram-ecc"
+- reg : Address and size for ECC block registers.
+
+Example:
+
+ eccmgr: eccmgr@ffd06000 {
+ compatible = "altr,socfpga-a10-ecc-manager";
+ altr,sysmgr-syscon = <&sysmgr>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 IRQ_TYPE_LEVEL_HIGH>;
+ ranges;
+
+ l2-ecc@ffd06010 {
+ compatible = "altr,socfpga-a10-l2-ecc";
+ reg = <0xffd06010 0x4>;
+ };
+
+ ocram-ecc@ff8c3000 {
+ compatible = "altr,socfpga-a10-ocram-ecc";
+ reg = <0xff8c3000 0x90>;
+ };
+ };
diff --git a/Bindings/arm/amlogic.txt b/Bindings/arm/amlogic.txt
index 1dfee20eee74..fcc6f6c10803 100644
--- a/Bindings/arm/amlogic.txt
+++ b/Bindings/arm/amlogic.txt
@@ -13,8 +13,18 @@ Boards with the Amlogic Meson8b SoC shall have the following properties:
Required root node property:
compatible: "amlogic,meson8b";
+Boards with the Amlogic Meson GXBaby SoC shall have the following properties:
+ Required root node property:
+ compatible: "amlogic,meson-gxbb";
+
Board compatible values:
- "geniatech,atv1200" (Meson6)
- "minix,neo-x8" (Meson8)
- "tronfy,mxq" (Meson8b)
- "hardkernel,odroid-c1" (Meson8b)
+ - "tronsmart,vega-s95-pro", "tronsmart,vega-s95" (Meson gxbb)
+ - "tronsmart,vega-s95-meta", "tronsmart,vega-s95" (Meson gxbb)
+ - "tronsmart,vega-s95-telos", "tronsmart,vega-s95" (Meson gxbb)
+ - "hardkernel,odroid-c2" (Meson gxbb)
+ - "amlogic,p200" (Meson gxbb)
+ - "amlogic,p201" (Meson gxbb)
diff --git a/Bindings/arm/arm-boards b/Bindings/arm/arm-boards
index 1a709970e7f7..ab318a56fca2 100644
--- a/Bindings/arm/arm-boards
+++ b/Bindings/arm/arm-boards
@@ -93,6 +93,14 @@ Required nodes:
a core-module with regs and the compatible strings
"arm,core-module-versatile", "syscon"
+Optional nodes:
+
+- arm,versatile-ib2-syscon : if the Versatile has an IB2 interface
+ board mounted, this has a separate system controller that is
+ defined in this node.
+ Required properties:
+ compatible = "arm,versatile-ib2-syscon", "syscon"
+
ARM RealView Boards
-------------------
The RealView boards cover tailored evaluation boards that are used to explore
@@ -123,7 +131,9 @@ Required nodes:
- syscon: some subnode of the RealView SoC node must be a
system controller node pointing to the control registers,
- with the compatible string set to one of these tuples:
+ with the compatible string set to one of these:
+ "arm,realview-eb11mp-revb-syscon", "arm,realview-eb-syscon", "syscon"
+ "arm,realview-eb11mp-revc-syscon", "arm,realview-eb-syscon", "syscon"
"arm,realview-eb-syscon", "syscon"
"arm,realview-pb1176-syscon", "syscon"
"arm,realview-pb11mp-syscon", "syscon"
@@ -180,6 +190,7 @@ described under the RS1 memory mapping.
Required properties (in root node):
compatible = "arm,juno"; /* For Juno r0 board */
compatible = "arm,juno-r1"; /* For Juno r1 board */
+ compatible = "arm,juno-r2"; /* For Juno r2 board */
Required nodes:
The description for the board must include:
diff --git a/Bindings/arm/atmel-at91.txt b/Bindings/arm/atmel-at91.txt
index 7fd64ec9ee1d..e1f5ad855f14 100644
--- a/Bindings/arm/atmel-at91.txt
+++ b/Bindings/arm/atmel-at91.txt
@@ -41,6 +41,10 @@ compatible: must be one of:
- "atmel,sama5d43"
- "atmel,sama5d44"
+Chipid required properties:
+- compatible: Should be "atmel,sama5d2-chipid"
+- reg : Should contain registers location and length
+
PIT Timer required properties:
- compatible: Should be "atmel,at91sam9260-pit"
- reg: Should contain registers location and length
@@ -147,6 +151,65 @@ Example:
clocks = <&clk32k>;
};
+SHDWC SAMA5D2-Compatible Shutdown Controller
+
+1) shdwc node
+
+required properties:
+- compatible: should be "atmel,sama5d2-shdwc".
+- reg: should contain registers location and length
+- clocks: phandle to input clock.
+- #address-cells: should be one. The cell is the wake-up input index.
+- #size-cells: should be zero.
+
+optional properties:
+
+- debounce-delay-us: minimum wake-up inputs debouncer period in
+ microseconds. It's usually a board-related property.
+- atmel,wakeup-rtc-timer: boolean to enable Real-Time Clock wake-up.
+
+The node contains child nodes for each wake-up input that the platform uses.
+
+2) input nodes
+
+Wake-up input nodes are usually described in the "board" part of the Device
+Tree. Note also that input 0 is linked to the wake-up pin and is frequently
+used.
+
+Required properties:
+- reg: should contain the wake-up input index [0 - 15].
+
+Optional properties:
+- atmel,wakeup-active-high: boolean, the corresponding wake-up input described
+ by the child, forces the wake-up of the core power supply on a high level.
+ The default is to be active low.
+
+Example:
+
+On the SoC side:
+ shdwc@f8048010 {
+ compatible = "atmel,sama5d2-shdwc";
+ reg = <0xf8048010 0x10>;
+ clocks = <&clk32k>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ atmel,wakeup-rtc-timer;
+ };
+
+On the board side:
+ shdwc@f8048010 {
+ debounce-delay-us = <976>;
+
+ input@0 {
+ reg = <0>;
+ };
+
+ input@1 {
+ reg = <1>;
+ atmel,wakeup-active-high;
+ };
+ };
+
Special Function Registers (SFR)
Special Function Registers (SFR) manage specific aspects of the integrated
@@ -155,7 +218,7 @@ elsewhere.
required properties:
- compatible: Should be "atmel,<chip>-sfr", "syscon".
- <chip> can be "sama5d3" or "sama5d4".
+ <chip> can be "sama5d3", "sama5d4" or "sama5d2".
- reg: Should contain registers location and length
sfr@f0038000 {
diff --git a/Bindings/arm/axis.txt b/Bindings/arm/axis.txt
new file mode 100644
index 000000000000..ae345e1c8d2b
--- /dev/null
+++ b/Bindings/arm/axis.txt
@@ -0,0 +1,29 @@
+Axis Communications AB
+ARTPEC series SoC Device Tree Bindings
+
+ARTPEC-6 ARM SoC
+================
+
+Required root node properties:
+- compatible = "axis,artpec6";
+
+ARTPEC-6 System Controller
+--------------------------
+
+The ARTPEC-6 has a system controller with mixed functions controlling DMA, PCIe
+and resets.
+
+Required properties:
+- compatible: "axis,artpec6-syscon", "syscon"
+- reg: Address and length of the register bank.
+
+Example:
+ syscon {
+ compatible = "axis,artpec6-syscon", "syscon";
+ reg = <0xf8000000 0x48>;
+ };
+
+ARTPEC-6 Development board:
+---------------------------
+Required root node properties:
+- compatible = "axis,artpec6-dev-board", "axis,artpec6";
diff --git a/Bindings/arm/bcm/brcm,vulcan-soc.txt b/Bindings/arm/bcm/brcm,vulcan-soc.txt
new file mode 100644
index 000000000000..223ed3471c08
--- /dev/null
+++ b/Bindings/arm/bcm/brcm,vulcan-soc.txt
@@ -0,0 +1,10 @@
+Broadcom Vulcan device tree bindings
+------------------------------------
+
+Boards with Broadcom Vulcan shall have the following root property:
+
+Broadcom Vulcan Evaluation Board:
+ compatible = "brcm,vulcan-eval", "brcm,vulcan-soc";
+
+Generic Vulcan board:
+ compatible = "brcm,vulcan-soc";
diff --git a/Bindings/arm/cci.txt b/Bindings/arm/cci.txt
index aef1d200a9b2..0f2153e8fa7e 100644
--- a/Bindings/arm/cci.txt
+++ b/Bindings/arm/cci.txt
@@ -34,6 +34,7 @@ specific to ARM.
Definition: must contain one of the following:
"arm,cci-400"
"arm,cci-500"
+ "arm,cci-550"
- reg
Usage: required
@@ -99,8 +100,9 @@ specific to ARM.
"arm,cci-400-pmu,r0"
"arm,cci-400-pmu,r1"
"arm,cci-400-pmu" - DEPRECATED, permitted only where OS has
- secure acces to CCI registers
+ secure access to CCI registers
"arm,cci-500-pmu,r0"
+ "arm,cci-550-pmu,r0"
- reg:
Usage: required
Value type: Integer cells. A register entry, expressed
diff --git a/Bindings/arm/coresight.txt b/Bindings/arm/coresight.txt
index 62938eb9697f..93147c0c8a0e 100644
--- a/Bindings/arm/coresight.txt
+++ b/Bindings/arm/coresight.txt
@@ -19,6 +19,7 @@ its hardware characteristcs.
- "arm,coresight-etm3x", "arm,primecell";
- "arm,coresight-etm4x", "arm,primecell";
- "qcom,coresight-replicator1x", "arm,primecell";
+ - "arm,coresight-stm", "arm,primecell"; [1]
* reg: physical base address and length of the register
set(s) of the component.
@@ -36,6 +37,14 @@ its hardware characteristcs.
layout using the generic DT graph presentation found in
"bindings/graph.txt".
+* Additional required properties for System Trace Macrocells (STM):
+ * reg: along with the physical base address and length of the register
+ set as described above, another entry is required to describe the
+ mapping of the extended stimulus port area.
+
+ * reg-names: the only acceptable values are "stm-base" and
+ "stm-stimulus-base", each corresponding to the areas defined in "reg".
+
* Required properties for devices that don't show up on the AMBA bus, such as
non-configurable replicators:
@@ -202,3 +211,22 @@ Example:
};
};
};
+
+4. STM
+ stm@20100000 {
+ compatible = "arm,coresight-stm", "arm,primecell";
+ reg = <0 0x20100000 0 0x1000>,
+ <0 0x28000000 0 0x180000>;
+ reg-names = "stm-base", "stm-stimulus-base";
+
+ clocks = <&soc_smc50mhz>;
+ clock-names = "apb_pclk";
+ port {
+ stm_out_port: endpoint {
+ remote-endpoint = <&main_funnel_in_port2>;
+ };
+ };
+ };
+
+[1]. There is currently two version of STM: STM32 and STM500. Both
+have the same HW interface and as such don't need an explicit binding name.
diff --git a/Bindings/arm/cpus.txt b/Bindings/arm/cpus.txt
index ae9be074d09f..3f0cbbb8395f 100644
--- a/Bindings/arm/cpus.txt
+++ b/Bindings/arm/cpus.txt
@@ -167,6 +167,7 @@ nodes to be present and contain the properties described below.
"arm,cortex-r5"
"arm,cortex-r7"
"brcm,brahma-b15"
+ "brcm,vulcan"
"cavium,thunder"
"faraday,fa526"
"intel,sa110"
@@ -178,6 +179,7 @@ nodes to be present and contain the properties described below.
"marvell,sheeva-v5"
"nvidia,tegra132-denver"
"qcom,krait"
+ "qcom,kryo"
"qcom,scorpion"
- enable-method
Value type: <stringlist>
@@ -190,7 +192,6 @@ nodes to be present and contain the properties described below.
can be one of:
"allwinner,sun6i-a31"
"allwinner,sun8i-a23"
- "arm,psci"
"arm,realview-smp"
"brcm,bcm-nsp-smp"
"brcm,brahma-b15"
@@ -250,7 +251,7 @@ nodes to be present and contain the properties described below.
Usage: optional
Value type: <prop-encoded-array>
Definition: A u32 value that represents the running time dynamic
- power coefficient in units of mW/MHz/uVolt^2. The
+ power coefficient in units of mW/MHz/uV^2. The
coefficient can either be calculated from power
measurements or derived by analysis.
diff --git a/Bindings/arm/fsl.txt b/Bindings/arm/fsl.txt
index 752a685d926f..dbbc0952021c 100644
--- a/Bindings/arm/fsl.txt
+++ b/Bindings/arm/fsl.txt
@@ -135,6 +135,10 @@ LS1043A ARMv8 based RDB Board
Required root node properties:
- compatible = "fsl,ls1043a-rdb", "fsl,ls1043a";
+LS1043A ARMv8 based QDS Board
+Required root node properties:
+ - compatible = "fsl,ls1043a-qds", "fsl,ls1043a";
+
LS2080A ARMv8 based Simulator model
Required root node properties:
- compatible = "fsl,ls2080a-simu", "fsl,ls2080a";
diff --git a/Bindings/arm/fw-cfg.txt b/Bindings/arm/fw-cfg.txt
index 953fb640d9c4..fd54e1db2156 100644
--- a/Bindings/arm/fw-cfg.txt
+++ b/Bindings/arm/fw-cfg.txt
@@ -11,43 +11,9 @@ QEMU exposes the control and data register to ARM guests as memory mapped
registers; their location is communicated to the guest's UEFI firmware in the
DTB that QEMU places at the bottom of the guest's DRAM.
-The guest writes a selector value (a key) to the selector register, and then
-can read the corresponding data (produced by QEMU) via the data register. If
-the selected entry is writable, the guest can rewrite it through the data
-register.
+The authoritative guest-side hardware interface documentation to the fw_cfg
+device can be found in "docs/specs/fw_cfg.txt" in the QEMU source tree.
-The selector register takes keys in big endian byte order.
-
-The data register allows accesses with 8, 16, 32 and 64-bit width (only at
-offset 0 of the register). Accesses larger than a byte are interpreted as
-arrays, bundled together only for better performance. The bytes constituting
-such a word, in increasing address order, correspond to the bytes that would
-have been transferred by byte-wide accesses in chronological order.
-
-The interface allows guest firmware to download various parameters and blobs
-that affect how the firmware works and what tables it installs for the guest
-OS. For example, boot order of devices, ACPI tables, SMBIOS tables, kernel and
-initrd images for direct kernel booting, virtual machine UUID, SMP information,
-virtual NUMA topology, and so on.
-
-The authoritative registry of the valid selector values and their meanings is
-the QEMU source code; the structure of the data blobs corresponding to the
-individual key values is also defined in the QEMU source code.
-
-The presence of the registers can be verified by selecting the "signature" blob
-with key 0x0000, and reading four bytes from the data register. The returned
-signature is "QEMU".
-
-The outermost protocol (involving the write / read sequences of the control and
-data registers) is expected to be versioned, and/or described by feature bits.
-The interface revision / feature bitmap can be retrieved with key 0x0001. The
-blob to be read from the data register has size 4, and it is to be interpreted
-as a uint32_t value in little endian byte order. The current value
-(corresponding to the above outer protocol) is zero.
-
-The guest kernel is not expected to use these registers (although it is
-certainly allowed to); the device tree bindings are documented here because
-this is where device tree bindings reside in general.
Required properties:
diff --git a/Bindings/arm/hisilicon/hisilicon.txt b/Bindings/arm/hisilicon/hisilicon.txt
index e3ccab114006..83fe816ae050 100644
--- a/Bindings/arm/hisilicon/hisilicon.txt
+++ b/Bindings/arm/hisilicon/hisilicon.txt
@@ -1,29 +1,33 @@
Hisilicon Platforms Device Tree Bindings
----------------------------------------------------
-Hi6220 SoC
-Required root node properties:
- - compatible = "hisilicon,hi6220";
-
Hi4511 Board
Required root node properties:
- compatible = "hisilicon,hi3620-hi4511";
-HiP04 D01 Board
+Hi6220 SoC
Required root node properties:
- - compatible = "hisilicon,hip04-d01";
+ - compatible = "hisilicon,hi6220";
+
+HiKey Board
+Required root node properties:
+ - compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220";
HiP01 ca9x2 Board
Required root node properties:
- compatible = "hisilicon,hip01-ca9x2";
-HiKey Board
+HiP04 D01 Board
Required root node properties:
- - compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220";
+ - compatible = "hisilicon,hip04-d01";
HiP05 D02 Board
Required root node properties:
- compatible = "hisilicon,hip05-d02";
+HiP06 D03 Board
+Required root node properties:
+ - compatible = "hisilicon,hip06-d03";
+
Hisilicon system controller
Required properties:
diff --git a/Bindings/arm/keystone/keystone.txt b/Bindings/arm/keystone/keystone.txt
index 3090a8a008c0..48f6703a28c8 100644
--- a/Bindings/arm/keystone/keystone.txt
+++ b/Bindings/arm/keystone/keystone.txt
@@ -22,6 +22,8 @@ SoCs:
compatible = "ti,k2l", "ti,keystone"
- Keystone 2 Edison
compatible = "ti,k2e", "ti,keystone"
+- K2G
+ compatible = "ti,k2g", "ti,keystone"
Boards:
- Keystone 2 Hawking/Kepler EVM
@@ -32,3 +34,6 @@ Boards:
- Keystone 2 Edison EVM
compatible = "ti,k2e-evm", "ti,k2e", "ti,keystone"
+
+- K2G EVM
+ compatible = "ti,k2g-evm", "ti,k2g", "ti-keystone"
diff --git a/Bindings/arm/l2c2x0.txt b/Bindings/arm/l2c2x0.txt
index fe0398c5c77b..c453ab5553cd 100644
--- a/Bindings/arm/l2c2x0.txt
+++ b/Bindings/arm/l2c2x0.txt
@@ -84,6 +84,12 @@ Optional properties:
- prefetch-instr : Instruction prefetch. Value: <0> (forcibly disable),
<1> (forcibly enable), property absent (retain settings set by
firmware)
+- arm,dynamic-clock-gating : L2 dynamic clock gating. Value: <0> (forcibly
+ disable), <1> (forcibly enable), property absent (OS specific behavior,
+ preferrably retain firmware settings)
+- arm,standby-mode: L2 standby mode enable. Value <0> (forcibly disable),
+ <1> (forcibly enable), property absent (OS specific behavior,
+ preferrably retain firmware settings)
Example:
diff --git a/Bindings/arm/marvell/ap806-system-controller.txt b/Bindings/arm/marvell/ap806-system-controller.txt
new file mode 100644
index 000000000000..8968371d84e2
--- /dev/null
+++ b/Bindings/arm/marvell/ap806-system-controller.txt
@@ -0,0 +1,35 @@
+Marvell Armada AP806 System Controller
+======================================
+
+The AP806 is one of the two core HW blocks of the Marvell Armada 7K/8K
+SoCs. It contains a system controller, which provides a number
+registers giving access to numerous features: clocks, pin-muxing and
+many other SoC configuration items. This DT binding allows to describe
+this system controller.
+
+The Device Tree node representing the AP806 system controller provides
+a number of clocks:
+
+ - 0: clock of CPU cluster 0
+ - 1: clock of CPU cluster 1
+ - 2: fixed PLL at 1200 Mhz
+ - 3: MSS clock, derived from the fixed PLL
+
+Required properties:
+
+ - compatible: must be:
+ "marvell,ap806-system-controller", "syscon"
+ - reg: register area of the AP806 system controller
+ - #clock-cells: must be set to 1
+ - clock-output-names: must be defined to:
+ "ap-cpu-cluster-0", "ap-cpu-cluster-1", "ap-fixed", "ap-mss"
+
+Example:
+
+ syscon: system-controller@6f4000 {
+ compatible = "marvell,ap806-system-controller", "syscon";
+ #clock-cells = <1>;
+ clock-output-names = "ap-cpu-cluster-0", "ap-cpu-cluster-1",
+ "ap-fixed", "ap-mss";
+ reg = <0x6f4000 0x1000>;
+ };
diff --git a/Bindings/arm/armada-370-xp-pmsu.txt b/Bindings/arm/marvell/armada-370-xp-pmsu.txt
index 26799ef562df..26799ef562df 100644
--- a/Bindings/arm/armada-370-xp-pmsu.txt
+++ b/Bindings/arm/marvell/armada-370-xp-pmsu.txt
diff --git a/Bindings/arm/armada-370-xp.txt b/Bindings/arm/marvell/armada-370-xp.txt
index c6ed90ea6e17..c6ed90ea6e17 100644
--- a/Bindings/arm/armada-370-xp.txt
+++ b/Bindings/arm/marvell/armada-370-xp.txt
diff --git a/Bindings/arm/armada-375.txt b/Bindings/arm/marvell/armada-375.txt
index 867d0b80cb8f..867d0b80cb8f 100644
--- a/Bindings/arm/armada-375.txt
+++ b/Bindings/arm/marvell/armada-375.txt
diff --git a/Bindings/arm/marvell/armada-37xx.txt b/Bindings/arm/marvell/armada-37xx.txt
new file mode 100644
index 000000000000..51336e5fc761
--- /dev/null
+++ b/Bindings/arm/marvell/armada-37xx.txt
@@ -0,0 +1,16 @@
+Marvell Armada 37xx Platforms Device Tree Bindings
+--------------------------------------------------
+
+Boards using a SoC of the Marvell Armada 37xx family must carry the
+following root node property:
+
+ - compatible: must contain "marvell,armada3710"
+
+In addition, boards using the Marvell Armada 3720 SoC shall have the
+following property before the previous one:
+
+ - compatible: must contain "marvell,armada3720"
+
+Example:
+
+compatible = "marvell,armada-3720-db", "marvell,armada3720", "marvell,armada3710";
diff --git a/Bindings/arm/armada-380-mpcore-soc-ctrl.txt b/Bindings/arm/marvell/armada-380-mpcore-soc-ctrl.txt
index 8781073029e9..8781073029e9 100644
--- a/Bindings/arm/armada-380-mpcore-soc-ctrl.txt
+++ b/Bindings/arm/marvell/armada-380-mpcore-soc-ctrl.txt
diff --git a/Bindings/arm/armada-38x.txt b/Bindings/arm/marvell/armada-38x.txt
index 202953f1887e..202953f1887e 100644
--- a/Bindings/arm/armada-38x.txt
+++ b/Bindings/arm/marvell/armada-38x.txt
diff --git a/Bindings/arm/armada-39x.txt b/Bindings/arm/marvell/armada-39x.txt
index 53d4ff9ea8ad..53d4ff9ea8ad 100644
--- a/Bindings/arm/armada-39x.txt
+++ b/Bindings/arm/marvell/armada-39x.txt
diff --git a/Bindings/arm/marvell/armada-7k-8k.txt b/Bindings/arm/marvell/armada-7k-8k.txt
new file mode 100644
index 000000000000..df98a9c82a8c
--- /dev/null
+++ b/Bindings/arm/marvell/armada-7k-8k.txt
@@ -0,0 +1,24 @@
+Marvell Armada 7K/8K Platforms Device Tree Bindings
+---------------------------------------------------
+
+Boards using a SoC of the Marvell Armada 7K or 8K families must carry
+the following root node property:
+
+ - compatible, with one of the following values:
+
+ - "marvell,armada7020", "marvell,armada-ap806-dual", "marvell,armada-ap806"
+ when the SoC being used is the Armada 7020
+
+ - "marvell,armada7040", "marvell,armada-ap806-quad", "marvell,armada-ap806"
+ when the SoC being used is the Armada 7040
+
+ - "marvell,armada8020", "marvell,armada-ap806-dual", "marvell,armada-ap806"
+ when the SoC being used is the Armada 8020
+
+ - "marvell,armada8040", "marvell,armada-ap806-quad", "marvell,armada-ap806"
+ when the SoC being used is the Armada 8040
+
+Example:
+
+compatible = "marvell,armada7040-db", "marvell,armada7040",
+ "marvell,armada-ap806-quad", "marvell,armada-ap806";
diff --git a/Bindings/arm/armada-cpu-reset.txt b/Bindings/arm/marvell/armada-cpu-reset.txt
index b63a7b6ab998..b63a7b6ab998 100644
--- a/Bindings/arm/armada-cpu-reset.txt
+++ b/Bindings/arm/marvell/armada-cpu-reset.txt
diff --git a/Bindings/arm/coherency-fabric.txt b/Bindings/arm/marvell/coherency-fabric.txt
index 9b5c3f620e65..9b5c3f620e65 100644
--- a/Bindings/arm/coherency-fabric.txt
+++ b/Bindings/arm/marvell/coherency-fabric.txt
diff --git a/Bindings/arm/marvell/cp110-system-controller0.txt b/Bindings/arm/marvell/cp110-system-controller0.txt
new file mode 100644
index 000000000000..30c546900b60
--- /dev/null
+++ b/Bindings/arm/marvell/cp110-system-controller0.txt
@@ -0,0 +1,83 @@
+Marvell Armada CP110 System Controller 0
+========================================
+
+The CP110 is one of the two core HW blocks of the Marvell Armada 7K/8K
+SoCs. It contains two sets of system control registers, System
+Controller 0 and System Controller 1. This Device Tree binding allows
+to describe the first system controller, which provides registers to
+configure various aspects of the SoC.
+
+The Device Tree node representing this System Controller 0 provides a
+number of clocks:
+
+ - a set of core clocks
+ - a set of gatable clocks
+
+Those clocks can be referenced by other Device Tree nodes using two
+cells:
+ - The first cell must be 0 or 1. 0 for the core clocks and 1 for the
+ gatable clocks.
+ - The second cell identifies the particular core clock or gatable
+ clocks.
+
+The following clocks are available:
+ - Core clocks
+ - 0 0 APLL
+ - 0 1 PPv2 core
+ - 0 2 EIP
+ - 0 3 Core
+ - 0 4 NAND core
+ - Gatable clocks
+ - 1 0 Audio
+ - 1 1 Comm Unit
+ - 1 2 NAND
+ - 1 3 PPv2
+ - 1 4 SDIO
+ - 1 5 MG Domain
+ - 1 6 MG Core
+ - 1 7 XOR1
+ - 1 8 XOR0
+ - 1 9 GOP DP
+ - 1 11 PCIe x1 0
+ - 1 12 PCIe x1 1
+ - 1 13 PCIe x4
+ - 1 14 PCIe / XOR
+ - 1 15 SATA
+ - 1 16 SATA USB
+ - 1 17 Main
+ - 1 18 SD/MMC
+ - 1 21 Slow IO (SPI, NOR, BootROM, I2C, UART)
+ - 1 22 USB3H0
+ - 1 23 USB3H1
+ - 1 24 USB3 Device
+ - 1 25 EIP150
+ - 1 26 EIP197
+
+Required properties:
+
+ - compatible: must be:
+ "marvell,cp110-system-controller0", "syscon";
+ - reg: register area of the CP110 system controller 0
+ - #clock-cells: must be set to 2
+ - core-clock-output-names must be set to:
+ "cpm-apll", "cpm-ppv2-core", "cpm-eip", "cpm-core", "cpm-nand-core"
+ - gate-clock-output-names must be set to:
+ "cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio",
+ "cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "none",
+ "cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata",
+ "cpm-sata-usb", "cpm-main", "cpm-sd-mmc", "none", "none", "cpm-slow-io",
+ "cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", "cpm-eip197";
+
+Example:
+
+ cpm_syscon0: system-controller@440000 {
+ compatible = "marvell,cp110-system-controller0", "syscon";
+ reg = <0x440000 0x1000>;
+ #clock-cells = <2>;
+ core-clock-output-names = "cpm-apll", "cpm-ppv2-core", "cpm-eip", "cpm-core", "cpm-nand-core";
+ gate-clock-output-names = "cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio",
+ "cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "none",
+ "cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata",
+ "cpm-sata-usb", "cpm-main", "cpm-sd-mmc", "none", "none", "cpm-slow-io",
+ "cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", "cpm-eip197";
+ };
diff --git a/Bindings/arm/kirkwood.txt b/Bindings/arm/marvell/kirkwood.txt
index 98cce9a653eb..98cce9a653eb 100644
--- a/Bindings/arm/kirkwood.txt
+++ b/Bindings/arm/marvell/kirkwood.txt
diff --git a/Bindings/arm/marvell,berlin.txt b/Bindings/arm/marvell/marvell,berlin.txt
index 3bab18409b7a..3bab18409b7a 100644
--- a/Bindings/arm/marvell,berlin.txt
+++ b/Bindings/arm/marvell/marvell,berlin.txt
diff --git a/Bindings/arm/marvell,dove.txt b/Bindings/arm/marvell/marvell,dove.txt
index aaaf64c56e44..aaaf64c56e44 100644
--- a/Bindings/arm/marvell,dove.txt
+++ b/Bindings/arm/marvell/marvell,dove.txt
diff --git a/Bindings/arm/marvell,kirkwood.txt b/Bindings/arm/marvell/marvell,kirkwood.txt
index ab0c9cdf388e..7d28fe4bf654 100644
--- a/Bindings/arm/marvell,kirkwood.txt
+++ b/Bindings/arm/marvell/marvell,kirkwood.txt
@@ -19,9 +19,12 @@ SoC. Currently known SoC compatibles are:
And in addition, the compatible shall be extended with the specific
board. Currently known boards are:
+"buffalo,linkstation-lsqvl"
+"buffalo,linkstation-lsvl"
+"buffalo,linkstation-lswsxl"
+"buffalo,linkstation-lswxl"
+"buffalo,linkstation-lswvl"
"buffalo,lschlv2"
-"buffalo,lswvl"
-"buffalo,lswxl"
"buffalo,lsxhl"
"buffalo,lsxl"
"cloudengines,pogo02"
diff --git a/Bindings/arm/mvebu-cpu-config.txt b/Bindings/arm/marvell/mvebu-cpu-config.txt
index 2cdcd716da40..2cdcd716da40 100644
--- a/Bindings/arm/mvebu-cpu-config.txt
+++ b/Bindings/arm/marvell/mvebu-cpu-config.txt
diff --git a/Bindings/arm/mvebu-system-controller.txt b/Bindings/arm/marvell/mvebu-system-controller.txt
index d24ab2ebf8a7..d24ab2ebf8a7 100644
--- a/Bindings/arm/mvebu-system-controller.txt
+++ b/Bindings/arm/marvell/mvebu-system-controller.txt
diff --git a/Bindings/arm/mediatek.txt b/Bindings/arm/mediatek.txt
index 54f43bc2df44..d9c2a37a4090 100644
--- a/Bindings/arm/mediatek.txt
+++ b/Bindings/arm/mediatek.txt
@@ -11,6 +11,7 @@ compatible: Must contain one of
"mediatek,mt6589"
"mediatek,mt6592"
"mediatek,mt6795"
+ "mediatek,mt7623"
"mediatek,mt8127"
"mediatek,mt8135"
"mediatek,mt8173"
@@ -33,6 +34,9 @@ Supported boards:
- Evaluation board for MT6795(Helio X10):
Required root node properties:
- compatible = "mediatek,mt6795-evb", "mediatek,mt6795";
+- Evaluation board for MT7623:
+ Required root node properties:
+ - compatible = "mediatek,mt7623-evb", "mediatek,mt7623";
- MTK mt8127 tablet moose EVB:
Required root node properties:
- compatible = "mediatek,mt8127-moose", "mediatek,mt8127";
diff --git a/Bindings/arm/lpc32xx.txt b/Bindings/arm/nxp/lpc32xx.txt
index 56ec8ddc4a3b..56ec8ddc4a3b 100644
--- a/Bindings/arm/lpc32xx.txt
+++ b/Bindings/arm/nxp/lpc32xx.txt
diff --git a/Bindings/arm/omap/crossbar.txt b/Bindings/arm/omap/crossbar.txt
index a9b28d74d902..bb5727ae004a 100644
--- a/Bindings/arm/omap/crossbar.txt
+++ b/Bindings/arm/omap/crossbar.txt
@@ -42,7 +42,8 @@ Examples:
Consumer:
========
See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt and
-Documentation/devicetree/bindings/arm/gic.txt for further details.
+Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt for
+further details.
An interrupt consumer on an SoC using crossbar will use:
interrupts = <GIC_SPI request_number interrupt_level>
diff --git a/Bindings/arm/omap/omap.txt b/Bindings/arm/omap/omap.txt
index a2bd593881ca..94b57f247615 100644
--- a/Bindings/arm/omap/omap.txt
+++ b/Bindings/arm/omap/omap.txt
@@ -23,6 +23,7 @@ Optional properties:
during suspend.
- ti,no-reset-on-init: When present, the module should not be reset at init
- ti,no-idle-on-init: When present, the module should not be idled at init
+- ti,no-idle: When present, the module is never allowed to idle.
Example:
@@ -132,6 +133,9 @@ Boards:
- AM335X Bone : Low cost community board
compatible = "ti,am335x-bone", "ti,am33xx", "ti,omap3"
+- AM3359 ICEv2 : Low cost Industrial Communication Engine EVM.
+ compatible = "ti,am3359-icev2", "ti,am33xx", "ti,omap3"
+
- AM335X OrionLXm : Substation Automation Platform
compatible = "novatech,am335x-lxm", "ti,am33xx"
@@ -154,7 +158,7 @@ Boards:
compatible = "compulab,am437x-sbc-t43", "compulab,am437x-cm-t43", "ti,am4372", "ti,am43"
- AM43x EPOS EVM
- compatible = "ti,am43x-epos-evm", "ti,am4372", "ti,am43"
+ compatible = "ti,am43x-epos-evm", "ti,am43", "ti,am438x"
- AM437x GP EVM
compatible = "ti,am437x-gp-evm", "ti,am4372", "ti,am43"
@@ -168,6 +172,9 @@ Boards:
- AM57XX SBC-AM57x
compatible = "compulab,sbc-am57x", "compulab,cl-som-am57x", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"
+- AM5728 IDK
+ compatible = "ti,am5728-idk", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"
+
- DRA742 EVM: Software Development Board for DRA742
compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"
diff --git a/Bindings/arm/oxnas.txt b/Bindings/arm/oxnas.txt
new file mode 100644
index 000000000000..b9e49711ba05
--- /dev/null
+++ b/Bindings/arm/oxnas.txt
@@ -0,0 +1,9 @@
+Oxford Semiconductor OXNAS SoCs Family device tree bindings
+-------------------------------------------
+
+Boards with the OX810SE SoC shall have the following properties:
+ Required root node property:
+ compatible: "oxsemi,ox810se"
+
+Board compatible values:
+ - "wd,mbwe" (OX810SE)
diff --git a/Bindings/arm/pmu.txt b/Bindings/arm/pmu.txt
index 56518839f52a..74d5417d0410 100644
--- a/Bindings/arm/pmu.txt
+++ b/Bindings/arm/pmu.txt
@@ -22,6 +22,8 @@ Required properties:
"arm,arm11mpcore-pmu"
"arm,arm1176-pmu"
"arm,arm1136-pmu"
+ "brcm,vulcan-pmu"
+ "cavium,thunder-pmu"
"qcom,scorpion-pmu"
"qcom,scorpion-mp-pmu"
"qcom,krait-pmu"
@@ -46,6 +48,16 @@ Optional properties:
- qcom,no-pc-write : Indicates that this PMU doesn't support the 0xc and 0xd
events.
+- secure-reg-access : Indicates that the ARMv7 Secure Debug Enable Register
+ (SDER) is accessible. This will cause the driver to do
+ any setup required that is only possible in ARMv7 secure
+ state. If not present the ARMv7 SDER will not be touched,
+ which means the PMU may fail to operate unless external
+ code (bootloader or security monitor) has performed the
+ appropriate initialisation. Note that this property is
+ not valid for non-ARMv7 CPUs or ARMv7 CPUs booting Linux
+ in Non-secure state.
+
Example:
pmu {
diff --git a/Bindings/arm/qcom.txt b/Bindings/arm/qcom.txt
new file mode 100644
index 000000000000..3e24518c6678
--- /dev/null
+++ b/Bindings/arm/qcom.txt
@@ -0,0 +1,51 @@
+QCOM device tree bindings
+-------------------------
+
+Some qcom based bootloaders identify the dtb blob based on a set of
+device properties like SoC and platform and revisions of those components.
+To support this scheme, we encode this information into the board compatible
+string.
+
+Each board must specify a top-level board compatible string with the following
+format:
+
+ compatible = "qcom,<SoC>[-<soc_version>][-<foundry_id>]-<board>[/<subtype>][-<board_version>]"
+
+The 'SoC' and 'board' elements are required. All other elements are optional.
+
+The 'SoC' element must be one of the following strings:
+
+ apq8016
+ apq8074
+ apq8084
+ apq8096
+ msm8916
+ msm8974
+ msm8996
+
+The 'board' element must be one of the following strings:
+
+ cdp
+ liquid
+ dragonboard
+ mtp
+ sbc
+
+The 'soc_version' and 'board_version' elements take the form of v<Major>.<Minor>
+where the minor number may be omitted when it's zero, i.e. v1.0 is the same
+as v1. If all versions of the 'board_version' elements match, then a
+wildcard '*' should be used, e.g. 'v*'.
+
+The 'foundry_id' and 'subtype' elements are one or more digits from 0 to 9.
+
+Examples:
+
+ "qcom,msm8916-v1-cdp-pm8916-v2.1"
+
+A CDP board with an msm8916 SoC, version 1 paired with a pm8916 PMIC of version
+2.1.
+
+ "qcom,apq8074-v2.0-2-dragonboard/1-v0.1"
+
+A dragonboard board v0.1 of subtype 1 with an apq8074 SoC version 2, made in
+foundry 2.
diff --git a/Bindings/arm/rockchip.txt b/Bindings/arm/rockchip.txt
index 078c14fcdaaa..715d960d5eea 100644
--- a/Bindings/arm/rockchip.txt
+++ b/Bindings/arm/rockchip.txt
@@ -39,6 +39,10 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "netxeon,r89", "rockchip,rk3288";
+- GeekBuying GeekBox:
+ Required root node properties:
+ - compatible = "geekbuying,geekbox", "rockchip,rk3368";
+
- Google Brain (dev-board):
Required root node properties:
- compatible = "google,veyron-brain-rev0", "google,veyron-brain",
@@ -87,6 +91,10 @@ Rockchip platforms device tree bindings
"google,veyron-speedy-rev3", "google,veyron-speedy-rev2",
"google,veyron-speedy", "google,veyron", "rockchip,rk3288";
+- mqmaker MiQi:
+ Required root node properties:
+ - compatible = "mqmaker,miqi", "rockchip,rk3288";
+
- Rockchip RK3368 evb:
Required root node properties:
- compatible = "rockchip,rk3368-evb-act8846", "rockchip,rk3368";
@@ -97,4 +105,8 @@ Rockchip platforms device tree bindings
- Rockchip RK3228 Evaluation board:
Required root node properties:
- - compatible = "rockchip,rk3228-evb", "rockchip,rk3228";
+ - compatible = "rockchip,rk3228-evb", "rockchip,rk3228";
+
+- Rockchip RK3399 evb:
+ Required root node properties:
+ - compatible = "rockchip,rk3399-evb", "rockchip,rk3399";
diff --git a/Bindings/arm/samsung/samsung-boards.txt b/Bindings/arm/samsung/samsung-boards.txt
index 12129c011c8f..f5deace2b380 100644
--- a/Bindings/arm/samsung/samsung-boards.txt
+++ b/Bindings/arm/samsung/samsung-boards.txt
@@ -2,6 +2,8 @@
Required root node properties:
- compatible = should be one or more of the following.
+ - "samsung,artik5" - for Exynos3250-based Samsung ARTIK5 module.
+ - "samsung,artik5-eval" - for Exynos3250-based Samsung ARTIK5 eval board.
- "samsung,monk" - for Exynos3250-based Samsung Simband board.
- "samsung,rinato" - for Exynos3250-based Samsung Gear2 board.
- "samsung,smdkv310" - for Exynos4210-based Samsung SMDKV310 eval board.
diff --git a/Bindings/arm/spear-misc.txt b/Bindings/arm/spear-misc.txt
index cf649827ffcd..e404e2556b4a 100644
--- a/Bindings/arm/spear-misc.txt
+++ b/Bindings/arm/spear-misc.txt
@@ -6,4 +6,4 @@ few properties of different peripheral controllers.
misc node required properties:
- compatible Should be "st,spear1340-misc", "syscon".
-- reg: Address range of misc space upto 8K
+- reg: Address range of misc space up to 8K
diff --git a/Bindings/arm/sunxi.txt b/Bindings/arm/sunxi.txt
index bb9b0faa919d..7e79fcc36b0d 100644
--- a/Bindings/arm/sunxi.txt
+++ b/Bindings/arm/sunxi.txt
@@ -11,5 +11,6 @@ using one of the following compatible strings:
allwinner,sun7i-a20
allwinner,sun8i-a23
allwinner,sun8i-a33
+ allwinner,sun8i-a83t
allwinner,sun8i-h3
allwinner,sun9i-a80
diff --git a/Bindings/arm/tegra/nvidia,tegra20-pmc.txt b/Bindings/arm/tegra/nvidia,tegra20-pmc.txt
index 02c27004d4a8..a74b37b07e5c 100644
--- a/Bindings/arm/tegra/nvidia,tegra20-pmc.txt
+++ b/Bindings/arm/tegra/nvidia,tegra20-pmc.txt
@@ -1,16 +1,20 @@
NVIDIA Tegra Power Management Controller (PMC)
+== Power Management Controller Node ==
+
The PMC block interacts with an external Power Management Unit. The PMC
mostly controls the entry and exit of the system from different sleep
modes. It provides power-gating controllers for SoC and CPU power-islands.
Required properties:
- name : Should be pmc
-- compatible : For Tegra20, must contain "nvidia,tegra20-pmc". For Tegra30,
- must contain "nvidia,tegra30-pmc". For Tegra114, must contain
- "nvidia,tegra114-pmc". For Tegra124, must contain "nvidia,tegra124-pmc".
- Otherwise, must contain "nvidia,<chip>-pmc", plus at least one of the
- above, where <chip> is tegra132.
+- compatible : Should contain one of the following:
+ For Tegra20 must contain "nvidia,tegra20-pmc".
+ For Tegra30 must contain "nvidia,tegra30-pmc".
+ For Tegra114 must contain "nvidia,tegra114-pmc"
+ For Tegra124 must contain "nvidia,tegra124-pmc"
+ For Tegra132 must contain "nvidia,tegra124-pmc"
+ For Tegra210 must contain "nvidia,tegra210-pmc"
- reg : Offset and length of the register set for the device
- clocks : Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
@@ -68,6 +72,11 @@ Optional properties for hardware-triggered thermal reset (inside 'i2c-thermtrip'
Defaults to 0. Valid values are described in section 12.5.2
"Pinmux Support" of the Tegra4 Technical Reference Manual.
+Optional nodes:
+- powergates : This node contains a hierarchy of power domain nodes, which
+ should match the powergates on the Tegra SoC. See "Powergate
+ Nodes" below.
+
Example:
/ SoC dts including file
@@ -113,3 +122,76 @@ pmc@7000f400 {
};
...
};
+
+
+== Powergate Nodes ==
+
+Each of the powergate nodes represents a power-domain on the Tegra SoC
+that can be power-gated by the Tegra PMC. The name of the powergate node
+should be one of the below. Note that not every powergate is applicable
+to all Tegra devices and the following list shows which powergates are
+applicable to which devices. Please refer to the Tegra TRM for more
+details on the various powergates.
+
+ Name Description Devices Applicable
+ 3d 3D Graphics Tegra20/114/124/210
+ 3d0 3D Graphics 0 Tegra30
+ 3d1 3D Graphics 1 Tegra30
+ aud Audio Tegra210
+ dfd Debug Tegra210
+ dis Display A Tegra114/124/210
+ disb Display B Tegra114/124/210
+ heg 2D Graphics Tegra30/114/124/210
+ iram Internal RAM Tegra124/210
+ mpe MPEG Encode All
+ nvdec NVIDIA Video Decode Engine Tegra210
+ nvjpg NVIDIA JPEG Engine Tegra210
+ pcie PCIE Tegra20/30/124/210
+ sata SATA Tegra30/124/210
+ sor Display interfaces Tegra124/210
+ ve2 Video Encode Engine 2 Tegra210
+ venc Video Encode Engine All
+ vdec Video Decode Engine Tegra20/30/114/124
+ vic Video Imaging Compositor Tegra124/210
+ xusba USB Partition A Tegra114/124/210
+ xusbb USB Partition B Tegra114/124/210
+ xusbc USB Partition C Tegra114/124/210
+
+Required properties:
+ - clocks: Must contain an entry for each clock required by the PMC for
+ controlling a power-gate. See ../clocks/clock-bindings.txt for details.
+ - resets: Must contain an entry for each reset required by the PMC for
+ controlling a power-gate. See ../reset/reset.txt for details.
+ - #power-domain-cells: Must be 0.
+
+Example:
+
+ pmc: pmc@7000e400 {
+ compatible = "nvidia,tegra210-pmc";
+ reg = <0x0 0x7000e400 0x0 0x400>;
+ clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
+ clock-names = "pclk", "clk32k_in";
+
+ powergates {
+ pd_audio: aud {
+ clocks = <&tegra_car TEGRA210_CLK_APE>,
+ <&tegra_car TEGRA210_CLK_APB2APE>;
+ resets = <&tegra_car 198>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+
+
+== Powergate Clients ==
+
+Hardware blocks belonging to a power domain should contain a "power-domains"
+property that is a phandle pointing to the corresponding powergate node.
+
+Example:
+
+ adma: adma@702e2000 {
+ ...
+ power-domains = <&pd_audio>;
+ ...
+ };
diff --git a/Bindings/arm/ux500/boards.txt b/Bindings/arm/ux500/boards.txt
index b8737a8de718..7334c24625fc 100644
--- a/Bindings/arm/ux500/boards.txt
+++ b/Bindings/arm/ux500/boards.txt
@@ -23,7 +23,7 @@ scu:
see binding for arm/scu.txt
interrupt-controller:
- see binding for arm/gic.txt
+ see binding for interrupt-controller/arm,gic.txt
timer:
see binding for arm/twd.txt
diff --git a/Bindings/ata/ahci-platform.txt b/Bindings/ata/ahci-platform.txt
index c2340eeeb97f..87adfb227ca9 100644
--- a/Bindings/ata/ahci-platform.txt
+++ b/Bindings/ata/ahci-platform.txt
@@ -11,8 +11,10 @@ Required properties:
- compatible : compatible string, one of:
- "allwinner,sun4i-a10-ahci"
- "hisilicon,hisi-ahci"
+ - "cavium,octeon-7130-ahci"
- "ibm,476gtr-ahci"
- "marvell,armada-380-ahci"
+ - "marvell,armada-3700-ahci"
- "snps,dwc-ahci"
- "snps,exynos5440-ahci"
- "snps,spear-ahci"
@@ -30,6 +32,10 @@ Optional properties:
- target-supply : regulator for SATA target power
- phys : reference to the SATA PHY node
- phy-names : must be "sata-phy"
+- ports-implemented : Mask that indicates which ports that the HBA supports
+ are available for software to use. Useful if PORTS_IMPL
+ is not programmed by the BIOS, which is true with
+ some embedded SOC's.
Required properties when using sub-nodes:
- #address-cells : number of cells to encode an address
diff --git a/Bindings/ata/tegra-sata.txt b/Bindings/ata/nvidia,tegra124-ahci.txt
index 66c83c3e8915..66c83c3e8915 100644
--- a/Bindings/ata/tegra-sata.txt
+++ b/Bindings/ata/nvidia,tegra124-ahci.txt
diff --git a/Bindings/btmrvl.txt b/Bindings/btmrvl.txt
deleted file mode 100644
index 58f964bb0a52..000000000000
--- a/Bindings/btmrvl.txt
+++ /dev/null
@@ -1,29 +0,0 @@
-btmrvl
-------
-
-Required properties:
-
- - compatible : must be "btmrvl,cfgdata"
-
-Optional properties:
-
- - btmrvl,cal-data : Calibration data downloaded to the device during
- initialization. This is an array of 28 values(u8).
-
- - btmrvl,gpio-gap : gpio and gap (in msecs) combination to be
- configured.
-
-Example:
-
-GPIO pin 13 is configured as a wakeup source and GAP is set to 100 msecs
-in below example.
-
-btmrvl {
- compatible = "btmrvl,cfgdata";
-
- btmrvl,cal-data = /bits/ 8 <
- 0x37 0x01 0x1c 0x00 0xff 0xff 0xff 0xff 0x01 0x7f 0x04 0x02
- 0x00 0x00 0xba 0xce 0xc0 0xc6 0x2d 0x00 0x00 0x00 0x00 0x00
- 0x00 0x00 0xf0 0x00>;
- btmrvl,gpio-gap = <0x0d64>;
-};
diff --git a/Bindings/clock/artpec6.txt b/Bindings/clock/artpec6.txt
new file mode 100644
index 000000000000..dff9cdf0009c
--- /dev/null
+++ b/Bindings/clock/artpec6.txt
@@ -0,0 +1,41 @@
+* Clock bindings for Axis ARTPEC-6 chip
+
+The bindings are based on the clock provider binding in
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+External clocks:
+----------------
+
+There are two external inputs to the main clock controller which should be
+provided using the common clock bindings.
+- "sys_refclk": External 50 Mhz oscillator (required)
+- "i2s_refclk": Alternate audio reference clock (optional).
+
+Main clock controller
+---------------------
+
+Required properties:
+- #clock-cells: Should be <1>
+ See dt-bindings/clock/axis,artpec6-clkctrl.h for the list of valid identifiers.
+- compatible: Should be "axis,artpec6-clkctrl"
+- reg: Must contain the base address and length of the system controller
+- clocks: Must contain a phandle entry for each clock in clock-names
+- clock-names: Must include the external oscillator ("sys_refclk"). Optional
+ ones are the audio reference clock ("i2s_refclk") and the audio fractional
+ dividers ("frac_clk0" and "frac_clk1").
+
+Examples:
+
+ext_clk: ext_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+};
+
+clkctrl: clkctrl@f8000000 {
+ #clock-cells = <1>;
+ compatible = "axis,artpec6-clkctrl";
+ reg = <0xf8000000 0x48>;
+ clocks = <&ext_clk>;
+ clock-names = "sys_refclk";
+};
diff --git a/Bindings/clock/axi-clkgen.txt b/Bindings/clock/axi-clkgen.txt
index 20e1704e7df2..fb40da303d25 100644
--- a/Bindings/clock/axi-clkgen.txt
+++ b/Bindings/clock/axi-clkgen.txt
@@ -8,7 +8,10 @@ Required properties:
- compatible : shall be "adi,axi-clkgen-1.00.a" or "adi,axi-clkgen-2.00.a".
- #clock-cells : from common clock binding; Should always be set to 0.
- reg : Address and length of the axi-clkgen register set.
-- clocks : Phandle and clock specifier for the parent clock.
+- clocks : Phandle and clock specifier for the parent clock(s). This must
+ either reference one clock if only the first clock input is connected or two
+ if both clock inputs are connected. For the later case the clock connected
+ to the first input must be specified first.
Optional properties:
- clock-output-names : From common clock binding.
diff --git a/Bindings/clock/axs10x-i2s-pll-clock.txt b/Bindings/clock/axs10x-i2s-pll-clock.txt
new file mode 100644
index 000000000000..5ffc8df7e6da
--- /dev/null
+++ b/Bindings/clock/axs10x-i2s-pll-clock.txt
@@ -0,0 +1,25 @@
+Binding for the AXS10X I2S PLL clock
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible: shall be "snps,axs10x-i2s-pll-clock"
+- reg : address and length of the I2S PLL register set.
+- clocks: shall be the input parent clock phandle for the PLL.
+- #clock-cells: from common clock binding; Should always be set to 0.
+
+Example:
+ pll_clock: pll_clock {
+ compatible = "fixed-clock";
+ clock-frequency = <27000000>;
+ #clock-cells = <0>;
+ };
+
+ i2s_clock@100a0 {
+ compatible = "snps,axs10x-i2s-pll-clock";
+ reg = <0x100a0 0x10>;
+ clocks = <&pll_clock>;
+ #clock-cells = <0>;
+ };
diff --git a/Bindings/clock/brcm,iproc-clocks.txt b/Bindings/clock/brcm,iproc-clocks.txt
index 0b35e71b39e8..6f66e9aa354c 100644
--- a/Bindings/clock/brcm,iproc-clocks.txt
+++ b/Bindings/clock/brcm,iproc-clocks.txt
@@ -92,6 +92,7 @@ PLL and leaf clock compatible strings for Cygnus are:
"brcm,cygnus-lcpll0"
"brcm,cygnus-mipipll"
"brcm,cygnus-asiu-clk"
+ "brcm,cygnus-audiopll"
The following table defines the set of PLL/clock index and ID for Cygnus.
These clock IDs are defined in:
@@ -131,6 +132,11 @@ These clock IDs are defined in:
ch4_unused mipipll 5 BCM_CYGNUS_MIPIPLL_CH4_UNUSED
ch5_unused mipipll 6 BCM_CYGNUS_MIPIPLL_CH5_UNUSED
+ audiopll crystal 0 BCM_CYGNUS_AUDIOPLL
+ ch0_audio audiopll 1 BCM_CYGNUS_AUDIOPLL_CH0
+ ch1_audio audiopll 2 BCM_CYGNUS_AUDIOPLL_CH1
+ ch2_audio audiopll 3 BCM_CYGNUS_AUDIOPLL_CH2
+
Northstar and Northstar Plus
------
PLL and leaf clock compatible strings for Northstar and Northstar Plus are:
diff --git a/Bindings/clock/hi3519-crg.txt b/Bindings/clock/hi3519-crg.txt
new file mode 100644
index 000000000000..acd1f235d548
--- /dev/null
+++ b/Bindings/clock/hi3519-crg.txt
@@ -0,0 +1,46 @@
+* Hisilicon Hi3519 Clock and Reset Generator(CRG)
+
+The Hi3519 CRG module provides clock and reset signals to various
+controllers within the SoC.
+
+This binding uses the following bindings:
+ Documentation/devicetree/bindings/clock/clock-bindings.txt
+ Documentation/devicetree/bindings/reset/reset.txt
+
+Required Properties:
+
+- compatible: should be one of the following.
+ - "hisilicon,hi3519-crg" - controller compatible with Hi3519 SoC.
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+Each clock is assigned an identifier and client nodes use this identifier
+to specify the clock which they consume.
+
+All these identifier could be found in <dt-bindings/clock/hi3519-clock.h>.
+
+- #reset-cells: should be 2.
+
+A reset signal can be controlled by writing a bit register in the CRG module.
+The reset specifier consists of two cells. The first cell represents the
+register offset relative to the base address. The second cell represents the
+bit index in the register.
+
+Example: CRG nodes
+CRG: clock-reset-controller@12010000 {
+ compatible = "hisilicon,hi3519-crg";
+ reg = <0x12010000 0x10000>;
+ #clock-cells = <1>;
+ #reset-cells = <2>;
+};
+
+Example: consumer nodes
+i2c0: i2c@12110000 {
+ compatible = "hisilicon,hi3519-i2c";
+ reg = <0x12110000 0x1000>;
+ clocks = <&CRG HI3519_I2C0_RST>;
+ resets = <&CRG 0xe4 0>;
+};
diff --git a/Bindings/clock/imx35-clock.txt b/Bindings/clock/imx35-clock.txt
index a70356452a82..f49783213c56 100644
--- a/Bindings/clock/imx35-clock.txt
+++ b/Bindings/clock/imx35-clock.txt
@@ -94,6 +94,7 @@ clocks and IDs.
csi_sel 79
iim_gate 80
gpu2d_gate 81
+ ckli_gate 82
Examples:
diff --git a/Bindings/clock/lpc1850-creg-clk.txt b/Bindings/clock/lpc1850-creg-clk.txt
new file mode 100644
index 000000000000..6f1c7b4e4d2c
--- /dev/null
+++ b/Bindings/clock/lpc1850-creg-clk.txt
@@ -0,0 +1,52 @@
+* NXP LPC1850 CREG clocks
+
+The NXP LPC18xx/43xx CREG (Configuration Registers) block contains
+control registers for two low speed clocks. One of the clocks is a
+32 kHz oscillator driver with power up/down and clock gating. Next
+is a fixed divider that creates a 1 kHz clock from the 32 kHz osc.
+
+These clocks are used by the RTC and the Event Router peripherials.
+The 32 kHz can also be routed to other peripherials to enable low
+power modes.
+
+This binding uses the common clock binding:
+ Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible:
+ Should be "nxp,lpc1850-creg-clk"
+- #clock-cells:
+ Shall have value <1>.
+- clocks:
+ Shall contain a phandle to the fixed 32 kHz crystal.
+
+The creg-clk node must be a child of the creg syscon node.
+
+The following clocks are available from the clock node.
+
+Clock ID Name
+ 0 1 kHz clock
+ 1 32 kHz Oscillator
+
+Example:
+soc {
+ creg: syscon@40043000 {
+ compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd";
+ reg = <0x40043000 0x1000>;
+
+ creg_clk: clock-controller {
+ compatible = "nxp,lpc1850-creg-clk";
+ clocks = <&xtal32>;
+ #clock-cells = <1>;
+ };
+
+ ...
+ };
+
+ rtc: rtc@40046000 {
+ ...
+ clocks = <&creg_clk 0>, <&ccu1 CLK_CPU_BUS>;
+ clock-names = "rtc", "reg";
+ ...
+ };
+};
diff --git a/Bindings/clock/microchip,pic32.txt b/Bindings/clock/microchip,pic32.txt
new file mode 100644
index 000000000000..c93d88fdd858
--- /dev/null
+++ b/Bindings/clock/microchip,pic32.txt
@@ -0,0 +1,39 @@
+Microchip PIC32 Clock Controller Binding
+----------------------------------------
+Microchip clock controller is consists of few oscillators, PLL, multiplexer
+and few divider modules.
+
+This binding uses common clock bindings.
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible: shall be "microchip,pic32mzda-clk".
+- reg: shall contain base address and length of clock registers.
+- #clock-cells: shall be 1.
+
+Optional properties:
+- microchip,pic32mzda-sosc: shall be added only if platform has
+ secondary oscillator connected.
+
+Example:
+ rootclk: clock-controller@1f801200 {
+ compatible = "microchip,pic32mzda-clk";
+ reg = <0x1f801200 0x200>;
+ #clock-cells = <1>;
+ /* optional */
+ microchip,pic32mzda-sosc;
+ };
+
+
+The clock consumer shall specify the desired clock-output of the clock
+controller (as defined in [2]) by specifying output-id in its "clock"
+phandle cell.
+[2] include/dt-bindings/clock/microchip,pic32-clock.h
+
+For example for UART2:
+uart2: serial@2 {
+ compatible = "microchip,pic32mzda-uart";
+ reg = <>;
+ interrupts = <>;
+ clocks = <&rootclk PB2CLK>;
+};
diff --git a/Bindings/clock/nvidia,tegra124-dfll.txt b/Bindings/clock/nvidia,tegra124-dfll.txt
index ee7e5fd4a50b..63f9d8277d48 100644
--- a/Bindings/clock/nvidia,tegra124-dfll.txt
+++ b/Bindings/clock/nvidia,tegra124-dfll.txt
@@ -50,7 +50,7 @@ Required properties for I2C mode:
Example:
-clock@0,70110000 {
+clock@70110000 {
compatible = "nvidia,tegra124-dfll";
reg = <0 0x70110000 0 0x100>, /* DFLL control */
<0 0x70110000 0 0x100>, /* I2C output control */
diff --git a/Bindings/clock/oxnas,stdclk.txt b/Bindings/clock/oxnas,stdclk.txt
new file mode 100644
index 000000000000..208cca6ac4ec
--- /dev/null
+++ b/Bindings/clock/oxnas,stdclk.txt
@@ -0,0 +1,35 @@
+Oxford Semiconductor OXNAS SoC Family Standard Clocks
+================================================
+
+Please also refer to clock-bindings.txt in this directory for common clock
+bindings usage.
+
+Required properties:
+- compatible: Should be "oxsemi,ox810se-stdclk"
+- #clock-cells: 1, see below
+
+Parent node should have the following properties :
+- compatible: Should be "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd"
+
+For OX810SE, the clock indices are :
+ - 0: LEON
+ - 1: DMA_SGDMA
+ - 2: CIPHER
+ - 3: SATA
+ - 4: AUDIO
+ - 5: USBMPH
+ - 6: ETHA
+ - 7: PCIA
+ - 8: NAND
+
+example:
+
+sys: sys-ctrl@000000 {
+ compatible = "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd";
+ reg = <0x000000 0x100000>;
+
+ stdclk: stdclk {
+ compatible = "oxsemi,ox810se-stdclk";
+ #clock-cells = <1>;
+ };
+};
diff --git a/Bindings/clock/qca,ath79-pll.txt b/Bindings/clock/qca,ath79-pll.txt
index e0fc2c11dd00..241fb0545b9e 100644
--- a/Bindings/clock/qca,ath79-pll.txt
+++ b/Bindings/clock/qca,ath79-pll.txt
@@ -3,7 +3,7 @@ Binding for Qualcomm Atheros AR7xxx/AR9XXX PLL controller
The PPL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB.
Required Properties:
-- compatible: has to be "qca,<soctype>-cpu-intc" and one of the following
+- compatible: has to be "qca,<soctype>-pll" and one of the following
fallbacks:
- "qca,ar7100-pll"
- "qca,ar7240-pll"
@@ -21,8 +21,8 @@ Optional properties:
Example:
- memory-controller@18050000 {
- compatible = "qca,ar9132-ppl", "qca,ar9130-pll";
+ pll-controller@18050000 {
+ compatible = "qca,ar9132-pll", "qca,ar9130-pll";
reg = <0x18050000 0x20>;
clock-names = "ref";
diff --git a/Bindings/clock/qcom,gcc.txt b/Bindings/clock/qcom,gcc.txt
index 72f82f444091..9a60fde32b02 100644
--- a/Bindings/clock/qcom,gcc.txt
+++ b/Bindings/clock/qcom,gcc.txt
@@ -7,6 +7,7 @@ Required properties :
"qcom,gcc-apq8064"
"qcom,gcc-apq8084"
"qcom,gcc-ipq8064"
+ "qcom,gcc-ipq4019"
"qcom,gcc-msm8660"
"qcom,gcc-msm8916"
"qcom,gcc-msm8960"
diff --git a/Bindings/clock/renesas,cpg-mssr.txt b/Bindings/clock/renesas,cpg-mssr.txt
index 59297d34b208..fefb8023020f 100644
--- a/Bindings/clock/renesas,cpg-mssr.txt
+++ b/Bindings/clock/renesas,cpg-mssr.txt
@@ -61,7 +61,7 @@ Examples
reg = <0 0xe6e88000 0 64>;
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 310>;
- clock-names = "sci_ick";
+ clock-names = "fck";
dmas = <&dmac1 0x13>, <&dmac1 0x12>;
dma-names = "tx", "rx";
power-domains = <&cpg>;
diff --git a/Bindings/clock/rockchip,rk3036-cru.txt b/Bindings/clock/rockchip,rk3036-cru.txt
index ace05992a262..20df350b9ef3 100644
--- a/Bindings/clock/rockchip,rk3036-cru.txt
+++ b/Bindings/clock/rockchip,rk3036-cru.txt
@@ -30,7 +30,7 @@ that they are defined using standard clock bindings with following
clock-output-names:
- "xin24m" - crystal input - required,
- "ext_i2s" - external I2S clock - optional,
- - "ext_gmac" - external GMAC clock - optional
+ - "rmii_clkin" - external EMAC clock - optional
Example: Clock controller node:
diff --git a/Bindings/clock/rockchip,rk3188-cru.txt b/Bindings/clock/rockchip,rk3188-cru.txt
index 0c2bf5eba43e..7f368530a2e4 100644
--- a/Bindings/clock/rockchip,rk3188-cru.txt
+++ b/Bindings/clock/rockchip,rk3188-cru.txt
@@ -16,7 +16,7 @@ Required Properties:
Optional Properties:
- rockchip,grf: phandle to the syscon managing the "general register files"
- If missing pll rates are not changable, due to the missing pll lock status.
+ If missing pll rates are not changeable, due to the missing pll lock status.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All available clocks are defined as
diff --git a/Bindings/clock/rockchip,rk3288-cru.txt b/Bindings/clock/rockchip,rk3288-cru.txt
index c9fbb76573e1..8cb47c39ba53 100644
--- a/Bindings/clock/rockchip,rk3288-cru.txt
+++ b/Bindings/clock/rockchip,rk3288-cru.txt
@@ -15,7 +15,7 @@ Required Properties:
Optional Properties:
- rockchip,grf: phandle to the syscon managing the "general register files"
- If missing pll rates are not changable, due to the missing pll lock status.
+ If missing pll rates are not changeable, due to the missing pll lock status.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All available clocks are defined as
diff --git a/Bindings/clock/rockchip,rk3399-cru.txt b/Bindings/clock/rockchip,rk3399-cru.txt
new file mode 100644
index 000000000000..3888dd33fcbd
--- /dev/null
+++ b/Bindings/clock/rockchip,rk3399-cru.txt
@@ -0,0 +1,62 @@
+* Rockchip RK3399 Clock and Reset Unit
+
+The RK3399 clock controller generates and supplies clock to various
+controllers within the SoC and also implements a reset controller for SoC
+peripherals.
+
+Required Properties:
+
+- compatible: PMU for CRU should be "rockchip,rk3399-pmucru"
+- compatible: CRU should be "rockchip,rk3399-cru"
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- #clock-cells: should be 1.
+- #reset-cells: should be 1.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. All available clocks are defined as
+preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be
+used in device tree sources. Similar macros exist for the reset sources in
+these files.
+
+External clocks:
+
+There are several clocks that are generated outside the SoC. It is expected
+that they are defined using standard clock bindings with following
+clock-output-names:
+ - "xin24m" - crystal input - required,
+ - "xin32k" - rtc clock - optional,
+ - "clkin_gmac" - external GMAC clock - optional,
+ - "clkin_i2s" - external I2S clock - optional,
+ - "pclkin_cif" - external ISP clock - optional,
+ - "clk_usbphy0_480m" - output clock of the pll in the usbphy0
+ - "clk_usbphy1_480m" - output clock of the pll in the usbphy1
+
+Example: Clock controller node:
+
+ pmucru: pmu-clock-controller@ff750000 {
+ compatible = "rockchip,rk3399-pmucru";
+ reg = <0x0 0xff750000 0x0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ cru: clock-controller@ff760000 {
+ compatible = "rockchip,rk3399-cru";
+ reg = <0x0 0xff760000 0x0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+Example: UART controller node that consumes the clock generated by the clock
+ controller:
+
+ uart0: serial@ff1a0000 {
+ compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xff180000 0x0 0x100>;
+ clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
+ clock-names = "baudclk", "apb_pclk";
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ };
diff --git a/Bindings/clock/st/st,clkgen.txt b/Bindings/clock/st/st,clkgen.txt
index 78978f1f5158..b18bf86f926f 100644
--- a/Bindings/clock/st/st,clkgen.txt
+++ b/Bindings/clock/st/st,clkgen.txt
@@ -40,7 +40,7 @@ address is common of all subnode.
};
This binding uses the common clock binding[1].
-Each subnode should use the binding discribe in [2]..[7]
+Each subnode should use the binding described in [2]..[7]
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/clock/st,clkgen-divmux.txt
diff --git a/Bindings/clock/sunxi.txt b/Bindings/clock/sunxi.txt
index e59f57b24777..8f7619d8c8d8 100644
--- a/Bindings/clock/sunxi.txt
+++ b/Bindings/clock/sunxi.txt
@@ -10,6 +10,7 @@ Required properties:
"allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
"allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
"allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23
+ "allwinner,sun4i-a10-pll3-clk" - for the video PLL clock on A10
"allwinner,sun9i-a80-pll4-clk" - for the peripheral PLLs on A80
"allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
"allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
@@ -18,6 +19,7 @@ Required properties:
"allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock
"allwinner,sun4i-a10-axi-clk" - for the AXI clock
"allwinner,sun8i-a23-axi-clk" - for the AXI clock on A23
+ "allwinner,sun4i-a10-gates-clk" - for generic gates on all compatible SoCs
"allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates
"allwinner,sun4i-a10-ahb-clk" - for the AHB clock
"allwinner,sun5i-a13-ahb-clk" - for the AHB clock on A13
@@ -39,12 +41,14 @@ Required properties:
"allwinner,sun6i-a31-apb0-clk" - for the APB0 clock on A31
"allwinner,sun8i-a23-apb0-clk" - for the APB0 clock on A23
"allwinner,sun9i-a80-apb0-clk" - for the APB0 bus clock on A80
+ "allwinner,sun8i-a83t-apb0-gates-clk" - for the APB0 gates on A83T
"allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10
"allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
"allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
"allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31
"allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
"allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23
+ "allwinner,sun8i-h3-apb0-gates-clk" - for the APB0 gates on H3
"allwinner,sun9i-a80-apb0-gates-clk" - for the APB0 gates on A80
"allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
"allwinner,sun9i-a80-apb1-clk" - for the APB1 bus clock on A80
@@ -57,9 +61,12 @@ Required properties:
"allwinner,sun9i-a80-apb1-gates-clk" - for the APB1 gates on A80
"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
"allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
+ "allwinner,sun8i-a83t-bus-gates-clk" - for the bus gates on A83T
"allwinner,sun8i-h3-bus-gates-clk" - for the bus gates on H3
"allwinner,sun9i-a80-apbs-gates-clk" - for the APBS gates on A80
+ "allwinner,sun4i-a10-display-clk" - for the display clocks on the A10
"allwinner,sun4i-a10-dram-gates-clk" - for the DRAM gates on A10
+ "allwinner,sun5i-a13-dram-gates-clk" - for the DRAM gates on A13
"allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
"allwinner,sun4i-a10-mmc-clk" - for the MMC clock
"allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80
@@ -69,6 +76,8 @@ Required properties:
"allwinner,sun8i-a23-mbus-clk" - for the MBUS clock on A23
"allwinner,sun7i-a20-out-clk" - for the external output clocks
"allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
+ "allwinner,sun4i-a10-tcon-ch0-clk" - for the TCON channel 0 clock on the A10
+ "allwinner,sun4i-a10-tcon-ch1-clk" - for the TCON channel 1 clock on the A10
"allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20
"allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13
"allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31
@@ -77,6 +86,7 @@ Required properties:
"allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80
"allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80
"allwinner,sun4i-a10-ve-clk" - for the Video Engine clock
+ "allwinner,sun6i-a31-display-clk" - for the display clocks
Required properties for all clocks:
- reg : shall be the control register address for the clock.
diff --git a/Bindings/clock/ti/adpll.txt b/Bindings/clock/ti/adpll.txt
new file mode 100644
index 000000000000..4c8a2ce2cd70
--- /dev/null
+++ b/Bindings/clock/ti/adpll.txt
@@ -0,0 +1,41 @@
+Binding for Texas Instruments ADPLL clock.
+
+Binding status: Unstable - ABI compatibility may be broken in the future
+
+This binding uses the common clock binding[1]. It assumes a
+register-mapped ADPLL with two to three selectable input clocks
+and three to four children.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be one of "ti,dm814-adpll-s-clock" or
+ "ti,dm814-adpll-lj-clock" depending on the type of the ADPLL
+- #clock-cells : from common clock binding; shall be set to 1.
+- clocks : link phandles of parent clocks clkinp and clkinpulow, note
+ that the adpll-s-clock also has an optional clkinphif
+- reg : address and length of the register set for controlling the ADPLL.
+
+Examples:
+ adpll_mpu_ck: adpll@40 {
+ #clock-cells = <1>;
+ compatible = "ti,dm814-adpll-s-clock";
+ reg = <0x40 0x40>;
+ clocks = <&devosc_ck &devosc_ck &devosc_ck>;
+ clock-names = "clkinp", "clkinpulow", "clkinphif";
+ clock-output-names = "481c5040.adpll.dcoclkldo",
+ "481c5040.adpll.clkout",
+ "481c5040.adpll.clkoutx2",
+ "481c5040.adpll.clkouthif";
+ };
+
+ adpll_dsp_ck: adpll@80 {
+ #clock-cells = <1>;
+ compatible = "ti,dm814-adpll-lj-clock";
+ reg = <0x80 0x30>;
+ clocks = <&devosc_ck &devosc_ck>;
+ clock-names = "clkinp", "clkinpulow";
+ clock-output-names = "481c5080.adpll.dcoclkldo",
+ "481c5080.adpll.clkout",
+ "481c5080.adpll.clkoutldo";
+ };
diff --git a/Bindings/clock/xgene.txt b/Bindings/clock/xgene.txt
index 1c4ef773feea..82f9638121db 100644
--- a/Bindings/clock/xgene.txt
+++ b/Bindings/clock/xgene.txt
@@ -9,6 +9,8 @@ Required properties:
"apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
"apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
"apm,xgene-device-clock" - for a X-Gene device clock
+ "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
+ "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
Required properties for SoC or PCP PLL clocks:
- reg : shall be the physical PLL register address for the pll clock.
diff --git a/Bindings/cpufreq/tegra124-cpufreq.txt b/Bindings/cpufreq/nvidia,tegra124-cpufreq.txt
index b1669fbfb740..b1669fbfb740 100644
--- a/Bindings/cpufreq/tegra124-cpufreq.txt
+++ b/Bindings/cpufreq/nvidia,tegra124-cpufreq.txt
diff --git a/Bindings/crypto/fsl-imx-scc.txt b/Bindings/crypto/fsl-imx-scc.txt
new file mode 100644
index 000000000000..7aad448e8a36
--- /dev/null
+++ b/Bindings/crypto/fsl-imx-scc.txt
@@ -0,0 +1,21 @@
+Freescale Security Controller (SCC)
+
+Required properties:
+- compatible : Should be "fsl,imx25-scc".
+- reg : Should contain register location and length.
+- interrupts : Should contain interrupt numbers for SCM IRQ and SMN IRQ.
+- interrupt-names : Should specify the names "scm" and "smn" for the
+ SCM IRQ and SMN IRQ.
+- clocks: Should contain the clock driving the SCC core.
+- clock-names: Should be set to "ipg".
+
+Example:
+
+ scc: crypto@53fac000 {
+ compatible = "fsl,imx25-scc";
+ reg = <0x53fac000 0x4000>;
+ clocks = <&clks 111>;
+ clock-names = "ipg";
+ interrupts = <49>, <50>;
+ interrupt-names = "scm", "smn";
+ };
diff --git a/Bindings/crypto/samsung-sss.txt b/Bindings/crypto/samsung-sss.txt
index a6dafa83c6df..7a5ca56683cc 100644
--- a/Bindings/crypto/samsung-sss.txt
+++ b/Bindings/crypto/samsung-sss.txt
@@ -23,10 +23,8 @@ Required properties:
- "samsung,exynos4210-secss" for Exynos4210, Exynos4212, Exynos4412, Exynos5250,
Exynos5260 and Exynos5420 SoCs.
- reg : Offset and length of the register set for the module
-- interrupts : interrupt specifiers of SSS module interrupts, should contain
- following entries:
- - first : feed control interrupt (required for all variants),
- - second : hash interrupt (required only for samsung,s5pv210-secss).
+- interrupts : interrupt specifiers of SSS module interrupts (one feed
+ control interrupt).
- clocks : list of clock phandle and specifier pairs for all clocks listed in
clock-names property.
diff --git a/Bindings/devfreq/event/exynos-nocp.txt b/Bindings/devfreq/event/exynos-nocp.txt
new file mode 100644
index 000000000000..fd459f00aa5a
--- /dev/null
+++ b/Bindings/devfreq/event/exynos-nocp.txt
@@ -0,0 +1,26 @@
+
+* Samsung Exynos NoC (Network on Chip) Probe device
+
+The Samsung Exynos542x SoC has NoC (Network on Chip) Probe for NoC bus.
+NoC provides the primitive values to get the performance data. The packets
+that the Network on Chip (NoC) probes detects are transported over
+the network infrastructure to observer units. You can configure probes to
+capture packets with header or data on the data request response network,
+or as traffic debug or statistic collectors. Exynos542x bus has multiple
+NoC probes to provide bandwidth information about behavior of the SoC
+that you can use while analyzing system performance.
+
+Required properties:
+- compatible: Should be "samsung,exynos5420-nocp"
+- reg: physical base address of each NoC Probe and length of memory mapped region.
+
+Optional properties:
+- clock-names : the name of clock used by the NoC Probe, "nocp"
+- clocks : phandles for clock specified in "clock-names" property
+
+Example : NoC Probe nodes in Device Tree are listed below.
+
+ nocp_mem0_0: nocp@10CA1000 {
+ compatible = "samsung,exynos5420-nocp";
+ reg = <0x10CA1000 0x200>;
+ };
diff --git a/Bindings/devfreq/exynos-bus.txt b/Bindings/devfreq/exynos-bus.txt
new file mode 100644
index 000000000000..d3ec8e676b6b
--- /dev/null
+++ b/Bindings/devfreq/exynos-bus.txt
@@ -0,0 +1,409 @@
+* Generic Exynos Bus frequency device
+
+The Samsung Exynos SoC has many buses for data transfer between DRAM
+and sub-blocks in SoC. Most Exynos SoCs share the common architecture
+for buses. Generally, each bus of Exynos SoC includes a source clock
+and a power line, which are able to change the clock frequency
+of the bus in runtime. To monitor the usage of each bus in runtime,
+the driver uses the PPMU (Platform Performance Monitoring Unit), which
+is able to measure the current load of sub-blocks.
+
+The Exynos SoC includes the various sub-blocks which have the each AXI bus.
+The each AXI bus has the owned source clock but, has not the only owned
+power line. The power line might be shared among one more sub-blocks.
+So, we can divide into two type of device as the role of each sub-block.
+There are two type of bus devices as following:
+- parent bus device
+- passive bus device
+
+Basically, parent and passive bus device share the same power line.
+The parent bus device can only change the voltage of shared power line
+and the rest bus devices (passive bus device) depend on the decision of
+the parent bus device. If there are three blocks which share the VDD_xxx
+power line, Only one block should be parent device and then the rest blocks
+should depend on the parent device as passive device.
+
+ VDD_xxx |--- A block (parent)
+ |--- B block (passive)
+ |--- C block (passive)
+
+There are a little different composition among Exynos SoC because each Exynos
+SoC has different sub-blocks. Therefore, such difference should be specified
+in devicetree file instead of each device driver. In result, this driver
+is able to support the bus frequency for all Exynos SoCs.
+
+Required properties for all bus devices:
+- compatible: Should be "samsung,exynos-bus".
+- clock-names : the name of clock used by the bus, "bus".
+- clocks : phandles for clock specified in "clock-names" property.
+- operating-points-v2: the OPP table including frequency/voltage information
+ to support DVFS (Dynamic Voltage/Frequency Scaling) feature.
+
+Required properties only for parent bus device:
+- vdd-supply: the regulator to provide the buses with the voltage.
+- devfreq-events: the devfreq-event device to monitor the current utilization
+ of buses.
+
+Required properties only for passive bus device:
+- devfreq: the parent bus device.
+
+Optional properties only for parent bus device:
+- exynos,saturation-ratio: the percentage value which is used to calibrate
+ the performance count against total cycle count.
+- exynos,voltage-tolerance: the percentage value for bus voltage tolerance
+ which is used to calculate the max voltage.
+
+Detailed correlation between sub-blocks and power line according to Exynos SoC:
+- In case of Exynos3250, there are two power line as following:
+ VDD_MIF |--- DMC
+
+ VDD_INT |--- LEFTBUS (parent device)
+ |--- PERIL
+ |--- MFC
+ |--- G3D
+ |--- RIGHTBUS
+ |--- PERIR
+ |--- FSYS
+ |--- LCD0
+ |--- PERIR
+ |--- ISP
+ |--- CAM
+
+- In case of Exynos4210, there is one power line as following:
+ VDD_INT |--- DMC (parent device)
+ |--- LEFTBUS
+ |--- PERIL
+ |--- MFC(L)
+ |--- G3D
+ |--- TV
+ |--- LCD0
+ |--- RIGHTBUS
+ |--- PERIR
+ |--- MFC(R)
+ |--- CAM
+ |--- FSYS
+ |--- GPS
+ |--- LCD0
+ |--- LCD1
+
+- In case of Exynos4x12, there are two power line as following:
+ VDD_MIF |--- DMC
+
+ VDD_INT |--- LEFTBUS (parent device)
+ |--- PERIL
+ |--- MFC(L)
+ |--- G3D
+ |--- TV
+ |--- IMAGE
+ |--- RIGHTBUS
+ |--- PERIR
+ |--- MFC(R)
+ |--- CAM
+ |--- FSYS
+ |--- GPS
+ |--- LCD0
+ |--- ISP
+
+- In case of Exynos5422, there are two power line as following:
+ VDD_MIF |--- DREX 0 (parent device, DRAM EXpress controller)
+ |--- DREX 1
+
+ VDD_INT |--- NoC_Core (parent device)
+ |--- G2D
+ |--- G3D
+ |--- DISP1
+ |--- NoC_WCORE
+ |--- GSCL
+ |--- MSCL
+ |--- ISP
+ |--- MFC
+ |--- GEN
+ |--- PERIS
+ |--- PERIC
+ |--- FSYS
+ |--- FSYS2
+
+Example1:
+ Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to
+ power line (regulator). The MIF (Memory Interface) AXI bus is used to
+ transfer data between DRAM and CPU and uses the VDD_MIF regulator.
+
+ - MIF (Memory Interface) block
+ : VDD_MIF |--- DMC (Dynamic Memory Controller)
+
+ - INT (Internal) block
+ : VDD_INT |--- LEFTBUS (parent device)
+ |--- PERIL
+ |--- MFC
+ |--- G3D
+ |--- RIGHTBUS
+ |--- FSYS
+ |--- LCD0
+ |--- PERIR
+ |--- ISP
+ |--- CAM
+
+ - MIF bus's frequency/voltage table
+ -----------------------
+ |Lv| Freq | Voltage |
+ -----------------------
+ |L1| 50000 |800000 |
+ |L2| 100000 |800000 |
+ |L3| 134000 |800000 |
+ |L4| 200000 |825000 |
+ |L5| 400000 |875000 |
+ -----------------------
+
+ - INT bus's frequency/voltage table
+ ----------------------------------------------------------
+ |Block|LEFTBUS|RIGHTBUS|MCUISP |ISP |PERIL ||VDD_INT |
+ | name| |LCD0 | | | || |
+ | | |FSYS | | | || |
+ | | |MFC | | | || |
+ ----------------------------------------------------------
+ |Mode |*parent|passive |passive|passive|passive|| |
+ ----------------------------------------------------------
+ |Lv |Frequency ||Voltage |
+ ----------------------------------------------------------
+ |L1 |50000 |50000 |50000 |50000 |50000 ||900000 |
+ |L2 |80000 |80000 |80000 |80000 |80000 ||900000 |
+ |L3 |100000 |100000 |100000 |100000 |100000 ||1000000 |
+ |L4 |134000 |134000 |200000 |200000 | ||1000000 |
+ |L5 |200000 |200000 |400000 |300000 | ||1000000 |
+ ----------------------------------------------------------
+
+Example2 :
+ The bus of DMC (Dynamic Memory Controller) block in exynos3250.dtsi
+ is listed below:
+
+ bus_dmc: bus_dmc {
+ compatible = "samsung,exynos-bus";
+ clocks = <&cmu_dmc CLK_DIV_DMC>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_dmc_opp_table>;
+ status = "disabled";
+ };
+
+ bus_dmc_opp_table: opp_table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp@50000000 {
+ opp-hz = /bits/ 64 <50000000>;
+ opp-microvolt = <800000>;
+ };
+ opp@100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ opp-microvolt = <800000>;
+ };
+ opp@134000000 {
+ opp-hz = /bits/ 64 <134000000>;
+ opp-microvolt = <800000>;
+ };
+ opp@200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <825000>;
+ };
+ opp@400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <875000>;
+ };
+ };
+
+ bus_leftbus: bus_leftbus {
+ compatible = "samsung,exynos-bus";
+ clocks = <&cmu CLK_DIV_GDL>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_rightbus: bus_rightbus {
+ compatible = "samsung,exynos-bus";
+ clocks = <&cmu CLK_DIV_GDR>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_lcd0: bus_lcd0 {
+ compatible = "samsung,exynos-bus";
+ clocks = <&cmu CLK_DIV_ACLK_160>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_fsys: bus_fsys {
+ compatible = "samsung,exynos-bus";
+ clocks = <&cmu CLK_DIV_ACLK_200>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_mcuisp: bus_mcuisp {
+ compatible = "samsung,exynos-bus";
+ clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_mcuisp_opp_table>;
+ status = "disabled";
+ };
+
+ bus_isp: bus_isp {
+ compatible = "samsung,exynos-bus";
+ clocks = <&cmu CLK_DIV_ACLK_266>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_isp_opp_table>;
+ status = "disabled";
+ };
+
+ bus_peril: bus_peril {
+ compatible = "samsung,exynos-bus";
+ clocks = <&cmu CLK_DIV_ACLK_100>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_peril_opp_table>;
+ status = "disabled";
+ };
+
+ bus_mfc: bus_mfc {
+ compatible = "samsung,exynos-bus";
+ clocks = <&cmu CLK_SCLK_MFC>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_leftbus_opp_table>;
+ status = "disabled";
+ };
+
+ bus_leftbus_opp_table: opp_table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp@50000000 {
+ opp-hz = /bits/ 64 <50000000>;
+ opp-microvolt = <900000>;
+ };
+ opp@80000000 {
+ opp-hz = /bits/ 64 <80000000>;
+ opp-microvolt = <900000>;
+ };
+ opp@100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ opp-microvolt = <1000000>;
+ };
+ opp@134000000 {
+ opp-hz = /bits/ 64 <134000000>;
+ opp-microvolt = <1000000>;
+ };
+ opp@200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <1000000>;
+ };
+ };
+
+ bus_mcuisp_opp_table: opp_table2 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp@50000000 {
+ opp-hz = /bits/ 64 <50000000>;
+ };
+ opp@80000000 {
+ opp-hz = /bits/ 64 <80000000>;
+ };
+ opp@100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ };
+ opp@200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ };
+ opp@400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ };
+ };
+
+ bus_isp_opp_table: opp_table3 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp@50000000 {
+ opp-hz = /bits/ 64 <50000000>;
+ };
+ opp@80000000 {
+ opp-hz = /bits/ 64 <80000000>;
+ };
+ opp@100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ };
+ opp@200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ };
+ opp@300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ };
+ };
+
+ bus_peril_opp_table: opp_table4 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp@50000000 {
+ opp-hz = /bits/ 64 <50000000>;
+ };
+ opp@80000000 {
+ opp-hz = /bits/ 64 <80000000>;
+ };
+ opp@100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ };
+ };
+
+
+ Usage case to handle the frequency and voltage of bus on runtime
+ in exynos3250-rinato.dts is listed below:
+
+ &bus_dmc {
+ devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
+ vdd-supply = <&buck1_reg>; /* VDD_MIF */
+ status = "okay";
+ };
+
+ &bus_leftbus {
+ devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
+ vdd-supply = <&buck3_reg>;
+ status = "okay";
+ };
+
+ &bus_rightbus {
+ devfreq = <&bus_leftbus>;
+ status = "okay";
+ };
+
+ &bus_lcd0 {
+ devfreq = <&bus_leftbus>;
+ status = "okay";
+ };
+
+ &bus_fsys {
+ devfreq = <&bus_leftbus>;
+ status = "okay";
+ };
+
+ &bus_mcuisp {
+ devfreq = <&bus_leftbus>;
+ status = "okay";
+ };
+
+ &bus_isp {
+ devfreq = <&bus_leftbus>;
+ status = "okay";
+ };
+
+ &bus_peril {
+ devfreq = <&bus_leftbus>;
+ status = "okay";
+ };
+
+ &bus_mfc {
+ devfreq = <&bus_leftbus>;
+ status = "okay";
+ };
diff --git a/Bindings/display/arm,hdlcd.txt b/Bindings/display/arm,hdlcd.txt
new file mode 100644
index 000000000000..78bc24296f3e
--- /dev/null
+++ b/Bindings/display/arm,hdlcd.txt
@@ -0,0 +1,79 @@
+ARM HDLCD
+
+This is a display controller found on several development platforms produced
+by ARM Ltd and in more modern of its' Fast Models. The HDLCD is an RGB
+streamer that reads the data from a framebuffer and sends it to a single
+digital encoder (DVI or HDMI).
+
+Required properties:
+ - compatible: "arm,hdlcd"
+ - reg: Physical base address and length of the controller's registers.
+ - interrupts: One interrupt used by the display controller to notify the
+ interrupt controller when any of the interrupt sources programmed in
+ the interrupt mask register have activated.
+ - clocks: A list of phandle + clock-specifier pairs, one for each
+ entry in 'clock-names'.
+ - clock-names: A list of clock names. For HDLCD it should contain:
+ - "pxlclk" for the clock feeding the output PLL of the controller.
+
+Required sub-nodes:
+ - port: The HDLCD connection to an encoder chip. The connection is modeled
+ using the OF graph bindings specified in
+ Documentation/devicetree/bindings/graph.txt.
+
+Optional properties:
+ - memory-region: phandle to a node describing memory (see
+ Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt) to be
+ used for the framebuffer; if not present, the framebuffer may be located
+ anywhere in memory.
+
+
+Example:
+
+/ {
+ ...
+
+ hdlcd@2b000000 {
+ compatible = "arm,hdlcd";
+ reg = <0 0x2b000000 0 0x1000>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&oscclk5>;
+ clock-names = "pxlclk";
+ port {
+ hdlcd_output: endpoint@0 {
+ remote-endpoint = <&hdmi_enc_input>;
+ };
+ };
+ };
+
+ /* HDMI encoder on I2C bus */
+ i2c@7ffa0000 {
+ ....
+ hdmi-transmitter@70 {
+ compatible = ".....";
+ reg = <0x70>;
+ port@0 {
+ hdmi_enc_input: endpoint {
+ remote-endpoint = <&hdlcd_output>;
+ };
+
+ hdmi_enc_output: endpoint {
+ remote-endpoint = <&hdmi_1_port>;
+ };
+ };
+ };
+
+ };
+
+ hdmi1: connector@1 {
+ compatible = "hdmi-connector";
+ type = "a";
+ port {
+ hdmi_1_port: endpoint {
+ remote-endpoint = <&hdmi_enc_output>;
+ };
+ };
+ };
+
+ ...
+};
diff --git a/Bindings/display/brcm,bcm-vc4.txt b/Bindings/display/brcm,bcm-vc4.txt
index 56a961aa5061..a5ea451e67fc 100644
--- a/Bindings/display/brcm,bcm-vc4.txt
+++ b/Bindings/display/brcm,bcm-vc4.txt
@@ -35,6 +35,22 @@ Optional properties for HDMI:
as an interrupt/status bit in the HDMI controller
itself). See bindings/pinctrl/brcm,bcm2835-gpio.txt
+Required properties for DPI:
+- compatible: Should be "brcm,bcm2835-dpi"
+- reg: Physical base address and length of the registers
+- clocks: a) core: The core clock the unit runs on
+ b) pixel: The pixel clock that feeds the pixelvalve
+- port: Port node with a single endpoint connecting to the panel
+ device, as defined in [1]
+
+Required properties for V3D:
+- compatible: Should be "brcm,bcm2835-v3d"
+- reg: Physical base address and length of the V3D's registers
+- interrupts: The interrupt number
+ See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
+
+[1] Documentation/devicetree/bindings/media/video-interfaces.txt
+
Example:
pixelvalve@7e807000 {
compatible = "brcm,bcm2835-pixelvalve2";
@@ -60,6 +76,38 @@ hdmi: hdmi@7e902000 {
clock-names = "pixel", "hdmi";
};
+dpi: dpi@7e208000 {
+ compatible = "brcm,bcm2835-dpi";
+ reg = <0x7e208000 0x8c>;
+ clocks = <&clocks BCM2835_CLOCK_VPU>,
+ <&clocks BCM2835_CLOCK_DPI>;
+ clock-names = "core", "pixel";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port {
+ dpi_out: endpoint@0 {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+};
+
+v3d: v3d@7ec00000 {
+ compatible = "brcm,bcm2835-v3d";
+ reg = <0x7ec00000 0x1000>;
+ interrupts = <1 10>;
+};
+
vc4: gpu {
compatible = "brcm,bcm2835-vc4";
};
+
+panel: panel {
+ compatible = "ontat,yx700wv03", "simple-panel";
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&dpi_out>;
+ };
+ };
+};
diff --git a/Bindings/display/bridge/analogix_dp.txt b/Bindings/display/bridge/analogix_dp.txt
new file mode 100644
index 000000000000..4f2ba8c13d92
--- /dev/null
+++ b/Bindings/display/bridge/analogix_dp.txt
@@ -0,0 +1,52 @@
+Analogix Display Port bridge bindings
+
+Required properties for dp-controller:
+ -compatible:
+ platform specific such as:
+ * "samsung,exynos5-dp"
+ * "rockchip,rk3288-dp"
+ -reg:
+ physical base address of the controller and length
+ of memory mapped region.
+ -interrupts:
+ interrupt combiner values.
+ -clocks:
+ from common clock binding: handle to dp clock.
+ -clock-names:
+ from common clock binding: Shall be "dp".
+ -interrupt-parent:
+ phandle to Interrupt combiner node.
+ -phys:
+ from general PHY binding: the phandle for the PHY device.
+ -phy-names:
+ from general PHY binding: Should be "dp".
+
+Optional properties for dp-controller:
+ -force-hpd:
+ Indicate driver need force hpd when hpd detect failed, this
+ is used for some eDP screen which don't have hpd signal.
+ -hpd-gpios:
+ Hotplug detect GPIO.
+ Indicates which GPIO should be used for hotplug detection
+ -port@[X]: SoC specific port nodes with endpoint definitions as defined
+ in Documentation/devicetree/bindings/media/video-interfaces.txt,
+ please refer to the SoC specific binding document:
+ * Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
+ * Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
+
+[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
+-------------------------------------------------------------------------------
+
+Example:
+
+ dp-controller {
+ compatible = "samsung,exynos5-dp";
+ reg = <0x145b0000 0x10000>;
+ interrupts = <10 3>;
+ interrupt-parent = <&combiner>;
+ clocks = <&clock 342>;
+ clock-names = "dp";
+
+ phys = <&dp_phy>;
+ phy-names = "dp";
+ };
diff --git a/Bindings/display/exynos/exynos5433-decon.txt b/Bindings/display/exynos/exynos5433-decon.txt
index 377afbf5122a..c9fd7b3807e7 100644
--- a/Bindings/display/exynos/exynos5433-decon.txt
+++ b/Bindings/display/exynos/exynos5433-decon.txt
@@ -5,7 +5,8 @@ Exynos series of SoCs which transfers the image data from a video memory
buffer to an external LCD interface.
Required properties:
-- compatible: value should be "samsung,exynos5433-decon";
+- compatible: value should be one of:
+ "samsung,exynos5433-decon", "samsung,exynos5433-decon-tv";
- reg: physical base address and length of the DECON registers set.
- interrupts: should contain a list of all DECON IP block interrupts in the
order: VSYNC, LCD_SYSTEM. The interrupt specifier format
@@ -16,7 +17,7 @@ Required properties:
- clocks: must include clock specifiers corresponding to entries in the
clock-names property.
- clock-names: list of clock names sorted in the same order as the clocks
- property. Must contain "aclk_decon", "aclk_smmu_decon0x",
+ property. Must contain "pclk", "aclk_decon", "aclk_smmu_decon0x",
"aclk_xiu_decon0x", "pclk_smmu_decon0x", clk_decon_vclk",
"sclk_decon_eclk"
- ports: contains a port which is connected to mic node. address-cells and
diff --git a/Bindings/display/exynos/exynos_dp.txt b/Bindings/display/exynos/exynos_dp.txt
index fe4a7a2dea9c..ade5d8eebf85 100644
--- a/Bindings/display/exynos/exynos_dp.txt
+++ b/Bindings/display/exynos/exynos_dp.txt
@@ -1,20 +1,3 @@
-Device-Tree bindings for Samsung Exynos Embedded DisplayPort Transmitter(eDP)
-
-DisplayPort is industry standard to accommodate the growing board adoption
-of digital display technology within the PC and CE industries.
-It consolidates the internal and external connection methods to reduce device
-complexity and cost. It also supports necessary features for important cross
-industry applications and provides performance scalability to enable the next
-generation of displays that feature higher color depths, refresh rates, and
-display resolutions.
-
-eDP (embedded display port) device is compliant with Embedded DisplayPort
-standard as follows,
-- DisplayPort standard 1.1a for Exynos5250 and Exynos5260.
-- DisplayPort standard 1.3 for Exynos5422s and Exynos5800.
-
-eDP resides between FIMD and panel or FIMD and bridge such as LVDS.
-
The Exynos display port interface should be configured based on
the type of panel connected to it.
@@ -48,26 +31,6 @@ Required properties for dp-controller:
from general PHY binding: the phandle for the PHY device.
-phy-names:
from general PHY binding: Should be "dp".
- -samsung,color-space:
- input video data format.
- COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2
- -samsung,dynamic-range:
- dynamic range for input video data.
- VESA = 0, CEA = 1
- -samsung,ycbcr-coeff:
- YCbCr co-efficients for input video.
- COLOR_YCBCR601 = 0, COLOR_YCBCR709 = 1
- -samsung,color-depth:
- number of bits per colour component.
- COLOR_6 = 0, COLOR_8 = 1, COLOR_10 = 2, COLOR_12 = 3
- -samsung,link-rate:
- link rate supported by the panel.
- LINK_RATE_1_62GBPS = 0x6, LINK_RATE_2_70GBPS = 0x0A
- -samsung,lane-count:
- number of lanes supported by the panel.
- LANE_COUNT1 = 1, LANE_COUNT2 = 2, LANE_COUNT4 = 4
- - display-timings: timings for the connected panel as described by
- Documentation/devicetree/bindings/display/display-timing.txt
Optional properties for dp-controller:
-interlaced:
@@ -83,17 +46,31 @@ Optional properties for dp-controller:
Hotplug detect GPIO.
Indicates which GPIO should be used for hotplug
detection
-Video interfaces:
- Device node can contain video interface port nodes according to [1].
- The following are properties specific to those nodes:
-
- endpoint node connected to bridge or panel node:
- - remote-endpoint: specifies the endpoint in panel or bridge node.
- This node is required in all kinds of exynos dp
- to represent the connection between dp and bridge
- or dp and panel.
-
-[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
+ -video interfaces: Device node can contain video interface port
+ nodes according to [1].
+ - display-timings: timings for the connected panel as described by
+ Documentation/devicetree/bindings/display/panel/display-timing.txt
+
+For the below properties, please refer to Analogix DP binding document:
+ * Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
+ -phys (required)
+ -phy-names (required)
+ -hpd-gpios (optional)
+ force-hpd (optional)
+
+Deprecated properties for DisplayPort:
+-interlaced: deprecated prop that can parsed from drm_display_mode.
+-vsync-active-high: deprecated prop that can parsed from drm_display_mode.
+-hsync-active-high: deprecated prop that can parsed from drm_display_mode.
+-samsung,ycbcr-coeff: deprecated prop that can parsed from drm_display_mode.
+-samsung,dynamic-range: deprecated prop that can parsed from drm_display_mode.
+-samsung,color-space: deprecated prop that can parsed from drm_display_info.
+-samsung,color-depth: deprecated prop that can parsed from drm_display_info.
+-samsung,link-rate: deprecated prop that can reading from monitor by dpcd method.
+-samsung,lane-count: deprecated prop that can reading from monitor by dpcd method.
+-samsung,hpd-gpio: deprecated name for hpd-gpios.
+
+-------------------------------------------------------------------------------
Example:
@@ -112,13 +89,6 @@ SOC specific portion:
Board Specific portion:
dp-controller {
- samsung,color-space = <0>;
- samsung,dynamic-range = <0>;
- samsung,ycbcr-coeff = <0>;
- samsung,color-depth = <1>;
- samsung,link-rate = <0x0a>;
- samsung,lane-count = <4>;
-
display-timings {
native-mode = <&lcd_timing>;
lcd_timing: 1366x768 {
@@ -135,18 +105,9 @@ Board Specific portion:
};
ports {
- port {
+ port@0 {
dp_out: endpoint {
- remote-endpoint = <&dp_in>;
- };
- };
- };
-
- panel {
- ...
- port {
- dp_in: endpoint {
- remote-endpoint = <&dp_out>;
+ remote-endpoint = <&bridge_in>;
};
};
};
diff --git a/Bindings/display/exynos/exynos_dsim.txt b/Bindings/display/exynos/exynos_dsim.txt
index 0e6f0c024858..a78265993665 100644
--- a/Bindings/display/exynos/exynos_dsim.txt
+++ b/Bindings/display/exynos/exynos_dsim.txt
@@ -6,6 +6,7 @@ Required properties:
"samsung,exynos4210-mipi-dsi" /* for Exynos4 SoCs */
"samsung,exynos4415-mipi-dsi" /* for Exynos4415 SoC */
"samsung,exynos5410-mipi-dsi" /* for Exynos5410/5420/5440 SoCs */
+ "samsung,exynos5422-mipi-dsi" /* for Exynos5422/5800 SoCs */
"samsung,exynos5433-mipi-dsi" /* for Exynos5433 SoCs */
- reg: physical base address and length of the registers set for the device
- interrupts: should contain DSI interrupt
@@ -40,7 +41,7 @@ Video interfaces:
endpoint node connected from mic node (reg = 0):
- remote-endpoint: specifies the endpoint in mic node. This node is required
for Exynos5433 mipi dsi. So mic can access to panel node
- thoughout this dsi node.
+ throughout this dsi node.
endpoint node connected to panel node (reg = 1):
- remote-endpoint: specifies the endpoint in panel node. This node is
required in all kinds of exynos mipi dsi to represent
diff --git a/Bindings/display/exynos/exynos_hdmi.txt b/Bindings/display/exynos/exynos_hdmi.txt
index d474f59be6d6..a2ec4c1c9382 100644
--- a/Bindings/display/exynos/exynos_hdmi.txt
+++ b/Bindings/display/exynos/exynos_hdmi.txt
@@ -5,6 +5,7 @@ Required properties:
1) "samsung,exynos4210-hdmi"
2) "samsung,exynos4212-hdmi"
3) "samsung,exynos5420-hdmi"
+ 4) "samsung,exynos5433-hdmi"
- reg: physical base address of the hdmi and length of memory mapped
region.
- interrupts: interrupt number to the cpu.
@@ -12,6 +13,11 @@ Required properties:
a) phandle of the gpio controller node.
b) pin number within the gpio controller.
c) optional flags and pull up/down.
+- ddc: phandle to the hdmi ddc node
+- phy: phandle to the hdmi phy node
+- samsung,syscon-phandle: phandle for system controller node for PMU.
+
+Required properties for Exynos 4210, 4212, 5420 and 5433:
- clocks: list of clock IDs from SoC clock driver.
a) hdmi: Gate of HDMI IP bus clock.
b) sclk_hdmi: Gate of HDMI special clock.
@@ -25,9 +31,24 @@ Required properties:
sclk_pixel.
- clock-names: aliases as per driver requirements for above clock IDs:
"hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy" and "mout_hdmi".
-- ddc: phandle to the hdmi ddc node
-- phy: phandle to the hdmi phy node
-- samsung,syscon-phandle: phandle for system controller node for PMU.
+
+Required properties for Exynos 5433:
+- clocks: list of clock specifiers according to common clock bindings.
+ a) hdmi_pclk: Gate of HDMI IP APB bus.
+ b) hdmi_i_pclk: Gate of HDMI-PHY IP APB bus.
+ d) i_tmds_clk: Gate of HDMI TMDS clock.
+ e) i_pixel_clk: Gate of HDMI pixel clock.
+ f) i_spdif_clk: Gate of HDMI SPDIF clock.
+ g) oscclk: Oscillator clock, used as parent of following *_user clocks
+ in case HDMI-PHY is not operational.
+ h) tmds_clko: TMDS clock generated by HDMI-PHY.
+ i) tmds_clko_user: MUX used to switch between oscclk and tmds_clko,
+ respectively if HDMI-PHY is off and operational.
+ j) pixel_clko: Pixel clock generated by HDMI-PHY.
+ k) pixel_clko_user: MUX used to switch between oscclk and pixel_clko,
+ respectively if HDMI-PHY is off and operational.
+- clock-names: aliases for above clock specfiers.
+- samsung,sysreg: handle to syscon used to control the system registers.
Example:
diff --git a/Bindings/display/exynos/samsung-fimd.txt b/Bindings/display/exynos/samsung-fimd.txt
index 27c3ce0db16a..c7c6b9af87ac 100644
--- a/Bindings/display/exynos/samsung-fimd.txt
+++ b/Bindings/display/exynos/samsung-fimd.txt
@@ -12,7 +12,8 @@ Required properties:
"samsung,exynos3250-fimd"; /* for Exynos3250/3472 SoCs */
"samsung,exynos4210-fimd"; /* for Exynos4 SoCs */
"samsung,exynos4415-fimd"; /* for Exynos4415 SoC */
- "samsung,exynos5250-fimd"; /* for Exynos5 SoCs */
+ "samsung,exynos5250-fimd"; /* for Exynos5250 SoCs */
+ "samsung,exynos5420-fimd"; /* for Exynos5420/5422/5800 SoCs */
- reg: physical base address and length of the FIMD registers set.
diff --git a/Bindings/display/fsl,dcu.txt b/Bindings/display/fsl,dcu.txt
index ebf1be9ae393..ae55cde1b69e 100644
--- a/Bindings/display/fsl,dcu.txt
+++ b/Bindings/display/fsl,dcu.txt
@@ -6,17 +6,24 @@ Required properties:
* "fsl,vf610-dcu".
- reg: Address and length of the register set for dcu.
-- clocks: From common clock binding: handle to dcu clock.
-- clock-names: From common clock binding: Shall be "dcu".
+- clocks: Handle to "dcu" and "pix" clock (in the order below)
+ This can be the same clock (e.g. LS1021a)
+ See ../clocks/clock-bindings.txt for details.
+- clock-names: Should be "dcu" and "pix"
+ See ../clocks/clock-bindings.txt for details.
- big-endian Boolean property, LS1021A DCU registers are big-endian.
- fsl,panel: The phandle to panel node.
+Optional properties:
+- fsl,tcon: The phandle to the timing controller node.
+
Examples:
dcu: dcu@2ce0000 {
compatible = "fsl,ls1021a-dcu";
reg = <0x0 0x2ce0000 0x0 0x10000>;
- clocks = <&platform_clk 0>;
- clock-names = "dcu";
+ clocks = <&platform_clk 0>, <&platform_clk 0>;
+ clock-names = "dcu", "pix";
big-endian;
fsl,panel = <&panel>;
+ fsl,tcon = <&tcon>;
};
diff --git a/Bindings/display/fsl,tcon.txt b/Bindings/display/fsl,tcon.txt
new file mode 100644
index 000000000000..6fa4ab668db5
--- /dev/null
+++ b/Bindings/display/fsl,tcon.txt
@@ -0,0 +1,18 @@
+Device Tree bindings for Freescale TCON Driver
+
+Required properties:
+- compatible: Should be one of
+ * "fsl,vf610-tcon".
+
+- reg: Address and length of the register set for tcon.
+- clocks: From common clock binding: handle to tcon ipg clock.
+- clock-names: From common clock binding: Shall be "ipg".
+
+Examples:
+timing-controller@4003d000 {
+ compatible = "fsl,vf610-tcon";
+ reg = <0x4003d000 0x1000>;
+ clocks = <&clks VF610_CLK_TCON0>;
+ clock-names = "ipg";
+ status = "okay";
+};
diff --git a/Bindings/display/hisilicon/dw-dsi.txt b/Bindings/display/hisilicon/dw-dsi.txt
new file mode 100644
index 000000000000..d270bfe4e4e0
--- /dev/null
+++ b/Bindings/display/hisilicon/dw-dsi.txt
@@ -0,0 +1,72 @@
+Device-Tree bindings for DesignWare DSI Host Controller v1.20a driver
+
+A DSI Host Controller resides in the middle of display controller and external
+HDMI converter or panel.
+
+Required properties:
+- compatible: value should be "hisilicon,hi6220-dsi".
+- reg: physical base address and length of dsi controller's registers.
+- clocks: contains APB clock phandle + clock-specifier pair.
+- clock-names: should be "pclk".
+- ports: contains DSI controller input and output sub port.
+ The input port connects to ADE output port with the reg value "0".
+ The output port with the reg value "1", it could connect to panel or
+ any other bridge endpoints.
+ See Documentation/devicetree/bindings/graph.txt for more device graph info.
+
+A example of HiKey board hi6220 SoC and board specific DT entry:
+Example:
+
+SoC specific:
+ dsi: dsi@f4107800 {
+ compatible = "hisilicon,hi6220-dsi";
+ reg = <0x0 0xf4107800 0x0 0x100>;
+ clocks = <&media_ctrl HI6220_DSI_PCLK>;
+ clock-names = "pclk";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* 0 for input port */
+ port@0 {
+ reg = <0>;
+ dsi_in: endpoint {
+ remote-endpoint = <&ade_out>;
+ };
+ };
+ };
+ };
+
+
+Board specific:
+ &dsi {
+ status = "ok";
+
+ ports {
+ /* 1 for output port */
+ port@1 {
+ reg = <1>;
+
+ dsi_out0: endpoint@0 {
+ remote-endpoint = <&adv7533_in>;
+ };
+ };
+ };
+ };
+
+ &i2c2 {
+ ...
+
+ adv7533: adv7533@39 {
+ ...
+
+ port {
+ adv7533_in: endpoint {
+ remote-endpoint = <&dsi_out0>;
+ };
+ };
+ };
+ };
+
diff --git a/Bindings/display/hisilicon/hisi-ade.txt b/Bindings/display/hisilicon/hisi-ade.txt
new file mode 100644
index 000000000000..38dc9d60eef8
--- /dev/null
+++ b/Bindings/display/hisilicon/hisi-ade.txt
@@ -0,0 +1,64 @@
+Device-Tree bindings for hisilicon ADE display controller driver
+
+ADE (Advanced Display Engine) is the display controller which grab image
+data from memory, do composition, do post image processing, generate RGB
+timing stream and transfer to DSI.
+
+Required properties:
+- compatible: value should be "hisilicon,hi6220-ade".
+- reg: physical base address and length of the ADE controller's registers.
+- hisilicon,noc-syscon: ADE NOC QoS syscon.
+- resets: The ADE reset controller node.
+- interrupt: the ldi vblank interrupt number used.
+- clocks: a list of phandle + clock-specifier pairs, one for each entry
+ in clock-names.
+- clock-names: should contain:
+ "clk_ade_core" for the ADE core clock.
+ "clk_codec_jpeg" for the media NOC QoS clock, which use the same clock with
+ jpeg codec.
+ "clk_ade_pix" for the ADE pixel clok.
+- assigned-clocks: Should contain "clk_ade_core" and "clk_codec_jpeg" clocks'
+ phandle + clock-specifier pairs.
+- assigned-clock-rates: clock rates, one for each entry in assigned-clocks.
+ The rate of "clk_ade_core" could be "360000000" or "180000000";
+ The rate of "clk_codec_jpeg" could be or less than "1440000000".
+ These rate values could be configured according to performance and power
+ consumption.
+- port: the output port. This contains one endpoint subnode, with its
+ remote-endpoint set to the phandle of the connected DSI input endpoint.
+ See Documentation/devicetree/bindings/graph.txt for more device graph info.
+
+Optional properties:
+- dma-coherent: Present if dma operations are coherent.
+
+
+A example of HiKey board hi6220 SoC specific DT entry:
+Example:
+
+ ade: ade@f4100000 {
+ compatible = "hisilicon,hi6220-ade";
+ reg = <0x0 0xf4100000 0x0 0x7800>;
+ reg-names = "ade_base";
+ hisilicon,noc-syscon = <&medianoc_ade>;
+ resets = <&media_ctrl MEDIA_ADE>;
+ interrupts = <0 115 4>; /* ldi interrupt */
+
+ clocks = <&media_ctrl HI6220_ADE_CORE>,
+ <&media_ctrl HI6220_CODEC_JPEG>,
+ <&media_ctrl HI6220_ADE_PIX_SRC>;
+ /*clock name*/
+ clock-names = "clk_ade_core",
+ "clk_codec_jpeg",
+ "clk_ade_pix";
+
+ assigned-clocks = <&media_ctrl HI6220_ADE_CORE>,
+ <&media_ctrl HI6220_CODEC_JPEG>;
+ assigned-clock-rates = <360000000>, <288000000>;
+ dma-coherent;
+
+ port {
+ ade_out: endpoint {
+ remote-endpoint = <&dsi_in>;
+ };
+ };
+ };
diff --git a/Bindings/display/imx/ldb.txt b/Bindings/display/imx/ldb.txt
index 0a175d991b52..a407462c885e 100644
--- a/Bindings/display/imx/ldb.txt
+++ b/Bindings/display/imx/ldb.txt
@@ -62,6 +62,7 @@ Required properties:
display-timings are used instead.
Optional properties (required if display-timings are used):
+ - ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
- display-timings : A node that describes the display timings as defined in
Documentation/devicetree/bindings/display/display-timing.txt.
- fsl,data-mapping : should be "spwg" or "jeida"
diff --git a/Bindings/display/mediatek/mediatek,disp.txt b/Bindings/display/mediatek/mediatek,disp.txt
new file mode 100644
index 000000000000..db6e77edbea8
--- /dev/null
+++ b/Bindings/display/mediatek/mediatek,disp.txt
@@ -0,0 +1,203 @@
+Mediatek display subsystem
+==========================
+
+The Mediatek display subsystem consists of various DISP function blocks in the
+MMSYS register space. The connections between them can be configured by output
+and input selectors in the MMSYS_CONFIG register space. Pixel clock and start
+of frame signal are distributed to the other function blocks by a DISP_MUTEX
+function block.
+
+All DISP device tree nodes must be siblings to the central MMSYS_CONFIG node.
+For a description of the MMSYS_CONFIG binding, see
+Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt.
+
+DISP function blocks
+====================
+
+A display stream starts at a source function block that reads pixel data from
+memory and ends with a sink function block that drives pixels on a display
+interface, or writes pixels back to memory. All DISP function blocks have
+their own register space, interrupt, and clock gate. The blocks that can
+access memory additionally have to list the IOMMU and local arbiter they are
+connected to.
+
+For a description of the display interface sink function blocks, see
+Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt and
+Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt.
+
+Required properties (all function blocks):
+- compatible: "mediatek,<chip>-disp-<function>", one of
+ "mediatek,<chip>-disp-ovl" - overlay (4 layers, blending, csc)
+ "mediatek,<chip>-disp-rdma" - read DMA / line buffer
+ "mediatek,<chip>-disp-wdma" - write DMA
+ "mediatek,<chip>-disp-color" - color processor
+ "mediatek,<chip>-disp-aal" - adaptive ambient light controller
+ "mediatek,<chip>-disp-gamma" - gamma correction
+ "mediatek,<chip>-disp-merge" - merge streams from two RDMA sources
+ "mediatek,<chip>-disp-split" - split stream to two encoders
+ "mediatek,<chip>-disp-ufoe" - data compression engine
+ "mediatek,<chip>-dsi" - DSI controller, see mediatek,dsi.txt
+ "mediatek,<chip>-dpi" - DPI controller, see mediatek,dpi.txt
+ "mediatek,<chip>-disp-mutex" - display mutex
+ "mediatek,<chip>-disp-od" - overdrive
+- reg: Physical base address and length of the function block register space
+- interrupts: The interrupt signal from the function block (required, except for
+ merge and split function blocks).
+- clocks: device clocks
+ See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
+ For most function blocks this is just a single clock input. Only the DSI and
+ DPI controller nodes have multiple clock inputs. These are documented in
+ mediatek,dsi.txt and mediatek,dpi.txt, respectively.
+
+Required properties (DMA function blocks):
+- compatible: Should be one of
+ "mediatek,<chip>-disp-ovl"
+ "mediatek,<chip>-disp-rdma"
+ "mediatek,<chip>-disp-wdma"
+- larb: Should contain a phandle pointing to the local arbiter device as defined
+ in Documentation/devicetree/bindings/soc/mediatek/mediatek,smi-larb.txt
+- iommus: Should point to the respective IOMMU block with master port as
+ argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
+ for details.
+
+Examples:
+
+mmsys: clock-controller@14000000 {
+ compatible = "mediatek,mt8173-mmsys", "syscon";
+ reg = <0 0x14000000 0 0x1000>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ #clock-cells = <1>;
+};
+
+ovl0: ovl@1400c000 {
+ compatible = "mediatek,mt8173-disp-ovl";
+ reg = <0 0x1400c000 0 0x1000>;
+ interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_OVL0>;
+ iommus = <&iommu M4U_PORT_DISP_OVL0>;
+ mediatek,larb = <&larb0>;
+};
+
+ovl1: ovl@1400d000 {
+ compatible = "mediatek,mt8173-disp-ovl";
+ reg = <0 0x1400d000 0 0x1000>;
+ interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_OVL1>;
+ iommus = <&iommu M4U_PORT_DISP_OVL1>;
+ mediatek,larb = <&larb4>;
+};
+
+rdma0: rdma@1400e000 {
+ compatible = "mediatek,mt8173-disp-rdma";
+ reg = <0 0x1400e000 0 0x1000>;
+ interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_RDMA0>;
+ iommus = <&iommu M4U_PORT_DISP_RDMA0>;
+ mediatek,larb = <&larb0>;
+};
+
+rdma1: rdma@1400f000 {
+ compatible = "mediatek,mt8173-disp-rdma";
+ reg = <0 0x1400f000 0 0x1000>;
+ interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_RDMA1>;
+ iommus = <&iommu M4U_PORT_DISP_RDMA1>;
+ mediatek,larb = <&larb4>;
+};
+
+rdma2: rdma@14010000 {
+ compatible = "mediatek,mt8173-disp-rdma";
+ reg = <0 0x14010000 0 0x1000>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_RDMA2>;
+ iommus = <&iommu M4U_PORT_DISP_RDMA2>;
+ mediatek,larb = <&larb4>;
+};
+
+wdma0: wdma@14011000 {
+ compatible = "mediatek,mt8173-disp-wdma";
+ reg = <0 0x14011000 0 0x1000>;
+ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_WDMA0>;
+ iommus = <&iommu M4U_PORT_DISP_WDMA0>;
+ mediatek,larb = <&larb0>;
+};
+
+wdma1: wdma@14012000 {
+ compatible = "mediatek,mt8173-disp-wdma";
+ reg = <0 0x14012000 0 0x1000>;
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_WDMA1>;
+ iommus = <&iommu M4U_PORT_DISP_WDMA1>;
+ mediatek,larb = <&larb4>;
+};
+
+color0: color@14013000 {
+ compatible = "mediatek,mt8173-disp-color";
+ reg = <0 0x14013000 0 0x1000>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_COLOR0>;
+};
+
+color1: color@14014000 {
+ compatible = "mediatek,mt8173-disp-color";
+ reg = <0 0x14014000 0 0x1000>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_COLOR1>;
+};
+
+aal@14015000 {
+ compatible = "mediatek,mt8173-disp-aal";
+ reg = <0 0x14015000 0 0x1000>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_AAL>;
+};
+
+gamma@14016000 {
+ compatible = "mediatek,mt8173-disp-gamma";
+ reg = <0 0x14016000 0 0x1000>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_GAMMA>;
+};
+
+ufoe@1401a000 {
+ compatible = "mediatek,mt8173-disp-ufoe";
+ reg = <0 0x1401a000 0 0x1000>;
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_UFOE>;
+};
+
+dsi0: dsi@1401b000 {
+ /* See mediatek,dsi.txt for details */
+};
+
+dpi0: dpi@1401d000 {
+ /* See mediatek,dpi.txt for details */
+};
+
+mutex: mutex@14020000 {
+ compatible = "mediatek,mt8173-disp-mutex";
+ reg = <0 0x14020000 0 0x1000>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_MUTEX_32K>;
+};
+
+od@14023000 {
+ compatible = "mediatek,mt8173-disp-od";
+ reg = <0 0x14023000 0 0x1000>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_OD>;
+};
diff --git a/Bindings/display/mediatek/mediatek,dpi.txt b/Bindings/display/mediatek/mediatek,dpi.txt
new file mode 100644
index 000000000000..b6a7e7397b8b
--- /dev/null
+++ b/Bindings/display/mediatek/mediatek,dpi.txt
@@ -0,0 +1,35 @@
+Mediatek DPI Device
+===================
+
+The Mediatek DPI function block is a sink of the display subsystem and
+provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel
+output bus.
+
+Required properties:
+- compatible: "mediatek,<chip>-dpi"
+- reg: Physical base address and length of the controller's registers
+- interrupts: The interrupt signal from the function block.
+- clocks: device clocks
+ See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
+- clock-names: must contain "pixel", "engine", and "pll"
+- port: Output port node with endpoint definitions as described in
+ Documentation/devicetree/bindings/graph.txt. This port should be connected
+ to the input port of an attached HDMI or LVDS encoder chip.
+
+Example:
+
+dpi0: dpi@1401d000 {
+ compatible = "mediatek,mt8173-dpi";
+ reg = <0 0x1401d000 0 0x1000>;
+ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&mmsys CLK_MM_DPI_PIXEL>,
+ <&mmsys CLK_MM_DPI_ENGINE>,
+ <&apmixedsys CLK_APMIXED_TVDPLL>;
+ clock-names = "pixel", "engine", "pll";
+
+ port {
+ dpi0_out: endpoint {
+ remote-endpoint = <&hdmi0_in>;
+ };
+ };
+};
diff --git a/Bindings/display/mediatek/mediatek,dsi.txt b/Bindings/display/mediatek/mediatek,dsi.txt
new file mode 100644
index 000000000000..2b1585a34b85
--- /dev/null
+++ b/Bindings/display/mediatek/mediatek,dsi.txt
@@ -0,0 +1,60 @@
+Mediatek DSI Device
+===================
+
+The Mediatek DSI function block is a sink of the display subsystem and can
+drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
+channel output.
+
+Required properties:
+- compatible: "mediatek,<chip>-dsi"
+- reg: Physical base address and length of the controller's registers
+- interrupts: The interrupt signal from the function block.
+- clocks: device clocks
+ See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
+- clock-names: must contain "engine", "digital", and "hs"
+- phys: phandle link to the MIPI D-PHY controller.
+- phy-names: must contain "dphy"
+- port: Output port node with endpoint definitions as described in
+ Documentation/devicetree/bindings/graph.txt. This port should be connected
+ to the input port of an attached DSI panel or DSI-to-eDP encoder chip.
+
+MIPI TX Configuration Module
+============================
+
+The MIPI TX configuration module controls the MIPI D-PHY.
+
+Required properties:
+- compatible: "mediatek,<chip>-mipi-tx"
+- reg: Physical base address and length of the controller's registers
+- clocks: PLL reference clock
+- clock-output-names: name of the output clock line to the DSI encoder
+- #clock-cells: must be <0>;
+- #phy-cells: must be <0>.
+
+Example:
+
+mipi_tx0: mipi-dphy@10215000 {
+ compatible = "mediatek,mt8173-mipi-tx";
+ reg = <0 0x10215000 0 0x1000>;
+ clocks = <&clk26m>;
+ clock-output-names = "mipi_tx0_pll";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+};
+
+dsi0: dsi@1401b000 {
+ compatible = "mediatek,mt8173-dsi";
+ reg = <0 0x1401b000 0 0x1000>;
+ interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>,
+ <&mipi_tx0>;
+ clock-names = "engine", "digital", "hs";
+ phys = <&mipi_tx0>;
+ phy-names = "dphy";
+
+ port {
+ dsi0_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+};
diff --git a/Bindings/display/msm/dsi.txt b/Bindings/display/msm/dsi.txt
index e7423bea1424..f5948c48b9a2 100644
--- a/Bindings/display/msm/dsi.txt
+++ b/Bindings/display/msm/dsi.txt
@@ -44,9 +44,34 @@ Optional properties:
- pinctrl-names: the pin control state names; should contain "default"
- pinctrl-0: the default pinctrl state (active)
- pinctrl-n: the "sleep" pinctrl state
-- port: DSI controller output port. This contains one endpoint subnode, with its
- remote-endpoint set to the phandle of the connected panel's endpoint.
- See Documentation/devicetree/bindings/graph.txt for device graph info.
+- port: DSI controller output port, containing one endpoint subnode.
+
+ DSI Endpoint properties:
+ - remote-endpoint: set to phandle of the connected panel's endpoint.
+ See Documentation/devicetree/bindings/graph.txt for device graph info.
+ - qcom,data-lane-map: this describes how the logical DSI lanes are mapped
+ to the physical lanes on the given platform. The value contained in
+ index n describes what logical data lane is mapped to the physical data
+ lane n (DATAn, where n lies between 0 and 3).
+
+ For example:
+
+ qcom,data-lane-map = <3 0 1 2>;
+
+ The above mapping describes that the logical data lane DATA3 is mapped to
+ the physical data lane DATA0, logical DATA0 to physical DATA1, logic DATA1
+ to phys DATA2 and logic DATA2 to phys DATA3.
+
+ There are only a limited number of physical to logical mappings possible:
+
+ "0123": Logic 0->Phys 0; Logic 1->Phys 1; Logic 2->Phys 2; Logic 3->Phys 3;
+ "3012": Logic 3->Phys 0; Logic 0->Phys 1; Logic 1->Phys 2; Logic 2->Phys 3;
+ "2301": Logic 2->Phys 0; Logic 3->Phys 1; Logic 0->Phys 2; Logic 1->Phys 3;
+ "1230": Logic 1->Phys 0; Logic 2->Phys 1; Logic 3->Phys 2; Logic 0->Phys 3;
+ "0321": Logic 0->Phys 0; Logic 3->Phys 1; Logic 2->Phys 2; Logic 1->Phys 3;
+ "1032": Logic 1->Phys 0; Logic 0->Phys 1; Logic 3->Phys 2; Logic 2->Phys 3;
+ "2103": Logic 2->Phys 0; Logic 1->Phys 1; Logic 0->Phys 2; Logic 3->Phys 3;
+ "3210": Logic 3->Phys 0; Logic 2->Phys 1; Logic 1->Phys 2; Logic 0->Phys 3;
DSI PHY:
Required properties:
@@ -131,6 +156,7 @@ Example:
port {
dsi0_out: endpoint {
remote-endpoint = <&panel_in>;
+ lanes = <0 1 2 3>;
};
};
};
diff --git a/Bindings/display/msm/hdmi.txt b/Bindings/display/msm/hdmi.txt
index 379ee2ea9a3d..b63f614e0c04 100644
--- a/Bindings/display/msm/hdmi.txt
+++ b/Bindings/display/msm/hdmi.txt
@@ -11,6 +11,7 @@ Required properties:
- reg: Physical base address and length of the controller's registers
- reg-names: "core_physical"
- interrupts: The interrupt signal from the hdmi block.
+- power-domains: Should be <&mmcc MDSS_GDSC>.
- clocks: device clocks
See ../clocks/clock-bindings.txt for details.
- qcom,hdmi-tx-ddc-clk-gpio: ddc clk pin
@@ -18,6 +19,8 @@ Required properties:
- qcom,hdmi-tx-hpd-gpio: hpd pin
- core-vdda-supply: phandle to supply regulator
- hdmi-mux-supply: phandle to mux regulator
+- phys: the phandle for the HDMI PHY device
+- phy-names: the name of the corresponding PHY device
Optional properties:
- qcom,hdmi-tx-mux-en-gpio: hdmi mux enable pin
@@ -27,15 +30,38 @@ Optional properties:
- pinctrl-0: the default pinctrl state (active)
- pinctrl-1: the "sleep" pinctrl state
+HDMI PHY:
+Required properties:
+- compatible: Could be the following
+ * "qcom,hdmi-phy-8660"
+ * "qcom,hdmi-phy-8960"
+ * "qcom,hdmi-phy-8974"
+ * "qcom,hdmi-phy-8084"
+ * "qcom,hdmi-phy-8996"
+- #phy-cells: Number of cells in a PHY specifier; Should be 0.
+- reg: Physical base address and length of the registers of the PHY sub blocks.
+- reg-names: The names of register regions. The following regions are required:
+ * "hdmi_phy"
+ * "hdmi_pll"
+ For HDMI PHY on msm8996, these additional register regions are required:
+ * "hdmi_tx_l0"
+ * "hdmi_tx_l1"
+ * "hdmi_tx_l3"
+ * "hdmi_tx_l4"
+- power-domains: Should be <&mmcc MDSS_GDSC>.
+- clocks: device clocks
+ See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.
+- core-vdda-supply: phandle to vdda regulator device node
+
Example:
/ {
...
- hdmi: qcom,hdmi-tx-8960@4a00000 {
+ hdmi: hdmi@4a00000 {
compatible = "qcom,hdmi-tx-8960";
reg-names = "core_physical";
- reg = <0x04a00000 0x1000>;
+ reg = <0x04a00000 0x2f0>;
interrupts = <GIC_SPI 79 0>;
power-domains = <&mmcc MDSS_GDSC>;
clock-names =
@@ -54,5 +80,21 @@ Example:
pinctrl-names = "default", "sleep";
pinctrl-0 = <&hpd_active &ddc_active &cec_active>;
pinctrl-1 = <&hpd_suspend &ddc_suspend &cec_suspend>;
+
+ phys = <&hdmi_phy>;
+ phy-names = "hdmi_phy";
+ };
+
+ hdmi_phy: phy@4a00400 {
+ compatible = "qcom,hdmi-phy-8960";
+ reg-names = "hdmi_phy",
+ "hdmi_pll";
+ reg = <0x4a00400 0x60>,
+ <0x4a00500 0x100>;
+ #phy-cells = <0>;
+ power-domains = <&mmcc MDSS_GDSC>;
+ clock-names = "slave_iface_clk";
+ clocks = <&mmcc HDMI_S_AHB_CLK>;
+ core-vdda-supply = <&pm8921_hdmi_mvs>;
};
};
diff --git a/Bindings/display/panel/innolux,at070tn92.txt b/Bindings/display/panel/innolux,at070tn92.txt
new file mode 100644
index 000000000000..3e10cd782491
--- /dev/null
+++ b/Bindings/display/panel/innolux,at070tn92.txt
@@ -0,0 +1,7 @@
+Innolux AT070TN92 7.0" WQVGA TFT LCD panel
+
+Required properties:
+- compatible: should be "innolux,at070tn92"
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/Bindings/display/panel/lg,lp120up1.txt b/Bindings/display/panel/lg,lp120up1.txt
new file mode 100644
index 000000000000..8c5de692c55c
--- /dev/null
+++ b/Bindings/display/panel/lg,lp120up1.txt
@@ -0,0 +1,7 @@
+LG 12.0" (1920x1280 pixels) TFT LCD panel
+
+Required properties:
+- compatible: should be "lg,lp120up1"
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/Bindings/display/panel/olimex,lcd-olinuxino-43-ts.txt b/Bindings/display/panel/olimex,lcd-olinuxino-43-ts.txt
new file mode 100644
index 000000000000..74540a090669
--- /dev/null
+++ b/Bindings/display/panel/olimex,lcd-olinuxino-43-ts.txt
@@ -0,0 +1,7 @@
+Olimex 4.3" TFT LCD panel
+
+Required properties:
+- compatible: should be "olimex,lcd-olinuxino-43-ts"
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/Bindings/display/panel/ontat,yx700wv03.txt b/Bindings/display/panel/ontat,yx700wv03.txt
new file mode 100644
index 000000000000..3d8a5e029242
--- /dev/null
+++ b/Bindings/display/panel/ontat,yx700wv03.txt
@@ -0,0 +1,7 @@
+On Tat Industrial Company 7" DPI TFT panel.
+
+Required properties:
+- compatible: should be "ontat,yx700wv03"
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/Bindings/display/panel/tpk,f07a-0102.txt b/Bindings/display/panel/tpk,f07a-0102.txt
new file mode 100644
index 000000000000..a2613b9675df
--- /dev/null
+++ b/Bindings/display/panel/tpk,f07a-0102.txt
@@ -0,0 +1,8 @@
+TPK U.S.A. LLC Fusion 7" integrated projected capacitive touch display with,
+800 x 480 (WVGA) LCD panel.
+
+Required properties:
+- compatible: should be "tpk,f07a-0102"
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/Bindings/display/panel/tpk,f10a-0102.txt b/Bindings/display/panel/tpk,f10a-0102.txt
new file mode 100644
index 000000000000..b9d051196ba9
--- /dev/null
+++ b/Bindings/display/panel/tpk,f10a-0102.txt
@@ -0,0 +1,8 @@
+TPK U.S.A. LLC Fusion 10.1" integrated projected capacitive touch display with,
+1024 x 600 (WSVGA) LCD panel.
+
+Required properties:
+- compatible: should be "tpk,f10a-0102"
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/Bindings/display/panel/urt,umsh-8596md.txt b/Bindings/display/panel/urt,umsh-8596md.txt
new file mode 100644
index 000000000000..088a6cea5015
--- /dev/null
+++ b/Bindings/display/panel/urt,umsh-8596md.txt
@@ -0,0 +1,16 @@
+United Radiant Technology UMSH-8596MD-xT 7.0" WVGA TFT LCD panel
+
+Supported are LVDS versions (-11T, -19T) and parallel ones
+(-T, -1T, -7T, -20T).
+
+Required properties:
+- compatible: should be one of:
+ "urt,umsh-8596md-t",
+ "urt,umsh-8596md-1t",
+ "urt,umsh-8596md-7t",
+ "urt,umsh-8596md-11t",
+ "urt,umsh-8596md-19t",
+ "urt,umsh-8596md-20t".
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/Bindings/display/renesas,du.txt b/Bindings/display/renesas,du.txt
index eccd4f4867b2..0d30e42e40be 100644
--- a/Bindings/display/renesas,du.txt
+++ b/Bindings/display/renesas,du.txt
@@ -8,6 +8,7 @@ Required Properties:
- "renesas,du-r8a7791" for R8A7791 (R-Car M2-W) compatible DU
- "renesas,du-r8a7793" for R8A7793 (R-Car M2-N) compatible DU
- "renesas,du-r8a7794" for R8A7794 (R-Car E2) compatible DU
+ - "renesas,du-r8a7795" for R8A7795 (R-Car H3) compatible DU
- reg: A list of base address and length of each memory resource, one for
each entry in the reg-names property.
@@ -24,7 +25,7 @@ Required Properties:
- clock-names: Name of the clocks. This property is model-dependent.
- R8A7779 uses a single functional clock. The clock doesn't need to be
named.
- - R8A779[0134] use one functional clock per channel and one clock per LVDS
+ - R8A779[01345] use one functional clock per channel and one clock per LVDS
encoder (if available). The functional clocks must be named "du.x" with
"x" being the channel numerical index. The LVDS clocks must be named
"lvds.x" with "x" being the LVDS encoder numerical index.
@@ -41,13 +42,14 @@ bindings specified in Documentation/devicetree/bindings/graph.txt.
The following table lists for each supported model the port number
corresponding to each DU output.
- Port 0 Port1 Port2
+ Port 0 Port1 Port2 Port3
-----------------------------------------------------------------------------
- R8A7779 (H1) DPAD 0 DPAD 1 -
- R8A7790 (H2) DPAD LVDS 0 LVDS 1
- R8A7791 (M2-W) DPAD LVDS 0 -
- R8A7793 (M2-N) DPAD LVDS 0 -
- R8A7794 (E2) DPAD 0 DPAD 1 -
+ R8A7779 (H1) DPAD 0 DPAD 1 - -
+ R8A7790 (H2) DPAD LVDS 0 LVDS 1 -
+ R8A7791 (M2-W) DPAD LVDS 0 - -
+ R8A7793 (M2-N) DPAD LVDS 0 - -
+ R8A7794 (E2) DPAD 0 DPAD 1 - -
+ R8A7795 (H3) DPAD HDMI 0 HDMI 1 LVDS
Example: R8A7790 (R-Car H2) DU
diff --git a/Bindings/display/rockchip/analogix_dp-rockchip.txt b/Bindings/display/rockchip/analogix_dp-rockchip.txt
new file mode 100644
index 000000000000..e832ff98fd61
--- /dev/null
+++ b/Bindings/display/rockchip/analogix_dp-rockchip.txt
@@ -0,0 +1,92 @@
+Rockchip RK3288 specific extensions to the Analogix Display Port
+================================
+
+Required properties:
+- compatible: "rockchip,rk3288-edp";
+
+- reg: physical base address of the controller and length
+
+- clocks: from common clock binding: handle to dp clock.
+ of memory mapped region.
+
+- clock-names: from common clock binding:
+ Required elements: "dp" "pclk"
+
+- resets: Must contain an entry for each entry in reset-names.
+ See ../reset/reset.txt for details.
+
+- pinctrl-names: Names corresponding to the chip hotplug pinctrl states.
+- pinctrl-0: pin-control mode. should be <&edp_hpd>
+
+- reset-names: Must include the name "dp"
+
+- rockchip,grf: this soc should set GRF regs, so need get grf here.
+
+- ports: there are 2 port nodes with endpoint definitions as defined in
+ Documentation/devicetree/bindings/media/video-interfaces.txt.
+ Port 0: contained 2 endpoints, connecting to the output of vop.
+ Port 1: contained 1 endpoint, connecting to the input of panel.
+
+For the below properties, please refer to Analogix DP binding document:
+ * Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
+- phys (required)
+- phy-names (required)
+- hpd-gpios (optional)
+- force-hpd (optional)
+-------------------------------------------------------------------------------
+
+Example:
+ dp-controller: dp@ff970000 {
+ compatible = "rockchip,rk3288-dp";
+ reg = <0xff970000 0x4000>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
+ clock-names = "dp", "pclk";
+ phys = <&dp_phy>;
+ phy-names = "dp";
+
+ rockchip,grf = <&grf>;
+ resets = <&cru 111>;
+ reset-names = "dp";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&edp_hpd>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ edp_in: port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ edp_in_vopb: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vopb_out_edp>;
+ };
+ edp_in_vopl: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vopl_out_edp>;
+ };
+ };
+
+ edp_out: port@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ edp_out_panel: endpoint {
+ reg = <0>;
+ remote-endpoint = <&panel_in_edp>
+ };
+ };
+ };
+ };
+
+ pinctrl {
+ edp {
+ edp_hpd: edp-hpd {
+ rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+ };
diff --git a/Bindings/display/rockchip/inno_hdmi-rockchip.txt b/Bindings/display/rockchip/inno_hdmi-rockchip.txt
new file mode 100644
index 000000000000..8096a29f9776
--- /dev/null
+++ b/Bindings/display/rockchip/inno_hdmi-rockchip.txt
@@ -0,0 +1,50 @@
+Rockchip specific extensions to the Innosilicon HDMI
+================================
+
+Required properties:
+- compatible:
+ "rockchip,rk3036-inno-hdmi";
+- reg:
+ Physical base address and length of the controller's registers.
+- clocks, clock-names:
+ Phandle to hdmi controller clock, name should be "pclk"
+- interrupts:
+ HDMI interrupt number
+- ports:
+ Contain one port node with endpoint definitions as defined in
+ Documentation/devicetree/bindings/graph.txt.
+- pinctrl-0, pinctrl-name:
+ Switch the iomux of HPD/CEC pins to HDMI function.
+
+Example:
+hdmi: hdmi@20034000 {
+ compatible = "rockchip,rk3036-inno-hdmi";
+ reg = <0x20034000 0x4000>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_HDMI>;
+ clock-names = "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_ctl>;
+ status = "disabled";
+
+ hdmi_in: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ hdmi_in_lcdc: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&lcdc_out_hdmi>;
+ };
+ };
+};
+
+&pinctrl {
+ hdmi {
+ hdmi_ctl: hdmi-ctl {
+ rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>,
+ <1 9 RK_FUNC_1 &pcfg_pull_none>,
+ <1 10 RK_FUNC_1 &pcfg_pull_none>,
+ <1 11 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+};
diff --git a/Bindings/display/snps,arcpgu.txt b/Bindings/display/snps,arcpgu.txt
new file mode 100644
index 000000000000..c5c7dfd37df2
--- /dev/null
+++ b/Bindings/display/snps,arcpgu.txt
@@ -0,0 +1,35 @@
+ARC PGU
+
+This is a display controller found on several development boards produced
+by Synopsys. The ARC PGU is an RGB streamer that reads the data from a
+framebuffer and sends it to a single digital encoder (usually HDMI).
+
+Required properties:
+ - compatible: "snps,arcpgu"
+ - reg: Physical base address and length of the controller's registers.
+ - clocks: A list of phandle + clock-specifier pairs, one for each
+ entry in 'clock-names'.
+ - clock-names: A list of clock names. For ARC PGU it should contain:
+ - "pxlclk" for the clock feeding the output PLL of the controller.
+
+Required sub-nodes:
+ - port: The PGU connection to an encoder chip.
+
+Example:
+
+/ {
+ ...
+
+ pgu@XXXXXXXX {
+ compatible = "snps,arcpgu";
+ reg = <0xXXXXXXXX 0x400>;
+ clocks = <&clock_node>;
+ clock-names = "pxlclk";
+
+ port {
+ pgu_output: endpoint {
+ remote-endpoint = <&hdmi_enc_input>;
+ };
+ };
+ };
+};
diff --git a/Bindings/display/sunxi/sun4i-drm.txt b/Bindings/display/sunxi/sun4i-drm.txt
new file mode 100644
index 000000000000..df8f4aeefe4c
--- /dev/null
+++ b/Bindings/display/sunxi/sun4i-drm.txt
@@ -0,0 +1,258 @@
+Allwinner A10 Display Pipeline
+==============================
+
+The Allwinner A10 Display pipeline is composed of several components
+that are going to be documented below:
+
+TV Encoder
+----------
+
+The TV Encoder supports the composite and VGA output. It is one end of
+the pipeline.
+
+Required properties:
+ - compatible: value should be "allwinner,sun4i-a10-tv-encoder".
+ - reg: base address and size of memory-mapped region
+ - clocks: the clocks driving the TV encoder
+ - resets: phandle to the reset controller driving the encoder
+
+- ports: A ports node with endpoint definitions as defined in
+ Documentation/devicetree/bindings/media/video-interfaces.txt. The
+ first port should be the input endpoint.
+
+TCON
+----
+
+The TCON acts as a timing controller for RGB, LVDS and TV interfaces.
+
+Required properties:
+ - compatible: value should be "allwinner,sun5i-a13-tcon".
+ - reg: base address and size of memory-mapped region
+ - interrupts: interrupt associated to this IP
+ - clocks: phandles to the clocks feeding the TCON. Three are needed:
+ - 'ahb': the interface clocks
+ - 'tcon-ch0': The clock driving the TCON channel 0
+ - 'tcon-ch1': The clock driving the TCON channel 1
+ - resets: phandles to the reset controllers driving the encoder
+ - "lcd": the reset line for the TCON channel 0
+
+ - clock-names: the clock names mentioned above
+ - reset-names: the reset names mentioned above
+ - clock-output-names: Name of the pixel clock created
+
+- ports: A ports node with endpoint definitions as defined in
+ Documentation/devicetree/bindings/media/video-interfaces.txt. The
+ first port should be the input endpoint, the second one the output
+
+ The output should have two endpoints. The first is the block
+ connected to the TCON channel 0 (usually a panel or a bridge), the
+ second the block connected to the TCON channel 1 (usually the TV
+ encoder)
+
+
+Display Engine Backend
+----------------------
+
+The display engine backend exposes layers and sprites to the
+system.
+
+Required properties:
+ - compatible: value must be one of:
+ * allwinner,sun5i-a13-display-backend
+ - reg: base address and size of the memory-mapped region.
+ - clocks: phandles to the clocks feeding the frontend and backend
+ * ahb: the backend interface clock
+ * mod: the backend module clock
+ * ram: the backend DRAM clock
+ - clock-names: the clock names mentioned above
+ - resets: phandles to the reset controllers driving the backend
+
+- ports: A ports node with endpoint definitions as defined in
+ Documentation/devicetree/bindings/media/video-interfaces.txt. The
+ first port should be the input endpoints, the second one the output
+
+Display Engine Frontend
+-----------------------
+
+The display engine frontend does formats conversion, scaling,
+deinterlacing and color space conversion.
+
+Required properties:
+ - compatible: value must be one of:
+ * allwinner,sun5i-a13-display-frontend
+ - reg: base address and size of the memory-mapped region.
+ - interrupts: interrupt associated to this IP
+ - clocks: phandles to the clocks feeding the frontend and backend
+ * ahb: the backend interface clock
+ * mod: the backend module clock
+ * ram: the backend DRAM clock
+ - clock-names: the clock names mentioned above
+ - resets: phandles to the reset controllers driving the backend
+
+- ports: A ports node with endpoint definitions as defined in
+ Documentation/devicetree/bindings/media/video-interfaces.txt. The
+ first port should be the input endpoints, the second one the outputs
+
+
+Display Engine Pipeline
+-----------------------
+
+The display engine pipeline (and its entry point, since it can be
+either directly the backend or the frontend) is represented as an
+extra node.
+
+Required properties:
+ - compatible: value must be one of:
+ * allwinner,sun5i-a13-display-engine
+
+ - allwinner,pipelines: list of phandle to the display engine
+ frontends available.
+
+Example:
+
+panel: panel {
+ compatible = "olimex,lcd-olinuxino-43-ts";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ panel_input: endpoint {
+ remote-endpoint = <&tcon0_out_panel>;
+ };
+ };
+};
+
+tve0: tv-encoder@01c0a000 {
+ compatible = "allwinner,sun4i-a10-tv-encoder";
+ reg = <0x01c0a000 0x1000>;
+ clocks = <&ahb_gates 34>;
+ resets = <&tcon_ch0_clk 0>;
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tve0_in_tcon0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon0_out_tve0>;
+ };
+ };
+};
+
+tcon0: lcd-controller@1c0c000 {
+ compatible = "allwinner,sun5i-a13-tcon";
+ reg = <0x01c0c000 0x1000>;
+ interrupts = <44>;
+ resets = <&tcon_ch0_clk 1>;
+ reset-names = "lcd";
+ clocks = <&ahb_gates 36>,
+ <&tcon_ch0_clk>,
+ <&tcon_ch1_clk>;
+ clock-names = "ahb",
+ "tcon-ch0",
+ "tcon-ch1";
+ clock-output-names = "tcon-pixel-clock";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon0_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ tcon0_in_be0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&be0_out_tcon0>;
+ };
+ };
+
+ tcon0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ tcon0_out_panel: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&panel_input>;
+ };
+
+ tcon0_out_tve0: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&tve0_in_tcon0>;
+ };
+ };
+ };
+};
+
+fe0: display-frontend@1e00000 {
+ compatible = "allwinner,sun5i-a13-display-frontend";
+ reg = <0x01e00000 0x20000>;
+ interrupts = <47>;
+ clocks = <&ahb_gates 46>, <&de_fe_clk>,
+ <&dram_gates 25>;
+ clock-names = "ahb", "mod",
+ "ram";
+ resets = <&de_fe_clk>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fe0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ fe0_out_be0: endpoint {
+ remote-endpoint = <&be0_in_fe0>;
+ };
+ };
+ };
+};
+
+be0: display-backend@1e60000 {
+ compatible = "allwinner,sun5i-a13-display-backend";
+ reg = <0x01e60000 0x10000>;
+ clocks = <&ahb_gates 44>, <&de_be_clk>,
+ <&dram_gates 26>;
+ clock-names = "ahb", "mod",
+ "ram";
+ resets = <&de_be_clk>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ be0_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ be0_in_fe0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&fe0_out_be0>;
+ };
+ };
+
+ be0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ be0_out_tcon0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon0_in_be0>;
+ };
+ };
+ };
+};
+
+display-engine {
+ compatible = "allwinner,sun5i-a13-display-engine";
+ allwinner,pipelines = <&fe0>;
+};
diff --git a/Bindings/dma/arm-pl330.txt b/Bindings/dma/arm-pl330.txt
index 267565894db9..db7e2260f9c5 100644
--- a/Bindings/dma/arm-pl330.txt
+++ b/Bindings/dma/arm-pl330.txt
@@ -15,6 +15,7 @@ Optional properties:
cells in the dmas property of client device.
- dma-channels: contains the total number of DMA channels supported by the DMAC
- dma-requests: contains the total number of DMA requests supported by the DMAC
+ - arm,pl330-broken-no-flushp: quirk for avoiding to execute DMAFLUSHP
Example:
diff --git a/Bindings/dma/brcm,bcm2835-dma.txt b/Bindings/dma/brcm,bcm2835-dma.txt
index 1396078d15ac..baf9b34d20bf 100644
--- a/Bindings/dma/brcm,bcm2835-dma.txt
+++ b/Bindings/dma/brcm,bcm2835-dma.txt
@@ -12,6 +12,10 @@ Required properties:
- reg: Should contain DMA registers location and length.
- interrupts: Should contain the DMA interrupts associated
to the DMA channels in ascending order.
+- interrupt-names: Should contain the names of the interrupt
+ in the form "dmaXX".
+ Use "dma-shared-all" for the common interrupt line
+ that is shared by all dma channels.
- #dma-cells: Must be <1>, the cell in the dmas property of the
client device represents the DREQ number.
- brcm,dma-channel-mask: Bit mask representing the channels
@@ -34,13 +38,35 @@ dma: dma@7e007000 {
<1 24>,
<1 25>,
<1 26>,
+ /* dma channel 11-14 share one irq */
<1 27>,
+ <1 27>,
+ <1 27>,
+ <1 27>,
+ /* unused shared irq for all channels */
<1 28>;
+ interrupt-names = "dma0",
+ "dma1",
+ "dma2",
+ "dma3",
+ "dma4",
+ "dma5",
+ "dma6",
+ "dma7",
+ "dma8",
+ "dma9",
+ "dma10",
+ "dma11",
+ "dma12",
+ "dma13",
+ "dma14",
+ "dma-shared-all";
#dma-cells = <1>;
brcm,dma-channel-mask = <0x7f35>;
};
+
DMA clients connected to the BCM2835 DMA controller must use the format
described in the dma.txt file, using a two-cell specifier for each channel.
diff --git a/Bindings/dma/fsl-imx-sdma.txt b/Bindings/dma/fsl-imx-sdma.txt
index dc8d3aac1aa9..175f0e44ed85 100644
--- a/Bindings/dma/fsl-imx-sdma.txt
+++ b/Bindings/dma/fsl-imx-sdma.txt
@@ -58,6 +58,15 @@ The third cell specifies the transfer priority as below.
1 Medium
2 Low
+Optional properties:
+
+- gpr : The phandle to the General Purpose Register (GPR) node.
+- fsl,sdma-event-remap : Register bits of sdma event remap, the format is
+ <reg shift val>.
+ reg is the GPR register offset.
+ shift is the bit position inside the GPR register.
+ val is the value of the bit (0 or 1).
+
Examples:
sdma@83fb0000 {
@@ -83,3 +92,21 @@ ssi2: ssi@70014000 {
dma-names = "rx", "tx";
fsl,fifo-depth = <15>;
};
+
+Using the fsl,sdma-event-remap property:
+
+If we want to use SDMA on the SAI1 port on a MX6SX:
+
+&sdma {
+ gpr = <&gpr>;
+ /* SDMA events remap for SAI1_RX and SAI1_TX */
+ fsl,sdma-event-remap = <0 15 1>, <0 16 1>;
+};
+
+The fsl,sdma-event-remap property in this case has two values:
+- <0 15 1> means that the offset is 0, so GPR0 is the register of the
+SDMA remap. Bit 15 of GPR0 selects between UART4_RX and SAI1_RX.
+Setting bit 15 to 1 selects SAI1_RX.
+- <0 16 1> means that the offset is 0, so GPR0 is the register of the
+SDMA remap. Bit 16 of GPR0 selects between UART4_TX and SAI1_TX.
+Setting bit 16 to 1 selects SAI1_TX.
diff --git a/Bindings/dma/mmp-dma.txt b/Bindings/dma/mmp-dma.txt
index 7a802f64e5bd..8f7364a7b349 100644
--- a/Bindings/dma/mmp-dma.txt
+++ b/Bindings/dma/mmp-dma.txt
@@ -12,6 +12,8 @@ Required properties:
Optional properties:
- #dma-channels: Number of DMA channels supported by the controller (defaults
to 32 when not specified)
+- #dma-requests: Number of DMA requestor lines supported by the controller
+ (defaults to 32 when not specified)
"marvell,pdma-1.0"
Used platforms: pxa25x, pxa27x, pxa3xx, pxa93x, pxa168, pxa910, pxa688.
diff --git a/Bindings/dma/mv-xor.txt b/Bindings/dma/mv-xor.txt
index 276ef815ef32..c075f5988135 100644
--- a/Bindings/dma/mv-xor.txt
+++ b/Bindings/dma/mv-xor.txt
@@ -1,7 +1,10 @@
* Marvell XOR engines
Required properties:
-- compatible: Should be "marvell,orion-xor" or "marvell,armada-380-xor"
+- compatible: Should be one of the following:
+ - "marvell,orion-xor"
+ - "marvell,armada-380-xor"
+ - "marvell,armada-3700-xor".
- reg: Should contain registers location and length (two sets)
the first set is the low registers, the second set the high
registers for the XOR engine.
diff --git a/Bindings/dma/tegra20-apbdma.txt b/Bindings/dma/nvidia,tegra20-apbdma.txt
index c6908e7c42cc..c6908e7c42cc 100644
--- a/Bindings/dma/tegra20-apbdma.txt
+++ b/Bindings/dma/nvidia,tegra20-apbdma.txt
diff --git a/Bindings/dma/nvidia,tegra210-adma.txt b/Bindings/dma/nvidia,tegra210-adma.txt
new file mode 100644
index 000000000000..1e1dc8f972e4
--- /dev/null
+++ b/Bindings/dma/nvidia,tegra210-adma.txt
@@ -0,0 +1,55 @@
+* NVIDIA Tegra Audio DMA (ADMA) controller
+
+The Tegra Audio DMA controller that is used for transferring data
+between system memory and the Audio Processing Engine (APE).
+
+Required properties:
+- compatible: Must be "nvidia,tegra210-adma".
+- reg: Should contain DMA registers location and length. This should be
+ a single entry that includes all of the per-channel registers in one
+ contiguous bank.
+- interrupt-parent: Phandle to the interrupt parent controller.
+- interrupts: Should contain all of the per-channel DMA interrupts in
+ ascending order with respect to the DMA channel index.
+- clocks: Must contain one entry for the ADMA module clock
+ (TEGRA210_CLK_D_AUDIO).
+- clock-names: Must contain the name "d_audio" for the corresponding
+ 'clocks' entry.
+- #dma-cells : Must be 1. The first cell denotes the receive/transmit
+ request number and should be between 1 and the maximum number of
+ requests supported. This value corresponds to the RX/TX_REQUEST_SELECT
+ fields in the ADMA_CHn_CTRL register.
+
+
+Example:
+
+adma: dma@702e2000 {
+ compatible = "nvidia,tegra210-adma";
+ reg = <0x0 0x702e2000 0x0 0x2000>;
+ interrupt-parent = <&tegra_agic>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
+ clock-names = "d_audio";
+ #dma-cells = <1>;
+};
diff --git a/Bindings/dma/qcom_bam_dma.txt b/Bindings/dma/qcom_bam_dma.txt
index 1c9d48ea4914..9cbf5d9df8fd 100644
--- a/Bindings/dma/qcom_bam_dma.txt
+++ b/Bindings/dma/qcom_bam_dma.txt
@@ -13,6 +13,8 @@ Required properties:
- clock-names: must contain "bam_clk" entry
- qcom,ee : indicates the active Execution Environment identifier (0-7) used in
the secure world.
+- qcom,controlled-remotely : optional, indicates that the bam is controlled by
+ remote proccessor i.e. execution environment.
Example:
diff --git a/Bindings/dma/qcom_hidma_mgmt.txt b/Bindings/dma/qcom_hidma_mgmt.txt
new file mode 100644
index 000000000000..fd5618bd8fbc
--- /dev/null
+++ b/Bindings/dma/qcom_hidma_mgmt.txt
@@ -0,0 +1,89 @@
+Qualcomm Technologies HIDMA Management interface
+
+Qualcomm Technologies HIDMA is a high speed DMA device. It only supports
+memcpy and memset capabilities. It has been designed for virtualized
+environments.
+
+Each HIDMA HW instance consists of multiple DMA channels. These channels
+share the same bandwidth. The bandwidth utilization can be parititioned
+among channels based on the priority and weight assignments.
+
+There are only two priority levels and 15 weigh assignments possible.
+
+Other parameters here determine how much of the system bus this HIDMA
+instance can use like maximum read/write request and and number of bytes to
+read/write in a single burst.
+
+Main node required properties:
+- compatible: "qcom,hidma-mgmt-1.0";
+- reg: Address range for DMA device
+- dma-channels: Number of channels supported by this DMA controller.
+- max-write-burst-bytes: Maximum write burst in bytes that HIDMA can
+ occupy the bus for in a single transaction. A memcpy requested is
+ fragmented to multiples of this amount. This parameter is used while
+ writing into destination memory. Setting this value incorrectly can
+ starve other peripherals in the system.
+- max-read-burst-bytes: Maximum read burst in bytes that HIDMA can
+ occupy the bus for in a single transaction. A memcpy request is
+ fragmented to multiples of this amount. This parameter is used while
+ reading the source memory. Setting this value incorrectly can starve
+ other peripherals in the system.
+- max-write-transactions: This value is how many times a write burst is
+ applied back to back while writing to the destination before yielding
+ the bus.
+- max-read-transactions: This value is how many times a read burst is
+ applied back to back while reading the source before yielding the bus.
+- channel-reset-timeout-cycles: Channel reset timeout in cycles for this SOC.
+ Once a reset is applied to the HW, HW starts a timer for reset operation
+ to confirm. If reset is not completed within this time, HW reports reset
+ failure.
+
+Sub-nodes:
+
+HIDMA has one or more DMA channels that are used to move data from one
+memory location to another.
+
+When the OS is not in control of the management interface (i.e. it's a guest),
+the channel nodes appear on their own, not under a management node.
+
+Required properties:
+- compatible: must contain "qcom,hidma-1.0"
+- reg: Addresses for the transfer and event channel
+- interrupts: Should contain the event interrupt
+- desc-count: Number of asynchronous requests this channel can handle
+- iommus: required a iommu node
+
+Example:
+
+Hypervisor OS configuration:
+
+ hidma-mgmt@f9984000 = {
+ compatible = "qcom,hidma-mgmt-1.0";
+ reg = <0xf9984000 0x15000>;
+ dma-channels = <6>;
+ max-write-burst-bytes = <1024>;
+ max-read-burst-bytes = <1024>;
+ max-write-transactions = <31>;
+ max-read-transactions = <31>;
+ channel-reset-timeout-cycles = <0x500>;
+
+ hidma_24: dma-controller@0x5c050000 {
+ compatible = "qcom,hidma-1.0";
+ reg = <0 0x5c050000 0x0 0x1000>,
+ <0 0x5c0b0000 0x0 0x1000>;
+ interrupts = <0 389 0>;
+ desc-count = <10>;
+ iommus = <&system_mmu>;
+ };
+ };
+
+Guest OS configuration:
+
+ hidma_24: dma-controller@0x5c050000 {
+ compatible = "qcom,hidma-1.0";
+ reg = <0 0x5c050000 0x0 0x1000>,
+ <0 0x5c0b0000 0x0 0x1000>;
+ interrupts = <0 389 0>;
+ desc-count = <10>;
+ iommus = <&system_mmu>;
+ };
diff --git a/Bindings/dma/snps-dma.txt b/Bindings/dma/snps-dma.txt
index c261598164a7..0f5583293c9c 100644
--- a/Bindings/dma/snps-dma.txt
+++ b/Bindings/dma/snps-dma.txt
@@ -13,6 +13,11 @@ Required properties:
- chan_priority: priority of channels. 0 (default): increase from chan 0->n, 1:
increase from chan n->0
- block_size: Maximum block size supported by the controller
+- data-width: Maximum data width supported by hardware per AHB master
+ (in bytes, power of 2)
+
+
+Deprecated properties:
- data_width: Maximum data width supported by hardware per AHB master
(0 - 8bits, 1 - 16bits, ..., 5 - 256bits)
@@ -38,7 +43,7 @@ Example:
chan_allocation_order = <1>;
chan_priority = <1>;
block_size = <0xfff>;
- data_width = <3 3>;
+ data-width = <8 8>;
};
DMA clients connected to the Designware DMA controller must use the format
@@ -47,8 +52,8 @@ The four cells in order are:
1. A phandle pointing to the DMA controller
2. The DMA request line number
-3. Source master for transfers on allocated channel
-4. Destination master for transfers on allocated channel
+3. Memory master for transfers on allocated channel
+4. Peripheral master for transfers on allocated channel
Example:
diff --git a/Bindings/dma/xilinx/xilinx_dma.txt b/Bindings/dma/xilinx/xilinx_dma.txt
index 2291c4098730..3cf0072d3141 100644
--- a/Bindings/dma/xilinx/xilinx_dma.txt
+++ b/Bindings/dma/xilinx/xilinx_dma.txt
@@ -7,7 +7,7 @@ Required properties:
- compatible: Should be "xlnx,axi-dma-1.00.a"
- #dma-cells: Should be <1>, see "dmas" property below
- reg: Should contain DMA registers location and length.
-- dma-channel child node: Should have atleast one channel and can have upto
+- dma-channel child node: Should have at least one channel and can have up to
two channels per device. This node specifies the properties of each
DMA channel (see child node properties below).
diff --git a/Bindings/dma/xilinx/xilinx_vdma.txt b/Bindings/dma/xilinx/xilinx_vdma.txt
index e4c4d47f8137..a1f2683c49bf 100644
--- a/Bindings/dma/xilinx/xilinx_vdma.txt
+++ b/Bindings/dma/xilinx/xilinx_vdma.txt
@@ -3,18 +3,44 @@ It can be configured to have one channel or two channels. If configured
as two channels, one is to transmit to the video device and another is
to receive from the video device.
+Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream
+target devices. It can be configured to have one channel or two channels.
+If configured as two channels, one is to transmit to the device and another
+is to receive from the device.
+
+Xilinx AXI CDMA engine, it does transfers between memory-mapped source
+address and a memory-mapped destination address.
+
Required properties:
-- compatible: Should be "xlnx,axi-vdma-1.00.a"
+- compatible: Should be "xlnx,axi-vdma-1.00.a" or "xlnx,axi-dma-1.00.a" or
+ "xlnx,axi-cdma-1.00.a""
- #dma-cells: Should be <1>, see "dmas" property below
- reg: Should contain VDMA registers location and length.
-- xlnx,num-fstores: Should be the number of framebuffers as configured in h/w.
+- xlnx,addrwidth: Should be the vdma addressing size in bits(ex: 32 bits).
+- dma-ranges: Should be as the following <dma_addr cpu_addr max_len>.
- dma-channel child node: Should have at least one channel and can have up to
two channels per device. This node specifies the properties of each
DMA channel (see child node properties below).
+- clocks: Input clock specifier. Refer to common clock bindings.
+- clock-names: List of input clocks
+ For VDMA:
+ Required elements: "s_axi_lite_aclk"
+ Optional elements: "m_axi_mm2s_aclk" "m_axi_s2mm_aclk",
+ "m_axis_mm2s_aclk", "s_axis_s2mm_aclk"
+ For CDMA:
+ Required elements: "s_axi_lite_aclk", "m_axi_aclk"
+ FOR AXIDMA:
+ Required elements: "s_axi_lite_aclk"
+ Optional elements: "m_axi_mm2s_aclk", "m_axi_s2mm_aclk",
+ "m_axi_sg_aclk"
+
+Required properties for VDMA:
+- xlnx,num-fstores: Should be the number of framebuffers as configured in h/w.
Optional properties:
- xlnx,include-sg: Tells configured for Scatter-mode in
the hardware.
+Optional properties for VDMA:
- xlnx,flush-fsync: Tells which channel to Flush on Frame sync.
It takes following values:
{1}, flush both channels
@@ -31,6 +57,7 @@ Required child node properties:
Optional child node properties:
- xlnx,include-dre: Tells hardware is configured for Data
Realignment Engine.
+Optional child node properties for VDMA:
- xlnx,genlock-mode: Tells Genlock synchronization is
enabled/disabled in hardware.
@@ -41,8 +68,13 @@ axi_vdma_0: axivdma@40030000 {
compatible = "xlnx,axi-vdma-1.00.a";
#dma_cells = <1>;
reg = < 0x40030000 0x10000 >;
+ dma-ranges = <0x00000000 0x00000000 0x40000000>;
xlnx,num-fstores = <0x8>;
xlnx,flush-fsync = <0x1>;
+ xlnx,addrwidth = <0x20>;
+ clocks = <&clk 0>, <&clk 1>, <&clk 2>, <&clk 3>, <&clk 4>;
+ clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk",
+ "m_axis_mm2s_aclk", "s_axis_s2mm_aclk";
dma-channel@40030000 {
compatible = "xlnx,axi-vdma-mm2s-channel";
interrupts = < 0 54 4 >;
diff --git a/Bindings/edac/apm-xgene-edac.txt b/Bindings/edac/apm-xgene-edac.txt
index 78e2a31c58d0..1006b0489464 100644
--- a/Bindings/edac/apm-xgene-edac.txt
+++ b/Bindings/edac/apm-xgene-edac.txt
@@ -16,6 +16,10 @@ Required properties:
- regmap-mcba : Regmap of the MCB-A (memory bridge) resource.
- regmap-mcbb : Regmap of the MCB-B (memory bridge) resource.
- regmap-efuse : Regmap of the PMD efuse resource.
+- regmap-rb : Regmap of the register bus resource. This property
+ is optional only for compatibility. If the RB
+ error conditions are not cleared, it will
+ continuously generate interrupt.
- reg : First resource shall be the CPU bus (PCP) resource.
- interrupts : Interrupt-specifier for MCU, PMD, L3, or SoC error
IRQ(s).
@@ -64,6 +68,11 @@ Example:
reg = <0x0 0x1054a000 0x0 0x20>;
};
+ rb: rb@7e000000 {
+ compatible = "apm,xgene-rb", "syscon";
+ reg = <0x0 0x7e000000 0x0 0x10>;
+ };
+
edac@78800000 {
compatible = "apm,xgene-edac";
#address-cells = <2>;
@@ -73,6 +82,7 @@ Example:
regmap-mcba = <&mcba>;
regmap-mcbb = <&mcbb>;
regmap-efuse = <&efuse>;
+ regmap-rb = <&rb>;
reg = <0x0 0x78800000 0x0 0x100>;
interrupts = <0x0 0x20 0x4>,
<0x0 0x21 0x4>,
diff --git a/Bindings/goldfish/audio.txt b/Bindings/goldfish/audio.txt
new file mode 100644
index 000000000000..d043fda433ba
--- /dev/null
+++ b/Bindings/goldfish/audio.txt
@@ -0,0 +1,17 @@
+Android Goldfish Audio
+
+Android goldfish audio device generated by android emulator.
+
+Required properties:
+
+- compatible : should contain "google,goldfish-audio" to match emulator
+- reg : <registers mapping>
+- interrupts : <interrupt mapping>
+
+Example:
+
+ goldfish_audio@9030000 {
+ compatible = "google,goldfish-audio";
+ reg = <0x9030000 0x100>;
+ interrupts = <0x4>;
+ };
diff --git a/Bindings/goldfish/battery.txt b/Bindings/goldfish/battery.txt
new file mode 100644
index 000000000000..4fb613933214
--- /dev/null
+++ b/Bindings/goldfish/battery.txt
@@ -0,0 +1,17 @@
+Android Goldfish Battery
+
+Android goldfish battery device generated by android emulator.
+
+Required properties:
+
+- compatible : should contain "google,goldfish-battery" to match emulator
+- reg : <registers mapping>
+- interrupts : <interrupt mapping>
+
+Example:
+
+ goldfish_battery@9020000 {
+ compatible = "google,goldfish-battery";
+ reg = <0x9020000 0x1000>;
+ interrupts = <0x3>;
+ };
diff --git a/Bindings/goldfish/events.txt b/Bindings/goldfish/events.txt
new file mode 100644
index 000000000000..5babf46317a4
--- /dev/null
+++ b/Bindings/goldfish/events.txt
@@ -0,0 +1,17 @@
+Android Goldfish Events Keypad
+
+Android goldfish events keypad device generated by android emulator.
+
+Required properties:
+
+- compatible : should contain "google,goldfish-events-keypad" to match emulator
+- reg : <registers mapping>
+- interrupts : <interrupt mapping>
+
+Example:
+
+ goldfish-events@9040000 {
+ compatible = "google,goldfish-events-keypad";
+ reg = <0x9040000 0x1000>;
+ interrupts = <0x5>;
+ };
diff --git a/Bindings/goldfish/pipe.txt b/Bindings/goldfish/pipe.txt
new file mode 100644
index 000000000000..e417a31a1ee3
--- /dev/null
+++ b/Bindings/goldfish/pipe.txt
@@ -0,0 +1,17 @@
+Android Goldfish QEMU Pipe
+
+Andorid pipe virtual device generated by android emulator.
+
+Required properties:
+
+- compatible : should contain "google,android-pipe" to match emulator
+- reg : <registers mapping>
+- interrupts : <interrupt mapping>
+
+Example:
+
+ android_pipe@a010000 {
+ compatible = "google,android-pipe";
+ reg = <ff018000 0x2000>;
+ interrupts = <0x12>;
+ };
diff --git a/Bindings/goldfish/tty.txt b/Bindings/goldfish/tty.txt
new file mode 100644
index 000000000000..82648278da77
--- /dev/null
+++ b/Bindings/goldfish/tty.txt
@@ -0,0 +1,17 @@
+Android Goldfish TTY
+
+Android goldfish tty device generated by android emulator.
+
+Required properties:
+
+- compatible : should contain "google,goldfish-tty" to match emulator
+- reg : <registers mapping>
+- interrupts : <interrupt mapping>
+
+Example:
+
+ goldfish_tty@1f004000 {
+ compatible = "google,goldfish-tty";
+ reg = <0x1f004000 0x1000>;
+ interrupts = <0xc>;
+ };
diff --git a/Bindings/gpio/gpio-74x164.txt b/Bindings/gpio/gpio-74x164.txt
index cc2608021f26..ce1b2231bf5d 100644
--- a/Bindings/gpio/gpio-74x164.txt
+++ b/Bindings/gpio/gpio-74x164.txt
@@ -1,7 +1,9 @@
* Generic 8-bits shift register GPIO driver
Required properties:
-- compatible : Should be "fairchild,74hc595"
+- compatible: Should contain one of the following:
+ "fairchild,74hc595"
+ "nxp,74lvc594"
- reg : chip select number
- gpio-controller : Marks the device node as a gpio controller.
- #gpio-cells : Should be two. The first cell is the pin number and
diff --git a/Bindings/gpio/gpio-altera.txt b/Bindings/gpio/gpio-altera.txt
index 12f50149e1ed..826a7208ca93 100644
--- a/Bindings/gpio/gpio-altera.txt
+++ b/Bindings/gpio/gpio-altera.txt
@@ -12,7 +12,7 @@ Required properties:
- #interrupt-cells : Should be 1. The interrupt type is fixed in the hardware.
- The first cell is the GPIO offset number within the GPIO controller.
- interrupts: Specify the interrupt.
-- altr,interrupt-trigger: Specifies the interrupt trigger type the GPIO
+- altr,interrupt-type: Specifies the interrupt trigger type the GPIO
hardware is synthesized. This field is required if the Altera GPIO controller
used has IRQ enabled as the interrupt type is not software controlled,
but hardware synthesized. Required if GPIO is used as an interrupt
@@ -35,7 +35,7 @@ gpio_altr: gpio@0xff200000 {
reg = <0xff200000 0x10>;
interrupts = <0 45 4>;
altr,ngpio = <32>;
- altr,interrupt-trigger = <IRQ_TYPE_EDGE_RISING>;
+ altr,interrupt-type = <IRQ_TYPE_EDGE_RISING>;
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <1>;
diff --git a/Bindings/gpio/gpio-mcp23s08.txt b/Bindings/gpio/gpio-mcp23s08.txt
index f3332b9a8ed4..c934106b10aa 100644
--- a/Bindings/gpio/gpio-mcp23s08.txt
+++ b/Bindings/gpio/gpio-mcp23s08.txt
@@ -10,6 +10,7 @@ Required properties:
- "microchip,mcp23s08" for 8 GPIO SPI version
- "microchip,mcp23s17" for 16 GPIO SPI version
+ - "microchip,mcp23s18" for 16 GPIO SPI version
- "microchip,mcp23008" for 8 GPIO I2C version or
- "microchip,mcp23017" for 16 GPIO I2C version of the chip
NOTE: Do not use the old mcp prefix any more. It is deprecated and will be
@@ -43,9 +44,6 @@ Optional properties:
- first cell is the pin number
- second cell is used to specify flags.
- interrupt-controller: Marks the device node as a interrupt controller.
-NOTE: The interrupt functionality is only supported for i2c versions of the
-chips. The spi chips can also do the interrupts, but this is not supported by
-the linux driver yet.
Optional device specific properties:
- microchip,irq-mirror: Sets the mirror flag in the IOCON register. Devices
diff --git a/Bindings/gpio/gpio-mpc8xxx.txt b/Bindings/gpio/gpio-mpc8xxx.txt
index 120bc4971cf3..4b6cc632ca5c 100644
--- a/Bindings/gpio/gpio-mpc8xxx.txt
+++ b/Bindings/gpio/gpio-mpc8xxx.txt
@@ -1,9 +1,10 @@
-* Freescale MPC512x/MPC8xxx/Layerscape GPIO controller
+* Freescale MPC512x/MPC8xxx/QorIQ/Layerscape GPIO controller
Required properties:
- compatible : Should be "fsl,<soc>-gpio"
The following <soc>s are known to be supported:
- mpc5121, mpc5125, mpc8349, mpc8572, mpc8610, pq3, qoriq.
+ mpc5121, mpc5125, mpc8349, mpc8572, mpc8610, pq3, qoriq,
+ ls1021a, ls1043a, ls2080a.
- reg : Address and length of the register set for the device
- interrupts : Should be the port interrupt shared by all 32 pins.
- #gpio-cells : Should be two. The first cell is the pin number and
@@ -15,7 +16,7 @@ Optional properties:
- little-endian : GPIO registers are used as little endian. If not
present registers are used as big endian by default.
-Example:
+Example of gpio-controller node for a mpc5125 SoC:
gpio0: gpio@1100 {
compatible = "fsl,mpc5125-gpio";
@@ -24,3 +25,16 @@ gpio0: gpio@1100 {
interrupts = <78 0x8>;
status = "okay";
};
+
+Example of gpio-controller node for a ls2080a SoC:
+
+gpio0: gpio@2300000 {
+ compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
+ reg = <0x0 0x2300000 0x0 0x10000>;
+ interrupts = <0 36 0x4>; /* Level high type */
+ gpio-controller;
+ little-endian;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+};
diff --git a/Bindings/gpio/gpio-pisosr.txt b/Bindings/gpio/gpio-pisosr.txt
new file mode 100644
index 000000000000..414a01cdf715
--- /dev/null
+++ b/Bindings/gpio/gpio-pisosr.txt
@@ -0,0 +1,34 @@
+Generic Parallel-in/Serial-out Shift Register GPIO Driver
+
+This binding describes generic parallel-in/serial-out shift register
+devices that can be used for GPI (General Purpose Input). This includes
+SN74165 serial-out shift registers and the SN65HVS88x series of
+industrial serializers.
+
+Required properties:
+ - compatible : Should be "pisosr-gpio".
+ - gpio-controller : Marks the device node as a GPIO controller.
+ - #gpio-cells : Should be two. For consumer use see gpio.txt.
+
+Optional properties:
+ - ngpios : Number of used GPIO lines (0..n-1), default is 8.
+ - load-gpios : GPIO pin specifier attached to load enable, this
+ pin is pulsed before reading from the device to
+ load input pin values into the the device.
+
+For other required and optional properties of SPI slave
+nodes please refer to ../spi/spi-bus.txt.
+
+Example:
+
+ gpio@0 {
+ compatible = "ti,sn65hvs882", "pisosr-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ load-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
+
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ spi-cpol;
+ };
diff --git a/Bindings/gpio/gpio-ts4800.txt b/Bindings/gpio/gpio-ts4800.txt
new file mode 100644
index 000000000000..92ea9c8f6399
--- /dev/null
+++ b/Bindings/gpio/gpio-ts4800.txt
@@ -0,0 +1,20 @@
+* TS-4800 FPGA's GPIO controller bindings
+
+Required properties:
+- compatible: Must be "technologic,ts4800-gpio".
+- #gpio-cells: Should be two. The first cell is the pin number.
+- reg: Physical base address of the controller and length
+ of memory mapped region.
+
+Optional property:
+- ngpios: See "gpio.txt"
+
+Example:
+
+gpio1: gpio {
+ compatible = "technologic,ts4800-gpio";
+ reg = <0x10020 0x6>;
+ ngpios = <8>;
+ gpio-controller;
+ #gpio-cells = <2>;
+};
diff --git a/Bindings/gpio/gpio-xgene-sb.txt b/Bindings/gpio/gpio-xgene-sb.txt
index dae130060537..5490c1d68981 100644
--- a/Bindings/gpio/gpio-xgene-sb.txt
+++ b/Bindings/gpio/gpio-xgene-sb.txt
@@ -1,10 +1,20 @@
APM X-Gene Standby GPIO controller bindings
-This is a gpio controller in the standby domain.
-
-There are 20 GPIO pins from 0..21. There is no GPIO_DS14 or GPIO_DS15,
-only GPIO_DS8..GPIO_DS13 support interrupts. The IRQ mapping
-is currently 1-to-1 on interrupts 0x28 thru 0x2d.
+This is a gpio controller in the standby domain. It also supports interrupt in
+some particular pins which are sourced to its parent interrupt controller
+as diagram below:
+ +-----------------+
+ | X-Gene standby |
+ | GPIO controller +------ GPIO_0
++------------+ | | ...
+| Parent IRQ | EXT_INT_0 | +------ GPIO_8/EXT_INT_0
+| controller | (SPI40) | | ...
+| (GICv2) +--------------+ +------ GPIO_[N+8]/EXT_INT_N
+| | ... | |
+| | EXT_INT_N | +------ GPIO_[N+9]
+| | (SPI[40 + N])| | ...
+| +--------------+ +------ GPIO_MAX
++------------+ +-----------------+
Required properties:
- compatible: "apm,xgene-gpio-sb" for the X-Gene Standby GPIO controller
@@ -15,10 +25,18 @@ Required properties:
0 = active high
1 = active low
- gpio-controller: Marks the device node as a GPIO controller.
-- interrupts: Shall contain exactly 6 interrupts.
+- interrupts: The EXT_INT_0 parent interrupt resource must be listed first.
+- interrupt-parent: Phandle of the parent interrupt controller.
+- interrupt-cells: Should be two.
+ - first cell is 0-N coresponding for EXT_INT_0 to EXT_INT_N.
+ - second cell is used to specify flags.
+- interrupt-controller: Marks the device node as an interrupt controller.
+- apm,nr-gpios: Optional, specify number of gpios pin.
+- apm,nr-irqs: Optional, specify number of interrupt pins.
+- apm,irq-start: Optional, specify lowest gpio pin support interrupt.
Example:
- sbgpio: sbgpio@17001000 {
+ sbgpio: gpio@17001000{
compatible = "apm,xgene-gpio-sb";
reg = <0x0 0x17001000 0x0 0x400>;
#gpio-cells = <2>;
@@ -29,4 +47,19 @@ Example:
<0x0 0x2b 0x1>,
<0x0 0x2c 0x1>,
<0x0 0x2d 0x1>;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ apm,nr-gpios = <22>;
+ apm,nr-irqs = <6>;
+ apm,irq-start = <8>;
+ };
+
+ testuser {
+ compatible = "example,testuser";
+ /* Use the GPIO_13/EXT_INT_5 line as an active high triggered
+ * level interrupt
+ */
+ interrupts = <5 4>;
+ interrupt-parent = <&sbgpio>;
};
diff --git a/Bindings/gpio/gpio-xlp.txt b/Bindings/gpio/gpio-xlp.txt
index 262ee4ddf2cb..28662d83a43e 100644
--- a/Bindings/gpio/gpio-xlp.txt
+++ b/Bindings/gpio/gpio-xlp.txt
@@ -3,6 +3,8 @@ Netlogic XLP Family GPIO
This GPIO driver is used for following Netlogic XLP SoCs:
XLP832, XLP316, XLP208, XLP980, XLP532
+This GPIO driver is also compatible with GPIO controller found on
+Broadcom Vulcan ARM64.
Required properties:
-------------------
@@ -13,6 +15,7 @@ Required properties:
- "netlogic,xlp208-gpio": For Netlogic XLP208
- "netlogic,xlp980-gpio": For Netlogic XLP980
- "netlogic,xlp532-gpio": For Netlogic XLP532
+ - "brcm,vulcan-gpio": For Broadcom Vulcan ARM64
- reg: Physical base address and length of the controller's registers.
- #gpio-cells: Should be two. The first cell is the pin number and the second
cell is used to specify optional parameters (currently unused).
diff --git a/Bindings/gpio/gpio.txt b/Bindings/gpio/gpio.txt
index 069cdf6f9dac..68d28f62a6f4 100644
--- a/Bindings/gpio/gpio.txt
+++ b/Bindings/gpio/gpio.txt
@@ -131,6 +131,13 @@ Every GPIO controller node must contain both an empty "gpio-controller"
property, and a #gpio-cells integer property, which indicates the number of
cells in a gpio-specifier.
+Some system-on-chips (SoCs) use the concept of GPIO banks. A GPIO bank is an
+instance of a hardware IP core on a silicon die, usually exposed to the
+programmer as a coherent range of I/O addresses. Usually each such bank is
+exposed in the device tree as an individual gpio-controller node, reflecting
+the fact that the hardware was synthesized by reusing the same IP block a
+few times over.
+
Optionally, a GPIO controller may have a "ngpios" property. This property
indicates the number of in-use slots of available slots for GPIOs. The
typical example is something like this: the hardware register is 32 bits
@@ -145,6 +152,21 @@ additional bitmask is needed to specify which GPIOs are actually in use,
and which are dummies. The bindings for this case has not yet been
specified, but should be specified if/when such hardware appears.
+Optionally, a GPIO controller may have a "gpio-line-names" property. This is
+an array of strings defining the names of the GPIO lines going out of the
+GPIO controller. This name should be the most meaningful producer name
+for the system, such as a rail name indicating the usage. Package names
+such as pin name are discouraged: such lines have opaque names (since they
+are by definition generic purpose) and such names are usually not very
+helpful. For example "MMC-CD", "Red LED Vdd" and "ethernet reset" are
+reasonable line names as they describe what the line is used for. "GPIO0"
+is not a good name to give to a GPIO line. Placeholders are discouraged:
+rather use the "" (blank string) if the use of the GPIO line is undefined
+in your design. The names are assigned starting from line offset 0 from
+left to right from the passed array. An incomplete array (where the number
+of passed named are less than ngpios) will still be used up until the last
+provided valid line index.
+
Example:
gpio-controller@00000000 {
@@ -153,6 +175,10 @@ gpio-controller@00000000 {
gpio-controller;
#gpio-cells = <2>;
ngpios = <18>;
+ gpio-line-names = "MMC-CD", "MMC-WP", "VDD eth", "RST eth", "LED R",
+ "LED G", "LED B", "Col A", "Col B", "Col C", "Col D",
+ "Row A", "Row B", "Row C", "Row D", "NMI button",
+ "poweroff", "reset";
}
The GPIO chip may contain GPIO hog definitions. GPIO hogging is a mechanism
diff --git a/Bindings/gpio/ibm,ppc4xx-gpio.txt b/Bindings/gpio/ibm,ppc4xx-gpio.txt
new file mode 100644
index 000000000000..d58b3958f3ea
--- /dev/null
+++ b/Bindings/gpio/ibm,ppc4xx-gpio.txt
@@ -0,0 +1,24 @@
+* IBM/AMCC/APM GPIO Controller for PowerPC 4XX series and compatible SoCs
+
+All GPIOs are pin-shared with other functions. DCRs control whether a
+particular pin that has GPIO capabilities acts as a GPIO or is used for
+another purpose. GPIO outputs are separately programmable to emulate
+an open-drain driver.
+
+Required properties:
+ - compatible: must be "ibm,ppc4xx-gpio"
+ - reg: address and length of the register set for the device
+ - #gpio-cells: must be set to 2. The first cell is the pin number
+ and the second cell is used to specify the gpio polarity:
+ 0 = active high
+ 1 = active low
+ - gpio-controller: marks the device node as a gpio controller.
+
+Example:
+
+GPIO0: gpio@ef600b00 {
+ compatible = "ibm,ppc4xx-gpio";
+ reg = <0xef600b00 0x00000048>;
+ #gpio-cells = <2>;
+ gpio-controller;
+};
diff --git a/Bindings/gpio/microchip,pic32-gpio.txt b/Bindings/gpio/microchip,pic32-gpio.txt
new file mode 100644
index 000000000000..dd031fc93b55
--- /dev/null
+++ b/Bindings/gpio/microchip,pic32-gpio.txt
@@ -0,0 +1,49 @@
+* Microchip PIC32 GPIO devices (PIO).
+
+Required properties:
+ - compatible: "microchip,pic32mzda-gpio"
+ - reg: Base address and length for the device.
+ - interrupts: The port interrupt shared by all pins.
+ - gpio-controller: Marks the port as GPIO controller.
+ - #gpio-cells: Two. The first cell is the pin number and
+ the second cell is used to specify the gpio polarity as defined in
+ defined in <dt-bindings/gpio/gpio.h>:
+ 0 = GPIO_ACTIVE_HIGH
+ 1 = GPIO_ACTIVE_LOW
+ 2 = GPIO_OPEN_DRAIN
+ - interrupt-controller: Marks the device node as an interrupt controller.
+ - #interrupt-cells: Two. The first cell is the GPIO number and second cell
+ is used to specify the trigger type as defined in
+ <dt-bindings/interrupt-controller/irq.h>:
+ IRQ_TYPE_EDGE_RISING
+ IRQ_TYPE_EDGE_FALLING
+ IRQ_TYPE_EDGE_BOTH
+ - clocks: Clock specifier (see clock bindings for details).
+ - microchip,gpio-bank: Specifies which bank a controller owns.
+ - gpio-ranges: Interaction with the PINCTRL subsystem.
+
+Example:
+
+/* PORTA */
+gpio0: gpio0@1f860000 {
+ compatible = "microchip,pic32mzda-gpio";
+ reg = <0x1f860000 0x100>;
+ interrupts = <118 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&rootclk PB4CLK>;
+ microchip,gpio-bank = <0>;
+ gpio-ranges = <&pic32_pinctrl 0 0 16>;
+};
+
+keys {
+ ...
+
+ button@sw1 {
+ label = "ESC";
+ linux,code = <1>;
+ gpios = <&gpio0 12 0>;
+ };
+};
diff --git a/Bindings/gpio/nvidia,tegra186-gpio.txt b/Bindings/gpio/nvidia,tegra186-gpio.txt
new file mode 100644
index 000000000000..c82a2e221bc1
--- /dev/null
+++ b/Bindings/gpio/nvidia,tegra186-gpio.txt
@@ -0,0 +1,161 @@
+NVIDIA Tegra186 GPIO controllers
+
+Tegra186 contains two GPIO controllers; a main controller and an "AON"
+controller. This binding document applies to both controllers. The register
+layouts for the controllers share many similarities, but also some significant
+differences. Hence, this document describes closely related but different
+bindings and compatible values.
+
+The Tegra186 GPIO controller allows software to set the IO direction of, and
+read/write the value of, numerous GPIO signals. Routing of GPIO signals to
+package balls is under the control of a separate pin controller HW block. Two
+major sets of registers exist:
+
+a) Security registers, which allow configuration of allowed access to the GPIO
+register set. These registers exist in a single contiguous block of physical
+address space. The size of this block, and the security features available,
+varies between the different GPIO controllers.
+
+Access to this set of registers is not necessary in all circumstances. Code
+that wishes to configure access to the GPIO registers needs access to these
+registers to do so. Code which simply wishes to read or write GPIO data does not
+need access to these registers.
+
+b) GPIO registers, which allow manipulation of the GPIO signals. In some GPIO
+controllers, these registers are exposed via multiple "physical aliases" in
+address space, each of which access the same underlying state. See the hardware
+documentation for rationale. Any particular GPIO client is expected to access
+just one of these physical aliases.
+
+Tegra HW documentation describes a unified naming convention for all GPIOs
+implemented by the SoC. Each GPIO is assigned to a port, and a port may control
+a number of GPIOs. Thus, each GPIO is named according to an alphabetical port
+name and an integer GPIO name within the port. For example, GPIO_PA0, GPIO_PN6,
+or GPIO_PCC3.
+
+The number of ports implemented by each GPIO controller varies. The number of
+implemented GPIOs within each port varies. GPIO registers within a controller
+are grouped and laid out according to the port they affect.
+
+The mapping from port name to the GPIO controller that implements that port, and
+the mapping from port name to register offset within a controller, are both
+extremely non-linear. The header file <dt-bindings/gpio/tegra186-gpio.h>
+describes the port-level mapping. In that file, the naming convention for ports
+matches the HW documentation. The values chosen for the names are alphabetically
+sorted within a particular controller. Drivers need to map between the DT GPIO
+IDs and HW register offsets using a lookup table.
+
+Each GPIO controller can generate a number of interrupt signals. Each signal
+represents the aggregate status for all GPIOs within a set of ports. Thus, the
+number of interrupt signals generated by a controller varies as a rough function
+of the number of ports it implements. Note that the HW documentation refers to
+both the overall controller HW module and the sets-of-ports as "controllers".
+
+Each GPIO controller in fact generates multiple interrupts signals for each set
+of ports. Each GPIO may be configured to feed into a specific one of the
+interrupt signals generated by a set-of-ports. The intent is for each generated
+signal to be routed to a different CPU, thus allowing different CPUs to each
+handle subsets of the interrupts within a port. The status of each of these
+per-port-set signals is reported via a separate register. Thus, a driver needs
+to know which status register to observe. This binding currently defines no
+configuration mechanism for this. By default, drivers should use register
+GPIO_${port}_INTERRUPT_STATUS_G1_0. Future revisions to the binding could
+define a property to configure this.
+
+Required properties:
+- compatible
+ Array of strings.
+ One of:
+ - "nvidia,tegra186-gpio".
+ - "nvidia,tegra186-gpio-aon".
+- reg-names
+ Array of strings.
+ Contains a list of names for the register spaces described by the reg
+ property. May contain the following entries, in any order:
+ - "gpio": Mandatory. GPIO control registers. This may cover either:
+ a) The single physical alias that this OS should use.
+ b) All physical aliases that exist in the controller. This is
+ appropriate when the OS is responsible for managing assignment of
+ the physical aliases.
+ - "security": Optional. Security configuration registers.
+ Users of this binding MUST look up entries in the reg property by name,
+ using this reg-names property to do so.
+- reg
+ Array of (physical base address, length) tuples.
+ Must contain one entry per entry in the reg-names property, in a matching
+ order.
+- interrupts
+ Array of interrupt specifiers.
+ The interrupt outputs from the HW block, one per set of ports, in the
+ order the HW manual describes them. The number of entries required varies
+ depending on compatible value:
+ - "nvidia,tegra186-gpio": 6 entries.
+ - "nvidia,tegra186-gpio-aon": 1 entry.
+- gpio-controller
+ Boolean.
+ Marks the device node as a GPIO controller/provider.
+- #gpio-cells
+ Single-cell integer.
+ Must be <2>.
+ Indicates how many cells are used in a consumer's GPIO specifier.
+ In the specifier:
+ - The first cell is the pin number.
+ See <dt-bindings/gpio/tegra186-gpio.h>.
+ - The second cell contains flags:
+ - Bit 0 specifies polarity
+ - 0: Active-high (normal).
+ - 1: Active-low (inverted).
+- interrupt-controller
+ Boolean.
+ Marks the device node as an interrupt controller/provider.
+- #interrupt-cells
+ Single-cell integer.
+ Must be <2>.
+ Indicates how many cells are used in a consumer's interrupt specifier.
+ In the specifier:
+ - The first cell is the GPIO number.
+ See <dt-bindings/gpio/tegra186-gpio.h>.
+ - The second cell is contains flags:
+ - Bits [3:0] indicate trigger type and level:
+ - 1: Low-to-high edge triggered.
+ - 2: High-to-low edge triggered.
+ - 4: Active high level-sensitive.
+ - 8: Active low level-sensitive.
+ Valid combinations are 1, 2, 3, 4, 8.
+
+Example:
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+gpio@2200000 {
+ compatible = "nvidia,tegra186-gpio";
+ reg-names = "security", "gpio";
+ reg =
+ <0x0 0x2200000 0x0 0x10000>,
+ <0x0 0x2210000 0x0 0x10000>;
+ interrupts =
+ <0 47 IRQ_TYPE_LEVEL_HIGH>,
+ <0 50 IRQ_TYPE_LEVEL_HIGH>,
+ <0 53 IRQ_TYPE_LEVEL_HIGH>,
+ <0 56 IRQ_TYPE_LEVEL_HIGH>,
+ <0 59 IRQ_TYPE_LEVEL_HIGH>,
+ <0 180 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+};
+
+gpio@c2f0000 {
+ compatible = "nvidia,tegra186-gpio-aon";
+ reg-names = "security", "gpio";
+ reg =
+ <0x0 0xc2f0000 0x0 0x1000>,
+ <0x0 0xc2f1000 0x0 0x1000>;
+ interrupts =
+ <0 60 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+};
diff --git a/Bindings/gpio/wd,mbl-gpio.txt b/Bindings/gpio/wd,mbl-gpio.txt
new file mode 100644
index 000000000000..038c3a6a1f4d
--- /dev/null
+++ b/Bindings/gpio/wd,mbl-gpio.txt
@@ -0,0 +1,38 @@
+Bindings for the Western Digital's MyBook Live memory-mapped GPIO controllers.
+
+The Western Digital MyBook Live has two memory-mapped GPIO controllers.
+Both GPIO controller only have a single 8-bit data register, where GPIO
+state can be read and/or written.
+
+Required properties:
+ - compatible: should be "wd,mbl-gpio"
+ - reg-names: must contain
+ "dat" - data register
+ - reg: address + size pairs describing the GPIO register sets;
+ order must correspond with the order of entries in reg-names
+ - #gpio-cells: must be set to 2. The first cell is the pin number and
+ the second cell is used to specify the gpio polarity:
+ 0 = active high
+ 1 = active low
+ - gpio-controller: Marks the device node as a gpio controller.
+
+Optional properties:
+ - no-output: GPIOs are read-only.
+
+Examples:
+ gpio0: gpio0@e0000000 {
+ compatible = "wd,mbl-gpio";
+ reg-names = "dat";
+ reg = <0xe0000000 0x1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+
+ gpio1: gpio1@e0100000 {
+ compatible = "wd,mbl-gpio";
+ reg-names = "dat";
+ reg = <0xe0100000 0x1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ no-output;
+ };
diff --git a/Bindings/gpu/nvidia,gk20a.txt b/Bindings/gpu/nvidia,gk20a.txt
index 23bfe8e1f7cc..ff3db65e50de 100644
--- a/Bindings/gpu/nvidia,gk20a.txt
+++ b/Bindings/gpu/nvidia,gk20a.txt
@@ -1,9 +1,10 @@
-NVIDIA GK20A Graphics Processing Unit
+NVIDIA Tegra Graphics Processing Units
Required properties:
-- compatible: "nvidia,<chip>-<gpu>"
+- compatible: "nvidia,<gpu>"
Currently recognized values:
- - nvidia,tegra124-gk20a
+ - nvidia,gk20a
+ - nvidia,gm20b
- reg: Physical base address and length of the controller's registers.
Must contain two entries:
- first entry for bar0
@@ -19,14 +20,20 @@ Required properties:
- clock-names: Must include the following entries:
- gpu
- pwr
+If the compatible string is "nvidia,gm20b", then the following clock
+is also required:
+ - ref
- resets: Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names: Must include the following entries:
- gpu
-Example:
+Optional properties:
+- iommus: A reference to the IOMMU. See ../iommu/iommu.txt for details.
- gpu@0,57000000 {
+Example for GK20A:
+
+ gpu@57000000 {
compatible = "nvidia,gk20a";
reg = <0x0 0x57000000 0x0 0x01000000>,
<0x0 0x58000000 0x0 0x01000000>;
@@ -39,5 +46,25 @@ Example:
clock-names = "gpu", "pwr";
resets = <&tegra_car 184>;
reset-names = "gpu";
+ iommus = <&mc TEGRA_SWGROUP_GPU>;
+ status = "disabled";
+ };
+
+Example for GM20B:
+
+ gpu@57000000 {
+ compatible = "nvidia,gm20b";
+ reg = <0x0 0x57000000 0x0 0x01000000>,
+ <0x0 0x58000000 0x0 0x01000000>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "stall", "nonstall";
+ clocks = <&tegra_car TEGRA210_CLK_GPU>,
+ <&tegra_car TEGRA210_CLK_PLL_P_OUT5>,
+ <&tegra_car TEGRA210_CLK_PLL_G_REF>;
+ clock-names = "gpu", "pwr", "ref";
+ resets = <&tegra_car 184>;
+ reset-names = "gpu";
+ iommus = <&mc TEGRA_SWGROUP_GPU>;
status = "disabled";
};
diff --git a/Bindings/hsi/nokia-modem.txt b/Bindings/hsi/nokia-modem.txt
index 8a979780452b..53de1d9d0b95 100644
--- a/Bindings/hsi/nokia-modem.txt
+++ b/Bindings/hsi/nokia-modem.txt
@@ -7,6 +7,8 @@ properties are needed by the Nokia modem HSI client:
Required properties:
- compatible: Should be one of
"nokia,n900-modem"
+ "nokia,n950-modem"
+ "nokia,n9-modem"
- hsi-channel-names: Should contain the following strings
"mcsaab-control"
"speech-control"
@@ -15,11 +17,11 @@ Required properties:
- gpios: Should provide a GPIO handler for each GPIO listed in
gpio-names
- gpio-names: Should contain the following strings
- "cmt_apeslpx"
- "cmt_rst_rq"
- "cmt_en"
- "cmt_rst"
- "cmt_bsi"
+ "cmt_apeslpx" (for n900, n950, n9)
+ "cmt_rst_rq" (for n900, n950, n9)
+ "cmt_en" (for n900, n950, n9)
+ "cmt_rst" (for n900)
+ "cmt_bsi" (for n900)
- interrupts: Should be IRQ handle for modem's reset indication
Example:
diff --git a/Bindings/hwmon/ina2xx.txt b/Bindings/hwmon/ina2xx.txt
index 9bcd5e87830d..02af0d94e921 100644
--- a/Bindings/hwmon/ina2xx.txt
+++ b/Bindings/hwmon/ina2xx.txt
@@ -7,6 +7,7 @@ Required properties:
- "ti,ina220" for ina220
- "ti,ina226" for ina226
- "ti,ina230" for ina230
+ - "ti,ina231" for ina231
- reg: I2C address
Optional properties:
diff --git a/Bindings/hwmon/ltc2978.txt b/Bindings/hwmon/ltc2978.txt
index a7afbf60bb9c..bf2a47bbdc58 100644
--- a/Bindings/hwmon/ltc2978.txt
+++ b/Bindings/hwmon/ltc2978.txt
@@ -13,6 +13,7 @@ Required properties:
* "lltc,ltc3886"
* "lltc,ltc3887"
* "lltc,ltm2987"
+ * "lltc,ltm4675"
* "lltc,ltm4676"
- reg: I2C slave address
diff --git a/Bindings/hwmon/nsa320-mcu.txt b/Bindings/hwmon/nsa320-mcu.txt
new file mode 100644
index 000000000000..0863e067c85b
--- /dev/null
+++ b/Bindings/hwmon/nsa320-mcu.txt
@@ -0,0 +1,20 @@
+Bindings for the fan / temperature monitor microcontroller used on
+the Zyxel NSA 320 and several subsequent models.
+
+Required properties:
+- compatible : "zyxel,nsa320-mcu"
+- data-gpios : The GPIO pin connected to the data line on the MCU
+- clk-gpios : The GPIO pin connected to the clock line on the MCU
+- act-gpios : The GPIO pin connected to the active line on the MCU
+
+Example:
+
+ hwmon {
+ compatible = "zyxel,nsa320-mcu";
+ pinctrl-0 = <&pmx_mcu_data &pmx_mcu_clk &pmx_mcu_act>;
+ pinctrl-names = "default";
+
+ data-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
+ clk-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
+ act-gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
+ };
diff --git a/Bindings/hwmon/ntc_thermistor.txt b/Bindings/hwmon/ntc_thermistor.txt
index a04a80f9cc70..c3b9c4cfe8df 100644
--- a/Bindings/hwmon/ntc_thermistor.txt
+++ b/Bindings/hwmon/ntc_thermistor.txt
@@ -10,6 +10,7 @@ Requires node properties:
"murata,ncp03wb473"
"murata,ncp15wl333"
"murata,ncp03wf104"
+ "murata,ncp15xh103"
/* Usage of vendor name "ntc" is deprecated */
<DEPRECATED> "ntc,ncp15wb473"
diff --git a/Bindings/i2c/i2c-arb-gpio-challenge.txt b/Bindings/i2c/i2c-arb-gpio-challenge.txt
index bfeabb843941..71191ff0e781 100644
--- a/Bindings/i2c/i2c-arb-gpio-challenge.txt
+++ b/Bindings/i2c/i2c-arb-gpio-challenge.txt
@@ -44,8 +44,8 @@ Required properties:
- our-claim-gpio: The GPIO that we use to claim the bus.
- their-claim-gpios: The GPIOs that the other sides use to claim the bus.
Note that some implementations may only support a single other master.
-- Standard I2C mux properties. See mux.txt in this directory.
-- Single I2C child bus node at reg 0. See mux.txt in this directory.
+- Standard I2C mux properties. See i2c-mux.txt in this directory.
+- Single I2C child bus node at reg 0. See i2c-mux.txt in this directory.
Optional properties:
- slew-delay-us: microseconds to wait for a GPIO to go high. Default is 10 us.
diff --git a/Bindings/i2c/i2c-demux-pinctrl.txt b/Bindings/i2c/i2c-demux-pinctrl.txt
new file mode 100644
index 000000000000..7ce23ac61308
--- /dev/null
+++ b/Bindings/i2c/i2c-demux-pinctrl.txt
@@ -0,0 +1,136 @@
+Pinctrl-based I2C Bus DeMux
+
+This binding describes an I2C bus demultiplexer that uses pin multiplexing to
+route the I2C signals, and represents the pin multiplexing configuration using
+the pinctrl device tree bindings. This may be used to select one I2C IP core at
+runtime which may have a better feature set for a given task than another I2C
+IP core on the SoC. The most simple example is to fall back to GPIO bitbanging
+if your current runtime configuration hits an errata of the internal IP core.
+
+ +-------------------------------+
+ | SoC |
+ | | +-----+ +-----+
+ | +------------+ | | dev | | dev |
+ | |I2C IP Core1|--\ | +-----+ +-----+
+ | +------------+ \-------+ | | |
+ | |Pinctrl|--|------+--------+
+ | +------------+ +-------+ |
+ | |I2C IP Core2|--/ |
+ | +------------+ |
+ | |
+ +-------------------------------+
+
+Required properties:
+- compatible: "i2c-demux-pinctrl"
+- i2c-parent: List of phandles of I2C masters available for selection. The first
+ one will be used as default.
+- i2c-bus-name: The name of this bus. Also needed as pinctrl-name for the I2C
+ parents.
+
+Furthermore, I2C mux properties and child nodes. See i2c-mux.txt in this
+directory.
+
+Example:
+
+Here is a snipplet for a bus to be demuxed. It contains various i2c clients for
+HDMI, so the bus is named "i2c-hdmi":
+
+ i2chdmi: i2c@8 {
+
+ compatible = "i2c-demux-pinctrl";
+ i2c-parent = <&gpioi2c>, <&iic2>, <&i2c2>;
+ i2c-bus-name = "i2c-hdmi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ak4643: sound-codec@12 {
+ compatible = "asahi-kasei,ak4643";
+
+ #sound-dai-cells = <0>;
+ reg = <0x12>;
+ };
+
+ composite-in@20 {
+ compatible = "adi,adv7180";
+ reg = <0x20>;
+ remote = <&vin1>;
+
+ port {
+ adv7180: endpoint {
+ bus-width = <8>;
+ remote-endpoint = <&vin1ep0>;
+ };
+ };
+ };
+
+ hdmi@39 {
+ compatible = "adi,adv7511w";
+ reg = <0x39>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
+
+ adi,input-depth = <8>;
+ adi,input-colorspace = "rgb";
+ adi,input-clock = "1x";
+ adi,input-style = <1>;
+ adi,input-justification = "evenly";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7511_in: endpoint {
+ remote-endpoint = <&du_out_lvds0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ adv7511_out: endpoint {
+ remote-endpoint = <&hdmi_con>;
+ };
+ };
+ };
+ };
+ };
+
+And for clarification, here are the snipplets for the i2c-parents:
+
+ gpioi2c: i2c@9 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "i2c-gpio";
+ status = "disabled";
+ gpios = <&gpio5 6 GPIO_ACTIVE_HIGH /* sda */
+ &gpio5 5 GPIO_ACTIVE_HIGH /* scl */
+ >;
+ i2c-gpio,delay-us = <5>;
+ };
+
+...
+
+&i2c2 {
+ pinctrl-0 = <&i2c2_pins>;
+ pinctrl-names = "i2c-hdmi";
+
+ clock-frequency = <100000>;
+};
+
+...
+
+&iic2 {
+ pinctrl-0 = <&iic2_pins>;
+ pinctrl-names = "i2c-hdmi";
+
+ clock-frequency = <100000>;
+};
+
+Please note:
+
+- pinctrl properties for the parent I2C controllers need a pinctrl state
+ with the same name as i2c-bus-name, not "default"!
+
+- the i2c masters must have their status "disabled". This driver will
+ enable them at runtime when needed.
diff --git a/Bindings/i2c/i2c-imx.txt b/Bindings/i2c/i2c-imx.txt
index eab5836ba7f9..b967544590e8 100644
--- a/Bindings/i2c/i2c-imx.txt
+++ b/Bindings/i2c/i2c-imx.txt
@@ -11,7 +11,7 @@ Required properties:
Optional properties:
- clock-frequency : Constains desired I2C/HS-I2C bus clock frequency in Hz.
- The absence of the propoerty indicates the default frequency 100 kHz.
+ The absence of the property indicates the default frequency 100 kHz.
- dmas: A list of two dma specifiers, one for each entry in dma-names.
- dma-names: should contain "tx" and "rx".
- scl-gpios: specify the gpio related to SCL pin
diff --git a/Bindings/i2c/i2c-mux-gpio.txt b/Bindings/i2c/i2c-mux-gpio.txt
index 66709a825541..21da3ecbb370 100644
--- a/Bindings/i2c/i2c-mux-gpio.txt
+++ b/Bindings/i2c/i2c-mux-gpio.txt
@@ -22,8 +22,8 @@ Required properties:
- i2c-parent: The phandle of the I2C bus that this multiplexer's master-side
port is connected to.
- mux-gpios: list of gpios used to control the muxer
-* Standard I2C mux properties. See mux.txt in this directory.
-* I2C child bus nodes. See mux.txt in this directory.
+* Standard I2C mux properties. See i2c-mux.txt in this directory.
+* I2C child bus nodes. See i2c-mux.txt in this directory.
Optional properties:
- idle-state: value to set the muxer to when idle. When no value is
@@ -33,7 +33,7 @@ For each i2c child node, an I2C child bus will be created. They will
be numbered based on their order in the device tree.
Whenever an access is made to a device on a child bus, the value set
-in the revelant node's reg property will be output using the list of
+in the relevant node's reg property will be output using the list of
GPIOs, the first in the list holding the least-significant value.
If an idle state is defined, using the idle-state (optional) property,
diff --git a/Bindings/i2c/i2c-mux-pinctrl.txt b/Bindings/i2c/i2c-mux-pinctrl.txt
index ae8af1694e95..33119a98e144 100644
--- a/Bindings/i2c/i2c-mux-pinctrl.txt
+++ b/Bindings/i2c/i2c-mux-pinctrl.txt
@@ -28,9 +28,9 @@ Also required are:
* Standard pinctrl properties that specify the pin mux state for each child
bus. See ../pinctrl/pinctrl-bindings.txt.
-* Standard I2C mux properties. See mux.txt in this directory.
+* Standard I2C mux properties. See i2c-mux.txt in this directory.
-* I2C child bus nodes. See mux.txt in this directory.
+* I2C child bus nodes. See i2c-mux.txt in this directory.
For each named state defined in the pinctrl-names property, an I2C child bus
will be created. I2C child bus numbers are assigned based on the index into
diff --git a/Bindings/i2c/i2c-mux-reg.txt b/Bindings/i2c/i2c-mux-reg.txt
index 688783fbe696..de00d7fc450b 100644
--- a/Bindings/i2c/i2c-mux-reg.txt
+++ b/Bindings/i2c/i2c-mux-reg.txt
@@ -7,8 +7,8 @@ Required properties:
- compatible: i2c-mux-reg
- i2c-parent: The phandle of the I2C bus that this multiplexer's master-side
port is connected to.
-* Standard I2C mux properties. See mux.txt in this directory.
-* I2C child bus nodes. See mux.txt in this directory.
+* Standard I2C mux properties. See i2c-mux.txt in this directory.
+* I2C child bus nodes. See i2c-mux.txt in this directory.
Optional properties:
- reg: this pair of <offset size> specifies the register to control the mux.
@@ -24,7 +24,7 @@ Optional properties:
given, it defaults to the last value used.
Whenever an access is made to a device on a child bus, the value set
-in the revelant node's reg property will be output to the register.
+in the relevant node's reg property will be output to the register.
If an idle state is defined, using the idle-state (optional) property,
whenever an access is not being made to a device on a child bus, the
diff --git a/Bindings/i2c/i2c-octeon.txt b/Bindings/i2c/i2c-octeon.txt
index dced82ebe31d..872d485dffab 100644
--- a/Bindings/i2c/i2c-octeon.txt
+++ b/Bindings/i2c/i2c-octeon.txt
@@ -4,6 +4,12 @@
Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.
+ or
+
+ compatible: "cavium,octeon-7890-twsi"
+
+ Compatibility with cn78XX SOCs.
+
- reg: The base address of the TWSI/I2C bus controller register bank.
- #address-cells: Must be <1>.
diff --git a/Bindings/i2c/i2c-rcar.txt b/Bindings/i2c/i2c-rcar.txt
index 95e97223a71c..5f0cb502b1db 100644
--- a/Bindings/i2c/i2c-rcar.txt
+++ b/Bindings/i2c/i2c-rcar.txt
@@ -17,8 +17,11 @@ Required properties:
Optional properties:
- clock-frequency: desired I2C bus clock frequency in Hz. The absence of this
- propoerty indicates the default frequency 100 kHz.
+ property indicates the default frequency 100 kHz.
- clocks: clock specifier.
+- dmas: Must contain a list of two references to DMA specifiers, one for
+ transmission, and one for reception.
+- dma-names: Must contain a list of two DMA names, "tx" and "rx".
- i2c-scl-falling-time-ns: see i2c.txt
- i2c-scl-internal-delay-ns: see i2c.txt
diff --git a/Bindings/i2c/i2c-rk3x.txt b/Bindings/i2c/i2c-rk3x.txt
index f0d71bc52e64..0b4a85fe2d86 100644
--- a/Bindings/i2c/i2c-rk3x.txt
+++ b/Bindings/i2c/i2c-rk3x.txt
@@ -6,8 +6,8 @@ RK3xxx SoCs.
Required properties :
- reg : Offset and length of the register set for the device
- - compatible : should be "rockchip,rk3066-i2c", "rockchip,rk3188-i2c" or
- "rockchip,rk3288-i2c".
+ - compatible : should be "rockchip,rk3066-i2c", "rockchip,rk3188-i2c",
+ "rockchip,rk3228-i2c" or "rockchip,rk3288-i2c".
- interrupts : interrupt number
- clocks : parent clock
diff --git a/Bindings/i2c/i2c-sirf.txt b/Bindings/i2c/i2c-sirf.txt
index 7baf9e133fa8..2701eefb00f7 100644
--- a/Bindings/i2c/i2c-sirf.txt
+++ b/Bindings/i2c/i2c-sirf.txt
@@ -8,7 +8,7 @@ Required properties :
Optional properties:
- clock-frequency : Constains desired I2C/HS-I2C bus clock frequency in Hz.
- The absence of the propoerty indicates the default frequency 100 kHz.
+ The absence of the property indicates the default frequency 100 kHz.
Examples :
diff --git a/Bindings/i2c/i2c-xiic.txt b/Bindings/i2c/i2c-xiic.txt
index ceabbe91ae44..caf42e989462 100644
--- a/Bindings/i2c/i2c-xiic.txt
+++ b/Bindings/i2c/i2c-xiic.txt
@@ -6,14 +6,17 @@ Required properties:
- interrupts : IIC controller unterrupt
- #address-cells = <1>
- #size-cells = <0>
+- clocks: Input clock specifier. Refer to common clock bindings.
Optional properties:
- Child nodes conforming to i2c bus binding
+- clock-names: Input clock name, should be 'pclk'.
Example:
axi_iic_0: i2c@40800000 {
compatible = "xlnx,xps-iic-2.00.a";
+ clocks = <&clkc 15>;
interrupts = < 1 2 >;
reg = < 0x40800000 0x10000 >;
diff --git a/Bindings/iio/accel/mma8452.txt b/Bindings/iio/accel/mma8452.txt
index 3c10e8581144..45f5c5c5929c 100644
--- a/Bindings/iio/accel/mma8452.txt
+++ b/Bindings/iio/accel/mma8452.txt
@@ -1,12 +1,15 @@
-Freescale MMA8452Q, MMA8453Q, MMA8652FC or MMA8653FC triaxial accelerometer
+Freescale MMA8451Q, MMA8452Q, MMA8453Q, MMA8652FC, MMA8653FC or FXLS8471Q
+triaxial accelerometer
Required properties:
- compatible: should contain one of
+ * "fsl,mma8451"
* "fsl,mma8452"
* "fsl,mma8453"
* "fsl,mma8652"
* "fsl,mma8653"
+ * "fsl,fxls8471"
- reg: the I2C address of the chip
diff --git a/Bindings/iio/adc/at91-sama5d2_adc.txt b/Bindings/iio/adc/at91-sama5d2_adc.txt
new file mode 100644
index 000000000000..3223684a643b
--- /dev/null
+++ b/Bindings/iio/adc/at91-sama5d2_adc.txt
@@ -0,0 +1,28 @@
+* AT91 SAMA5D2 Analog to Digital Converter (ADC)
+
+Required properties:
+ - compatible: Should be "atmel,sama5d2-adc".
+ - reg: Should contain ADC registers location and length.
+ - interrupts: Should contain the IRQ line for the ADC.
+ - clocks: phandle to device clock.
+ - clock-names: Must be "adc_clk".
+ - vref-supply: Supply used as reference for conversions.
+ - vddana-supply: Supply for the adc device.
+ - atmel,min-sample-rate-hz: Minimum sampling rate, it depends on SoC.
+ - atmel,max-sample-rate-hz: Maximum sampling rate, it depends on SoC.
+ - atmel,startup-time-ms: Startup time expressed in ms, it depends on SoC.
+
+Example:
+
+adc: adc@fc030000 {
+ compatible = "atmel,sama5d2-adc";
+ reg = <0xfc030000 0x100>;
+ interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&adc_clk>;
+ clock-names = "adc_clk";
+ atmel,min-sample-rate-hz = <200000>;
+ atmel,max-sample-rate-hz = <20000000>;
+ atmel,startup-time-ms = <4>;
+ vddana-supply = <&vdd_3v3_lp_reg>;
+ vref-supply = <&vdd_3v3_lp_reg>;
+}
diff --git a/Bindings/iio/adc/fsl,imx25-gcq.txt b/Bindings/iio/adc/fsl,imx25-gcq.txt
new file mode 100644
index 000000000000..b0866d36a307
--- /dev/null
+++ b/Bindings/iio/adc/fsl,imx25-gcq.txt
@@ -0,0 +1,58 @@
+Freescale i.MX25 ADC GCQ device
+
+This is a generic conversion queue device that can convert any of the
+analog inputs using the ADC unit of the i.MX25.
+
+Required properties:
+ - compatible: Should be "fsl,imx25-gcq".
+ - reg: Should be the register range of the module.
+ - interrupts: Should be the interrupt number of the module.
+ Typically this is <1>.
+ - interrupt-parent: phandle to the tsadc module of the i.MX25.
+ - #address-cells: Should be <1> (setting for the subnodes)
+ - #size-cells: Should be <0> (setting for the subnodes)
+
+Optional properties:
+ - vref-ext-supply: The regulator supplying the ADC reference voltage.
+ Required when at least one subnode uses the this reference.
+ - vref-xp-supply: The regulator supplying the ADC reference voltage on pin XP.
+ Required when at least one subnode uses this reference.
+ - vref-yp-supply: The regulator supplying the ADC reference voltage on pin YP.
+ Required when at least one subnode uses this reference.
+
+Sub-nodes:
+Optionally you can define subnodes which define the reference voltage
+for the analog inputs.
+
+Required properties for subnodes:
+ - reg: Should be the number of the analog input.
+ 0: xp
+ 1: yp
+ 2: xn
+ 3: yn
+ 4: wiper
+ 5: inaux0
+ 6: inaux1
+ 7: inaux2
+Optional properties for subnodes:
+ - fsl,adc-refp: specifies the positive reference input as defined in
+ <dt-bindings/iio/adc/fsl-imx25-gcq.h>
+ - fsl,adc-refn: specifies the negative reference input as defined in
+ <dt-bindings/iio/adc/fsl-imx25-gcq.h>
+
+Example:
+
+ adc: adc@50030800 {
+ compatible = "fsl,imx25-gcq";
+ reg = <0x50030800 0x60>;
+ interrupt-parent = <&tscadc>;
+ interrupts = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ inaux@5 {
+ reg = <5>;
+ fsl,adc-refp = <MX25_ADC_REFP_INT>;
+ fsl,adc-refn = <MX25_ADC_REFN_NGND>;
+ };
+ };
diff --git a/Bindings/iio/adc/lpc1850-adc.txt b/Bindings/iio/adc/lpc1850-adc.txt
new file mode 100644
index 000000000000..0bcae5140bc5
--- /dev/null
+++ b/Bindings/iio/adc/lpc1850-adc.txt
@@ -0,0 +1,21 @@
+NXP LPC1850 ADC bindings
+
+Required properties:
+- compatible: Should be "nxp,lpc1850-adc"
+- reg: Offset and length of the register set for the ADC device
+- interrupts: The interrupt number for the ADC device
+- clocks: The root clock of the ADC controller
+- vref-supply: The regulator supply ADC reference voltage
+- resets: phandle to reset controller and line specifier
+
+Example:
+
+adc0: adc@400e3000 {
+ compatible = "nxp,lpc1850-adc";
+ reg = <0x400e3000 0x1000>;
+ interrupts = <17>;
+ clocks = <&ccu1 CLK_APB3_ADC0>;
+ vref-supply = <&reg_vdda>;
+ resets = <&rgu 40>;
+ status = "disabled";
+};
diff --git a/Bindings/iio/adc/mcp3422.txt b/Bindings/iio/adc/mcp3422.txt
index dcae4ccfcc52..82bcce07255d 100644
--- a/Bindings/iio/adc/mcp3422.txt
+++ b/Bindings/iio/adc/mcp3422.txt
@@ -6,6 +6,7 @@ Required properties:
"microchip,mcp3422" or
"microchip,mcp3423" or
"microchip,mcp3424" or
+ "microchip,mcp3425" or
"microchip,mcp3426" or
"microchip,mcp3427" or
"microchip,mcp3428"
diff --git a/Bindings/staging/iio/adc/mxs-lradc.txt b/Bindings/iio/adc/mxs-lradc.txt
index 555fb117d4fa..555fb117d4fa 100644
--- a/Bindings/staging/iio/adc/mxs-lradc.txt
+++ b/Bindings/iio/adc/mxs-lradc.txt
diff --git a/Bindings/iio/adc/rockchip-saradc.txt b/Bindings/iio/adc/rockchip-saradc.txt
index a9a5fe19ff2a..bf99e2f24788 100644
--- a/Bindings/iio/adc/rockchip-saradc.txt
+++ b/Bindings/iio/adc/rockchip-saradc.txt
@@ -1,7 +1,11 @@
Rockchip Successive Approximation Register (SAR) A/D Converter bindings
Required properties:
-- compatible: Should be "rockchip,saradc" or "rockchip,rk3066-tsadc"
+- compatible: should be "rockchip,<name>-saradc" or "rockchip,rk3066-tsadc"
+ - "rockchip,saradc": for rk3188, rk3288
+ - "rockchip,rk3066-tsadc": for rk3036
+ - "rockchip,rk3399-saradc": for rk3399
+
- reg: physical base address of the controller and length of memory mapped
region.
- interrupts: The interrupt number to the cpu. The interrupt specifier format
diff --git a/Bindings/iio/adc/ti-adc0832.txt b/Bindings/iio/adc/ti-adc0832.txt
new file mode 100644
index 000000000000..d91130587d01
--- /dev/null
+++ b/Bindings/iio/adc/ti-adc0832.txt
@@ -0,0 +1,19 @@
+* Texas Instruments' ADC0831/ADC0832/ADC0832/ADC0838
+
+Required properties:
+ - compatible: Should be one of
+ * "ti,adc0831"
+ * "ti,adc0832"
+ * "ti,adc0834"
+ * "ti,adc0838"
+ - reg: spi chip select number for the device
+ - vref-supply: The regulator supply for ADC reference voltage
+ - spi-max-frequency: Max SPI frequency to use (< 400000)
+
+Example:
+adc@0 {
+ compatible = "ti,adc0832";
+ reg = <0>;
+ vref-supply = <&vdd_supply>;
+ spi-max-frequency = <200000>;
+};
diff --git a/Bindings/iio/chemical/atlas,ph-sm.txt b/Bindings/iio/chemical/atlas,ph-sm.txt
new file mode 100644
index 000000000000..cffa1907463a
--- /dev/null
+++ b/Bindings/iio/chemical/atlas,ph-sm.txt
@@ -0,0 +1,22 @@
+* Atlas Scientific pH-SM OEM sensor
+
+http://www.atlas-scientific.com/_files/_datasheets/_oem/pH_oem_datasheet.pdf
+
+Required properties:
+
+ - compatible: must be "atlas,ph-sm"
+ - reg: the I2C address of the sensor
+ - interrupt-parent: should be the phandle for the interrupt controller
+ - interrupts: the sole interrupt generated by the device
+
+ Refer to interrupt-controller/interrupts.txt for generic interrupt client
+ node bindings.
+
+Example:
+
+atlas@65 {
+ compatible = "atlas,ph-sm";
+ reg = <0x65>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <16 2>;
+};
diff --git a/Bindings/iio/dac/ad5592r.txt b/Bindings/iio/dac/ad5592r.txt
new file mode 100644
index 000000000000..989f96f31c66
--- /dev/null
+++ b/Bindings/iio/dac/ad5592r.txt
@@ -0,0 +1,155 @@
+Analog Devices AD5592R/AD5593R DAC/ADC device driver
+
+Required properties for the AD5592R:
+ - compatible: Must be "adi,ad5592r"
+ - reg: SPI chip select number for the device
+ - spi-max-frequency: Max SPI frequency to use (< 30000000)
+ - spi-cpol: The AD5592R requires inverse clock polarity (CPOL) mode
+
+Required properties for the AD5593R:
+ - compatible: Must be "adi,ad5593r"
+ - reg: I2C address of the device
+
+Required properties for all supported chips:
+ - #address-cells: Should be 1.
+ - #size-cells: Should be 0.
+ - channel nodes:
+ Each child node represents one channel and has the following
+ Required properties:
+ * reg: Pin on which this channel is connected to.
+ * adi,mode: Mode or function of this channel.
+ Macros specifying the valid values
+ can be found in <dt-bindings/iio/adi,ad5592r.h>.
+
+ The following values are currently supported:
+ * CH_MODE_UNUSED (the pin is unused)
+ * CH_MODE_ADC (the pin is ADC input)
+ * CH_MODE_DAC (the pin is DAC output)
+ * CH_MODE_DAC_AND_ADC (the pin is DAC output
+ but can be monitored by an ADC, since
+ there is no disadvantage this
+ this should be considered as the
+ preferred DAC mode)
+ * CH_MODE_GPIO (the pin is registered
+ with GPIOLIB)
+ Optional properties:
+ * adi,off-state: State of this channel when unused or the
+ device gets removed. Macros specifying the
+ valid values can be found in
+ <dt-bindings/iio/adi,ad5592r.h>.
+
+ * CH_OFFSTATE_PULLDOWN (the pin is pulled down)
+ * CH_OFFSTATE_OUT_LOW (the pin is output low)
+ * CH_OFFSTATE_OUT_HIGH (the pin is output high)
+ * CH_OFFSTATE_OUT_TRISTATE (the pin is
+ tristated output)
+
+
+Optional properties:
+ - vref-supply: Phandle to the external reference voltage supply. This should
+ only be set if there is an external reference voltage connected to the VREF
+ pin. If the property is not set the internal 2.5V reference is used.
+ - reset-gpios : GPIO spec for the RESET pin. If specified, it will be
+ asserted during driver probe.
+ - gpio-controller: Marks the device node as a GPIO controller.
+ - #gpio-cells: Should be 2. The first cell is the GPIO number and the second
+ cell specifies GPIO flags, as defined in <dt-bindings/gpio/gpio.h>.
+
+AD5592R Example:
+
+ #include <dt-bindings/iio/adi,ad5592r.h>
+
+ vref: regulator-vref {
+ compatible = "regulator-fixed";
+ regulator-name = "vref-ad559x";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ ad5592r@0 {
+ #size-cells = <0>;
+ #address-cells = <1>;
+ #gpio-cells = <2>;
+ compatible = "adi,ad5592r";
+ reg = <0>;
+
+ spi-max-frequency = <1000000>;
+ spi-cpol;
+
+ vref-supply = <&vref>; /* optional */
+ reset-gpios = <&gpio0 86 0>; /* optional */
+ gpio-controller;
+
+ channel@0 {
+ reg = <0>;
+ adi,mode = <CH_MODE_DAC>;
+ };
+ channel@1 {
+ reg = <1>;
+ adi,mode = <CH_MODE_ADC>;
+ };
+ channel@2 {
+ reg = <2>;
+ adi,mode = <CH_MODE_DAC_AND_ADC>;
+ };
+ channel@3 {
+ reg = <3>;
+ adi,mode = <CH_MODE_DAC_AND_ADC>;
+ adi,off-state = <CH_OFFSTATE_PULLDOWN>;
+ };
+ channel@4 {
+ reg = <4>;
+ adi,mode = <CH_MODE_UNUSED>;
+ adi,off-state = <CH_OFFSTATE_PULLDOWN>;
+ };
+ channel@5 {
+ reg = <5>;
+ adi,mode = <CH_MODE_GPIO>;
+ adi,off-state = <CH_OFFSTATE_PULLDOWN>;
+ };
+ channel@6 {
+ reg = <6>;
+ adi,mode = <CH_MODE_GPIO>;
+ adi,off-state = <CH_OFFSTATE_PULLDOWN>;
+ };
+ channel@7 {
+ reg = <7>;
+ adi,mode = <CH_MODE_GPIO>;
+ adi,off-state = <CH_OFFSTATE_PULLDOWN>;
+ };
+ };
+
+AD5593R Example:
+
+ #include <dt-bindings/iio/adi,ad5592r.h>
+
+ ad5593r@10 {
+ #size-cells = <0>;
+ #address-cells = <1>;
+ #gpio-cells = <2>;
+ compatible = "adi,ad5593r";
+ reg = <0x10>;
+ gpio-controller;
+
+ channel@0 {
+ reg = <0>;
+ adi,mode = <CH_MODE_DAC>;
+ adi,off-state = <CH_OFFSTATE_PULLDOWN>;
+ };
+ channel@1 {
+ reg = <1>;
+ adi,mode = <CH_MODE_ADC>;
+ adi,off-state = <CH_OFFSTATE_PULLDOWN>;
+ };
+ channel@2 {
+ reg = <2>;
+ adi,mode = <CH_MODE_DAC_AND_ADC>;
+ adi,off-state = <CH_OFFSTATE_PULLDOWN>;
+ };
+ channel@6 {
+ reg = <6>;
+ adi,mode = <CH_MODE_GPIO>;
+ adi,off-state = <CH_OFFSTATE_PULLDOWN>;
+ };
+ };
diff --git a/Bindings/iio/dac/lpc1850-dac.txt b/Bindings/iio/dac/lpc1850-dac.txt
new file mode 100644
index 000000000000..7d6647d4af5e
--- /dev/null
+++ b/Bindings/iio/dac/lpc1850-dac.txt
@@ -0,0 +1,20 @@
+NXP LPC1850 DAC bindings
+
+Required properties:
+- compatible: Should be "nxp,lpc1850-dac"
+- reg: Offset and length of the register set for the ADC device
+- interrupts: The interrupt number for the ADC device
+- clocks: The root clock of the ADC controller
+- vref-supply: The regulator supply ADC reference voltage
+- resets: phandle to reset controller and line specifier
+
+Example:
+dac: dac@400e1000 {
+ compatible = "nxp,lpc1850-dac";
+ reg = <0x400e1000 0x1000>;
+ interrupts = <0>;
+ clocks = <&ccu1 CLK_APB3_DAC>;
+ vref-supply = <&reg_vdda>;
+ resets = <&rgu 42>;
+ status = "disabled";
+};
diff --git a/Bindings/iio/dac/vf610-dac.txt b/Bindings/iio/dac/vf610-dac.txt
new file mode 100644
index 000000000000..20c6c7ae9687
--- /dev/null
+++ b/Bindings/iio/dac/vf610-dac.txt
@@ -0,0 +1,20 @@
+Freescale vf610 Digital to Analog Converter bindings
+
+The devicetree bindings are for the new DAC driver written for
+vf610 SoCs from Freescale.
+
+Required properties:
+- compatible: Should contain "fsl,vf610-dac"
+- reg: Offset and length of the register set for the device
+- interrupts: Should contain the interrupt for the device
+- clocks: The clock is needed by the DAC controller
+- clock-names: Must contain "dac" matching entry in the clocks property.
+
+Example:
+dac0: dac@400cc000 {
+ compatible = "fsl,vf610-dac";
+ reg = <0x400cc000 0x1000>;
+ interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "dac";
+ clocks = <&clks VF610_CLK_DAC0>;
+};
diff --git a/Bindings/iio/health/afe4403.txt b/Bindings/iio/health/afe4403.txt
new file mode 100644
index 000000000000..2fffd70336ba
--- /dev/null
+++ b/Bindings/iio/health/afe4403.txt
@@ -0,0 +1,34 @@
+Texas Instruments AFE4403 Heart rate and Pulse Oximeter
+
+Required properties:
+ - compatible : Should be "ti,afe4403".
+ - reg : SPI chip select address of device.
+ - tx-supply : Regulator supply to transmitting LEDs.
+ - interrupt-parent : Phandle to he parent interrupt controller.
+ - interrupts : The interrupt line the device ADC_RDY pin is
+ connected to. For details refer to,
+ ../../interrupt-controller/interrupts.txt.
+
+Optional properties:
+ - reset-gpios : GPIO used to reset the device.
+ For details refer to, ../../gpio/gpio.txt.
+
+For other required and optional properties of SPI slave nodes
+please refer to ../../spi/spi-bus.txt.
+
+Example:
+
+&spi0 {
+ heart_mon@0 {
+ compatible = "ti,afe4403";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+
+ tx-supply = <&vbat>;
+
+ interrupt-parent = <&gpio1>;
+ interrupts = <28 IRQ_TYPE_EDGE_RISING>;
+
+ reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
+ };
+};
diff --git a/Bindings/iio/health/afe4404.txt b/Bindings/iio/health/afe4404.txt
new file mode 100644
index 000000000000..de69f203edfa
--- /dev/null
+++ b/Bindings/iio/health/afe4404.txt
@@ -0,0 +1,30 @@
+Texas Instruments AFE4404 Heart rate and Pulse Oximeter
+
+Required properties:
+ - compatible : Should be "ti,afe4404".
+ - reg : I2C address of the device.
+ - tx-supply : Regulator supply to transmitting LEDs.
+ - interrupt-parent : Phandle to he parent interrupt controller.
+ - interrupts : The interrupt line the device ADC_RDY pin is
+ connected to. For details refer to,
+ ../interrupt-controller/interrupts.txt.
+
+Optional properties:
+ - reset-gpios : GPIO used to reset the device.
+ For details refer to, ../gpio/gpio.txt.
+
+Example:
+
+&i2c2 {
+ heart_mon@58 {
+ compatible = "ti,afe4404";
+ reg = <0x58>;
+
+ tx-supply = <&vbat>;
+
+ interrupt-parent = <&gpio1>;
+ interrupts = <28 IRQ_TYPE_EDGE_RISING>;
+
+ reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
+ };
+};
diff --git a/Bindings/iio/health/max30100.txt b/Bindings/iio/health/max30100.txt
index f6fbac66ad06..295a9edfa4fd 100644
--- a/Bindings/iio/health/max30100.txt
+++ b/Bindings/iio/health/max30100.txt
@@ -11,11 +11,19 @@ Required properties:
Refer to interrupt-controller/interrupts.txt for generic
interrupt client node bindings.
+Optional properties:
+ - maxim,led-current-microamp: configuration for LED current in microamperes
+ while the engine is running. First indexed value is the configuration for
+ the RED LED, and second value is for the IR LED.
+
+ Refer to the datasheet for the allowed current values.
+
Example:
max30100@057 {
compatible = "maxim,max30100";
reg = <57>;
+ maxim,led-current-microamp = <24000 50000>;
interrupt-parent = <&gpio1>;
interrupts = <16 2>;
};
diff --git a/Bindings/iio/iio-bindings.txt b/Bindings/iio/iio-bindings.txt
index 0b447d9ad196..68d6f8ce063b 100644
--- a/Bindings/iio/iio-bindings.txt
+++ b/Bindings/iio/iio-bindings.txt
@@ -82,7 +82,7 @@ vdd channel is connected to output 0 of the &ref device.
...
- iio_hwmon {
+ iio-hwmon {
compatible = "iio-hwmon";
io-channels = <&adc 0>, <&adc 1>, <&adc 2>,
<&adc 3>, <&adc 4>, <&adc 5>,
diff --git a/Bindings/iio/imu/inv_mpu6050.txt b/Bindings/iio/imu/inv_mpu6050.txt
index e4d8f1c52f4a..a9fc11e43b45 100644
--- a/Bindings/iio/imu/inv_mpu6050.txt
+++ b/Bindings/iio/imu/inv_mpu6050.txt
@@ -8,10 +8,23 @@ Required properties:
- interrupt-parent : should be the phandle for the interrupt controller
- interrupts : interrupt mapping for GPIO IRQ
+Optional properties:
+ - mount-matrix: an optional 3x3 mounting rotation matrix
+
+
Example:
mpu6050@68 {
compatible = "invensense,mpu6050";
reg = <0x68>;
interrupt-parent = <&gpio1>;
interrupts = <18 1>;
+ mount-matrix = "-0.984807753012208", /* x0 */
+ "0", /* y0 */
+ "-0.173648177666930", /* z0 */
+ "0", /* x1 */
+ "-1", /* y1 */
+ "0", /* z1 */
+ "-0.173648177666930", /* x2 */
+ "0", /* y2 */
+ "0.984807753012208"; /* z2 */
};
diff --git a/Bindings/iio/light/opt3001.txt b/Bindings/iio/light/opt3001.txt
new file mode 100644
index 000000000000..eac30d508849
--- /dev/null
+++ b/Bindings/iio/light/opt3001.txt
@@ -0,0 +1,26 @@
+* Texas Instruments OPT3001 Ambient Light Sensor
+
+The driver supports interrupt-driven and interrupt-less operation, depending
+on whether an interrupt property has been populated into the DT. Note that
+the optional generation of IIO events on rising/falling light threshold changes
+requires the use of interrupts. Without interrupts, only the simple reading
+of the current light value is supported through the IIO API.
+
+http://www.ti.com/product/opt3001
+
+Required properties:
+ - compatible: should be "ti,opt3001"
+ - reg: the I2C address of the sensor
+
+Optional properties:
+ - interrupt-parent: should be the phandle for the interrupt controller
+ - interrupts: interrupt mapping for GPIO IRQ (configure for falling edge)
+
+Example:
+
+opt3001@44 {
+ compatible = "ti,opt3001";
+ reg = <0x44>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
+};
diff --git a/Bindings/iio/magnetometer/ak8975.txt b/Bindings/iio/magnetometer/ak8975.txt
index 011679f1a425..e1e7dd3259f6 100644
--- a/Bindings/iio/magnetometer/ak8975.txt
+++ b/Bindings/iio/magnetometer/ak8975.txt
@@ -8,6 +8,8 @@ Required properties:
Optional properties:
- gpios : should be device tree identifier of the magnetometer DRDY pin
+ - vdd-supply: an optional regulator that needs to be on to provide VDD
+ - mount-matrix: an optional 3x3 mounting rotation matrix
Example:
@@ -15,4 +17,14 @@ ak8975@0c {
compatible = "asahi-kasei,ak8975";
reg = <0x0c>;
gpios = <&gpj0 7 0>;
+ vdd-supply = <&ldo_3v3_gnss>;
+ mount-matrix = "-0.984807753012208", /* x0 */
+ "0", /* y0 */
+ "-0.173648177666930", /* z0 */
+ "0", /* x1 */
+ "-1", /* y1 */
+ "0", /* z1 */
+ "-0.173648177666930", /* x2 */
+ "0", /* y2 */
+ "0.984807753012208"; /* z2 */
};
diff --git a/Bindings/iio/potentiometer/ds1803.txt b/Bindings/iio/potentiometer/ds1803.txt
new file mode 100644
index 000000000000..df77bf552656
--- /dev/null
+++ b/Bindings/iio/potentiometer/ds1803.txt
@@ -0,0 +1,21 @@
+* Maxim Integrated DS1803 digital potentiometer driver
+
+The node for this driver must be a child node of a I2C controller, hence
+all mandatory properties for your controller must be specified. See directory:
+
+ Documentation/devicetree/bindings/i2c
+
+for more details.
+
+Required properties:
+ - compatible: Must be one of the following, depending on the
+ model:
+ "maxim,ds1803-010",
+ "maxim,ds1803-050",
+ "maxim,ds1803-100"
+
+Example:
+ds1803: ds1803@1 {
+ reg = <0x28>;
+ compatible = "maxim,ds1803-010";
+};
diff --git a/Bindings/iio/potentiometer/mcp4131.txt b/Bindings/iio/potentiometer/mcp4131.txt
new file mode 100644
index 000000000000..3ccba16f7035
--- /dev/null
+++ b/Bindings/iio/potentiometer/mcp4131.txt
@@ -0,0 +1,84 @@
+* Microchip MCP413X/414X/415X/416X/423X/424X/425X/426X Digital Potentiometer
+ driver
+
+The node for this driver must be a child node of a SPI controller, hence
+all mandatory properties described in
+
+ Documentation/devicetree/bindings/spi/spi-bus.txt
+
+must be specified.
+
+Required properties:
+ - compatible: Must be one of the following, depending on the
+ model:
+ "microchip,mcp4131-502"
+ "microchip,mcp4131-103"
+ "microchip,mcp4131-503"
+ "microchip,mcp4131-104"
+ "microchip,mcp4132-502"
+ "microchip,mcp4132-103"
+ "microchip,mcp4132-503"
+ "microchip,mcp4132-104"
+ "microchip,mcp4141-502"
+ "microchip,mcp4141-103"
+ "microchip,mcp4141-503"
+ "microchip,mcp4141-104"
+ "microchip,mcp4142-502"
+ "microchip,mcp4142-103"
+ "microchip,mcp4142-503"
+ "microchip,mcp4142-104"
+ "microchip,mcp4151-502"
+ "microchip,mcp4151-103"
+ "microchip,mcp4151-503"
+ "microchip,mcp4151-104"
+ "microchip,mcp4152-502"
+ "microchip,mcp4152-103"
+ "microchip,mcp4152-503"
+ "microchip,mcp4152-104"
+ "microchip,mcp4161-502"
+ "microchip,mcp4161-103"
+ "microchip,mcp4161-503"
+ "microchip,mcp4161-104"
+ "microchip,mcp4162-502"
+ "microchip,mcp4162-103"
+ "microchip,mcp4162-503"
+ "microchip,mcp4162-104"
+ "microchip,mcp4231-502"
+ "microchip,mcp4231-103"
+ "microchip,mcp4231-503"
+ "microchip,mcp4231-104"
+ "microchip,mcp4232-502"
+ "microchip,mcp4232-103"
+ "microchip,mcp4232-503"
+ "microchip,mcp4232-104"
+ "microchip,mcp4241-502"
+ "microchip,mcp4241-103"
+ "microchip,mcp4241-503"
+ "microchip,mcp4241-104"
+ "microchip,mcp4242-502"
+ "microchip,mcp4242-103"
+ "microchip,mcp4242-503"
+ "microchip,mcp4242-104"
+ "microchip,mcp4251-502"
+ "microchip,mcp4251-103"
+ "microchip,mcp4251-503"
+ "microchip,mcp4251-104"
+ "microchip,mcp4252-502"
+ "microchip,mcp4252-103"
+ "microchip,mcp4252-503"
+ "microchip,mcp4252-104"
+ "microchip,mcp4261-502"
+ "microchip,mcp4261-103"
+ "microchip,mcp4261-503"
+ "microchip,mcp4261-104"
+ "microchip,mcp4262-502"
+ "microchip,mcp4262-103"
+ "microchip,mcp4262-503"
+ "microchip,mcp4262-104"
+
+Example:
+mcp4131: mcp4131@0 {
+ compatible = "mcp4131-502";
+ reg = <0>;
+ spi-max-frequency = <500000>;
+};
diff --git a/Bindings/iio/pressure/hp03.txt b/Bindings/iio/pressure/hp03.txt
new file mode 100644
index 000000000000..54e7e70bcea5
--- /dev/null
+++ b/Bindings/iio/pressure/hp03.txt
@@ -0,0 +1,17 @@
+HopeRF HP03 digital pressure/temperature sensors
+
+Required properties:
+- compatible: must be "hoperf,hp03"
+- xclr-gpio: must be device tree identifier of the XCLR pin.
+ The XCLR pin is a reset of the ADC in the chip,
+ it must be pulled HI before the conversion and
+ readout of the value from the ADC registers and
+ pulled LO afterward.
+
+Example:
+
+hp03@0x77 {
+ compatible = "hoperf,hp03";
+ reg = <0x77>;
+ xclr-gpio = <&portc 0 0x0>;
+};
diff --git a/Bindings/iio/pressure/ms5611.txt b/Bindings/iio/pressure/ms5611.txt
new file mode 100644
index 000000000000..17bca866c084
--- /dev/null
+++ b/Bindings/iio/pressure/ms5611.txt
@@ -0,0 +1,19 @@
+MEAS ms5611 family pressure sensors
+
+Pressure sensors from MEAS Switzerland with SPI and I2C bus interfaces.
+
+Required properties:
+- compatible: "meas,ms5611" or "meas,ms5607"
+- reg: the I2C address or SPI chip select the device will respond to
+
+Optional properties:
+- vdd-supply: an optional regulator that needs to be on to provide VDD
+ power to the sensor.
+
+Example:
+
+ms5607@77 {
+ compatible = "meas,ms5607";
+ reg = <0x77>;
+ vdd-supply = <&ldo_3v3_gnss>;
+};
diff --git a/Bindings/iio/st-sensors.txt b/Bindings/iio/st-sensors.txt
index d4b87cc1e446..5844cf72862d 100644
--- a/Bindings/iio/st-sensors.txt
+++ b/Bindings/iio/st-sensors.txt
@@ -16,6 +16,10 @@ Optional properties:
- st,drdy-int-pin: the pin on the package that will be used to signal
"data ready" (valid values: 1 or 2). This property is not configurable
on all sensors.
+- drive-open-drain: the interrupt/data ready line will be configured
+ as open drain, which is useful if several sensors share the same
+ interrupt line. (This binding is taken from pinctrl/pinctrl-bindings.txt)
+ This is a boolean property.
Sensors may also have applicable pin control settings, those use the
standard bindings from pinctrl/pinctrl-bindings.txt.
@@ -37,6 +41,7 @@ Accelerometers:
- st,lsm330-accel
- st,lsm303agr-accel
- st,lis2dh12-accel
+- st,h3lis331dl-accel
Gyroscopes:
- st,l3g4200d-gyro
@@ -46,6 +51,7 @@ Gyroscopes:
- st,l3gd20-gyro
- st,l3g4is-gyro
- st,lsm330-gyro
+- st,lsm9ds0-gyro
Magnetometers:
- st,lsm303agr-magn
diff --git a/Bindings/input/ads7846.txt b/Bindings/input/ads7846.txt
index 33a1638b61d6..9fc47b006fd1 100644
--- a/Bindings/input/ads7846.txt
+++ b/Bindings/input/ads7846.txt
@@ -29,6 +29,8 @@ Optional properties:
ti,vref-delay-usecs vref supply delay in usecs, 0 for
external vref (u16).
ti,vref-mv The VREF voltage, in millivolts (u16).
+ Set to 0 to use internal references
+ (ADS7846).
ti,keep-vref-on set to keep vref on for differential
measurements as well
ti,swap-xy swap x and y axis
diff --git a/Bindings/input/gpio-keys.txt b/Bindings/input/gpio-keys.txt
index 21641236c095..a94940481e55 100644
--- a/Bindings/input/gpio-keys.txt
+++ b/Bindings/input/gpio-keys.txt
@@ -32,17 +32,17 @@ Optional subnode-properties:
Example nodes:
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
autorepeat;
- button@21 {
+
+ up {
label = "GPIO Key UP";
linux,code = <103>;
gpios = <&gpio1 0 1>;
};
- button@22 {
+
+ down {
label = "GPIO Key DOWN";
linux,code = <108>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
diff --git a/Bindings/input/rmi4/rmi_2d_sensor.txt b/Bindings/input/rmi4/rmi_2d_sensor.txt
new file mode 100644
index 000000000000..f2c30c8b725d
--- /dev/null
+++ b/Bindings/input/rmi4/rmi_2d_sensor.txt
@@ -0,0 +1,56 @@
+Synaptics RMI4 2D Sensor Device Binding
+
+The Synaptics RMI4 core is able to support RMI4 devices using different
+transports and different functions. This file describes the device tree
+bindings for devices which contain 2D sensors using Function 11 or
+Function 12. Complete documentation for transports and other functions
+can be found in:
+Documentation/devicetree/bindings/input/rmi4.
+
+RMI4 Function 11 and Function 12 are for 2D touch position sensing.
+Additional documentation for F11 can be found at:
+http://www.synaptics.com/sites/default/files/511-000136-01-Rev-E-RMI4-Interfacing-Guide.pdf
+
+Optional Touch Properties:
+Description in Documentation/devicetree/bindings/input/touch
+- touchscreen-inverted-x
+- touchscreen-inverted-y
+- touchscreen-swapped-x-y
+- touchscreen-x-mm
+- touchscreen-y-mm
+
+Optional Properties:
+- syna,clip-x-low: Sets a minimum value for X.
+- syna,clip-y-low: Sets a minimum value for Y.
+- syna,clip-x-high: Sets a maximum value for X.
+- syna,clip-y-high: Sets a maximum value for Y.
+- syna,offset-x: Add an offset to X.
+- syna,offset-y: Add an offset to Y.
+- syna,delta-x-threshold: Set the minimum distance on the X axis required
+ to generate an interrupt in reduced reporting
+ mode.
+- syna,delta-y-threshold: Set the minimum distance on the Y axis required
+ to generate an interrupt in reduced reporting
+ mode.
+- syna,sensor-type: Set the sensor type. 1 for touchscreen 2 for touchpad.
+- syna,disable-report-mask: Mask for disabling posiiton reporting. Used to
+ disable reporing absolute position data.
+- syna,rezero-wait-ms: Time in miliseconds to wait after issuing a rezero
+ command.
+
+
+Example of a RMI4 I2C device with F11:
+Example:
+ &i2c1 {
+ rmi4-i2c-dev@2c {
+ compatible = "syna,rmi4-i2c";
+
+ ...
+
+ rmi4-f11@11 {
+ reg = <0x11>;
+ touchscreen-inverted-y;
+ syna,sensor-type = <2>;
+ };
+ };
+ };
diff --git a/Bindings/input/rmi4/rmi_f01.txt b/Bindings/input/rmi4/rmi_f01.txt
new file mode 100644
index 000000000000..079cad2b6843
--- /dev/null
+++ b/Bindings/input/rmi4/rmi_f01.txt
@@ -0,0 +1,39 @@
+Synaptics RMI4 F01 Device Binding
+
+The Synaptics RMI4 core is able to support RMI4 devices using different
+transports and different functions. This file describes the device tree
+bindings for devices which contain Function 1. Complete documentation
+for transports and other functions can be found in:
+Documentation/devicetree/bindings/input/rmi4.
+
+Additional documentation for F01 can be found at:
+http://www.synaptics.com/sites/default/files/511-000136-01-Rev-E-RMI4-Interfacing-Guide.pdf
+
+Optional Properties:
+- syna,nosleep-mode: If set the device will run at full power without sleeping.
+ nosleep has 3 modes, 0 will not change the default
+ setting, 1 will disable nosleep (allow sleeping),
+ and 2 will enable nosleep (disabling sleep).
+- syna,wakeup-threshold: Defines the amplitude of the disturbance to the
+ background capacitance that will cause the
+ device to wake from dozing.
+- syna,doze-holdoff-ms: The delay to wait after the last finger lift and the
+ first doze cycle.
+- syna,doze-interval-ms: The time period that the device sleeps between finger
+ activity.
+
+
+Example of a RMI4 I2C device with F01:
+ Example:
+ &i2c1 {
+ rmi4-i2c-dev@2c {
+ compatible = "syna,rmi4-i2c";
+
+ ...
+
+ rmi4-f01@1 {
+ reg = <0x1>;
+ syna,nosleep-mode = <1>;
+ };
+ };
+ };
diff --git a/Bindings/input/rmi4/rmi_i2c.txt b/Bindings/input/rmi4/rmi_i2c.txt
new file mode 100644
index 000000000000..95fa715c6046
--- /dev/null
+++ b/Bindings/input/rmi4/rmi_i2c.txt
@@ -0,0 +1,53 @@
+Synaptics RMI4 I2C Device Binding
+
+The Synaptics RMI4 core is able to support RMI4 devices using different
+transports and different functions. This file describes the device tree
+bindings for devices using the I2C transport driver. Complete documentation
+for other transports and functions can be found in
+Documentation/devicetree/bindings/input/rmi4.
+
+Required Properties:
+- compatible: syna,rmi4-i2c
+- reg: I2C address
+- #address-cells: Set to 1 to indicate that the function child nodes
+ consist of only on uint32 value.
+- #size-cells: Set to 0 to indicate that the function child nodes do not
+ have a size property.
+
+Optional Properties:
+- interrupts: interrupt which the rmi device is connected to.
+- interrupt-parent: The interrupt controller.
+See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
+
+- syna,reset-delay-ms: The number of milliseconds to wait after resetting the
+ device.
+
+Function Parameters:
+Parameters specific to RMI functions are contained in child nodes of the rmi device
+ node. Documentation for the parameters of each function can be found in:
+Documentation/devicetree/bindings/input/rmi4/rmi_f*.txt.
+
+
+
+Example:
+ &i2c1 {
+ rmi4-i2c-dev@2c {
+ compatible = "syna,rmi4-i2c";
+ reg = <0x2c>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = <&gpio>;
+ interrupts = <4 2>;
+
+ rmi4-f01@1 {
+ reg = <0x1>;
+ syna,nosleep-mode = <1>;
+ };
+
+ rmi4-f11@11 {
+ reg = <0x11>;
+ touchscreen-inverted-y;
+ syna,sensor-type = <2>;
+ };
+ };
+ };
diff --git a/Bindings/input/rmi4/rmi_spi.txt b/Bindings/input/rmi4/rmi_spi.txt
new file mode 100644
index 000000000000..a4ca7828f21d
--- /dev/null
+++ b/Bindings/input/rmi4/rmi_spi.txt
@@ -0,0 +1,57 @@
+Synaptics RMI4 SPI Device Binding
+
+The Synaptics RMI4 core is able to support RMI4 devices using different
+transports and different functions. This file describes the device tree
+bindings for devices using the SPI transport driver. Complete documentation
+for other transports and functions can be found in
+Documentation/devicetree/bindings/input/rmi4.
+
+Required Properties:
+- compatible: syna,rmi4-spi
+- reg: Chip select address for the device
+- #address-cells: Set to 1 to indicate that the function child nodes
+ consist of only on uint32 value.
+- #size-cells: Set to 0 to indicate that the function child nodes do not
+ have a size property.
+
+Optional Properties:
+- interrupts: interrupt which the rmi device is connected to.
+- interrupt-parent: The interrupt controller.
+See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
+
+- spi-rx-delay-us: microsecond delay after a read transfer.
+- spi-tx-delay-us: microsecond delay after a write transfer.
+
+Function Parameters:
+Parameters specific to RMI functions are contained in child nodes of the rmi device
+ node. Documentation for the parameters of each function can be found in:
+Documentation/devicetree/bindings/input/rmi4/rmi_f*.txt.
+
+
+
+Example:
+ spi@7000d800 {
+ rmi4-spi-dev@0 {
+ compatible = "syna,rmi4-spi";
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ spi-max-frequency = <4000000>;
+ spi-cpha;
+ spi-cpol;
+ interrupt-parent = <&gpio>;
+ interrupts = <TEGRA_GPIO(K, 2) 0x2>;
+ spi-rx-delay-us = <30>;
+
+ rmi4-f01@1 {
+ reg = <0x1>;
+ syna,nosleep-mode = <1>;
+ };
+
+ rmi4-f11@11 {
+ reg = <0x11>;
+ touchscreen-inverted-y;
+ syna,sensor-type = <2>;
+ };
+ };
+ };
diff --git a/Bindings/input/rotary-encoder.txt b/Bindings/input/rotary-encoder.txt
index de99cbbbf6da..6c9f0c8a846c 100644
--- a/Bindings/input/rotary-encoder.txt
+++ b/Bindings/input/rotary-encoder.txt
@@ -1,7 +1,7 @@
Rotary encoder DT bindings
Required properties:
-- gpios: a spec for two GPIOs to be used
+- gpios: a spec for at least two GPIOs to be used, most significant first
Optional properties:
- linux,axis: the input subsystem axis to map to this rotary encoder.
diff --git a/Bindings/input/touchscreen/ad7879.txt b/Bindings/input/touchscreen/ad7879.txt
new file mode 100644
index 000000000000..e3f22d23fc8f
--- /dev/null
+++ b/Bindings/input/touchscreen/ad7879.txt
@@ -0,0 +1,53 @@
+* Analog Devices AD7879(-1)/AD7889(-1) touchscreen interface (SPI/I2C)
+
+Required properties:
+- compatible : for SPI slave, use "adi,ad7879"
+ for I2C slave, use "adi,ad7879-1"
+- reg : SPI chipselect/I2C slave address
+ See spi-bus.txt for more SPI slave properties
+- interrupt-parent : the phandle for the interrupt controller
+- interrupts : touch controller interrupt
+- touchscreen-max-pressure : maximum reported pressure
+- adi,resistance-plate-x : total resistance of X-plate (for pressure
+ calculation)
+Optional properties:
+- touchscreen-swapped-x-y : X and Y axis are swapped (boolean)
+- adi,first-conversion-delay : 0-12: In 128us steps (starting with 128us)
+ 13 : 2.560ms
+ 14 : 3.584ms
+ 15 : 4.096ms
+ This property has to be a '/bits/ 8' value
+- adi,acquisition-time : 0: 2us
+ 1: 4us
+ 2: 8us
+ 3: 16us
+ This property has to be a '/bits/ 8' value
+- adi,median-filter-size : 0: disabled
+ 1: 4 measurements
+ 2: 8 measurements
+ 3: 16 measurements
+ This property has to be a '/bits/ 8' value
+- adi,averaging : 0: 2 middle values (1 if median disabled)
+ 1: 4 middle values
+ 2: 8 middle values
+ 3: 16 values
+ This property has to be a '/bits/ 8' value
+- adi,conversion-interval: : 0 : convert one time only
+ 1-255: 515us + val * 35us (up to 9.440ms)
+ This property has to be a '/bits/ 8' value
+
+Example:
+
+ ad7879@2c {
+ compatible = "adi,ad7879-1";
+ reg = <0x2c>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
+ touchscreen-max-pressure = <4096>;
+ adi,resistance-plate-x = <120>;
+ adi,first-conversion-delay = /bits/ 8 <3>;
+ adi,acquisition-time = /bits/ 8 <1>;
+ adi,median-filter-size = /bits/ 8 <2>;
+ adi,averaging = /bits/ 8 <1>;
+ adi,conversion-interval = /bits/ 8 <255>;
+ };
diff --git a/Bindings/input/touchscreen/brcm,iproc-touchscreen.txt b/Bindings/input/touchscreen/brcm,iproc-touchscreen.txt
index 34e3382a0659..ac5dff412e25 100644
--- a/Bindings/input/touchscreen/brcm,iproc-touchscreen.txt
+++ b/Bindings/input/touchscreen/brcm,iproc-touchscreen.txt
@@ -2,11 +2,17 @@
Required properties:
- compatible: must be "brcm,iproc-touchscreen"
-- reg: physical base address of the controller and length of memory mapped
- region.
+- ts_syscon: handler of syscon node defining physical base
+ address of the controller and length of memory mapped region.
+ If this property is selected please make sure MFD_SYSCON config
+ is enabled in the defconfig file.
- clocks: The clock provided by the SOC to driver the tsc
-- clock-name: name for the clock
+- clock-names: name for the clock
- interrupts: The touchscreen controller's interrupt
+- address-cells: Specify the number of u32 entries needed in child nodes.
+ Should set to 1.
+- size-cells: Specify number of u32 entries needed to specify child nodes size
+ in reg property. Should set to 1.
Optional properties:
- scanning_period: Time between scans. Each step is 1024 us. Valid 1-256.
@@ -53,13 +59,18 @@ Optional properties:
- touchscreen-inverted-x: X axis is inverted (boolean)
- touchscreen-inverted-y: Y axis is inverted (boolean)
-Example:
+Example: An example of touchscreen node
- touchscreen: tsc@0x180A6000 {
+ ts_adc_syscon: ts_adc_syscon@180a6000 {
+ compatible = "brcm,iproc-ts-adc-syscon","syscon";
+ reg = <0x180a6000 0xc30>;
+ };
+
+ touchscreen: touchscreen@180A6000 {
compatible = "brcm,iproc-touchscreen";
#address-cells = <1>;
#size-cells = <1>;
- reg = <0x180A6000 0x40>;
+ ts_syscon = <&ts_adc_syscon>;
clocks = <&adc_clk>;
clock-names = "tsc_clk";
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/Bindings/input/touchscreen/cyttsp.txt b/Bindings/input/touchscreen/cyttsp.txt
new file mode 100644
index 000000000000..b75d4cfd2c36
--- /dev/null
+++ b/Bindings/input/touchscreen/cyttsp.txt
@@ -0,0 +1,95 @@
+* Cypress cyttsp touchscreen controller
+
+Required properties:
+ - compatible : must be "cypress,cyttsp-i2c" or "cypress,cyttsp-spi"
+ - reg : Device I2C address or SPI chip select number
+ - spi-max-frequency : Maximum SPI clocking speed of the device (for cyttsp-spi)
+ - interrupt-parent : the phandle for the gpio controller
+ (see interrupt binding[0]).
+ - interrupts : (gpio) interrupt to which the chip is connected
+ (see interrupt binding[0]).
+ - bootloader-key : the 8-byte bootloader key that is required to switch
+ the chip from bootloader mode (default mode) to
+ application mode.
+ This property has to be specified as an array of 8
+ '/bits/ 8' values.
+
+Optional properties:
+ - reset-gpios : the reset gpio the chip is connected to
+ (see GPIO binding[1] for more details).
+ - touchscreen-size-x : horizontal resolution of touchscreen (in pixels)
+ - touchscreen-size-y : vertical resolution of touchscreen (in pixels)
+ - touchscreen-fuzz-x : horizontal noise value of the absolute input device
+ (in pixels)
+ - touchscreen-fuzz-y : vertical noise value of the absolute input device
+ (in pixels)
+ - active-distance : the distance in pixels beyond which a touch must move
+ before movement is detected and reported by the device.
+ Valid values: 0-15.
+ - active-interval-ms : the minimum period in ms between consecutive
+ scanning/processing cycles when the chip is in active mode.
+ Valid values: 0-255.
+ - lowpower-interval-ms : the minimum period in ms between consecutive
+ scanning/processing cycles when the chip is in low-power mode.
+ Valid values: 0-2550
+ - touch-timeout-ms : minimum time in ms spent in the active power state while no
+ touches are detected before entering low-power mode.
+ Valid values: 0-2550
+ - use-handshake : enable register-based handshake (boolean). This should
+ only be used if the chip is configured to use 'blocking
+ communication with timeout' (in this case the device
+ generates an interrupt at the end of every
+ scanning/processing cycle).
+
+[0]: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
+[1]: Documentation/devicetree/bindings/gpio/gpio.txt
+
+Example:
+ &i2c1 {
+ /* ... */
+ cyttsp@a {
+ compatible = "cypress,cyttsp-i2c";
+ reg = <0xa>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <28 0>;
+ reset-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>;
+
+ touchscreen-size-x = <800>;
+ touchscreen-size-y = <480>;
+ touchscreen-fuzz-x = <4>;
+ touchscreen-fuzz-y = <7>;
+
+ bootloader-key = /bits/ 8 <0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08>;
+ active-distance = <8>;
+ active-interval-ms = <0>;
+ lowpower-interval-ms = <200>;
+ touch-timeout-ms = <100>;
+ };
+
+ /* ... */
+ };
+
+ &mcspi1 {
+ /* ... */
+ cyttsp@0 {
+ compatible = "cypress,cyttsp-spi";
+ spi-max-frequency = <6000000>;
+ reg = <0>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <28 0>;
+ reset-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>;
+
+ touchscreen-size-x = <800>;
+ touchscreen-size-y = <480>;
+ touchscreen-fuzz-x = <4>;
+ touchscreen-fuzz-y = <7>;
+
+ bootloader-key = /bits/ 8 <0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08>;
+ active-distance = <8>;
+ active-interval-ms = <0>;
+ lowpower-interval-ms = <200>;
+ touch-timeout-ms = <100>;
+ };
+
+ /* ... */
+ };
diff --git a/Bindings/input/touchscreen/fsl-mx25-tcq.txt b/Bindings/input/touchscreen/fsl-mx25-tcq.txt
new file mode 100644
index 000000000000..abfcab3edc66
--- /dev/null
+++ b/Bindings/input/touchscreen/fsl-mx25-tcq.txt
@@ -0,0 +1,35 @@
+Freescale mx25 TS conversion queue module
+
+mx25 touchscreen conversion queue module which controls the ADC unit of the
+mx25 for attached touchscreens.
+
+Required properties:
+ - compatible: Should be "fsl,imx25-tcq".
+ - reg: Memory range of the device.
+ - interrupts: Should be the interrupt number associated with this module within
+ the tscadc unit (<0>).
+ - interrupt-parent: Should be a phandle to the tscadc unit.
+ - fsl,wires: Should be '<4>' or '<5>'
+
+Optional properties:
+ - fsl,pen-debounce-ns: Pen debounce time in nanoseconds.
+ - fsl,pen-threshold: Pen-down threshold for the touchscreen. This is a value
+ between 1 and 4096. It is the ratio between the internal reference voltage
+ and the measured voltage after the plate was precharged. Resistance between
+ plates and therefore the voltage decreases with pressure so that a smaller
+ value is equivalent to a higher pressure.
+ - fsl,settling-time-ns: Settling time in nanoseconds. The settling time is before
+ the actual touch detection to wait for an even charge distribution in the
+ plate.
+
+This device includes two conversion queues which can be added as subnodes.
+The first queue is for the touchscreen, the second for general purpose ADC.
+
+Example:
+ tsc: tcq@50030400 {
+ compatible = "fsl,imx25-tcq";
+ reg = <0x50030400 0x60>;
+ interrupt-parent = <&tscadc>;
+ interrupts = <0>;
+ fsl,wires = <4>;
+ };
diff --git a/Bindings/input/touchscreen/touchscreen.txt b/Bindings/input/touchscreen/touchscreen.txt
index ac23caf518ad..bccaa4e73045 100644
--- a/Bindings/input/touchscreen/touchscreen.txt
+++ b/Bindings/input/touchscreen/touchscreen.txt
@@ -18,6 +18,8 @@ Optional properties for Touchscreens:
- touchscreen-inverted-y : Y axis is inverted (boolean)
- touchscreen-swapped-x-y : X and Y axis are swapped (boolean)
Swapping is done after inverting the axis
+ - touchscreen-x-mm : horizontal length in mm of the touchscreen
+ - touchscreen-y-mm : vertical length in mm of the touchscreen
Deprecated properties for Touchscreens:
- x-size : deprecated name for touchscreen-size-x
diff --git a/Bindings/interrupt-controller/al,alpine-msix.txt b/Bindings/interrupt-controller/al,alpine-msix.txt
new file mode 100644
index 000000000000..f6f1c14bf99b
--- /dev/null
+++ b/Bindings/interrupt-controller/al,alpine-msix.txt
@@ -0,0 +1,26 @@
+Alpine MSIX controller
+
+See arm,gic-v3.txt for SPI and MSI definitions.
+
+Required properties:
+
+- compatible: should be "al,alpine-msix"
+- reg: physical base address and size of the registers
+- interrupt-parent: specifies the parent interrupt controller.
+- interrupt-controller: identifies the node as an interrupt controller
+- msi-controller: identifies the node as an PCI Message Signaled Interrupt
+ controller
+- al,msi-base-spi: SPI base of the MSI frame
+- al,msi-num-spis: number of SPIs assigned to th