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authorEmmanuel Vadot <manu@FreeBSD.org>2017-11-13 20:15:33 +0000
committerEmmanuel Vadot <manu@FreeBSD.org>2017-11-13 20:15:33 +0000
commit550370858c61e6f7fe3832de73daa9cc25ba716a (patch)
treeb8d380020ec7026d5a54e3a2c67ef46ac8859511
parentd5464ff11700ac44568e6816e00d1d1427cc46ae (diff)
downloadsrc-550370858c61e6f7fe3832de73daa9cc25ba716a.tar.gz
src-550370858c61e6f7fe3832de73daa9cc25ba716a.zip
Update our copies of the Device Tree Source to Linux 4.14vendor/device-tree/4.14
Notes
Notes: svn path=/vendor/device-tree/dist/; revision=325773 svn path=/vendor/device-tree/4.14/; revision=325774; tag=vendor/device-tree/4.14
-rw-r--r--Bindings/arc/hsdk.txt7
-rw-r--r--Bindings/arm/amlogic.txt41
-rw-r--r--Bindings/arm/arch_timer.txt1
-rw-r--r--Bindings/arm/bcm/brcm,bcm2835.txt4
-rw-r--r--Bindings/arm/bhf.txt6
-rw-r--r--Bindings/arm/coresight.txt4
-rw-r--r--Bindings/arm/cpus.txt1
-rw-r--r--Bindings/arm/marvell/armada-8kp.txt15
-rw-r--r--Bindings/arm/marvell/cp110-system-controller0.txt1
-rw-r--r--Bindings/arm/mediatek.txt18
-rw-r--r--Bindings/arm/omap/omap.txt9
-rw-r--r--Bindings/arm/pmu.txt2
-rw-r--r--Bindings/arm/qcom.txt2
-rw-r--r--Bindings/arm/rockchip.txt12
-rw-r--r--Bindings/arm/shmobile.txt8
-rw-r--r--Bindings/ata/ahci-mtk.txt51
-rw-r--r--Bindings/ata/apm-xgene.txt2
-rw-r--r--Bindings/ata/imx-pata.txt1
-rw-r--r--Bindings/bus/mvebu-mbus.txt3
-rw-r--r--Bindings/bus/nvidia,tegra20-gmi.txt2
-rw-r--r--Bindings/bus/nvidia,tegra210-aconnect.txt1
-rw-r--r--Bindings/chosen.txt26
-rw-r--r--Bindings/clock/alphascale,acc.txt1
-rw-r--r--Bindings/clock/amlogic,gxbb-aoclkc.txt23
-rw-r--r--Bindings/clock/amlogic,gxbb-clkc.txt1
-rw-r--r--Bindings/clock/amlogic,meson8b-clkc.txt10
-rw-r--r--Bindings/clock/at91-clock.txt10
-rw-r--r--Bindings/clock/brcm,kona-ccu.txt1
-rw-r--r--Bindings/clock/exynos5433-clock.txt1
-rw-r--r--Bindings/clock/hi3660-clock.txt1
-rw-r--r--Bindings/clock/hix5hd2-clock.txt1
-rw-r--r--Bindings/clock/idt,versaclock5.txt30
-rw-r--r--Bindings/clock/imx21-clock.txt1
-rw-r--r--Bindings/clock/imx23-clock.txt1
-rw-r--r--Bindings/clock/imx25-clock.txt1
-rw-r--r--Bindings/clock/imx27-clock.txt1
-rw-r--r--Bindings/clock/imx28-clock.txt1
-rw-r--r--Bindings/clock/imx31-clock.txt1
-rw-r--r--Bindings/clock/imx5-clock.txt1
-rw-r--r--Bindings/clock/imx6q-clock.txt1
-rw-r--r--Bindings/clock/mt8173-cpu-dvfs.txt83
-rw-r--r--Bindings/clock/nvidia,tegra124-dfll.txt1
-rw-r--r--Bindings/clock/pxa-clock.txt1
-rw-r--r--Bindings/clock/renesas,cpg-mssr.txt4
-rw-r--r--Bindings/clock/renesas,r8a7778-cpg-clocks.txt1
-rw-r--r--Bindings/clock/renesas,rcar-usb2-clock-sel.txt55
-rw-r--r--Bindings/clock/renesas,rz-cpg-clocks.txt1
-rw-r--r--Bindings/clock/rockchip,rk3128-cru.txt8
-rw-r--r--Bindings/clock/samsung,s3c2410-clock.txt1
-rw-r--r--Bindings/clock/samsung,s3c2412-clock.txt1
-rw-r--r--Bindings/clock/samsung,s3c2443-clock.txt1
-rw-r--r--Bindings/clock/samsung,s3c64xx-clock.txt1
-rw-r--r--Bindings/clock/samsung,s5pv210-clock.txt1
-rw-r--r--Bindings/clock/silabs,si5351.txt6
-rw-r--r--Bindings/clock/snps,hsdk-pll-clock.txt28
-rw-r--r--Bindings/clock/snps,pll-clock.txt28
-rw-r--r--Bindings/clock/st,stm32h7-rcc.txt71
-rw-r--r--Bindings/clock/sunxi-ccu.txt6
-rw-r--r--Bindings/clock/ti,sci-clk.txt7
-rw-r--r--Bindings/clock/ti/dra7-atl.txt2
-rw-r--r--Bindings/clock/uniphier-clock.txt8
-rw-r--r--Bindings/clock/zx296702-clk.txt1
-rw-r--r--Bindings/clock/zx296718-clk.txt1
-rw-r--r--Bindings/cpufreq/cpufreq-mediatek.txt247
-rw-r--r--Bindings/crypto/artpec6-crypto.txt16
-rw-r--r--Bindings/crypto/atmel-crypto.txt13
-rw-r--r--Bindings/crypto/fsl-dcp.txt1
-rw-r--r--Bindings/crypto/inside-secure-safexcel.txt1
-rw-r--r--Bindings/crypto/marvell-cesa.txt1
-rw-r--r--Bindings/crypto/mv_cesa.txt1
-rw-r--r--Bindings/crypto/rockchip-crypto.txt1
-rw-r--r--Bindings/crypto/st,stm32-hash.txt30
-rw-r--r--Bindings/devfreq/event/rockchip-dfi.txt1
-rw-r--r--Bindings/devfreq/rk3399_dmc.txt1
-rw-r--r--Bindings/display/atmel,lcdc.txt1
-rw-r--r--Bindings/display/atmel/hlcdc-dc.txt1
-rw-r--r--Bindings/display/bridge/dw_mipi_dsi.txt32
-rw-r--r--Bindings/display/bridge/megachips-stdpxxxx-ge-b850v3-fw.txt1
-rw-r--r--Bindings/display/bridge/renesas,dw-hdmi.txt2
-rw-r--r--Bindings/display/exynos/exynos5433-decon.txt12
-rw-r--r--Bindings/display/fsl,tcon.txt1
-rw-r--r--Bindings/display/imx/fsl-imx-drm.txt2
-rw-r--r--Bindings/display/marvell,pxa2xx-lcdc.txt1
-rw-r--r--Bindings/display/panel/innolux,p079zca.txt1
-rw-r--r--Bindings/display/renesas,du.txt51
-rw-r--r--Bindings/display/repaper.txt52
-rw-r--r--Bindings/display/rockchip/analogix_dp-rockchip.txt1
-rw-r--r--Bindings/display/rockchip/dw_hdmi-rockchip.txt8
-rw-r--r--Bindings/display/rockchip/dw_mipi_dsi_rockchip.txt2
-rw-r--r--Bindings/display/rockchip/inno_hdmi-rockchip.txt1
-rw-r--r--Bindings/display/rockchip/rockchip-vop.txt4
-rw-r--r--Bindings/display/simple-framebuffer-sunxi.txt1
-rw-r--r--Bindings/display/sitronix,st7586.txt22
-rw-r--r--Bindings/display/st,stm32-ltdc.txt105
-rw-r--r--Bindings/display/sunxi/sun4i-drm.txt37
-rw-r--r--Bindings/dma/fsl-edma.txt1
-rw-r--r--Bindings/dma/mv-xor.txt1
-rw-r--r--Bindings/dma/qcom_adm.txt1
-rw-r--r--Bindings/dma/renesas,rcar-dmac.txt1
-rw-r--r--Bindings/dma/renesas,usb-dmac.txt1
-rw-r--r--Bindings/dma/snps-dma.txt1
-rw-r--r--Bindings/dma/st_fdma.txt1
-rw-r--r--Bindings/dma/ste-dma40.txt1
-rw-r--r--Bindings/dma/sun4i-dma.txt1
-rw-r--r--Bindings/dma/sun6i-dma.txt1
-rw-r--r--Bindings/dma/ti-dma-crossbar.txt1
-rw-r--r--Bindings/dma/ti-edma.txt96
-rw-r--r--Bindings/eeprom/eeprom.txt6
-rw-r--r--Bindings/extcon/extcon-usbc-cros-ec.txt24
-rw-r--r--Bindings/fpga/altera-passive-serial.txt29
-rw-r--r--Bindings/fpga/xilinx-pr-decoupler.txt36
-rw-r--r--Bindings/fpga/xilinx-slave-serial.txt1
-rw-r--r--Bindings/gpio/gpio-74x164.txt3
-rw-r--r--Bindings/gpio/gpio-aspeed.txt2
-rw-r--r--Bindings/gpio/gpio-davinci.txt91
-rw-r--r--Bindings/gpio/gpio-mpc8xxx.txt1
-rw-r--r--Bindings/gpio/gpio-vf610.txt4
-rw-r--r--Bindings/gpio/renesas,gpio-rcar.txt16
-rw-r--r--Bindings/gpio/spear_spics.txt1
-rw-r--r--Bindings/gpu/arm,mali-midgard.txt1
-rw-r--r--Bindings/gpu/arm,mali-utgard.txt5
-rw-r--r--Bindings/gpu/nvidia,gk20a.txt3
-rw-r--r--Bindings/gpu/samsung-g2d.txt1
-rw-r--r--Bindings/hsi/omap-ssi.txt1
-rw-r--r--Bindings/hwmon/aspeed-pwm-tacho.txt9
-rw-r--r--Bindings/hwmon/ibm,cffps1.txt21
-rw-r--r--Bindings/hwmon/ltq-cputemp.txt10
-rw-r--r--Bindings/i2c/i2c-altera.txt39
-rw-r--r--Bindings/i2c/i2c-cbus-gpio.txt4
-rw-r--r--Bindings/i2c/i2c-demux-pinctrl.txt1
-rw-r--r--Bindings/i2c/i2c-efm32.txt1
-rw-r--r--Bindings/i2c/i2c-mtk.txt15
-rw-r--r--Bindings/i2c/i2c-rcar.txt5
-rw-r--r--Bindings/i2c/i2c-rk3x.txt1
-rw-r--r--Bindings/i2c/i2c-sh_mobile.txt5
-rw-r--r--Bindings/i2c/i2c-sprd.txt31
-rw-r--r--Bindings/i2c/i2c-stm32.txt29
-rw-r--r--Bindings/i2c/nvidia,tegra20-i2c.txt1
-rw-r--r--Bindings/iio/adc/at91-sama5d2_adc.txt6
-rw-r--r--Bindings/iio/adc/brcm,iproc-static-adc.txt1
-rw-r--r--Bindings/iio/adc/lpc1850-adc.txt1
-rw-r--r--Bindings/iio/adc/mt6577_auxadc.txt1
-rw-r--r--Bindings/iio/adc/rockchip-saradc.txt1
-rw-r--r--Bindings/iio/adc/st,stm32-adc.txt5
-rw-r--r--Bindings/iio/counter/stm32-lptimer-cnt.txt27
-rw-r--r--Bindings/iio/dac/lpc1850-dac.txt1
-rw-r--r--Bindings/iio/dac/st,stm32-dac.txt4
-rw-r--r--Bindings/iio/humidity/hdc100x.txt17
-rw-r--r--Bindings/iio/humidity/hts221.txt11
-rw-r--r--Bindings/iio/humidity/htu21.txt13
-rw-r--r--Bindings/iio/imu/st_lsm6dsx.txt8
-rw-r--r--Bindings/iio/pressure/ms5637.txt17
-rw-r--r--Bindings/iio/proximity/as3935.txt5
-rw-r--r--Bindings/iio/st-sensors.txt3
-rw-r--r--Bindings/iio/temperature/tsys01.txt19
-rw-r--r--Bindings/iio/timer/stm32-lptimer-trigger.txt23
-rw-r--r--Bindings/iio/timer/stm32-timer-trigger.txt6
-rw-r--r--Bindings/input/atmel,maxtouch.txt2
-rw-r--r--Bindings/input/brcm,bcm-keypad.txt1
-rw-r--r--Bindings/input/pwm-vibrator.txt66
-rw-r--r--Bindings/input/ti,drv260x.txt2
-rw-r--r--Bindings/input/touchscreen/colibri-vf50-ts.txt1
-rw-r--r--Bindings/input/touchscreen/imx6ul_tsc.txt1
-rw-r--r--Bindings/interrupt-controller/arm,gic-v3.txt6
-rw-r--r--Bindings/interrupt-controller/fsl,ls-scfg-msi.txt8
-rw-r--r--Bindings/interrupt-controller/mediatek,sysirq.txt1
-rw-r--r--Bindings/interrupt-controller/socionext,uniphier-aidet.txt32
-rw-r--r--Bindings/iommu/qcom,iommu.txt121
-rw-r--r--Bindings/iommu/rockchip,iommu.txt5
-rw-r--r--Bindings/leds/ams,as3645a.txt79
-rw-r--r--Bindings/leds/irled/gpio-ir-tx.txt14
-rw-r--r--Bindings/leds/irled/pwm-ir-tx.txt13
-rw-r--r--Bindings/leds/leds-gpio.txt3
-rw-r--r--Bindings/leds/leds-pca955x.txt88
-rw-r--r--Bindings/media/i2c/adv748x.txt95
-rw-r--r--Bindings/media/i2c/dongwoon,dw9714.txt9
-rw-r--r--Bindings/media/meson-ao-cec.txt28
-rw-r--r--Bindings/media/mtk-cir.txt8
-rw-r--r--Bindings/media/pxa-camera.txt1
-rw-r--r--Bindings/media/qcom,camss.txt197
-rw-r--r--Bindings/media/renesas,drif.txt1
-rw-r--r--Bindings/media/s5p-cec.txt1
-rw-r--r--Bindings/media/samsung-fimc.txt2
-rw-r--r--Bindings/media/stih407-c8sectpfe.txt1
-rw-r--r--Bindings/media/ti,da850-vpif.txt1
-rw-r--r--Bindings/media/video-interfaces.txt8
-rw-r--r--Bindings/media/zx-irdec.txt14
-rw-r--r--Bindings/memory-controllers/mediatek,smi-larb.txt15
-rw-r--r--Bindings/memory-controllers/mvebu-devbus.txt1
-rw-r--r--Bindings/mfd/act8945a.txt2
-rw-r--r--Bindings/mfd/atmel-hlcdc.txt1
-rw-r--r--Bindings/mfd/atmel-smc.txt1
-rw-r--r--Bindings/mfd/axp20x.txt50
-rw-r--r--Bindings/mfd/bd9571mwv.txt49
-rw-r--r--Bindings/mfd/da9052-i2c.txt9
-rw-r--r--Bindings/mfd/mc13xxx.txt1
-rw-r--r--Bindings/mfd/mxs-lradc.txt2
-rw-r--r--Bindings/mfd/retu.txt25
-rw-r--r--Bindings/mfd/rk808.txt22
-rw-r--r--Bindings/mfd/samsung,exynos5433-lpass.txt2
-rw-r--r--Bindings/mfd/stm32-lptimer.txt48
-rw-r--r--Bindings/mfd/tps6105x.txt17
-rw-r--r--Bindings/mfd/wm831x.txt1
-rw-r--r--Bindings/mfd/zii,rave-sp.txt39
-rw-r--r--Bindings/mips/lantiq/fpi-bus.txt31
-rw-r--r--Bindings/mips/lantiq/rcu-gphy.txt36
-rw-r--r--Bindings/mips/lantiq/rcu.txt89
-rw-r--r--Bindings/mips/ni.txt7
-rw-r--r--Bindings/mips/ralink.txt1
-rw-r--r--Bindings/misc/atmel-ssc.txt1
-rw-r--r--Bindings/mmc/arasan,sdhci.txt1
-rw-r--r--Bindings/mmc/davinci_mmc.txt1
-rw-r--r--Bindings/mmc/fsl-imx-mmc.txt1
-rw-r--r--Bindings/mmc/marvell,xenon-sdhci.txt12
-rw-r--r--Bindings/mmc/mmc-card.txt1
-rw-r--r--Bindings/mmc/mmc.txt1
-rw-r--r--Bindings/mmc/orion-sdio.txt1
-rw-r--r--Bindings/mmc/renesas,mmcif.txt4
-rw-r--r--Bindings/mmc/rockchip-dw-mshc.txt1
-rw-r--r--Bindings/mmc/sdhci-st.txt3
-rw-r--r--Bindings/mmc/sunxi-mmc.txt1
-rw-r--r--Bindings/mmc/ti-omap-hsmmc.txt52
-rw-r--r--Bindings/mmc/tmio_mmc.txt8
-rw-r--r--Bindings/mmc/zx-dw-mshc.txt1
-rw-r--r--Bindings/mtd/atmel-quadspi.txt1
-rw-r--r--Bindings/mtd/mtk-quadspi.txt1
-rw-r--r--Bindings/mtd/qcom_nandc.txt65
-rw-r--r--Bindings/mtd/st-fsm.txt1
-rw-r--r--Bindings/mtd/sunxi-nand.txt1
-rw-r--r--Bindings/net/anarion-gmac.txt25
-rw-r--r--Bindings/net/brcm,amac.txt1
-rw-r--r--Bindings/net/broadcom-bluetooth.txt35
-rw-r--r--Bindings/net/btusb.txt1
-rw-r--r--Bindings/net/can/c_can.txt13
-rw-r--r--Bindings/net/can/m_can.txt1
-rw-r--r--Bindings/net/dsa/ksz.txt2
-rw-r--r--Bindings/net/dsa/lan9303.txt3
-rw-r--r--Bindings/net/ethernet.txt4
-rw-r--r--Bindings/net/ftgmac100.txt1
-rw-r--r--Bindings/net/marvell-armada-370-neta.txt1
-rw-r--r--Bindings/net/marvell-bt-8xxx.txt2
-rw-r--r--Bindings/net/marvell-neta-bm.txt2
-rw-r--r--Bindings/net/marvell-pp2.txt42
-rw-r--r--Bindings/net/mediatek-net.txt18
-rw-r--r--Bindings/net/meson-dwmac.txt1
-rw-r--r--Bindings/net/micrel-ksz90x1.txt1
-rw-r--r--Bindings/net/microchip,enc28j60.txt1
-rw-r--r--Bindings/net/nfc/nfcmrvl.txt2
-rw-r--r--Bindings/net/nfc/nxp-nci.txt1
-rw-r--r--Bindings/net/nfc/pn533-i2c.txt1
-rw-r--r--Bindings/net/nfc/pn544.txt1
-rw-r--r--Bindings/net/nfc/s3fwrn5.txt1
-rw-r--r--Bindings/net/nfc/st-nci-i2c.txt1
-rw-r--r--Bindings/net/nfc/st-nci-spi.txt1
-rw-r--r--Bindings/net/nfc/st21nfca.txt1
-rw-r--r--Bindings/net/nfc/st95hf.txt2
-rw-r--r--Bindings/net/nfc/trf7970a.txt2
-rw-r--r--Bindings/net/oxnas-dwmac.txt1
-rw-r--r--Bindings/net/phy.txt15
-rw-r--r--Bindings/net/qca,qca7000.txt2
-rw-r--r--Bindings/net/renesas,ravb.txt30
-rw-r--r--Bindings/net/rockchip-dwmac.txt3
-rw-r--r--Bindings/net/sff,sfp.txt76
-rw-r--r--Bindings/net/smsc-lan87xx.txt1
-rw-r--r--Bindings/net/socfpga-dwmac.txt1
-rw-r--r--Bindings/net/sti-dwmac.txt1
-rw-r--r--Bindings/net/stm32-dwmac.txt1
-rw-r--r--Bindings/net/wireless/brcm,bcm43xx-fmac.txt1
-rw-r--r--Bindings/net/wireless/esp,esp8089.txt1
-rw-r--r--Bindings/net/wireless/marvell-8xxx.txt1
-rw-r--r--Bindings/net/wireless/ti,wlcore.txt1
-rw-r--r--Bindings/net/xilinx_axienet.txt55
-rw-r--r--Bindings/nvmem/mtk-efuse.txt5
-rw-r--r--Bindings/nvmem/mxs-ocotp.txt1
-rw-r--r--Bindings/opp/opp.txt1
-rw-r--r--Bindings/pci/83xx-512x-pci.txt6
-rw-r--r--Bindings/pci/aardvark-pci.txt1
-rw-r--r--Bindings/pci/altera-pcie.txt18
-rw-r--r--Bindings/pci/axis,artpec6-pcie.txt2
-rw-r--r--Bindings/pci/designware-pcie.txt24
-rw-r--r--Bindings/pci/fsl,imx6q-pcie.txt2
-rw-r--r--Bindings/pci/hisilicon-pcie.txt6
-rw-r--r--Bindings/pci/kirin-pcie.txt8
-rw-r--r--Bindings/pci/layerscape-pci.txt4
-rw-r--r--Bindings/pci/mediatek,mt7623-pcie.txt130
-rw-r--r--Bindings/pci/mediatek-pcie.txt284
-rw-r--r--Bindings/pci/mvebu-pci.txt15
-rw-r--r--Bindings/pci/pci-armada8k.txt3
-rw-r--r--Bindings/pci/pci-keystone.txt15
-rw-r--r--Bindings/pci/pci-rcar-gen2.txt7
-rw-r--r--Bindings/pci/pci.txt4
-rw-r--r--Bindings/pci/qcom,pcie.txt27
-rw-r--r--Bindings/pci/ralink,rt3883-pci.txt2
-rw-r--r--Bindings/pci/rcar-pci.txt8
-rw-r--r--Bindings/pci/rockchip-pcie.txt28
-rw-r--r--Bindings/pci/samsung,exynos5440-pcie.txt22
-rw-r--r--Bindings/pci/spear13xx-pcie.txt6
-rw-r--r--Bindings/pci/ti-pci.txt8
-rw-r--r--Bindings/pci/versatile.txt2
-rw-r--r--Bindings/pci/xgene-pci-msi.txt6
-rw-r--r--Bindings/pci/xgene-pci.txt8
-rw-r--r--Bindings/pci/xilinx-nwl-pcie.txt7
-rw-r--r--Bindings/phy/apm-xgene-phy.txt3
-rw-r--r--Bindings/phy/keystone-usb-phy.txt1
-rw-r--r--Bindings/phy/phy-bindings.txt4
-rw-r--r--Bindings/phy/phy-lantiq-rcu-usb2.txt40
-rw-r--r--Bindings/phy/phy-mtk-tphy.txt (renamed from Bindings/phy/phy-mt65xx-usb.txt)21
-rw-r--r--Bindings/phy/phy-mvebu-comphy.txt43
-rw-r--r--Bindings/phy/phy-mvebu.txt1
-rw-r--r--Bindings/phy/phy-rockchip-inno-usb2.txt13
-rw-r--r--Bindings/phy/qcom-dwc3-usb-phy.txt2
-rw-r--r--Bindings/phy/qcom-qmp-phy.txt11
-rw-r--r--Bindings/phy/ralink-usb-phy.txt23
-rw-r--r--Bindings/phy/rockchip-pcie-phy.txt7
-rw-r--r--Bindings/phy/samsung-phy.txt1
-rw-r--r--Bindings/phy/sun4i-usb-phy.txt10
-rw-r--r--Bindings/phy/sun9i-usb-phy.txt1
-rw-r--r--Bindings/pinctrl/atmel,at91-pinctrl.txt1
-rw-r--r--Bindings/pinctrl/cortina,gemini-pinctrl.txt59
-rw-r--r--Bindings/pinctrl/fsl,imx-pinctrl.txt1
-rw-r--r--Bindings/pinctrl/fsl,imx7d-pinctrl.txt1
-rw-r--r--Bindings/pinctrl/fsl,imx7ulp-pinctrl.txt61
-rw-r--r--Bindings/pinctrl/nvidia,tegra124-dpaux-padctl.txt1
-rw-r--r--Bindings/pinctrl/oxnas,pinctrl.txt1
-rw-r--r--Bindings/pinctrl/pinctrl-aspeed.txt8
-rw-r--r--Bindings/pinctrl/pinctrl-bindings.txt2
-rw-r--r--Bindings/pinctrl/pinctrl-mt65xx.txt1
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-rw-r--r--Bindings/pinctrl/pinctrl-zx.txt1
-rw-r--r--Bindings/pinctrl/qcom,apq8064-pinctrl.txt3
-rw-r--r--Bindings/pinctrl/qcom,ipq4019-pinctrl.txt6
-rw-r--r--Bindings/pinctrl/qcom,pmic-gpio.txt26
-rw-r--r--Bindings/pinctrl/renesas,pfc-pinctrl.txt4
-rw-r--r--Bindings/pinctrl/rockchip,pinctrl.txt2
-rw-r--r--Bindings/pinctrl/sprd,pinctrl.txt83
-rw-r--r--Bindings/pinctrl/sprd,sc9860-pinctrl.txt70
-rw-r--r--Bindings/pinctrl/st,stm32-pinctrl.txt1
-rw-r--r--Bindings/power/power-controller.txt1
-rw-r--r--Bindings/power/renesas,apmu.txt3
-rw-r--r--Bindings/power/renesas,rcar-sysc.txt1
-rw-r--r--Bindings/power/reset/st-reset.txt1
-rw-r--r--Bindings/power/rockchip-io-domain.txt2
-rw-r--r--Bindings/power/supply/act8945a-charger.txt2
-rw-r--r--Bindings/power/supply/bq24190.txt51
-rw-r--r--Bindings/power/supply/ltc2941.txt15
-rw-r--r--Bindings/power/supply/max8903-charger.txt1
-rw-r--r--Bindings/power/supply/maxim,max14656.txt1
-rw-r--r--Bindings/power/wakeup-source.txt9
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-rw-r--r--Bindings/powerpc/opal/sensor-groups.txt27
-rw-r--r--Bindings/pps/pps-gpio.txt8
-rw-r--r--Bindings/ptp/brcm,ptp-dte.txt1
-rw-r--r--Bindings/pwm/pwm-bcm2835.txt4
-rw-r--r--Bindings/pwm/pwm-mediatek.txt6
-rw-r--r--Bindings/pwm/pwm-meson.txt1
-rw-r--r--Bindings/pwm/pwm-rockchip.txt11
-rw-r--r--Bindings/pwm/pwm-stm32-lp.txt24
-rw-r--r--Bindings/pwm/pwm-sun4i.txt1
-rw-r--r--Bindings/pwm/pwm-tiecap.txt1
-rw-r--r--Bindings/pwm/pwm-tipwmss.txt2
-rw-r--r--Bindings/pwm/pwm-zx.txt22
-rw-r--r--Bindings/pwm/renesas,tpu-pwm.txt1
-rw-r--r--Bindings/regulator/act8865-regulator.txt1
-rw-r--r--Bindings/regulator/act8945a-regulator.txt1
-rw-r--r--Bindings/regulator/mt6311-regulator.txt2
-rw-r--r--Bindings/regulator/mt6323-regulator.txt2
-rw-r--r--Bindings/regulator/mt6380-regulator.txt89
-rw-r--r--Bindings/regulator/mt6397-regulator.txt2
-rw-r--r--Bindings/regulator/pwm-regulator.txt2
-rw-r--r--Bindings/regulator/st,stm32-vrefbuf.txt20
-rw-r--r--Bindings/remoteproc/imx-rproc.txt33
-rw-r--r--Bindings/remoteproc/qcom,adsp.txt7
-rw-r--r--Bindings/remoteproc/qcom,q6v5.txt5
-rw-r--r--Bindings/remoteproc/ti,davinci-rproc.txt86
-rw-r--r--Bindings/remoteproc/ti,keystone-rproc.txt73
-rw-r--r--Bindings/reset/lantiq,reset.txt30
-rw-r--r--Bindings/reset/nxp,lpc1850-rgu.txt1
-rw-r--r--Bindings/reset/renesas,rst.txt1
-rw-r--r--Bindings/reset/snps,hsdk-reset.txt28
-rw-r--r--Bindings/reset/uniphier-reset.txt27
-rw-r--r--Bindings/rng/imx-rngc.txt21
-rw-r--r--Bindings/rtc/google,goldfish-rtc.txt17
-rw-r--r--Bindings/rtc/isil,isl12057.txt1
-rw-r--r--Bindings/rtc/realtek,rtd119x.txt16
-rw-r--r--Bindings/rtc/st,stm32-rtc.txt1
-rw-r--r--Bindings/rtc/sun6i-rtc.txt4
-rw-r--r--Bindings/scsi/hisilicon-sas.txt1
-rw-r--r--Bindings/security/tpm/st33zp24-i2c.txt1
-rw-r--r--Bindings/security/tpm/st33zp24-spi.txt1
-rw-r--r--Bindings/security/tpm/tpm-i2c.txt7
-rw-r--r--Bindings/security/tpm/tpm_tis_spi.txt1
-rw-r--r--Bindings/serial/8250.txt2
-rw-r--r--Bindings/serial/arc-uart.txt1
-rw-r--r--Bindings/serial/axis,etraxfs-uart.txt1
-rw-r--r--Bindings/serial/mtk-uart.txt1
-rw-r--r--Bindings/serial/nvidia,tegra20-hsuart.txt1
-rw-r--r--Bindings/serial/qcom,msm-uartdm.txt3
-rw-r--r--Bindings/serial/renesas,sci-serial.txt4
-rw-r--r--Bindings/serial/rs485.txt5
-rw-r--r--Bindings/serial/serial.txt2
-rw-r--r--Bindings/serial/st,stm32-usart.txt17
-rw-r--r--Bindings/serio/allwinner,sun4i-ps2.txt1
-rw-r--r--Bindings/serio/ps2-gpio.txt23
-rw-r--r--Bindings/soc/mediatek/scpsys.txt3
-rw-r--r--Bindings/soc/qcom/qcom,glink.txt13
-rw-r--r--Bindings/soc/qcom/qcom,gsbi.txt1
-rw-r--r--Bindings/soc/rockchip/grf.txt3
-rw-r--r--Bindings/soc/rockchip/power_domain.txt3
-rw-r--r--Bindings/soc/ti/sci-pm-domain.txt5
-rw-r--r--Bindings/sound/armada-370db-audio.txt1
-rw-r--r--Bindings/sound/atmel-classd.txt9
-rw-r--r--Bindings/sound/axentia,tse850-pcm5142.txt1
-rw-r--r--Bindings/sound/brcm,cygnus-audio.txt4
-rw-r--r--Bindings/sound/cs43130.txt67
-rw-r--r--Bindings/sound/davinci-mcbsp.txt1
-rw-r--r--Bindings/sound/dmic.txt16
-rw-r--r--Bindings/sound/fsl,asrc.txt1
-rw-r--r--Bindings/sound/fsl,esai.txt1
-rw-r--r--Bindings/sound/fsl,spdif.txt1
-rw-r--r--Bindings/sound/hdmi.txt1
-rw-r--r--Bindings/sound/mt2701-afe-pcm.txt4
-rw-r--r--Bindings/sound/qcom,msm8916-wcd-analog.txt18
-rw-r--r--Bindings/sound/renesas,rsnd.txt70
-rw-r--r--Bindings/sound/rockchip,pdm.txt8
-rw-r--r--Bindings/sound/rockchip,rk3399-gru-sound.txt2
-rw-r--r--Bindings/sound/rockchip-i2s.txt4
-rw-r--r--Bindings/sound/rockchip-spdif.txt1
-rw-r--r--Bindings/sound/rt274.txt33
-rw-r--r--Bindings/sound/rt5663.txt8
-rw-r--r--Bindings/sound/samsung,odroid.txt6
-rw-r--r--Bindings/sound/simple-card.txt3
-rw-r--r--Bindings/sound/simple-scu-card.txt1
-rw-r--r--Bindings/sound/st,sti-asoc-card.txt5
-rw-r--r--Bindings/sound/sun4i-i2s.txt2
-rw-r--r--Bindings/sound/sunxi,sun4i-spdif.txt1
-rw-r--r--Bindings/sound/tas5720.txt1
-rw-r--r--Bindings/sound/tlv320aic32x4.txt13
-rw-r--r--Bindings/sound/tlv320aic3x.txt5
-rw-r--r--Bindings/sound/wm8524.txt16
-rw-r--r--Bindings/sound/zte,zx-i2s.txt1
-rw-r--r--Bindings/sound/zte,zx-spdif.txt1
-rw-r--r--Bindings/spi/efm32-spi.txt2
-rw-r--r--Bindings/spi/fsl-imx-cspi.txt1
-rw-r--r--Bindings/spi/nvidia,tegra114-spi.txt1
-rw-r--r--Bindings/spi/nvidia,tegra20-sflash.txt1
-rw-r--r--Bindings/spi/nvidia,tegra20-slink.txt1
-rw-r--r--Bindings/spi/sh-hspi.txt1
-rw-r--r--Bindings/spi/sh-msiof.txt2
-rw-r--r--Bindings/spi/spi-clps711x.txt1
-rw-r--r--Bindings/spi/spi-fsl-dspi.txt1
-rw-r--r--Bindings/spi/spi-mt65xx.txt1
-rw-r--r--Bindings/spi/spi-orion.txt2
-rw-r--r--Bindings/spi/spi-rockchip.txt1
-rw-r--r--Bindings/spi/spi-sun4i.txt1
-rw-r--r--Bindings/spi/spi-sun6i.txt1
-rw-r--r--Bindings/spi/spi_atmel.txt1
-rw-r--r--Bindings/sram/renesas,smp-sram.txt27
-rw-r--r--Bindings/sram/sunxi-sram.txt10
-rw-r--r--Bindings/thermal/armada-thermal.txt1
-rw-r--r--Bindings/thermal/exynos-thermal.txt1
-rw-r--r--Bindings/thermal/mediatek-thermal.txt1
-rw-r--r--Bindings/thermal/rcar-gen3-thermal.txt1
-rw-r--r--Bindings/thermal/rockchip-thermal.txt1
-rw-r--r--Bindings/thermal/uniphier-thermal.txt64
-rw-r--r--Bindings/timer/nxp,tpm-timer.txt28
-rw-r--r--Bindings/timer/renesas,cmt.txt73
-rw-r--r--Bindings/trivial-devices.txt14
-rw-r--r--Bindings/unittest.txt5
-rw-r--r--Bindings/usb/allwinner,sun4i-a10-musb.txt1
-rw-r--r--Bindings/usb/am33xx-usb.txt4
-rw-r--r--Bindings/usb/brcm,bdc.txt29
-rw-r--r--Bindings/usb/da8xx-usb.txt2
-rw-r--r--Bindings/usb/dwc3-st.txt1
-rw-r--r--Bindings/usb/dwc3-xilinx.txt1
-rw-r--r--Bindings/usb/ehci-st.txt1
-rw-r--r--Bindings/usb/exynos-usb.txt2
-rw-r--r--Bindings/usb/fcs,fusb302.txt29
-rw-r--r--Bindings/usb/isp1301.txt1
-rw-r--r--Bindings/usb/keystone-usb.txt18
-rw-r--r--Bindings/usb/mediatek,mtk-xhci.txt (renamed from Bindings/usb/mt8173-xhci.txt)14
-rw-r--r--Bindings/usb/mediatek,mtu3.txt (renamed from Bindings/usb/mt8173-mtu3.txt)10
-rw-r--r--Bindings/usb/ohci-st.txt1
-rw-r--r--Bindings/usb/qcom,dwc3.txt3
-rw-r--r--Bindings/usb/renesas_usb3.txt16
-rw-r--r--Bindings/usb/rockchip,dwc3.txt4
-rw-r--r--Bindings/usb/usb-device.txt3
-rw-r--r--Bindings/vendor-prefixes.txt13
-rw-r--r--Bindings/w1/fsl-imx-owire.txt1
-rw-r--r--Bindings/watchdog/aspeed-wdt.txt40
-rw-r--r--Bindings/watchdog/atmel-sama5d4-wdt.txt1
-rw-r--r--Bindings/watchdog/atmel-wdt.txt1
-rw-r--r--Bindings/watchdog/lantiq-wdt.txt24
-rw-r--r--Bindings/watchdog/marvel.txt1
-rw-r--r--Bindings/watchdog/meson-wdt.txt6
-rw-r--r--Bindings/watchdog/mtk-wdt.txt8
-rw-r--r--Bindings/watchdog/renesas-wdt.txt1
-rw-r--r--Bindings/xilinx.txt2
-rw-r--r--include/dt-bindings/clock/berlin2.h1
-rw-r--r--include/dt-bindings/clock/berlin2q.h1
-rw-r--r--include/dt-bindings/clock/cortina,gemini-clock.h1
-rw-r--r--include/dt-bindings/clock/efm32-cmu.h1
-rw-r--r--include/dt-bindings/clock/exynos-audss-clk.h1
-rw-r--r--include/dt-bindings/clock/gxbb-aoclkc.h1
-rw-r--r--include/dt-bindings/clock/gxbb-clkc.h64
-rw-r--r--include/dt-bindings/clock/jz4740-cgu.h1
-rw-r--r--include/dt-bindings/clock/jz4780-cgu.h1
-rw-r--r--include/dt-bindings/clock/marvell,mmp2.h1
-rw-r--r--include/dt-bindings/clock/marvell,pxa168.h1
-rw-r--r--include/dt-bindings/clock/marvell,pxa1928.h1
-rw-r--r--include/dt-bindings/clock/marvell,pxa910.h1
-rw-r--r--include/dt-bindings/clock/meson8b-clkc.h71
-rw-r--r--include/dt-bindings/clock/mpc512x-clock.h1
-rw-r--r--include/dt-bindings/clock/qcom,gcc-msm8996.h2
-rw-r--r--include/dt-bindings/clock/r8a77995-cpg-mssr.h57
-rw-r--r--include/dt-bindings/clock/rk3228-cru.h1
-rw-r--r--include/dt-bindings/clock/rockchip,rk808.h1
-rw-r--r--include/dt-bindings/clock/rv1108-cru.h125
-rw-r--r--include/dt-bindings/clock/ste-ab8500.h1
-rw-r--r--include/dt-bindings/clock/stih407-clks.h1
-rw-r--r--include/dt-bindings/clock/stih410-clks.h1
-rw-r--r--include/dt-bindings/clock/stih416-clks.h1
-rw-r--r--include/dt-bindings/clock/stih418-clks.h1
-rw-r--r--include/dt-bindings/clock/stm32h7-clks.h165
-rw-r--r--include/dt-bindings/clock/sun4i-a10-ccu.h200
-rw-r--r--include/dt-bindings/clock/sun7i-a20-ccu.h53
-rw-r--r--include/dt-bindings/clock/sun8i-r40-ccu.h187
-rw-r--r--include/dt-bindings/clock/tegra114-car.h1
-rw-r--r--include/dt-bindings/clock/tegra124-car-common.h1
-rw-r--r--include/dt-bindings/clock/tegra124-car.h1
-rw-r--r--include/dt-bindings/clock/tegra186-clock.h1
-rw-r--r--include/dt-bindings/clock/tegra20-car.h1
-rw-r--r--include/dt-bindings/clock/tegra210-car.h1
-rw-r--r--include/dt-bindings/clock/tegra30-car.h1
-rw-r--r--include/dt-bindings/display/tda998x.h1
-rw-r--r--include/dt-bindings/genpd/k2g.h90
-rw-r--r--include/dt-bindings/gpio/gpio.h1
-rw-r--r--include/dt-bindings/gpio/tegra-gpio.h1
-rw-r--r--include/dt-bindings/gpio/tegra186-gpio.h1
-rw-r--r--include/dt-bindings/iio/adc/fsl-imx25-gcq.h1
-rw-r--r--include/dt-bindings/iio/adi,ad5592r.h1
-rw-r--r--include/dt-bindings/input/input.h1
-rw-r--r--include/dt-bindings/input/linux-event-codes.h1
-rw-r--r--include/dt-bindings/interrupt-controller/arm-gic.h1
-rw-r--r--include/dt-bindings/interrupt-controller/irq.h1
-rw-r--r--include/dt-bindings/interrupt-controller/mips-gic.h1
-rw-r--r--include/dt-bindings/interrupt-controller/mvebu-icu.h1
-rw-r--r--include/dt-bindings/leds/common.h1
-rw-r--r--include/dt-bindings/leds/leds-ns2.h1
-rw-r--r--include/dt-bindings/leds/leds-pca955x.h16
-rw-r--r--include/dt-bindings/mailbox/tegra186-hsp.h1
-rw-r--r--include/dt-bindings/media/c8sectpfe.h1
-rw-r--r--include/dt-bindings/memory/mt8173-larb-port.h4
-rw-r--r--include/dt-bindings/memory/tegra114-mc.h1
-rw-r--r--include/dt-bindings/memory/tegra124-mc.h1
-rw-r--r--include/dt-bindings/memory/tegra210-mc.h1
-rw-r--r--include/dt-bindings/memory/tegra30-mc.h1
-rw-r--r--include/dt-bindings/mfd/as3722.h1
-rw-r--r--include/dt-bindings/mfd/dbx500-prcmu.h1
-rw-r--r--include/dt-bindings/mfd/max77620.h1
-rw-r--r--include/dt-bindings/mfd/palmas.h1
-rw-r--r--include/dt-bindings/mfd/qcom-rpm.h1
-rw-r--r--include/dt-bindings/mfd/st-lpc.h1
-rw-r--r--include/dt-bindings/mfd/stm32f4-rcc.h1
-rw-r--r--include/dt-bindings/mfd/stm32f7-rcc.h1
-rw-r--r--include/dt-bindings/mfd/stm32h7-rcc.h136
-rw-r--r--include/dt-bindings/mips/lantiq_rcu_gphy.h15
-rw-r--r--include/dt-bindings/mux/mux.h1
-rw-r--r--include/dt-bindings/pinctrl/am33xx.h1
-rw-r--r--include/dt-bindings/pinctrl/am43xx.h1
-rw-r--r--include/dt-bindings/pinctrl/dm814x.h1
-rw-r--r--include/dt-bindings/pinctrl/dra.h3
-rw-r--r--include/dt-bindings/pinctrl/mt6397-pinfunc.h1
-rw-r--r--include/dt-bindings/pinctrl/mt7623-pinfunc.h1
-rw-r--r--include/dt-bindings/pinctrl/omap.h1
-rw-r--r--include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h1
-rw-r--r--include/dt-bindings/pinctrl/qcom,pmic-gpio.h3
-rw-r--r--include/dt-bindings/pinctrl/qcom,pmic-mpp.h1
-rw-r--r--include/dt-bindings/pinctrl/r7s72100-pinctrl.h1
-rw-r--r--include/dt-bindings/pinctrl/samsung.h3
-rw-r--r--include/dt-bindings/pinctrl/stm32f429-pinfunc.h1
-rw-r--r--include/dt-bindings/pinctrl/stm32f746-pinfunc.h1
-rw-r--r--include/dt-bindings/pinctrl/stm32h7-pinfunc.h1
-rw-r--r--include/dt-bindings/power/mt7622-power.h22
-rw-r--r--include/dt-bindings/power/mt8173-power.h1
-rw-r--r--include/dt-bindings/power/r8a77995-sysc.h23
-rw-r--r--include/dt-bindings/power/rk3288-power.h1
-rw-r--r--include/dt-bindings/power/rk3328-power.h1
-rw-r--r--include/dt-bindings/power/rk3366-power.h24
-rw-r--r--include/dt-bindings/power/rk3368-power.h1
-rw-r--r--include/dt-bindings/power/rk3399-power.h1
-rw-r--r--include/dt-bindings/pwm/pwm.h1
-rw-r--r--include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h27
-rw-r--r--include/dt-bindings/reset/cortina,gemini-reset.h1
-rw-r--r--include/dt-bindings/reset/hisi,hi6220-resets.h1
-rw-r--r--include/dt-bindings/reset/pistachio-resets.h1
-rw-r--r--include/dt-bindings/reset/snps,hsdk-reset.h17
-rw-r--r--include/dt-bindings/reset/stih407-resets.h1
-rw-r--r--include/dt-bindings/reset/stih415-resets.h1
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-rw-r--r--include/dt-bindings/reset/sun4i-a10-ccu.h69
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-rw-r--r--include/dt-bindings/reset/tegra124-car.h1
-rw-r--r--include/dt-bindings/reset/tegra210-car.h1
-rw-r--r--include/dt-bindings/soc/rockchip,boot-mode.h1
-rw-r--r--include/dt-bindings/sound/apq8016-lpass.h1
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-rw-r--r--include/dt-bindings/sound/cs35l32.h1
-rw-r--r--include/dt-bindings/sound/fsl-imx-audmux.h1
-rw-r--r--include/dt-bindings/sound/samsung-i2s.h1
-rw-r--r--include/dt-bindings/sound/tas2552.h1
-rw-r--r--include/dt-bindings/sound/tlv320aic31xx-micbias.h1
-rw-r--r--include/dt-bindings/thermal/lm90.h1
-rw-r--r--include/dt-bindings/thermal/tegra124-soctherm.h1
-rwxr-xr-xscripts/cronjob14
-rwxr-xr-xscripts/filter.sh3
-rwxr-xr-xscripts/flatten-symlinks.sh31
-rwxr-xr-xscripts/git-filter-branch557
-rwxr-xr-xscripts/index-filter.sh6
-rwxr-xr-xscripts/merge-new-release.sh30
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-rw-r--r--src/arc/axc001.dtsi2
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-rw-r--r--src/arc/axs10x_mb.dtsi10
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-rw-r--r--src/arc/nsim_hs.dts2
-rw-r--r--src/arc/vdk_axs10x_mb.dtsi1
-rw-r--r--src/arm/am335x-bone-common.dtsi3
-rw-r--r--src/arm/am335x-chiliboard.dts3
-rw-r--r--src/arm/am335x-evm.dts1
-rw-r--r--src/arm/am335x-moxa-uc-8100-me-t.dts525
-rw-r--r--src/arm/am33xx.dtsi2
-rw-r--r--src/arm/am437x-gp-evm.dts15
-rw-r--r--src/arm/am43x-epos-evm.dts7
-rw-r--r--src/arm/am571x-idk.dts35
-rw-r--r--src/arm/am572x-idk.dts34
-rw-r--r--src/arm/am57xx-beagle-x15-common.dtsi36
-rw-r--r--src/arm/am57xx-beagle-x15-revb1.dts17
-rw-r--r--src/arm/am57xx-beagle-x15-revc.dts39
-rw-r--r--src/arm/am57xx-beagle-x15.dts11
-rw-r--r--src/arm/am57xx-commercial-grade.dtsi1
-rw-r--r--src/arm/am57xx-idk-common.dtsi8
-rw-r--r--src/arm/am57xx-industrial-grade.dtsi1
-rw-r--r--src/arm/armada-370.dtsi4
-rw-r--r--src/arm/armada-375.dtsi8
-rw-r--r--src/arm/armada-380.dtsi5
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-rw-r--r--src/arm64/socionext/uniphier-ld11-global.dts6
-rw-r--r--src/arm64/socionext/uniphier-ld11-ref.dts6
-rw-r--r--src/arm64/socionext/uniphier-ld11.dtsi44
-rw-r--r--src/arm64/socionext/uniphier-ld20-global.dts6
-rw-r--r--src/arm64/socionext/uniphier-ld20-ref.dts6
-rw-r--r--src/arm64/socionext/uniphier-ld20.dtsi37
-rw-r--r--src/arm64/socionext/uniphier-pinctrl.dtsi142
-rw-r--r--src/arm64/socionext/uniphier-pxs3-ref.dts62
-rw-r--r--src/arm64/socionext/uniphier-pxs3.dtsi367
-rw-r--r--src/arm64/socionext/uniphier-ref-daughter.dtsi17
-rw-r--r--src/arm64/socionext/uniphier-support-card.dtsi35
-rw-r--r--src/arm64/xilinx/zynqmp-ep108-clk.dtsi50
-rw-r--r--src/arm64/xilinx/zynqmp-ep108.dts18
-rw-r--r--src/arm64/xilinx/zynqmp.dtsi277
-rw-r--r--src/arm64/zte/zx296718-evb.dts68
-rw-r--r--src/arm64/zte/zx296718-pcbox.dts143
-rw-r--r--src/arm64/zte/zx296718.dtsi171
-rw-r--r--src/c6x/tms320c6455.dtsi1
-rw-r--r--src/c6x/tms320c6457.dtsi1
-rw-r--r--src/c6x/tms320c6472.dtsi1
-rw-r--r--src/c6x/tms320c6474.dtsi1
-rw-r--r--src/c6x/tms320c6678.dtsi1
-rw-r--r--src/cris/artpec3.dtsi1
-rw-r--r--src/cris/dev88.dts1
-rw-r--r--src/cris/etraxfs.dtsi1
-rw-r--r--src/cris/p1343.dts1
-rw-r--r--src/h8300/edosk2674.dts1
-rw-r--r--src/h8300/h8300h_sim.dts1
-rw-r--r--src/h8300/h8s_sim.dts1
-rw-r--r--src/metag/skeleton.dtsi1
-rw-r--r--src/mips/brcm/bcm3368-netgear-cvg834g.dts1
-rw-r--r--src/mips/brcm/bcm3368.dtsi1
-rw-r--r--src/mips/brcm/bcm3384_viper.dtsi1
-rw-r--r--src/mips/brcm/bcm3384_zephyr.dtsi1
-rw-r--r--src/mips/brcm/bcm63268-comtrend-vr-3032u.dts1
-rw-r--r--src/mips/brcm/bcm63268.dtsi1
-rw-r--r--src/mips/brcm/bcm6328.dtsi1
-rw-r--r--src/mips/brcm/bcm6358-neufbox4-sercomm.dts1
-rw-r--r--src/mips/brcm/bcm6358.dtsi1
-rw-r--r--src/mips/brcm/bcm6362-neufbox6-sercomm.dts1
-rw-r--r--src/mips/brcm/bcm6362.dtsi1
-rw-r--r--src/mips/brcm/bcm6368.dtsi1
-rw-r--r--src/mips/brcm/bcm7125.dtsi1
-rw-r--r--src/mips/brcm/bcm7346.dtsi1
-rw-r--r--src/mips/brcm/bcm7358.dtsi1
-rw-r--r--src/mips/brcm/bcm7360.dtsi1
-rw-r--r--src/mips/brcm/bcm7362.dtsi1
-rw-r--r--src/mips/brcm/bcm7420.dtsi1
-rw-r--r--src/mips/brcm/bcm7425.dtsi1
-rw-r--r--src/mips/brcm/bcm7435.dtsi1
-rw-r--r--src/mips/brcm/bcm93384wvg.dts1
-rw-r--r--src/mips/brcm/bcm93384wvg_viper.dts1
-rw-r--r--src/mips/brcm/bcm96368mvwg.dts1
-rw-r--r--src/mips/brcm/bcm97125cbmb.dts1
-rw-r--r--src/mips/brcm/bcm97346dbsmb.dts1
-rw-r--r--src/mips/brcm/bcm97358svmb.dts1
-rw-r--r--src/mips/brcm/bcm97360svmb.dts1
-rw-r--r--src/mips/brcm/bcm97362svmb.dts1
-rw-r--r--src/mips/brcm/bcm97420c.dts1
-rw-r--r--src/mips/brcm/bcm97425svmb.dts1
-rw-r--r--src/mips/brcm/bcm97435svmb.dts1
-rw-r--r--src/mips/brcm/bcm97xxx-nand-cs1-bch24.dtsi1
-rw-r--r--src/mips/brcm/bcm97xxx-nand-cs1-bch4.dtsi1
-rw-r--r--src/mips/brcm/bcm9ejtagprb.dts1
-rw-r--r--src/mips/cavium-octeon/octeon_3xxx.dts1
-rw-r--r--src/mips/cavium-octeon/octeon_3xxx.dtsi1
-rw-r--r--src/mips/cavium-octeon/octeon_68xx.dts1
-rw-r--r--src/mips/img/boston.dts1
-rw-r--r--src/mips/ingenic/ci20.dts38
-rw-r--r--src/mips/ingenic/jz4740.dtsi1
-rw-r--r--src/mips/ingenic/jz4780.dtsi12
-rw-r--r--src/mips/ingenic/qi_lb60.dts1
-rw-r--r--src/mips/lantiq/danube.dtsi1
-rw-r--r--src/mips/lantiq/easy50712.dts1
-rw-r--r--src/mips/mti/malta.dts1
-rw-r--r--src/mips/mti/sead3.dts1
-rw-r--r--src/mips/netlogic/xlp_evp.dts1
-rw-r--r--src/mips/netlogic/xlp_fvp.dts1
-rw-r--r--src/mips/netlogic/xlp_gvp.dts1
-rw-r--r--src/mips/netlogic/xlp_rvp.dts1
-rw-r--r--src/mips/netlogic/xlp_svp.dts1
-rw-r--r--src/mips/ni/169445.dts100
-rw-r--r--src/mips/qca/ar9132.dtsi1
-rw-r--r--src/mips/qca/ar9132_tl_wr1043nd_v1.dts1
-rw-r--r--src/mips/qca/ar9331.dtsi1
-rw-r--r--src/mips/qca/ar9331_dpt_module.dts1
-rw-r--r--src/mips/qca/ar9331_dragino_ms14.dts1
-rw-r--r--src/mips/qca/ar9331_omega.dts1
-rw-r--r--src/mips/qca/ar9331_tl_mr3020.dts1
-rw-r--r--src/mips/ralink/mt7620a.dtsi1
-rw-r--r--src/mips/ralink/mt7620a_eval.dts1
-rw-r--r--src/mips/ralink/mt7628a.dtsi126
-rw-r--r--src/mips/ralink/omega2p.dts18
-rw-r--r--src/mips/ralink/rt2880.dtsi1
-rw-r--r--src/mips/ralink/rt2880_eval.dts1
-rw-r--r--src/mips/ralink/rt3050.dtsi1
-rw-r--r--src/mips/ralink/rt3052_eval.dts1
-rw-r--r--src/mips/ralink/rt3883.dtsi1
-rw-r--r--src/mips/ralink/rt3883_eval.dts1
-rw-r--r--src/mips/ralink/vocore2.dts18
-rw-r--r--src/mips/xilfpga/microAptiv.dtsi1
-rw-r--r--src/mips/xilfpga/nexys4ddr.dts1
-rw-r--r--src/nios2/3c120_devboard.dts3
-rw-r--r--src/openrisc/or1ksim.dts1
-rw-r--r--src/powerpc/fsp2.dts33
-rw-r--r--src/powerpc/virtex440-ml510.dts1
-rwxr-xr-xsrc/sh/j2_mimas_v2.dts1
-rw-r--r--src/xtensa/csp.dts1
-rw-r--r--src/xtensa/kc705.dts1
-rw-r--r--src/xtensa/kc705_nommu.dts1
-rw-r--r--src/xtensa/lx200mx.dts1
-rw-r--r--src/xtensa/lx60.dts1
-rw-r--r--src/xtensa/ml605.dts1
-rw-r--r--src/xtensa/xtfpga-flash-128m.dtsi1
-rw-r--r--src/xtensa/xtfpga-flash-16m.dtsi1
-rw-r--r--src/xtensa/xtfpga-flash-4m.dtsi1
-rw-r--r--src/xtensa/xtfpga.dtsi1
1378 files changed, 31128 insertions, 5078 deletions
diff --git a/Bindings/arc/hsdk.txt b/Bindings/arc/hsdk.txt
new file mode 100644
index 000000000000..be50654bbf61
--- /dev/null
+++ b/Bindings/arc/hsdk.txt
@@ -0,0 +1,7 @@
+Synopsys DesignWare ARC HS Development Kit Device Tree Bindings
+---------------------------------------------------------------------------
+
+ARC HSDK Board with quad-core ARC HS38x4 in silicon.
+
+Required root node properties:
+ - compatible = "snps,hsdk";
diff --git a/Bindings/arm/amlogic.txt b/Bindings/arm/amlogic.txt
index 0fff40a6330d..4e4bc0bae597 100644
--- a/Bindings/arm/amlogic.txt
+++ b/Bindings/arm/amlogic.txt
@@ -1,6 +1,18 @@
Amlogic MesonX device tree bindings
-------------------------------------------
+Work in progress statement:
+
+Device tree files and bindings applying to Amlogic SoCs and boards are
+considered "unstable". Any Amlogic device tree binding may change at
+any time. Be sure to use a device tree binary and a kernel image
+generated from the same source tree.
+
+Please refer to Documentation/devicetree/bindings/ABI.txt for a definition of a
+stable binding/ABI.
+
+---------------------------------------------------------------
+
Boards with the Amlogic Meson6 SoC shall have the following properties:
Required root node property:
compatible: "amlogic,meson6"
@@ -61,3 +73,32 @@ Board compatible values (alphabetically, grouped by SoC):
- "amlogic,q201" (Meson gxm s912)
- "kingnovel,r-box-pro" (Meson gxm S912)
- "nexbox,a1" (Meson gxm s912)
+
+Amlogic Meson Firmware registers Interface
+------------------------------------------
+
+The Meson SoCs have a register bank with status and data shared with the
+secure firmware.
+
+Required properties:
+ - compatible: For Meson GX SoCs, must be "amlogic,meson-gx-ao-secure", "syscon"
+
+Properties should indentify components of this register interface :
+
+Meson GX SoC Information
+------------------------
+A firmware register encodes the SoC type, package and revision information on
+the Meson GX SoCs.
+If present, the following property should be added :
+
+Optional properties:
+ - amlogic,has-chip-id: If present, the interface gives the current SoC version.
+
+Example
+-------
+
+ao-secure@140 {
+ compatible = "amlogic,meson-gx-ao-secure", "syscon";
+ reg = <0x0 0x140 0x0 0x140>;
+ amlogic,has-chip-id;
+};
diff --git a/Bindings/arm/arch_timer.txt b/Bindings/arm/arch_timer.txt
index e926aea1147d..68301b77e854 100644
--- a/Bindings/arm/arch_timer.txt
+++ b/Bindings/arm/arch_timer.txt
@@ -108,6 +108,5 @@ Example:
frame-number = <1>
interrupts = <0 15 0x8>;
reg = <0xf0003000 0x1000>;
- status = "disabled";
};
};
diff --git a/Bindings/arm/bcm/brcm,bcm2835.txt b/Bindings/arm/bcm/brcm,bcm2835.txt
index 9c97de23919a..3e3efa046ac5 100644
--- a/Bindings/arm/bcm/brcm,bcm2835.txt
+++ b/Bindings/arm/bcm/brcm,bcm2835.txt
@@ -42,6 +42,10 @@ Raspberry Pi Zero
Required root node properties:
compatible = "raspberrypi,model-zero", "brcm,bcm2835";
+Raspberry Pi Zero W
+Required root node properties:
+compatible = "raspberrypi,model-zero-w", "brcm,bcm2835";
+
Generic BCM2835 board
Required root node properties:
compatible = "brcm,bcm2835";
diff --git a/Bindings/arm/bhf.txt b/Bindings/arm/bhf.txt
new file mode 100644
index 000000000000..886b503caf9c
--- /dev/null
+++ b/Bindings/arm/bhf.txt
@@ -0,0 +1,6 @@
+Beckhoff Automation Platforms Device Tree Bindings
+--------------------------------------------------
+
+CX9020 Embedded PC
+Required root node properties:
+ - compatible = "bhf,cx9020", "fsl,imx53";
diff --git a/Bindings/arm/coresight.txt b/Bindings/arm/coresight.txt
index fcbae6a5e6c1..15ac8e8dcfdf 100644
--- a/Bindings/arm/coresight.txt
+++ b/Bindings/arm/coresight.txt
@@ -34,8 +34,8 @@ its hardware characteristcs.
- Embedded Trace Macrocell (version 4.x):
"arm,coresight-etm4x", "arm,primecell";
- - Qualcomm Configurable Replicator (version 1.x):
- "qcom,coresight-replicator1x", "arm,primecell";
+ - Coresight programmable Replicator :
+ "arm,coresight-dynamic-replicator", "arm,primecell";
- System Trace Macrocell:
"arm,coresight-stm", "arm,primecell"; [1]
diff --git a/Bindings/arm/cpus.txt b/Bindings/arm/cpus.txt
index a44253cad269..b92f12bd5244 100644
--- a/Bindings/arm/cpus.txt
+++ b/Bindings/arm/cpus.txt
@@ -200,6 +200,7 @@ described below.
"arm,realview-smp"
"brcm,bcm11351-cpu-method"
"brcm,bcm23550"
+ "brcm,bcm2836-smp"
"brcm,bcm-nsp-smp"
"brcm,brahma-b15"
"marvell,armada-375-smp"
diff --git a/Bindings/arm/marvell/armada-8kp.txt b/Bindings/arm/marvell/armada-8kp.txt
new file mode 100644
index 000000000000..f3e9624534c6
--- /dev/null
+++ b/Bindings/arm/marvell/armada-8kp.txt
@@ -0,0 +1,15 @@
+Marvell Armada 8KPlus Platforms Device Tree Bindings
+----------------------------------------------------
+
+Boards using a SoC of the Marvell Armada 8KP families must carry
+the following root node property:
+
+ - compatible, with one of the following values:
+
+ - "marvell,armada-8080", "marvell,armada-ap810-octa", "marvell,armada-ap810"
+ when the SoC being used is the Armada 8080
+
+Example:
+
+compatible = "marvell,armada-8080-db", "marvell,armada-8080",
+ "marvell,armada-ap810-octa", "marvell,armada-ap810"
diff --git a/Bindings/arm/marvell/cp110-system-controller0.txt b/Bindings/arm/marvell/cp110-system-controller0.txt
index 171d02cadea4..29cdbae6c5ac 100644
--- a/Bindings/arm/marvell/cp110-system-controller0.txt
+++ b/Bindings/arm/marvell/cp110-system-controller0.txt
@@ -183,7 +183,6 @@ cpm_syscon0: system-controller@440000 {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&cpm_pinctrl 0 0 32>;
- status = "disabled";
};
};
diff --git a/Bindings/arm/mediatek.txt b/Bindings/arm/mediatek.txt
index da7bd138e6f2..91d517849483 100644
--- a/Bindings/arm/mediatek.txt
+++ b/Bindings/arm/mediatek.txt
@@ -1,12 +1,12 @@
-MediaTek mt65xx, mt67xx & mt81xx Platforms Device Tree Bindings
+MediaTek SoC based Platforms Device Tree Bindings
-Boards with a MediaTek mt65xx/mt67xx/mt81xx SoC shall have the
-following property:
+Boards with a MediaTek SoC shall have the following property:
Required root node property:
compatible: Must contain one of
"mediatek,mt2701"
+ "mediatek,mt2712"
"mediatek,mt6580"
"mediatek,mt6589"
"mediatek,mt6592"
@@ -14,7 +14,8 @@ compatible: Must contain one of
"mediatek,mt6795"
"mediatek,mt6797"
"mediatek,mt7622"
- "mediatek,mt7623"
+ "mediatek,mt7623" which is referred to MT7623N SoC
+ "mediatek,mt7623a"
"mediatek,mt8127"
"mediatek,mt8135"
"mediatek,mt8173"
@@ -25,6 +26,9 @@ Supported boards:
- Evaluation board for MT2701:
Required root node properties:
- compatible = "mediatek,mt2701-evb", "mediatek,mt2701";
+- Evaluation board for MT2712:
+ Required root node properties:
+ - compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
- Evaluation board for MT6580:
Required root node properties:
- compatible = "mediatek,mt6580-evbp1", "mediatek,mt6580";
@@ -46,9 +50,11 @@ Supported boards:
- Reference board variant 1 for MT7622:
Required root node properties:
- compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
-- Evaluation board for MT7623:
+- Reference board for MT7623n with NAND:
Required root node properties:
- - compatible = "mediatek,mt7623-evb", "mediatek,mt7623";
+ - compatible = "mediatek,mt7623n-rfb-nand", "mediatek,mt7623";
+- Bananapi BPI-R2 board:
+ - compatible = "bananapi,bpi-r2", "mediatek,mt7623";
- MTK mt8127 tablet moose EVB:
Required root node properties:
- compatible = "mediatek,mt8127-moose", "mediatek,mt8127";
diff --git a/Bindings/arm/omap/omap.txt b/Bindings/arm/omap/omap.txt
index 8219b2c6bb29..2ecc712bf707 100644
--- a/Bindings/arm/omap/omap.txt
+++ b/Bindings/arm/omap/omap.txt
@@ -80,6 +80,9 @@ SoCs:
- OMAP5432
compatible = "ti,omap5432", "ti,omap5"
+- DRA762
+ compatible = "ti,dra762", "ti,dra7"
+
- DRA742
compatible = "ti,dra742", "ti,dra74", "ti,dra7"
@@ -154,6 +157,9 @@ Boards:
- AM335X phyCORE-AM335x: Development kit
compatible = "phytec,am335x-pcm-953", "phytec,am335x-phycore-som", "ti,am33xx"
+- AM335X UC-8100-ME-T: Communication-centric industrial computing platform
+ compatible = "moxa,uc-8100-me-t", "ti,am33xx";
+
- OMAP5 EVM : Evaluation Module
compatible = "ti,omap5-evm", "ti,omap5"
@@ -184,6 +190,9 @@ Boards:
- AM5718 IDK
compatible = "ti,am5718-idk", "ti,am5718", "ti,dra7"
+- DRA762 EVM: Software Development Board for DRA762
+ compatible = "ti,dra76-evm", "ti,dra762", "ti,dra7"
+
- DRA742 EVM: Software Development Board for DRA742
compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"
diff --git a/Bindings/arm/pmu.txt b/Bindings/arm/pmu.txt
index 61c8b4620415..13611a8199bb 100644
--- a/Bindings/arm/pmu.txt
+++ b/Bindings/arm/pmu.txt
@@ -9,9 +9,11 @@ Required properties:
- compatible : should be one of
"apm,potenza-pmu"
"arm,armv8-pmuv3"
+ "arm,cortex-a73-pmu"
"arm,cortex-a72-pmu"
"arm,cortex-a57-pmu"
"arm,cortex-a53-pmu"
+ "arm,cortex-a35-pmu"
"arm,cortex-a17-pmu"
"arm,cortex-a15-pmu"
"arm,cortex-a12-pmu"
diff --git a/Bindings/arm/qcom.txt b/Bindings/arm/qcom.txt
index 028d16e72186..0ed4d39d7fe1 100644
--- a/Bindings/arm/qcom.txt
+++ b/Bindings/arm/qcom.txt
@@ -25,6 +25,7 @@ The 'SoC' element must be one of the following strings:
msm8994
msm8996
mdm9615
+ ipq8074
The 'board' element must be one of the following strings:
@@ -33,6 +34,7 @@ The 'board' element must be one of the following strings:
dragonboard
mtp
sbc
+ hk01
The 'soc_version' and 'board_version' elements take the form of v<Major>.<Minor>
where the minor number may be omitted when it's zero, i.e. v1.0 is the same
diff --git a/Bindings/arm/rockchip.txt b/Bindings/arm/rockchip.txt
index 11c0ac4a2d56..b003148e2945 100644
--- a/Bindings/arm/rockchip.txt
+++ b/Bindings/arm/rockchip.txt
@@ -134,6 +134,10 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "phytec,rk3288-pcm-947", "phytec,rk3288-phycore-som", "rockchip,rk3288";
+- Pine64 Rock64 board:
+ Required root node properties:
+ - compatible = "pine64,rock64", "rockchip,rk3328";
+
- Rockchip PX3 Evaluation board:
Required root node properties:
- compatible = "rockchip,px3-evb", "rockchip,px3", "rockchip,rk3188";
@@ -173,6 +177,14 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "rockchip,rk3399-evb", "rockchip,rk3399";
+- Rockchip RK3399 Sapphire Excavator board:
+ Required root node properties:
+ - compatible = "rockchip,rk3399-sapphire-excavator", "rockchip,rk3399";
+
+- Theobroma Systems RK3399-Q7 Haikou Baseboard:
+ Required root node properties:
+ - compatible = "tsd,rk3399-q7-haikou", "rockchip,rk3399";
+
- Tronsmart Orion R68 Meta
Required root node properties:
- compatible = "tronsmart,orion-r68-meta", "rockchip,rk3368";
diff --git a/Bindings/arm/shmobile.txt b/Bindings/arm/shmobile.txt
index 1a671e329864..ae75cb3b1331 100644
--- a/Bindings/arm/shmobile.txt
+++ b/Bindings/arm/shmobile.txt
@@ -39,6 +39,8 @@ SoCs:
compatible = "renesas,r8a7795"
- R-Car M3-W (R8A77960)
compatible = "renesas,r8a7796"
+ - R-Car D3 (R8A77995)
+ compatible = "renesas,r8a77995"
Boards:
@@ -53,6 +55,8 @@ Boards:
compatible = "renesas,blanche", "renesas,r8a7792"
- BOCK-W
compatible = "renesas,bockw", "renesas,r8a7778"
+ - Draak (RTP0RC77995SEB0010S)
+ compatible = "renesas,draak", "renesas,r8a77995"
- Genmai (RTK772100BC00000BR)
compatible = "renesas,genmai", "renesas,r7s72100"
- GR-Peach (X28A-M01-E/F)
@@ -64,6 +68,10 @@ Boards:
compatible = "renesas,h3ulcb", "renesas,r8a7795";
- Henninger
compatible = "renesas,henninger", "renesas,r8a7791"
+ - iWave Systems RZ/G1E SODIMM SOM Development Platform (iW-RainboW-G22D)
+ compatible = "iwave,g22d", "iwave,g22m", "renesas,r8a7745"
+ - iWave Systems RZ/G1E SODIMM System On Module (iW-RainboW-G22M-SM)
+ compatible = "iwave,g22m", "renesas,r8a7745"
- iWave Systems RZ/G1M Qseven Development Platform (iW-RainboW-G20D-Qseven)
compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743"
- iWave Systems RZ/G1M Qseven System On Module (iW-RainboW-G20M-Qseven)
diff --git a/Bindings/ata/ahci-mtk.txt b/Bindings/ata/ahci-mtk.txt
new file mode 100644
index 000000000000..d2aa696b161b
--- /dev/null
+++ b/Bindings/ata/ahci-mtk.txt
@@ -0,0 +1,51 @@
+MediaTek Serial ATA controller
+
+Required properties:
+ - compatible : Must be "mediatek,<chip>-ahci", "mediatek,mtk-ahci".
+ When using "mediatek,mtk-ahci" compatible strings, you
+ need SoC specific ones in addition, one of:
+ - "mediatek,mt7622-ahci"
+ - reg : Physical base addresses and length of register sets.
+ - interrupts : Interrupt associated with the SATA device.
+ - interrupt-names : Associated name must be: "hostc".
+ - clocks : A list of phandle and clock specifier pairs, one for each
+ entry in clock-names.
+ - clock-names : Associated names must be: "ahb", "axi", "asic", "rbc", "pm".
+ - phys : A phandle and PHY specifier pair for the PHY port.
+ - phy-names : Associated name must be: "sata-phy".
+ - ports-implemented : See ./ahci-platform.txt for details.
+
+Optional properties:
+ - power-domains : A phandle and power domain specifier pair to the power
+ domain which is responsible for collapsing and restoring
+ power to the peripheral.
+ - resets : Must contain an entry for each entry in reset-names.
+ See ../reset/reset.txt for details.
+ - reset-names : Associated names must be: "axi", "sw", "reg".
+ - mediatek,phy-mode : A phandle to the system controller, used to enable
+ SATA function.
+
+Example:
+
+ sata: sata@1a200000 {
+ compatible = "mediatek,mt7622-ahci",
+ "mediatek,mtk-ahci";
+ reg = <0 0x1a200000 0 0x1100>;
+ interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hostc";
+ clocks = <&pciesys CLK_SATA_AHB_EN>,
+ <&pciesys CLK_SATA_AXI_EN>,
+ <&pciesys CLK_SATA_ASIC_EN>,
+ <&pciesys CLK_SATA_RBC_EN>,
+ <&pciesys CLK_SATA_PM_EN>;
+ clock-names = "ahb", "axi", "asic", "rbc", "pm";
+ phys = <&u3port1 PHY_TYPE_SATA>;
+ phy-names = "sata-phy";
+ ports-implemented = <0x1>;
+ power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
+ resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
+ <&pciesys MT7622_SATA_PHY_SW_RST>,
+ <&pciesys MT7622_SATA_PHY_REG_RST>;
+ reset-names = "axi", "sw", "reg";
+ mediatek,phy-mode = <&pciesys>;
+ };
diff --git a/Bindings/ata/apm-xgene.txt b/Bindings/ata/apm-xgene.txt
index a668f0e7d001..02e690a675db 100644
--- a/Bindings/ata/apm-xgene.txt
+++ b/Bindings/ata/apm-xgene.txt
@@ -57,7 +57,6 @@ Example:
<0x0 0x1f227000 0x0 0x1000>;
interrupts = <0x0 0x87 0x4>;
dma-coherent;
- status = "ok";
clocks = <&sataclk 0>;
phys = <&phy2 0>;
phy-names = "sata-phy";
@@ -72,7 +71,6 @@ Example:
<0x0 0x1f237000 0x0 0x1000>;
interrupts = <0x0 0x88 0x4>;
dma-coherent;
- status = "ok";
clocks = <&sataclk 0>;
phys = <&phy3 0>;
phy-names = "sata-phy";
diff --git a/Bindings/ata/imx-pata.txt b/Bindings/ata/imx-pata.txt
index e38d73414b0d..f1172f00188a 100644
--- a/Bindings/ata/imx-pata.txt
+++ b/Bindings/ata/imx-pata.txt
@@ -13,5 +13,4 @@ Example:
reg = <0x83fe0000 0x4000>;
interrupts = <70>;
clocks = <&clks 161>;
- status = "disabled";
};
diff --git a/Bindings/bus/mvebu-mbus.txt b/Bindings/bus/mvebu-mbus.txt
index fa6cde41b460..f2ab7fd013bd 100644
--- a/Bindings/bus/mvebu-mbus.txt
+++ b/Bindings/bus/mvebu-mbus.txt
@@ -227,7 +227,6 @@ See the example below, where a more complete device tree is shown:
};
devbus-bootcs {
- status = "okay";
ranges = <0 MBUS_ID(0x01, 0x2f) 0 0x8000000>;
/* NOR */
@@ -240,7 +239,6 @@ See the example below, where a more complete device tree is shown:
pcie-controller {
compatible = "marvell,armada-xp-pcie";
- status = "okay";
device_type = "pci";
#address-cells = <3>;
@@ -258,7 +256,6 @@ See the example below, where a more complete device tree is shown:
pcie@1,0 {
/* Port 0, Lane 0 */
- status = "okay";
};
};
diff --git a/Bindings/bus/nvidia,tegra20-gmi.txt b/Bindings/bus/nvidia,tegra20-gmi.txt
index 83b0e54f727c..3e21eb822811 100644
--- a/Bindings/bus/nvidia,tegra20-gmi.txt
+++ b/Bindings/bus/nvidia,tegra20-gmi.txt
@@ -84,7 +84,6 @@ gmi@70090000 {
reset-names = "gmi";
ranges = <4 0 0xd0000000 0xfffffff>;
- status = "okay";
bus@4,0 {
compatible = "simple-bus";
@@ -121,7 +120,6 @@ gmi@70090000 {
reset-names = "gmi";
ranges = <4 0 0xd0000000 0xfffffff>;
- status = "okay";
can@4,0 {
reg = <4 0 0x100>;
diff --git a/Bindings/bus/nvidia,tegra210-aconnect.txt b/Bindings/bus/nvidia,tegra210-aconnect.txt
index 7ff13be1750b..3108d03802ee 100644
--- a/Bindings/bus/nvidia,tegra210-aconnect.txt
+++ b/Bindings/bus/nvidia,tegra210-aconnect.txt
@@ -33,7 +33,6 @@ Example:
#size-cells = <1>;
ranges = <0x702c0000 0x0 0x702c0000 0x00040000>;
- status = "disabled";
child1 {
...
diff --git a/Bindings/chosen.txt b/Bindings/chosen.txt
index dee3f5d9df26..e3b13ea7d2ae 100644
--- a/Bindings/chosen.txt
+++ b/Bindings/chosen.txt
@@ -5,9 +5,31 @@ The chosen node does not represent a real device, but serves as a place
for passing data between firmware and the operating system, like boot
arguments. Data in the chosen node does not represent the hardware.
+The following properties are recognized:
-stdout-path property
---------------------
+
+kaslr-seed
+-----------
+
+This property is used when booting with CONFIG_RANDOMIZE_BASE as the
+entropy used to randomize the kernel image base address location. Since
+it is used directly, this value is intended only for KASLR, and should
+not be used for other purposes (as it may leak information about KASLR
+offsets). It is parsed as a u64 value, e.g.
+
+/ {
+ chosen {
+ kaslr-seed = <0xfeedbeef 0xc0def00d>;
+ };
+};
+
+Note that if this property is set from UEFI (or a bootloader in EFI
+mode) when EFI_RNG_PROTOCOL is supported, it will be overwritten by
+the Linux EFI stub (which will populate the property itself, using
+EFI_RNG_PROTOCOL).
+
+stdout-path
+-----------
Device trees may specify the device to be used for boot console output
with a stdout-path property under /chosen, as described in the Devicetree
diff --git a/Bindings/clock/alphascale,acc.txt b/Bindings/clock/alphascale,acc.txt
index 62e67e883e76..b3205b21c9d0 100644
--- a/Bindings/clock/alphascale,acc.txt
+++ b/Bindings/clock/alphascale,acc.txt
@@ -102,7 +102,6 @@ uart4: serial@80010000 {
reg = <0x80010000 0x4000>;
clocks = <&acc CLKID_SYS_UART4>, <&acc CLKID_AHB_UART4>;
interrupts = <19>;
- status = "disabled";
};
Clock consumer with only one, _AHB_ sink.
diff --git a/Bindings/clock/amlogic,gxbb-aoclkc.txt b/Bindings/clock/amlogic,gxbb-aoclkc.txt
index a55d31b48d6e..786dc39ca904 100644
--- a/Bindings/clock/amlogic,gxbb-aoclkc.txt
+++ b/Bindings/clock/amlogic,gxbb-aoclkc.txt
@@ -5,9 +5,11 @@ controllers within the Always-On part of the SoC.
Required Properties:
-- compatible: should be "amlogic,gxbb-aoclkc"
-- reg: physical base address of the clock controller and length of memory
- mapped region.
+- compatible: value should be different for each SoC family as :
+ - GXBB (S905) : "amlogic,meson-gxbb-aoclkc"
+ - GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc"
+ - GXM (S912) : "amlogic,meson-gxm-aoclkc"
+ followed by the common "amlogic,meson-gx-aoclkc"
- #clock-cells: should be 1.
@@ -23,14 +25,22 @@ to specify the reset which they consume. All available resets are defined as
preprocessor macros in the dt-bindings/reset/gxbb-aoclkc.h header and can be
used in device tree sources.
+Parent node should have the following properties :
+- compatible: "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd"
+- reg: base address and size of the AO system control register space.
+
Example: AO Clock controller node:
- clkc_AO: clock-controller@040 {
- compatible = "amlogic,gxbb-aoclkc";
- reg = <0x0 0x040 0x0 0x4>;
+ao_sysctrl: sys-ctrl@0 {
+ compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd";
+ reg = <0x0 0x0 0x0 0x100>;
+
+ clkc_AO: clock-controller {
+ compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
#clock-cells = <1>;
#reset-cells = <1>;
};
+};
Example: UART controller node that consumes the clock and reset generated
by the clock controller:
@@ -41,5 +51,4 @@ Example: UART controller node that consumes the clock and reset generated
interrupts = <0 90 1>;
clocks = <&clkc_AO CLKID_AO_UART1>;
resets = <&clkc_AO RESET_AO_UART1>;
- status = "disabled";
};
diff --git a/Bindings/clock/amlogic,gxbb-clkc.txt b/Bindings/clock/amlogic,gxbb-clkc.txt
index a09d627b5508..924040769186 100644
--- a/Bindings/clock/amlogic,gxbb-clkc.txt
+++ b/Bindings/clock/amlogic,gxbb-clkc.txt
@@ -33,5 +33,4 @@ Example: UART controller node that consumes the clock generated by the clock
reg = <0xc81004c0 0x14>;
interrupts = <0 90 1>;
clocks = <&clkc CLKID_CLK81>;
- status = "disabled";
};
diff --git a/Bindings/clock/amlogic,meson8b-clkc.txt b/Bindings/clock/amlogic,meson8b-clkc.txt
index 606da38c0959..b455c5aa9139 100644
--- a/Bindings/clock/amlogic,meson8b-clkc.txt
+++ b/Bindings/clock/amlogic,meson8b-clkc.txt
@@ -16,18 +16,25 @@ Required Properties:
mapped region.
- #clock-cells: should be 1.
+- #reset-cells: should be 1.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All available clocks are defined as
preprocessor macros in the dt-bindings/clock/meson8b-clkc.h header and can be
used in device tree sources.
+Similarly a preprocessor macro for each reset line is defined in
+dt-bindings/reset/amlogic,meson8b-clkc-reset.h (which can be used from the
+device tree sources).
+
+
Example: Clock controller node:
clkc: clock-controller@c1104000 {
- #clock-cells = <1>;
compatible = "amlogic,meson8b-clkc";
reg = <0xc1108000 0x4>, <0xc1104000 0x460>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
};
@@ -39,5 +46,4 @@ Example: UART controller node that consumes the clock generated by the clock
reg = <0xc81004c0 0x14>;
interrupts = <0 90 1>;
clocks = <&clkc CLKID_CLK81>;
- status = "disabled";
};
diff --git a/Bindings/clock/at91-clock.txt b/Bindings/clock/at91-clock.txt
index 5f3ad65daf69..51c259a92d02 100644
--- a/Bindings/clock/at91-clock.txt
+++ b/Bindings/clock/at91-clock.txt
@@ -81,6 +81,16 @@ Required properties:
"atmel,sama5d2-clk-generated":
at91 generated clock
+ "atmel,sama5d2-clk-audio-pll-frac":
+ at91 audio fractional pll
+
+ "atmel,sama5d2-clk-audio-pll-pad":
+ at91 audio pll CLK_AUDIO output pin
+
+ "atmel,sama5d2-clk-audio-pll-pmc"
+ at91 audio pll output on AUDIOPLLCLK that feeds the PMC
+ and can be used by peripheral clock or generic clock
+
Required properties for SCKC node:
- reg : defines the IO memory reserved for the SCKC.
- #size-cells : shall be 0 (reg is used to encode clk id).
diff --git a/Bindings/clock/brcm,kona-ccu.txt b/Bindings/clock/brcm,kona-ccu.txt
index 5286e260fcae..8e5a7d868557 100644
--- a/Bindings/clock/brcm,kona-ccu.txt
+++ b/Bindings/clock/brcm,kona-ccu.txt
@@ -46,7 +46,6 @@ Device tree example:
uart@3e002000 {
compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
- status = "disabled";
reg = <0x3e002000 0x1000>;
clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB3>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/Bindings/clock/exynos5433-clock.txt b/Bindings/clock/exynos5433-clock.txt
index 1dc80f8811fe..fe885abc9cb4 100644
--- a/Bindings/clock/exynos5433-clock.txt
+++ b/Bindings/clock/exynos5433-clock.txt
@@ -465,5 +465,4 @@ Example 3: UART controller node that consumes the clock generated by the clock
clock-names = "uart", "clk_uart_baud0";
pinctrl-names = "default";
pinctrl-0 = <&uart0_bus>;
- status = "disabled";
};
diff --git a/Bindings/clock/hi3660-clock.txt b/Bindings/clock/hi3660-clock.txt
index cc9b86c35758..0035a7ecaf20 100644
--- a/Bindings/clock/hi3660-clock.txt
+++ b/Bindings/clock/hi3660-clock.txt
@@ -38,5 +38,4 @@ Examples:
clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>,
<&crg_ctrl HI3660_PCLK>;
clock-names = "uartclk", "apb_pclk";
- status = "disabled";
};
diff --git a/Bindings/clock/hix5hd2-clock.txt b/Bindings/clock/hix5hd2-clock.txt
index 7894a64887cb..4733e58e491b 100644
--- a/Bindings/clock/hix5hd2-clock.txt
+++ b/Bindings/clock/hix5hd2-clock.txt
@@ -27,5 +27,4 @@ Examples:
interrupts = <0 49 4>;
clocks = <&clock HIX5HD2_FIXED_83M>;
clock-names = "apb_pclk";
- status = "disabled";
};
diff --git a/Bindings/clock/idt,versaclock5.txt b/Bindings/clock/idt,versaclock5.txt
index 53d7e50ed875..05a245c9df08 100644
--- a/Bindings/clock/idt,versaclock5.txt
+++ b/Bindings/clock/idt,versaclock5.txt
@@ -1,24 +1,32 @@
-Binding for IDT VersaClock5 programmable i2c clock generator.
+Binding for IDT VersaClock 5,6 programmable i2c clock generators.
-The IDT VersaClock5 are programmable i2c clock generators providing
-from 3 to 12 output clocks.
+The IDT VersaClock 5 and VersaClock 6 are programmable i2c clock
+generators providing from 3 to 12 output clocks.
==I2C device node==
Required properties:
-- compatible: shall be one of "idt,5p49v5923" , "idt,5p49v5933" ,
- "idt,5p49v5935".
+- compatible: shall be one of
+ "idt,5p49v5923"
+ "idt,5p49v5925"
+ "idt,5p49v5933"
+ "idt,5p49v5935"
+ "idt,5p49v6901"
- reg: i2c device address, shall be 0x68 or 0x6a.
- #clock-cells: from common clock binding; shall be set to 1.
- clocks: from common clock binding; list of parent clock handles,
- - 5p49v5923: (required) either or both of XTAL or CLKIN
+ - 5p49v5923 and
+ 5p49v5925 and
+ 5p49v6901: (required) either or both of XTAL or CLKIN
reference clock.
- 5p49v5933 and
- 5p49v5935: (optional) property not present (internal
Xtal used) or CLKIN reference
clock.
- clock-names: from common clock binding; clock input names, can be
- - 5p49v5923: (required) either or both of "xin", "clkin".
+ - 5p49v5923 and
+ 5p49v5925 and
+ 5p49v6901: (required) either or both of "xin", "clkin".
- 5p49v5933 and
- 5p49v5935: (optional) property not present or "clkin".
@@ -37,6 +45,7 @@ clock specifier, the following mapping applies:
1 -- OUT1
2 -- OUT4
+5P49V5925 and
5P49V5935:
0 -- OUT0_SEL_I2CB
1 -- OUT1
@@ -44,6 +53,13 @@ clock specifier, the following mapping applies:
3 -- OUT3
4 -- OUT4
+5P49V6901:
+ 0 -- OUT0_SEL_I2CB
+ 1 -- OUT1
+ 2 -- OUT2
+ 3 -- OUT3
+ 4 -- OUT4
+
==Example==
/* 25MHz reference crystal */
diff --git a/Bindings/clock/imx21-clock.txt b/Bindings/clock/imx21-clock.txt
index c3b0db437c48..806f63d628bd 100644
--- a/Bindings/clock/imx21-clock.txt
+++ b/Bindings/clock/imx21-clock.txt
@@ -24,5 +24,4 @@ Examples:
clocks = <&clks IMX21_CLK_UART1_IPG_GATE>,
<&clks IMX21_CLK_PER1>;
clock-names = "ipg", "per";
- status = "disabled";
};
diff --git a/Bindings/clock/imx23-clock.txt b/Bindings/clock/imx23-clock.txt
index 5083c0b834b2..8385348d3bd9 100644
--- a/Bindings/clock/imx23-clock.txt
+++ b/Bindings/clock/imx23-clock.txt
@@ -67,5 +67,4 @@ auart0: serial@8006c000 {
reg = <0x8006c000 0x2000>;
interrupts = <24 25 23>;
clocks = <&clks 32>;
- status = "disabled";
};
diff --git a/Bindings/clock/imx25-clock.txt b/Bindings/clock/imx25-clock.txt
index ba6b312ff8a5..f8135ea9ca4e 100644
--- a/Bindings/clock/imx25-clock.txt
+++ b/Bindings/clock/imx25-clock.txt
@@ -157,5 +157,4 @@ uart1: serial@43f90000 {
interrupts = <45>;
clocks = <&clks 79>, <&clks 50>;
clock-names = "ipg", "per";
- status = "disabled";
};
diff --git a/Bindings/clock/imx27-clock.txt b/Bindings/clock/imx27-clock.txt
index cc05de9ec393..4c95c048d3b2 100644
--- a/Bindings/clock/imx27-clock.txt
+++ b/Bindings/clock/imx27-clock.txt
@@ -24,5 +24,4 @@ Examples:
clocks = <&clks IMX27_CLK_UART1_IPG_GATE>,
<&clks IMX27_CLK_PER1_GATE>;
clock-names = "ipg", "per";
- status = "disabled";
};
diff --git a/Bindings/clock/imx28-clock.txt b/Bindings/clock/imx28-clock.txt
index e6587af62ff0..d84a37d2885f 100644
--- a/Bindings/clock/imx28-clock.txt
+++ b/Bindings/clock/imx28-clock.txt
@@ -90,5 +90,4 @@ auart0: serial@8006a000 {
reg = <0x8006a000 0x2000>;
interrupts = <112 70 71>;
clocks = <&clks 45>;
- status = "disabled";
};
diff --git a/Bindings/clock/imx31-clock.txt b/Bindings/clock/imx31-clock.txt
index 8163d565f697..0a291090e562 100644
--- a/Bindings/clock/imx31-clock.txt
+++ b/Bindings/clock/imx31-clock.txt
@@ -87,5 +87,4 @@ uart1: serial@43f90000 {
interrupts = <45>;
clocks = <&clks 10>, <&clks 30>;
clock-names = "ipg", "per";
- status = "disabled";
};
diff --git a/Bindings/clock/imx5-clock.txt b/Bindings/clock/imx5-clock.txt
index cadc4d29ada6..a24ca9e582d2 100644
--- a/Bindings/clock/imx5-clock.txt
+++ b/Bindings/clock/imx5-clock.txt
@@ -25,5 +25,4 @@ can1: can@53fc8000 {
interrupts = <82>;
clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
clock-names = "ipg", "per";
- status = "disabled";
};
diff --git a/Bindings/clock/imx6q-clock.txt b/Bindings/clock/imx6q-clock.txt
index 9252912a5b0e..aa0a4d423ef5 100644
--- a/Bindings/clock/imx6q-clock.txt
+++ b/Bindings/clock/imx6q-clock.txt
@@ -27,5 +27,4 @@ uart1: serial@02020000 {
interrupts = <0 26 0x04>;
clocks = <&clks IMX6QDL_CLK_UART_IPG>, <&clks IMX6QDL_CLK_UART_SERIAL>;
clock-names = "ipg", "per";
- status = "disabled";
};
diff --git a/Bindings/clock/mt8173-cpu-dvfs.txt b/Bindings/clock/mt8173-cpu-dvfs.txt
deleted file mode 100644
index 52b457c23eed..000000000000
--- a/Bindings/clock/mt8173-cpu-dvfs.txt
+++ /dev/null
@@ -1,83 +0,0 @@
-Device Tree Clock bindins for CPU DVFS of Mediatek MT8173 SoC
-
-Required properties:
-- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
-- clock-names: Should contain the following:
- "cpu" - The multiplexer for clock input of CPU cluster.
- "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock
- source (usually MAINPLL) when the original CPU PLL is under
- transition and not stable yet.
- Please refer to Documentation/devicetree/bindings/clk/clock-bindings.txt for
- generic clock consumer properties.
-- proc-supply: Regulator for Vproc of CPU cluster.
-
-Optional properties:
-- sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
- needs to do "voltage tracking" to step by step scale up/down Vproc and
- Vsram to fit SoC specific needs. When absent, the voltage scaling
- flow is handled by hardware, hence no software "voltage tracking" is
- needed.
-
-Example:
---------
- cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x000>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0>;
- clocks = <&infracfg CLK_INFRA_CA53SEL>,
- <&apmixedsys CLK_APMIXED_MAINPLL>;
- clock-names = "cpu", "intermediate";
- };
-
- cpu1: cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x001>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0>;
- clocks = <&infracfg CLK_INFRA_CA53SEL>,
- <&apmixedsys CLK_APMIXED_MAINPLL>;
- clock-names = "cpu", "intermediate";
- };
-
- cpu2: cpu@100 {
- device_type = "cpu";
- compatible = "arm,cortex-a57";
- reg = <0x100>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0>;
- clocks = <&infracfg CLK_INFRA_CA57SEL>,
- <&apmixedsys CLK_APMIXED_MAINPLL>;
- clock-names = "cpu", "intermediate";
- };
-
- cpu3: cpu@101 {
- device_type = "cpu";
- compatible = "arm,cortex-a57";
- reg = <0x101>;
- enable-method = "psci";
- cpu-idle-states = <&CPU_SLEEP_0>;
- clocks = <&infracfg CLK_INFRA_CA57SEL>,
- <&apmixedsys CLK_APMIXED_MAINPLL>;
- clock-names = "cpu", "intermediate";
- };
-
- &cpu0 {
- proc-supply = <&mt6397_vpca15_reg>;
- };
-
- &cpu1 {
- proc-supply = <&mt6397_vpca15_reg>;
- };
-
- &cpu2 {
- proc-supply = <&da9211_vcpu_reg>;
- sram-supply = <&mt6397_vsramca7_reg>;
- };
-
- &cpu3 {
- proc-supply = <&da9211_vcpu_reg>;
- sram-supply = <&mt6397_vsramca7_reg>;
- };
diff --git a/Bindings/clock/nvidia,tegra124-dfll.txt b/Bindings/clock/nvidia,tegra124-dfll.txt
index 63f9d8277d48..dff236f524a7 100644
--- a/Bindings/clock/nvidia,tegra124-dfll.txt
+++ b/Bindings/clock/nvidia,tegra124-dfll.txt
@@ -66,7 +66,6 @@ clock@70110000 {
#clock-cells = <0>;
clock-output-names = "dfllCPU_out";
vdd-cpu-supply = <&vdd_cpu>;
- status = "okay";
nvidia,sample-rate = <12500>;
nvidia,droop-ctrl = <0x00000f00>;
diff --git a/Bindings/clock/pxa-clock.txt b/Bindings/clock/pxa-clock.txt
index 4b4a9024bd99..8f67239411fe 100644
--- a/Bindings/clock/pxa-clock.txt
+++ b/Bindings/clock/pxa-clock.txt
@@ -12,5 +12,4 @@ Examples:
pxa2xx_clks: pxa2xx_clks@41300004 {
compatible = "marvell,pxa-clocks";
#clock-cells = <1>;
- status = "okay";
};
diff --git a/Bindings/clock/renesas,cpg-mssr.txt b/Bindings/clock/renesas,cpg-mssr.txt
index 0cd894f987a3..316e13686568 100644
--- a/Bindings/clock/renesas,cpg-mssr.txt
+++ b/Bindings/clock/renesas,cpg-mssr.txt
@@ -22,6 +22,7 @@ Required Properties:
- "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2)
- "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
- "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)
+ - "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3)
- reg: Base address and length of the memory resource used by the CPG/MSSR
block
@@ -30,7 +31,7 @@ Required Properties:
clock-names
- clock-names: List of external parent clock names. Valid names are:
- "extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794,
- r8a7795, r8a7796)
+ r8a7795, r8a7796, r8a77995)
- "extalr" (r8a7795, r8a7796)
- "usb_extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7793, r8a7794)
@@ -81,5 +82,4 @@ Examples
dma-names = "tx", "rx";
power-domains = <&cpg>;
resets = <&cpg 310>;
- status = "disabled";
};
diff --git a/Bindings/clock/renesas,r8a7778-cpg-clocks.txt b/Bindings/clock/renesas,r8a7778-cpg-clocks.txt
index e4cdaf1cb333..7cc4c0330b53 100644
--- a/Bindings/clock/renesas,r8a7778-cpg-clocks.txt
+++ b/Bindings/clock/renesas,r8a7778-cpg-clocks.txt
@@ -44,5 +44,4 @@ Examples
interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
power-domains = <&cpg_clocks>;
- status = "disabled";
};
diff --git a/Bindings/clock/renesas,rcar-usb2-clock-sel.txt b/Bindings/clock/renesas,rcar-usb2-clock-sel.txt
new file mode 100644
index 000000000000..e96e085271c1
--- /dev/null
+++ b/Bindings/clock/renesas,rcar-usb2-clock-sel.txt
@@ -0,0 +1,55 @@
+* Renesas R-Car USB 2.0 clock selector
+
+This file provides information on what the device node for the R-Car USB 2.0
+clock selector.
+
+If you connect an external clock to the USB_EXTAL pin only, you should set
+the clock rate to "usb_extal" node only.
+If you connect an oscillator to both the USB_XTAL and USB_EXTAL, this module
+is not needed because this is default setting. (Of course, you can set the
+clock rates to both "usb_extal" and "usb_xtal" nodes.
+
+Case 1: An external clock connects to R-Car SoC
+ +----------+ +--- R-Car ---------------------+
+ |External |---|USB_EXTAL ---> all usb channels|
+ |clock | |USB_XTAL |
+ +----------+ +-------------------------------+
+In this case, we need this driver with "usb_extal" clock.
+
+Case 2: An oscillator connects to R-Car SoC
+ +----------+ +--- R-Car ---------------------+
+ |Oscillator|---|USB_EXTAL -+-> all usb channels|
+ | |---|USB_XTAL --+ |
+ +----------+ +-------------------------------+
+In this case, we don't need this selector.
+
+Required properties:
+- compatible: "renesas,r8a7795-rcar-usb2-clock-sel" if the device is a part of
+ an R8A7795 SoC.
+ "renesas,r8a7796-rcar-usb2-clock-sel" if the device if a part of
+ an R8A7796 SoC.
+ "renesas,rcar-gen3-usb2-clock-sel" for a generic R-Car Gen3
+ compatible device.
+
+ When compatible with the generic version, nodes must list the
+ SoC-specific version corresponding to the platform first
+ followed by the generic version.
+
+- reg: offset and length of the USB 2.0 clock selector register block.
+- clocks: A list of phandles and specifier pairs.
+- clock-names: Name of the clocks.
+ - The functional clock must be "ehci_ohci"
+ - The USB_EXTAL clock pin must be "usb_extal"
+ - The USB_XTAL clock pin must be "usb_xtal"
+- #clock-cells: Must be 0
+
+Example (R-Car H3):
+
+ usb2_clksel: clock-controller@e6590630 {
+ compatible = "renesas,r8a77950-rcar-usb2-clock-sel",
+ "renesas,rcar-gen3-usb2-clock-sel";
+ reg = <0 0xe6590630 0 0x02>;
+ clocks = <&cpg CPG_MOD 703>, <&usb_extal>, <&usb_xtal>;
+ clock-names = "ehci_ohci", "usb_extal", "usb_xtal";
+ #clock-cells = <0>;
+ };
diff --git a/Bindings/clock/renesas,rz-cpg-clocks.txt b/Bindings/clock/renesas,rz-cpg-clocks.txt
index bb51a33a1fbf..bb5d942075fb 100644
--- a/Bindings/clock/renesas,rz-cpg-clocks.txt
+++ b/Bindings/clock/renesas,rz-cpg-clocks.txt
@@ -50,5 +50,4 @@ Examples
clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
clock-names = "fck";
power-domains = <&cpg_clocks>;
- status = "disabled";
};
diff --git a/Bindings/clock/rockchip,rk3128-cru.txt b/Bindings/clock/rockchip,rk3128-cru.txt
index 455a9a00a623..6f8744fd301b 100644
--- a/Bindings/clock/rockchip,rk3128-cru.txt
+++ b/Bindings/clock/rockchip,rk3128-cru.txt
@@ -1,12 +1,14 @@
-* Rockchip RK3128 Clock and Reset Unit
+* Rockchip RK3126/RK3128 Clock and Reset Unit
-The RK3128 clock controller generates and supplies clock to various
+The RK3126/RK3128 clock controller generates and supplies clock to various
controllers within the SoC and also implements a reset controller for SoC
peripherals.
Required Properties:
-- compatible: should be "rockchip,rk3128-cru"
+- compatible: should be "rockchip,rk3126-cru" or "rockchip,rk3128-cru"
+ "rockchip,rk3126-cru" - controller compatible with RK3126 SoC.
+ "rockchip,rk3128-cru" - controller compatible with RK3128 SoC.
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
diff --git a/Bindings/clock/samsung,s3c2410-clock.txt b/Bindings/clock/samsung,s3c2410-clock.txt
index 822505e715ae..2632d3f13004 100644
--- a/Bindings/clock/samsung,s3c2410-clock.txt
+++ b/Bindings/clock/samsung,s3c2410-clock.txt
@@ -46,5 +46,4 @@ Example: UART controller node that consumes the clock generated by the clock
interrupts = <1 23 3 4>, <1 23 4 4>;
clock-names = "uart", "clk_uart_baud2";
clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>;
- status = "disabled";
};
diff --git a/Bindings/clock/samsung,s3c2412-clock.txt b/Bindings/clock/samsung,s3c2412-clock.txt
index 2b430960ba47..21a8c23e658f 100644
--- a/Bindings/clock/samsung,s3c2412-clock.txt
+++ b/Bindings/clock/samsung,s3c2412-clock.txt
@@ -46,5 +46,4 @@ Example: UART controller node that consumes the clock generated by the clock
clock-names = "uart", "clk_uart_baud2", "clk_uart_baud3";
clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
<&clocks SCLK_UART>;
- status = "disabled";
};
diff --git a/Bindings/clock/samsung,s3c2443-clock.txt b/Bindings/clock/samsung,s3c2443-clock.txt
index e67bb05478af..985c0f574e9a 100644
--- a/Bindings/clock/samsung,s3c2443-clock.txt
+++ b/Bindings/clock/samsung,s3c2443-clock.txt
@@ -52,5 +52,4 @@ Example: UART controller node that consumes the clock generated by the clock
"clk_uart_baud3";
clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
<&clocks SCLK_UART>;
- status = "disabled";
};
diff --git a/Bindings/clock/samsung,s3c64xx-clock.txt b/Bindings/clock/samsung,s3c64xx-clock.txt
index fa171dc4bd3c..872ee8e0f041 100644
--- a/Bindings/clock/samsung,s3c64xx-clock.txt
+++ b/Bindings/clock/samsung,s3c64xx-clock.txt
@@ -73,5 +73,4 @@ Example: UART controller node that consumes the clock generated by the clock
"clk_uart_baud3";
clocks = <&clock PCLK_UART0>, <&clocks PCLK_UART0>,
<&clock SCLK_UART>;
- status = "disabled";
};
diff --git a/Bindings/clock/samsung,s5pv210-clock.txt b/Bindings/clock/samsung,s5pv210-clock.txt
index effd9401c133..15b48e20a061 100644
--- a/Bindings/clock/samsung,s5pv210-clock.txt
+++ b/Bindings/clock/samsung,s5pv210-clock.txt
@@ -74,5 +74,4 @@ Example: UART controller node that consumes the clock generated by the clock
"clk_uart_baud1";
clocks = <&clocks UART0>, <&clocks UART0>,
<&clocks SCLK_UART0>;
- status = "disabled";
};
diff --git a/Bindings/clock/silabs,si5351.txt b/Bindings/clock/silabs,si5351.txt
index 28b28309f535..a6c4ef343b44 100644
--- a/Bindings/clock/silabs,si5351.txt
+++ b/Bindings/clock/silabs,si5351.txt
@@ -12,7 +12,11 @@ generators can be found in [1].
==I2C device node==
Required properties:
-- compatible: shall be one of "silabs,si5351{a,a-msop,b,c}".
+- compatible: shall be one of the following:
+ "silabs,si5351a" - Si5351a, QFN20 package
+ "silabs,si5351a-msop" - Si5351a, MSOP10 package
+ "silabs,si5351b" - Si5351b, QFN20 package
+ "silabs,si5351c" - Si5351c, QFN20 package
- reg: i2c device address, shall be 0x60 or 0x61.
- #clock-cells: from common clock binding; shall be set to 1.
- clocks: from common clock binding; list of parent clock
diff --git a/Bindings/clock/snps,hsdk-pll-clock.txt b/Bindings/clock/snps,hsdk-pll-clock.txt
new file mode 100644
index 000000000000..c56c7553c730
--- /dev/null
+++ b/Bindings/clock/snps,hsdk-pll-clock.txt
@@ -0,0 +1,28 @@
+Binding for the HSDK Generic PLL clock
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible: should be "snps,hsdk-<name>-pll-clock"
+ "snps,hsdk-core-pll-clock"
+ "snps,hsdk-gp-pll-clock"
+ "snps,hsdk-hdmi-pll-clock"
+- reg : should contain base register location and length.
+- clocks: shall be the input parent clock phandle for the PLL.
+- #clock-cells: from common clock binding; Should always be set to 0.
+
+Example:
+ input_clk: input-clk {
+ clock-frequency = <33333333>;
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ cpu_clk: cpu-clk@0 {
+ compatible = "snps,hsdk-core-pll-clock";
+ reg = <0x00 0x10>;
+ #clock-cells = <0>;
+ clocks = <&input_clk>;
+ };
diff --git a/Bindings/clock/snps,pll-clock.txt b/Bindings/clock/snps,pll-clock.txt
new file mode 100644
index 000000000000..11fe4876612c
--- /dev/null
+++ b/Bindings/clock/snps,pll-clock.txt
@@ -0,0 +1,28 @@
+Binding for the AXS10X Generic PLL clock
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible: should be "snps,axs10x-<name>-pll-clock"
+ "snps,axs10x-arc-pll-clock"
+ "snps,axs10x-pgu-pll-clock"
+- reg: should always contain 2 pairs address - length: first for PLL config
+registers and second for corresponding LOCK CGU register.
+- clocks: shall be the input parent clock phandle for the PLL.
+- #clock-cells: from common clock binding; Should always be set to 0.
+
+Example:
+ input-clk: input-clk {
+ clock-frequency = <33333333>;
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ core-clk: core-clk@80 {
+ compatible = "snps,axs10x-arc-pll-clock";
+ reg = <0x80 0x10>, <0x100 0x10>;
+ #clock-cells = <0>;
+ clocks = <&input-clk>;
+ };
diff --git a/Bindings/clock/st,stm32h7-rcc.txt b/Bindings/clock/st,stm32h7-rcc.txt
new file mode 100644
index 000000000000..cac24ee10b72
--- /dev/null
+++ b/Bindings/clock/st,stm32h7-rcc.txt
@@ -0,0 +1,71 @@
+STMicroelectronics STM32H7 Reset and Clock Controller
+=====================================================
+
+The RCC IP is both a reset and a clock controller.
+
+Please refer to clock-bindings.txt for common clock controller binding usage.
+Please also refer to reset.txt for common reset controller binding usage.
+
+Required properties:
+- compatible: Should be:
+ "st,stm32h743-rcc"
+
+- reg: should be register base and length as documented in the
+ datasheet
+
+- #reset-cells: 1, see below
+
+- #clock-cells : from common clock binding; shall be set to 1
+
+- clocks: External oscillator clock phandle
+ - high speed external clock signal (HSE)
+ - low speed external clock signal (LSE)
+ - external I2S clock (I2S_CKIN)
+
+Optional properties:
+- st,syscfg: phandle for pwrcfg, mandatory to disable/enable backup domain
+ write protection (RTC clock).
+
+Example:
+
+ rcc: reset-clock-controller@58024400 {
+ compatible = "st,stm32h743-rcc", "st,stm32-rcc";
+ reg = <0x58024400 0x400>;
+ #reset-cells = <1>;
+ #clock-cells = <1>;
+ clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s_ckin>;
+
+ st,syscfg = <&pwrcfg>;
+};
+
+The peripheral clock consumer should specify the desired clock by
+having the clock ID in its "clocks" phandle cell.
+
+Example:
+
+ timer5: timer@40000c00 {
+ compatible = "st,stm32-timer";
+ reg = <0x40000c00 0x400>;
+ interrupts = <50>;
+ clocks = <&rcc TIM5_CK>;
+ };
+
+Specifying softreset control of devices
+=======================================
+
+Device nodes should specify the reset channel required in their "resets"
+property, containing a phandle to the reset device node and an index specifying
+which channel to use.
+The index is the bit number within the RCC registers bank, starting from RCC
+base address.
+It is calculated as: index = register_offset / 4 * 32 + bit_offset.
+Where bit_offset is the bit offset within the register.
+
+For example, for CRC reset:
+ crc = AHB4RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x88 / 4 * 32 + 19 = 1107
+
+Example:
+
+ timer2 {
+ resets = <&rcc STM32H7_APB1L_RESET(TIM2)>;
+ };
diff --git a/Bindings/clock/sunxi-ccu.txt b/Bindings/clock/sunxi-ccu.txt
index df9fad58facd..7eda08eb8a1e 100644
--- a/Bindings/clock/sunxi-ccu.txt
+++ b/Bindings/clock/sunxi-ccu.txt
@@ -3,18 +3,24 @@ Allwinner Clock Control Unit Binding
Required properties :
- compatible: must contain one of the following compatibles:
+ - "allwinner,sun4i-a10-ccu"
+ - "allwinner,sun5i-a10s-ccu"
+ - "allwinner,sun5i-a13-ccu"
- "allwinner,sun6i-a31-ccu"
+ - "allwinner,sun7i-a20-ccu"
- "allwinner,sun8i-a23-ccu"
- "allwinner,sun8i-a33-ccu"
- "allwinner,sun8i-a83t-ccu"
- "allwinner,sun8i-a83t-r-ccu"
- "allwinner,sun8i-h3-ccu"
- "allwinner,sun8i-h3-r-ccu"
++ - "allwinner,sun8i-r40-ccu"
- "allwinner,sun8i-v3s-ccu"
- "allwinner,sun9i-a80-ccu"
- "allwinner,sun50i-a64-ccu"
- "allwinner,sun50i-a64-r-ccu"
- "allwinner,sun50i-h5-ccu"
+ - "nextthing,gr8-ccu"
- reg: Must contain the registers base address and length
- clocks: phandle to the oscillators feeding the CCU. Two are needed:
diff --git a/Bindings/clock/ti,sci-clk.txt b/Bindings/clock/ti,sci-clk.txt
index 1e884c40ab50..4e59dc6b1778 100644
--- a/Bindings/clock/ti,sci-clk.txt
+++ b/Bindings/clock/ti,sci-clk.txt
@@ -14,10 +14,9 @@ Required properties:
- compatible: Must be "ti,k2g-sci-clk"
- #clock-cells: Shall be 2.
In clock consumers, this cell represents the device ID and clock ID
- exposed by the PM firmware. The assignments can be found in the header
- files <dt-bindings/genpd/<soc>.h> (which covers the device IDs) and
- <dt-bindings/clock/<soc>.h> (which covers the clock IDs), where <soc>
- is the SoC involved, for example 'k2g'.
+ exposed by the PM firmware. The list of valid values for the device IDs
+ and clocks IDs for 66AK2G SoC are documented at
+ http://processors.wiki.ti.com/index.php/TISCI#66AK2G02_Data
Examples:
--------
diff --git a/Bindings/clock/ti/dra7-atl.txt b/Bindings/clock/ti/dra7-atl.txt
index 585e8c191f50..10f7047755f3 100644
--- a/Bindings/clock/ti/dra7-atl.txt
+++ b/Bindings/clock/ti/dra7-atl.txt
@@ -81,13 +81,11 @@ atl: atl@4843c000 {
<&atl_clkin2_ck>, <&atl_clkin3_ck>;
clocks = <&atl_gfclk_mux>;
clock-names = "fck";
- status = "disabled";
};
#include <dt-bindings/clk/ti-dra7-atl.h>
&atl {
- status = "okay";
atl2 {
bws = <DRA7_ATL_WS_MCASP2_FSX>;
diff --git a/Bindings/clock/uniphier-clock.txt b/Bindings/clock/uniphier-clock.txt
index 812163060fa3..7b5f602765fe 100644
--- a/Bindings/clock/uniphier-clock.txt
+++ b/Bindings/clock/uniphier-clock.txt
@@ -6,7 +6,6 @@ System clock
Required properties:
- compatible: should be one of the following:
- "socionext,uniphier-sld3-clock" - for sLD3 SoC.
"socionext,uniphier-ld4-clock" - for LD4 SoC.
"socionext,uniphier-pro4-clock" - for Pro4 SoC.
"socionext,uniphier-sld8-clock" - for sLD8 SoC.
@@ -14,6 +13,7 @@ Required properties:
"socionext,uniphier-pxs2-clock" - for PXs2/LD6b SoC.
"socionext,uniphier-ld11-clock" - for LD11 SoC.
"socionext,uniphier-ld20-clock" - for LD20 SoC.
+ "socionext,uniphier-pxs3-clock" - for PXs3 SoC
- #clock-cells: should be 1.
Example:
@@ -48,7 +48,6 @@ Media I/O (MIO) clock, SD clock
Required properties:
- compatible: should be one of the following:
- "socionext,uniphier-sld3-mio-clock" - for sLD3 SoC.
"socionext,uniphier-ld4-mio-clock" - for LD4 SoC.
"socionext,uniphier-pro4-mio-clock" - for Pro4 SoC.
"socionext,uniphier-sld8-mio-clock" - for sLD8 SoC.
@@ -56,6 +55,7 @@ Required properties:
"socionext,uniphier-pxs2-sd-clock" - for PXs2/LD6b SoC.
"socionext,uniphier-ld11-mio-clock" - for LD11 SoC.
"socionext,uniphier-ld20-sd-clock" - for LD20 SoC.
+ "socionext,uniphier-pxs3-sd-clock" - for PXs3 SoC
- #clock-cells: should be 1.
Example:
@@ -82,11 +82,9 @@ Provided clocks:
8: USB2 ch0 host
9: USB2 ch1 host
10: USB2 ch2 host
-11: USB2 ch3 host
12: USB2 ch0 PHY
13: USB2 ch1 PHY
14: USB2 ch2 PHY
-15: USB2 ch3 PHY
Peripheral clock
@@ -94,7 +92,6 @@ Peripheral clock
Required properties:
- compatible: should be one of the following:
- "socionext,uniphier-sld3-peri-clock" - for sLD3 SoC.
"socionext,uniphier-ld4-peri-clock" - for LD4 SoC.
"socionext,uniphier-pro4-peri-clock" - for Pro4 SoC.
"socionext,uniphier-sld8-peri-clock" - for sLD8 SoC.
@@ -102,6 +99,7 @@ Required properties:
"socionext,uniphier-pxs2-peri-clock" - for PXs2/LD6b SoC.
"socionext,uniphier-ld11-peri-clock" - for LD11 SoC.
"socionext,uniphier-ld20-peri-clock" - for LD20 SoC.
+ "socionext,uniphier-pxs3-peri-clock" - for PXs3 SoC
- #clock-cells: should be 1.
Example:
diff --git a/Bindings/clock/zx296702-clk.txt b/Bindings/clock/zx296702-clk.txt
index 750442b65505..e85ecb510d56 100644
--- a/Bindings/clock/zx296702-clk.txt
+++ b/Bindings/clock/zx296702-clk.txt
@@ -31,5 +31,4 @@ uart0: serial@0x09405000 {
reg = <0x09405000 0x1000>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&lsp1clk ZX296702_UART0_PCLK>;
- status = "disabled";
};
diff --git a/Bindings/clock/zx296718-clk.txt b/Bindings/clock/zx296718-clk.txt
index 4ad703808407..3a46bf0b2540 100644
--- a/Bindings/clock/zx296718-clk.txt
+++ b/Bindings/clock/zx296718-clk.txt
@@ -34,5 +34,4 @@ usbphy0:usb-phy0 {
#phy-cells = <0>;
clocks = <&topclk USB20_PHY_CLK>;
clock-names = "phyclk";
- status = "okay";
};
diff --git a/Bindings/cpufreq/cpufreq-mediatek.txt b/Bindings/cpufreq/cpufreq-mediatek.txt
new file mode 100644
index 000000000000..f6403089edcf
--- /dev/null
+++ b/Bindings/cpufreq/cpufreq-mediatek.txt
@@ -0,0 +1,247 @@
+Binding for MediaTek's CPUFreq driver
+=====================================
+
+Required properties:
+- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
+- clock-names: Should contain the following:
+ "cpu" - The multiplexer for clock input of CPU cluster.
+ "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock
+ source (usually MAINPLL) when the original CPU PLL is under
+ transition and not stable yet.
+ Please refer to Documentation/devicetree/bindings/clk/clock-bindings.txt for
+ generic clock consumer properties.
+- operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp.txt
+ for detail.
+- proc-supply: Regulator for Vproc of CPU cluster.
+
+Optional properties:
+- sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
+ needs to do "voltage tracking" to step by step scale up/down Vproc and
+ Vsram to fit SoC specific needs. When absent, the voltage scaling
+ flow is handled by hardware, hence no software "voltage tracking" is
+ needed.
+- #cooling-cells:
+- cooling-min-level:
+- cooling-max-level:
+ Please refer to Documentation/devicetree/bindings/thermal/thermal.txt
+ for detail.
+
+Example 1 (MT7623 SoC):
+
+ cpu_opp_table: opp_table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-598000000 {
+ opp-hz = /bits/ 64 <598000000>;
+ opp-microvolt = <1050000>;
+ };
+
+ opp-747500000 {
+ opp-hz = /bits/ 64 <747500000>;
+ opp-microvolt = <1050000>;
+ };
+
+ opp-1040000000 {
+ opp-hz = /bits/ 64 <1040000000>;
+ opp-microvolt = <1150000>;
+ };
+
+ opp-1196000000 {
+ opp-hz = /bits/ 64 <1196000000>;
+ opp-microvolt = <1200000>;
+ };
+
+ opp-1300000000 {
+ opp-hz = /bits/ 64 <1300000000>;
+ opp-microvolt = <1300000>;
+ };
+ };
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x0>;
+ clocks = <&infracfg CLK_INFRA_CPUSEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cpu_opp_table>;
+ #cooling-cells = <2>;
+ cooling-min-level = <0>;
+ cooling-max-level = <7>;
+ };
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x1>;
+ operating-points-v2 = <&cpu_opp_table>;
+ };
+ cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x2>;
+ operating-points-v2 = <&cpu_opp_table>;
+ };
+ cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x3>;
+ operating-points-v2 = <&cpu_opp_table>;
+ };
+
+Example 2 (MT8173 SoC):
+ cpu_opp_table_a: opp_table_a {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-507000000 {
+ opp-hz = /bits/ 64 <507000000>;
+ opp-microvolt = <859000>;
+ };
+
+ opp-702000000 {
+ opp-hz = /bits/ 64 <702000000>;
+ opp-microvolt = <908000>;
+ };
+
+ opp-1001000000 {
+ opp-hz = /bits/ 64 <1001000000>;
+ opp-microvolt = <983000>;
+ };
+
+ opp-1105000000 {
+ opp-hz = /bits/ 64 <1105000000>;
+ opp-microvolt = <1009000>;
+ };
+
+ opp-1183000000 {
+ opp-hz = /bits/ 64 <1183000000>;
+ opp-microvolt = <1028000>;
+ };
+
+ opp-1404000000 {
+ opp-hz = /bits/ 64 <1404000000>;
+ opp-microvolt = <1083000>;
+ };
+
+ opp-1508000000 {
+ opp-hz = /bits/ 64 <1508000000>;
+ opp-microvolt = <1109000>;
+ };
+
+ opp-1573000000 {
+ opp-hz = /bits/ 64 <1573000000>;
+ opp-microvolt = <1125000>;
+ };
+ };
+
+ cpu_opp_table_b: opp_table_b {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-507000000 {
+ opp-hz = /bits/ 64 <507000000>;
+ opp-microvolt = <828000>;
+ };
+
+ opp-702000000 {
+ opp-hz = /bits/ 64 <702000000>;
+ opp-microvolt = <867000>;
+ };
+
+ opp-1001000000 {
+ opp-hz = /bits/ 64 <1001000000>;
+ opp-microvolt = <927000>;
+ };
+
+ opp-1209000000 {
+ opp-hz = /bits/ 64 <1209000000>;
+ opp-microvolt = <968000>;
+ };
+
+ opp-1404000000 {
+ opp-hz = /bits/ 64 <1007000000>;
+ opp-microvolt = <1028000>;
+ };
+
+ opp-1612000000 {
+ opp-hz = /bits/ 64 <1612000000>;
+ opp-microvolt = <1049000>;
+ };
+
+ opp-1807000000 {
+ opp-hz = /bits/ 64 <1807000000>;
+ opp-microvolt = <1089000>;
+ };
+
+ opp-1989000000 {
+ opp-hz = /bits/ 64 <1989000000>;
+ opp-microvolt = <1125000>;
+ };
+ };
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x000>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&infracfg CLK_INFRA_CA53SEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cpu_opp_table_a>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x001>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&infracfg CLK_INFRA_CA53SEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cpu_opp_table_a>;
+ };
+
+ cpu2: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x100>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&infracfg CLK_INFRA_CA57SEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cpu_opp_table_b>;
+ };
+
+ cpu3: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x101>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&infracfg CLK_INFRA_CA57SEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cpu_opp_table_b>;
+ };
+
+ &cpu0 {
+ proc-supply = <&mt6397_vpca15_reg>;
+ };
+
+ &cpu1 {
+ proc-supply = <&mt6397_vpca15_reg>;
+ };
+
+ &cpu2 {
+ proc-supply = <&da9211_vcpu_reg>;
+ sram-supply = <&mt6397_vsramca7_reg>;
+ };
+
+ &cpu3 {
+ proc-supply = <&da9211_vcpu_reg>;
+ sram-supply = <&mt6397_vsramca7_reg>;
+ };
diff --git a/Bindings/crypto/artpec6-crypto.txt b/Bindings/crypto/artpec6-crypto.txt
new file mode 100644
index 000000000000..d9cca4875bd6
--- /dev/null
+++ b/Bindings/crypto/artpec6-crypto.txt
@@ -0,0 +1,16 @@
+Axis crypto engine with PDMA interface.
+
+Required properties:
+- compatible : Should be one of the following strings:
+ "axis,artpec6-crypto" for the version in the Axis ARTPEC-6 SoC
+ "axis,artpec7-crypto" for the version in the Axis ARTPEC-7 SoC.
+- reg: Base address and size for the PDMA register area.
+- interrupts: Interrupt handle for the PDMA interrupt line.
+
+Example:
+
+crypto@f4264000 {
+ compatible = "axis,artpec6-crypto";
+ reg = <0xf4264000 0x1000>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+};
diff --git a/Bindings/crypto/atmel-crypto.txt b/Bindings/crypto/atmel-crypto.txt
index f2aab3dc2b52..7de1a9674c70 100644
--- a/Bindings/crypto/atmel-crypto.txt
+++ b/Bindings/crypto/atmel-crypto.txt
@@ -66,3 +66,16 @@ sha@f8034000 {
dmas = <&dma1 2 17>;
dma-names = "tx";
};
+
+* Eliptic Curve Cryptography (I2C)
+
+Required properties:
+- compatible : must be "atmel,atecc508a".
+- reg: I2C bus address of the device.
+- clock-frequency: must be present in the i2c controller node.
+
+Example:
+atecc508a@C0 {
+ compatible = "atmel,atecc508a";
+ reg = <0xC0>;
+};
diff --git a/Bindings/crypto/fsl-dcp.txt b/Bindings/crypto/fsl-dcp.txt
index 6949e50f1f16..76a0b4e80e83 100644
--- a/Bindings/crypto/fsl-dcp.txt
+++ b/Bindings/crypto/fsl-dcp.txt
@@ -13,5 +13,4 @@ dcp@80028000 {
compatible = "fsl,imx28-dcp", "fsl,imx23-dcp";
reg = <0x80028000 0x2000>;
interrupts = <52 53>;
- status = "okay";
};
diff --git a/Bindings/crypto/inside-secure-safexcel.txt b/Bindings/crypto/inside-secure-safexcel.txt
index 941bb6a6fb13..fbc07d12322f 100644
--- a/Bindings/crypto/inside-secure-safexcel.txt
+++ b/Bindings/crypto/inside-secure-safexcel.txt
@@ -23,5 +23,4 @@ Example:
interrupt-names = "mem", "ring0", "ring1", "ring2", "ring3",
"eip";
clocks = <&cpm_syscon0 1 26>;
- status = "disabled";
};
diff --git a/Bindings/crypto/marvell-cesa.txt b/Bindings/crypto/marvell-cesa.txt
index c6c6a4a045bd..28d3f2496b89 100644
--- a/Bindings/crypto/marvell-cesa.txt
+++ b/Bindings/crypto/marvell-cesa.txt
@@ -41,5 +41,4 @@ Examples:
clock-names = "cesa0", "cesa1";
marvell,crypto-srams = <&crypto_sram0>, <&crypto_sram1>;
marvell,crypto-sram-size = <0x600>;
- status = "okay";
};
diff --git a/Bindings/crypto/mv_cesa.txt b/Bindings/crypto/mv_cesa.txt
index c0c35f00335b..d9b92e2f3138 100644
--- a/Bindings/crypto/mv_cesa.txt
+++ b/Bindings/crypto/mv_cesa.txt
@@ -29,5 +29,4 @@ Examples:
interrupts = <22>;
marvell,crypto-srams = <&crypto_sram>;
marvell,crypto-sram-size = <0x600>;
- status = "okay";
};
diff --git a/Bindings/crypto/rockchip-crypto.txt b/Bindings/crypto/rockchip-crypto.txt
index 096df34b11c1..5e2ba385b8c9 100644
--- a/Bindings/crypto/rockchip-crypto.txt
+++ b/Bindings/crypto/rockchip-crypto.txt
@@ -25,5 +25,4 @@ Examples:
clock-names = "aclk", "hclk", "sclk", "apb_pclk";
resets = <&cru SRST_CRYPTO>;
reset-names = "crypto-rst";
- status = "okay";
};
diff --git a/Bindings/crypto/st,stm32-hash.txt b/Bindings/crypto/st,stm32-hash.txt
new file mode 100644
index 000000000000..04fc246f02f7
--- /dev/null
+++ b/Bindings/crypto/st,stm32-hash.txt
@@ -0,0 +1,30 @@
+* STMicroelectronics STM32 HASH
+
+Required properties:
+- compatible: Should contain entries for this and backward compatible
+ HASH versions:
+ - "st,stm32f456-hash" for stm32 F456.
+ - "st,stm32f756-hash" for stm32 F756.
+- reg: The address and length of the peripheral registers space
+- interrupts: the interrupt specifier for the HASH
+- clocks: The input clock of the HASH instance
+
+Optional properties:
+- resets: The input reset of the HASH instance
+- dmas: DMA specifiers for the HASH. See the DMA client binding,
+ Documentation/devicetree/bindings/dma/dma.txt
+- dma-names: DMA request name. Should be "in" if a dma is present.
+- dma-maxburst: Set number of maximum dma burst supported
+
+Example:
+
+hash1: hash@50060400 {
+ compatible = "st,stm32f756-hash";
+ reg = <0x50060400 0x400>;
+ interrupts = <80>;
+ clocks = <&rcc 0 STM32F7_AHB2_CLOCK(HASH)>;
+ resets = <&rcc STM32F7_AHB2_RESET(HASH)>;
+ dmas = <&dma2 7 2 0x400 0x0>;
+ dma-names = "in";
+ dma-maxburst = <0>;
+};
diff --git a/Bindings/devfreq/event/rockchip-dfi.txt b/Bindings/devfreq/event/rockchip-dfi.txt
index f2233138eba9..001dd63979a9 100644
--- a/Bindings/devfreq/event/rockchip-dfi.txt
+++ b/Bindings/devfreq/event/rockchip-dfi.txt
@@ -15,5 +15,4 @@ Example:
rockchip,pmu = <&pmugrf>;
clocks = <&cru PCLK_DDR_MON>;
clock-names = "pclk_ddr_mon";
- status = "disabled";
};
diff --git a/Bindings/devfreq/rk3399_dmc.txt b/Bindings/devfreq/rk3399_dmc.txt
index 7a9e8603c150..d6d2833482c9 100644
--- a/Bindings/devfreq/rk3399_dmc.txt
+++ b/Bindings/devfreq/rk3399_dmc.txt
@@ -205,5 +205,4 @@ Example:
rockchip,phy_lpddr4_ck_cs_drv = <PHY_DRV_ODT_80>;
rockchip,phy_lpddr4_dq_drv = <PHY_DRV_ODT_80>;
rockchip,phy_lpddr4_odt = <PHY_DRV_ODT_60>;
- status = "disabled";
};
diff --git a/Bindings/display/atmel,lcdc.txt b/Bindings/display/atmel,lcdc.txt
index ecb8da063d07..1a21202778ee 100644
--- a/Bindings/display/atmel,lcdc.txt
+++ b/Bindings/display/atmel,lcdc.txt
@@ -34,7 +34,6 @@ Example:
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fb>;
display = <&display0>;
- status = "okay";
#address-cells = <1>;
#size-cells = <1>;
diff --git a/Bindings/display/atmel/hlcdc-dc.txt b/Bindings/display/atmel/hlcdc-dc.txt
index ec94468b35be..82f2acb3d374 100644
--- a/Bindings/display/atmel/hlcdc-dc.txt
+++ b/Bindings/display/atmel/hlcdc-dc.txt
@@ -23,7 +23,6 @@ Example:
interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
clock-names = "periph_clk","sys_clk", "slow_clk";
- status = "disabled";
hlcdc-display-controller {
compatible = "atmel,hlcdc-display-controller";
diff --git a/Bindings/display/bridge/dw_mipi_dsi.txt b/Bindings/display/bridge/dw_mipi_dsi.txt
new file mode 100644
index 000000000000..b13adf30b8d3
--- /dev/null
+++ b/Bindings/display/bridge/dw_mipi_dsi.txt
@@ -0,0 +1,32 @@
+Synopsys DesignWare MIPI DSI host controller
+============================================
+
+This document defines device tree properties for the Synopsys DesignWare MIPI
+DSI host controller. It doesn't constitue a device tree binding specification
+by itself but is meant to be referenced by platform-specific device tree
+bindings.
+
+When referenced from platform device tree bindings the properties defined in
+this document are defined as follows. The platform device tree bindings are
+responsible for defining whether each optional property is used or not.
+
+- reg: Memory mapped base address and length of the DesignWare MIPI DSI
+ host controller registers. (mandatory)
+
+- clocks: References to all the clocks specified in the clock-names property
+ as specified in [1]. (mandatory)
+
+- clock-names:
+ - "pclk" is the peripheral clock for either AHB and APB. (mandatory)
+ - "px_clk" is the pixel clock for the DPI/RGB input. (optional)
+
+- resets: References to all the resets specified in the reset-names property
+ as specified in [2]. (optional)
+
+- reset-names: string reset name, must be "apb" if used. (optional)
+
+- panel or bridge node: see [3]. (mandatory)
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/reset/reset.txt
+[3] Documentation/devicetree/bindings/display/mipi-dsi-bus.txt
diff --git a/Bindings/display/bridge/megachips-stdpxxxx-ge-b850v3-fw.txt b/Bindings/display/bridge/megachips-stdpxxxx-ge-b850v3-fw.txt
index 7baa6582517e..aacc8b92968c 100644
--- a/Bindings/display/bridge/megachips-stdpxxxx-ge-b850v3-fw.txt
+++ b/Bindings/display/bridge/megachips-stdpxxxx-ge-b850v3-fw.txt
@@ -33,7 +33,6 @@ stdp2690-ge-b850v3-fw required properties:
Example:
&mux2_i2c2 {
- status = "okay";
clock-frequency = <100000>;
stdp4028@73 {
diff --git a/Bindings/display/bridge/renesas,dw-hdmi.txt b/Bindings/display/bridge/renesas,dw-hdmi.txt
index 81b68580e199..b1a8929c2536 100644
--- a/Bindings/display/bridge/renesas,dw-hdmi.txt
+++ b/Bindings/display/bridge/renesas,dw-hdmi.txt
@@ -13,6 +13,7 @@ Required properties:
- compatible : Shall contain one or more of
- "renesas,r8a7795-hdmi" for R8A7795 (R-Car H3) compatible HDMI TX
+ - "renesas,r8a7796-hdmi" for R8A7796 (R-Car M3-W) compatible HDMI TX
- "renesas,rcar-gen3-hdmi" for the generic R-Car Gen3 compatible HDMI TX
When compatible with generic versions, nodes must list the SoC-specific
@@ -43,7 +44,6 @@ Example:
clocks = <&cpg CPG_CORE R8A7795_CLK_S0D4>, <&cpg CPG_MOD 729>;
clock-names = "iahb", "isfr";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- status = "disabled";
ports {
#address-cells = <1>;
diff --git a/Bindings/display/exynos/exynos5433-decon.txt b/Bindings/display/exynos/exynos5433-decon.txt
index 549c538b38a5..fc2588292a68 100644
--- a/Bindings/display/exynos/exynos5433-decon.txt
+++ b/Bindings/display/exynos/exynos5433-decon.txt
@@ -25,12 +25,6 @@ Required properties:
size-cells must 1 and 0, respectively.
- port: contains an endpoint node which is connected to the endpoint in the mic
node. The reg value muset be 0.
-- i80-if-timings: specify whether the panel which is connected to decon uses
- i80 lcd interface or mipi video interface. This node contains
- no timing information as that of fimd does. Because there is
- no register in decon to specify i80 interface timing value,
- it is not needed, but make it remain to use same kind of node
- in fimd and exynos7 decon.
Example:
SoC specific DT entry:
@@ -59,9 +53,3 @@ decon: decon@13800000 {
};
};
};
-
-Board specific DT entry:
-&decon {
- i80-if-timings {
- };
-};
diff --git a/Bindings/display/fsl,tcon.txt b/Bindings/display/fsl,tcon.txt
index 6fa4ab668db5..475008747801 100644
--- a/Bindings/display/fsl,tcon.txt
+++ b/Bindings/display/fsl,tcon.txt
@@ -14,5 +14,4 @@ timing-controller@4003d000 {
reg = <0x4003d000 0x1000>;
clocks = <&clks VF610_CLK_TCON0>;
clock-names = "ipg";
- status = "okay";
};
diff --git a/Bindings/display/imx/fsl-imx-drm.txt b/Bindings/display/imx/fsl-imx-drm.txt
index fa01db7eb66c..f79854783c2c 100644
--- a/Bindings/display/imx/fsl-imx-drm.txt
+++ b/Bindings/display/imx/fsl-imx-drm.txt
@@ -116,7 +116,7 @@ Parallel display support
Required properties:
- compatible: Should be "fsl,imx-parallel-display"
Optional properties:
-- interface_pix_fmt: How this display is connected to the
+- interface-pix-fmt: How this display is connected to the
display interface. Currently supported types: "rgb24", "rgb565", "bgr666"
and "lvds666".
- edid: verbatim EDID data block describing attached display.
diff --git a/Bindings/display/marvell,pxa2xx-lcdc.txt b/Bindings/display/marvell,pxa2xx-lcdc.txt
index 309c47f25b87..f79641bd5f18 100644
--- a/Bindings/display/marvell,pxa2xx-lcdc.txt
+++ b/Bindings/display/marvell,pxa2xx-lcdc.txt
@@ -23,7 +23,6 @@ Example:
reg = <0x44000000 0x10000>;
interrupts = <17>;
clocks = <&clks CLK_LCD>;
- status = "okay";
port {
lcdc_out: endpoint {
diff --git a/Bindings/display/panel/innolux,p079zca.txt b/Bindings/display/panel/innolux,p079zca.txt
index 5c70a8380e58..d0f55161579a 100644
--- a/Bindings/display/panel/innolux,p079zca.txt
+++ b/Bindings/display/panel/innolux,p079zca.txt
@@ -18,6 +18,5 @@ Example:
power-supply = <...>;
backlight = <&backlight>;
enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
- status = "okay";
};
};
diff --git a/Bindings/display/renesas,du.txt b/Bindings/display/renesas,du.txt
index c6cb96a4fa93..4bbd1e9bf3be 100644
--- a/Bindings/display/renesas,du.txt
+++ b/Bindings/display/renesas,du.txt
@@ -36,8 +36,10 @@ Required Properties:
When supplied they must be named "dclkin.x" with "x" being the input
clock numerical index.
- - vsps: A list of phandles to the VSP nodes that handle the memory
- interfaces for the DU channels.
+ - vsps: A list of phandle and channel index tuples to the VSPs that handle
+ the memory interfaces for the DU channels. The phandle identifies the VSP
+ instance that serves the DU channel, and the channel index identifies the
+ LIF instance in that VSP.
Required nodes:
@@ -59,24 +61,24 @@ corresponding to each DU output.
R8A7796 (M3-W) DPAD HDMI LVDS -
-Example: R8A7790 (R-Car H2) DU
+Example: R8A7795 (R-Car H3) ES2.0 DU
- du: du@feb00000 {
- compatible = "renesas,du-r8a7790";
- reg = <0 0xfeb00000 0 0x70000>,
- <0 0xfeb90000 0 0x1c>,
- <0 0xfeb94000 0 0x1c>;
- reg-names = "du", "lvds.0", "lvds.1";
- interrupt-parent = <&gic>;
- interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>,
- <0 268 IRQ_TYPE_LEVEL_HIGH>,
- <0 269 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&mstp7_clks R8A7790_CLK_DU0>,
- <&mstp7_clks R8A7790_CLK_DU1>,
- <&mstp7_clks R8A7790_CLK_DU2>,
- <&mstp7_clks R8A7790_CLK_LVDS0>,
- <&mstp7_clks R8A7790_CLK_LVDS1>;
- clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1";
+ du: display@feb00000 {
+ compatible = "renesas,du-r8a7795";
+ reg = <0 0xfeb00000 0 0x80000>,
+ <0 0xfeb90000 0 0x14>;
+ reg-names = "du", "lvds.0";
+ interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 724>,
+ <&cpg CPG_MOD 723>,
+ <&cpg CPG_MOD 722>,
+ <&cpg CPG_MOD 721>,
+ <&cpg CPG_MOD 727>;
+ clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0";
+ vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>;
ports {
#address-cells = <1>;
@@ -89,12 +91,19 @@ Example: R8A7790 (R-Car H2) DU
};
port@1 {
reg = <1>;
- du_out_lvds0: endpoint {
+ du_out_hdmi0: endpoint {
+ remote-endpoint = <&dw_hdmi0_in>;
};
};
port@2 {
reg = <2>;
- du_out_lvds1: endpoint {
+ du_out_hdmi1: endpoint {
+ remote-endpoint = <&dw_hdmi1_in>;
+ };
+ };
+ port@3 {
+ reg = <3>;
+ du_out_lvds0: endpoint {
};
};
};
diff --git a/Bindings/display/repaper.txt b/Bindings/display/repaper.txt
new file mode 100644
index 000000000000..f5f9f9cf6a25
--- /dev/null
+++ b/Bindings/display/repaper.txt
@@ -0,0 +1,52 @@
+Pervasive Displays RePaper branded e-ink displays
+
+Required properties:
+- compatible: "pervasive,e1144cs021" for 1.44" display
+ "pervasive,e1190cs021" for 1.9" display
+ "pervasive,e2200cs021" for 2.0" display
+ "pervasive,e2271cs021" for 2.7" display
+
+- panel-on-gpios: Timing controller power control
+- discharge-gpios: Discharge control
+- reset-gpios: RESET pin
+- busy-gpios: BUSY pin
+
+Required property for e2271cs021:
+- border-gpios: Border control
+
+The node for this driver must be a child node of a SPI controller, hence
+all mandatory properties described in ../spi/spi-bus.txt must be specified.
+
+Optional property:
+- pervasive,thermal-zone: name of thermometer's thermal zone
+
+Example:
+
+ display_temp: lm75@48 {
+ compatible = "lm75b";
+ reg = <0x48>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ thermal-zones {
+ display {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&display_temp>;
+ };
+ };
+
+ papirus27@0{
+ compatible = "pervasive,e2271cs021";
+ reg = <0>;
+
+ spi-max-frequency = <8000000>;
+
+ panel-on-gpios = <&gpio 23 0>;
+ border-gpios = <&gpio 14 0>;
+ discharge-gpios = <&gpio 15 0>;
+ reset-gpios = <&gpio 24 0>;
+ busy-gpios = <&gpio 25 0>;
+
+ pervasive,thermal-zone = "display";
+ };
diff --git a/Bindings/display/rockchip/analogix_dp-rockchip.txt b/Bindings/display/rockchip/analogix_dp-rockchip.txt
index 47665a12786f..43561584c13a 100644
--- a/Bindings/display/rockchip/analogix_dp-rockchip.txt
+++ b/Bindings/display/rockchip/analogix_dp-rockchip.txt
@@ -59,7 +59,6 @@ Example:
pinctrl-names = "default";
pinctrl-0 = <&edp_hpd>;
- status = "disabled";
ports {
#address-cells = <1>;
diff --git a/Bindings/display/rockchip/dw_hdmi-rockchip.txt b/Bindings/display/rockchip/dw_hdmi-rockchip.txt
index 046076c6b277..adc94fc3c9f8 100644
--- a/Bindings/display/rockchip/dw_hdmi-rockchip.txt
+++ b/Bindings/display/rockchip/dw_hdmi-rockchip.txt
@@ -11,7 +11,9 @@ following device-specific properties.
Required properties:
-- compatible: Shall contain "rockchip,rk3288-dw-hdmi".
+- compatible: should be one of the following:
+ "rockchip,rk3288-dw-hdmi"
+ "rockchip,rk3399-dw-hdmi"
- reg: See dw_hdmi.txt.
- reg-io-width: See dw_hdmi.txt. Shall be 4.
- interrupts: HDMI interrupt number
@@ -30,7 +32,8 @@ Optional properties
I2C master controller.
- clock-names: See dw_hdmi.txt. The "cec" clock is optional.
- clock-names: May contain "cec" as defined in dw_hdmi.txt.
-
+- clock-names: May contain "grf", power for grf io.
+- clock-names: May contain "vpll", external clock for some hdmi phy.
Example:
@@ -43,7 +46,6 @@ hdmi: hdmi@ff980000 {
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
clock-names = "iahb", "isfr";
- status = "disabled";
ports {
hdmi_in: port {
#address-cells = <1>;
diff --git a/Bindings/display/rockchip/dw_mipi_dsi_rockchip.txt b/Bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
index 543b07435f4f..6bb59ab39f2f 100644
--- a/Bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
+++ b/Bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
@@ -36,7 +36,6 @@ Example:
resets = <&cru SRST_MIPIDSI0>;
reset-names = "apb";
rockchip,grf = <&grf>;
- status = "okay";
ports {
#address-cells = <1>;
@@ -65,6 +64,5 @@ Example:
pinctrl-names = "default";
pinctrl-0 = <&lcd_en>;
backlight = <&backlight>;
- status = "okay";
};
};
diff --git a/Bindings/display/rockchip/inno_hdmi-rockchip.txt b/Bindings/display/rockchip/inno_hdmi-rockchip.txt
index 8096a29f9776..cec21714f0e0 100644
--- a/Bindings/display/rockchip/inno_hdmi-rockchip.txt
+++ b/Bindings/display/rockchip/inno_hdmi-rockchip.txt
@@ -25,7 +25,6 @@ hdmi: hdmi@20034000 {
clock-names = "pclk";
pinctrl-names = "default";
pinctrl-0 = <&hdmi_ctl>;
- status = "disabled";
hdmi_in: port {
#address-cells = <1>;
diff --git a/Bindings/display/rockchip/rockchip-vop.txt b/Bindings/display/rockchip/rockchip-vop.txt
index 9eb3f0a2a078..5d835d9c1ba8 100644
--- a/Bindings/display/rockchip/rockchip-vop.txt
+++ b/Bindings/display/rockchip/rockchip-vop.txt
@@ -8,8 +8,12 @@ Required properties:
- compatible: value should be one of the following
"rockchip,rk3036-vop";
"rockchip,rk3288-vop";
+ "rockchip,rk3368-vop";
+ "rockchip,rk3366-vop";
"rockchip,rk3399-vop-big";
"rockchip,rk3399-vop-lit";
+ "rockchip,rk3228-vop";
+ "rockchip,rk3328-vop";
- interrupts: should contain a list of all VOP IP block interrupts in the
order: VSYNC, LCD_SYSTEM. The interrupt specifier
diff --git a/Bindings/display/simple-framebuffer-sunxi.txt b/Bindings/display/simple-framebuffer-sunxi.txt
index c46ba641a1df..a9168ae6946c 100644
--- a/Bindings/display/simple-framebuffer-sunxi.txt
+++ b/Bindings/display/simple-framebuffer-sunxi.txt
@@ -28,6 +28,5 @@ chosen {
allwinner,pipeline = "de_be0-lcd0-hdmi";
clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
<&ahb_gates 44>;
- status = "disabled";
};
};
diff --git a/Bindings/display/sitronix,st7586.txt b/Bindings/display/sitronix,st7586.txt
new file mode 100644
index 000000000000..1d0dad1210d3
--- /dev/null
+++ b/Bindings/display/sitronix,st7586.txt
@@ -0,0 +1,22 @@
+Sitronix ST7586 display panel
+
+Required properties:
+- compatible: "lego,ev3-lcd".
+- a0-gpios: The A0 signal (since this binding is for serial mode, this is
+ the pin labeled D1 on the controller, not the pin labeled A0)
+- reset-gpios: Reset pin
+
+The node for this driver must be a child node of a SPI controller, hence
+all mandatory properties described in ../spi/spi-bus.txt must be specified.
+
+Optional properties:
+- rotation: panel rotation in degrees counter clockwise (0,90,180,270)
+
+Example:
+ display@0{
+ compatible = "lego,ev3-lcd";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+ a0-gpios = <&gpio 43 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio 80 GPIO_ACTIVE_HIGH>;
+ };
diff --git a/Bindings/display/st,stm32-ltdc.txt b/Bindings/display/st,stm32-ltdc.txt
index 8e1476941c0f..74b5ac7b26d6 100644
--- a/Bindings/display/st,stm32-ltdc.txt
+++ b/Bindings/display/st,stm32-ltdc.txt
@@ -1,7 +1,6 @@
* STMicroelectronics STM32 lcd-tft display controller
- ltdc: lcd-tft display controller host
- must be a sub-node of st-display-subsystem
Required properties:
- compatible: "st,stm32-ltdc"
- reg: Physical base address of the IP registers and length of memory mapped region.
@@ -13,8 +12,40 @@
Required nodes:
- Video port for RGB output.
-Example:
+* STMicroelectronics STM32 DSI controller specific extensions to Synopsys
+ DesignWare MIPI DSI host controller
+The STMicroelectronics STM32 DSI controller uses the Synopsys DesignWare MIPI
+DSI host controller. For all mandatory properties & nodes, please refer
+to the related documentation in [5].
+
+Mandatory properties specific to STM32 DSI:
+- #address-cells: Should be <1>.
+- #size-cells: Should be <0>.
+- compatible: "st,stm32-dsi".
+- clock-names:
+ - phy pll reference clock string name, must be "ref".
+- resets: see [5].
+- reset-names: see [5].
+
+Mandatory nodes specific to STM32 DSI:
+- ports: A node containing DSI input & output port nodes with endpoint
+ definitions as documented in [3] & [4].
+ - port@0: DSI input port node, connected to the ltdc rgb output port.
+ - port@1: DSI output port node, connected to a panel or a bridge input port.
+- panel or bridge node: A node containing the panel or bridge description as
+ documented in [6].
+ - port: panel or bridge port node, connected to the DSI output port (port@1).
+
+Note: You can find more documentation in the following references
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/reset/reset.txt
+[3] Documentation/devicetree/bindings/media/video-interfaces.txt
+[4] Documentation/devicetree/bindings/graph.txt
+[5] Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt
+[6] Documentation/devicetree/bindings/display/mipi-dsi-bus.txt
+
+Example 1: RGB panel
/ {
...
soc {
@@ -34,3 +65,73 @@ Example:
};
};
};
+
+Example 2: DSI panel
+
+/ {
+ ...
+ soc {
+ ...
+ ltdc: display-controller@40016800 {
+ compatible = "st,stm32-ltdc";
+ reg = <0x40016800 0x200>;
+ interrupts = <88>, <89>;
+ resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
+ clocks = <&rcc 1 CLK_LCD>;
+ clock-names = "lcd";
+
+ port {
+ ltdc_out_dsi: endpoint {
+ remote-endpoint = <&dsi_in>;
+ };
+ };
+ };
+
+
+ dsi: dsi@40016c00 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-dsi";
+ reg = <0x40016c00 0x800>;
+ clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>;
+ clock-names = "ref", "pclk";
+ resets = <&rcc STM32F4_APB2_RESET(DSI)>;
+ reset-names = "apb";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi_in: endpoint {
+ remote-endpoint = <&ltdc_out_dsi>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi_out: endpoint {
+ remote-endpoint = <&dsi_in_panel>;
+ };
+ };
+
+ };
+
+ panel-dsi@0 {
+ reg = <0>; /* dsi virtual channel (0..3) */
+ compatible = ...;
+ enable-gpios = ...;
+
+ port {
+ dsi_in_panel: endpoint {
+ remote-endpoint = <&dsi_out>;
+ };
+ };
+
+ };
+
+ };
+
+ };
+};
diff --git a/Bindings/display/sunxi/sun4i-drm.txt b/Bindings/display/sunxi/sun4i-drm.txt
index b83e6018041d..92441086caba 100644
--- a/Bindings/display/sunxi/sun4i-drm.txt
+++ b/Bindings/display/sunxi/sun4i-drm.txt
@@ -4,15 +4,33 @@ Allwinner A10 Display Pipeline
The Allwinner A10 Display pipeline is composed of several components
that are going to be documented below:
-For the input port of all components up to the TCON in the display
-pipeline, if there are multiple components, the local endpoint IDs
-must correspond to the index of the upstream block. For example, if
-the remote endpoint is Frontend 1, then the local endpoint ID must
-be 1.
-
-Conversely, for the output ports of the same group, the remote endpoint
-ID must be the index of the local hardware block. If the local backend
-is backend 1, then the remote endpoint ID must be 1.
+For all connections between components up to the TCONs in the display
+pipeline, when there are multiple components of the same type at the
+same depth, the local endpoint ID must be the same as the remote
+component's index. For example, if the remote endpoint is Frontend 1,
+then the local endpoint ID must be 1.
+
+ Frontend 0 [0] ------- [0] Backend 0 [0] ------- [0] TCON 0
+ [1] -- -- [1] [1] -- -- [1]
+ \ / \ /
+ X X
+ / \ / \
+ [0] -- -- [0] [0] -- -- [0]
+ Frontend 1 [1] ------- [1] Backend 1 [1] ------- [1] TCON 1
+
+For a two pipeline system such as the one depicted above, the lines
+represent the connections between the components, while the numbers
+within the square brackets corresponds to the ID of the local endpoint.
+
+The same rule also applies to DE 2.0 mixer-TCON connections:
+
+ Mixer 0 [0] ----------- [0] TCON 0
+ [1] ---- ---- [1]
+ \ /
+ X
+ / \
+ [0] ---- ---- [0]
+ Mixer 1 [1] ----------- [1] TCON 1
HDMI Encoder
------------
@@ -260,7 +278,6 @@ hdmi: hdmi@01c16000 {
<&dma SUN4I_DMA_NORMAL 16>,
<&dma SUN4I_DMA_DEDICATED 24>;
dma-names = "ddc-tx", "ddc-rx", "audio-tx";
- status = "disabled";
ports {
#address-cells = <1>;
diff --git a/Bindings/dma/fsl-edma.txt b/Bindings/dma/fsl-edma.txt
index 191d7bd8a6fe..97e213e07660 100644
--- a/Bindings/dma/fsl-edma.txt
+++ b/Bindings/dma/fsl-edma.txt
@@ -72,5 +72,4 @@ sai2: sai@40031000 {
dma-names = "tx", "rx";
dmas = <&edma0 0 21>,
<&edma0 0 20>;
- status = "disabled";
};
diff --git a/Bindings/dma/mv-xor.txt b/Bindings/dma/mv-xor.txt
index c075f5988135..0ffb4d8766a8 100644
--- a/Bindings/dma/mv-xor.txt
+++ b/Bindings/dma/mv-xor.txt
@@ -30,7 +30,6 @@ xor@d0060900 {
reg = <0xd0060900 0x100
0xd0060b00 0x100>;
clocks = <&coreclk 0>;
- status = "okay";
xor00 {
interrupts = <51>;
diff --git a/Bindings/dma/qcom_adm.txt b/Bindings/dma/qcom_adm.txt
index 9bcab9115982..9d3b2f917b7b 100644
--- a/Bindings/dma/qcom_adm.txt
+++ b/Bindings/dma/qcom_adm.txt
@@ -48,7 +48,6 @@ Each dmas request consists of 3 cells:
Example:
spi4: spi@1a280000 {
- status = "ok";
spi-max-frequency = <50000000>;
pinctrl-0 = <&spi_pins>;
diff --git a/Bindings/dma/renesas,rcar-dmac.txt b/Bindings/dma/renesas,rcar-dmac.txt
index 79a204d50234..891db41e9420 100644
--- a/Bindings/dma/renesas,rcar-dmac.txt
+++ b/Bindings/dma/renesas,rcar-dmac.txt
@@ -25,6 +25,7 @@ Required Properties:
- "renesas,dmac-r8a7794" (R-Car E2)
- "renesas,dmac-r8a7795" (R-Car H3)
- "renesas,dmac-r8a7796" (R-Car M3-W)
+ - "renesas,dmac-r8a77970" (R-Car V3M)
- reg: base address and length of the registers block for the DMAC
diff --git a/Bindings/dma/renesas,usb-dmac.txt b/Bindings/dma/renesas,usb-dmac.txt
index e7780a186a36..1be6941ac1e5 100644
--- a/Bindings/dma/renesas,usb-dmac.txt
+++ b/Bindings/dma/renesas,usb-dmac.txt
@@ -8,6 +8,7 @@ Required Properties:
- "renesas,r8a7793-usb-dmac" (R-Car M2-N)
- "renesas,r8a7794-usb-dmac" (R-Car E2)
- "renesas,r8a7795-usb-dmac" (R-Car H3)
+ - "renesas,r8a7796-usb-dmac" (R-Car M3-W)
- reg: base address and length of the registers block for the DMAC
- interrupts: interrupt specifiers for the DMAC, one for each entry in
interrupt-names.
diff --git a/Bindings/dma/snps-dma.txt b/Bindings/dma/snps-dma.txt
index 4775c66f4508..a122723907ac 100644
--- a/Bindings/dma/snps-dma.txt
+++ b/Bindings/dma/snps-dma.txt
@@ -63,7 +63,6 @@ Example:
compatible = "arm,pl011", "arm,primecell";
reg = <0xe0000000 0x1000>;
interrupts = <0 35 0x4>;
- status = "disabled";
dmas = <&dmahost 12 0 1>,
<&dmahost 13 0 1 0>;
dma-names = "rx", "rx";
diff --git a/Bindings/dma/st_fdma.txt b/Bindings/dma/st_fdma.txt
index 495d853c569b..52cfec9e77ad 100644
--- a/Bindings/dma/st_fdma.txt
+++ b/Bindings/dma/st_fdma.txt
@@ -69,7 +69,6 @@ Example:
sti_uni_player2: sti-uni-player@2 {
compatible = "st,sti-uni-player";
- status = "disabled";
#sound-dai-cells = <0>;
st,syscfg = <&syscfg_core>;
clocks = <&clk_s_d0_flexgen CLK_PCM_2>;
diff --git a/Bindings/dma/ste-dma40.txt b/Bindings/dma/ste-dma40.txt
index 95800ab37bb0..aa7dbd565ad0 100644
--- a/Bindings/dma/ste-dma40.txt
+++ b/Bindings/dma/ste-dma40.txt
@@ -135,5 +135,4 @@ Example:
<&dma 13 0 0x0>; /* Logical - MemToDev */
dma-names = "rx", "rx";
- status = "disabled";
};
diff --git a/Bindings/dma/sun4i-dma.txt b/Bindings/dma/sun4i-dma.txt
index f1634a27a830..3b484380c56a 100644
--- a/Bindings/dma/sun4i-dma.txt
+++ b/Bindings/dma/sun4i-dma.txt
@@ -40,7 +40,6 @@ Example:
clock-names = "ahb", "mod";
dmas = <&dma 1 29>, <&dma 1 28>;
dma-names = "rx", "tx";
- status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
diff --git a/Bindings/dma/sun6i-dma.txt b/Bindings/dma/sun6i-dma.txt
index 6b267045f522..98fbe1a5c6dd 100644
--- a/Bindings/dma/sun6i-dma.txt
+++ b/Bindings/dma/sun6i-dma.txt
@@ -9,6 +9,7 @@ Required properties:
"allwinner,sun8i-a23-dma"
"allwinner,sun8i-a83t-dma"
"allwinner,sun8i-h3-dma"
+ "allwinner,sun8i-v3s-dma"
- reg: Should contain the registers base address and length
- interrupts: Should contain a reference to the interrupt used by this device
- clocks: Should contain a reference to the parent AHB clock
diff --git a/Bindings/dma/ti-dma-crossbar.txt b/Bindings/dma/ti-dma-crossbar.txt
index aead5869a28d..b849a1ed389d 100644
--- a/Bindings/dma/ti-dma-crossbar.txt
+++ b/Bindings/dma/ti-dma-crossbar.txt
@@ -62,7 +62,6 @@ uart1: serial@4806a000 {
interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart1";
clock-frequency = <48000000>;
- status = "disabled";
/* Requesting crossbar input 49 and 50 */
dmas = <&sdma_xbar 49>, <&sdma_xbar 50>;
dma-names = "tx", "rx";
diff --git a/Bindings/dma/ti-edma.txt b/Bindings/dma/ti-edma.txt
index 18090e7226b4..41f0c1a07c56 100644
--- a/Bindings/dma/ti-edma.txt
+++ b/Bindings/dma/ti-edma.txt
@@ -9,7 +9,12 @@ execute the actual DMA tansfer.
eDMA3 Channel Controller
Required properties:
-- compatible: "ti,edma3-tpcc" for the channel controller(s)
+--------------------
+- compatible: Should be:
+ - "ti,edma3-tpcc" for the channel controller(s) on OMAP,
+ AM33xx and AM43xx SoCs.
+ - "ti,k2g-edma3-tpcc", "ti,edma3-tpcc" for the
+ channel controller(s) on 66AK2G.
- #dma-cells: Should be set to <2>. The first number is the DMA request
number and the second is the TC the channel is serviced on.
- reg: Memory map of eDMA CC
@@ -19,8 +24,19 @@ Required properties:
- ti,tptcs: List of TPTCs associated with the eDMA in the following form:
<&tptc_phandle TC_priority_number>. The highest priority is 0.
+SoC-specific Required properties:
+--------------------------------
+The following are mandatory properties for OMAP, AM33xx and AM43xx SoCs only:
+- ti,hwmods: Name of the hwmods associated to the eDMA CC.
+
+The following are mandatory properties for 66AK2G SoCs only:
+- power-domains:Should contain a phandle to a PM domain provider node
+ and an args specifier containing the device id
+ value. This property is as per the binding,
+ Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
+
Optional properties:
-- ti,hwmods: Name of the hwmods associated to the eDMA CC
+-------------------
- ti,edma-memcpy-channels: List of channels allocated to be used for memcpy, iow
these channels will be SW triggered channels. See example.
- ti,edma-reserved-slot-ranges: PaRAM slot ranges which should not be used by
@@ -31,17 +47,34 @@ Optional properties:
eDMA3 Transfer Controller
Required properties:
-- compatible: "ti,edma3-tptc" for the transfer controller(s)
+--------------------
+- compatible: Should be:
+ - "ti,edma3-tptc" for the transfer controller(s) on OMAP,
+ AM33xx and AM43xx SoCs.
+ - "ti,k2g-edma3-tptc", "ti,edma3-tptc" for the
+ transfer controller(s) on 66AK2G.
- reg: Memory map of eDMA TC
- interrupts: Interrupt number for TCerrint.
+SoC-specific Required properties:
+--------------------------------
+The following are mandatory properties for OMAP, AM33xx and AM43xx SoCs only:
+- ti,hwmods: Name of the hwmods associated to the eDMA TC.
+
+The following are mandatory properties for 66AK2G SoCs only:
+- power-domains:Should contain a phandle to a PM domain provider node
+ and an args specifier containing the device id
+ value. This property is as per the binding,
+ Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
+
Optional properties:
-- ti,hwmods: Name of the hwmods associated to the given eDMA TC
+-------------------
- interrupt-names: "edma3_tcerrint"
------------------------------------------------------------------------------
-Example:
+Examples:
+1.
edma: edma@49000000 {
compatible = "ti,edma3-tpcc";
ti,hwmods = "tpcc";
@@ -102,13 +135,64 @@ mcasp0: mcasp@48038000 {
reg-names = "mpu", "dat";
interrupts = <80>, <81>;
interrupt-names = "tx", "rx";
- status = "disabled";
/* DMA channels 8 and 9 executed on eDMA TC2 - high priority queue */
dmas = <&edma 8 2>,
<&edma 9 2>;
dma-names = "tx", "rx";
};
+2.
+edma1: edma@02728000 {
+ compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc";
+ reg = <0x02728000 0x8000>;
+ reg-names = "edma3_cc";
+ interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 219 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 220 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "edma3_ccint", "emda3_mperr",
+ "edma3_ccerrint";
+ dma-requests = <64>;
+ #dma-cells = <2>;
+
+ ti,tptcs = <&edma1_tptc0 7>, <&edma1_tptc1 0>;
+
+ /*
+ * memcpy is disabled, can be enabled with:
+ * ti,edma-memcpy-channels = <12 13 14 15>;
+ * for example.
+ */
+
+ power-domains = <&k2g_pds 0x4f>;
+};
+
+edma1_tptc0: tptc@027b0000 {
+ compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc";
+ reg = <0x027b0000 0x400>;
+ power-domains = <&k2g_pds 0x4f>;
+};
+
+edma1_tptc1: tptc@027b8000 {
+ compatible = "ti, k2g-edma3-tptc", "ti,edma3-tptc";
+ reg = <0x027b8000 0x400>;
+ power-domains = <&k2g_pds 0x4f>;
+};
+
+mmc0: mmc@23000000 {
+ compatible = "ti,k2g-hsmmc", "ti,omap4-hsmmc";
+ reg = <0x23000000 0x400>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_EDGE_RISING>;
+ dmas = <&edma1 24 0>, <&edma1 25 0>;
+ dma-names = "tx", "rx";
+ bus-width = <4>;
+ ti,needs-special-reset;
+ no-1-8-v;
+ max-frequency = <96000000>;
+ power-domains = <&k2g_pds 0xb>;
+ clocks = <&k2g_clks 0xb 1>, <&k2g_clks 0xb 2>;
+ clock-names = "fck", "mmchsdb_fck";
+ status = "disabled";
+};
+
------------------------------------------------------------------------------
DEPRECATED binding, new DTS files must use the ti,edma3-tpcc/ti,edma3-tptc
binding.
diff --git a/Bindings/eeprom/eeprom.txt b/Bindings/eeprom/eeprom.txt
index 5696eb508e95..afc04589eadf 100644
--- a/Bindings/eeprom/eeprom.txt
+++ b/Bindings/eeprom/eeprom.txt
@@ -16,8 +16,12 @@ Required properties:
"renesas,r1ex24002"
+ The following manufacturers values have been deprecated:
+ "at", "at24"
+
If there is no specific driver for <manufacturer>, a generic
- driver based on <type> is selected. Possible types are:
+ device with <type> and manufacturer "atmel" should be used.
+ Possible types are:
"24c00", "24c01", "24c02", "24c04", "24c08", "24c16", "24c32", "24c64",
"24c128", "24c256", "24c512", "24c1024", "spd"
diff --git a/Bindings/extcon/extcon-usbc-cros-ec.txt b/Bindings/extcon/extcon-usbc-cros-ec.txt
new file mode 100644
index 000000000000..8e8625c00dfa
--- /dev/null
+++ b/Bindings/extcon/extcon-usbc-cros-ec.txt
@@ -0,0 +1,24 @@
+ChromeOS EC USB Type-C cable and accessories detection
+
+On ChromeOS systems with USB Type C ports, the ChromeOS Embedded Controller is
+able to detect the state of external accessories such as display adapters
+or USB devices when said accessories are attached or detached.
+
+The node for this device must be under a cros-ec node like google,cros-ec-spi
+or google,cros-ec-i2c.
+
+Required properties:
+- compatible: Should be "google,extcon-usbc-cros-ec".
+- google,usb-port-id: Specifies the USB port ID to use.
+
+Example:
+ cros-ec@0 {
+ compatible = "google,cros-ec-i2c";
+
+ ...
+
+ extcon {
+ compatible = "google,extcon-usbc-cros-ec";
+ google,usb-port-id = <0>;
+ };
+ }
diff --git a/Bindings/fpga/altera-passive-serial.txt b/Bindings/fpga/altera-passive-serial.txt
new file mode 100644
index 000000000000..48478bc07e29
--- /dev/null
+++ b/Bindings/fpga/altera-passive-serial.txt
@@ -0,0 +1,29 @@
+Altera Passive Serial SPI FPGA Manager
+
+Altera FPGAs support a method of loading the bitstream over what is
+referred to as "passive serial".
+The passive serial link is not technically SPI, and might require extra
+circuits in order to play nicely with other SPI slaves on the same bus.
+
+See https://www.altera.com/literature/hb/cyc/cyc_c51013.pdf
+
+Required properties:
+- compatible: Must be one of the following:
+ "altr,fpga-passive-serial",
+ "altr,fpga-arria10-passive-serial"
+- reg: SPI chip select of the FPGA
+- nconfig-gpios: config pin (referred to as nCONFIG in the manual)
+- nstat-gpios: status pin (referred to as nSTATUS in the manual)
+
+Optional properties:
+- confd-gpios: confd pin (referred to as CONF_DONE in the manual)
+
+Example:
+ fpga: fpga@0 {
+ compatible = "altr,fpga-passive-serial";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ nconfig-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
+ nstat-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
+ confd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
+ };
diff --git a/Bindings/fpga/xilinx-pr-decoupler.txt b/Bindings/fpga/xilinx-pr-decoupler.txt
new file mode 100644
index 000000000000..8dcfba926bc7
--- /dev/null
+++ b/Bindings/fpga/xilinx-pr-decoupler.txt
@@ -0,0 +1,36 @@
+Xilinx LogiCORE Partial Reconfig Decoupler Softcore
+
+The Xilinx LogiCORE Partial Reconfig Decoupler manages one or more
+decouplers / fpga bridges.
+The controller can decouple/disable the bridges which prevents signal
+changes from passing through the bridge. The controller can also
+couple / enable the bridges which allows traffic to pass through the
+bridge normally.
+
+The Driver supports only MMIO handling. A PR region can have multiple
+PR Decouplers which can be handled independently or chained via decouple/
+decouple_status signals.
+
+Required properties:
+- compatible : Should contain "xlnx,pr-decoupler-1.00" followed by
+ "xlnx,pr-decoupler"
+- regs : base address and size for decoupler module
+- clocks : input clock to IP
+- clock-names : should contain "aclk"
+
+Optional properties:
+- bridge-enable : 0 if driver should disable bridge at startup
+ 1 if driver should enable bridge at startup
+ Default is to leave bridge in current state.
+
+See Documentation/devicetree/bindings/fpga/fpga-region.txt for generic bindings.
+
+Example:
+ fpga-bridge@100000450 {
+ compatible = "xlnx,pr-decoupler-1.00",
+ "xlnx-pr-decoupler";
+ regs = <0x10000045 0x10>;
+ clocks = <&clkc 15>;
+ clock-names = "aclk";
+ bridge-enable = <0>;
+ };
diff --git a/Bindings/fpga/xilinx-slave-serial.txt b/Bindings/fpga/xilinx-slave-serial.txt
index 9766f7472f51..cfa4ed42b62f 100644
--- a/Bindings/fpga/xilinx-slave-serial.txt
+++ b/Bindings/fpga/xilinx-slave-serial.txt
@@ -31,7 +31,6 @@ Example for full FPGA configuration:
cell-index = <1>;
interrupts = <92>;
clocks = <&coreclk 0>;
- status = "okay";
fpga_mgr_spi: fpga-mgr@0 {
compatible = "xlnx,fpga-slave-serial";
diff --git a/Bindings/gpio/gpio-74x164.txt b/Bindings/gpio/gpio-74x164.txt
index ce1b2231bf5d..2a97553d8d76 100644
--- a/Bindings/gpio/gpio-74x164.txt
+++ b/Bindings/gpio/gpio-74x164.txt
@@ -12,6 +12,9 @@ Required properties:
1 = active low
- registers-number: Number of daisy-chained shift registers
+Optional properties:
+- enable-gpios: GPIO connected to the OE (Output Enable) pin.
+
Example:
gpio5: gpio5@0 {
diff --git a/Bindings/gpio/gpio-aspeed.txt b/Bindings/gpio/gpio-aspeed.txt
index c756afa88cc6..fc6378c778c5 100644
--- a/Bindings/gpio/gpio-aspeed.txt
+++ b/Bindings/gpio/gpio-aspeed.txt
@@ -18,7 +18,7 @@ Required properties:
Optional properties:
- interrupt-parent : The parent interrupt controller, optional if inherited
-- clocks : A phandle to the HPLL clock node for debounce timings
+- clocks : A phandle to the clock to use for debounce timings
The gpio and interrupt properties are further described in their respective
bindings documentation:
diff --git a/Bindings/gpio/gpio-davinci.txt b/Bindings/gpio/gpio-davinci.txt
index 5079ba7d6568..8beb0539b6d8 100644
--- a/Bindings/gpio/gpio-davinci.txt
+++ b/Bindings/gpio/gpio-davinci.txt
@@ -1,7 +1,10 @@
Davinci/Keystone GPIO controller bindings
Required Properties:
-- compatible: should be "ti,dm6441-gpio", "ti,keystone-gpio"
+- compatible: should be "ti,dm6441-gpio": for Davinci da850 SoCs
+ "ti,keystone-gpio": for Keystone 2 66AK2H/K, 66AK2L,
+ 66AK2E SoCs
+ "ti,k2g-gpio", "ti,keystone-gpio": for 66AK2G
- reg: Physical base address of the controller and the size of memory mapped
registers.
@@ -20,7 +23,21 @@ Required Properties:
- ti,ngpio: The number of GPIO pins supported.
- ti,davinci-gpio-unbanked: The number of GPIOs that have an individual interrupt
- line to processor.
+ line to processor.
+
+- clocks: Should contain the device's input clock, and should be defined as per
+ the appropriate clock bindings consumer usage in,
+
+ Documentation/devicetree/bindings/clock/keystone-gate.txt
+ for 66AK2HK/66AK2L/66AK2E SoCs or,
+
+ Documentation/devicetree/bindings/clock/ti,sci-clk.txt
+ for 66AK2G SoCs
+
+- clock-names: Name should be "gpio";
+
+Currently clock-names and clocks are needed for all keystone 2 platforms
+Davinci platforms do not have DT clocks as of now.
The GPIO controller also acts as an interrupt controller. It uses the default
two cells specifier as described in Documentation/devicetree/bindings/
@@ -60,3 +77,73 @@ leds {
...
};
};
+
+Example for 66AK2G:
+
+gpio0: gpio@2603000 {
+ compatible = "ti,k2g-gpio", "ti,keystone-gpio";
+ reg = <0x02603000 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <GIC_SPI 432 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 433 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 434 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 435 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 436 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 437 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 438 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 439 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 440 IRQ_TYPE_EDGE_RISING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <144>;
+ ti,davinci-gpio-unbanked = <0>;
+ clocks = <&k2g_clks 0x001b 0x0>;
+ clock-names = "gpio";
+};
+
+Example for 66AK2HK/66AK2L/66AK2E:
+
+gpio0: gpio@260bf00 {
+ compatible = "ti,keystone-gpio";
+ reg = <0x0260bf00 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /* HW Interrupts mapped to GPIO pins */
+ interrupts = <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 123 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 124 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 147 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&clkgpio>;
+ clock-names = "gpio";
+ ti,ngpio = <32>;
+ ti,davinci-gpio-unbanked = <32>;
+};
diff --git a/Bindings/gpio/gpio-mpc8xxx.txt b/Bindings/gpio/gpio-mpc8xxx.txt
index 4b6cc632ca5c..69d46162d0f5 100644
--- a/Bindings/gpio/gpio-mpc8xxx.txt
+++ b/Bindings/gpio/gpio-mpc8xxx.txt
@@ -23,7 +23,6 @@ gpio0: gpio@1100 {
#gpio-cells = <2>;
reg = <0x1100 0x080>;
interrupts = <78 0x8>;
- status = "okay";
};
Example of gpio-controller node for a ls2080a SoC:
diff --git a/Bindings/gpio/gpio-vf610.txt b/Bindings/gpio/gpio-vf610.txt
index 436cc99c6598..0ccbae44019c 100644
--- a/Bindings/gpio/gpio-vf610.txt
+++ b/Bindings/gpio/gpio-vf610.txt
@@ -5,7 +5,9 @@ functionality. Each pair serves 32 GPIOs. The VF610 has 5 instances of
each, and each PORT module has its own interrupt.
Required properties for GPIO node:
-- compatible : Should be "fsl,<soc>-gpio", currently "fsl,vf610-gpio"
+- compatible : Should be "fsl,<soc>-gpio", below is supported list:
+ "fsl,vf610-gpio"
+ "fsl,imx7ulp-gpio"
- reg : The first reg tuple represents the PORT module, the second tuple
the GPIO module.
- interrupts : Should be the port interrupt shared by all 32 pins.
diff --git a/Bindings/gpio/renesas,gpio-rcar.txt b/Bindings/gpio/renesas,gpio-rcar.txt
index 6826a371fb69..51c86f69995e 100644
--- a/Bindings/gpio/renesas,gpio-rcar.txt
+++ b/Bindings/gpio/renesas,gpio-rcar.txt
@@ -2,8 +2,9 @@
Required Properties:
- - compatible: should contain one of the following.
+ - compatible: should contain one or more of the following:
- "renesas,gpio-r8a7743": for R8A7743 (RZ/G1M) compatible GPIO controller.
+ - "renesas,gpio-r8a7745": for R8A7745 (RZ/G1E) compatible GPIO controller.
- "renesas,gpio-r8a7778": for R8A7778 (R-Mobile M1) compatible GPIO controller.
- "renesas,gpio-r8a7779": for R8A7779 (R-Car H1) compatible GPIO controller.
- "renesas,gpio-r8a7790": for R8A7790 (R-Car H2) compatible GPIO controller.
@@ -13,7 +14,14 @@ Required Properties:
- "renesas,gpio-r8a7794": for R8A7794 (R-Car E2) compatible GPIO controller.
- "renesas,gpio-r8a7795": for R8A7795 (R-Car H3) compatible GPIO controller.
- "renesas,gpio-r8a7796": for R8A7796 (R-Car M3-W) compatible GPIO controller.
- - "renesas,gpio-rcar": for generic R-Car GPIO controller.
+ - "renesas,rcar-gen1-gpio": for a generic R-Car Gen1 GPIO controller.
+ - "renesas,rcar-gen2-gpio": for a generic R-Car Gen2 or RZ/G1 GPIO controller.
+ - "renesas,rcar-gen3-gpio": for a generic R-Car Gen3 GPIO controller.
+ - "renesas,gpio-rcar": deprecated.
+
+ When compatible with the generic version nodes must list the
+ SoC-specific version corresponding to the platform first followed by
+ the generic version.
- reg: Base address and length of each memory resource used by the GPIO
controller hardware module.
@@ -43,7 +51,7 @@ interrupt-controller/interrupts.txt.
Example: R8A7779 (R-Car H1) GPIO controller nodes
gpio0: gpio@ffc40000 {
- compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
+ compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
reg = <0xffc40000 0x2c>;
interrupt-parent = <&gic>;
interrupts = <0 141 0x4>;
@@ -55,7 +63,7 @@ Example: R8A7779 (R-Car H1) GPIO controller nodes
};
...
gpio6: gpio@ffc46000 {
- compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
+ compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
reg = <0xffc46000 0x2c>;
interrupt-parent = <&gic>;
interrupts = <0 147 0x4>;
diff --git a/Bindings/gpio/spear_spics.txt b/Bindings/gpio/spear_spics.txt
index 96c37eb15075..dd04d96e6ff1 100644
--- a/Bindings/gpio/spear_spics.txt
+++ b/Bindings/gpio/spear_spics.txt
@@ -42,7 +42,6 @@ spics: spics@e0700000{
spi0: spi@e0100000 {
- status = "okay";
num-cs = <3>;
cs-gpios = <&gpio1 7 0>, <&spics 0>,
<&spics 1>;
diff --git a/Bindings/gpu/arm,mali-midgard.txt b/Bindings/gpu/arm,mali-midgard.txt
index 5aa5926029ee..039219df05c5 100644
--- a/Bindings/gpu/arm,mali-midgard.txt
+++ b/Bindings/gpu/arm,mali-midgard.txt
@@ -17,6 +17,7 @@ Required properties:
* which must be preceded by one of the following vendor specifics:
+ "amlogic,meson-gxm-mali"
+ "rockchip,rk3288-mali"
+ + "rockchip,rk3399-mali"
- reg : Physical base address of the device and length of the register area.
diff --git a/Bindings/gpu/arm,mali-utgard.txt b/Bindings/gpu/arm,mali-utgard.txt
index 2b6243e730f6..b4ebd56d03f3 100644
--- a/Bindings/gpu/arm,mali-utgard.txt
+++ b/Bindings/gpu/arm,mali-utgard.txt
@@ -10,6 +10,7 @@ Required properties:
* And, optionally, one of the vendor specific compatible:
+ allwinner,sun4i-a10-mali
+ allwinner,sun7i-a20-mali
+ + allwinner,sun50i-h5-mali
+ amlogic,meson-gxbb-mali
+ amlogic,meson-gxl-mali
+ stericsson,db8500-mali
@@ -58,6 +59,10 @@ to specify one more vendor-specific compatible, among:
Required properties:
* resets: phandle to the reset line for the GPU
+ - allwinner,sun50i-h5-mali
+ Required properties:
+ * resets: phandle to the reset line for the GPU
+
- stericsson,db8500-mali
Required properties:
* interrupt-names and interrupts:
diff --git a/Bindings/gpu/nvidia,gk20a.txt b/Bindings/gpu/nvidia,gk20a.txt
index b7e4c7444510..f32bbba4d3bc 100644
--- a/Bindings/gpu/nvidia,gk20a.txt
+++ b/Bindings/gpu/nvidia,gk20a.txt
@@ -51,7 +51,6 @@ Example for GK20A:
resets = <&tegra_car 184>;
reset-names = "gpu";
iommus = <&mc TEGRA_SWGROUP_GPU>;
- status = "disabled";
};
Example for GM20B:
@@ -70,7 +69,6 @@ Example for GM20B:
resets = <&tegra_car 184>;
reset-names = "gpu";
iommus = <&mc TEGRA_SWGROUP_GPU>;
- status = "disabled";
};
Example for GP10B:
@@ -89,5 +87,4 @@ Example for GP10B:
reset-names = "gpu";
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
iommus = <&smmu TEGRA186_SID_GPU>;
- status = "disabled";
};
diff --git a/Bindings/gpu/samsung-g2d.txt b/Bindings/gpu/samsung-g2d.txt
index c4f358dafdaa..1e7959332dbc 100644
--- a/Bindings/gpu/samsung-g2d.txt
+++ b/Bindings/gpu/samsung-g2d.txt
@@ -24,5 +24,4 @@ Example:
interrupts = <0 89 0>;
clocks = <&clock 177>, <&clock 277>;
clock-names = "sclk_fimg2d", "fimg2d";
- status = "disabled";
};
diff --git a/Bindings/hsi/omap-ssi.txt b/Bindings/hsi/omap-ssi.txt
index f26625e42693..b8eca3c7810d 100644
--- a/Bindings/hsi/omap-ssi.txt
+++ b/Bindings/hsi/omap-ssi.txt
@@ -92,6 +92,5 @@ ssi-controller@48058000 {
interrupts = <69>,
<70>;
- status = "disabled"; /* second port is not used on N900 */
}
}
diff --git a/Bindings/hwmon/aspeed-pwm-tacho.txt b/Bindings/hwmon/aspeed-pwm-tacho.txt
index cf4460564adb..367c8203213b 100644
--- a/Bindings/hwmon/aspeed-pwm-tacho.txt
+++ b/Bindings/hwmon/aspeed-pwm-tacho.txt
@@ -11,6 +11,8 @@ Required properties for pwm-tacho node:
- #size-cells : should be 1.
+- #cooling-cells: should be 2.
+
- reg : address and length of the register set for the device.
- pinctrl-names : a pinctrl state named "default" must be defined.
@@ -28,12 +30,17 @@ fan subnode format:
Under fan subnode there can upto 8 child nodes, with each child node
representing a fan. If there are 8 fans each fan can have one PWM port and
one/two Fan tach inputs.
+For PWM port can be configured cooling-levels to create cooling device.
+Cooling device could be bound to a thermal zone for the thermal control.
Required properties for each child node:
- reg : should specify PWM source port.
integer value in the range 0 to 7 with 0 indicating PWM port A and
7 indicating PWM port H.
+- cooling-levels: PWM duty cycle values in a range from 0 to 255
+ which correspond to thermal cooling states.
+
- aspeed,fan-tach-ch : should specify the Fan tach input channel.
integer value in the range 0 through 15, with 0 indicating
Fan tach channel 0 and 15 indicating Fan tach channel 15.
@@ -50,6 +57,7 @@ pwm_tacho_fixed_clk: fixedclk {
pwm_tacho: pwmtachocontroller@1e786000 {
#address-cells = <1>;
#size-cells = <1>;
+ #cooling-cells = <2>;
reg = <0x1E786000 0x1000>;
compatible = "aspeed,ast2500-pwm-tacho";
clocks = <&pwm_tacho_fixed_clk>;
@@ -58,6 +66,7 @@ pwm_tacho: pwmtachocontroller@1e786000 {
fan@0 {
reg = <0x00>;
+ cooling-levels = /bits/ 8 <125 151 177 203 229 255>;
aspeed,fan-tach-ch = /bits/ 8 <0x00>;
};
diff --git a/Bindings/hwmon/ibm,cffps1.txt b/Bindings/hwmon/ibm,cffps1.txt
new file mode 100644
index 000000000000..f68a0a68fc52
--- /dev/null
+++ b/Bindings/hwmon/ibm,cffps1.txt
@@ -0,0 +1,21 @@
+Device-tree bindings for IBM Common Form Factor Power Supply Version 1
+----------------------------------------------------------------------
+
+Required properties:
+ - compatible = "ibm,cffps1";
+ - reg = < I2C bus address >; : Address of the power supply on the
+ I2C bus.
+
+Example:
+
+ i2c-bus@100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+ < more properties >
+
+ power-supply@68 {
+ compatible = "ibm,cffps1";
+ reg = <0x68>;
+ };
+ };
diff --git a/Bindings/hwmon/ltq-cputemp.txt b/Bindings/hwmon/ltq-cputemp.txt
new file mode 100644
index 000000000000..33fd00a987c7
--- /dev/null
+++ b/Bindings/hwmon/ltq-cputemp.txt
@@ -0,0 +1,10 @@
+Lantiq cpu temperatur sensor
+
+Requires node properties:
+- compatible value :
+ "lantiq,cputemp"
+
+Example:
+ cputemp@0 {
+ compatible = "lantiq,cputemp";
+ };
diff --git a/Bindings/i2c/i2c-altera.txt b/Bindings/i2c/i2c-altera.txt
new file mode 100644
index 000000000000..767664f448ec
--- /dev/null
+++ b/Bindings/i2c/i2c-altera.txt
@@ -0,0 +1,39 @@
+* Altera I2C Controller
+* This is Altera's synthesizable logic block I2C Controller for use
+* in Altera's FPGAs.
+
+Required properties :
+ - compatible : should be "altr,softip-i2c-v1.0"
+ - reg : Offset and length of the register set for the device
+ - interrupts : <IRQ> where IRQ is the interrupt number.
+ - clocks : phandle to input clock.
+ - #address-cells = <1>;
+ - #size-cells = <0>;
+
+Recommended properties :
+ - clock-frequency : desired I2C bus clock frequency in Hz.
+
+Optional properties :
+ - fifo-size : Size of the RX and TX FIFOs in bytes.
+ - Child nodes conforming to i2c bus binding
+
+Example :
+
+ i2c@100080000 {
+ compatible = "altr,softip-i2c-v1.0";
+ reg = <0x00000001 0x00080000 0x00000040>;
+ interrupt-parent = <&intc>;
+ interrupts = <0 43 4>;
+ clocks = <&clk_0>;
+ clock-frequency = <100000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ fifo-size = <4>;
+
+ eeprom@51 {
+ compatible = "atmel,24c32";
+ reg = <0x51>;
+ pagesize = <32>;
+ };
+ };
+
diff --git a/Bindings/i2c/i2c-cbus-gpio.txt b/Bindings/i2c/i2c-cbus-gpio.txt
index 8ce9cd2855b5..c143948b2a37 100644
--- a/Bindings/i2c/i2c-cbus-gpio.txt
+++ b/Bindings/i2c/i2c-cbus-gpio.txt
@@ -20,8 +20,8 @@ i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
- retu-mfd: retu@1 {
- compatible = "retu-mfd";
+ retu: retu@1 {
+ compatible = "nokia,retu";
reg = <0x1>;
};
};
diff --git a/Bindings/i2c/i2c-demux-pinctrl.txt b/Bindings/i2c/i2c-demux-pinctrl.txt
index 7ce23ac61308..81b5d55086fa 100644
--- a/Bindings/i2c/i2c-demux-pinctrl.txt
+++ b/Bindings/i2c/i2c-demux-pinctrl.txt
@@ -102,7 +102,6 @@ And for clarification, here are the snipplets for the i2c-parents:
#address-cells = <1>;
#size-cells = <0>;
compatible = "i2c-gpio";
- status = "disabled";
gpios = <&gpio5 6 GPIO_ACTIVE_HIGH /* sda */
&gpio5 5 GPIO_ACTIVE_HIGH /* scl */
>;
diff --git a/Bindings/i2c/i2c-efm32.txt b/Bindings/i2c/i2c-efm32.txt
index 50b25c3da186..3b30e54ae3c7 100644
--- a/Bindings/i2c/i2c-efm32.txt
+++ b/Bindings/i2c/i2c-efm32.txt
@@ -22,7 +22,6 @@ Example:
interrupts = <9>;
clocks = <&cmu clk_HFPERCLKI2C0>;
clock-frequency = <100000>;
- status = "ok";
energymicro,location = <3>;
eeprom@50 {
diff --git a/Bindings/i2c/i2c-mtk.txt b/Bindings/i2c/i2c-mtk.txt
index bd5a7befd951..ff7bf37deb43 100644
--- a/Bindings/i2c/i2c-mtk.txt
+++ b/Bindings/i2c/i2c-mtk.txt
@@ -1,14 +1,15 @@
-* Mediatek's I2C controller
+* MediaTek's I2C controller
-The Mediatek's I2C controller is used to interface with I2C devices.
+The MediaTek's I2C controller is used to interface with I2C devices.
Required properties:
- compatible: value should be either of the following.
- "mediatek,mt2701-i2c", "mediatek,mt6577-i2c": for Mediatek mt2701
- "mediatek,mt6577-i2c": for i2c compatible with mt6577.
- "mediatek,mt6589-i2c": for i2c compatible with mt6589.
- "mediatek,mt7623-i2c", "mediatek,mt6577-i2c": for i2c compatible with mt7623.
- "mediatek,mt8173-i2c": for i2c compatible with mt8173.
+ "mediatek,mt2701-i2c", "mediatek,mt6577-i2c": for MediaTek MT2701
+ "mediatek,mt6577-i2c": for MediaTek MT6577
+ "mediatek,mt6589-i2c": for MediaTek MT6589
+ "mediatek,mt7622-i2c": for MediaTek MT7622
+ "mediatek,mt7623-i2c", "mediatek,mt6577-i2c": for MediaTek MT7623
+ "mediatek,mt8173-i2c": for MediaTek MT8173
- reg: physical base address of the controller and dma base, length of memory
mapped region.
- interrupts: interrupt number to the cpu.
diff --git a/Bindings/i2c/i2c-rcar.txt b/Bindings/i2c/i2c-rcar.txt
index 2b8bd33dbf8d..cad39aee9f73 100644
--- a/Bindings/i2c/i2c-rcar.txt
+++ b/Bindings/i2c/i2c-rcar.txt
@@ -2,6 +2,8 @@ I2C for R-Car platforms
Required properties:
- compatible:
+ "renesas,i2c-r8a7743" if the device is a part of a R8A7743 SoC.
+ "renesas,i2c-r8a7745" if the device is a part of a R8A7745 SoC.
"renesas,i2c-r8a7778" if the device is a part of a R8A7778 SoC.
"renesas,i2c-r8a7779" if the device is a part of a R8A7779 SoC.
"renesas,i2c-r8a7790" if the device is a part of a R8A7790 SoC.
@@ -12,7 +14,8 @@ Required properties:
"renesas,i2c-r8a7795" if the device is a part of a R8A7795 SoC.
"renesas,i2c-r8a7796" if the device is a part of a R8A7796 SoC.
"renesas,rcar-gen1-i2c" for a generic R-Car Gen1 compatible device.
- "renesas,rcar-gen2-i2c" for a generic R-Car Gen2 compatible device.
+ "renesas,rcar-gen2-i2c" for a generic R-Car Gen2 or RZ/G1 compatible
+ device.
"renesas,rcar-gen3-i2c" for a generic R-Car Gen3 compatible device.
"renesas,i2c-rcar" (deprecated)
diff --git a/Bindings/i2c/i2c-rk3x.txt b/Bindings/i2c/i2c-rk3x.txt
index e18445d0980c..22f2eeb2c4c9 100644
--- a/Bindings/i2c/i2c-rk3x.txt
+++ b/Bindings/i2c/i2c-rk3x.txt
@@ -7,6 +7,7 @@ Required properties :
- reg : Offset and length of the register set for the device
- compatible: should be one of the following:
+ - "rockchip,rv1108-i2c": for rv1108
- "rockchip,rk3066-i2c": for rk3066
- "rockchip,rk3188-i2c": for rk3188
- "rockchip,rk3228-i2c": for rk3228
diff --git a/Bindings/i2c/i2c-sh_mobile.txt b/Bindings/i2c/i2c-sh_mobile.txt
index ae9c2a735f39..224390999e81 100644
--- a/Bindings/i2c/i2c-sh_mobile.txt
+++ b/Bindings/i2c/i2c-sh_mobile.txt
@@ -4,6 +4,8 @@ Required properties:
- compatible :
- "renesas,iic-r8a73a4" (R-Mobile APE6)
- "renesas,iic-r8a7740" (R-Mobile A1)
+ - "renesas,iic-r8a7743" (RZ/G1M)
+ - "renesas,iic-r8a7745" (RZ/G1E)
- "renesas,iic-r8a7790" (R-Car H2)
- "renesas,iic-r8a7791" (R-Car M2-W)
- "renesas,iic-r8a7792" (R-Car V2H)
@@ -12,7 +14,8 @@ Required properties:
- "renesas,iic-r8a7795" (R-Car H3)
- "renesas,iic-r8a7796" (R-Car M3-W)
- "renesas,iic-sh73a0" (SH-Mobile AG5)
- - "renesas,rcar-gen2-iic" (generic R-Car Gen2 compatible device)
+ - "renesas,rcar-gen2-iic" (generic R-Car Gen2 or RZ/G1
+ compatible device)
- "renesas,rcar-gen3-iic" (generic R-Car Gen3 compatible device)
- "renesas,rmobile-iic" (generic device)
diff --git a/Bindings/i2c/i2c-sprd.txt b/Bindings/i2c/i2c-sprd.txt
new file mode 100644
index 000000000000..60b7cda15dd2
--- /dev/null
+++ b/Bindings/i2c/i2c-sprd.txt
@@ -0,0 +1,31 @@
+I2C for Spreadtrum platforms
+
+Required properties:
+- compatible: Should be "sprd,sc9860-i2c".
+- reg: Specify the physical base address of the controller and length
+ of memory mapped region.
+- interrupts: Should contain I2C interrupt.
+- clock-names: Should contain following entries:
+ "i2c" for I2C clock,
+ "source" for I2C source (parent) clock,
+ "enable" for I2C module enable clock.
+- clocks: Should contain a clock specifier for each entry in clock-names.
+- clock-frequency: Constains desired I2C bus clock frequency in Hz.
+- #address-cells: Should be 1 to describe address cells for I2C device address.
+- #size-cells: Should be 0 means no size cell for I2C device address.
+
+Optional properties:
+- Child nodes conforming to I2C bus binding
+
+Examples:
+i2c0: i2c@70500000 {
+ compatible = "sprd,sc9860-i2c";
+ reg = <0 0x70500000 0 0x1000>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "i2c", "source", "enable";
+ clocks = <&clk_i2c3>, <&ext_26m>, <&clk_ap_apb_gates 11>;
+ clock-frequency = <400000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+};
+
diff --git a/Bindings/i2c/i2c-stm32.txt b/Bindings/i2c/i2c-stm32.txt
index 78eaf7b718ed..3b5489966634 100644
--- a/Bindings/i2c/i2c-stm32.txt
+++ b/Bindings/i2c/i2c-stm32.txt
@@ -1,7 +1,9 @@
* I2C controller embedded in STMicroelectronics STM32 I2C platform
Required properties :
-- compatible : Must be "st,stm32f4-i2c"
+- compatible : Must be one of the following
+ - "st,stm32f4-i2c"
+ - "st,stm32f7-i2c"
- reg : Offset and length of the register set for the device
- interrupts : Must contain the interrupt id for I2C event and then the
interrupt id for I2C error.
@@ -14,8 +16,16 @@ Required properties :
Optional properties :
- clock-frequency : Desired I2C bus clock frequency in Hz. If not specified,
- the default 100 kHz frequency will be used. As only Normal and Fast modes
- are supported, possible values are 100000 and 400000.
+ the default 100 kHz frequency will be used.
+ For STM32F4 SoC Standard-mode and Fast-mode are supported, possible values are
+ 100000 and 400000.
+ For STM32F7 SoC, Standard-mode, Fast-mode and Fast-mode Plus are supported,
+ possible values are 100000, 400000 and 1000000.
+- i2c-scl-rising-time-ns : Only for STM32F7, I2C SCL Rising time for the board
+ (default: 25)
+- i2c-scl-falling-time-ns : Only for STM32F7, I2C SCL Falling time for the board
+ (default: 10)
+ I2C Timings are derived from these 2 values
Example :
@@ -31,3 +41,16 @@ Example :
pinctrl-0 = <&i2c1_sda_pin>, <&i2c1_scl_pin>;
pinctrl-names = "default";
};
+
+ i2c@40005400 {
+ compatible = "st,stm32f7-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x40005400 0x400>;
+ interrupts = <31>,
+ <32>;
+ resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
+ clocks = <&rcc 1 CLK_I2C1>;
+ pinctrl-0 = <&i2c1_sda_pin>, <&i2c1_scl_pin>;
+ pinctrl-names = "default";
+ };
diff --git a/Bindings/i2c/nvidia,tegra20-i2c.txt b/Bindings/i2c/nvidia,tegra20-i2c.txt
index 656716b72cc4..f64064f8bdc2 100644
--- a/Bindings/i2c/nvidia,tegra20-i2c.txt
+++ b/Bindings/i2c/nvidia,tegra20-i2c.txt
@@ -71,5 +71,4 @@ Example:
reset-names = "i2c";
dmas = <&apbdma 16>, <&apbdma 16>;
dma-names = "rx", "tx";
- status = "disabled";
};
diff --git a/Bindings/iio/adc/at91-sama5d2_adc.txt b/Bindings/iio/adc/at91-sama5d2_adc.txt
index 3223684a643b..552e7a83951d 100644
--- a/Bindings/iio/adc/at91-sama5d2_adc.txt
+++ b/Bindings/iio/adc/at91-sama5d2_adc.txt
@@ -11,6 +11,11 @@ Required properties:
- atmel,min-sample-rate-hz: Minimum sampling rate, it depends on SoC.
- atmel,max-sample-rate-hz: Maximum sampling rate, it depends on SoC.
- atmel,startup-time-ms: Startup time expressed in ms, it depends on SoC.
+ - atmel,trigger-edge-type: One of possible edge types for the ADTRG hardware
+ trigger pin. When the specific edge type is detected, the conversion will
+ start. Possible values are rising, falling, or both.
+ This property uses the IRQ edge types values: IRQ_TYPE_EDGE_RISING ,
+ IRQ_TYPE_EDGE_FALLING or IRQ_TYPE_EDGE_BOTH
Example:
@@ -25,4 +30,5 @@ adc: adc@fc030000 {
atmel,startup-time-ms = <4>;
vddana-supply = <&vdd_3v3_lp_reg>;
vref-supply = <&vdd_3v3_lp_reg>;
+ atmel,trigger-edge-type = <IRQ_TYPE_EDGE_BOTH>;
}
diff --git a/Bindings/iio/adc/brcm,iproc-static-adc.txt b/Bindings/iio/adc/brcm,iproc-static-adc.txt
index caaaed765ce4..7b1b1e4086d4 100644
--- a/Bindings/iio/adc/brcm,iproc-static-adc.txt
+++ b/Bindings/iio/adc/brcm,iproc-static-adc.txt
@@ -37,5 +37,4 @@ For example:
clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>;
clock-names = "tsc_clk";
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
};
diff --git a/Bindings/iio/adc/lpc1850-adc.txt b/Bindings/iio/adc/lpc1850-adc.txt
index 0bcae5140bc5..9ada5abd45fa 100644
--- a/Bindings/iio/adc/lpc1850-adc.txt
+++ b/Bindings/iio/adc/lpc1850-adc.txt
@@ -17,5 +17,4 @@ adc0: adc@400e3000 {
clocks = <&ccu1 CLK_APB3_ADC0>;
vref-supply = <&reg_vdda>;
resets = <&rgu 40>;
- status = "disabled";
};
diff --git a/Bindings/iio/adc/mt6577_auxadc.txt b/Bindings/iio/adc/mt6577_auxadc.txt
index 68c45cbbe3d9..64dc4843c180 100644
--- a/Bindings/iio/adc/mt6577_auxadc.txt
+++ b/Bindings/iio/adc/mt6577_auxadc.txt
@@ -12,6 +12,7 @@ for the Thermal Controller which holds a phandle to the AUXADC.
Required properties:
- compatible: Should be one of:
- "mediatek,mt2701-auxadc": For MT2701 family of SoCs
+ - "mediatek,mt7622-auxadc": For MT7622 family of SoCs
- "mediatek,mt8173-auxadc": For MT8173 family of SoCs
- reg: Address range of the AUXADC unit.
- clocks: Should contain a clock specifier for each entry in clock-names
diff --git a/Bindings/iio/adc/rockchip-saradc.txt b/Bindings/iio/adc/rockchip-saradc.txt
index e0a9b9d6d6fd..c2c50b59873d 100644
--- a/Bindings/iio/adc/rockchip-saradc.txt
+++ b/Bindings/iio/adc/rockchip-saradc.txt
@@ -6,6 +6,7 @@ Required properties:
- "rockchip,rk3066-tsadc": for rk3036
- "rockchip,rk3328-saradc", "rockchip,rk3399-saradc": for rk3328
- "rockchip,rk3399-saradc": for rk3399
+ - "rockchip,rv1108-saradc", "rockchip,rk3399-saradc": for rv1108
- reg: physical base address of the controller and length of memory mapped
region.
diff --git a/Bindings/iio/adc/st,stm32-adc.txt b/Bindings/iio/adc/st,stm32-adc.txt
index 8310073f14e1..48bfcaa3ffcd 100644
--- a/Bindings/iio/adc/st,stm32-adc.txt
+++ b/Bindings/iio/adc/st,stm32-adc.txt
@@ -74,6 +74,11 @@ Optional properties:
* can be 6, 8, 10 or 12 on stm32f4
* can be 8, 10, 12, 14 or 16 on stm32h7
Default is maximum resolution if unset.
+- st,min-sample-time-nsecs: Minimum sampling time in nanoseconds.
+ Depending on hardware (board) e.g. high/low analog input source impedance,
+ fine tune of ADC sampling time may be recommended.
+ This can be either one value or an array that matches 'st,adc-channels' list,
+ to set sample time resp. for all channels, or independently for each channel.
Example:
adc: adc@40012000 {
diff --git a/Bindings/iio/counter/stm32-lptimer-cnt.txt b/Bindings/iio/counter/stm32-lptimer-cnt.txt
new file mode 100644
index 000000000000..a04aa5c04103
--- /dev/null
+++ b/Bindings/iio/counter/stm32-lptimer-cnt.txt
@@ -0,0 +1,27 @@
+STMicroelectronics STM32 Low-Power Timer quadrature encoder and counter
+
+STM32 Low-Power Timer provides several counter modes. It can be used as:
+- quadrature encoder to detect angular position and direction of rotary
+ elements, from IN1 and IN2 input signals.
+- simple counter from IN1 input signal.
+
+Must be a sub-node of an STM32 Low-Power Timer device tree node.
+See ../mfd/stm32-lptimer.txt for details about the parent node.
+
+Required properties:
+- compatible: Must be "st,stm32-lptimer-counter".
+- pinctrl-names: Set to "default".
+- pinctrl-0: List of phandles pointing to pin configuration nodes,
+ to set IN1/IN2 pins in mode of operation for Low-Power
+ Timer input on external pin.
+
+Example:
+ timer@40002400 {
+ compatible = "st,stm32-lptimer";
+ ...
+ counter {
+ compatible = "st,stm32-lptimer-counter";
+ pinctrl-names = "default";
+ pinctrl-0 = <&lptim1_in_pins>;
+ };
+ };
diff --git a/Bindings/iio/dac/lpc1850-dac.txt b/Bindings/iio/dac/lpc1850-dac.txt
index 7d6647d4af5e..42db783c4e75 100644
--- a/Bindings/iio/dac/lpc1850-dac.txt
+++ b/Bindings/iio/dac/lpc1850-dac.txt
@@ -16,5 +16,4 @@ dac: dac@400e1000 {
clocks = <&ccu1 CLK_APB3_DAC>;
vref-supply = <&reg_vdda>;
resets = <&rgu 42>;
- status = "disabled";
};
diff --git a/Bindings/iio/dac/st,stm32-dac.txt b/Bindings/iio/dac/st,stm32-dac.txt
index bcee71f808d0..bf2925c671c6 100644
--- a/Bindings/iio/dac/st,stm32-dac.txt
+++ b/Bindings/iio/dac/st,stm32-dac.txt
@@ -10,7 +10,9 @@ current.
Contents of a stm32 dac root node:
-----------------------------------
Required properties:
-- compatible: Must be "st,stm32h7-dac-core".
+- compatible: Should be one of:
+ "st,stm32f4-dac-core"
+ "st,stm32h7-dac-core"
- reg: Offset and length of the device's register set.
- clocks: Must contain an entry for pclk (which feeds the peripheral bus
interface)
diff --git a/Bindings/iio/humidity/hdc100x.txt b/Bindings/iio/humidity/hdc100x.txt
new file mode 100644
index 000000000000..c52333bdfd19
--- /dev/null
+++ b/Bindings/iio/humidity/hdc100x.txt
@@ -0,0 +1,17 @@
+* HDC100x temperature + humidity sensors
+
+Required properties:
+ - compatible: Should contain one of the following:
+ ti,hdc1000
+ ti,hdc1008
+ ti,hdc1010
+ ti,hdc1050
+ ti,hdc1080
+ - reg: i2c address of the sensor
+
+Example:
+
+hdc100x@40 {
+ compatible = "ti,hdc1000";
+ reg = <0x40>;
+};
diff --git a/Bindings/iio/humidity/hts221.txt b/Bindings/iio/humidity/hts221.txt
index b20ab9c12080..10adeb0d703d 100644
--- a/Bindings/iio/humidity/hts221.txt
+++ b/Bindings/iio/humidity/hts221.txt
@@ -5,9 +5,18 @@ Required properties:
- reg: i2c address of the sensor / spi cs line
Optional properties:
+- drive-open-drain: the interrupt/data ready line will be configured
+ as open drain, which is useful if several sensors share the same
+ interrupt line. This is a boolean property.
+ If the requested interrupt is configured as IRQ_TYPE_LEVEL_HIGH or
+ IRQ_TYPE_EDGE_RISING a pull-down resistor is needed to drive the line
+ when it is not active, whereas a pull-up one is needed when interrupt
+ line is configured as IRQ_TYPE_LEVEL_LOW or IRQ_TYPE_EDGE_FALLING.
+ Refer to pinctrl/pinctrl-bindings.txt for the property description.
- interrupt-parent: should be the phandle for the interrupt controller
- interrupts: interrupt mapping for IRQ. It should be configured with
- flags IRQ_TYPE_LEVEL_HIGH or IRQ_TYPE_EDGE_RISING.
+ flags IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_EDGE_RISING, IRQ_TYPE_LEVEL_LOW or
+ IRQ_TYPE_EDGE_FALLING.
Refer to interrupt-controller/interrupts.txt for generic interrupt
client node bindings.
diff --git a/Bindings/iio/humidity/htu21.txt b/Bindings/iio/humidity/htu21.txt
new file mode 100644
index 000000000000..97d79636f7ae
--- /dev/null
+++ b/Bindings/iio/humidity/htu21.txt
@@ -0,0 +1,13 @@
+*HTU21 - Measurement-Specialties htu21 temperature & humidity sensor and humidity part of MS8607 sensor
+
+Required properties:
+
+ - compatible: should be "meas,htu21" or "meas,ms8607-humidity"
+ - reg: I2C address of the sensor
+
+Example:
+
+htu21@40 {
+ compatible = "meas,htu21";
+ reg = <0x40>;
+};
diff --git a/Bindings/iio/imu/st_lsm6dsx.txt b/Bindings/iio/imu/st_lsm6dsx.txt
index 6f28ff55f3ec..1ff1af799c76 100644
--- a/Bindings/iio/imu/st_lsm6dsx.txt
+++ b/Bindings/iio/imu/st_lsm6dsx.txt
@@ -11,6 +11,14 @@ Required properties:
Optional properties:
- st,drdy-int-pin: the pin on the package that will be used to signal
"data ready" (valid values: 1 or 2).
+- drive-open-drain: the interrupt/data ready line will be configured
+ as open drain, which is useful if several sensors share the same
+ interrupt line. This is a boolean property.
+ (This binding is taken from pinctrl/pinctrl-bindings.txt)
+ If the requested interrupt is configured as IRQ_TYPE_LEVEL_HIGH or
+ IRQ_TYPE_EDGE_RISING a pull-down resistor is needed to drive the line
+ when it is not active, whereas a pull-up one is needed when interrupt
+ line is configured as IRQ_TYPE_LEVEL_LOW or IRQ_TYPE_EDGE_FALLING.
- interrupt-parent: should be the phandle for the interrupt controller
- interrupts: interrupt mapping for IRQ. It should be configured with
flags IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_EDGE_RISING, IRQ_TYPE_LEVEL_LOW or
diff --git a/Bindings/iio/pressure/ms5637.txt b/Bindings/iio/pressure/ms5637.txt
new file mode 100644
index 000000000000..1f43ffa068ac
--- /dev/null
+++ b/Bindings/iio/pressure/ms5637.txt
@@ -0,0 +1,17 @@
+* MS5637 - Measurement-Specialties MS5637, MS5805, MS5837 and MS8607 pressure & temperature sensor
+
+Required properties:
+
+ -compatible: should be one of the following
+ meas,ms5637
+ meas,ms5805
+ meas,ms5837
+ meas,ms8607-temppressure
+ -reg: I2C address of the sensor
+
+Example:
+
+ms5637@76 {
+ compatible = "meas,ms5637";
+ reg = <0x76>;
+};
diff --git a/Bindings/iio/proximity/as3935.txt b/Bindings/iio/proximity/as3935.txt
index 38d74314b7ab..b6c1afa6f02d 100644
--- a/Bindings/iio/proximity/as3935.txt
+++ b/Bindings/iio/proximity/as3935.txt
@@ -16,6 +16,10 @@ Optional properties:
- ams,tuning-capacitor-pf: Calibration tuning capacitor stepping
value 0 - 120pF. This will require using the calibration data from
the manufacturer.
+ - ams,nflwdth: Set the noise and watchdog threshold register on
+ startup. This will need to set according to the noise from the
+ MCU board, and possibly the local environment. Refer to the
+ datasheet for the threshold settings.
Example:
@@ -27,4 +31,5 @@ as3935@0 {
interrupt-parent = <&gpio1>;
interrupts = <16 1>;
ams,tuning-capacitor-pf = <80>;
+ ams,nflwdth = <0x44>;
};
diff --git a/Bindings/iio/st-sensors.txt b/Bindings/iio/st-sensors.txt
index eaa8fbba34e2..9ec6f5ce54fc 100644
--- a/Bindings/iio/st-sensors.txt
+++ b/Bindings/iio/st-sensors.txt
@@ -45,6 +45,7 @@ Accelerometers:
- st,lis2dh12-accel
- st,h3lis331dl-accel
- st,lng2dm-accel
+- st,lis3l02dq
Gyroscopes:
- st,l3g4200d-gyro
@@ -52,6 +53,7 @@ Gyroscopes:
- st,lsm330dl-gyro
- st,lsm330dlc-gyro
- st,l3gd20-gyro
+- st,l3gd20h-gyro
- st,l3g4is-gyro
- st,lsm330-gyro
- st,lsm9ds0-gyro
@@ -62,6 +64,7 @@ Magnetometers:
- st,lsm303dlhc-magn
- st,lsm303dlm-magn
- st,lis3mdl-magn
+- st,lis2mdl
Pressure sensors:
- st,lps001wp-press
diff --git a/Bindings/iio/temperature/tsys01.txt b/Bindings/iio/temperature/tsys01.txt
new file mode 100644
index 000000000000..0d5cc5595d0c
--- /dev/null
+++ b/Bindings/iio/temperature/tsys01.txt
@@ -0,0 +1,19 @@
+* TSYS01 - Measurement Specialties temperature sensor
+
+Required properties:
+
+ - compatible: should be "meas,tsys01"
+ - reg: I2C address of the sensor (changeable via CSB pin)
+
+ ------------------------
+ | CSB | Device Address |
+ ------------------------
+ 1 0x76
+ 0 0x77
+
+Example:
+
+tsys01@76 {
+ compatible = "meas,tsys01";
+ reg = <0x76>;
+};
diff --git a/Bindings/iio/timer/stm32-lptimer-trigger.txt b/Bindings/iio/timer/stm32-lptimer-trigger.txt
new file mode 100644
index 000000000000..85e6806b17d7
--- /dev/null
+++ b/Bindings/iio/timer/stm32-lptimer-trigger.txt
@@ -0,0 +1,23 @@
+STMicroelectronics STM32 Low-Power Timer Trigger
+
+STM32 Low-Power Timer provides trigger source (LPTIM output) that can be used
+by STM32 internal ADC and/or DAC.
+
+Must be a sub-node of an STM32 Low-Power Timer device tree node.
+See ../mfd/stm32-lptimer.txt for details about the parent node.
+
+Required properties:
+- compatible: Must be "st,stm32-lptimer-trigger".
+- reg: Identify trigger hardware block. Must be 0, 1 or 2
+ respectively for lptimer1, lptimer2 or lptimer3
+ trigger output.
+
+Example:
+ timer@40002400 {
+ compatible = "st,stm32-lptimer";
+ ...
+ trigger@0 {
+ compatible = "st,stm32-lptimer-trigger";
+ reg = <0>;
+ };
+ };
diff --git a/Bindings/iio/timer/stm32-timer-trigger.txt b/Bindings/iio/timer/stm32-timer-trigger.txt
index 55a653d15303..b8e8c769d434 100644
--- a/Bindings/iio/timer/stm32-timer-trigger.txt
+++ b/Bindings/iio/timer/stm32-timer-trigger.txt
@@ -4,7 +4,9 @@ Must be a sub-node of an STM32 Timers device tree node.
See ../mfd/stm32-timers.txt for details about the parent node.
Required parameters:
-- compatible: Must be "st,stm32-timer-trigger".
+- compatible: Must be one of:
+ "st,stm32-timer-trigger"
+ "st,stm32h7-timer-trigger"
- reg: Identify trigger hardware block.
Example:
@@ -14,7 +16,7 @@ Example:
compatible = "st,stm32-timers";
reg = <0x40010000 0x400>;
clocks = <&rcc 0 160>;
- clock-names = "clk_int";
+ clock-names = "int";
timer@0 {
compatible = "st,stm32-timer-trigger";
diff --git a/Bindings/input/atmel,maxtouch.txt b/Bindings/input/atmel,maxtouch.txt
index 1852906517ab..23e3abc3fdef 100644
--- a/Bindings/input/atmel,maxtouch.txt
+++ b/Bindings/input/atmel,maxtouch.txt
@@ -22,6 +22,8 @@ Optional properties for main touchpad device:
experiment to determine which bit corresponds to which input. Use
KEY_RESERVED for unused padding values.
+- reset-gpios: GPIO specifier for the touchscreen's reset pin (active low)
+
Example:
touch@4b {
diff --git a/Bindings/input/brcm,bcm-keypad.txt b/Bindings/input/brcm,bcm-keypad.txt
index b77f50bd6403..262deab73588 100644
--- a/Bindings/input/brcm,bcm-keypad.txt
+++ b/Bindings/input/brcm,bcm-keypad.txt
@@ -72,7 +72,6 @@ Example:
/* Required Board specific properties */
keypad,num-rows = <5>;
keypad,num-columns = <5>;
- status = "okay";
linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_F) /* key_forward */
MATRIX_KEY(0x00, 0x03, KEY_HOME) /* key_home */
diff --git a/Bindings/input/pwm-vibrator.txt b/Bindings/input/pwm-vibrator.txt
new file mode 100644
index 000000000000..09145d18491d
--- /dev/null
+++ b/Bindings/input/pwm-vibrator.txt
@@ -0,0 +1,66 @@
+* PWM vibrator device tree bindings
+
+Registers a PWM device as vibrator. It is expected, that the vibrator's
+strength increases based on the duty cycle of the enable PWM channel
+(100% duty cycle meaning strongest vibration, 0% meaning no vibration).
+
+The binding supports an optional direction PWM channel, that can be
+driven at fixed duty cycle. If available this is can be used to increase
+the vibration effect of some devices.
+
+Required properties:
+- compatible: should contain "pwm-vibrator"
+- pwm-names: Should contain "enable" and optionally "direction"
+- pwms: Should contain a PWM handle for each entry in pwm-names
+
+Optional properties:
+- vcc-supply: Phandle for the regulator supplying power
+- direction-duty-cycle-ns: Duty cycle of the direction PWM channel in
+ nanoseconds, defaults to 50% of the channel's
+ period.
+
+Example from Motorola Droid 4:
+
+&omap4_pmx_core {
+ vibrator_direction_pin: pinmux_vibrator_direction_pin {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0x1ce, PIN_OUTPUT | MUX_MODE1) /* dmtimer8_pwm_evt (gpio_27) */
+ >;
+ };
+
+ vibrator_enable_pin: pinmux_vibrator_enable_pin {
+ pinctrl-single,pins = <
+ OMAP4_IOPAD(0X1d0, PIN_OUTPUT | MUX_MODE1) /* dmtimer9_pwm_evt (gpio_28) */
+ >;
+ };
+};
+
+/ {
+ pwm8: dmtimer-pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&vibrator_direction_pin>;
+
+ compatible = "ti,omap-dmtimer-pwm";
+ #pwm-cells = <3>;
+ ti,timers = <&timer8>;
+ ti,clock-source = <0x01>;
+ };
+
+ pwm9: dmtimer-pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&vibrator_enable_pin>;
+
+ compatible = "ti,omap-dmtimer-pwm";
+ #pwm-cells = <3>;
+ ti,timers = <&timer9>;
+ ti,clock-source = <0x01>;
+ };
+
+ vibrator {
+ compatible = "pwm-vibrator";
+ pwms = <&pwm8 0 1000000000 0>,
+ <&pwm9 0 1000000000 0>;
+ pwm-names = "enable", "direction";
+ direction-duty-cycle-ns = <1000000000>;
+ };
+};
diff --git a/Bindings/input/ti,drv260x.txt b/Bindings/input/ti,drv260x.txt
index ee09c8f4474a..4c5312eaaa85 100644
--- a/Bindings/input/ti,drv260x.txt
+++ b/Bindings/input/ti,drv260x.txt
@@ -43,7 +43,7 @@ haptics: haptics@5a {
mode = <DRV260X_LRA_MODE>;
library-sel = <DRV260X_LIB_LRA>;
vib-rated-mv = <3200>;
- vib-overdriver-mv = <3200>;
+ vib-overdrive-mv = <3200>;
}
For more product information please see the link below:
diff --git a/Bindings/input/touchscreen/colibri-vf50-ts.txt b/Bindings/input/touchscreen/colibri-vf50-ts.txt
index 9d9e930f3251..df531b5b6a0d 100644
--- a/Bindings/input/touchscreen/colibri-vf50-ts.txt
+++ b/Bindings/input/touchscreen/colibri-vf50-ts.txt
@@ -32,5 +32,4 @@ Example:
pinctrl-1 = <&pinctrl_touchctrl_default>;
pinctrl-2 = <&pinctrl_touchctrl_gpios>;
vf50-ts-min-pressure = <200>;
- status = "disabled";
};
diff --git a/Bindings/input/touchscreen/imx6ul_tsc.txt b/Bindings/input/touchscreen/imx6ul_tsc.txt
index d4927c202aef..e67e58b61706 100644
--- a/Bindings/input/touchscreen/imx6ul_tsc.txt
+++ b/Bindings/input/touchscreen/imx6ul_tsc.txt
@@ -35,5 +35,4 @@ Example:
measure-delay-time = <0xfff>;
pre-charge-time = <0xffff>;
touchscreen-average-samples = <32>;
- status = "okay";
};
diff --git a/Bindings/interrupt-controller/arm,gic-v3.txt b/Bindings/interrupt-controller/arm,gic-v3.txt
index 4c29cdab0ea5..5eb108e180fa 100644
--- a/Bindings/interrupt-controller/arm,gic-v3.txt
+++ b/Bindings/interrupt-controller/arm,gic-v3.txt
@@ -99,7 +99,7 @@ Examples:
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
- reg = <0x0 0x2c200000 0 0x200000>;
+ reg = <0x0 0x2c200000 0 0x20000>;
};
};
@@ -124,14 +124,14 @@ Examples:
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
- reg = <0x0 0x2c200000 0 0x200000>;
+ reg = <0x0 0x2c200000 0 0x20000>;
};
gic-its@2c400000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
- reg = <0x0 0x2c400000 0 0x200000>;
+ reg = <0x0 0x2c400000 0 0x20000>;
};
ppi-partitions {
diff --git a/Bindings/interrupt-controller/fsl,ls-scfg-msi.txt b/Bindings/interrupt-controller/fsl,ls-scfg-msi.txt
index 9e389493203f..49ccabbfa6f3 100644
--- a/Bindings/interrupt-controller/fsl,ls-scfg-msi.txt
+++ b/Bindings/interrupt-controller/fsl,ls-scfg-msi.txt
@@ -4,8 +4,10 @@ Required properties:
- compatible: should be "fsl,<soc-name>-msi" to identify
Layerscape PCIe MSI controller block such as:
- "fsl,1s1021a-msi"
- "fsl,1s1043a-msi"
+ "fsl,ls1021a-msi"
+ "fsl,ls1043a-msi"
+ "fsl,ls1046a-msi"
+ "fsl,ls1043a-v1.1-msi"
- msi-controller: indicates that this is a PCIe MSI controller node
- reg: physical base address of the controller and length of memory mapped.
- interrupts: an interrupt to the parent interrupt controller.
@@ -23,7 +25,7 @@ MSI controller node
Examples:
msi1: msi-controller@1571000 {
- compatible = "fsl,1s1043a-msi";
+ compatible = "fsl,ls1043a-msi";
reg = <0x0 0x1571000 0x0 0x8>,
msi-controller;
interrupts = <0 116 0x4>;
diff --git a/Bindings/interrupt-controller/mediatek,sysirq.txt b/Bindings/interrupt-controller/mediatek,sysirq.txt
index 11cc87aeb276..07bf0b9a5139 100644
--- a/Bindings/interrupt-controller/mediatek,sysirq.txt
+++ b/Bindings/interrupt-controller/mediatek,sysirq.txt
@@ -17,6 +17,7 @@ Required properties:
"mediatek,mt6582-sysirq", "mediatek,mt6577-sysirq": for MT6582
"mediatek,mt6580-sysirq", "mediatek,mt6577-sysirq": for MT6580
"mediatek,mt6577-sysirq": for MT6577
+ "mediatek,mt2712-sysirq", "mediatek,mt6577-sysirq": for MT2712
"mediatek,mt2701-sysirq", "mediatek,mt6577-sysirq": for MT2701
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
diff --git a/Bindings/interrupt-controller/socionext,uniphier-aidet.txt b/Bindings/interrupt-controller/socionext,uniphier-aidet.txt
new file mode 100644
index 000000000000..48e71d3ac2ad
--- /dev/null
+++ b/Bindings/interrupt-controller/socionext,uniphier-aidet.txt
@@ -0,0 +1,32 @@
+UniPhier AIDET
+
+UniPhier AIDET (ARM Interrupt Detector) is an add-on block for ARM GIC (Generic
+Interrupt Controller). GIC itself can handle only high level and rising edge
+interrupts. The AIDET provides logic inverter to support low level and falling
+edge interrupts.
+
+Required properties:
+- compatible: Should be one of the following:
+ "socionext,uniphier-ld4-aidet" - for LD4 SoC
+ "socionext,uniphier-pro4-aidet" - for Pro4 SoC
+ "socionext,uniphier-sld8-aidet" - for sLD8 SoC
+ "socionext,uniphier-pro5-aidet" - for Pro5 SoC
+ "socionext,uniphier-pxs2-aidet" - for PXs2/LD6b SoC
+ "socionext,uniphier-ld11-aidet" - for LD11 SoC
+ "socionext,uniphier-ld20-aidet" - for LD20 SoC
+ "socionext,uniphier-pxs3-aidet" - for PXs3 SoC
+- reg: Specifies offset and length of the register set for the device.
+- interrupt-controller: Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an interrupt
+ source. The value should be 2. The first cell defines the interrupt number
+ (corresponds to the SPI interrupt number of GIC). The second cell specifies
+ the trigger type as defined in interrupts.txt in this directory.
+
+Example:
+
+ aidet: aidet@5fc20000 {
+ compatible = "socionext,uniphier-pro4-aidet";
+ reg = <0x5fc20000 0x200>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
diff --git a/Bindings/iommu/qcom,iommu.txt b/Bindings/iommu/qcom,iommu.txt
new file mode 100644
index 000000000000..b2641ceb2b40
--- /dev/null
+++ b/Bindings/iommu/qcom,iommu.txt
@@ -0,0 +1,121 @@
+* QCOM IOMMU v1 Implementation
+
+Qualcomm "B" family devices which are not compatible with arm-smmu have
+a similar looking IOMMU but without access to the global register space,
+and optionally requiring additional configuration to route context irqs
+to non-secure vs secure interrupt line.
+
+** Required properties:
+
+- compatible : Should be one of:
+
+ "qcom,msm8916-iommu"
+
+ Followed by "qcom,msm-iommu-v1".
+
+- clock-names : Should be a pair of "iface" (required for IOMMUs
+ register group access) and "bus" (required for
+ the IOMMUs underlying bus access).
+
+- clocks : Phandles for respective clocks described by
+ clock-names.
+
+- #address-cells : must be 1.
+
+- #size-cells : must be 1.
+
+- #iommu-cells : Must be 1. Index identifies the context-bank #.
+
+- ranges : Base address and size of the iommu context banks.
+
+- qcom,iommu-secure-id : secure-id.
+
+- List of sub-nodes, one per translation context bank. Each sub-node
+ has the following required properties:
+
+ - compatible : Should be one of:
+ - "qcom,msm-iommu-v1-ns" : non-secure context bank
+ - "qcom,msm-iommu-v1-sec" : secure context bank
+ - reg : Base address and size of context bank within the iommu
+ - interrupts : The context fault irq.
+
+** Optional properties:
+
+- reg : Base address and size of the SMMU local base, should
+ be only specified if the iommu requires configuration
+ for routing of context bank irq's to secure vs non-
+ secure lines. (Ie. if the iommu contains secure
+ context banks)
+
+
+** Examples:
+
+ apps_iommu: iommu@1e20000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #iommu-cells = <1>;
+ compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
+ ranges = <0 0x1e20000 0x40000>;
+ reg = <0x1ef0000 0x3000>;
+ clocks = <&gcc GCC_SMMU_CFG_CLK>,
+ <&gcc GCC_APSS_TCU_CLK>;
+ clock-names = "iface", "bus";
+ qcom,iommu-secure-id = <17>;
+
+ // mdp_0:
+ iommu-ctx@4000 {
+ compatible = "qcom,msm-iommu-v1-ns";
+ reg = <0x4000 0x1000>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ // venus_ns:
+ iommu-ctx@5000 {
+ compatible = "qcom,msm-iommu-v1-sec";
+ reg = <0x5000 0x1000>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ gpu_iommu: iommu@1f08000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #iommu-cells = <1>;
+ compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
+ ranges = <0 0x1f08000 0x10000>;
+ clocks = <&gcc GCC_SMMU_CFG_CLK>,
+ <&gcc GCC_GFX_TCU_CLK>;
+ clock-names = "iface", "bus";
+ qcom,iommu-secure-id = <18>;
+
+ // gfx3d_user:
+ iommu-ctx@1000 {
+ compatible = "qcom,msm-iommu-v1-ns";
+ reg = <0x1000 0x1000>;
+ interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ // gfx3d_priv:
+ iommu-ctx@2000 {
+ compatible = "qcom,msm-iommu-v1-ns";
+ reg = <0x2000 0x1000>;
+ interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ ...
+
+ venus: video-codec@1d00000 {
+ ...
+ iommus = <&apps_iommu 5>;
+ };
+
+ mdp: mdp@1a01000 {
+ ...
+ iommus = <&apps_iommu 4>;
+ };
+
+ gpu@01c00000 {
+ ...
+ iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
+ };
diff --git a/Bindings/iommu/rockchip,iommu.txt b/Bindings/iommu/rockchip,iommu.txt
index 9a55ac3735e5..2098f7732264 100644
--- a/Bindings/iommu/rockchip,iommu.txt
+++ b/Bindings/iommu/rockchip,iommu.txt
@@ -15,6 +15,11 @@ Required properties:
to associate with its master device. See:
Documentation/devicetree/bindings/iommu/iommu.txt
+Optional properties:
+- rockchip,disable-mmu-reset : Don't use the mmu reset operation.
+ Some mmu instances may produce unexpected results
+ when the reset operation is used.
+
Example:
vopl_mmu: iommu@ff940300 {
diff --git a/Bindings/leds/ams,as3645a.txt b/Bindings/leds/ams,as3645a.txt
new file mode 100644
index 000000000000..fdc40e354a64
--- /dev/null
+++ b/Bindings/leds/ams,as3645a.txt
@@ -0,0 +1,79 @@
+Analog devices AS3645A device tree bindings
+
+The AS3645A flash LED controller can drive two LEDs, one high current
+flash LED and one indicator LED. The high current flash LED can be
+used in torch mode as well.
+
+Ranges below noted as [a, b] are closed ranges between a and b, i.e. a
+and b are included in the range.
+
+Please also see common.txt in the same directory.
+
+
+Required properties
+===================
+
+compatible : Must be "ams,as3645a".
+reg : The I2C address of the device. Typically 0x30.
+#address-cells : 1
+#size-cells : 0
+
+
+Required properties of the flash child node (0)
+===============================================
+
+reg: 0
+flash-timeout-us: Flash timeout in microseconds. The value must be in
+ the range [100000, 850000] and divisible by 50000.
+flash-max-microamp: Maximum flash current in microamperes. Has to be
+ in the range between [200000, 500000] and
+ divisible by 20000.
+led-max-microamp: Maximum torch (assist) current in microamperes. The
+ value must be in the range between [20000, 160000] and
+ divisible by 20000.
+ams,input-max-microamp: Maximum flash controller input current. The
+ value must be in the range [1250000, 2000000]
+ and divisible by 50000.
+
+
+Optional properties of the flash child node
+===========================================
+
+label : The label of the flash LED.
+
+
+Required properties of the indicator child node (1)
+===================================================
+
+reg: 1
+led-max-microamp: Maximum indicator current. The allowed values are
+ 2500, 5000, 7500 and 10000.
+
+Optional properties of the indicator child node
+===============================================
+
+label : The label of the indicator LED.
+
+
+Example
+=======
+
+ as3645a@30 {
+ #address-cells: 1
+ #size-cells: 0
+ reg = <0x30>;
+ compatible = "ams,as3645a";
+ flash@0 {
+ reg = <0x0>;
+ flash-timeout-us = <150000>;
+ flash-max-microamp = <320000>;
+ led-max-microamp = <60000>;
+ ams,input-max-microamp = <1750000>;
+ label = "as3645a:flash";
+ };
+ indicator@1 {
+ reg = <0x1>;
+ led-max-microamp = <10000>;
+ label = "as3645a:indicator";
+ };
+ };
diff --git a/Bindings/leds/irled/gpio-ir-tx.txt b/Bindings/leds/irled/gpio-ir-tx.txt
new file mode 100644
index 000000000000..cbe8dfd29715
--- /dev/null
+++ b/Bindings/leds/irled/gpio-ir-tx.txt
@@ -0,0 +1,14 @@
+Device tree bindings for IR LED connected through gpio pin which is used as
+remote controller transmitter.
+
+Required properties:
+ - compatible: should be "gpio-ir-tx".
+ - gpios : Should specify the IR LED GPIO, see "gpios property" in
+ Documentation/devicetree/bindings/gpio/gpio.txt. Active low LEDs
+ should be indicated using flags in the GPIO specifier.
+
+Example:
+ irled@0 {
+ compatible = "gpio-ir-tx";
+ gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+ };
diff --git a/Bindings/leds/irled/pwm-ir-tx.txt b/Bindings/leds/irled/pwm-ir-tx.txt
new file mode 100644
index 000000000000..66e5672c2e3d
--- /dev/null
+++ b/Bindings/leds/irled/pwm-ir-tx.txt
@@ -0,0 +1,13 @@
+Device tree bindings for IR LED connected through pwm pin which is used as
+remote controller transmitter.
+
+Required properties:
+ - compatible: should be "pwm-ir-tx".
+ - pwms : PWM property to point to the PWM device (phandle)/port (id)
+ and to specify the period time to be used: <&phandle id period_ns>;
+
+Example:
+ irled {
+ compatible = "pwm-ir-tx";
+ pwms = <&pwm0 0 10000000>;
+ };
diff --git a/Bindings/leds/leds-gpio.txt b/Bindings/leds/leds-gpio.txt
index 76535ca37120..a48dda268f81 100644
--- a/Bindings/leds/leds-gpio.txt
+++ b/Bindings/leds/leds-gpio.txt
@@ -18,6 +18,9 @@ LED sub-node properties:
see Documentation/devicetree/bindings/leds/common.txt
- retain-state-suspended: (optional) The suspend state can be retained.Such
as charge-led gpio.
+- retain-state-shutdown: (optional) Retain the state of the LED on shutdown.
+ Useful in BMC systems, for example when the BMC is rebooted while the host
+ remains up.
- panic-indicator : (optional)
see Documentation/devicetree/bindings/leds/common.txt
diff --git a/Bindings/leds/leds-pca955x.txt b/Bindings/leds/leds-pca955x.txt
new file mode 100644
index 000000000000..7984efb767b4
--- /dev/null
+++ b/Bindings/leds/leds-pca955x.txt
@@ -0,0 +1,88 @@
+* NXP - pca955x LED driver
+
+The PCA955x family of chips are I2C LED blinkers whose pins not used
+to control LEDs can be used as general purpose I/Os. The GPIO pins can
+be input or output, and output pins can also be pulse-width controlled.
+
+Required properties:
+- compatible : should be one of :
+ "nxp,pca9550"
+ "nxp,pca9551"
+ "nxp,pca9552"
+ "nxp,pca9553"
+- #address-cells: must be 1
+- #size-cells: must be 0
+- reg: I2C slave address. depends on the model.
+
+Optional properties:
+- gpio-controller: allows pins to be used as GPIOs.
+- #gpio-cells: must be 2.
+- gpio-line-names: define the names of the GPIO lines
+
+LED sub-node properties:
+- reg : number of LED line.
+ from 0 to 1 for the pca9550
+ from 0 to 7 for the pca9551
+ from 0 to 15 for the pca9552
+ from 0 to 3 for the pca9553
+- type: (optional) either
+ PCA9532_TYPE_NONE
+ PCA9532_TYPE_LED
+ PCA9532_TYPE_GPIO
+ see dt-bindings/leds/leds-pca955x.h (default to LED)
+- label : (optional)
+ see Documentation/devicetree/bindings/leds/common.txt
+- linux,default-trigger : (optional)
+ see Documentation/devicetree/bindings/leds/common.txt
+
+Examples:
+
+pca9552: pca9552@60 {
+ compatible = "nxp,pca9552";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x60>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "GPIO12", "GPIO13", "GPIO14", "GPIO15";
+
+ gpio@12 {
+ reg = <12>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ gpio@13 {
+ reg = <13>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ gpio@14 {
+ reg = <14>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ gpio@15 {
+ reg = <15>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ led@0 {
+ label = "red:power";
+ linux,default-trigger = "default-on";
+ reg = <0>;
+ type = <PCA955X_TYPE_LED>;
+ };
+ led@1 {
+ label = "green:power";
+ reg = <1>;
+ type = <PCA955X_TYPE_LED>;
+ };
+ led@2 {
+ label = "pca9552:yellow";
+ reg = <2>;
+ type = <PCA955X_TYPE_LED>;
+ };
+ led@3 {
+ label = "pca9552:white";
+ reg = <3>;
+ type = <PCA955X_TYPE_LED>;
+ };
+};
diff --git a/Bindings/media/i2c/adv748x.txt b/Bindings/media/i2c/adv748x.txt
new file mode 100644
index 000000000000..21ffb5ed8183
--- /dev/null
+++ b/Bindings/media/i2c/adv748x.txt
@@ -0,0 +1,95 @@
+* Analog Devices ADV748X video decoder with HDMI receiver
+
+The ADV7481 and ADV7482 are multi format video decoders with an integrated
+HDMI receiver. They can output CSI-2 on two independent outputs TXA and TXB
+from three input sources HDMI, analog and TTL.
+
+Required Properties:
+
+ - compatible: Must contain one of the following
+ - "adi,adv7481" for the ADV7481
+ - "adi,adv7482" for the ADV7482
+
+ - reg: I2C slave address
+
+Optional Properties:
+
+ - interrupt-names: Should specify the interrupts as "intrq1", "intrq2" and/or
+ "intrq3". All interrupts are optional. The "intrq3" interrupt
+ is only available on the adv7481
+ - interrupts: Specify the interrupt lines for the ADV748x
+
+The device node must contain one 'port' child node per device input and output
+port, in accordance with the video interface bindings defined in
+Documentation/devicetree/bindings/media/video-interfaces.txt. The port nodes
+are numbered as follows.
+
+ Name Type Port
+ ---------------------------------------
+ AIN0 sink 0
+ AIN1 sink 1
+ AIN2 sink 2
+ AIN3 sink 3
+ AIN4 sink 4
+ AIN5 sink 5
+ AIN6 sink 6
+ AIN7 sink 7
+ HDMI sink 8
+ TTL sink 9
+ TXA source 10
+ TXB source 11
+
+The digital output port nodes must contain at least one endpoint.
+
+Ports are optional if they are not connected to anything at the hardware level.
+
+Example:
+
+ video-receiver@70 {
+ compatible = "adi,adv7482";
+ reg = <0x70>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ interrupt-parent = <&gpio6>;
+ interrupt-names = "intrq1", "intrq2";
+ interrupts = <30 IRQ_TYPE_LEVEL_LOW>,
+ <31 IRQ_TYPE_LEVEL_LOW>;
+
+ port@7 {
+ reg = <7>;
+
+ adv7482_ain7: endpoint {
+ remote-endpoint = <&cvbs_in>;
+ };
+ };
+
+ port@8 {
+ reg = <8>;
+
+ adv7482_hdmi: endpoint {
+ remote-endpoint = <&hdmi_in>;
+ };
+ };
+
+ port@10 {
+ reg = <10>;
+
+ adv7482_txa: endpoint {
+ clock-lanes = <0>;
+ data-lanes = <1 2 3 4>;
+ remote-endpoint = <&csi40_in>;
+ };
+ };
+
+ port@11 {
+ reg = <11>;
+
+ adv7482_txb: endpoint {
+ clock-lanes = <0>;
+ data-lanes = <1>;
+ remote-endpoint = <&csi20_in>;
+ };
+ };
+ };
diff --git a/Bindings/media/i2c/dongwoon,dw9714.txt b/Bindings/media/i2c/dongwoon,dw9714.txt
new file mode 100644
index 000000000000..b88dcdd41def
--- /dev/null
+++ b/Bindings/media/i2c/dongwoon,dw9714.txt
@@ -0,0 +1,9 @@
+Dongwoon Anatech DW9714 camera voice coil lens driver
+
+DW9174 is a 10-bit DAC with current sink capability. It is intended
+for driving voice coil lenses in camera modules.
+
+Mandatory properties:
+
+- compatible: "dongwoon,dw9714"
+- reg: I²C slave address
diff --git a/Bindings/media/meson-ao-cec.txt b/Bindings/media/meson-ao-cec.txt
new file mode 100644
index 000000000000..8671bdb08080
--- /dev/null
+++ b/Bindings/media/meson-ao-cec.txt
@@ -0,0 +1,28 @@
+* Amlogic Meson AO-CEC driver
+
+The Amlogic Meson AO-CEC module is present is Amlogic SoCs and its purpose is
+to handle communication between HDMI connected devices over the CEC bus.
+
+Required properties:
+ - compatible : value should be following
+ "amlogic,meson-gx-ao-cec"
+
+ - reg : Physical base address of the IP registers and length of memory
+ mapped region.
+
+ - interrupts : AO-CEC interrupt number to the CPU.
+ - clocks : from common clock binding: handle to AO-CEC clock.
+ - clock-names : from common clock binding: must contain "core",
+ corresponding to entry in the clocks property.
+ - hdmi-phandle: phandle to the HDMI controller
+
+Example:
+
+cec_AO: cec@100 {
+ compatible = "amlogic,meson-gx-ao-cec";
+ reg = <0x0 0x00100 0x0 0x14>;
+ interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&clkc_AO CLKID_AO_CEC_32K>;
+ clock-names = "core";
+ hdmi-phandle = <&hdmi_tx>;
+};
diff --git a/Bindings/media/mtk-cir.txt b/Bindings/media/mtk-cir.txt
index 2be2005577d6..5e18087ce11f 100644
--- a/Bindings/media/mtk-cir.txt
+++ b/Bindings/media/mtk-cir.txt
@@ -2,10 +2,14 @@ Device-Tree bindings for Mediatek consumer IR controller
found in Mediatek SoC family
Required properties:
-- compatible : "mediatek,mt7623-cir"
+- compatible : Should be
+ "mediatek,mt7623-cir": for MT7623 SoC
+ "mediatek,mt7622-cir": for MT7622 SoC
- clocks : list of clock specifiers, corresponding to
entries in clock-names property;
-- clock-names : should contain "clk" entries;
+- clock-names : should contain
+ - "clk" entries: for MT7623 SoC
+ - "clk", "bus" entries: for MT7622 SoC
- interrupts : should contain IR IRQ number;
- reg : should contain IO map address for IR.
diff --git a/Bindings/media/pxa-camera.txt b/Bindings/media/pxa-camera.txt
index 11f5b5d51af8..bc03ec096269 100644
--- a/Bindings/media/pxa-camera.txt
+++ b/Bindings/media/pxa-camera.txt
@@ -24,7 +24,6 @@ Example:
clock-frequency = <50000000>;
clock-output-names = "qci_mclk";
- status = "okay";
port {
#address-cells = <1>;
diff --git a/Bindings/media/qcom,camss.txt b/Bindings/media/qcom,camss.txt
new file mode 100644
index 000000000000..cadecebc73f7
--- /dev/null
+++ b/Bindings/media/qcom,camss.txt
@@ -0,0 +1,197 @@
+Qualcomm Camera Subsystem
+
+* Properties
+
+- compatible:
+ Usage: required
+ Value type: <stringlist>
+ Definition: Should contain:
+ - "qcom,msm8916-camss"
+- reg:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: Register ranges as listed in the reg-names property.
+- reg-names:
+ Usage: required
+ Value type: <stringlist>
+ Definition: Should contain the following entries:
+ - "csiphy0"
+ - "csiphy0_clk_mux"
+ - "csiphy1"
+ - "csiphy1_clk_mux"
+ - "csid0"
+ - "csid1"
+ - "ispif"
+ - "csi_clk_mux"
+ - "vfe0"
+- interrupts:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: Interrupts as listed in the interrupt-names property.
+- interrupt-names:
+ Usage: required
+ Value type: <stringlist>
+ Definition: Should contain the following entries:
+ - "csiphy0"
+ - "csiphy1"
+ - "csid0"
+ - "csid1"
+ - "ispif"
+ - "vfe0"
+- power-domains:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: A phandle and power domain specifier pairs to the
+ power domain which is responsible for collapsing
+ and restoring power to the peripheral.
+- clocks:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: A list of phandle and clock specifier pairs as listed
+ in clock-names property.
+- clock-names:
+ Usage: required
+ Value type: <stringlist>
+ Definition: Should contain the following entries:
+ - "camss_top_ahb"
+ - "ispif_ahb"
+ - "csiphy0_timer"
+ - "csiphy1_timer"
+ - "csi0_ahb"
+ - "csi0"
+ - "csi0_phy"
+ - "csi0_pix"
+ - "csi0_rdi"
+ - "csi1_ahb"
+ - "csi1"
+ - "csi1_phy"
+ - "csi1_pix"
+ - "csi1_rdi"
+ - "camss_ahb"
+ - "camss_vfe_vfe"
+ - "camss_csi_vfe"
+ - "iface"
+ - "bus"
+- vdda-supply:
+ Usage: required
+ Value type: <phandle>
+ Definition: A phandle to voltage supply for CSI2.
+- iommus:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: A list of phandle and IOMMU specifier pairs.
+
+* Nodes
+
+- ports:
+ Usage: required
+ Definition: As described in video-interfaces.txt in same directory.
+ Properties:
+ - reg:
+ Usage: required
+ Value type: <u32>
+ Definition: Selects CSI2 PHY interface - PHY0 or PHY1.
+ Endpoint node properties:
+ - clock-lanes:
+ Usage: required
+ Value type: <u32>
+ Definition: The physical clock lane index. The value
+ must always be <1> as the physical clock
+ lane is lane 1.
+ - data-lanes:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: An array of physical data lanes indexes.
+ Position of an entry determines the logical
+ lane number, while the value of an entry
+ indicates physical lane index. Lane swapping
+ is supported.
+
+* An Example
+
+ camss: camss@1b00000 {
+ compatible = "qcom,msm8916-camss";
+ reg = <0x1b0ac00 0x200>,
+ <0x1b00030 0x4>,
+ <0x1b0b000 0x200>,
+ <0x1b00038 0x4>,
+ <0x1b08000 0x100>,
+ <0x1b08400 0x100>,
+ <0x1b0a000 0x500>,
+ <0x1b00020 0x10>,
+ <0x1b10000 0x1000>;
+ reg-names = "csiphy0",
+ "csiphy0_clk_mux",
+ "csiphy1",
+ "csiphy1_clk_mux",
+ "csid0",
+ "csid1",
+ "ispif",
+ "csi_clk_mux",
+ "vfe0";
+ interrupts = <GIC_SPI 78 0>,
+ <GIC_SPI 79 0>,
+ <GIC_SPI 51 0>,
+ <GIC_SPI 52 0>,
+ <GIC_SPI 55 0>,
+ <GIC_SPI 57 0>;
+ interrupt-names = "csiphy0",
+ "csiphy1",
+ "csid0",
+ "csid1",
+ "ispif",
+ "vfe0";
+ power-domains = <&gcc VFE_GDSC>;
+ clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
+ <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
+ <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
+ <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
+ <&gcc GCC_CAMSS_CSI0_AHB_CLK>,
+ <&gcc GCC_CAMSS_CSI0_CLK>,
+ <&gcc GCC_CAMSS_CSI0PHY_CLK>,
+ <&gcc GCC_CAMSS_CSI0PIX_CLK>,
+ <&gcc GCC_CAMSS_CSI0RDI_CLK>,
+ <&gcc GCC_CAMSS_CSI1_AHB_CLK>,
+ <&gcc GCC_CAMSS_CSI1_CLK>,
+ <&gcc GCC_CAMSS_CSI1PHY_CLK>,
+ <&gcc GCC_CAMSS_CSI1PIX_CLK>,
+ <&gcc GCC_CAMSS_CSI1RDI_CLK>,
+ <&gcc GCC_CAMSS_AHB_CLK>,
+ <&gcc GCC_CAMSS_VFE0_CLK>,
+ <&gcc GCC_CAMSS_CSI_VFE0_CLK>,
+ <&gcc GCC_CAMSS_VFE_AHB_CLK>,
+ <&gcc GCC_CAMSS_VFE_AXI_CLK>;
+ clock-names = "camss_top_ahb",
+ "ispif_ahb",
+ "csiphy0_timer",
+ "csiphy1_timer",
+ "csi0_ahb",
+ "csi0",
+ "csi0_phy",
+ "csi0_pix",
+ "csi0_rdi",
+ "csi1_ahb",
+ "csi1",
+ "csi1_phy",
+ "csi1_pix",
+ "csi1_rdi",
+ "camss_ahb",
+ "camss_vfe_vfe",
+ "camss_csi_vfe",
+ "iface",
+ "bus";
+ vdda-supply = <&pm8916_l2>;
+ iommus = <&apps_iommu 3>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ csiphy0_ep: endpoint {
+ clock-lanes = <1>;
+ data-lanes = <0 2>;
+ remote-endpoint = <&ov5645_ep>;
+ };
+ };
+ };
+ };
diff --git a/Bindings/media/renesas,drif.txt b/Bindings/media/renesas,drif.txt
index 39516b94c28f..0d8974aa8b38 100644
--- a/Bindings/media/renesas,drif.txt
+++ b/Bindings/media/renesas,drif.txt
@@ -40,6 +40,7 @@ To summarize,
Required properties of an internal channel:
-------------------------------------------
- compatible: "renesas,r8a7795-drif" if DRIF controller is a part of R8A7795 SoC.
+ "renesas,r8a7796-drif" if DRIF controller is a part of R8A7796 SoC.
"renesas,rcar-gen3-drif" for a generic R-Car Gen3 compatible device.
When compatible with the generic version, nodes must list the
diff --git a/Bindings/media/s5p-cec.txt b/Bindings/media/s5p-cec.txt
index 1b1a10ba48ce..6f3756da900f 100644
--- a/Bindings/media/s5p-cec.txt
+++ b/Bindings/media/s5p-cec.txt
@@ -33,5 +33,4 @@ hdmicec: cec@100B0000 {
hdmi-phandle = <&hdmi>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_cec>;
- status = "okay";
};
diff --git a/Bindings/media/samsung-fimc.txt b/Bindings/media/samsung-fimc.txt
index 922d6f8e74be..e4e15d8d7521 100644
--- a/Bindings/media/samsung-fimc.txt
+++ b/Bindings/media/samsung-fimc.txt
@@ -166,7 +166,6 @@ Example:
clock-output-names = "cam_a_clkout", "cam_b_clkout";
pinctrl-names = "default";
pinctrl-0 = <&cam_port_a_clk_active>;
- status = "okay";
#address-cells = <1>;
#size-cells = <1>;
@@ -189,7 +188,6 @@ Example:
compatible = "samsung,exynos4210-fimc";
reg = <0x11800000 0x1000>;
interrupts = <0 85 0>;
- status = "okay";
};
csis_0: csis@11880000 {
diff --git a/Bindings/media/stih407-c8sectpfe.txt b/Bindings/media/stih407-c8sectpfe.txt
index cc51b1fd6e0c..6af3fc210ecc 100644
--- a/Bindings/media/stih407-c8sectpfe.txt
+++ b/Bindings/media/stih407-c8sectpfe.txt
@@ -52,7 +52,6 @@ Example:
c8sectpfe@08a20000 {
compatible = "st,stih407-c8sectpfe";
- status = "okay";
reg = <0x08a20000 0x10000>, <0x08a00000 0x4000>;
reg-names = "stfe", "stfe-ram";
interrupts = <GIC_SPI 34 IRQ_TYPE_NONE>, <GIC_SPI 35 IRQ_TYPE_NONE>;
diff --git a/Bindings/media/ti,da850-vpif.txt b/Bindings/media/ti,da850-vpif.txt
index df7182a63e59..e47c7ccc57f1 100644
--- a/Bindings/media/ti,da850-vpif.txt
+++ b/Bindings/media/ti,da850-vpif.txt
@@ -59,7 +59,6 @@ I2C-connected TVP5147 decoder:
tvp5147@5d {
compatible = "ti,tvp5147";
reg = <0x5d>;
- status = "okay";
port {
composite_in: endpoint {
diff --git a/Bindings/media/video-interfaces.txt b/Bindings/media/video-interfaces.txt
index 9cd2a369125d..852041a7480c 100644
--- a/Bindings/media/video-interfaces.txt
+++ b/Bindings/media/video-interfaces.txt
@@ -76,6 +76,11 @@ Optional endpoint properties
mode horizontal and vertical synchronization signals are provided to the
slave device (data source) by the master device (data sink). In the master
mode the data source device is also the source of the synchronization signals.
+- bus-type: data bus type. Possible values are:
+ 0 - autodetect based on other properties (MIPI CSI-2 D-PHY, parallel or Bt656)
+ 1 - MIPI CSI-2 C-PHY
+ 2 - MIPI CSI1
+ 3 - CCP2
- bus-width: number of data lines actively used, valid for the parallel busses.
- data-shift: on the parallel data busses, if bus-width is used to specify the
number of data lines, data-shift can be used to specify which data lines are
@@ -112,7 +117,8 @@ Optional endpoint properties
should be the combined length of data-lanes and clock-lanes properties.
If the lane-polarities property is omitted, the value must be interpreted
as 0 (normal). This property is valid for serial busses only.
-
+- strobe: Whether the clock signal is used as clock (0) or strobe (1). Used
+ with CCP2, for instance.
Example
-------
diff --git a/Bindings/media/zx-irdec.txt b/Bindings/media/zx-irdec.txt
new file mode 100644
index 000000000000..295b9fab593e
--- /dev/null
+++ b/Bindings/media/zx-irdec.txt
@@ -0,0 +1,14 @@
+IR Decoder (IRDEC) on ZTE ZX family SoCs
+
+Required properties:
+ - compatible: Should be "zte,zx296718-irdec".
+ - reg: Physical base address and length of IRDEC registers.
+ - interrupts: Interrupt number of IRDEC.
+
+Exmaples:
+
+ irdec: ir-decoder@111000 {
+ compatible = "zte,zx296718-irdec";
+ reg = <0x111000 0x1000>;
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+ };
diff --git a/Bindings/memory-controllers/mediatek,smi-larb.txt b/Bindings/memory-controllers/mediatek,smi-larb.txt
index 21277a56e94c..ddf46b8856a5 100644
--- a/Bindings/memory-controllers/mediatek,smi-larb.txt
+++ b/Bindings/memory-controllers/mediatek,smi-larb.txt
@@ -15,6 +15,9 @@ Required properties:
the register.
- "smi" : It's the clock for transfer data and command.
+Required property for mt2701:
+- mediatek,larb-id :the hardware id of this larb.
+
Example:
larb1: larb@16010000 {
compatible = "mediatek,mt8173-smi-larb";
@@ -25,3 +28,15 @@ Example:
<&vdecsys CLK_VDEC_LARB_CKEN>;
clock-names = "apb", "smi";
};
+
+Example for mt2701:
+ larb0: larb@14010000 {
+ compatible = "mediatek,mt2701-smi-larb";
+ reg = <0 0x14010000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ mediatek,larb-id = <0>;
+ clocks = <&mmsys CLK_MM_SMI_LARB0>,
+ <&mmsys CLK_MM_SMI_LARB0>;
+ clock-names = "apb", "smi";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
+ };
diff --git a/Bindings/memory-controllers/mvebu-devbus.txt b/Bindings/memory-controllers/mvebu-devbus.txt
index 1ee3bc09f319..8b9388cc1ccc 100644
--- a/Bindings/memory-controllers/mvebu-devbus.txt
+++ b/Bindings/memory-controllers/mvebu-devbus.txt
@@ -130,7 +130,6 @@ The reg property implicitly specifies the chip select as this:
Example:
devbus-bootcs@d0010400 {
- status = "okay";
ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf0000000, size 0x1000000 */
#address-cells = <1>;
#size-cells = <1>;
diff --git a/Bindings/mfd/act8945a.txt b/Bindings/mfd/act8945a.txt
index 462819ac3da8..e6f168db6c72 100644
--- a/Bindings/mfd/act8945a.txt
+++ b/Bindings/mfd/act8945a.txt
@@ -12,7 +12,6 @@ Example:
pmic@5b {
compatible = "active-semi,act8945a";
reg = <0x5b>;
- status = "okay";
active-semi,vsel-high;
@@ -79,6 +78,5 @@ Example:
active-semi,input-voltage-threshold-microvolt = <6600>;
active-semi,precondition-timeout = <40>;
active-semi,total-timeout = <3>;
- status = "okay";
};
};
diff --git a/Bindings/mfd/atmel-hlcdc.txt b/Bindings/mfd/atmel-hlcdc.txt
index eec40be7f79a..3f643ef121ff 100644
--- a/Bindings/mfd/atmel-hlcdc.txt
+++ b/Bindings/mfd/atmel-hlcdc.txt
@@ -25,7 +25,6 @@ Example:
clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
clock-names = "periph_clk","sys_clk", "slow_clk";
interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
- status = "disabled";
hlcdc-display-controller {
compatible = "atmel,hlcdc-display-controller";
diff --git a/Bindings/mfd/atmel-smc.txt b/Bindings/mfd/atmel-smc.txt
index 26eeed373934..1103ce2030fb 100644
--- a/Bindings/mfd/atmel-smc.txt
+++ b/Bindings/mfd/atmel-smc.txt
@@ -8,6 +8,7 @@ Required properties:
- compatible: Should be one of the following
"atmel,at91sam9260-smc", "syscon"
"atmel,sama5d3-smc", "syscon"
+ "atmel,sama5d2-smc", "syscon"
- reg: Contains offset/length value of the SMC memory
region.
diff --git a/Bindings/mfd/axp20x.txt b/Bindings/mfd/axp20x.txt
index aca09af66514..9455503b0299 100644
--- a/Bindings/mfd/axp20x.txt
+++ b/Bindings/mfd/axp20x.txt
@@ -7,7 +7,14 @@ axp209 (X-Powers)
axp221 (X-Powers)
axp223 (X-Powers)
axp803 (X-Powers)
+axp806 (X-Powers)
axp809 (X-Powers)
+axp813 (X-Powers)
+
+The AXP813 is 2 chips packaged into 1. The 2 chips do not share anything
+other than the packaging. Pins are routed separately. As such they should
+be treated as separate entities. The other half is an AC100 RTC/codec
+combo chip. Please see ./ac100.txt for its bindings.
Required properties:
- compatible: should be one of:
@@ -19,6 +26,7 @@ Required properties:
* "x-powers,axp803"
* "x-powers,axp806"
* "x-powers,axp809"
+ * "x-powers,axp813"
- reg: The I2C slave address or RSB hardware address for the AXP chip
- interrupt-parent: The parent interrupt controller
- interrupts: SoC NMI / GPIO interrupt connected to the PMIC's IRQ pin
@@ -28,12 +36,14 @@ Required properties:
Optional properties:
- x-powers,dcdc-freq: defines the work frequency of DC-DC in KHz
AXP152/20X: range: 750-1875, Default: 1.5 MHz
- AXP22X/80X: range: 1800-4050, Default: 3 MHz
+ AXP22X/8XX: range: 1800-4050, Default: 3 MHz
-- x-powers,drive-vbus-en: axp221 / axp223 only boolean, set this when the
- N_VBUSEN pin is used as an output pin to control an external
- regulator to drive the OTG VBus, rather then as an input pin
- which signals whether the board is driving OTG VBus or not.
+- x-powers,drive-vbus-en: boolean, set this when the N_VBUSEN pin is
+ used as an output pin to control an external
+ regulator to drive the OTG VBus, rather then
+ as an input pin which signals whether the
+ board is driving OTG VBus or not.
+ (axp221 / axp223 / axp813 only)
- x-powers,master-mode: Boolean (axp806 only). Set this when the PMIC is
wired for master mode. The default is slave mode.
@@ -171,6 +181,36 @@ LDO_IO1 : LDO : ips-supply : GPIO 1
RTC_LDO : LDO : ips-supply : always on
SW : On/Off Switch : swin-supply
+AXP813 regulators, type, and corresponding input supply names:
+
+Regulator Type Supply Name Notes
+--------- ---- ----------- -----
+DCDC1 : DC-DC buck : vin1-supply
+DCDC2 : DC-DC buck : vin2-supply : poly-phase capable
+DCDC3 : DC-DC buck : vin3-supply : poly-phase capable
+DCDC4 : DC-DC buck : vin4-supply
+DCDC5 : DC-DC buck : vin5-supply : poly-phase capable
+DCDC6 : DC-DC buck : vin6-supply : poly-phase capable
+DCDC7 : DC-DC buck : vin7-supply
+ALDO1 : LDO : aldoin-supply : shared supply
+ALDO2 : LDO : aldoin-supply : shared supply
+ALDO3 : LDO : aldoin-supply : shared supply
+DLDO1 : LDO : dldoin-supply : shared supply
+DLDO2 : LDO : dldoin-supply : shared supply
+DLDO3 : LDO : dldoin-supply : shared supply
+DLDO4 : LDO : dldoin-supply : shared supply
+ELDO1 : LDO : eldoin-supply : shared supply
+ELDO2 : LDO : eldoin-supply : shared supply
+ELDO3 : LDO : eldoin-supply : shared supply
+FLDO1 : LDO : fldoin-supply : shared supply
+FLDO2 : LDO : fldoin-supply : shared supply
+FLDO3 : LDO : fldoin-supply : shared supply
+LDO_IO0 : LDO : ips-supply : GPIO 0
+LDO_IO1 : LDO : ips-supply : GPIO 1
+RTC_LDO : LDO : ips-supply : always on
+SW : On/Off Switch : swin-supply
+DRIVEVBUS : Enable output : drivevbus-supply : external regulator
+
Example:
axp209: pmic@34 {
diff --git a/Bindings/mfd/bd9571mwv.txt b/Bindings/mfd/bd9571mwv.txt
new file mode 100644
index 000000000000..9ab216a851d5
--- /dev/null
+++ b/Bindings/mfd/bd9571mwv.txt
@@ -0,0 +1,49 @@
+* ROHM BD9571MWV Power Management Integrated Circuit (PMIC) bindings
+
+Required properties:
+ - compatible : Should be "rohm,bd9571mwv".
+ - reg : I2C slave address.
+ - interrupt-parent : Phandle to the parent interrupt controller.
+ - interrupts : The interrupt line the device is connected to.
+ - interrupt-controller : Marks the device node as an interrupt controller.
+ - #interrupt-cells : The number of cells to describe an IRQ, should be 2.
+ The first cell is the IRQ number.
+ The second cell is the flags, encoded as trigger
+ masks from ../interrupt-controller/interrupts.txt.
+ - gpio-controller : Marks the device node as a GPIO Controller.
+ - #gpio-cells : Should be two. The first cell is the pin number and
+ the second cell is used to specify flags.
+ See ../gpio/gpio.txt for more information.
+ - regulators: : List of child nodes that specify the regulator
+ initialization data. Child nodes must be named
+ after their hardware counterparts:
+ - vd09
+ - vd18
+ - vd25
+ - vd33
+ - dvfs
+ Each child node is defined using the standard
+ binding for regulators.
+
+Example:
+
+ pmic: pmic@30 {
+ compatible = "rohm,bd9571mwv";
+ reg = <0x30>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ regulators {
+ dvfs: dvfs {
+ regulator-name = "dvfs";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1030000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
diff --git a/Bindings/mfd/da9052-i2c.txt b/Bindings/mfd/da9052-i2c.txt
index 9554292dc6cb..07c69c0c6624 100644
--- a/Bindings/mfd/da9052-i2c.txt
+++ b/Bindings/mfd/da9052-i2c.txt
@@ -4,6 +4,14 @@ Required properties:
- compatible : Should be "dlg,da9052", "dlg,da9053-aa",
"dlg,da9053-ab", or "dlg,da9053-bb"
+Optional properties:
+- dlg,tsi-as-adc : Boolean, if set the X+, X-, Y+, Y- touchscreen
+ input lines are used as general purpose analogue
+ input.
+- tsiref-supply: Phandle to the regulator, which provides the reference
+ voltage for the TSIREF pin. Must be provided when the
+ touchscreen pins are used for ADC purposes.
+
Sub-nodes:
- regulators : Contain the regulator nodes. The DA9052/53 regulators are
bound using their names as listed below:
@@ -29,7 +37,6 @@ Sub-nodes:
Examples:
i2c@63fc8000 { /* I2C1 */
- status = "okay";
pmic: dialog@48 {
compatible = "dlg,da9053-aa";
diff --git a/Bindings/mfd/mc13xxx.txt b/Bindings/mfd/mc13xxx.txt
index 8aba48821a85..39ba4146769d 100644
--- a/Bindings/mfd/mc13xxx.txt
+++ b/Bindings/mfd/mc13xxx.txt
@@ -116,7 +116,6 @@ ecspi@70010000 { /* ECSPI1 */
fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio4 24 0>, /* GPIO4_24 */
<&gpio4 25 0>; /* GPIO4_25 */
- status = "okay";
pmic: mc13892@0 {
#address-cells = <1>;
diff --git a/Bindings/mfd/mxs-lradc.txt b/Bindings/mfd/mxs-lradc.txt
index 555fb117d4fa..755cbef0647d 100644
--- a/Bindings/mfd/mxs-lradc.txt
+++ b/Bindings/mfd/mxs-lradc.txt
@@ -26,7 +26,6 @@ Example for i.MX23 SoC:
compatible = "fsl,imx23-lradc";
reg = <0x80050000 0x2000>;
interrupts = <36 37 38 39 40 41 42 43 44>;
- status = "okay";
fsl,lradc-touchscreen-wires = <4>;
fsl,ave-ctrl = <4>;
fsl,ave-delay = <2>;
@@ -39,7 +38,6 @@ Example for i.MX28 SoC:
compatible = "fsl,imx28-lradc";
reg = <0x80050000 0x2000>;
interrupts = <10 14 15 16 17 18 19 20 21 22 23 24 25>;
- status = "okay";
fsl,lradc-touchscreen-wires = <5>;
fsl,ave-ctrl = <4>;
fsl,ave-delay = <2>;
diff --git a/Bindings/mfd/retu.txt b/Bindings/mfd/retu.txt
new file mode 100644
index 000000000000..876242394a16
--- /dev/null
+++ b/Bindings/mfd/retu.txt
@@ -0,0 +1,25 @@
+* Device tree bindings for Nokia Retu and Tahvo multi-function device
+
+Retu and Tahvo are a multi-function devices found on Nokia Internet
+Tablets (770, N800 and N810). The Retu chip provides watchdog timer
+and power button control functionalities while Tahvo chip provides
+USB transceiver functionality.
+
+Required properties:
+- compatible: "nokia,retu" or "nokia,tahvo"
+- reg: Specifies the CBUS slave address of the ASIC chip
+- interrupts: The interrupt line the device is connected to
+- interrupt-parent: The parent interrupt controller
+
+Example:
+
+cbus0 {
+ compatible = "i2c-cbus-gpio";
+ ...
+ retu: retu@1 {
+ compatible = "nokia,retu";
+ interrupt-parent = <&gpio4>;
+ interrupts = <12 IRQ_TYPE_EDGE_RISING>;
+ reg = <0x1>;
+ };
+};
diff --git a/Bindings/mfd/rk808.txt b/Bindings/mfd/rk808.txt
index 9636ae8d8d41..91b65227afeb 100644
--- a/Bindings/mfd/rk808.txt
+++ b/Bindings/mfd/rk808.txt
@@ -1,11 +1,14 @@
RK8XX Power Management Integrated Circuit
The rk8xx family current members:
+rk805
rk808
rk818
Required properties:
-- compatible: "rockchip,rk808", "rockchip,rk818"
+- compatible: "rockchip,rk805"
+- compatible: "rockchip,rk808"
+- compatible: "rockchip,rk818"
- reg: I2C slave address
- interrupt-parent: The parent interrupt controller.
- interrupts: the interrupt outputs of the controller.
@@ -18,6 +21,14 @@ Optional properties:
- rockchip,system-power-controller: Telling whether or not this pmic is controlling
the system power.
+Optional RK805 properties:
+- vcc1-supply: The input supply for DCDC_REG1
+- vcc2-supply: The input supply for DCDC_REG2
+- vcc3-supply: The input supply for DCDC_REG3
+- vcc4-supply: The input supply for DCDC_REG4
+- vcc5-supply: The input supply for LDO_REG1 and LDO_REG2
+- vcc6-supply: The input supply for LDO_REG3
+
Optional RK808 properties:
- vcc1-supply: The input supply for DCDC_REG1
- vcc2-supply: The input supply for DCDC_REG2
@@ -56,6 +67,15 @@ by a child node of the 'regulators' node.
/* standard regulator bindings here */
};
+Following regulators of the RK805 PMIC regulators are supported. Note that
+the 'n' in regulator name, as in DCDC_REGn or LDOn, represents the DCDC or LDO
+number as described in RK805 datasheet.
+
+ - DCDC_REGn
+ - valid values for n are 1 to 4.
+ - LDO_REGn
+ - valid values for n are 1 to 3
+
Following regulators of the RK808 PMIC block are supported. Note that
the 'n' in regulator name, as in DCDC_REGn or LDOn, represents the DCDC or LDO
number as described in RK808 datasheet.
diff --git a/Bindings/mfd/samsung,exynos5433-lpass.txt b/Bindings/mfd/samsung,exynos5433-lpass.txt
index df664018c148..d759da606f75 100644
--- a/Bindings/mfd/samsung,exynos5433-lpass.txt
+++ b/Bindings/mfd/samsung,exynos5433-lpass.txt
@@ -57,7 +57,6 @@ audio-subsystem {
clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
pinctrl-names = "default";
pinctrl-0 = <&i2s0_bus>;
- status = "disabled";
};
serial_3: serial@11460000 {
@@ -69,6 +68,5 @@ audio-subsystem {
clock-names = "uart", "clk_uart_baud0";
pinctrl-names = "default";
pinctrl-0 = <&uart_aud_bus>;
- status = "disabled";
};
};
diff --git a/Bindings/mfd/stm32-lptimer.txt b/Bindings/mfd/stm32-lptimer.txt
new file mode 100644
index 000000000000..2a9ff29db9c9
--- /dev/null
+++ b/Bindings/mfd/stm32-lptimer.txt
@@ -0,0 +1,48 @@
+STMicroelectronics STM32 Low-Power Timer
+
+The STM32 Low-Power Timer (LPTIM) is a 16-bit timer that provides several
+functions:
+- PWM output (with programmable prescaler, configurable polarity)
+- Quadrature encoder, counter
+- Trigger source for STM32 ADC/DAC (LPTIM_OUT)
+
+Required properties:
+- compatible: Must be "st,stm32-lptimer".
+- reg: Offset and length of the device's register set.
+- clocks: Phandle to the clock used by the LP Timer module.
+- clock-names: Must be "mux".
+- #address-cells: Should be '<1>'.
+- #size-cells: Should be '<0>'.
+
+Optional subnodes:
+- pwm: See ../pwm/pwm-stm32-lp.txt
+- counter: See ../iio/timer/stm32-lptimer-cnt.txt
+- trigger: See ../iio/timer/stm32-lptimer-trigger.txt
+
+Example:
+
+ timer@40002400 {
+ compatible = "st,stm32-lptimer";
+ reg = <0x40002400 0x400>;
+ clocks = <&timer_clk>;
+ clock-names = "mux";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pwm {
+ compatible = "st,stm32-pwm-lp";
+ pinctrl-names = "default";
+ pinctrl-0 = <&lppwm1_pins>;
+ };
+
+ trigger@0 {
+ compatible = "st,stm32-lptimer-trigger";
+ reg = <0>;
+ };
+
+ counter {
+ compatible = "st,stm32-lptimer-counter";
+ pinctrl-names = "default";
+ pinctrl-0 = <&lptim1_in_pins>;
+ };
+ };
diff --git a/Bindings/mfd/tps6105x.txt b/Bindings/mfd/tps6105x.txt
new file mode 100644
index 000000000000..93602c7a19c8
--- /dev/null
+++ b/Bindings/mfd/tps6105x.txt
@@ -0,0 +1,17 @@
+* Device tree bindings for TI TPS61050/61052 Boost Converters
+
+The TP61050/TPS61052 is a high-power "white LED driver". The
+device provides LED, GPIO and regulator functionalities.
+
+Required properties:
+- compatible: "ti,tps61050" or "ti,tps61052"
+- reg: Specifies the I2C slave address
+
+Example:
+
+i2c0 {
+ tps61052@33 {
+ compatible = "ti,tps61052";
+ reg = <0x33>;
+ };
+};
diff --git a/Bindings/mfd/wm831x.txt b/Bindings/mfd/wm831x.txt
index 9f8b7430673c..505709403d3f 100644
--- a/Bindings/mfd/wm831x.txt
+++ b/Bindings/mfd/wm831x.txt
@@ -31,6 +31,7 @@ Required properties:
../interrupt-controller/interrupts.txt
Optional sub-nodes:
+ - phys : Contains a phandle to the USB PHY.
- regulators : Contains sub-nodes for each of the regulators supplied by
the device. The regulators are bound using their names listed below:
diff --git a/Bindings/mfd/zii,rave-sp.txt b/Bindings/mfd/zii,rave-sp.txt
new file mode 100644
index 000000000000..088eff9ddb78
--- /dev/null
+++ b/Bindings/mfd/zii,rave-sp.txt
@@ -0,0 +1,39 @@
+Zodiac Inflight Innovations RAVE Supervisory Processor
+
+RAVE Supervisory Processor communicates with SoC over UART. It is
+expected that its Device Tree node is specified as a child of a node
+corresponding to UART controller used for communication.
+
+Required parent device properties:
+
+ - compatible: Should be one of:
+ - "zii,rave-sp-niu"
+ - "zii,rave-sp-mezz"
+ - "zii,rave-sp-esb"
+ - "zii,rave-sp-rdu1"
+ - "zii,rave-sp-rdu2"
+
+ - current-speed: Should be set to baud rate SP device is using
+
+RAVE SP consists of the following sub-devices:
+
+Device Description
+------ -----------
+rave-sp-wdt : Watchdog
+rave-sp-nvmem : Interface to onborad EEPROM
+rave-sp-backlight : Display backlight
+rave-sp-hwmon : Interface to onboard hardware sensors
+rave-sp-leds : Interface to onboard LEDs
+rave-sp-input : Interface to onboard power button
+
+Example of usage:
+
+ rdu {
+ compatible = "zii,rave-sp-rdu2";
+ current-speed = <1000000>;
+
+ watchdog {
+ compatible = "zii,rave-sp-watchdog";
+ };
+ };
+
diff --git a/Bindings/mips/lantiq/fpi-bus.txt b/Bindings/mips/lantiq/fpi-bus.txt
new file mode 100644
index 000000000000..0a2df4338332
--- /dev/null
+++ b/Bindings/mips/lantiq/fpi-bus.txt
@@ -0,0 +1,31 @@
+Lantiq XWAY SoC FPI BUS binding
+============================
+
+
+-------------------------------------------------------------------------------
+Required properties:
+- compatible : Should be one of
+ "lantiq,xrx200-fpi"
+- reg : The address and length of the XBAR
+ configuration register.
+ Address and length of the FPI bus itself.
+- lantiq,rcu : A phandle to the RCU syscon
+- lantiq,offset-endianness : Offset of the endianness configuration
+ register
+
+-------------------------------------------------------------------------------
+Example for the FPI on the xrx200 SoCs:
+ fpi@10000000 {
+ compatible = "lantiq,xrx200-fpi";
+ ranges = <0x0 0x10000000 0xf000000>;
+ reg = <0x1f400000 0x1000>,
+ <0x10000000 0xf000000>;
+ lantiq,rcu = <&rcu0>;
+ lantiq,offset-endianness = <0x4c>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ gptu@e100a00 {
+ ......
+ };
+ };
diff --git a/Bindings/mips/lantiq/rcu-gphy.txt b/Bindings/mips/lantiq/rcu-gphy.txt
new file mode 100644
index 000000000000..a0c19bd1ce66
--- /dev/null
+++ b/Bindings/mips/lantiq/rcu-gphy.txt
@@ -0,0 +1,36 @@
+Lantiq XWAY SoC GPHY binding
+============================
+
+This binding describes a software-defined ethernet PHY, provided by the RCU
+module on newer Lantiq XWAY SoCs (xRX200 and newer).
+
+-------------------------------------------------------------------------------
+Required properties:
+- compatible : Should be one of
+ "lantiq,xrx200a1x-gphy"
+ "lantiq,xrx200a2x-gphy"
+ "lantiq,xrx300-gphy"
+ "lantiq,xrx330-gphy"
+- reg : Addrress of the GPHY FW load address register
+- resets : Must reference the RCU GPHY reset bit
+- reset-names : One entry, value must be "gphy" or optional "gphy2"
+- clocks : A reference to the (PMU) GPHY clock gate
+
+Optional properties:
+- lantiq,gphy-mode : GPHY_MODE_GE (default) or GPHY_MODE_FE as defined in
+ <dt-bindings/mips/lantiq_xway_gphy.h>
+
+
+-------------------------------------------------------------------------------
+Example for the GPHys on the xRX200 SoCs:
+
+#include <dt-bindings/mips/lantiq_rcu_gphy.h>
+ gphy0: gphy@20 {
+ compatible = "lantiq,xrx200a2x-gphy";
+ reg = <0x20 0x4>;
+
+ resets = <&reset0 31 30>, <&reset1 7 7>;
+ reset-names = "gphy", "gphy2";
+ clocks = <&pmu0 XRX200_PMU_GATE_GPHY>;
+ lantiq,gphy-mode = <GPHY_MODE_GE>;
+ };
diff --git a/Bindings/mips/lantiq/rcu.txt b/Bindings/mips/lantiq/rcu.txt
new file mode 100644
index 000000000000..a086f1e1cdd7
--- /dev/null
+++ b/Bindings/mips/lantiq/rcu.txt
@@ -0,0 +1,89 @@
+Lantiq XWAY SoC RCU binding
+===========================
+
+This binding describes the RCU (reset controller unit) multifunction device,
+where each sub-device has it's own set of registers.
+
+The RCU register range is used for multiple purposes. Mostly one device
+uses one or multiple register exclusively, but for some registers some
+bits are for one driver and some other bits are for a different driver.
+With this patch all accesses to the RCU registers will go through
+syscon.
+
+
+-------------------------------------------------------------------------------
+Required properties:
+- compatible : The first and second values must be:
+ "lantiq,xrx200-rcu", "simple-mfd", "syscon"
+- reg : The address and length of the system control registers
+
+
+-------------------------------------------------------------------------------
+Example of the RCU bindings on a xRX200 SoC:
+ rcu0: rcu@203000 {
+ compatible = "lantiq,xrx200-rcu", "simple-mfd", "syscon";
+ reg = <0x203000 0x100>;
+ ranges = <0x0 0x203000 0x100>;
+ big-endian;
+
+ gphy0: gphy@20 {
+ compatible = "lantiq,xrx200a2x-gphy";
+ reg = <0x20 0x4>;
+
+ resets = <&reset0 31 30>, <&reset1 7 7>;
+ reset-names = "gphy", "gphy2";
+ lantiq,gphy-mode = <GPHY_MODE_GE>;
+ };
+
+ gphy1: gphy@68 {
+ compatible = "lantiq,xrx200a2x-gphy";
+ reg = <0x68 0x4>;
+
+ resets = <&reset0 29 28>, <&reset1 6 6>;
+ reset-names = "gphy", "gphy2";
+ lantiq,gphy-mode = <GPHY_MODE_GE>;
+ };
+
+ reset0: reset-controller@10 {
+ compatible = "lantiq,xrx200-reset";
+ reg = <0x10 4>, <0x14 4>;
+
+ #reset-cells = <2>;
+ };
+
+ reset1: reset-controller@48 {
+ compatible = "lantiq,xrx200-reset";
+ reg = <0x48 4>, <0x24 4>;
+
+ #reset-cells = <2>;
+ };
+
+ usb_phy0: usb2-phy@18 {
+ compatible = "lantiq,xrx200-usb2-phy";
+ reg = <0x18 4>, <0x38 4>;
+ status = "disabled";
+
+ resets = <&reset1 4 4>, <&reset0 4 4>;
+ reset-names = "phy", "ctrl";
+ #phy-cells = <0>;
+ };
+
+ usb_phy1: usb2-phy@34 {
+ compatible = "lantiq,xrx200-usb2-phy";
+ reg = <0x34 4>, <0x3C 4>;
+ status = "disabled";
+
+ resets = <&reset1 5 4>, <&reset0 4 4>;
+ reset-names = "phy", "ctrl";
+ #phy-cells = <0>;
+ };
+
+ reboot@10 {
+ compatible = "syscon-reboot";
+ reg = <0x10 4>;
+
+ regmap = <&rcu0>;
+ offset = <0x10>;
+ mask = <0x40000000>;
+ };
+ };
diff --git a/Bindings/mips/ni.txt b/Bindings/mips/ni.txt
new file mode 100644
index 000000000000..722bf2d62da9
--- /dev/null
+++ b/Bindings/mips/ni.txt
@@ -0,0 +1,7 @@
+National Instruments MIPS platforms
+
+required root node properties:
+ - compatible: must be "ni,169445"
+
+CPU Nodes
+ - compatible: must be "mti,mips14KEc"
diff --git a/Bindings/mips/ralink.txt b/Bindings/mips/ralink.txt
index b35a8d04f8b6..a16e8d7fe56c 100644
--- a/Bindings/mips/ralink.txt
+++ b/Bindings/mips/ralink.txt
@@ -15,3 +15,4 @@ value must be one of the following values:
ralink,rt5350-soc
ralink,mt7620a-soc
ralink,mt7620n-soc
+ ralink,mt7628a-soc
diff --git a/Bindings/misc/atmel-ssc.txt b/Bindings/misc/atmel-ssc.txt
index f8629bb73945..f9fb412642fe 100644
--- a/Bindings/misc/atmel-ssc.txt
+++ b/Bindings/misc/atmel-ssc.txt
@@ -47,5 +47,4 @@ ssc0: ssc@f0010000 {
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
- status = "disabled";
};
diff --git a/Bindings/mmc/arasan,sdhci.txt b/Bindings/mmc/arasan,sdhci.txt
index 49df630bd44f..60481bfc3d31 100644
--- a/Bindings/mmc/arasan,sdhci.txt
+++ b/Bindings/mmc/arasan,sdhci.txt
@@ -74,5 +74,4 @@ Example:
phys = <&emmc_phy>;
phy-names = "phy_arasan";
#clock-cells = <0>;
- status = "disabled";
};
diff --git a/Bindings/mmc/davinci_mmc.txt b/Bindings/mmc/davinci_mmc.txt
index e5a0140b2381..516fb0143d4c 100644
--- a/Bindings/mmc/davinci_mmc.txt
+++ b/Bindings/mmc/davinci_mmc.txt
@@ -24,7 +24,6 @@ mmc0: mmc@1c40000 {
compatible = "ti,da830-mmc",
reg = <0x40000 0x1000>;
interrupts = <16>;
- status = "okay";
bus-width = <4>;
max-frequency = <50000000>;
dmas = <&edma 16
diff --git a/Bindings/mmc/fsl-imx-mmc.txt b/Bindings/mmc/fsl-imx-mmc.txt
index db442355cd24..184ccffe2739 100644
--- a/Bindings/mmc/fsl-imx-mmc.txt
+++ b/Bindings/mmc/fsl-imx-mmc.txt
@@ -20,5 +20,4 @@ sdhci1: sdhci@10014000 {
dma-names = "rx-tx";
bus-width = <4>;
cd-gpios = <&gpio3 29>;
- status = "okay";
};
diff --git a/Bindings/mmc/marvell,xenon-sdhci.txt b/Bindings/mmc/marvell,xenon-sdhci.txt
index b878a1e305af..ed1456f5c94d 100644
--- a/Bindings/mmc/marvell,xenon-sdhci.txt
+++ b/Bindings/mmc/marvell,xenon-sdhci.txt
@@ -16,11 +16,13 @@ Required Properties:
- clocks:
Array of clocks required for SDHC.
- Require at least input clock for Xenon IP core.
+ Require at least input clock for Xenon IP core. For Armada AP806 and
+ CP110, the AXI clock is also mandatory.
- clock-names:
Array of names corresponding to clocks property.
The input clock for Xenon IP core should be named as "core".
+ The input clock for the AXI bus must be named as "axi".
- reg:
* For "marvell,armada-3700-sdhci", two register areas.
@@ -106,8 +108,8 @@ Example:
compatible = "marvell,armada-ap806-sdhci";
reg = <0xaa0000 0x1000>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>
- clocks = <&emmc_clk>;
- clock-names = "core";
+ clocks = <&emmc_clk>,<&axi_clk>;
+ clock-names = "core", "axi";
bus-width = <4>;
marvell,xenon-phy-slow-mode;
marvell,xenon-tun-count = <11>;
@@ -126,8 +128,8 @@ Example:
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>
vqmmc-supply = <&sd_vqmmc_regulator>;
vmmc-supply = <&sd_vmmc_regulator>;
- clocks = <&sdclk>;
- clock-names = "core";
+ clocks = <&sdclk>, <&axi_clk>;
+ clock-names = "core", "axi";
bus-width = <4>;
marvell,xenon-tun-count = <9>;
};
diff --git a/Bindings/mmc/mmc-card.txt b/Bindings/mmc/mmc-card.txt
index a70fcd65b9ea..8d2d71758907 100644
--- a/Bindings/mmc/mmc-card.txt
+++ b/Bindings/mmc/mmc-card.txt
@@ -21,7 +21,6 @@ Example:
vmmc-supply = <&reg_vcc3v3>;
bus-width = <8>;
non-removable;
- status = "okay";
mmccard: mmccard@0 {
reg = <0>;
diff --git a/Bindings/mmc/mmc.txt b/Bindings/mmc/mmc.txt
index c7f4a0ec48ed..b32ade645ad9 100644
--- a/Bindings/mmc/mmc.txt
+++ b/Bindings/mmc/mmc.txt
@@ -153,7 +153,6 @@ mmc3: mmc@01c12000 {
bus-width = <4>;
non-removable;
mmc-pwrseq = <&sdhci0_pwrseq>
- status = "okay";
brcmf: bcrmf@1 {
reg = <1>;
diff --git a/Bindings/mmc/orion-sdio.txt b/Bindings/mmc/orion-sdio.txt
index 84f0ebd67a13..10f0818a34c5 100644
--- a/Bindings/mmc/orion-sdio.txt
+++ b/Bindings/mmc/orion-sdio.txt
@@ -13,5 +13,4 @@ Example:
reg = <0xd00d4000 0x200>;
interrupts = <54>;
clocks = <&gateclk 17>;
- status = "disabled";
};
diff --git a/Bindings/mmc/renesas,mmcif.txt b/Bindings/mmc/renesas,mmcif.txt
index c32dc5a9dbe6..5ff1e12c655a 100644
--- a/Bindings/mmc/renesas,mmcif.txt
+++ b/Bindings/mmc/renesas,mmcif.txt
@@ -11,6 +11,8 @@ Required properties:
- "renesas,mmcif-r7s72100" for the MMCIF found in r7s72100 SoCs
- "renesas,mmcif-r8a73a4" for the MMCIF found in r8a73a4 SoCs
- "renesas,mmcif-r8a7740" for the MMCIF found in r8a7740 SoCs
+ - "renesas,mmcif-r8a7743" for the MMCIF found in r8a7743 SoCs
+ - "renesas,mmcif-r8a7745" for the MMCIF found in r8a7745 SoCs
- "renesas,mmcif-r8a7778" for the MMCIF found in r8a7778 SoCs
- "renesas,mmcif-r8a7790" for the MMCIF found in r8a7790 SoCs
- "renesas,mmcif-r8a7791" for the MMCIF found in r8a7791 SoCs
@@ -21,7 +23,7 @@ Required properties:
- interrupts: Some SoCs have only 1 shared interrupt, while others have either
2 or 3 individual interrupts (error, int, card detect). Below is the number
of interrupts for each SoC:
- 1: r8a73a4, r8a7778, r8a7790, r8a7791, r8a7793, r8a7794
+ 1: r8a73a4, r8a7743, r8a7745, r8a7778, r8a7790, r8a7791, r8a7793, r8a7794
2: r8a7740, sh73a0
3: r7s72100
diff --git a/Bindings/mmc/rockchip-dw-mshc.txt b/Bindings/mmc/rockchip-dw-mshc.txt
index 49ed3ad2524a..c6558785e61b 100644
--- a/Bindings/mmc/rockchip-dw-mshc.txt
+++ b/Bindings/mmc/rockchip-dw-mshc.txt
@@ -15,6 +15,7 @@ Required Properties:
- "rockchip,rk3288-dw-mshc": for Rockchip RK3288
- "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RV1108
- "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3036
+ - "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK322x
- "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3328
- "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3368
- "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3399
diff --git a/Bindings/mmc/sdhci-st.txt b/Bindings/mmc/sdhci-st.txt
index 230fd696eb92..e35645598315 100644
--- a/Bindings/mmc/sdhci-st.txt
+++ b/Bindings/mmc/sdhci-st.txt
@@ -63,7 +63,6 @@ Example:
mmc0: sdhci@fe81e000 {
compatible = "st,sdhci";
- status = "disabled";
reg = <0xfe81e000 0x1000>;
interrupts = <GIC_SPI 127 IRQ_TYPE_NONE>;
interrupt-names = "mmcirq";
@@ -77,7 +76,6 @@ mmc0: sdhci@fe81e000 {
mmc1: sdhci@09080000 {
compatible = "st,sdhci-stih407", "st,sdhci";
- status = "disabled";
reg = <0x09080000 0x7ff>;
reg-names = "mmc";
interrupts = <GIC_SPI 90 IRQ_TYPE_NONE>;
@@ -94,7 +92,6 @@ mmc1: sdhci@09080000 {
mmc0: sdhci@09060000 {
compatible = "st,sdhci-stih407", "st,sdhci";
- status = "disabled";
reg = <0x09060000 0x7ff>, <0x9061008 0x20>;
reg-names = "mmc", "top-mmc-delay";
interrupts = <GIC_SPI 92 IRQ_TYPE_NONE>;
diff --git a/Bindings/mmc/sunxi-mmc.txt b/Bindings/mmc/sunxi-mmc.txt
index 7d53a799f140..63b57e2a10fb 100644
--- a/Bindings/mmc/sunxi-mmc.txt
+++ b/Bindings/mmc/sunxi-mmc.txt
@@ -12,6 +12,7 @@ Required properties:
* "allwinner,sun4i-a10-mmc"
* "allwinner,sun5i-a13-mmc"
* "allwinner,sun7i-a20-mmc"
+ * "allwinner,sun8i-a83t-emmc"
* "allwinner,sun9i-a80-mmc"
* "allwinner,sun50i-a64-emmc"
* "allwinner,sun50i-a64-mmc"
diff --git a/Bindings/mmc/ti-omap-hsmmc.txt b/Bindings/mmc/ti-omap-hsmmc.txt
index 0e026c151c1c..3a4ac401e6f9 100644
--- a/Bindings/mmc/ti-omap-hsmmc.txt
+++ b/Bindings/mmc/ti-omap-hsmmc.txt
@@ -1,33 +1,55 @@
-* TI Highspeed MMC host controller for OMAP
+* TI Highspeed MMC host controller for OMAP and 66AK2G family.
-The Highspeed MMC Host Controller on TI OMAP family
+The Highspeed MMC Host Controller on TI OMAP and 66AK2G family
provides an interface for MMC, SD, and SDIO types of memory cards.
This file documents differences between the core properties described
by mmc.txt and the properties used by the omap_hsmmc driver.
Required properties:
+--------------------
- compatible:
Should be "ti,omap2-hsmmc", for OMAP2 controllers
Should be "ti,omap3-hsmmc", for OMAP3 controllers
Should be "ti,omap3-pre-es3-hsmmc" for OMAP3 controllers pre ES3.0
Should be "ti,omap4-hsmmc", for OMAP4 controllers
Should be "ti,am33xx-hsmmc", for AM335x controllers
-- ti,hwmods: Must be "mmc<n>", n is controller instance starting 1
+ Should be "ti,k2g-hsmmc", "ti,omap4-hsmmc" for 66AK2G controllers.
+
+SoC specific required properties:
+---------------------------------
+The following are mandatory properties for OMAPs, AM33xx and AM43xx SoCs only:
+- ti,hwmods: Must be "mmc<n>", n is controller instance starting 1.
+
+The following are mandatory properties for 66AK2G SoCs only:
+- power-domains:Should contain a phandle to a PM domain provider node
+ and an args specifier containing the MMC device id
+ value. This property is as per the binding,
+ Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
+- clocks: Must contain an entry for each entry in clock-names. Should
+ be defined as per the he appropriate clock bindings consumer
+ usage in Documentation/devicetree/bindings/clock/ti,sci-clk.txt
+- clock-names: Shall be "fck" for the functional clock,
+ and "mmchsdb_fck" for the debounce clock.
+
Optional properties:
-ti,dual-volt: boolean, supports dual voltage cards
-<supply-name>-supply: phandle to the regulator device tree node
-"supply-name" examples are "vmmc", "vmmc_aux"(deprecated)/"vqmmc" etc
-ti,non-removable: non-removable slot (like eMMC)
-ti,needs-special-reset: Requires a special softreset sequence
-ti,needs-special-hs-handling: HSMMC IP needs special setting for handling High Speed
-dmas: List of DMA specifiers with the controller specific format
-as described in the generic DMA client binding. A tx and rx
-specifier is required.
-dma-names: List of DMA request names. These strings correspond
-1:1 with the DMA specifiers listed in dmas. The string naming is
-to be "rx" and "tx" for RX and TX DMA requests, respectively.
+--------------------
+- ti,dual-volt: boolean, supports dual voltage cards
+- <supply-name>-supply: phandle to the regulator device tree node
+ "supply-name" examples are "vmmc",
+ "vmmc_aux"(deprecated)/"vqmmc" etc
+- ti,non-removable: non-removable slot (like eMMC)
+- ti,needs-special-reset: Requires a special softreset sequence
+- ti,needs-special-hs-handling: HSMMC IP needs special setting
+ for handling High Speed
+- dmas: List of DMA specifiers with the controller specific
+ format as described in the generic DMA client
+ binding. A tx and rx specifier is required.
+- dma-names: List of DMA request names. These strings correspond
+ 1:1 with the DMA specifiers listed in dmas.
+ The string naming is to be "rx" and "tx" for
+ RX and TX DMA requests, respectively.
Examples:
diff --git a/Bindings/mmc/tmio_mmc.txt b/Bindings/mmc/tmio_mmc.txt
index 4fd8b7acc510..54ef642f23a0 100644
--- a/Bindings/mmc/tmio_mmc.txt
+++ b/Bindings/mmc/tmio_mmc.txt
@@ -15,6 +15,8 @@ Required properties:
"renesas,sdhi-r7s72100" - SDHI IP on R7S72100 SoC
"renesas,sdhi-r8a73a4" - SDHI IP on R8A73A4 SoC
"renesas,sdhi-r8a7740" - SDHI IP on R8A7740 SoC
+ "renesas,sdhi-r8a7743" - SDHI IP on R8A7743 SoC
+ "renesas,sdhi-r8a7745" - SDHI IP on R8A7745 SoC
"renesas,sdhi-r8a7778" - SDHI IP on R8A7778 SoC
"renesas,sdhi-r8a7779" - SDHI IP on R8A7779 SoC
"renesas,sdhi-r8a7790" - SDHI IP on R8A7790 SoC
@@ -33,10 +35,8 @@ Required properties:
If 2 clocks are specified by the hardware, you must name them as
"core" and "cd". If the controller only has 1 clock, naming is not
required.
- Below is the number clocks for each supported SoC:
- 1: SH73A0, R8A73A4, R8A7740, R8A7778, R8A7779, R8A7790
- R8A7791, R8A7792, R8A7793, R8A7794, R8A7795, R8A7796
- 2: R7S72100
+ Devices which have more than 1 clock are listed below:
+ 2: R7S72100
Optional properties:
- toshiba,mmc-wrprotect-disable: write-protect detection is unavailable
diff --git a/Bindings/mmc/zx-dw-mshc.txt b/Bindings/mmc/zx-dw-mshc.txt
index 906819a90c2b..0f59bd5361f5 100644
--- a/Bindings/mmc/zx-dw-mshc.txt
+++ b/Bindings/mmc/zx-dw-mshc.txt
@@ -28,5 +28,4 @@ Example:
max-frequency = <50000000>;
cap-sdio-irq;
cap-sd-highspeed;
- status = "disabled";
};
diff --git a/Bindings/mtd/atmel-quadspi.txt b/Bindings/mtd/atmel-quadspi.txt
index 489807005eda..b93c1e2f25dd 100644
--- a/Bindings/mtd/atmel-quadspi.txt
+++ b/Bindings/mtd/atmel-quadspi.txt
@@ -24,7 +24,6 @@ spi@f0020000 {
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0_default>;
- status = "okay";
m25p80@0 {
...
diff --git a/Bindings/mtd/mtk-quadspi.txt b/Bindings/mtd/mtk-quadspi.txt
index 5ded66ad7aef..840f9405dcf0 100644
--- a/Bindings/mtd/mtk-quadspi.txt
+++ b/Bindings/mtd/mtk-quadspi.txt
@@ -37,7 +37,6 @@ nor_flash: spi@1100d000 {
clock-names = "spi", "sf";
#address-cells = <1>;
#size-cells = <0>;
- status = "disabled";
flash@0 {
compatible = "jedec,spi-nor";
diff --git a/Bindings/mtd/qcom_nandc.txt b/Bindings/mtd/qcom_nandc.txt
index 70dd5118a324..73d336befa08 100644
--- a/Bindings/mtd/qcom_nandc.txt
+++ b/Bindings/mtd/qcom_nandc.txt
@@ -1,11 +1,20 @@
* Qualcomm NAND controller
Required properties:
-- compatible: should be "qcom,ipq806x-nand"
+- compatible: must be one of the following:
+ * "qcom,ipq806x-nand" - for EBI2 NAND controller being used in IPQ806x
+ SoC and it uses ADM DMA
+ * "qcom,ipq4019-nand" - for QPIC NAND controller v1.4.0 being used in
+ IPQ4019 SoC and it uses BAM DMA
+ * "qcom,ipq8074-nand" - for QPIC NAND controller v1.5.0 being used in
+ IPQ8074 SoC and it uses BAM DMA
+
- reg: MMIO address range
- clocks: must contain core clock and always on clock
- clock-names: must contain "core" for the core clock and "aon" for the
always on clock
+
+EBI2 specific properties:
- dmas: DMA specifier, consisting of a phandle to the ADM DMA
controller node and the channel number to be used for
NAND. Refer to dma.txt and qcom_adm.txt for more details
@@ -16,6 +25,12 @@ Required properties:
- qcom,data-crci: must contain the ADM data type CRCI block instance
number specified for the NAND controller on the given
platform
+
+QPIC specific properties:
+- dmas: DMA specifier, consisting of a phandle to the BAM DMA
+ and the channel number to be used for NAND. Refer to
+ dma.txt, qcom_bam_dma.txt for more details
+- dma-names: must contain all 3 channel names : "tx", "rx", "cmd"
- #address-cells: <1> - subnodes give the chip-select number
- #size-cells: <0>
@@ -26,7 +41,6 @@ chip-selects which (may) contain NAND flash chips. Their properties are as
follows.
Required properties:
-- compatible: should contain "qcom,nandcs"
- reg: a single integer representing the chip-select
number (e.g., 0, 1, 2, etc.)
- #address-cells: see partition.txt
@@ -43,8 +57,8 @@ partition.txt for more detail.
Example:
-nand@1ac00000 {
- compatible = "qcom,ebi2-nandc";
+nand-controller@1ac00000 {
+ compatible = "qcom,ipq806x-nand";
reg = <0x1ac00000 0x800>;
clocks = <&gcc EBI2_CLK>,
@@ -59,8 +73,7 @@ nand@1ac00000 {
#address-cells = <1>;
#size-cells = <0>;
- nandcs@0 {
- compatible = "qcom,nandcs";
+ nand@0 {
reg = <0>;
nand-ecc-strength = <4>;
@@ -84,3 +97,43 @@ nand@1ac00000 {
};
};
};
+
+nand-controller@79b0000 {
+ compatible = "qcom,ipq4019-nand";
+ reg = <0x79b0000 0x1000>;
+
+ clocks = <&gcc GCC_QPIC_CLK>,
+ <&gcc GCC_QPIC_AHB_CLK>;
+ clock-names = "core", "aon";
+
+ dmas = <&qpicbam 0>,
+ <&qpicbam 1>,
+ <&qpicbam 2>;
+ dma-names = "tx", "rx", "cmd";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ nand@0 {
+ reg = <0>;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ nand-bus-width = <8>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "boot-nand";
+ reg = <0 0x58a0000>;
+ };
+
+ partition@58a0000 {
+ label = "fs-nand";
+ reg = <0x58a0000 0x4000000>;
+ };
+ };
+ };
+};
diff --git a/Bindings/mtd/st-fsm.txt b/Bindings/mtd/st-fsm.txt
index c2489391c437..54cef9ef3083 100644
--- a/Bindings/mtd/st-fsm.txt
+++ b/Bindings/mtd/st-fsm.txt
@@ -21,6 +21,5 @@ Example:
st,syscfg = <&syscfg_rear>;
st,boot-device-reg = <0x958>;
st,boot-device-spi = <0x1a>;
- status = "okay";
};
diff --git a/Bindings/mtd/sunxi-nand.txt b/Bindings/mtd/sunxi-nand.txt
index f322f56aef74..a37c67bcb43b 100644
--- a/Bindings/mtd/sunxi-nand.txt
+++ b/Bindings/mtd/sunxi-nand.txt
@@ -41,7 +41,6 @@ nfc: nand@01c03000 {
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&nand_pins_a &nand_cs0_pins_a &nand_rb0_pins_a>;
- status = "okay";
nand@0 {
reg = <0>;
diff --git a/Bindings/net/anarion-gmac.txt b/Bindings/net/anarion-gmac.txt
new file mode 100644
index 000000000000..fe678965ae69
--- /dev/null
+++ b/Bindings/net/anarion-gmac.txt
@@ -0,0 +1,25 @@
+* Adaptrum Anarion ethernet controller
+
+This device is a platform glue layer for stmmac.
+Please see stmmac.txt for the other unchanged properties.
+
+Required properties:
+ - compatible: Should be "adaptrum,anarion-gmac", "snps,dwmac"
+ - phy-mode: Should be "rgmii". Other modes are not currently supported.
+
+
+Examples:
+
+ gmac1: ethernet@f2014000 {
+ compatible = "adaptrum,anarion-gmac", "snps,dwmac";
+ reg = <0xf2014000 0x4000>, <0xf2018100 8>;
+
+ interrupt-parent = <&core_intc>;
+ interrupts = <21>;
+ interrupt-names = "macirq";
+
+ clocks = <&core_clk>;
+ clock-names = "stmmaceth";
+
+ phy-mode = "rgmii";
+ };
diff --git a/Bindings/net/brcm,amac.txt b/Bindings/net/brcm,amac.txt
index ad16c1f481f7..0bfad656a9ff 100644
--- a/Bindings/net/brcm,amac.txt
+++ b/Bindings/net/brcm,amac.txt
@@ -27,5 +27,4 @@ amac0: ethernet@18022000 {
<0x18110000 0x1000>;
reg-names = "amac_base", "idm_base";
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
};
diff --git a/Bindings/net/broadcom-bluetooth.txt b/Bindings/net/broadcom-bluetooth.txt
new file mode 100644
index 000000000000..4194ff7e6ee6
--- /dev/null
+++ b/Bindings/net/broadcom-bluetooth.txt
@@ -0,0 +1,35 @@
+Broadcom Bluetooth Chips
+---------------------
+
+This documents the binding structure and common properties for serial
+attached Broadcom devices.
+
+Serial attached Broadcom devices shall be a child node of the host UART
+device the slave device is attached to.
+
+Required properties:
+
+ - compatible: should contain one of the following:
+ * "brcm,bcm43438-bt"
+
+Optional properties:
+
+ - max-speed: see Documentation/devicetree/bindings/serial/slave-device.txt
+ - shutdown-gpios: GPIO specifier, used to enable the BT module
+ - device-wakeup-gpios: GPIO specifier, used to wakeup the controller
+ - host-wakeup-gpios: GPIO specifier, used to wakeup the host processor
+ - clocks: clock specifier if external clock provided to the controller
+ - clock-names: should be "extclk"
+
+
+Example:
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ max-speed = <921600>;
+ };
+};
diff --git a/Bindings/net/btusb.txt b/Bindings/net/btusb.txt
index 01fa2d4188d4..9c5e663fa1af 100644
--- a/Bindings/net/btusb.txt
+++ b/Bindings/net/btusb.txt
@@ -29,7 +29,6 @@ Example:
Following example uses irq pin number 3 of gpio0 for out of band wake-on-bt:
&usb_host1_ehci {
- status = "okay";
#address-cells = <1>;
#size-cells = <0>;
diff --git a/Bindings/net/can/c_can.txt b/Bindings/net/can/c_can.txt
index 5a1d8b0c39e9..2d504256b0d8 100644
--- a/Bindings/net/can/c_can.txt
+++ b/Bindings/net/can/c_can.txt
@@ -11,9 +11,20 @@ Required properties:
- interrupts : property with a value describing the interrupt
number
-Optional properties:
+The following are mandatory properties for DRA7x, AM33xx and AM43xx SoCs only:
- ti,hwmods : Must be "d_can<n>" or "c_can<n>", n being the
instance number
+
+The following are mandatory properties for Keystone 2 66AK2G SoCs only:
+- power-domains : Should contain a phandle to a PM domain provider node
+ and an args specifier containing the DCAN device id
+ value. This property is as per the binding,
+ Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
+- clocks : CAN functional clock phandle. This property is as per the
+ binding,
+ Documentation/devicetree/bindings/clock/ti,sci-clk.txt
+
+Optional properties:
- syscon-raminit : Handle to system control region that contains the
RAMINIT register, register offset to the RAMINIT
register and the CAN instance number (0 offset).
diff --git a/Bindings/net/can/m_can.txt b/Bindings/net/can/m_can.txt
index 9e331777c203..78138333ff7a 100644
--- a/Bindings/net/can/m_can.txt
+++ b/Bindings/net/can/m_can.txt
@@ -56,7 +56,6 @@ m_can1: can@020e8000 {
<&clks IMX6SX_CLK_CANFD>;
clock-names = "hclk", "cclk";
bosch,mram-cfg = <0x0 0 0 32 0 0 0 1>;
- status = "disabled";
};
Board dts:
diff --git a/Bindings/net/dsa/ksz.txt b/Bindings/net/dsa/ksz.txt
index 0ab8b39d0b30..fd23904ac68e 100644
--- a/Bindings/net/dsa/ksz.txt
+++ b/Bindings/net/dsa/ksz.txt
@@ -24,7 +24,6 @@ Ethernet switch connected via SPI to the host, CPU port wired to eth0:
pinctrl-0 = <&pinctrl_spi_ksz>;
cs-gpios = <&pioC 25 0>;
id = <1>;
- status = "okay";
ksz9477: ksz9477@0 {
compatible = "microchip,ksz9477";
@@ -34,7 +33,6 @@ Ethernet switch connected via SPI to the host, CPU port wired to eth0:
spi-cpha;
spi-cpol;
- status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/Bindings/net/dsa/lan9303.txt b/Bindings/net/dsa/lan9303.txt
index 04f2965a4467..4448d063ddf6 100644
--- a/Bindings/net/dsa/lan9303.txt
+++ b/Bindings/net/dsa/lan9303.txt
@@ -27,7 +27,6 @@ Example:
I2C managed mode:
master: masterdevice@X {
- status = "okay";
fixed-link { /* RMII fixed link to LAN9303 */
speed = <100>;
@@ -38,7 +37,6 @@ I2C managed mode:
switch: switch@a {
compatible = "smsc,lan9303-i2c";
reg = <0xa>;
- status = "okay";
reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
reset-duration = <200>;
@@ -67,7 +65,6 @@ I2C managed mode:
MDIO managed mode:
master: masterdevice@X {
- status = "okay";
phy-handle = <&switch>;
mdio {
diff --git a/Bindings/net/ethernet.txt b/Bindings/net/ethernet.txt
index 7da86f22a13b..2974e63ba311 100644
--- a/Bindings/net/ethernet.txt
+++ b/Bindings/net/ethernet.txt
@@ -1,5 +1,9 @@
The following properties are common to the Ethernet controllers:
+NOTE: All 'phy*' properties documented below are Ethernet specific. For the
+generic PHY 'phys' property, see
+Documentation/devicetree/bindings/phy/phy-bindings.txt.
+
- local-mac-address: array of 6 bytes, specifies the MAC address that was