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authorEmmanuel Vadot <manu@FreeBSD.org>2021-01-14 15:25:07 +0000
committerEmmanuel Vadot <manu@FreeBSD.org>2021-01-14 15:25:07 +0000
commit5ee353c36d3c9c7f63df7c7671875e73fba70958 (patch)
tree77f0dc489fc4baaf2bab03da6d182a7339bc1297
parent2554fe8f89383d8dedd834b46a9f616a277f8af4 (diff)
downloadsrc-vendor/device-tree/5.9.tar.gz
src-vendor/device-tree/5.9.zip
Import device tree files from Linux 5.9vendor/device-tree/5.9
-rw-r--r--Bindings/arm/amazon,al.yaml33
-rw-r--r--Bindings/arm/amlogic.yaml1
-rw-r--r--Bindings/arm/arm,integrator.yaml6
-rw-r--r--Bindings/arm/arm,realview.yaml66
-rw-r--r--Bindings/arm/arm,scmi.txt2
-rw-r--r--Bindings/arm/arm,scpi.txt2
-rw-r--r--Bindings/arm/arm,vexpress-juno.yaml12
-rw-r--r--Bindings/arm/bcm/brcm,bcm11351.yaml2
-rw-r--r--Bindings/arm/bcm/brcm,bcm21664.yaml2
-rw-r--r--Bindings/arm/bcm/brcm,bcm23550.yaml2
-rw-r--r--Bindings/arm/bcm/brcm,cygnus.yaml20
-rw-r--r--Bindings/arm/bcm/brcm,hr2.yaml2
-rw-r--r--Bindings/arm/bcm/brcm,ns2.yaml4
-rw-r--r--Bindings/arm/bcm/brcm,nsp.yaml14
-rw-r--r--Bindings/arm/bcm/brcm,stingray.yaml6
-rw-r--r--Bindings/arm/bcm/brcm,vulcan-soc.yaml4
-rw-r--r--Bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml68
-rw-r--r--Bindings/arm/coresight-cti.yaml20
-rw-r--r--Bindings/arm/coresight.txt13
-rw-r--r--Bindings/arm/cpus.yaml4
-rw-r--r--Bindings/arm/freescale/fsl,scu.txt2
-rw-r--r--Bindings/arm/fsl.yaml18
-rw-r--r--Bindings/arm/intel,keembay.yaml19
-rw-r--r--Bindings/arm/keystone/ti,k3-sci-common.yaml44
-rw-r--r--Bindings/arm/marvell/ap80x-system-controller.txt2
-rw-r--r--Bindings/arm/marvell/cp110-system-controller.txt2
-rw-r--r--Bindings/arm/mediatek.yaml5
-rw-r--r--Bindings/arm/mediatek/mediatek,pericfg.yaml30
-rw-r--r--Bindings/arm/microchip,sparx5.yaml65
-rw-r--r--Bindings/arm/mstar/mstar,l3bridge.yaml44
-rw-r--r--Bindings/arm/mstar/mstar.yaml33
-rw-r--r--Bindings/arm/nvidia,tegra194-ccplex.yaml69
-rw-r--r--Bindings/arm/renesas.yaml13
-rw-r--r--Bindings/arm/rockchip.yaml6
-rw-r--r--Bindings/arm/stm32/st,stm32-syscon.yaml14
-rw-r--r--Bindings/arm/sunxi.yaml5
-rw-r--r--Bindings/arm/tegra.yaml18
-rw-r--r--Bindings/bus/baikal,bt1-apb.yaml2
-rw-r--r--Bindings/bus/baikal,bt1-axi.yaml2
-rw-r--r--Bindings/bus/mti,mips-cdmm.yaml35
-rw-r--r--Bindings/clock/brcm,bcm2711-dvp.yaml47
-rw-r--r--Bindings/clock/brcm,bcm63xx-clocks.txt2
-rw-r--r--Bindings/clock/clock-bindings.txt2
-rw-r--r--Bindings/clock/idt,versaclock5.yaml154
-rw-r--r--Bindings/clock/imx23-clock.yaml2
-rw-r--r--Bindings/clock/imx28-clock.yaml2
-rw-r--r--Bindings/clock/imx35-clock.yaml2
-rw-r--r--Bindings/clock/imx7ulp-pcc-clock.yaml121
-rw-r--r--Bindings/clock/imx7ulp-scg-clock.yaml99
-rw-r--r--Bindings/clock/imx8qxp-lpcg.yaml2
-rw-r--r--Bindings/clock/ingenic,cgu.yaml16
-rw-r--r--Bindings/clock/microchip,sparx5-dpll.yaml52
-rw-r--r--Bindings/clock/qcom,a53pll.yaml21
-rw-r--r--Bindings/clock/qcom,gpucc.yaml82
-rw-r--r--Bindings/clock/qcom,mmcc.yaml2
-rw-r--r--Bindings/clock/qcom,msm8996-apcc.yaml54
-rw-r--r--Bindings/clock/qcom,rpmcc.txt4
-rw-r--r--Bindings/clock/qcom,sc7180-lpasscorecc.yaml108
-rw-r--r--Bindings/clock/renesas,cpg-clocks.yaml241
-rw-r--r--Bindings/clock/renesas,cpg-mssr.yaml1
-rw-r--r--Bindings/clock/rockchip,rk3288-cru.txt8
-rw-r--r--Bindings/clock/silabs,si514.txt2
-rw-r--r--Bindings/clock/silabs,si5351.txt2
-rw-r--r--Bindings/clock/silabs,si570.txt4
-rw-r--r--Bindings/clock/sprd,sc9863a-clk.yaml2
-rw-r--r--Bindings/clock/ti,cdce706.txt2
-rw-r--r--Bindings/clock/ti,cdce925.txt8
-rw-r--r--Bindings/cpufreq/cpufreq-dt.txt3
-rw-r--r--Bindings/cpufreq/cpufreq-mediatek.txt4
-rw-r--r--Bindings/cpufreq/nvidia,tegra20-cpufreq.txt2
-rw-r--r--Bindings/crypto/ti,sa2ul.yaml76
-rw-r--r--Bindings/devfreq/rk3399_dmc.txt2
-rw-r--r--Bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml3
-rw-r--r--Bindings/display/brcm,bcm2835-dpi.yaml62
-rw-r--r--Bindings/display/brcm,bcm2835-dsi0.yaml84
-rw-r--r--Bindings/display/brcm,bcm2835-hdmi.yaml79
-rw-r--r--Bindings/display/brcm,bcm2835-hvs.yaml37
-rw-r--r--Bindings/display/brcm,bcm2835-pixelvalve0.yaml40
-rw-r--r--Bindings/display/brcm,bcm2835-txp.yaml37
-rw-r--r--Bindings/display/brcm,bcm2835-v3d.yaml42
-rw-r--r--Bindings/display/brcm,bcm2835-vc4.yaml34
-rw-r--r--Bindings/display/brcm,bcm2835-vec.yaml44
-rw-r--r--Bindings/display/bridge/nwl-dsi.yaml22
-rw-r--r--Bindings/display/bridge/renesas,lvds.yaml248
-rw-r--r--Bindings/display/bridge/simple-bridge.yaml18
-rw-r--r--Bindings/display/bridge/ti,sn65dsi86.yaml293
-rw-r--r--Bindings/display/bridge/ti,tfp410.yaml131
-rw-r--r--Bindings/display/connector/analog-tv-connector.yaml52
-rw-r--r--Bindings/display/connector/dvi-connector.yaml70
-rw-r--r--Bindings/display/connector/hdmi-connector.yaml64
-rw-r--r--Bindings/display/connector/vga-connector.yaml46
-rw-r--r--Bindings/display/dsi-controller.yaml10
-rw-r--r--Bindings/display/ilitek,ili9486.yaml4
-rw-r--r--Bindings/display/ingenic,ipu.yaml65
-rw-r--r--Bindings/display/ingenic,lcd.yaml126
-rw-r--r--Bindings/display/msm/dsi.txt1
-rw-r--r--Bindings/display/msm/gmu.yaml38
-rw-r--r--Bindings/display/msm/gpu.txt28
-rw-r--r--Bindings/display/panel/asus,z00t-tm5p5-nt35596.yaml4
-rw-r--r--Bindings/display/panel/boe,tv101wum-nl6.yaml12
-rw-r--r--Bindings/display/panel/elida,kd35t133.yaml4
-rw-r--r--Bindings/display/panel/feixin,k101-im2ba02.yaml6
-rw-r--r--Bindings/display/panel/ilitek,ili9322.yaml3
-rw-r--r--Bindings/display/panel/ilitek,ili9881c.yaml3
-rw-r--r--Bindings/display/panel/leadtek,ltk050h3146w.yaml4
-rw-r--r--Bindings/display/panel/leadtek,ltk500hd1829.yaml4
-rw-r--r--Bindings/display/panel/novatek,nt35510.yaml4
-rw-r--r--Bindings/display/panel/panel-dsi-cm.yaml86
-rw-r--r--Bindings/display/panel/panel-simple-dsi.yaml2
-rw-r--r--Bindings/display/panel/panel-simple.yaml8
-rw-r--r--Bindings/display/panel/panel-timing.yaml20
-rw-r--r--Bindings/display/panel/raydium,rm68200.yaml4
-rw-r--r--Bindings/display/panel/rocktech,jh057n00900.yaml71
-rw-r--r--Bindings/display/panel/samsung,s6e88a0-ams452ef01.yaml4
-rw-r--r--Bindings/display/panel/samsung,s6e8aa0.yaml100
-rw-r--r--Bindings/display/panel/sharp,lq101r1sx01.yaml87
-rw-r--r--Bindings/display/panel/visionox,rm69299.yaml2
-rw-r--r--Bindings/display/simple-framebuffer.yaml44
-rw-r--r--Bindings/display/st,stm32-dsi.yaml3
-rw-r--r--Bindings/display/ti/ti,j721e-dss.yaml2
-rw-r--r--Bindings/display/tilcdc/tilcdc.txt2
-rw-r--r--Bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml174
-rw-r--r--Bindings/dma/arm-pl330.txt1
-rw-r--r--Bindings/dma/owl-dma.yaml79
-rw-r--r--Bindings/dma/renesas,rcar-dmac.yaml1
-rw-r--r--Bindings/dma/renesas,usb-dmac.yaml2
-rw-r--r--Bindings/dma/snps,dma-spear1340.yaml176
-rw-r--r--Bindings/dma/xilinx/xlnx,zynqmp-dpdma.yaml68
-rw-r--r--Bindings/dsp/fsl,dsp.yaml4
-rw-r--r--Bindings/example-schema.yaml4
-rw-r--r--Bindings/firmware/qcom,scm.txt2
-rw-r--r--Bindings/fpga/fpga-region.txt2
-rw-r--r--Bindings/fpga/xilinx-slave-serial.txt16
-rw-r--r--Bindings/fsi/ibm,fsi2spi.yaml2
-rw-r--r--Bindings/fuse/nvidia,tegra20-fuse.txt5
-rw-r--r--Bindings/gpio/brcm,xgs-iproc-gpio.yaml6
-rw-r--r--Bindings/gpio/gpio-mxs.yaml2
-rw-r--r--Bindings/gpio/gpio-pca953x.txt1
-rw-r--r--Bindings/gpio/gpio-pca9570.yaml47
-rw-r--r--Bindings/gpio/gpio-zynq.txt4
-rw-r--r--Bindings/gpio/mrvl-gpio.yaml173
-rw-r--r--Bindings/gpio/renesas,rcar-gpio.yaml58
-rw-r--r--Bindings/gpio/sgpio-aspeed.txt5
-rw-r--r--Bindings/gpu/nvidia,gk20a.txt25
-rw-r--r--Bindings/gpu/vivante,gc.yaml3
-rw-r--r--Bindings/hwlock/qcom-hwspinlock.yaml42
-rw-r--r--Bindings/hwmon/adi,axi-fan-control.yaml2
-rw-r--r--Bindings/hwmon/gpio-fan.txt3
-rw-r--r--Bindings/hwmon/lm90.txt4
-rw-r--r--Bindings/hwmon/microchip,sparx5-temp.yaml44
-rw-r--r--Bindings/hwmon/ti,tmp513.yaml4
-rw-r--r--Bindings/i2c/i2c-gpio.yaml8
-rw-r--r--Bindings/i2c/i2c-imx-lpi2c.yaml47
-rw-r--r--Bindings/i2c/i2c-imx.yaml103
-rw-r--r--Bindings/i2c/i2c-mt65xx.txt1
-rw-r--r--Bindings/i2c/i2c-mxs.yaml51
-rw-r--r--Bindings/i2c/i2c-pxa.yaml74
-rw-r--r--Bindings/i2c/i2c.txt10
-rw-r--r--Bindings/i2c/marvell,mv64xxx-i2c.yaml3
-rw-r--r--Bindings/i2c/nvidia,tegra20-i2c.txt19
-rw-r--r--Bindings/i2c/renesas,i2c.txt1
-rw-r--r--Bindings/i2c/renesas,iic.txt1
-rw-r--r--Bindings/iio/accel/adi,adxl345.yaml4
-rw-r--r--Bindings/iio/accel/kionix,kxsd9.yaml65
-rw-r--r--Bindings/iio/adc/adi,ad7606.yaml8
-rw-r--r--Bindings/iio/adc/ingenic,adc.yaml71
-rw-r--r--Bindings/iio/adc/maxim,max1238.yaml2
-rw-r--r--Bindings/iio/adc/qcom,spmi-vadc.yaml276
-rw-r--r--Bindings/iio/adc/rockchip-saradc.yaml8
-rw-r--r--Bindings/iio/adc/ti,ads8688.yaml45
-rw-r--r--Bindings/iio/amplifiers/adi,hmc425a.yaml4
-rw-r--r--Bindings/iio/chemical/atlas,sensor.yaml4
-rw-r--r--Bindings/iio/chemical/sensirion,scd30.yaml68
-rw-r--r--Bindings/iio/dac/adi,ad5770r.yaml60
-rw-r--r--Bindings/iio/dac/ti,dac7612.txt2
-rw-r--r--Bindings/iio/iio-bindings.txt2
-rw-r--r--Bindings/iio/imu/bosch,bmi160.yaml14
-rw-r--r--Bindings/iio/imu/invensense,icm42600.yaml90
-rw-r--r--Bindings/iio/light/apds9300.txt2
-rw-r--r--Bindings/iio/light/apds9960.txt2
-rw-r--r--Bindings/iio/light/opt3001.txt2
-rw-r--r--Bindings/iio/light/vishay,vcnl4000.yaml22
-rw-r--r--Bindings/iio/light/vl6180.txt2
-rw-r--r--Bindings/iio/magnetometer/asahi-kasei,ak8975.yaml83
-rw-r--r--Bindings/iio/magnetometer/bmc150_magn.txt6
-rw-r--r--Bindings/iio/multiplexer/io-channel-mux.txt2
-rw-r--r--Bindings/iio/potentiometer/mcp41010.txt2
-rw-r--r--Bindings/iio/potentiostat/lmp91000.txt4
-rw-r--r--Bindings/iio/pressure/asc,dlhl60d.yaml2
-rw-r--r--Bindings/iio/proximity/devantech-srf04.yaml4
-rw-r--r--Bindings/iio/proximity/vishay,vcnl3020.yaml4
-rw-r--r--Bindings/iio/temperature/adi,ltc2983.yaml2
-rw-r--r--Bindings/input/imx-keypad.yaml85
-rw-r--r--Bindings/input/matrix-keymap.txt28
-rw-r--r--Bindings/input/matrix-keymap.yaml46
-rw-r--r--Bindings/input/touchscreen/cypress,cy8ctma140.yaml2
-rw-r--r--Bindings/input/touchscreen/edt-ft5x06.yaml10
-rw-r--r--Bindings/input/touchscreen/eeti,exc3000.yaml58
-rw-r--r--Bindings/input/touchscreen/goodix.yaml5
-rw-r--r--Bindings/input/touchscreen/touchscreen.yaml12
-rw-r--r--Bindings/interconnect/fsl,imx8m-noc.yaml20
-rw-r--r--Bindings/interconnect/qcom,sc7180.yaml2
-rw-r--r--Bindings/interconnect/qcom,sdm845.yaml2
-rw-r--r--Bindings/interrupt-controller/arm,gic.yaml4
-rw-r--r--Bindings/interrupt-controller/brcm,l2-intc.txt5
-rw-r--r--Bindings/interrupt-controller/ingenic,intc.yaml22
-rw-r--r--Bindings/interrupt-controller/loongson,htvec.yaml4
-rw-r--r--Bindings/interrupt-controller/loongson,liointc.yaml4
-rw-r--r--Bindings/interrupt-controller/mrvl,intc.yaml134
-rw-r--r--Bindings/interrupt-controller/mti,gic.yaml146
-rw-r--r--Bindings/interrupt-controller/renesas,rza1-irqc.yaml80
-rw-r--r--Bindings/interrupt-controller/ti,sci-inta.yaml98
-rw-r--r--Bindings/interrupt-controller/ti,sci-intr.yaml102
-rw-r--r--Bindings/iommu/arm,smmu.yaml31
-rw-r--r--Bindings/iommu/mediatek,iommu.txt2
-rw-r--r--Bindings/iommu/renesas,ipmmu-vmsa.yaml2
-rw-r--r--Bindings/leds/backlight/gpio-backlight.yaml41
-rw-r--r--Bindings/leds/backlight/led-backlight.yaml57
-rw-r--r--Bindings/leds/backlight/pwm-backlight.yaml104
-rw-r--r--Bindings/leds/backlight/qcom-wled.yaml3
-rw-r--r--Bindings/leds/cznic,turris-omnia-leds.yaml90
-rw-r--r--Bindings/leds/leds-class-multicolor.yaml37
-rw-r--r--Bindings/leds/leds-lm3532.txt2
-rw-r--r--Bindings/leds/leds-lm3601x.txt4
-rw-r--r--Bindings/leds/leds-lm36274.txt2
-rw-r--r--Bindings/leds/leds-lm3692x.txt2
-rw-r--r--Bindings/leds/leds-lm3697.txt2
-rw-r--r--Bindings/leds/leds-lp55xx.yaml220
-rw-r--r--Bindings/leds/leds-lp8860.txt2
-rw-r--r--Bindings/leds/leds-pca955x.txt6
-rw-r--r--Bindings/mailbox/fsl,mu.yaml12
-rw-r--r--Bindings/mailbox/mtk-gce.txt8
-rw-r--r--Bindings/mailbox/qcom,apcs-kpss-global.yaml2
-rw-r--r--Bindings/mailbox/qcom-ipcc.yaml2
-rw-r--r--Bindings/media/allwinner,sun8i-a83t-de2-rotate.yaml4
-rw-r--r--Bindings/media/allwinner,sun8i-h3-deinterlace.yaml4
-rw-r--r--Bindings/media/i2c/adv7180.yaml183
-rw-r--r--Bindings/media/i2c/chrontel,ch7322.yaml67
-rw-r--r--Bindings/media/i2c/dongwoon,dw9768.yaml97
-rw-r--r--Bindings/media/i2c/imi,rdacm2x-gmsl.yaml159
-rw-r--r--Bindings/media/i2c/maxim,max9286.yaml366
-rw-r--r--Bindings/media/i2c/ov8856.yaml3
-rw-r--r--Bindings/media/i2c/sony,imx274.yaml76
-rw-r--r--Bindings/media/renesas,csi2.yaml18
-rw-r--r--Bindings/media/renesas,fcp.yaml66
-rw-r--r--Bindings/media/renesas,fdp1.yaml69
-rw-r--r--Bindings/media/renesas,vsp1.yaml97
-rw-r--r--Bindings/media/rockchip-vpu.yaml4
-rw-r--r--Bindings/media/xilinx/video.txt2
-rw-r--r--Bindings/media/xilinx/xlnx,csi2rxss.yaml236
-rw-r--r--Bindings/memory-controllers/fsl/mmdc.yaml49
-rw-r--r--Bindings/memory-controllers/ingenic,nemc.yaml8
-rw-r--r--Bindings/memory-controllers/mediatek,smi-common.txt5
-rw-r--r--Bindings/memory-controllers/mediatek,smi-larb.txt3
-rw-r--r--Bindings/memory-controllers/renesas,rpc-if.yaml88
-rw-r--r--Bindings/memory-controllers/st,stm32-fmc2-ebi.yaml252
-rw-r--r--Bindings/mfd/aspeed-lpc.txt2
-rw-r--r--Bindings/mfd/cirrus,madera.yaml34
-rw-r--r--Bindings/mfd/da9062.txt4
-rw-r--r--Bindings/mfd/gateworks-gsc.yaml9
-rw-r--r--Bindings/mfd/google,cros-ec.yaml129
-rw-r--r--Bindings/mfd/khadas,mcu.yaml44
-rw-r--r--Bindings/mfd/st,stm32-lptimer.yaml5
-rw-r--r--Bindings/mfd/st,stmfx.yaml122
-rw-r--r--Bindings/mfd/st,stpmic1.yaml24
-rw-r--r--Bindings/mfd/syscon.yaml5
-rw-r--r--Bindings/mfd/ti,j721e-system-controller.yaml73
-rw-r--r--[-rwxr-xr-x]Bindings/mfd/tps6507x.txt0
-rw-r--r--Bindings/mfd/twl-family.txt2
-rw-r--r--Bindings/mfd/wlf,arizona.yaml22
-rw-r--r--Bindings/mips/ingenic/devices.yaml17
-rw-r--r--Bindings/mips/ingenic/ingenic,cpu.yaml67
-rw-r--r--Bindings/mips/loongson/devices.yaml20
-rw-r--r--Bindings/misc/fsl,qoriq-mc.txt52
-rw-r--r--Bindings/misc/olpc,xo1.75-ec.yaml52
-rw-r--r--Bindings/mmc/amlogic,meson-mx-sdhc.yaml6
-rw-r--r--Bindings/mmc/arasan,sdhci.yaml303
-rw-r--r--Bindings/mmc/fsl-imx-esdhc.yaml124
-rw-r--r--Bindings/mmc/fsl-imx-mmc.yaml53
-rw-r--r--Bindings/mmc/ingenic,mmc.yaml14
-rw-r--r--Bindings/mmc/mmc-controller.yaml5
-rw-r--r--Bindings/mmc/mmc-pwrseq-emmc.yaml46
-rw-r--r--Bindings/mmc/mmc-pwrseq-sd8787.yaml39
-rw-r--r--Bindings/mmc/mmc-pwrseq-simple.yaml62
-rw-r--r--Bindings/mmc/mtk-sd.txt3
-rw-r--r--Bindings/mmc/mxs-mmc.yaml58
-rw-r--r--Bindings/mmc/nvidia,tegra20-sdhci.txt32
-rw-r--r--Bindings/mmc/renesas,sdhi.yaml191
-rw-r--r--Bindings/mmc/sdhci-am654.txt1
-rw-r--r--Bindings/mmc/sdhci-msm.txt18
-rw-r--r--Bindings/mtd/arasan,nand-controller.yaml8
-rw-r--r--Bindings/mtd/davinci-nand.txt4
-rw-r--r--Bindings/mtd/fsl-upm-nand.txt10
-rw-r--r--Bindings/mtd/gpmi-nand.yaml118
-rw-r--r--Bindings/mtd/mxc-nand.yaml42
-rw-r--r--Bindings/mtd/nand-controller.yaml7
-rw-r--r--Bindings/mtd/st,stm32-fmc2-nand.yaml85
-rw-r--r--Bindings/net/amlogic,meson-dwmac.yaml3
-rw-r--r--Bindings/net/dsa/dsa.txt255
-rw-r--r--Bindings/net/dsa/dsa.yaml92
-rw-r--r--Bindings/net/dsa/ocelot.txt105
-rw-r--r--Bindings/net/ethernet-controller.yaml3
-rw-r--r--Bindings/net/ethernet-phy.yaml12
-rw-r--r--Bindings/net/mdio.yaml7
-rw-r--r--Bindings/net/mscc-phy-vsc8531.txt3
-rw-r--r--Bindings/net/qcom,ipa.yaml12
-rw-r--r--Bindings/net/realtek-bluetooth.yaml2
-rw-r--r--Bindings/net/renesas,ether.yaml22
-rw-r--r--Bindings/net/renesas,ravb.txt1
-rw-r--r--Bindings/net/socionext,uniphier-ave4.yaml12
-rw-r--r--Bindings/net/stm32-dwmac.yaml12
-rw-r--r--Bindings/net/ti,cpsw-switch.yaml62
-rw-r--r--Bindings/net/ti,dp83867.yaml2
-rw-r--r--Bindings/net/ti,dp83869.yaml18
-rw-r--r--Bindings/net/ti,k3-am654-cpsw-nuss.yaml66
-rw-r--r--Bindings/net/wireless/microchip,wilc1000.yaml71
-rw-r--r--Bindings/nvmem/allwinner,sun4i-a10-sid.yaml19
-rw-r--r--Bindings/nvmem/imx-ocotp.yaml24
-rw-r--r--Bindings/nvmem/qcom,qfprom.yaml96
-rw-r--r--Bindings/pci/cdns,cdns-pcie-host.yaml8
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-rw-r--r--src/mips/ingenic/qi_lb60.dts8
-rw-r--r--src/mips/ingenic/rs90.dts315
-rw-r--r--src/mips/ingenic/x1000.dtsi126
-rw-r--r--src/mips/ingenic/x1830.dtsi300
-rw-r--r--src/mips/loongson/loongson64c-package.dtsi64
-rw-r--r--src/mips/loongson/loongson64c_4core_ls7a.dts37
-rw-r--r--src/mips/loongson/loongson64c_4core_rs780e.dts25
-rw-r--r--src/mips/loongson/loongson64c_8core_rs780e.dts25
-rw-r--r--src/mips/loongson/loongson64g-package.dtsi61
-rw-r--r--src/mips/loongson/loongson64g_4core_ls7a.dts41
-rw-r--r--src/mips/loongson/loongson64v_4core_virtio.dts102
-rw-r--r--src/mips/loongson/ls7a-pch.dtsi378
-rw-r--r--src/mips/loongson/rs780e-pch.dtsi4
-rw-r--r--src/mips/mscc/ocelot_pcb120.dts12
-rw-r--r--[-rwxr-xr-x]src/nios2/10m50_devboard.dts0
-rw-r--r--src/powerpc/akebono.dts8
-rw-r--r--src/powerpc/bluestone.dts2
-rw-r--r--src/powerpc/canyonlands.dts4
-rw-r--r--src/powerpc/currituck.dts6
-rw-r--r--src/powerpc/fsl/p4080ds.dts43
-rw-r--r--src/powerpc/glacier.dts4
-rw-r--r--src/powerpc/haleakala.dts2
-rw-r--r--src/powerpc/icon.dts4
-rw-r--r--src/powerpc/katmai.dts6
-rw-r--r--src/powerpc/kilauea.dts4
-rw-r--r--src/powerpc/makalu.dts4
-rw-r--r--src/powerpc/redwood.dts6
-rw-r--r--src/riscv/kendryte/k210.dtsi6
-rw-r--r--[-rwxr-xr-x]src/sh/j2_mimas_v2.dts0
1263 files changed, 61522 insertions, 8893 deletions
diff --git a/Bindings/arm/amazon,al.yaml b/Bindings/arm/amazon,al.yaml
new file mode 100644
index 000000000000..a3a4d710bd02
--- /dev/null
+++ b/Bindings/arm/amazon,al.yaml
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/amazon,al.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Amazon's Annapurna Labs Alpine Platform Device Tree Bindings
+
+maintainers:
+ - Hanna Hawa <hhhawa@amazon.com>
+ - Talel Shenhar <talel@amazon.com>, <talelshenhar@gmail.com>
+ - Ronen Krupnik <ronenk@amazon.com>
+
+properties:
+ compatible:
+ oneOf:
+ - description: Boards with Alpine V1 SoC
+ items:
+ - const: al,alpine
+
+ - description: Boards with Alpine V2 SoC
+ items:
+ - enum:
+ - al,alpine-v2-evp
+ - const: al,alpine-v2
+
+ - description: Boards with Alpine V3 SoC
+ items:
+ - enum:
+ - amazon,al-alpine-v3-evp
+ - const: amazon,al-alpine-v3
+
+...
diff --git a/Bindings/arm/amlogic.yaml b/Bindings/arm/amlogic.yaml
index 378229fa8310..5eba9f48823e 100644
--- a/Bindings/arm/amlogic.yaml
+++ b/Bindings/arm/amlogic.yaml
@@ -121,6 +121,7 @@ properties:
- libretech,aml-s912-pc
- nexbox,a1
- tronsmart,vega-s96
+ - wetek,core2
- const: amlogic,s912
- const: amlogic,meson-gxm
diff --git a/Bindings/arm/arm,integrator.yaml b/Bindings/arm/arm,integrator.yaml
index 192ded470e32..f0daf990e077 100644
--- a/Bindings/arm/arm,integrator.yaml
+++ b/Bindings/arm/arm,integrator.yaml
@@ -67,9 +67,9 @@ patternProperties:
compatible:
items:
- enum:
- - arm,integrator-ap-syscon
- - arm,integrator-cp-syscon
- - arm,integrator-sp-syscon
+ - arm,integrator-ap-syscon
+ - arm,integrator-cp-syscon
+ - arm,integrator-sp-syscon
- const: syscon
reg:
maxItems: 1
diff --git a/Bindings/arm/arm,realview.yaml b/Bindings/arm/arm,realview.yaml
index d6e85d198afe..1d0b4e2bc7d2 100644
--- a/Bindings/arm/arm,realview.yaml
+++ b/Bindings/arm/arm,realview.yaml
@@ -55,20 +55,20 @@ properties:
compatible:
oneOf:
- items:
- - const: arm,realview-eb-soc
- - const: simple-bus
+ - const: arm,realview-eb-soc
+ - const: simple-bus
- items:
- - const: arm,realview-pb1176-soc
- - const: simple-bus
+ - const: arm,realview-pb1176-soc
+ - const: simple-bus
- items:
- - const: arm,realview-pb11mp-soc
- - const: simple-bus
+ - const: arm,realview-pb11mp-soc
+ - const: simple-bus
- items:
- - const: arm,realview-pba8-soc
- - const: simple-bus
+ - const: arm,realview-pba8-soc
+ - const: simple-bus
- items:
- - const: arm,realview-pbx-soc
- - const: simple-bus
+ - const: arm,realview-pbx-soc
+ - const: simple-bus
patternProperties:
"^.*syscon@[0-9a-f]+$":
@@ -79,35 +79,35 @@ properties:
compatible:
oneOf:
- items:
- - const: arm,realview-eb11mp-revb-syscon
- - const: arm,realview-eb-syscon
- - const: syscon
- - const: simple-mfd
+ - const: arm,realview-eb11mp-revb-syscon
+ - const: arm,realview-eb-syscon
+ - const: syscon
+ - const: simple-mfd
- items:
- - const: arm,realview-eb11mp-revc-syscon
- - const: arm,realview-eb-syscon
- - const: syscon
- - const: simple-mfd
+ - const: arm,realview-eb11mp-revc-syscon
+ - const: arm,realview-eb-syscon
+ - const: syscon
+ - const: simple-mfd
- items:
- - const: arm,realview-eb-syscon
- - const: syscon
- - const: simple-mfd
+ - const: arm,realview-eb-syscon
+ - const: syscon
+ - const: simple-mfd
- items:
- - const: arm,realview-pb1176-syscon
- - const: syscon
- - const: simple-mfd
+ - const: arm,realview-pb1176-syscon
+ - const: syscon
+ - const: simple-mfd
- items:
- - const: arm,realview-pb11mp-syscon
- - const: syscon
- - const: simple-mfd
+ - const: arm,realview-pb11mp-syscon
+ - const: syscon
+ - const: simple-mfd
- items:
- - const: arm,realview-pba8-syscon
- - const: syscon
- - const: simple-mfd
+ - const: arm,realview-pba8-syscon
+ - const: syscon
+ - const: simple-mfd
- items:
- - const: arm,realview-pbx-syscon
- - const: syscon
- - const: simple-mfd
+ - const: arm,realview-pbx-syscon
+ - const: syscon
+ - const: simple-mfd
required:
- compatible
diff --git a/Bindings/arm/arm,scmi.txt b/Bindings/arm/arm,scmi.txt
index 1f293ea24cd8..55deb68230eb 100644
--- a/Bindings/arm/arm,scmi.txt
+++ b/Bindings/arm/arm,scmi.txt
@@ -102,7 +102,7 @@ Required sub-node properties:
[0] http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/index.html
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/power/power-domain.yaml
-[3] Documentation/devicetree/bindings/thermal/thermal.txt
+[3] Documentation/devicetree/bindings/thermal/thermal*.yaml
[4] Documentation/devicetree/bindings/sram/sram.yaml
[5] Documentation/devicetree/bindings/reset/reset.txt
diff --git a/Bindings/arm/arm,scpi.txt b/Bindings/arm/arm,scpi.txt
index dd04d9d9a1b8..bcd6c3ec471e 100644
--- a/Bindings/arm/arm,scpi.txt
+++ b/Bindings/arm/arm,scpi.txt
@@ -108,7 +108,7 @@ Required properties:
[0] http://infocenter.arm.com/help/topic/com.arm.doc.dui0922b/index.html
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-[2] Documentation/devicetree/bindings/thermal/thermal.txt
+[2] Documentation/devicetree/bindings/thermal/thermal*.yaml
[3] Documentation/devicetree/bindings/sram/sram.yaml
[4] Documentation/devicetree/bindings/power/power-domain.yaml
diff --git a/Bindings/arm/arm,vexpress-juno.yaml b/Bindings/arm/arm,vexpress-juno.yaml
index a3420c81cf35..26829a803fda 100644
--- a/Bindings/arm/arm,vexpress-juno.yaml
+++ b/Bindings/arm/arm,vexpress-juno.yaml
@@ -165,10 +165,10 @@ patternProperties:
compatible:
oneOf:
- items:
- - enum:
- - arm,vexpress,v2m-p1
- - arm,vexpress,v2p-p1
- - const: simple-bus
+ - enum:
+ - arm,vexpress,v2m-p1
+ - arm,vexpress,v2p-p1
+ - const: simple-bus
- const: simple-bus
motherboard:
type: object
@@ -186,8 +186,8 @@ patternProperties:
compatible:
items:
- enum:
- - arm,vexpress,v2m-p1
- - arm,vexpress,v2p-p1
+ - arm,vexpress,v2m-p1
+ - arm,vexpress,v2p-p1
- const: simple-bus
arm,v2m-memory-map:
description: This describes the memory map type.
diff --git a/Bindings/arm/bcm/brcm,bcm11351.yaml b/Bindings/arm/bcm/brcm,bcm11351.yaml
index b5ef2666e6b2..497600a2ffb9 100644
--- a/Bindings/arm/bcm/brcm,bcm11351.yaml
+++ b/Bindings/arm/bcm/brcm,bcm11351.yaml
@@ -15,7 +15,7 @@ properties:
compatible:
items:
- enum:
- - brcm,bcm28155-ap
+ - brcm,bcm28155-ap
- const: brcm,bcm11351
...
diff --git a/Bindings/arm/bcm/brcm,bcm21664.yaml b/Bindings/arm/bcm/brcm,bcm21664.yaml
index aafbd6a27708..e0ee931723dc 100644
--- a/Bindings/arm/bcm/brcm,bcm21664.yaml
+++ b/Bindings/arm/bcm/brcm,bcm21664.yaml
@@ -15,7 +15,7 @@ properties:
compatible:
items:
- enum:
- - brcm,bcm21664-garnet
+ - brcm,bcm21664-garnet
- const: brcm,bcm21664
...
diff --git a/Bindings/arm/bcm/brcm,bcm23550.yaml b/Bindings/arm/bcm/brcm,bcm23550.yaml
index c4b4efd28a55..40d12ea56e54 100644
--- a/Bindings/arm/bcm/brcm,bcm23550.yaml
+++ b/Bindings/arm/bcm/brcm,bcm23550.yaml
@@ -15,7 +15,7 @@ properties:
compatible:
items:
- enum:
- - brcm,bcm23550-sparrow
+ - brcm,bcm23550-sparrow
- const: brcm,bcm23550
...
diff --git a/Bindings/arm/bcm/brcm,cygnus.yaml b/Bindings/arm/bcm/brcm,cygnus.yaml
index fe111e72dac3..9ba7b16e1fc4 100644
--- a/Bindings/arm/bcm/brcm,cygnus.yaml
+++ b/Bindings/arm/bcm/brcm,cygnus.yaml
@@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom Cygnus device tree bindings
maintainers:
- - Ray Jui <rjui@broadcom.com>
- - Scott Branden <sbranden@broadcom.com>
+ - Ray Jui <rjui@broadcom.com>
+ - Scott Branden <sbranden@broadcom.com>
properties:
$nodename:
@@ -16,14 +16,14 @@ properties:
compatible:
items:
- enum:
- - brcm,bcm11300
- - brcm,bcm11320
- - brcm,bcm11350
- - brcm,bcm11360
- - brcm,bcm58300
- - brcm,bcm58302
- - brcm,bcm58303
- - brcm,bcm58305
+ - brcm,bcm11300
+ - brcm,bcm11320
+ - brcm,bcm11350
+ - brcm,bcm11360
+ - brcm,bcm58300
+ - brcm,bcm58302
+ - brcm,bcm58303
+ - brcm,bcm58305
- const: brcm,cygnus
...
diff --git a/Bindings/arm/bcm/brcm,hr2.yaml b/Bindings/arm/bcm/brcm,hr2.yaml
index 1158f49b0b83..ae614b6722c2 100644
--- a/Bindings/arm/bcm/brcm,hr2.yaml
+++ b/Bindings/arm/bcm/brcm,hr2.yaml
@@ -21,7 +21,7 @@ properties:
compatible:
items:
- enum:
- - ubnt,unifi-switch8
+ - ubnt,unifi-switch8
- const: brcm,bcm53342
- const: brcm,hr2
diff --git a/Bindings/arm/bcm/brcm,ns2.yaml b/Bindings/arm/bcm/brcm,ns2.yaml
index 2451704f87f0..0749adf94c28 100644
--- a/Bindings/arm/bcm/brcm,ns2.yaml
+++ b/Bindings/arm/bcm/brcm,ns2.yaml
@@ -16,8 +16,8 @@ properties:
compatible:
items:
- enum:
- - brcm,ns2-svk
- - brcm,ns2-xmc
+ - brcm,ns2-svk
+ - brcm,ns2-xmc
- const: brcm,ns2
...
diff --git a/Bindings/arm/bcm/brcm,nsp.yaml b/Bindings/arm/bcm/brcm,nsp.yaml
index fe364cebf57f..8c2cacb2bb4f 100644
--- a/Bindings/arm/bcm/brcm,nsp.yaml
+++ b/Bindings/arm/bcm/brcm,nsp.yaml
@@ -24,13 +24,13 @@ properties:
compatible:
items:
- enum:
- - brcm,bcm58522
- - brcm,bcm58525
- - brcm,bcm58535
- - brcm,bcm58622
- - brcm,bcm58623
- - brcm,bcm58625
- - brcm,bcm88312
+ - brcm,bcm58522
+ - brcm,bcm58525
+ - brcm,bcm58535
+ - brcm,bcm58622
+ - brcm,bcm58623
+ - brcm,bcm58625
+ - brcm,bcm88312
- const: brcm,nsp
...
diff --git a/Bindings/arm/bcm/brcm,stingray.yaml b/Bindings/arm/bcm/brcm,stingray.yaml
index 4ad2b2124ab4..c13cb96545a2 100644
--- a/Bindings/arm/bcm/brcm,stingray.yaml
+++ b/Bindings/arm/bcm/brcm,stingray.yaml
@@ -16,9 +16,9 @@ properties:
compatible:
items:
- enum:
- - brcm,bcm958742k
- - brcm,bcm958742t
- - brcm,bcm958802a802x
+ - brcm,bcm958742k
+ - brcm,bcm958742t
+ - brcm,bcm958802a802x
- const: brcm,stingray
...
diff --git a/Bindings/arm/bcm/brcm,vulcan-soc.yaml b/Bindings/arm/bcm/brcm,vulcan-soc.yaml
index c5b6f31c20b9..ccdf9f99cb2b 100644
--- a/Bindings/arm/bcm/brcm,vulcan-soc.yaml
+++ b/Bindings/arm/bcm/brcm,vulcan-soc.yaml
@@ -15,8 +15,8 @@ properties:
compatible:
items:
- enum:
- - brcm,vulcan-eval
- - cavium,thunderx2-cn9900
+ - brcm,vulcan-eval
+ - cavium,thunderx2-cn9900
- const: brcm,vulcan-soc
...
diff --git a/Bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml b/Bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml
new file mode 100644
index 000000000000..6834f5e8df5f
--- /dev/null
+++ b/Bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/bcm/raspberrypi,bcm2835-firmware.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Raspberry Pi VideoCore firmware driver
+
+maintainers:
+ - Eric Anholt <eric@anholt.net>
+ - Stefan Wahren <wahrenst@gmx.net>
+
+select:
+ properties:
+ compatible:
+ contains:
+ const: raspberrypi,bcm2835-firmware
+
+ required:
+ - compatible
+
+properties:
+ compatible:
+ items:
+ - const: raspberrypi,bcm2835-firmware
+ - const: simple-mfd
+
+ mboxes:
+ $ref: '/schemas/types.yaml#/definitions/phandle'
+ description: |
+ Phandle to the firmware device's Mailbox.
+ (See: ../mailbox/mailbox.txt for more information)
+
+ clocks:
+ type: object
+
+ properties:
+ compatible:
+ const: raspberrypi,firmware-clocks
+
+ "#clock-cells":
+ const: 1
+ description: >
+ The argument is the ID of the clocks contained by the
+ firmware messages.
+
+ required:
+ - compatible
+ - "#clock-cells"
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - mboxes
+
+examples:
+ - |
+ firmware {
+ compatible = "raspberrypi,bcm2835-firmware", "simple-mfd";
+ mboxes = <&mailbox>;
+
+ firmware_clocks: clocks {
+ compatible = "raspberrypi,firmware-clocks";
+ #clock-cells = <1>;
+ };
+ };
+...
diff --git a/Bindings/arm/coresight-cti.yaml b/Bindings/arm/coresight-cti.yaml
index 17df5cd12d8d..e42ff69d8bfb 100644
--- a/Bindings/arm/coresight-cti.yaml
+++ b/Bindings/arm/coresight-cti.yaml
@@ -82,12 +82,12 @@ properties:
compatible:
oneOf:
- items:
- - const: arm,coresight-cti
- - const: arm,primecell
+ - const: arm,coresight-cti
+ - const: arm,primecell
- items:
- - const: arm,coresight-cti-v8-arch
- - const: arm,coresight-cti
- - const: arm,primecell
+ - const: arm,coresight-cti-v8-arch
+ - const: arm,coresight-cti
+ - const: arm,primecell
reg:
maxItems: 1
@@ -191,16 +191,16 @@ patternProperties:
anyOf:
- required:
- - arm,trig-in-sigs
+ - arm,trig-in-sigs
- required:
- - arm,trig-out-sigs
+ - arm,trig-out-sigs
oneOf:
- required:
- - arm,trig-conn-name
+ - arm,trig-conn-name
- required:
- - cpu
+ - cpu
- required:
- - arm,cs-dev-assoc
+ - arm,cs-dev-assoc
required:
- reg
diff --git a/Bindings/arm/coresight.txt b/Bindings/arm/coresight.txt
index 846f6daae71b..d711676b4a51 100644
--- a/Bindings/arm/coresight.txt
+++ b/Bindings/arm/coresight.txt
@@ -108,6 +108,13 @@ its hardware characteristcs.
* arm,cp14: must be present if the system accesses ETM/PTM management
registers via co-processor 14.
+ * qcom,skip-power-up: boolean. Indicates that an implementation can
+ skip powering up the trace unit. TRCPDCR.PU does not have to be set
+ on Qualcomm Technologies Inc. systems since ETMs are in the same power
+ domain as their CPU cores. This property is required to identify such
+ systems with hardware errata where the CPU watchdog counter is stopped
+ when TRCPDCR.PU is set.
+
* Optional property for TMC:
* arm,buffer-size: size of contiguous buffer space for TMC ETR
@@ -121,6 +128,12 @@ its hardware characteristcs.
* interrupts : Exactly one SPI may be listed for reporting the address
error
+* Optional property for configurable replicators:
+
+ * qcom,replicator-loses-context: boolean. Indicates that the replicator
+ will lose register context when AMBA clock is removed which is observed
+ in some replicator designs.
+
Graph bindings for Coresight
-------------------------------
diff --git a/Bindings/arm/cpus.yaml b/Bindings/arm/cpus.yaml
index 40f692c846f0..1222bf1831fa 100644
--- a/Bindings/arm/cpus.yaml
+++ b/Bindings/arm/cpus.yaml
@@ -330,8 +330,8 @@ if:
- enable-method
then:
- required:
- - secondary-boot-reg
+ required:
+ - secondary-boot-reg
required:
- device_type
diff --git a/Bindings/arm/freescale/fsl,scu.txt b/Bindings/arm/freescale/fsl,scu.txt
index 10b8459e49f8..6064d98b1031 100644
--- a/Bindings/arm/freescale/fsl,scu.txt
+++ b/Bindings/arm/freescale/fsl,scu.txt
@@ -176,7 +176,7 @@ Required properties:
"fsl,imx8qxp-sc-thermal"
followed by "fsl,imx-sc-thermal";
-- #thermal-sensor-cells: See Documentation/devicetree/bindings/thermal/thermal.txt
+- #thermal-sensor-cells: See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml
for a description.
Example (imx8qxp):
diff --git a/Bindings/arm/fsl.yaml b/Bindings/arm/fsl.yaml
index 05906e291e38..6da9d734cdb7 100644
--- a/Bindings/arm/fsl.yaml
+++ b/Bindings/arm/fsl.yaml
@@ -120,6 +120,8 @@ properties:
- fsl,imx6q-sabrelite
- fsl,imx6q-sabresd
- kontron,imx6q-samx6i # Kontron i.MX6 Dual/Quad SMARC Module
+ - prt,prti6q # Protonic PRTI6Q board
+ - prt,prtwd2 # Protonic WD2 board
- technexion,imx6q-pico-dwarf # TechNexion i.MX6Q Pico-Dwarf
- technexion,imx6q-pico-hobbit # TechNexion i.MX6Q Pico-Hobbit
- technexion,imx6q-pico-nymph # TechNexion i.MX6Q Pico-Nymph
@@ -172,6 +174,8 @@ properties:
- fsl,imx6dl-sabreauto # i.MX6 DualLite/Solo SABRE Automotive Board
- fsl,imx6dl-sabresd # i.MX6 DualLite SABRE Smart Device Board
- kontron,imx6dl-samx6i # Kontron i.MX6 Solo SMARC Module
+ - prt,prtrvt # Protonic RVT board
+ - prt,prtvt7 # Protonic VT7 board
- technexion,imx6dl-pico-dwarf # TechNexion i.MX6DL Pico-Dwarf
- technexion,imx6dl-pico-hobbit # TechNexion i.MX6DL Pico-Hobbit
- technexion,imx6dl-pico-nymph # TechNexion i.MX6DL Pico-Nymph
@@ -268,8 +272,9 @@ properties:
- armadeus,imx6ull-opos6uldev # OPOS6UL (i.MX6ULL) SoM on OPOS6ULDev board
- fsl,imx6ull-14x14-evk # i.MX6 UltraLiteLite 14x14 EVK Board
- kontron,imx6ull-n6411-som # Kontron N6411 SOM
- - toradex,colibri-imx6ull-eval # Colibri iMX6ULL Module on Colibri Evaluation Board
- - toradex,colibri-imx6ull-wifi-eval # Colibri iMX6ULL Wi-Fi / Bluetooth Module on Colibri Evaluation Board
+ - myir,imx6ull-mys-6ulx-eval # MYiR Tech iMX6ULL Evaluation Board
+ - toradex,colibri-imx6ull-eval # Colibri iMX6ULL Module on Colibri Eval Board
+ - toradex,colibri-imx6ull-wifi-eval # Colibri iMX6ULL Wi-Fi / BT Module on Colibri Eval Board
- const: fsl,imx6ull
- description: Kontron N6411 S Board
@@ -307,9 +312,12 @@ properties:
- toradex,colibri-imx7d # Colibri iMX7 Dual Module
- toradex,colibri-imx7d-aster # Colibri iMX7 Dual Module on Aster Carrier Board
- toradex,colibri-imx7d-emmc # Colibri iMX7 Dual 1GB (eMMC) Module
- - toradex,colibri-imx7d-emmc-aster # Colibri iMX7 Dual 1GB (eMMC) Module on Aster Carrier Board
- - toradex,colibri-imx7d-emmc-eval-v3 # Colibri iMX7 Dual 1GB (eMMC) Module on Colibri Evaluation Board V3
- - toradex,colibri-imx7d-eval-v3 # Colibri iMX7 Dual Module on Colibri Evaluation Board V3
+ - toradex,colibri-imx7d-emmc-aster # Colibri iMX7 Dual 1GB (eMMC) Module on
+ # Aster Carrier Board
+ - toradex,colibri-imx7d-emmc-eval-v3 # Colibri iMX7 Dual 1GB (eMMC) Module on
+ # Colibri Evaluation Board V3
+ - toradex,colibri-imx7d-eval-v3 # Colibri iMX7 Dual Module on
+ # Colibri Evaluation Board V3
- tq,imx7d-mba7 # i.MX7D TQ MBa7 with TQMa7D SoM
- zii,imx7d-rmu2 # ZII RMU2 Board
- zii,imx7d-rpu2 # ZII RPU2 Board
diff --git a/Bindings/arm/intel,keembay.yaml b/Bindings/arm/intel,keembay.yaml
new file mode 100644
index 000000000000..06a7b05f435f
--- /dev/null
+++ b/Bindings/arm/intel,keembay.yaml
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/intel,keembay.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Keem Bay platform device tree bindings
+
+maintainers:
+ - Paul J. Murphy <paul.j.murphy@intel.com>
+ - Daniele Alessandrelli <daniele.alessandrelli@intel.com>
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - intel,keembay-evm
+ - const: intel,keembay
+...
diff --git a/Bindings/arm/keystone/ti,k3-sci-common.yaml b/Bindings/arm/keystone/ti,k3-sci-common.yaml
new file mode 100644
index 000000000000..7597bc93a55f
--- /dev/null
+++ b/Bindings/arm/keystone/ti,k3-sci-common.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/keystone/ti,k3-sci-common.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Common K3 TI-SCI bindings
+
+maintainers:
+ - Nishanth Menon <nm@ti.com>
+
+description: |
+ The TI K3 family of SoCs usually have a central System Controller Processor
+ that is responsible for managing various SoC-level resources like clocks,
+ resets, interrupts etc. The communication with that processor is performed
+ through the TI-SCI protocol.
+
+ Each specific device management node like a clock controller node, a reset
+ controller node or an interrupt-controller node should define a common set
+ of properties that enables them to implement the corresponding functionality
+ over the TI-SCI protocol. The following are some of the common properties
+ needed by such individual nodes. The required properties for each device
+ management node is defined in the respective binding.
+
+properties:
+ ti,sci:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Should be a phandle to the TI-SCI System Controller node
+
+ ti,sci-dev-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Should contain the TI-SCI device id corresponding to the device. Please
+ refer to the corresponding System Controller documentation for valid
+ values for the desired device.
+
+ ti,sci-proc-ids:
+ description: Should contain a single tuple of <proc_id host_id>.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ items:
+ - description: TI-SCI processor id for the remote processor device
+ - description: TI-SCI host id to which processor control ownership
+ should be transferred to
diff --git a/Bindings/arm/marvell/ap80x-system-controller.txt b/Bindings/arm/marvell/ap80x-system-controller.txt
index 098d932fc963..e31511255d8e 100644
--- a/Bindings/arm/marvell/ap80x-system-controller.txt
+++ b/Bindings/arm/marvell/ap80x-system-controller.txt
@@ -111,7 +111,7 @@ Thermal:
--------
For common binding part and usage, refer to
-Documentation/devicetree/bindings/thermal/thermal.txt
+Documentation/devicetree/bindings/thermal/thermal*.yaml
The thermal IP can probe the temperature all around the processor. It
may feature several channels, each of them wired to one sensor.
diff --git a/Bindings/arm/marvell/cp110-system-controller.txt b/Bindings/arm/marvell/cp110-system-controller.txt
index f982a8ed9396..a21f7709596c 100644
--- a/Bindings/arm/marvell/cp110-system-controller.txt
+++ b/Bindings/arm/marvell/cp110-system-controller.txt
@@ -203,7 +203,7 @@ It is possible to setup an overheat interrupt by giving at least one
critical point to any subnode of the thermal-zone node.
For common binding part and usage, refer to
-Documentation/devicetree/bindings/thermal/thermal.txt
+Documentation/devicetree/bindings/thermal/thermal*.yaml
Required properties:
- compatible: must be one of:
diff --git a/Bindings/arm/mediatek.yaml b/Bindings/arm/mediatek.yaml
index abc544dde692..30908963ae26 100644
--- a/Bindings/arm/mediatek.yaml
+++ b/Bindings/arm/mediatek.yaml
@@ -114,4 +114,9 @@ properties:
- enum:
- mediatek,mt8183-evb
- const: mediatek,mt8183
+ - description: Google Krane (Lenovo IdeaPad Duet, 10e,...)
+ items:
+ - const: google,krane-sku176
+ - const: google,krane
+ - const: mediatek,mt8183
...
diff --git a/Bindings/arm/mediatek/mediatek,pericfg.yaml b/Bindings/arm/mediatek/mediatek,pericfg.yaml
index e271c4682ebc..1af30174b2d0 100644
--- a/Bindings/arm/mediatek/mediatek,pericfg.yaml
+++ b/Bindings/arm/mediatek/mediatek,pericfg.yaml
@@ -17,22 +17,22 @@ properties:
compatible:
oneOf:
- items:
- - enum:
- - mediatek,mt2701-pericfg
- - mediatek,mt2712-pericfg
- - mediatek,mt6765-pericfg
- - mediatek,mt7622-pericfg
- - mediatek,mt7629-pericfg
- - mediatek,mt8135-pericfg
- - mediatek,mt8173-pericfg
- - mediatek,mt8183-pericfg
- - mediatek,mt8516-pericfg
- - const: syscon
+ - enum:
+ - mediatek,mt2701-pericfg
+ - mediatek,mt2712-pericfg
+ - mediatek,mt6765-pericfg
+ - mediatek,mt7622-pericfg
+ - mediatek,mt7629-pericfg
+ - mediatek,mt8135-pericfg
+ - mediatek,mt8173-pericfg
+ - mediatek,mt8183-pericfg
+ - mediatek,mt8516-pericfg
+ - const: syscon
- items:
- # Special case for mt7623 for backward compatibility
- - const: mediatek,mt7623-pericfg
- - const: mediatek,mt2701-pericfg
- - const: syscon
+ # Special case for mt7623 for backward compatibility
+ - const: mediatek,mt7623-pericfg
+ - const: mediatek,mt2701-pericfg
+ - const: syscon
reg:
maxItems: 1
diff --git a/Bindings/arm/microchip,sparx5.yaml b/Bindings/arm/microchip,sparx5.yaml
new file mode 100644
index 000000000000..ecf6fa12e6ad
--- /dev/null
+++ b/Bindings/arm/microchip,sparx5.yaml
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/microchip,sparx5.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip Sparx5 Boards Device Tree Bindings
+
+maintainers:
+ - Lars Povlsen <lars.povlsen@microchip.com>
+
+description: |+
+ The Microchip Sparx5 SoC is a ARMv8-based used in a family of
+ gigabit TSN-capable gigabit switches.
+
+ The SparX-5 Ethernet switch family provides a rich set of switching
+ features such as advanced TCAM-based VLAN and QoS processing
+ enabling delivery of differentiated services, and security through
+ TCAM-based frame processing using versatile content aware processor
+ (VCAP)
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+ - description: The Sparx5 pcb125 board is a modular board,
+ which has both spi-nor and eMMC storage. The modular design
+ allows for connection of different network ports.
+ items:
+ - const: microchip,sparx5-pcb125
+ - const: microchip,sparx5
+
+ - description: The Sparx5 pcb134 is a pizzabox form factor
+ gigabit switch with 20 SFP ports. It features spi-nor and
+ either spi-nand or eMMC storage (mount option).
+ items:
+ - const: microchip,sparx5-pcb134
+ - const: microchip,sparx5
+
+ - description: The Sparx5 pcb135 is a pizzabox form factor
+ gigabit switch with 48+4 Cu ports. It features spi-nor and
+ either spi-nand or eMMC storage (mount option).
+ items:
+ - const: microchip,sparx5-pcb135
+ - const: microchip,sparx5
+
+ axi@600000000:
+ type: object
+ description: the root node in the Sparx5 platforms must contain
+ an axi bus child node. They are always at physical address
+ 0x600000000 in all the Sparx5 variants.
+ properties:
+ compatible:
+ items:
+ - const: simple-bus
+
+ required:
+ - compatible
+
+required:
+ - compatible
+ - axi@600000000
+
+...
diff --git a/Bindings/arm/mstar/mstar,l3bridge.yaml b/Bindings/arm/mstar/mstar,l3bridge.yaml
new file mode 100644
index 000000000000..6816bd68f9cf
--- /dev/null
+++ b/Bindings/arm/mstar/mstar,l3bridge.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2020 thingy.jp.
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/arm/mstar/mstar,l3bridge.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: MStar/SigmaStar Armv7 SoC l3bridge
+
+maintainers:
+ - Daniel Palmer <daniel@thingy.jp>
+
+description: |
+ MStar/SigmaStar's Armv7 SoCs have a pipeline in the interface
+ between the CPU and memory. This means that before DMA capable
+ devices are allowed to run the pipeline must be flushed to ensure
+ everything is in memory.
+
+ The l3bridge region contains registers that allow such a flush
+ to be triggered.
+
+ This node is used by the platform code to find where the registers
+ are and install a barrier that triggers the required pipeline flush.
+
+properties:
+ compatible:
+ items:
+ - const: mstar,l3bridge
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ l3bridge: l3bridge@1f204400 {
+ compatible = "mstar,l3bridge";
+ reg = <0x1f204400 0x200>;
+ };
diff --git a/Bindings/arm/mstar/mstar.yaml b/Bindings/arm/mstar/mstar.yaml
new file mode 100644
index 000000000000..c2f980b00b06
--- /dev/null
+++ b/Bindings/arm/mstar/mstar.yaml
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/mstar/mstar.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MStar platforms device tree bindings
+
+maintainers:
+ - Daniel Palmer <daniel@thingy.jp>
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+ - description: infinity boards
+ items:
+ - enum:
+ - thingyjp,breadbee-crust # thingy.jp BreadBee Crust
+ - const: mstar,infinity
+
+ - description: infinity3 boards
+ items:
+ - enum:
+ - thingyjp,breadbee # thingy.jp BreadBee
+ - const: mstar,infinity3
+
+ - description: mercury5 boards
+ items:
+ - enum:
+ - 70mai,midrived08 # 70mai midrive d08
+ - const: mstar,mercury5
diff --git a/Bindings/arm/nvidia,tegra194-ccplex.yaml b/Bindings/arm/nvidia,tegra194-ccplex.yaml
new file mode 100644
index 000000000000..1043e4be4fca
--- /dev/null
+++ b/Bindings/arm/nvidia,tegra194-ccplex.yaml
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/arm/nvidia,tegra194-ccplex.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: NVIDIA Tegra194 CPU Complex device tree bindings
+
+maintainers:
+ - Thierry Reding <thierry.reding@gmail.com>
+ - Jonathan Hunter <jonathanh@nvidia.com>
+ - Sumit Gupta <sumitg@nvidia.com>
+
+description: |+
+ Tegra194 SOC has homogeneous architecture where each cluster has two
+ symmetric cores. Compatible string in "cpus" node represents the CPU
+ Complex having all clusters.
+
+properties:
+ $nodename:
+ const: cpus
+
+ compatible:
+ enum:
+ - nvidia,tegra194-ccplex
+
+ nvidia,bpmp:
+ $ref: '/schemas/types.yaml#/definitions/phandle'
+ description: |
+ Specifies the bpmp node that needs to be queried to get
+ operating point data for all CPUs.
+
+examples:
+ - |
+ cpus {
+ compatible = "nvidia,tegra194-ccplex";
+ nvidia,bpmp = <&bpmp>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0_0: cpu@0 {
+ compatible = "nvidia,tegra194-carmel";
+ device_type = "cpu";
+ reg = <0x0>;
+ enable-method = "psci";
+ };
+
+ cpu0_1: cpu@1 {
+ compatible = "nvidia,tegra194-carmel";
+ device_type = "cpu";
+ reg = <0x001>;
+ enable-method = "psci";
+ };
+
+ cpu1_0: cpu@100 {
+ compatible = "nvidia,tegra194-carmel";
+ device_type = "cpu";
+ reg = <0x100>;
+ enable-method = "psci";
+ };
+
+ cpu1_1: cpu@101 {
+ compatible = "nvidia,tegra194-carmel";
+ device_type = "cpu";
+ reg = <0x101>;
+ enable-method = "psci";
+ };
+ };
+...
diff --git a/Bindings/arm/renesas.yaml b/Bindings/arm/renesas.yaml
index b7d2e921150a..0d4dabb4a164 100644
--- a/Bindings/arm/renesas.yaml
+++ b/Bindings/arm/renesas.yaml
@@ -118,6 +118,7 @@ properties:
items:
- enum:
- hoperun,hihope-rzg2m # HopeRun HiHope RZ/G2M platform
+ - beacon,beacon-rzg2m # Beacon EmbeddedWorks RZ/G2M Kit
- const: renesas,r8a774a1
- items:
@@ -150,6 +151,18 @@ properties:
- const: si-linux,cat874
- const: renesas,r8a774c0
+ - description: RZ/G2H (R8A774E1)
+ items:
+ - enum:
+ - hoperun,hihope-rzg2h # HopeRun HiHope RZ/G2H platform
+ - const: renesas,r8a774e1
+
+ - items:
+ - enum:
+ - hoperun,hihope-rzg2-ex # HopeRun expansion board for HiHope RZ/G2 platforms
+ - const: hoperun,hihope-rzg2h
+ - const: renesas,r8a774e1
+
- description: R-Car M1A (R8A77781)
items:
- enum:
diff --git a/Bindings/arm/rockchip.yaml b/Bindings/arm/rockchip.yaml
index d4a4045092df..db2e35796795 100644
--- a/Bindings/arm/rockchip.yaml
+++ b/Bindings/arm/rockchip.yaml
@@ -435,6 +435,12 @@ properties:
- const: radxa,rockpi4
- const: rockchip,rk3399
+ - description: Radxa ROCK Pi N8
+ items:
+ - const: radxa,rockpi-n8
+ - const: vamrs,rk3288-vmarc-som
+ - const: rockchip,rk3288
+
- description: Radxa ROCK Pi N10
items:
- const: radxa,rockpi-n10
diff --git a/Bindings/arm/stm32/st,stm32-syscon.yaml b/Bindings/arm/stm32/st,stm32-syscon.yaml
index cf5db5e273f3..6f1cd0103c74 100644
--- a/Bindings/arm/stm32/st,stm32-syscon.yaml
+++ b/Bindings/arm/stm32/st,stm32-syscon.yaml
@@ -16,6 +16,9 @@ properties:
- items:
- enum:
- st,stm32mp157-syscfg
+ - st,stm32mp151-pwr-mcu
+ - st,stm32-syscfg
+ - st,stm32-power-config
- const: syscon
reg:
@@ -27,7 +30,16 @@ properties:
required:
- compatible
- reg
- - clocks
+
+if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - st,stm32mp157-syscfg
+then:
+ required:
+ - clocks
additionalProperties: false
diff --git a/Bindings/arm/sunxi.yaml b/Bindings/arm/sunxi.yaml
index 87817ff0cd35..efc9118233b4 100644
--- a/Bindings/arm/sunxi.yaml
+++ b/Bindings/arm/sunxi.yaml
@@ -657,6 +657,11 @@ properties:
- const: pine64,pinephone-1.1
- const: allwinner,sun50i-a64
+ - description: Pine64 PinePhone (1.2)
+ items:
+ - const: pine64,pinephone-1.2
+ - const: allwinner,sun50i-a64
+
- description: Pine64 PineTab
items:
- const: pine64,pinetab
diff --git a/Bindings/arm/tegra.yaml b/Bindings/arm/tegra.yaml
index 60b38eb5c61a..e0b3debaee9e 100644
--- a/Bindings/arm/tegra.yaml
+++ b/Bindings/arm/tegra.yaml
@@ -35,6 +35,9 @@ properties:
- const: toradex,colibri_t20
- const: nvidia,tegra20
- items:
+ - const: acer,picasso
+ - const: nvidia,tegra20
+ - items:
- enum:
- nvidia,beaver
- const: nvidia,tegra30
@@ -60,6 +63,13 @@ properties:
- const: toradex,colibri_t30
- const: nvidia,tegra30
- items:
+ - const: asus,grouper
+ - const: nvidia,tegra30
+ - items:
+ - const: asus,tilapia
+ - const: asus,grouper
+ - const: nvidia,tegra30
+ - items:
- enum:
- nvidia,dalmore
- nvidia,roth
@@ -101,3 +111,11 @@ properties:
- enum:
- nvidia,p2972-0000
- const: nvidia,tegra194
+ - description: Jetson Xavier NX
+ items:
+ - const: nvidia,p3668-0000
+ - const: nvidia,tegra194
+ - description: Jetson Xavier NX Developer Kit
+ items:
+ - const: nvidia,p3509-0000+p3668-0000
+ - const: nvidia,tegra194
diff --git a/Bindings/bus/baikal,bt1-apb.yaml b/Bindings/bus/baikal,bt1-apb.yaml
index 68b0131a31d0..37ba3337f944 100644
--- a/Bindings/bus/baikal,bt1-apb.yaml
+++ b/Bindings/bus/baikal,bt1-apb.yaml
@@ -19,7 +19,7 @@ description: |
reported to the APB terminator (APB Errors Handler Block).
allOf:
- - $ref: /schemas/simple-bus.yaml#
+ - $ref: /schemas/simple-bus.yaml#
properties:
compatible:
diff --git a/Bindings/bus/baikal,bt1-axi.yaml b/Bindings/bus/baikal,bt1-axi.yaml
index 29e1aaea132b..0bee4694578a 100644
--- a/Bindings/bus/baikal,bt1-axi.yaml
+++ b/Bindings/bus/baikal,bt1-axi.yaml
@@ -23,7 +23,7 @@ description: |
accessible by means of the Baikal-T1 System Controller.
allOf:
- - $ref: /schemas/simple-bus.yaml#
+ - $ref: /schemas/simple-bus.yaml#
properties:
compatible:
diff --git a/Bindings/bus/mti,mips-cdmm.yaml b/Bindings/bus/mti,mips-cdmm.yaml
new file mode 100644
index 000000000000..9cc2d5f1beef
--- /dev/null
+++ b/Bindings/bus/mti,mips-cdmm.yaml
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bus/mti,mips-cdmm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MIPS Common Device Memory Map
+
+description: |
+ Defines a location of the MIPS Common Device Memory Map registers.
+
+maintainers:
+ - James Hogan <jhogan@kernel.org>
+
+properties:
+ compatible:
+ const: mti,mips-cdmm
+
+ reg:
+ description: |
+ Base address and size of an unoccupied memory region, which will be
+ used to map the MIPS CDMM registers block.
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ cdmm@1bde8000 {
+ compatible = "mti,mips-cdmm";
+ reg = <0x1bde8000 0x8000>;
+ };
+...
diff --git a/Bindings/clock/brcm,bcm2711-dvp.yaml b/Bindings/clock/brcm,bcm2711-dvp.yaml
new file mode 100644
index 000000000000..08543ecbe35b
--- /dev/null
+++ b/Bindings/clock/brcm,bcm2711-dvp.yaml
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/brcm,bcm2711-dvp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom BCM2711 HDMI DVP Device Tree Bindings
+
+maintainers:
+ - Maxime Ripard <mripard@kernel.org>
+
+properties:
+ "#clock-cells":
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
+ compatible:
+ const: brcm,brcm2711-dvp
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+required:
+ - "#clock-cells"
+ - "#reset-cells"
+ - compatible
+ - reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ dvp: clock@7ef00000 {
+ compatible = "brcm,brcm2711-dvp";
+ reg = <0x7ef00000 0x10>;
+ clocks = <&clk_108MHz>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+...
diff --git a/Bindings/clock/brcm,bcm63xx-clocks.txt b/Bindings/clock/brcm,bcm63xx-clocks.txt
index 3041657e2f96..3e7ca5530775 100644
--- a/Bindings/clock/brcm,bcm63xx-clocks.txt
+++ b/Bindings/clock/brcm,bcm63xx-clocks.txt
@@ -3,6 +3,8 @@ Gated Clock Controller Bindings for MIPS based BCM63XX SoCs
Required properties:
- compatible: must be one of:
"brcm,bcm3368-clocks"
+ "brcm,bcm6318-clocks"
+ "brcm,bcm6318-ubus-clocks"
"brcm,bcm6328-clocks"
"brcm,bcm6358-clocks"
"brcm,bcm6362-clocks"
diff --git a/Bindings/clock/clock-bindings.txt b/Bindings/clock/clock-bindings.txt
index 8a55fdcf96ee..f2ea53832ac6 100644
--- a/Bindings/clock/clock-bindings.txt
+++ b/Bindings/clock/clock-bindings.txt
@@ -9,7 +9,7 @@ specifier is an array of zero, one or more cells identifying the clock
output on a device. The length of a clock specifier is defined by the
value of a #clock-cells property in the clock provider node.
-[1] http://patchwork.ozlabs.org/patch/31551/
+[1] https://patchwork.ozlabs.org/patch/31551/
==Clock providers==
diff --git a/Bindings/clock/idt,versaclock5.yaml b/Bindings/clock/idt,versaclock5.yaml
new file mode 100644
index 000000000000..28c6461b9a9a
--- /dev/null
+++ b/Bindings/clock/idt,versaclock5.yaml
@@ -0,0 +1,154 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/idt,versaclock5.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Binding for IDT VersaClock 5 and 6 programmable I2C clock generators
+
+description: |
+ The IDT VersaClock 5 and VersaClock 6 are programmable I2C
+ clock generators providing from 3 to 12 output clocks.
+
+ When referencing the provided clock in the DT using phandle and clock
+ specifier, the following mapping applies:
+
+ - 5P49V5923:
+ 0 -- OUT0_SEL_I2CB
+ 1 -- OUT1
+ 2 -- OUT2
+
+ - 5P49V5933:
+ 0 -- OUT0_SEL_I2CB
+ 1 -- OUT1
+ 2 -- OUT4
+
+ - other parts:
+ 0 -- OUT0_SEL_I2CB
+ 1 -- OUT1
+ 2 -- OUT2
+ 3 -- OUT3
+ 4 -- OUT4
+
+maintainers:
+ - Luca Ceresoli <luca@lucaceresoli.net>
+
+properties:
+ compatible:
+ enum:
+ - idt,5p49v5923
+ - idt,5p49v5925
+ - idt,5p49v5933
+ - idt,5p49v5935
+ - idt,5p49v6901
+ - idt,5p49v6965
+
+ reg:
+ description: I2C device address
+ enum: [ 0x68, 0x6a ]
+
+ '#clock-cells':
+ const: 1
+
+patternProperties:
+ "^OUT[1-4]$":
+ type: object
+ description:
+ Description of one of the outputs (OUT1..OUT4). See "Clock1 Output
+ Configuration" in the Versaclock 5/6/6E Family Register Description
+ and Programming Guide.
+ properties:
+ idt,mode:
+ description:
+ The output drive mode. Values defined in dt-bindings/clk/versaclock.h
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 6
+ idt,voltage-microvolt:
+ description: The output drive voltage.
+ enum: [ 1800000, 2500000, 3300000 ]
+ idt,slew-percent:
+ description: The Slew rate control for CMOS single-ended.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [ 80, 85, 90, 100 ]
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ enum:
+ - idt,5p49v5933
+ - idt,5p49v5935
+ then:
+ # Devices with builtin crystal + optional external input
+ properties:
+ clock-names:
+ const: clkin
+ clocks:
+ maxItems: 1
+ else:
+ # Devices without builtin crystal
+ properties:
+ clock-names:
+ minItems: 1
+ maxItems: 2
+ items:
+ enum: [ xin, clkin ]
+ clocks:
+ minItems: 1
+ maxItems: 2
+ required:
+ - clock-names
+ - clocks
+
+examples:
+ - |
+ #include <dt-bindings/clk/versaclock.h>
+
+ /* 25MHz reference crystal */
+ ref25: ref25m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ i2c@0 {
+ reg = <0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* IDT 5P49V5923 I2C clock generator */
+ vc5: clock-generator@6a {
+ compatible = "idt,5p49v5923";
+ reg = <0x6a>;
+ #clock-cells = <1>;
+
+ /* Connect XIN input to 25MHz reference */
+ clocks = <&ref25m>;
+ clock-names = "xin";
+
+ OUT1 {
+ idt,drive-mode = <VC5_CMOSD>;
+ idt,voltage-microvolts = <1800000>;
+ idt,slew-percent = <80>;
+ };
+
+ OUT4 {
+ idt,drive-mode = <VC5_LVDS>;
+ };
+ };
+ };
+
+ /* Consumer referencing the 5P49V5923 pin OUT1 */
+ consumer {
+ /* ... */
+ clocks = <&vc5 1>;
+ /* ... */
+ };
+
+...
diff --git a/Bindings/clock/imx23-clock.yaml b/Bindings/clock/imx23-clock.yaml
index 66cb238a1040..ad21899981af 100644
--- a/Bindings/clock/imx23-clock.yaml
+++ b/Bindings/clock/imx23-clock.yaml
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Clock bindings for Freescale i.MX23
maintainers:
- - Shawn Guo <shawn.guo@linaro.org>
+ - Shawn Guo <shawnguo@kernel.org>
description: |
The clock consumer should specify the desired clock by having the clock
diff --git a/Bindings/clock/imx28-clock.yaml b/Bindings/clock/imx28-clock.yaml
index 72328d5ca09a..f1af1108129e 100644
--- a/Bindings/clock/imx28-clock.yaml
+++ b/Bindings/clock/imx28-clock.yaml
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Clock bindings for Freescale i.MX28
maintainers:
- - Shawn Guo <shawn.guo@linaro.org>
+ - Shawn Guo <shawnguo@kernel.org>
description: |
The clock consumer should specify the desired clock by having the clock
diff --git a/Bindings/clock/imx35-clock.yaml b/Bindings/clock/imx35-clock.yaml
index bd871da6fc7c..3e20ccaf8131 100644
--- a/Bindings/clock/imx35-clock.yaml
+++ b/Bindings/clock/imx35-clock.yaml
@@ -130,7 +130,7 @@ examples:
#clock-cells = <1>;
};
- esdhc@53fb4000 {
+ mmc@53fb4000 {
compatible = "fsl,imx35-esdhc";
reg = <0x53fb4000 0x4000>;
interrupts = <7>;
diff --git a/Bindings/clock/imx7ulp-pcc-clock.yaml b/Bindings/clock/imx7ulp-pcc-clock.yaml
new file mode 100644
index 000000000000..7caf5cee9199
--- /dev/null
+++ b/Bindings/clock/imx7ulp-pcc-clock.yaml
@@ -0,0 +1,121 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/imx7ulp-pcc-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Clock bindings for Freescale i.MX7ULP Peripheral Clock Control (PCC) modules
+
+maintainers:
+ - A.s. Dong <aisheng.dong@nxp.com>
+
+description: |
+ i.MX7ULP Clock functions are under joint control of the System
+ Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
+ modules, and Core Mode Controller (CMC)1 blocks
+
+ The clocking scheme provides clear separation between M4 domain
+ and A7 domain. Except for a few clock sources shared between two
+ domains, such as the System Oscillator clock, the Slow IRC (SIRC),
+ and and the Fast IRC clock (FIRCLK), clock sources and clock
+ management are separated and contained within each domain.
+
+ M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
+ A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
+
+ Note: this binding doc is only for A7 clock domain.
+
+ The Peripheral Clock Control (PCC) is responsible for clock selection,
+ optional division and clock gating mode for peripherals in their
+ respected power domain.
+
+ The clock consumer should specify the desired clock by having the clock
+ ID in its "clocks" phandle cell.
+ See include/dt-bindings/clock/imx7ulp-clock.h for the full list of
+ i.MX7ULP clock IDs of each module.
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx7ulp-pcc2
+ - fsl,imx7ulp-pcc3
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+ clocks:
+ items:
+ - description: nic1 bus clock
+ - description: nic1 clock
+ - description: ddr clock
+ - description: apll pfd2
+ - description: apll pfd1
+ - description: apll pfd0
+ - description: usb pll
+ - description: system osc bus clock
+ - description: fast internal reference clock bus
+ - description: rtc osc
+ - description: system pll bus clock
+
+ clock-names:
+ items:
+ - const: nic1_bus_clk
+ - const: nic1_clk
+ - const: ddr_clk
+ - const: apll_pfd2
+ - const: apll_pfd1
+ - const: apll_pfd0
+ - const: upll
+ - const: sosc_bus_clk
+ - const: firc_bus_clk
+ - const: rosc
+ - const: spll_bus_clk
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx7ulp-clock.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ clock-controller@403f0000 {
+ compatible = "fsl,imx7ulp-pcc2";
+ reg = <0x403f0000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
+ <&scg1 IMX7ULP_CLK_NIC1_DIV>,
+ <&scg1 IMX7ULP_CLK_DDR_DIV>,
+ <&scg1 IMX7ULP_CLK_APLL_PFD2>,
+ <&scg1 IMX7ULP_CLK_APLL_PFD1>,
+ <&scg1 IMX7ULP_CLK_APLL_PFD0>,
+ <&scg1 IMX7ULP_CLK_UPLL>,
+ <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
+ <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
+ <&scg1 IMX7ULP_CLK_ROSC>,
+ <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
+ clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
+ "apll_pfd2", "apll_pfd1", "apll_pfd0",
+ "upll", "sosc_bus_clk", "firc_bus_clk",
+ "rosc", "spll_bus_clk";
+ };
+
+ mmc@40380000 {
+ compatible = "fsl,imx7ulp-usdhc";
+ reg = <0x40380000 0x10000>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
+ <&scg1 IMX7ULP_CLK_NIC1_DIV>,
+ <&pcc2 IMX7ULP_CLK_USDHC1>;
+ clock-names ="ipg", "ahb", "per";
+ bus-width = <4>;
+ };
diff --git a/Bindings/clock/imx7ulp-scg-clock.yaml b/Bindings/clock/imx7ulp-scg-clock.yaml
new file mode 100644
index 000000000000..ee8efb4ed599
--- /dev/null
+++ b/Bindings/clock/imx7ulp-scg-clock.yaml
@@ -0,0 +1,99 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/imx7ulp-scg-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Clock bindings for Freescale i.MX7ULP System Clock Generation (SCG) modules
+
+maintainers:
+ - A.s. Dong <aisheng.dong@nxp.com>
+
+description: |
+ i.MX7ULP Clock functions are under joint control of the System
+ Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
+ modules, and Core Mode Controller (CMC)1 blocks
+
+ The clocking scheme provides clear separation between M4 domain
+ and A7 domain. Except for a few clock sources shared between two
+ domains, such as the System Oscillator clock, the Slow IRC (SIRC),
+ and and the Fast IRC clock (FIRCLK), clock sources and clock
+ management are separated and contained within each domain.
+
+ M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
+ A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
+
+ Note: this binding doc is only for A7 clock domain.
+
+ The System Clock Generation (SCG) is responsible for clock generation
+ and distribution across this device. Functions performed by the SCG
+ include: clock reference selection, generation of clock used to derive
+ processor, system, peripheral bus and external memory interface clocks,
+ source selection for peripheral clocks and control of power saving
+ clock gating mode.
+
+ The clock consumer should specify the desired clock by having the clock
+ ID in its "clocks" phandle cell.
+ See include/dt-bindings/clock/imx7ulp-clock.h for the full list of
+ i.MX7ULP clock IDs of each module.
+
+properties:
+ compatible:
+ const: fsl,imx7ulp-scg1
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+ clocks:
+ items:
+ - description: rtc osc
+ - description: system osc
+ - description: slow internal reference clock
+ - description: fast internal reference clock
+ - description: usb PLL
+
+ clock-names:
+ items:
+ - const: rosc
+ - const: sosc
+ - const: sirc
+ - const: firc
+ - const: upll
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx7ulp-clock.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ clock-controller@403e0000 {
+ compatible = "fsl,imx7ulp-scg1";
+ reg = <0x403e0000 0x10000>;
+ clocks = <&rosc>, <&sosc>, <&sirc>,
+ <&firc>, <&upll>;
+ clock-names = "rosc", "sosc", "sirc",
+ "firc", "upll";
+ #clock-cells = <1>;
+ };
+
+ mmc@40380000 {
+ compatible = "fsl,imx7ulp-usdhc";
+ reg = <0x40380000 0x10000>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
+ <&scg1 IMX7ULP_CLK_NIC1_DIV>,
+ <&pcc2 IMX7ULP_CLK_USDHC1>;
+ clock-names ="ipg", "ahb", "per";
+ bus-width = <4>;
+ };
diff --git a/Bindings/clock/imx8qxp-lpcg.yaml b/Bindings/clock/imx8qxp-lpcg.yaml
index 33f3010f48c3..1d5e9bcce4c8 100644
--- a/Bindings/clock/imx8qxp-lpcg.yaml
+++ b/Bindings/clock/imx8qxp-lpcg.yaml
@@ -62,7 +62,7 @@ examples:
};
mmc@5b010000 {
- compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
+ compatible = "fsl,imx8qxp-usdhc";
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5b010000 0x10000>;
clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>,
diff --git a/Bindings/clock/ingenic,cgu.yaml b/Bindings/clock/ingenic,cgu.yaml
index a952d5811823..5dd7ea8a78e4 100644
--- a/Bindings/clock/ingenic,cgu.yaml
+++ b/Bindings/clock/ingenic,cgu.yaml
@@ -47,12 +47,12 @@ properties:
compatible:
items:
- enum:
- - ingenic,jz4740-cgu
- - ingenic,jz4725b-cgu
- - ingenic,jz4770-cgu
- - ingenic,jz4780-cgu
- - ingenic,x1000-cgu
- - ingenic,x1830-cgu
+ - ingenic,jz4740-cgu
+ - ingenic,jz4725b-cgu
+ - ingenic,jz4770-cgu
+ - ingenic,jz4780-cgu
+ - ingenic,x1000-cgu
+ - ingenic,x1830-cgu
- const: simple-mfd
minItems: 1
@@ -68,8 +68,8 @@ properties:
items:
- const: ext
- enum:
- - rtc
- - osc32k # Different name, same clock
+ - rtc
+ - osc32k # Different name, same clock
assigned-clocks:
minItems: 1
diff --git a/Bindings/clock/microchip,sparx5-dpll.yaml b/Bindings/clock/microchip,sparx5-dpll.yaml
new file mode 100644
index 000000000000..39559a0a598a
--- /dev/null
+++ b/Bindings/clock/microchip,sparx5-dpll.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/microchip,sparx5-dpll.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip Sparx5 DPLL Clock
+
+maintainers:
+ - Lars Povlsen <lars.povlsen@microchip.com>
+
+description: |
+ The Sparx5 DPLL clock controller generates and supplies clock to
+ various peripherals within the SoC.
+
+properties:
+ compatible:
+ const: microchip,sparx5-dpll
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ # Clock provider for eMMC:
+ - |
+ lcpll_clk: lcpll-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2500000000>;
+ };
+ clks: clock-controller@61110000c {
+ compatible = "microchip,sparx5-dpll";
+ #clock-cells = <1>;
+ clocks = <&lcpll_clk>;
+ reg = <0x1110000c 0x24>;
+ };
+
+...
diff --git a/Bindings/clock/qcom,a53pll.yaml b/Bindings/clock/qcom,a53pll.yaml
index 20d2638b4cd2..db3d0ea6bc7a 100644
--- a/Bindings/clock/qcom,a53pll.yaml
+++ b/Bindings/clock/qcom,a53pll.yaml
@@ -15,7 +15,9 @@ description:
properties:
compatible:
- const: qcom,msm8916-a53pll
+ enum:
+ - qcom,ipq6018-a53pll
+ - qcom,msm8916-a53pll
reg:
maxItems: 1
@@ -23,6 +25,14 @@ properties:
'#clock-cells':
const: 0
+ clocks:
+ items:
+ - description: board XO clock
+
+ clock-names:
+ items:
+ - const: xo
+
required:
- compatible
- reg
@@ -38,3 +48,12 @@ examples:
reg = <0xb016000 0x40>;
#clock-cells = <0>;
};
+ #Example 2 - A53 PLL found on IPQ6018 devices
+ - |
+ a53pll_ipq: clock-controller@b116000 {
+ compatible = "qcom,ipq6018-a53pll";
+ reg = <0x0b116000 0x40>;
+ #clock-cells = <0>;
+ clocks = <&xo>;
+ clock-names = "xo";
+ };
diff --git a/Bindings/clock/qcom,gpucc.yaml b/Bindings/clock/qcom,gpucc.yaml
new file mode 100644
index 000000000000..df943c4c3234
--- /dev/null
+++ b/Bindings/clock/qcom,gpucc.yaml
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,gpucc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Graphics Clock & Reset Controller Binding
+
+maintainers:
+ - Taniya Das <tdas@codeaurora.org>
+
+description: |
+ Qualcomm graphics clock control module which supports the clocks, resets and
+ power domains on SDM845/SC7180/SM8150/SM8250.
+
+ See also:
+ dt-bindings/clock/qcom,gpucc-sdm845.h
+ dt-bindings/clock/qcom,gpucc-sc7180.h
+ dt-bindings/clock/qcom,gpucc-sm8150.h
+ dt-bindings/clock/qcom,gpucc-sm8250.h
+
+properties:
+ compatible:
+ enum:
+ - qcom,sdm845-gpucc
+ - qcom,sc7180-gpucc
+ - qcom,sm8150-gpucc
+ - qcom,sm8250-gpucc
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: GPLL0 main branch source
+ - description: GPLL0 div branch source
+
+ clock-names:
+ items:
+ - const: bi_tcxo
+ - const: gcc_gpu_gpll0_clk_src
+ - const: gcc_gpu_gpll0_div_clk_src
+
+ '#clock-cells':
+ const: 1
+
+ '#reset-cells':
+ const: 1
+
+ '#power-domain-cells':
+ const: 1
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#reset-cells'
+ - '#power-domain-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-sdm845.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ clock-controller@5090000 {
+ compatible = "qcom,sdm845-gpucc";
+ reg = <0x05090000 0x9000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_GPU_GPLL0_CLK_SRC>,
+ <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
+ clock-names = "bi_tcxo",
+ "gcc_gpu_gpll0_clk_src",
+ "gcc_gpu_gpll0_div_clk_src";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+...
diff --git a/Bindings/clock/qcom,mmcc.yaml b/Bindings/clock/qcom,mmcc.yaml
index 1b16a863b355..af32dee14fc6 100644
--- a/Bindings/clock/qcom,mmcc.yaml
+++ b/Bindings/clock/qcom,mmcc.yaml
@@ -65,7 +65,7 @@ properties:
protected-clocks:
description:
- Protected clock specifier list as per common clock binding
+ Protected clock specifier list as per common clock binding
vdd-gfx-supply:
description:
diff --git a/Bindings/clock/qcom,msm8996-apcc.yaml b/Bindings/clock/qcom,msm8996-apcc.yaml
new file mode 100644
index 000000000000..a20cb10636dd
--- /dev/null
+++ b/Bindings/clock/qcom,msm8996-apcc.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,msm8996-apcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm clock controller for MSM8996 CPUs
+
+maintainers:
+ - Loic Poulain <loic.poulain@linaro.org>
+
+description: |
+ Qualcomm CPU clock controller for MSM8996 CPUs, clock 0 is for Power cluster
+ and clock 1 is for Perf cluster.
+
+properties:
+ compatible:
+ enum:
+ - qcom,msm8996-apcc
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+ clocks:
+ items:
+ - description: Primary PLL clock for power cluster (little)
+ - description: Primary PLL clock for perf cluster (big)
+ - description: Alternate PLL clock for power cluster (little)
+ - description: Alternate PLL clock for perf cluster (big)
+
+ clock-names:
+ items:
+ - const: pwrcl_pll
+ - const: perfcl_pll
+ - const: pwrcl_alt_pll
+ - const: perfcl_alt_pll
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ kryocc: clock-controller@6400000 {
+ compatible = "qcom,msm8996-apcc";
+ reg = <0x6400000 0x90000>;
+ #clock-cells = <1>;
+ };
diff --git a/Bindings/clock/qcom,rpmcc.txt b/Bindings/clock/qcom,rpmcc.txt
index 90a1349bc713..b44a0622fb3a 100644
--- a/Bindings/clock/qcom,rpmcc.txt
+++ b/Bindings/clock/qcom,rpmcc.txt
@@ -13,13 +13,17 @@ Required properties :
"qcom,rpmcc-msm8660", "qcom,rpmcc"
"qcom,rpmcc-apq8060", "qcom,rpmcc"
"qcom,rpmcc-msm8916", "qcom,rpmcc"
+ "qcom,rpmcc-msm8936", "qcom,rpmcc"
"qcom,rpmcc-msm8974", "qcom,rpmcc"
"qcom,rpmcc-msm8976", "qcom,rpmcc"
"qcom,rpmcc-apq8064", "qcom,rpmcc"
"qcom,rpmcc-ipq806x", "qcom,rpmcc"
+ "qcom,rpmcc-msm8992",·"qcom,rpmcc"
+ "qcom,rpmcc-msm8994",·"qcom,rpmcc"
"qcom,rpmcc-msm8996", "qcom,rpmcc"
"qcom,rpmcc-msm8998", "qcom,rpmcc"
"qcom,rpmcc-qcs404", "qcom,rpmcc"
+ "qcom,rpmcc-sdm660", "qcom,rpmcc"
- #clock-cells : shall contain 1
diff --git a/Bindings/clock/qcom,sc7180-lpasscorecc.yaml b/Bindings/clock/qcom,sc7180-lpasscorecc.yaml
new file mode 100644
index 000000000000..c54172fbf29f
--- /dev/null
+++ b/Bindings/clock/qcom,sc7180-lpasscorecc.yaml
@@ -0,0 +1,108 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,sc7180-lpasscorecc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm LPASS Core Clock Controller Binding for SC7180
+
+maintainers:
+ - Taniya Das <tdas@codeaurora.org>
+
+description: |
+ Qualcomm LPASS core clock control module which supports the clocks and
+ power domains on SC7180.
+
+ See also:
+ - dt-bindings/clock/qcom,lpasscorecc-sc7180.h
+
+properties:
+ compatible:
+ enum:
+ - qcom,sc7180-lpasshm
+ - qcom,sc7180-lpasscorecc
+
+ clocks:
+ items:
+ - description: gcc_lpass_sway clock from GCC
+ - description: Board XO source
+
+ clock-names:
+ items:
+ - const: iface
+ - const: bi_tcxo
+
+ power-domains:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+ '#power-domain-cells':
+ const: 1
+
+ reg:
+ minItems: 1
+ items:
+ - description: lpass core cc register
+ - description: lpass audio cc register
+
+ reg-names:
+ items:
+ - const: lpass_core_cc
+ - const: lpass_audio_cc
+
+if:
+ properties:
+ compatible:
+ contains:
+ const: qcom,sc7180-lpasshm
+then:
+ properties:
+ reg:
+ maxItems: 1
+
+else:
+ properties:
+ reg:
+ minItems: 2
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#power-domain-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/clock/qcom,gcc-sc7180.h>
+ #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
+ clock-controller@63000000 {
+ compatible = "qcom,sc7180-lpasshm";
+ reg = <0x63000000 0x28>;
+ clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "bi_tcxo";
+ #clock-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/clock/qcom,gcc-sc7180.h>
+ #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
+ clock-controller@62d00000 {
+ compatible = "qcom,sc7180-lpasscorecc";
+ reg = <0x62d00000 0x50000>, <0x62780000 0x30000>;
+ reg-names = "lpass_core_cc", "lpass_audio_cc";
+ clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "bi_tcxo";
+ power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
+ #clock-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+...
diff --git a/Bindings/clock/renesas,cpg-clocks.yaml b/Bindings/clock/renesas,cpg-clocks.yaml
new file mode 100644
index 000000000000..9185d101737e
--- /dev/null
+++ b/Bindings/clock/renesas,cpg-clocks.yaml
@@ -0,0 +1,241 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/renesas,cpg-clocks.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas Clock Pulse Generator (CPG)
+
+maintainers:
+ - Geert Uytterhoeven <geert+renesas@glider.be>
+
+description:
+ The Clock Pulse Generator (CPG) generates core clocks for the SoC. It
+ includes PLLs, and fixed and variable ratio dividers.
+
+ The CPG may also provide a Clock Domain for SoC devices, in combination with
+ the CPG Module Stop (MSTP) Clocks.
+
+properties:
+ compatible:
+ oneOf:
+ - const: renesas,r8a73a4-cpg-clocks # R-Mobile APE6
+ - const: renesas,r8a7740-cpg-clocks # R-Mobile A1
+ - const: renesas,r8a7778-cpg-clocks # R-Car M1
+ - const: renesas,r8a7779-cpg-clocks # R-Car H1
+ - items:
+ - enum:
+ - renesas,r7s72100-cpg-clocks # RZ/A1H
+ - const: renesas,rz-cpg-clocks # RZ/A1
+ - const: renesas,sh73a0-cpg-clocks # SH-Mobile AG5
+
+ reg:
+ maxItems: 1
+
+ clocks: true
+
+ '#clock-cells':
+ const: 1
+
+ clock-output-names: true
+
+ renesas,mode:
+ description: Board-specific settings of the MD_CK* bits on R-Mobile A1
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 7
+
+ '#power-domain-cells':
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - '#clock-cells'
+ - clock-output-names
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r8a73a4-cpg-clocks
+ then:
+ properties:
+ clocks:
+ items:
+ - description: extal1
+ - description: extal2
+
+ clock-output-names:
+ items:
+ - const: main
+ - const: pll0
+ - const: pll1
+ - const: pll2
+ - const: pll2s
+ - const: pll2h
+ - const: z
+ - const: z2
+ - const: i
+ - const: m3
+ - const: b
+ - const: m1
+ - const: m2
+ - const: zx
+ - const: zs
+ - const: hp
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r8a7740-cpg-clocks
+ then:
+ properties:
+ clocks:
+ items:
+ - description: extal1
+ - description: extal2
+ - description: extalr
+
+ clock-output-names:
+ items:
+ - const: system
+ - const: pllc0
+ - const: pllc1
+ - const: pllc2
+ - const: r
+ - const: usb24s
+ - const: i
+ - const: zg
+ - const: b
+ - const: m1
+ - const: hp
+ - const: hpp
+ - const: usbp
+ - const: s
+ - const: zb
+ - const: m3
+ - const: cp
+
+ required:
+ - renesas,mode
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r8a7778-cpg-clocks
+ then:
+ properties:
+ clocks:
+ maxItems: 1
+
+ clock-output-names:
+ items:
+ - const: plla
+ - const: pllb
+ - const: b
+ - const: out
+ - const: p
+ - const: s
+ - const: s1
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r8a7779-cpg-clocks
+ then:
+ properties:
+ clocks:
+ maxItems: 1
+
+ clock-output-names:
+ items:
+ - const: plla
+ - const: z
+ - const: zs
+ - const: s
+ - const: s1
+ - const: p
+ - const: b
+ - const: out
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r7s72100-cpg-clocks
+ then:
+ properties:
+ clocks:
+ items:
+ - description: extal1
+ - description: usb_x1
+
+ clock-output-names:
+ items:
+ - const: pll
+ - const: i
+ - const: g
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,sh73a0-cpg-clocks
+ then:
+ properties:
+ clocks:
+ items:
+ - description: extal1
+ - description: extal2
+
+ clock-output-names:
+ items:
+ - const: main
+ - const: pll0
+ - const: pll1
+ - const: pll2
+ - const: pll3
+ - const: dsi0phy
+ - const: dsi1phy
+ - const: zg
+ - const: m3
+ - const: b
+ - const: m1
+ - const: m2
+ - const: z
+ - const: zx
+ - const: hp
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,r8a7778-cpg-clocks
+ - renesas,r8a7779-cpg-clocks
+ - renesas,rz-cpg-clocks
+ then:
+ required:
+ - '#power-domain-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r8a7740-clock.h>
+ cpg_clocks: cpg_clocks@e6150000 {
+ compatible = "renesas,r8a7740-cpg-clocks";
+ reg = <0xe6150000 0x10000>;
+ clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>;
+ #clock-cells = <1>;
+ clock-output-names = "system", "pllc0", "pllc1", "pllc2", "r",
+ "usb24s", "i", "zg", "b", "m1", "hp", "hpp",
+ "usbp", "s", "zb", "m3", "cp";
+ renesas,mode = <0x05>;
+ };
diff --git a/Bindings/clock/renesas,cpg-mssr.yaml b/Bindings/clock/renesas,cpg-mssr.yaml
index c745bd60719a..e13aee8ab61a 100644
--- a/Bindings/clock/renesas,cpg-mssr.yaml
+++ b/Bindings/clock/renesas,cpg-mssr.yaml
@@ -33,6 +33,7 @@ properties:
- renesas,r8a774a1-cpg-mssr # RZ/G2M
- renesas,r8a774b1-cpg-mssr # RZ/G2N
- renesas,r8a774c0-cpg-mssr # RZ/G2E
+ - renesas,r8a774e1-cpg-mssr # RZ/G2H
- renesas,r8a7790-cpg-mssr # R-Car H2
- renesas,r8a7791-cpg-mssr # R-Car M2-W
- renesas,r8a7792-cpg-mssr # R-Car V2H
diff --git a/Bindings/clock/rockchip,rk3288-cru.txt b/Bindings/clock/rockchip,rk3288-cru.txt
index 8cb47c39ba53..bf3a9ec19241 100644
--- a/Bindings/clock/rockchip,rk3288-cru.txt
+++ b/Bindings/clock/rockchip,rk3288-cru.txt
@@ -4,9 +4,15 @@ The RK3288 clock controller generates and supplies clock to various
controllers within the SoC and also implements a reset controller for SoC
peripherals.
+A revision of this SoC is available: rk3288w. The clock tree is a bit
+different so another dt-compatible is available. Noticed that it is only
+setting the difference but there is no automatic revision detection. This
+should be performed by bootloaders.
+
Required Properties:
-- compatible: should be "rockchip,rk3288-cru"
+- compatible: should be "rockchip,rk3288-cru" or "rockchip,rk3288w-cru" in
+ case of this revision of Rockchip rk3288.
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
diff --git a/Bindings/clock/silabs,si514.txt b/Bindings/clock/silabs,si514.txt
index ea1a9dbc63b6..a4f28ec86f35 100644
--- a/Bindings/clock/silabs,si514.txt
+++ b/Bindings/clock/silabs,si514.txt
@@ -6,7 +6,7 @@ found in the datasheet[2].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Si514 datasheet
- http://www.silabs.com/Support%20Documents/TechnicalDocs/si514.pdf
+ https://www.silabs.com/Support%20Documents/TechnicalDocs/si514.pdf
Required properties:
- compatible: Shall be "silabs,si514"
diff --git a/Bindings/clock/silabs,si5351.txt b/Bindings/clock/silabs,si5351.txt
index f00191cad8cd..8fe6f80afade 100644
--- a/Bindings/clock/silabs,si5351.txt
+++ b/Bindings/clock/silabs,si5351.txt
@@ -2,7 +2,7 @@ Binding for Silicon Labs Si5351a/b/c programmable i2c clock generator.
Reference
[1] Si5351A/B/C Data Sheet
- http://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351.pdf
+ https://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351.pdf
The Si5351a/b/c are programmable i2c clock generators with up to 8 output
clocks. Si5351a also has a reduced pin-count package (MSOP10) where only
diff --git a/Bindings/clock/silabs,si570.txt b/Bindings/clock/silabs,si570.txt
index c09f21e1d98f..901935e929d2 100644
--- a/Bindings/clock/silabs,si570.txt
+++ b/Bindings/clock/silabs,si570.txt
@@ -7,9 +7,9 @@ found in the data sheets[2][3].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Si570/571 Data Sheet
- http://www.silabs.com/Support%20Documents/TechnicalDocs/si570.pdf
+ https://www.silabs.com/Support%20Documents/TechnicalDocs/si570.pdf
[3] Si598/599 Data Sheet
- http://www.silabs.com/Support%20Documents/TechnicalDocs/si598-99.pdf
+ https://www.silabs.com/Support%20Documents/TechnicalDocs/si598-99.pdf
Required properties:
- compatible: Shall be one of "silabs,si570", "silabs,si571",
diff --git a/Bindings/clock/sprd,sc9863a-clk.yaml b/Bindings/clock/sprd,sc9863a-clk.yaml
index 29813873cfbc..c6d091518650 100644
--- a/Bindings/clock/sprd,sc9863a-clk.yaml
+++ b/Bindings/clock/sprd,sc9863a-clk.yaml
@@ -16,7 +16,7 @@ properties:
"#clock-cells":
const: 1
- compatible :
+ compatible:
enum:
- sprd,sc9863a-ap-clk
- sprd,sc9863a-aon-clk
diff --git a/Bindings/clock/ti,cdce706.txt b/Bindings/clock/ti,cdce706.txt
index 959d96632f5d..21c3ff764788 100644
--- a/Bindings/clock/ti,cdce706.txt
+++ b/Bindings/clock/ti,cdce706.txt
@@ -1,7 +1,7 @@
Bindings for Texas Instruments CDCE706 programmable 3-PLL clock
synthesizer/multiplier/divider.
-Reference: http://www.ti.com/lit/ds/symlink/cdce706.pdf
+Reference: https://www.ti.com/lit/ds/symlink/cdce706.pdf
I2C device node required properties:
- compatible: shall be "ti,cdce706".
diff --git a/Bindings/clock/ti,cdce925.txt b/Bindings/clock/ti,cdce925.txt
index 26544c85202a..df42ab72718f 100644
--- a/Bindings/clock/ti,cdce925.txt
+++ b/Bindings/clock/ti,cdce925.txt
@@ -4,10 +4,10 @@ Reference
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-[2] http://www.ti.com/product/cdce913
-[3] http://www.ti.com/product/cdce925
-[4] http://www.ti.com/product/cdce937
-[5] http://www.ti.com/product/cdce949
+[2] https://www.ti.com/product/cdce913
+[3] https://www.ti.com/product/cdce925
+[4] https://www.ti.com/product/cdce937
+[5] https://www.ti.com/product/cdce949
The driver provides clock sources for each output Y1 through Y5.
diff --git a/Bindings/cpufreq/cpufreq-dt.txt b/Bindings/cpufreq/cpufreq-dt.txt
index 332aed8f4597..56f442374383 100644
--- a/Bindings/cpufreq/cpufreq-dt.txt
+++ b/Bindings/cpufreq/cpufreq-dt.txt
@@ -18,7 +18,8 @@ Optional properties:
in unit of nanoseconds.
- voltage-tolerance: Specify the CPU voltage tolerance in percentage.
- #cooling-cells:
- Please refer to Documentation/devicetree/bindings/thermal/thermal.txt.
+ Please refer to
+ Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml.
Examples:
diff --git a/Bindings/cpufreq/cpufreq-mediatek.txt b/Bindings/cpufreq/cpufreq-mediatek.txt
index 0551c78619de..ea4994b35207 100644
--- a/Bindings/cpufreq/cpufreq-mediatek.txt
+++ b/Bindings/cpufreq/cpufreq-mediatek.txt
@@ -21,8 +21,8 @@ Optional properties:
flow is handled by hardware, hence no software "voltage tracking" is
needed.
- #cooling-cells:
- Please refer to Documentation/devicetree/bindings/thermal/thermal.txt
- for detail.
+ For details, please refer to
+ Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml
Example 1 (MT7623 SoC):
diff --git a/Bindings/cpufreq/nvidia,tegra20-cpufreq.txt b/Bindings/cpufreq/nvidia,tegra20-cpufreq.txt
index daeca6ae6b76..52a24b82fd86 100644
--- a/Bindings/cpufreq/nvidia,tegra20-cpufreq.txt
+++ b/Bindings/cpufreq/nvidia,tegra20-cpufreq.txt
@@ -5,7 +5,7 @@ Required properties:
- clocks: Must contain an entry for the CPU clock.
See ../clocks/clock-bindings.txt for details.
- operating-points-v2: See ../bindings/opp/opp.txt for details.
-- #cooling-cells: Should be 2. See ../thermal/thermal.txt for details.
+- #cooling-cells: Should be 2. See ../thermal/thermal-cooling-devices.yaml for details.
For each opp entry in 'operating-points-v2' table:
- opp-supported-hw: Two bitfields indicating:
diff --git a/Bindings/crypto/ti,sa2ul.yaml b/Bindings/crypto/ti,sa2ul.yaml
new file mode 100644
index 000000000000..1465c9ebaf93
--- /dev/null
+++ b/Bindings/crypto/ti,sa2ul.yaml
@@ -0,0 +1,76 @@
+# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/crypto/ti,sa2ul.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: K3 SoC SA2UL crypto module
+
+maintainers:
+ - Tero Kristo <t-kristo@ti.com>
+
+properties:
+ compatible:
+ enum:
+ - ti,j721e-sa2ul
+ - ti,am654-sa2ul
+
+ reg:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ dmas:
+ items:
+ - description: TX DMA Channel
+ - description: RX DMA Channel #1
+ - description: RX DMA Channel #2
+
+ dma-names:
+ items:
+ - const: tx
+ - const: rx1
+ - const: rx2
+
+ dma-coherent: true
+
+ "#address-cells":
+ const: 2
+
+ "#size-cells":
+ const: 2
+
+ ranges:
+ description:
+ Address translation for the possible RNG child node for SA2UL
+
+patternProperties:
+ "^rng@[a-f0-9]+$":
+ type: object
+ description:
+ Child RNG node for SA2UL
+
+required:
+ - compatible
+ - reg
+ - power-domains
+ - dmas
+ - dma-names
+ - dma-coherent
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/soc/ti,sci_pm_domain.h>
+
+ main_crypto: crypto@4e00000 {
+ compatible = "ti,j721-sa2ul";
+ reg = <0x4e00000 0x1200>;
+ power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>;
+ dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
+ <&main_udmap 0x4001>;
+ dma-names = "tx", "rx1", "rx2";
+ dma-coherent;
+ };
diff --git a/Bindings/devfreq/rk3399_dmc.txt b/Bindings/devfreq/rk3399_dmc.txt
index 0ec68141f85a..a10d1f6d85c6 100644
--- a/Bindings/devfreq/rk3399_dmc.txt
+++ b/Bindings/devfreq/rk3399_dmc.txt
@@ -18,6 +18,8 @@ Optional properties:
format depends on the interrupt controller.
It should be a DCF interrupt. When DDR DVFS finishes
a DCF interrupt is triggered.
+- rockchip,pmu: Phandle to the syscon managing the "PMU general register
+ files".
Following properties relate to DDR timing:
diff --git a/Bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml b/Bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml
index 1dee641e3ea1..c040eef56518 100644
--- a/Bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml
+++ b/Bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml
@@ -36,6 +36,9 @@ properties:
- const: bus
- const: mod
+ iommus:
+ maxItems: 1
+
resets:
maxItems: 1
diff --git a/Bindings/display/brcm,bcm2835-dpi.yaml b/Bindings/display/brcm,bcm2835-dpi.yaml
new file mode 100644
index 000000000000..5c1024bbc1b3
--- /dev/null
+++ b/Bindings/display/brcm,bcm2835-dpi.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/brcm,bcm2835-dpi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom VC4 (VideoCore4) DPI Controller
+
+maintainers:
+ - Eric Anholt <eric@anholt.net>
+
+properties:
+ compatible:
+ const: brcm,bcm2835-dpi
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: The core clock the unit runs on
+ - description: The pixel clock that feeds the pixelvalve
+
+ clock-names:
+ items:
+ - const: core
+ - const: pixel
+
+ port:
+ type: object
+ description: >
+ Port node with a single endpoint connecting to the panel, as
+ defined in Documentation/devicetree/bindings/media/video-interfaces.txt.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - port
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/bcm2835.h>
+
+ dpi: dpi@7e208000 {
+ compatible = "brcm,bcm2835-dpi";
+ reg = <0x7e208000 0x8c>;
+ clocks = <&clocks BCM2835_CLOCK_VPU>,
+ <&clocks BCM2835_CLOCK_DPI>;
+ clock-names = "core", "pixel";
+
+ port {
+ dpi_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+
+...
diff --git a/Bindings/display/brcm,bcm2835-dsi0.yaml b/Bindings/display/brcm,bcm2835-dsi0.yaml
new file mode 100644
index 000000000000..3c643b227a70
--- /dev/null
+++ b/Bindings/display/brcm,bcm2835-dsi0.yaml
@@ -0,0 +1,84 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/brcm,bcm2835-dsi0.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom VC4 (VideoCore4) DSI Controller
+
+maintainers:
+ - Eric Anholt <eric@anholt.net>
+
+properties:
+ "#clock-cells":
+ const: 1
+
+ compatible:
+ enum:
+ - brcm,bcm2835-dsi0
+ - brcm,bcm2835-dsi1
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: The DSI PLL clock feeding the DSI analog PHY
+ - description: The DSI ESC clock
+ - description: The DSI pixel clock
+
+ clock-names:
+ items:
+ - const: phy
+ - const: escape
+ - const: pixel
+
+ clock-output-names: true
+ # FIXME: The meta-schemas don't seem to allow it for now
+ # items:
+ # - description: The DSI byte clock for the PHY
+ # - description: The DSI DDR2 clock
+ # - description: The DSI DDR clock
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - "#clock-cells"
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - clock-output-names
+ - interrupts
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/bcm2835.h>
+
+ dsi1: dsi@7e700000 {
+ compatible = "brcm,bcm2835-dsi1";
+ reg = <0x7e700000 0x8c>;
+ interrupts = <2 12>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <1>;
+
+ clocks = <&clocks BCM2835_PLLD_DSI1>,
+ <&clocks BCM2835_CLOCK_DSI1E>,
+ <&clocks BCM2835_CLOCK_DSI1P>;
+ clock-names = "phy", "escape", "pixel";
+
+ clock-output-names = "dsi1_byte", "dsi1_ddr2", "dsi1_ddr";
+
+ pitouchscreen: panel@0 {
+ compatible = "raspberrypi,touchscreen";
+ reg = <0>;
+
+ /* ... */
+ };
+ };
+
+...
diff --git a/Bindings/display/brcm,bcm2835-hdmi.yaml b/Bindings/display/brcm,bcm2835-hdmi.yaml
new file mode 100644
index 000000000000..f54b4e4808f0
--- /dev/null
+++ b/Bindings/display/brcm,bcm2835-hdmi.yaml
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/brcm,bcm2835-hdmi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom VC4 (VideoCore4) HDMI Controller
+
+maintainers:
+ - Eric Anholt <eric@anholt.net>
+
+properties:
+ compatible:
+ const: brcm,bcm2835-hdmi
+
+ reg:
+ items:
+ - description: HDMI register range
+ - description: HD register range
+
+ interrupts:
+ minItems: 2
+
+ clocks:
+ items:
+ - description: The pixel clock
+ - description: The HDMI state machine clock
+
+ clock-names:
+ items:
+ - const: pixel
+ - const: hdmi
+
+ ddc:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: >
+ Phandle of the I2C controller used for DDC EDID probing
+
+ hpd-gpios:
+ description: >
+ The GPIO pin for the HDMI hotplug detect (if it doesn't appear
+ as an interrupt/status bit in the HDMI controller itself)
+
+ dmas:
+ maxItems: 1
+ description: >
+ Should contain one entry pointing to the DMA channel used to
+ transfer audio data.
+
+ dma-names:
+ const: audio-rx
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - ddc
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/bcm2835.h>
+ #include <dt-bindings/gpio/gpio.h>
+
+ hdmi: hdmi@7e902000 {
+ compatible = "brcm,bcm2835-hdmi";
+ reg = <0x7e902000 0x600>,
+ <0x7e808000 0x100>;
+ interrupts = <2 8>, <2 9>;
+ ddc = <&i2c2>;
+ hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>;
+ clocks = <&clocks BCM2835_PLLH_PIX>,
+ <&clocks BCM2835_CLOCK_HSM>;
+ clock-names = "pixel", "hdmi";
+ };
+
+...
diff --git a/Bindings/display/brcm,bcm2835-hvs.yaml b/Bindings/display/brcm,bcm2835-hvs.yaml
new file mode 100644
index 000000000000..02410f8d6d49
--- /dev/null
+++ b/Bindings/display/brcm,bcm2835-hvs.yaml
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/brcm,bcm2835-hvs.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom VC4 (VideoCore4) Hardware Video Scaler
+
+maintainers:
+ - Eric Anholt <eric@anholt.net>
+
+properties:
+ compatible:
+ const: brcm,bcm2835-hvs
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ hvs@7e400000 {
+ compatible = "brcm,bcm2835-hvs";
+ reg = <0x7e400000 0x6000>;
+ interrupts = <2 1>;
+ };
+
+...
diff --git a/Bindings/display/brcm,bcm2835-pixelvalve0.yaml b/Bindings/display/brcm,bcm2835-pixelvalve0.yaml
new file mode 100644
index 000000000000..e60791db1fa1
--- /dev/null
+++ b/Bindings/display/brcm,bcm2835-pixelvalve0.yaml
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/brcm,bcm2835-pixelvalve0.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom VC4 (VideoCore4) PixelValve
+
+maintainers:
+ - Eric Anholt <eric@anholt.net>
+
+properties:
+ compatible:
+ enum:
+ - brcm,bcm2835-pixelvalve0
+ - brcm,bcm2835-pixelvalve1
+ - brcm,bcm2835-pixelvalve2
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ pixelvalve@7e807000 {
+ compatible = "brcm,bcm2835-pixelvalve2";
+ reg = <0x7e807000 0x100>;
+ interrupts = <2 10>; /* pixelvalve */
+ };
+
+...
diff --git a/Bindings/display/brcm,bcm2835-txp.yaml b/Bindings/display/brcm,bcm2835-txp.yaml
new file mode 100644
index 000000000000..bb186197e471
--- /dev/null
+++ b/Bindings/display/brcm,bcm2835-txp.yaml
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/brcm,bcm2835-txp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom VC4 (VideoCore4) TXP (writeback) Controller
+
+maintainers:
+ - Eric Anholt <eric@anholt.net>
+
+properties:
+ compatible:
+ const: brcm,bcm2835-txp
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ txp: txp@7e004000 {
+ compatible = "brcm,bcm2835-txp";
+ reg = <0x7e004000 0x20>;
+ interrupts = <1 11>;
+ };
+
+...
diff --git a/Bindings/display/brcm,bcm2835-v3d.yaml b/Bindings/display/brcm,bcm2835-v3d.yaml
new file mode 100644
index 000000000000..8a73780f573d
--- /dev/null
+++ b/Bindings/display/brcm,bcm2835-v3d.yaml
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/brcm,bcm2835-v3d.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom VC4 (VideoCore4) V3D GPU
+
+maintainers:
+ - Eric Anholt <eric@anholt.net>
+
+properties:
+ compatible:
+ enum:
+ - brcm,bcm2835-v3d
+ - brcm,cygnus-v3d
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ v3d: v3d@7ec00000 {
+ compatible = "brcm,bcm2835-v3d";
+ reg = <0x7ec00000 0x1000>;
+ interrupts = <1 10>;
+ };
+
+...
diff --git a/Bindings/display/brcm,bcm2835-vc4.yaml b/Bindings/display/brcm,bcm2835-vc4.yaml
new file mode 100644
index 000000000000..0dcf0c397375
--- /dev/null
+++ b/Bindings/display/brcm,bcm2835-vc4.yaml
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/brcm,bcm2835-vc4.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom VC4 (VideoCore4) GPU
+
+maintainers:
+ - Eric Anholt <eric@anholt.net>
+
+description: >
+ The VC4 device present on the Raspberry Pi includes a display system
+ with HDMI output and the HVS (Hardware Video Scaler) for compositing
+ display planes.
+
+properties:
+ compatible:
+ enum:
+ - brcm,bcm2835-vc4
+ - brcm,cygnus-vc4
+
+required:
+ - compatible
+
+additionalProperties: false
+
+examples:
+ - |
+ vc4: gpu {
+ compatible = "brcm,bcm2835-vc4";
+ };
+
+...
diff --git a/Bindings/display/brcm,bcm2835-vec.yaml b/Bindings/display/brcm,bcm2835-vec.yaml
new file mode 100644
index 000000000000..d900cc57b4ec
--- /dev/null
+++ b/Bindings/display/brcm,bcm2835-vec.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/brcm,bcm2835-vec.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom VC4 (VideoCore4) VEC
+
+maintainers:
+ - Eric Anholt <eric@anholt.net>
+
+properties:
+ compatible:
+ const: brcm,bcm2835-vec
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/bcm2835.h>
+
+ vec: vec@7e806000 {
+ compatible = "brcm,bcm2835-vec";
+ reg = <0x7e806000 0x1000>;
+ clocks = <&clocks BCM2835_CLOCK_VEC>;
+ interrupts = <2 27>;
+ };
+
+...
diff --git a/Bindings/display/bridge/nwl-dsi.yaml b/Bindings/display/bridge/nwl-dsi.yaml
index 8aff2d68fc33..04099f5bea3f 100644
--- a/Bindings/display/bridge/nwl-dsi.yaml
+++ b/Bindings/display/bridge/nwl-dsi.yaml
@@ -162,13 +162,13 @@ required:
additionalProperties: false
examples:
- - |
+ - |
+ #include <dt-bindings/clock/imx8mq-clock.h>
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/reset/imx8mq-reset.h>
- #include <dt-bindings/clock/imx8mq-clock.h>
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/reset/imx8mq-reset.h>
-
- mipi_dsi: mipi_dsi@30a00000 {
+ mipi_dsi: mipi_dsi@30a00000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8mq-nwl-dsi";
@@ -191,12 +191,12 @@ examples:
phy-names = "dphy";
panel@0 {
- #address-cells = <1>;
- #size-cells = <0>;
compatible = "rocktech,jh057n00900";
reg = <0>;
- port@0 {
- reg = <0>;
+ vcc-supply = <&reg_2v8_p>;
+ iovcc-supply = <&reg_1v8_p>;
+ reset-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>;
+ port {
panel_in: endpoint {
remote-endpoint = <&mipi_dsi_out>;
};
@@ -223,4 +223,4 @@ examples:
};
};
};
- };
+ };
diff --git a/Bindings/display/bridge/renesas,lvds.yaml b/Bindings/display/bridge/renesas,lvds.yaml
new file mode 100644
index 000000000000..baaf2a2a6fed
--- /dev/null
+++ b/Bindings/display/bridge/renesas,lvds.yaml
@@ -0,0 +1,248 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/renesas,lvds.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas R-Car LVDS Encoder
+
+maintainers:
+ - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+
+description: |
+ These DT bindings describe the LVDS encoder embedded in the Renesas R-Car
+ Gen2, R-Car Gen3, RZ/G1 and RZ/G2 SoCs.
+
+properties:
+ compatible:
+ enum:
+ - renesas,r8a7743-lvds # for RZ/G1M compatible LVDS encoders
+ - renesas,r8a7744-lvds # for RZ/G1N compatible LVDS encoders
+ - renesas,r8a774a1-lvds # for RZ/G2M compatible LVDS encoders
+ - renesas,r8a774b1-lvds # for RZ/G2N compatible LVDS encoders
+ - renesas,r8a774c0-lvds # for RZ/G2E compatible LVDS encoders
+ - renesas,r8a7790-lvds # for R-Car H2 compatible LVDS encoders
+ - renesas,r8a7791-lvds # for R-Car M2-W compatible LVDS encoders
+ - renesas,r8a7793-lvds # for R-Car M2-N compatible LVDS encoders
+ - renesas,r8a7795-lvds # for R-Car H3 compatible LVDS encoders
+ - renesas,r8a7796-lvds # for R-Car M3-W compatible LVDS encoders
+ - renesas,r8a77965-lvds # for R-Car M3-N compatible LVDS encoders
+ - renesas,r8a77970-lvds # for R-Car V3M compatible LVDS encoders
+ - renesas,r8a77980-lvds # for R-Car V3H compatible LVDS encoders
+ - renesas,r8a77990-lvds # for R-Car E3 compatible LVDS encoders
+ - renesas,r8a77995-lvds # for R-Car D3 compatible LVDS encoders
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 4
+
+ clock-names:
+ minItems: 1
+ maxItems: 4
+
+ resets:
+ maxItems: 1
+
+ ports:
+ type: object
+ description: |
+ This device has two video ports. Their connections are modelled using the
+ OF graph bindings specified in Documentation/devicetree/bindings/graph.txt.
+ Each port shall have a single endpoint.
+
+ properties:
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ port@0:
+ type: object
+ description: Parallel RGB input port
+
+ port@1:
+ type: object
+ description: LVDS output port
+
+ required:
+ - port@0
+ - port@1
+
+ additionalProperties: false
+
+ power-domains:
+ maxItems: 1
+
+ renesas,companion:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ phandle to the companion LVDS encoder. This property is mandatory
+ for the first LVDS encoder on D3 and E3 SoCs, and shall point to
+ the second encoder to be used as a companion in dual-link mode. It
+ shall not be set for any other LVDS encoder.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - power-domains
+ - resets
+ - ports
+
+if:
+ properties:
+ compatible:
+ enum:
+ - renesas,r8a774c0-lvds
+ - renesas,r8a77990-lvds
+ - renesas,r8a77995-lvds
+then:
+ properties:
+ clocks:
+ minItems: 1
+ maxItems: 4
+ items:
+ - description: Functional clock
+ - description: EXTAL input clock
+ - description: DU_DOTCLKIN0 input clock
+ - description: DU_DOTCLKIN1 input clock
+
+ clock-names:
+ minItems: 1
+ maxItems: 4
+ items:
+ - const: fck
+ # The LVDS encoder can use the EXTAL or DU_DOTCLKINx clocks.
+ # These clocks are optional.
+ - enum:
+ - extal
+ - dclkin.0
+ - dclkin.1
+ - enum:
+ - extal
+ - dclkin.0
+ - dclkin.1
+ - enum:
+ - extal
+ - dclkin.0
+ - dclkin.1
+
+ required:
+ - clock-names
+
+else:
+ properties:
+ clocks:
+ maxItems: 1
+ items:
+ - description: Functional clock
+
+ clock-names:
+ maxItems: 1
+ items:
+ - const: fck
+
+ renesas,companion: false
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/renesas-cpg-mssr.h>
+ #include <dt-bindings/power/r8a7795-sysc.h>
+
+ lvds@feb90000 {
+ compatible = "renesas,r8a7795-lvds";
+ reg = <0xfeb90000 0x14>;
+ clocks = <&cpg CPG_MOD 727>;
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 727>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ lvds_in: endpoint {
+ remote-endpoint = <&du_out_lvds0>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ lvds_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+ };
+
+ - |
+ #include <dt-bindings/clock/renesas-cpg-mssr.h>
+ #include <dt-bindings/power/r8a77990-sysc.h>
+
+ lvds0: lvds@feb90000 {
+ compatible = "renesas,r8a77990-lvds";
+ reg = <0xfeb90000 0x20>;
+ clocks = <&cpg CPG_MOD 727>,
+ <&x13_clk>,
+ <&extal_clk>;
+ clock-names = "fck", "dclkin.0", "extal";
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 727>;
+
+ renesas,companion = <&lvds1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ lvds0_in: endpoint {
+ remote-endpoint = <&du_out_lvds0>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ lvds0_out: endpoint {
+ remote-endpoint = <&panel_in1>;
+ };
+ };
+ };
+ };
+
+ lvds1: lvds@feb90100 {
+ compatible = "renesas,r8a77990-lvds";
+ reg = <0xfeb90100 0x20>;
+ clocks = <&cpg CPG_MOD 727>,
+ <&x13_clk>,
+ <&extal_clk>;
+ clock-names = "fck", "dclkin.0", "extal";
+ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
+ resets = <&cpg 726>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ lvds1_in: endpoint {
+ remote-endpoint = <&du_out_lvds1>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ lvds1_out: endpoint {
+ remote-endpoint = <&panel_in2>;
+ };
+ };
+ };
+ };
+
+...
diff --git a/Bindings/display/bridge/simple-bridge.yaml b/Bindings/display/bridge/simple-bridge.yaml
index 0880cbf217d5..3ddb35fcf0a2 100644
--- a/Bindings/display/bridge/simple-bridge.yaml
+++ b/Bindings/display/bridge/simple-bridge.yaml
@@ -18,16 +18,16 @@ properties:
compatible:
oneOf:
- items:
- - enum:
- - ti,ths8134a
- - ti,ths8134b
- - const: ti,ths8134
+ - enum:
+ - ti,ths8134a
+ - ti,ths8134b
+ - const: ti,ths8134
- enum:
- - adi,adv7123
- - dumb-vga-dac
- - ti,opa362
- - ti,ths8134
- - ti,ths8135
+ - adi,adv7123
+ - dumb-vga-dac
+ - ti,opa362
+ - ti,ths8134
+ - ti,ths8135
ports:
type: object
diff --git a/Bindings/display/bridge/ti,sn65dsi86.yaml b/Bindings/display/bridge/ti,sn65dsi86.yaml
new file mode 100644
index 000000000000..f8622bd0f61e
--- /dev/null
+++ b/Bindings/display/bridge/ti,sn65dsi86.yaml
@@ -0,0 +1,293 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/ti,sn65dsi86.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SN65DSI86 DSI to eDP bridge chip
+
+maintainers:
+ - Sandeep Panda <spanda@codeaurora.org>
+
+description: |
+ The Texas Instruments SN65DSI86 bridge takes MIPI DSI in and outputs eDP.
+ https://www.ti.com/general/docs/lit/getliterature.tsp?genericPartNumber=sn65dsi86&fileType=pdf
+
+properties:
+ compatible:
+ const: ti,sn65dsi86
+
+ reg:
+ const: 0x2d
+
+ enable-gpios:
+ maxItems: 1
+ description: GPIO specifier for bridge_en pin (active high).
+
+ suspend-gpios:
+ maxItems: 1
+ description: GPIO specifier for GPIO1 pin on bridge (active low).
+
+ no-hpd:
+ type: boolean
+ description:
+ Set if the HPD line on the bridge isn't hooked up to anything or is
+ otherwise unusable.
+
+ vccio-supply:
+ description: A 1.8V supply that powers the digital IOs.
+
+ vpll-supply:
+ description: A 1.8V supply that powers the DisplayPort PLL.
+
+ vcca-supply:
+ description: A 1.2V supply that powers the analog circuits.
+
+ vcc-supply:
+ description: A 1.2V supply that powers the digital core.
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+ description:
+ Clock specifier for input reference clock. The reference clock rate must
+ be 12 MHz, 19.2 MHz, 26 MHz, 27 MHz or 38.4 MHz.
+
+ clock-names:
+ const: refclk
+
+ gpio-controller: true
+ '#gpio-cells':
+ const: 2
+ description:
+ First cell is pin number, second cell is flags. GPIO pin numbers are
+ 1-based to match the datasheet. See ../../gpio/gpio.txt for more
+ information.
+
+ '#pwm-cells':
+ const: 1
+ description: See ../../pwm/pwm.yaml for description of the cell formats.
+
+ ports:
+ type: object
+ additionalProperties: false
+
+ properties:
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ port@0:
+ type: object
+ additionalProperties: false
+
+ description:
+ Video port for MIPI DSI input
+
+ properties:
+ reg:
+ const: 0
+
+ endpoint:
+ type: object
+ additionalProperties: false
+ properties:
+ remote-endpoint: true
+
+ required:
+ - reg
+
+ port@1:
+ type: object
+ additionalProperties: false
+
+ description:
+ Video port for eDP output (panel or connector).
+
+ properties:
+ reg:
+ const: 1
+
+ endpoint:
+ type: object
+ additionalProperties: false
+
+ properties:
+ remote-endpoint: true
+
+ data-lanes:
+ oneOf:
+ - minItems: 1
+ maxItems: 1
+ uniqueItems: true
+ items:
+ enum:
+ - 0
+ - 1
+ description:
+ If you have 1 logical lane the bridge supports routing
+ to either port 0 or port 1. Port 0 is suggested.
+ See ../../media/video-interface.txt for details.
+
+ - minItems: 2
+ maxItems: 2
+ uniqueItems: true
+ items:
+ enum:
+ - 0
+ - 1
+ description:
+ If you have 2 logical lanes the bridge supports
+ reordering but only on physical ports 0 and 1.
+ See ../../media/video-interface.txt for details.
+
+ - minItems: 4
+ maxItems: 4
+ uniqueItems: true
+ items:
+ enum:
+ - 0
+ - 1
+ - 2
+ - 3
+ description:
+ If you have 4 logical lanes the bridge supports
+ reordering in any way.
+ See ../../media/video-interface.txt for details.
+
+ lane-polarities:
+ minItems: 1
+ maxItems: 4
+ items:
+ enum:
+ - 0
+ - 1
+ description: See ../../media/video-interface.txt
+
+ dependencies:
+ lane-polarities: [data-lanes]
+
+ required:
+ - reg
+
+ required:
+ - "#address-cells"
+ - "#size-cells"
+ - port@0
+ - port@1
+
+required:
+ - compatible
+ - reg
+ - enable-gpios
+ - vccio-supply
+ - vpll-supply
+ - vcca-supply
+ - vcc-supply
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bridge@2d {
+ compatible = "ti,sn65dsi86";
+ reg = <0x2d>;
+
+ interrupt-parent = <&tlmm>;
+ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
+
+ enable-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>;
+
+ vpll-supply = <&src_pp1800_s4a>;
+ vccio-supply = <&src_pp1800_s4a>;
+ vcca-supply = <&src_pp1200_l2a>;
+ vcc-supply = <&src_pp1200_l2a>;
+
+ clocks = <&rpmhcc RPMH_LN_BB_CLK2>;
+ clock-names = "refclk";
+
+ no-hpd;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ endpoint {
+ remote-endpoint = <&dsi0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ endpoint {
+ remote-endpoint = <&panel_in_edp>;
+ };
+ };
+ };
+ };
+ };
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bridge@2d {
+ compatible = "ti,sn65dsi86";
+ reg = <0x2d>;
+
+ enable-gpios = <&msmgpio 33 GPIO_ACTIVE_HIGH>;
+ suspend-gpios = <&msmgpio 34 GPIO_ACTIVE_LOW>;
+
+ interrupts-extended = <&gpio3 4 IRQ_TYPE_EDGE_FALLING>;
+
+ vccio-supply = <&pm8916_l17>;
+ vcca-supply = <&pm8916_l6>;
+ vpll-supply = <&pm8916_l17>;
+ vcc-supply = <&pm8916_l6>;
+
+ clock-names = "refclk";
+ clocks = <&input_refclk>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ edp_bridge_in: endpoint {
+ remote-endpoint = <&dsi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ edp_bridge_out: endpoint {
+ data-lanes = <2 1 3 0>;
+ lane-polarities = <0 1 0 1>;
+ remote-endpoint = <&edp_panel_in>;
+ };
+ };
+ };
+ };
+ };
diff --git a/Bindings/display/bridge/ti,tfp410.yaml b/Bindings/display/bridge/ti,tfp410.yaml
new file mode 100644
index 000000000000..605831c1e836
--- /dev/null
+++ b/Bindings/display/bridge/ti,tfp410.yaml
@@ -0,0 +1,131 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/ti,tfp410.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TFP410 DPI to DVI encoder
+
+maintainers:
+ - Tomi Valkeinen <tomi.valkeinen@ti.com>
+ - Jyri Sarha <jsarha@ti.com>
+
+properties:
+ compatible:
+ const: ti,tfp410
+
+ reg:
+ description: I2C address of the device.
+ maxItems: 1
+
+ powerdown-gpios:
+ maxItems: 1
+
+ ti,deskew:
+ description:
+ Data de-skew value in 350ps increments, from 0 to 7, as configured
+ through the DK[3:1] pins. The de-skew multiplier is computed as
+ (DK[3:1] - 4), so it ranges from -4 to 3.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 7
+
+ ports:
+ description:
+ A node containing input and output port nodes with endpoint
+ definitions as documented in
+ Documentation/devicetree/bindings/media/video-interfaces.txt
+ type: object
+
+ properties:
+ port@0:
+ description: DPI input port.
+ type: object
+
+ properties:
+ reg:
+ const: 0
+
+ endpoint:
+ type: object
+
+ properties:
+ pclk-sample:
+ description:
+ Endpoint sampling edge.
+ enum:
+ - 0 # Falling edge
+ - 1 # Rising edge
+ default: 0
+
+ bus-width:
+ description:
+ Endpoint bus width.
+ enum:
+ - 12 # 12 data lines connected and dual-edge mode
+ - 24 # 24 data lines connected and single-edge mode
+ default: 24
+
+ port@1:
+ description: DVI output port.
+ type: object
+
+ properties:
+ reg:
+ const: 1
+
+ endpoint:
+ type: object
+
+ required:
+ - port@0
+ - port@1
+
+required:
+ - compatible
+ - ports
+
+if:
+ required:
+ - reg
+then:
+ properties:
+ ti,deskew: false
+else:
+ required:
+ - ti,deskew
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ tfp410: encoder {
+ compatible = "ti,tfp410";
+ powerdown-gpios = <&twl_gpio 2 GPIO_ACTIVE_LOW>;
+ ti,deskew = <3>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ tfp410_in: endpoint {
+ pclk-sample = <1>;
+ bus-width = <24>;
+ remote-endpoint = <&dpi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ tfp410_out: endpoint {
+ remote-endpoint = <&dvi_connector_in>;
+ };
+ };
+ };
+ };
+
+...
diff --git a/Bindings/display/connector/analog-tv-connector.yaml b/Bindings/display/connector/analog-tv-connector.yaml
new file mode 100644
index 000000000000..eebe88fed999
--- /dev/null
+++ b/Bindings/display/connector/analog-tv-connector.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/connector/analog-tv-connector.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog TV Connector
+
+maintainers:
+ - Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
+
+properties:
+ compatible:
+ enum:
+ - composite-video-connector
+ - svideo-connector
+
+ label: true
+
+ sdtv-standards:
+ description:
+ Limit the supported TV standards on a connector to the given ones. If
+ not specified all TV standards are allowed. Possible TV standards are
+ defined in include/dt-bindings/display/sdtv-standards.h.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ port:
+ description: Connection to controller providing analog TV signals
+
+required:
+ - compatible
+ - port
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/display/sdtv-standards.h>
+
+ connector {
+ compatible = "composite-video-connector";
+ label = "tv";
+ sdtv-standards = <(SDTV_STD_PAL | SDTV_STD_NTSC)>;
+
+ port {
+ tv_connector_in: endpoint {
+ remote-endpoint = <&venc_out>;
+ };
+ };
+ };
+
+...
diff --git a/Bindings/display/connector/dvi-connector.yaml b/Bindings/display/connector/dvi-connector.yaml
new file mode 100644
index 000000000000..71cb9220fa59
--- /dev/null
+++ b/Bindings/display/connector/dvi-connector.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/connector/dvi-connector.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: DVI Connector
+
+maintainers:
+ - Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
+
+properties:
+ compatible:
+ const: dvi-connector
+
+ label: true
+
+ hpd-gpios:
+ description: A GPIO line connected to HPD
+ maxItems: 1
+
+ ddc-i2c-bus:
+ description: phandle link to the I2C controller used for DDC EDID probing
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+ analog:
+ type: boolean
+ description: the connector has DVI analog pins
+
+ digital:
+ type: boolean
+ description: the connector has DVI digital pins
+
+ dual-link:
+ type: boolean
+ description: the connector has pins for DVI dual-link
+
+ port:
+ description: Connection to controller providing DVI signals
+
+required:
+ - compatible
+ - port
+
+anyOf:
+ - required:
+ - analog
+ - required:
+ - digital
+
+additionalProperties: false
+
+examples:
+ - |
+ connector {
+ compatible = "dvi-connector";
+ label = "dvi";
+
+ digital;
+
+ ddc-i2c-bus = <&i2c3>;
+
+ port {
+ dvi_connector_in: endpoint {
+ remote-endpoint = <&tfp410_out>;
+ };
+ };
+ };
+
+...
diff --git a/Bindings/display/connector/hdmi-connector.yaml b/Bindings/display/connector/hdmi-connector.yaml
new file mode 100644
index 000000000000..14d7128af592
--- /dev/null
+++ b/Bindings/display/connector/hdmi-connector.yaml
@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/connector/hdmi-connector.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: HDMI Connector
+
+maintainers:
+ - Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
+
+properties:
+ compatible:
+ const: hdmi-connector
+
+ type:
+ description: The HDMI connector type
+ enum:
+ - a # Standard full size
+ - b # Never deployed?
+ - c # Mini
+ - d # Micro
+ - e # automotive
+
+ label: true
+
+ hpd-gpios:
+ description: A GPIO line connected to HPD
+ maxItems: 1
+
+ ddc-i2c-bus:
+ description: phandle link to the I2C controller used for DDC EDID probing
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+ ddc-en-gpios:
+ description: GPIO signal to enable DDC bus
+ maxItems: 1
+
+ port:
+ description: Connection to controller providing HDMI signals
+
+required:
+ - compatible
+ - port
+ - type
+
+additionalProperties: false
+
+examples:
+ - |
+ connector {
+ compatible = "hdmi-connector";
+ label = "hdmi";
+
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&tpd12s015_out>;
+ };
+ };
+ };
+
+...
diff --git a/Bindings/display/connector/vga-connector.yaml b/Bindings/display/connector/vga-connector.yaml
new file mode 100644
index 000000000000..5782c4bb3252
--- /dev/null
+++ b/Bindings/display/connector/vga-connector.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/connector/vga-connector.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: VGA Connector
+
+maintainers:
+ - Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
+
+properties:
+ compatible:
+ const: vga-connector
+
+ label: true
+
+ ddc-i2c-bus:
+ description: phandle link to the I2C controller used for DDC EDID probing
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+ port:
+ description: Connection to controller providing VGA signals
+
+required:
+ - compatible
+ - port
+
+additionalProperties: false
+
+examples:
+ - |
+ connector {
+ compatible = "vga-connector";
+ label = "vga";
+
+ ddc-i2c-bus = <&i2c3>;
+
+ port {
+ vga_connector_in: endpoint {
+ remote-endpoint = <&adv7123_out>;
+ };
+ };
+ };
+
+...
diff --git a/Bindings/display/dsi-controller.yaml b/Bindings/display/dsi-controller.yaml
index 85b71b1fd28a..a02039e3aca0 100644
--- a/Bindings/display/dsi-controller.yaml
+++ b/Bindings/display/dsi-controller.yaml
@@ -55,11 +55,11 @@ patternProperties:
clock-master:
type: boolean
description:
- Should be enabled if the host is being used in conjunction with
- another DSI host to drive the same peripheral. Hardware supporting
- such a configuration generally requires the data on both the busses
- to be driven by the same clock. Only the DSI host instance
- controlling this clock should contain this property.
+ Should be enabled if the host is being used in conjunction with
+ another DSI host to drive the same peripheral. Hardware supporting
+ such a configuration generally requires the data on both the busses
+ to be driven by the same clock. Only the DSI host instance
+ controlling this clock should contain this property.
enforce-video-mode:
type: boolean
diff --git a/Bindings/display/ilitek,ili9486.yaml b/Bindings/display/ilitek,ili9486.yaml
index 66e93e563653..aecff34f505d 100644
--- a/Bindings/display/ilitek,ili9486.yaml
+++ b/Bindings/display/ilitek,ili9486.yaml
@@ -21,9 +21,9 @@ properties:
items:
- enum:
# Waveshare 3.5" 320x480 Color TFT LCD
- - waveshare,rpi-lcd-35
+ - waveshare,rpi-lcd-35
# Ozzmaker 3.5" 320x480 Color TFT LCD
- - ozzmaker,piscreen
+ - ozzmaker,piscreen
- const: ilitek,ili9486
spi-max-frequency:
diff --git a/Bindings/display/ingenic,ipu.yaml b/Bindings/display/ingenic,ipu.yaml
new file mode 100644
index 000000000000..12064a8e7a92
--- /dev/null
+++ b/Bindings/display/ingenic,ipu.yaml
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/ingenic,ipu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Ingenic SoCs Image Processing Unit (IPU) devicetree bindings
+
+maintainers:
+ - Paul Cercueil <paul@crapouillou.net>
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - ingenic,jz4725b-ipu
+ - ingenic,jz4760-ipu
+ - items:
+ - const: ingenic,jz4770-ipu
+ - const: ingenic,jz4760-ipu
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: ipu
+
+patternProperties:
+ "^ports?$":
+ description: OF graph bindings (specified in bindings/graph.txt).
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/jz4770-cgu.h>
+ ipu@13080000 {
+ compatible = "ingenic,jz4770-ipu", "ingenic,jz4760-ipu";
+ reg = <0x13080000 0x800>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <29>;
+
+ clocks = <&cgu JZ4770_CLK_IPU>;
+ clock-names = "ipu";
+
+ port {
+ ipu_ep: endpoint {
+ remote-endpoint = <&lcdc_ep>;
+ };
+ };
+ };
diff --git a/Bindings/display/ingenic,lcd.yaml b/Bindings/display/ingenic,lcd.yaml
new file mode 100644
index 000000000000..768050f30dba
--- /dev/null
+++ b/Bindings/display/ingenic,lcd.yaml
@@ -0,0 +1,126 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/ingenic,lcd.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Ingenic SoCs LCD controller devicetree bindings
+
+maintainers:
+ - Paul Cercueil <paul@crapouillou.net>
+
+properties:
+ $nodename:
+ pattern: "^lcd-controller@[0-9a-f]+$"
+
+ compatible:
+ enum:
+ - ingenic,jz4740-lcd
+ - ingenic,jz4725b-lcd
+ - ingenic,jz4770-lcd
+ - ingenic,jz4780-lcd
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Pixel clock
+ - description: Module clock
+ minItems: 1
+
+ clock-names:
+ items:
+ - const: lcd_pclk
+ - const: lcd
+ minItems: 1
+
+ port:
+ description: OF graph bindings (specified in bindings/graph.txt).
+
+ ports:
+ description: OF graph bindings (specified in bindings/graph.txt).
+ type: object
+ properties:
+ port@0:
+ type: object
+ description: DPI output, to interface with TFT panels.
+
+ port@8:
+ type: object
+ description: Link to the Image Processing Unit (IPU).
+ (See ingenic,ipu.yaml).
+
+ required:
+ - port@0
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - ingenic,jz4740-lcd
+ - ingenic,jz4780-lcd
+then:
+ properties:
+ clocks:
+ minItems: 2
+ clock-names:
+ minItems: 2
+else:
+ properties:
+ clocks:
+ maxItems: 1
+ clock-names:
+ maxItems: 1
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/jz4740-cgu.h>
+ lcd-controller@13050000 {
+ compatible = "ingenic,jz4740-lcd";
+ reg = <0x13050000 0x1000>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <30>;
+
+ clocks = <&cgu JZ4740_CLK_LCD_PCLK>, <&cgu JZ4740_CLK_LCD>;
+ clock-names = "lcd_pclk", "lcd";
+
+ port {
+ endpoint {
+ remote-endpoint = <&panel_input>;
+ };
+ };
+ };
+
+ - |
+ #include <dt-bindings/clock/jz4725b-cgu.h>
+ lcd-controller@13050000 {
+ compatible = "ingenic,jz4725b-lcd";
+ reg = <0x13050000 0x1000>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <31>;
+
+ clocks = <&cgu JZ4725B_CLK_LCD>;
+ clock-names = "lcd_pclk";
+
+ port {
+ endpoint {
+ remote-endpoint = <&panel_input>;
+ };
+ };
+ };
diff --git a/Bindings/display/msm/dsi.txt b/Bindings/display/msm/dsi.txt
index af95586c898f..7884fd7a85c1 100644
--- a/Bindings/display/msm/dsi.txt
+++ b/Bindings/display/msm/dsi.txt
@@ -87,6 +87,7 @@ Required properties:
* "qcom,dsi-phy-20nm"
* "qcom,dsi-phy-28nm-8960"
* "qcom,dsi-phy-14nm"
+ * "qcom,dsi-phy-14nm-660"
* "qcom,dsi-phy-10nm"
* "qcom,dsi-phy-10nm-8998"
- reg: Physical base address and length of the registers of PLL, PHY. Some
diff --git a/Bindings/display/msm/gmu.yaml b/Bindings/display/msm/gmu.yaml
index 0b8736a9384e..53056dd02597 100644
--- a/Bindings/display/msm/gmu.yaml
+++ b/Bindings/display/msm/gmu.yaml
@@ -38,10 +38,10 @@ properties:
clocks:
items:
- - description: GMU clock
- - description: GPU CX clock
- - description: GPU AXI clock
- - description: GPU MEMNOC clock
+ - description: GMU clock
+ - description: GPU CX clock
+ - description: GPU AXI clock
+ - description: GPU MEMNOC clock
clock-names:
items:
@@ -52,8 +52,8 @@ properties:
interrupts:
items:
- - description: GMU HFI interrupt
- - description: GMU interrupt
+ - description: GMU HFI interrupt
+ - description: GMU interrupt
interrupt-names:
@@ -62,14 +62,14 @@ properties:
- const: gmu
power-domains:
- items:
- - description: CX power domain
- - description: GX power domain
+ items:
+ - description: CX power domain
+ - description: GX power domain
power-domain-names:
- items:
- - const: cx
- - const: gx
+ items:
+ - const: cx
+ - const: gx
iommus:
maxItems: 1
@@ -90,13 +90,13 @@ required:
- operating-points-v2
examples:
- - |
- #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
- #include <dt-bindings/clock/qcom,gcc-sdm845.h>
- #include <dt-bindings/interrupt-controller/irq.h>
- #include <dt-bindings/interrupt-controller/arm-gic.h>
+ - |
+ #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
+ #include <dt-bindings/clock/qcom,gcc-sdm845.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
- gmu: gmu@506a000 {
+ gmu: gmu@506a000 {
compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
reg = <0x506a000 0x30000>,
@@ -120,4 +120,4 @@ examples:
iommus = <&adreno_smmu 5>;
operating-points-v2 = <&gmu_opp_table>;
- };
+ };
diff --git a/Bindings/display/msm/gpu.txt b/Bindings/display/msm/gpu.txt
index fd779cd6994d..1af0ff102b50 100644
--- a/Bindings/display/msm/gpu.txt
+++ b/Bindings/display/msm/gpu.txt
@@ -112,6 +112,34 @@ Example a6xx (with GMU):
interconnects = <&rsc_hlos MASTER_GFX3D &rsc_hlos SLAVE_EBI1>;
interconnect-names = "gfx-mem";
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-430000000 {
+ opp-hz = /bits/ 64 <430000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ opp-peak-kBps = <5412000>;
+ };
+
+ opp-355000000 {
+ opp-hz = /bits/ 64 <355000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ opp-peak-kBps = <3072000>;
+ };
+
+ opp-267000000 {
+ opp-hz = /bits/ 64 <267000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ opp-peak-kBps = <3072000>;
+ };
+
+ opp-180000000 {
+ opp-hz = /bits/ 64 <180000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+ opp-peak-kBps = <1804000>;
+ };
+ };
+
qcom,gmu = <&gmu>;
zap-shader {
diff --git a/Bindings/display/panel/asus,z00t-tm5p5-nt35596.yaml b/Bindings/display/panel/asus,z00t-tm5p5-nt35596.yaml
index 083d2b9d0c69..75a09df68ba0 100644
--- a/Bindings/display/panel/asus,z00t-tm5p5-nt35596.yaml
+++ b/Bindings/display/panel/asus,z00t-tm5p5-nt35596.yaml
@@ -24,9 +24,9 @@ properties:
reg: true
reset-gpios: true
vdd-supply:
- description: core voltage supply
+ description: core voltage supply
vddio-supply:
- description: vddio supply
+ description: vddio supply
required:
- compatible
diff --git a/Bindings/display/panel/boe,tv101wum-nl6.yaml b/Bindings/display/panel/boe,tv101wum-nl6.yaml
index 7f5df5851017..38bc1d1b511e 100644
--- a/Bindings/display/panel/boe,tv101wum-nl6.yaml
+++ b/Bindings/display/panel/boe,tv101wum-nl6.yaml
@@ -48,12 +48,12 @@ properties:
port: true
required:
- - compatible
- - reg
- - enable-gpios
- - pp1800-supply
- - avdd-supply
- - avee-supply
+ - compatible
+ - reg
+ - enable-gpios
+ - pp1800-supply
+ - avdd-supply
+ - avee-supply
additionalProperties: false
diff --git a/Bindings/display/panel/elida,kd35t133.yaml b/Bindings/display/panel/elida,kd35t133.yaml
index aa761f697b7a..7adb83e2e8d9 100644
--- a/Bindings/display/panel/elida,kd35t133.yaml
+++ b/Bindings/display/panel/elida,kd35t133.yaml
@@ -19,9 +19,9 @@ properties:
backlight: true
reset-gpios: true
iovcc-supply:
- description: regulator that supplies the iovcc voltage
+ description: regulator that supplies the iovcc voltage
vdd-supply:
- description: regulator that supplies the vdd voltage
+ description: regulator that supplies the vdd voltage
required:
- compatible
diff --git a/Bindings/display/panel/feixin,k101-im2ba02.yaml b/Bindings/display/panel/feixin,k101-im2ba02.yaml
index 927f1eea18d2..81adb82f061d 100644
--- a/Bindings/display/panel/feixin,k101-im2ba02.yaml
+++ b/Bindings/display/panel/feixin,k101-im2ba02.yaml
@@ -19,11 +19,11 @@ properties:
backlight: true
reset-gpios: true
avdd-supply:
- description: regulator that supplies the AVDD voltage
+ description: regulator that supplies the AVDD voltage
dvdd-supply:
- description: regulator that supplies the DVDD voltage
+ description: regulator that supplies the DVDD voltage
cvdd-supply:
- description: regulator that supplies the CVDD voltage
+ description: regulator that supplies the CVDD voltage
required:
- compatible
diff --git a/Bindings/display/panel/ilitek,ili9322.yaml b/Bindings/display/panel/ilitek,ili9322.yaml
index 177d48c5bd97..e89c1ea62ffa 100644
--- a/Bindings/display/panel/ilitek,ili9322.yaml
+++ b/Bindings/display/panel/ilitek,ili9322.yaml
@@ -25,8 +25,7 @@ properties:
compatible:
items:
- enum:
- - dlink,dir-685-panel
-
+ - dlink,dir-685-panel
- const: ilitek,ili9322
reset-gpios: true
diff --git a/Bindings/display/panel/ilitek,ili9881c.yaml b/Bindings/display/panel/ilitek,ili9881c.yaml
index a39332276bab..76a9068a85dd 100644
--- a/Bindings/display/panel/ilitek,ili9881c.yaml
+++ b/Bindings/display/panel/ilitek,ili9881c.yaml
@@ -13,8 +13,7 @@ properties:
compatible:
items:
- enum:
- - bananapi,lhr050h41
-
+ - bananapi,lhr050h41
- const: ilitek,ili9881c
backlight: true
diff --git a/Bindings/display/panel/leadtek,ltk050h3146w.yaml b/Bindings/display/panel/leadtek,ltk050h3146w.yaml
index a372bdc5bde1..3715882b63b6 100644
--- a/Bindings/display/panel/leadtek,ltk050h3146w.yaml
+++ b/Bindings/display/panel/leadtek,ltk050h3146w.yaml
@@ -21,9 +21,9 @@ properties:
backlight: true
reset-gpios: true
iovcc-supply:
- description: regulator that supplies the iovcc voltage
+ description: regulator that supplies the iovcc voltage
vci-supply:
- description: regulator that supplies the vci voltage
+ description: regulator that supplies the vci voltage
required:
- compatible
diff --git a/Bindings/display/panel/leadtek,ltk500hd1829.yaml b/Bindings/display/panel/leadtek,ltk500hd1829.yaml
index b900973b5f7b..c5944b4d636c 100644
--- a/Bindings/display/panel/leadtek,ltk500hd1829.yaml
+++ b/Bindings/display/panel/leadtek,ltk500hd1829.yaml
@@ -19,9 +19,9 @@ properties:
backlight: true
reset-gpios: true
iovcc-supply:
- description: regulator that supplies the iovcc voltage
+ description: regulator that supplies the iovcc voltage
vcc-supply:
- description: regulator that supplies the vcc voltage
+ description: regulator that supplies the vcc voltage
required:
- compatible
diff --git a/Bindings/display/panel/novatek,nt35510.yaml b/Bindings/display/panel/novatek,nt35510.yaml
index 73d2ff3baaff..bc92928c805b 100644
--- a/Bindings/display/panel/novatek,nt35510.yaml
+++ b/Bindings/display/panel/novatek,nt35510.yaml
@@ -25,9 +25,9 @@ properties:
reg: true
reset-gpios: true
vdd-supply:
- description: regulator that supplies the vdd voltage
+ description: regulator that supplies the vdd voltage
vddi-supply:
- description: regulator that supplies the vddi voltage
+ description: regulator that supplies the vddi voltage
backlight: true
required:
diff --git a/Bindings/display/panel/panel-dsi-cm.yaml b/Bindings/display/panel/panel-dsi-cm.yaml
new file mode 100644
index 000000000000..4a36aa64c716
--- /dev/null
+++ b/Bindings/display/panel/panel-dsi-cm.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/panel-dsi-cm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: DSI command mode panels
+
+maintainers:
+ - Tomi Valkeinen <tomi.valkeinen@ti.com>
+ - Sebastian Reichel <sre@kernel.org>
+
+description: |
+ This binding file is a collection of the DSI panels that
+ are usually driven in command mode. If no backlight is
+ referenced via the optional backlight property, the DSI
+ panel is assumed to have native backlight support.
+ The panel may use an OF graph binding for the association
+ to the display, or it may be a direct child node of the
+ display.
+
+allOf:
+ - $ref: panel-common.yaml#
+
+properties:
+
+ compatible:
+ items:
+ - enum:
+ - motorola,droid4-panel # Panel from Motorola Droid4 phone
+ - nokia,himalaya # Panel from Nokia N950 phone
+ - tpo,taal # Panel from OMAP4 SDP board
+ - const: panel-dsi-cm # Generic DSI command mode panel compatible fallback
+
+ reg:
+ maxItems: 1
+ description: DSI virtual channel
+
+ vddi-supply:
+ description:
+ Display panels require power to be supplied. While several panels need
+ more than one power supply with panel-specific constraints governing the
+ order and timings of the power supplies, in many cases a single power
+ supply is sufficient, either because the panel has a single power rail, or
+ because all its power rails can be driven by the same supply. In that case
+ the vddi-supply property specifies the supply powering the panel as a
+ phandle to a regulator.
+
+ vpnl-supply:
+ description:
+ When the display panel needs a second power supply, this property can be
+ used in addition to vddi-supply. Both supplies will be enabled at the
+ same time before the panel is being accessed.
+
+ width-mm: true
+ height-mm: true
+ label: true
+ rotation: true
+ panel-timing: true
+ port: true
+ reset-gpios: true
+ te-gpios: true
+ backlight: true
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ dsi-controller {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ panel@0 {
+ compatible = "tpo,taal", "panel-dsi-cm";
+ reg = <0>;
+ reset-gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+...
diff --git a/Bindings/display/panel/panel-simple-dsi.yaml b/Bindings/display/panel/panel-simple-dsi.yaml
index 16778ce782fc..c0dd9fa29f1d 100644
--- a/Bindings/display/panel/panel-simple-dsi.yaml
+++ b/Bindings/display/panel/panel-simple-dsi.yaml
@@ -33,6 +33,8 @@ properties:
- auo,b080uan01
# Boe Corporation 8.0" WUXGA TFT LCD panel
- boe,tv080wum-nl0
+ # Innolux P079ZCA 7.85" 768x1024 TFT LCD panel
+ - innolux,p079zca
# Kingdisplay KD097D04 9.7" 1536x2048 TFT LCD panel
- kingdisplay,kd097d04
# LG ACX467AKM-7 4.95" 1080×1920 LCD Panel
diff --git a/Bindings/display/panel/panel-simple.yaml b/Bindings/display/panel/panel-simple.yaml
index d6cca1479633..6deeeed59e59 100644
--- a/Bindings/display/panel/panel-simple.yaml
+++ b/Bindings/display/panel/panel-simple.yaml
@@ -81,6 +81,10 @@ properties:
- boe,nv140fhmn49
# CDTech(H.K.) Electronics Limited 4.3" 480x272 color TFT-LCD panel
- cdtech,s043wq26h-ct7
+ # CDTech(H.K.) Electronics Limited 7" WSVGA (1024x600) TFT LCD Panel
+ - cdtech,s070pws19hp-fc21
+ # CDTech(H.K.) Electronics Limited 7" WVGA (800x480) TFT LCD Panel
+ - cdtech,s070swv29hg-dc44
# CDTech(H.K.) Electronics Limited 7" 800x480 color TFT-LCD panel
- cdtech,s070wv95-ct16
# Chunghwa Picture Tubes Ltd. 7" WXGA TFT LCD panel
@@ -157,6 +161,8 @@ properties:
- innolux,zj070na-01p
# Kaohsiung Opto-Electronics Inc. 5.7" QVGA (320 x 240) TFT LCD panel
- koe,tx14d24vm1bpa
+ # Kaohsiung Opto-Electronics Inc. 10.1" WUXGA (1920 x 1200) LVDS TFT LCD panel
+ - koe,tx26d202vm0bwa
# Kaohsiung Opto-Electronics. TX31D200VM0BAA 12.3" HSXGA LVDS panel
- koe,tx31d200vm0baa
# Kyocera Corporation 12.1" XGA (1024x768) TFT LCD panel
@@ -245,6 +251,8 @@ properties:
- starry,kr122ea0sra
# Tianma Micro-electronics TM070JDHG30 7.0" WXGA TFT LCD panel
- tianma,tm070jdhg30
+ # Tianma Micro-electronics TM070JVHG33 7.0" WXGA TFT LCD panel
+ - tianma,tm070jvhg33
# Tianma Micro-electronics TM070RVHG71 7.0" WXGA TFT LCD panel
- tianma,tm070rvhg71
# Toshiba 8.9" WXGA (1280x768) TFT LCD panel
diff --git a/Bindings/display/panel/panel-timing.yaml b/Bindings/display/panel/panel-timing.yaml
index 182c19cb7fdd..9bf592dc3033 100644
--- a/Bindings/display/panel/panel-timing.yaml
+++ b/Bindings/display/panel/panel-timing.yaml
@@ -59,7 +59,7 @@ description: |
properties:
clock-frequency:
- description: Panel clock in Hz
+ description: Panel clock in Hz
hactive:
$ref: /schemas/types.yaml#/definitions/uint32
@@ -200,15 +200,15 @@ properties:
description: Enable double clock mode
required:
- - clock-frequency
- - hactive
- - vactive
- - hfront-porch
- - hback-porch
- - hsync-len
- - vfront-porch
- - vback-porch
- - vsync-len
+ - clock-frequency
+ - hactive
+ - vactive
+ - hfront-porch
+ - hback-porch
+ - hsync-len
+ - vfront-porch
+ - vback-porch
+ - vsync-len
additionalProperties: false
diff --git a/Bindings/display/panel/raydium,rm68200.yaml b/Bindings/display/panel/raydium,rm68200.yaml
index a35ba16fc000..39477793d289 100644
--- a/Bindings/display/panel/raydium,rm68200.yaml
+++ b/Bindings/display/panel/raydium,rm68200.yaml
@@ -10,8 +10,8 @@ maintainers:
- Philippe CORNU <philippe.cornu@st.com>
description: |
- The Raydium Semiconductor Corporation RM68200 is a 5.5" 720x1280 TFT LCD
- panel connected using a MIPI-DSI video interface.
+ The Raydium Semiconductor Corporation RM68200 is a 5.5" 720x1280 TFT LCD
+ panel connected using a MIPI-DSI video interface.
allOf:
- $ref: panel-common.yaml#
diff --git a/Bindings/display/panel/rocktech,jh057n00900.yaml b/Bindings/display/panel/rocktech,jh057n00900.yaml
new file mode 100644
index 000000000000..d5733ef30954
--- /dev/null
+++ b/Bindings/display/panel/rocktech,jh057n00900.yaml
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/rocktech,jh057n00900.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rocktech JH057N00900 5.5" 720x1440 TFT LCD panel
+
+maintainers:
+ - Ondrej Jirman <megi@xff.cz>
+
+description: |
+ Rocktech JH057N00900 is a 720x1440 TFT LCD panel
+ connected using a MIPI-DSI video interface.
+
+allOf:
+ - $ref: panel-common.yaml#
+
+properties:
+ compatible:
+ enum:
+ # Rocktech JH057N00900 5.5" 720x1440 TFT LCD panel
+ - rocktech,jh057n00900
+ # Xingbangda XBD599 5.99" 720x1440 TFT LCD panel
+ - xingbangda,xbd599
+
+ port: true
+ reg:
+ maxItems: 1
+ description: DSI virtual channel
+
+ vcc-supply:
+ description: Panel power supply
+
+ iovcc-supply:
+ description: I/O voltage supply
+
+ reset-gpios:
+ description: GPIO used for the reset pin
+ maxItems: 1
+
+ backlight:
+ description: Backlight used by the panel
+ $ref: "/schemas/types.yaml#/definitions/phandle"
+
+required:
+ - compatible
+ - reg
+ - vcc-supply
+ - iovcc-supply
+ - reset-gpios
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ panel@0 {
+ compatible = "rocktech,jh057n00900";
+ reg = <0>;
+ vcc-supply = <&reg_2v8_p>;
+ iovcc-supply = <&reg_1v8_p>;
+ reset-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>;
+ backlight = <&backlight>;
+ };
+ };
+...
diff --git a/Bindings/display/panel/samsung,s6e88a0-ams452ef01.yaml b/Bindings/display/panel/samsung,s6e88a0-ams452ef01.yaml
index 7a685d0428b3..44ce98f68705 100644
--- a/Bindings/display/panel/samsung,s6e88a0-ams452ef01.yaml
+++ b/Bindings/display/panel/samsung,s6e88a0-ams452ef01.yaml
@@ -18,9 +18,9 @@ properties:
reg: true
reset-gpios: true
vdd3-supply:
- description: core voltage supply
+ description: core voltage supply
vci-supply:
- description: voltage supply for analog circuits
+ description: voltage supply for analog circuits
required:
- compatible
diff --git a/Bindings/display/panel/samsung,s6e8aa0.yaml b/Bindings/display/panel/samsung,s6e8aa0.yaml
new file mode 100644
index 000000000000..ca959451557e
--- /dev/null
+++ b/Bindings/display/panel/samsung,s6e8aa0.yaml
@@ -0,0 +1,100 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/samsung,s6e8aa0.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung S6E8AA0 AMOLED LCD 5.3 inch panel
+
+maintainers:
+ - Andrzej Hajda <a.hajda@samsung.com>
+
+allOf:
+ - $ref: panel-common.yaml#
+
+properties:
+ compatible:
+ const: samsung,s6e8aa0
+
+ reg: true
+ reset-gpios: true
+ display-timings: true
+
+ vdd3-supply:
+ description: core voltage supply
+
+ vci-supply:
+ description: voltage supply for analog circuits
+
+ power-on-delay:
+ description: delay after turning regulators on [ms]
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ reset-delay:
+ description: delay after reset sequence [ms]
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ init-delay:
+ description: delay after initialization sequence [ms]
+
+ panel-width-mm:
+ description: physical panel width [mm]
+
+ panel-height-mm:
+ description: physical panel height [mm]
+
+ flip-horizontal:
+ description: boolean to flip image horizontally
+ type: boolean
+
+ flip-vertical:
+ description: boolean to flip image vertically
+ type: boolean
+
+required:
+ - compatible
+ - reg
+ - vdd3-supply
+ - vci-supply
+ - reset-gpios
+ - display-timings
+
+additionalProperties: false
+
+examples:
+ - |
+ dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ panel@0 {
+ compatible = "samsung,s6e8aa0";
+ reg = <0>;
+ vdd3-supply = <&vcclcd_reg>;
+ vci-supply = <&vlcd_reg>;
+ reset-gpios = <&gpy4 5 0>;
+ power-on-delay= <50>;
+ reset-delay = <100>;
+ init-delay = <100>;
+ panel-width-mm = <58>;
+ panel-height-mm = <103>;
+ flip-horizontal;
+ flip-vertical;
+
+ display-timings {
+ timing0: timing-0 {
+ clock-frequency = <57153600>;
+ hactive = <720>;
+ vactive = <1280>;
+ hfront-porch = <5>;
+ hback-porch = <5>;
+ hsync-len = <5>;
+ vfront-porch = <13>;
+ vback-porch = <1>;
+ vsync-len = <2>;
+ };
+ };
+ };
+ };
+
+...
diff --git a/Bindings/display/panel/sharp,lq101r1sx01.yaml b/Bindings/display/panel/sharp,lq101r1sx01.yaml
new file mode 100644
index 000000000000..a679d3647dbd
--- /dev/null
+++ b/Bindings/display/panel/sharp,lq101r1sx01.yaml
@@ -0,0 +1,87 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/sharp,lq101r1sx01.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sharp Microelectronics 10.1" WQXGA TFT LCD panel
+
+maintainers:
+ - Thierry Reding <treding@nvidia.com>
+
+description: |
+ This panel requires a dual-channel DSI host to operate. It supports two modes:
+ - left-right: each channel drives the left or right half of the screen
+ - even-odd: each channel drives the even or odd lines of the screen
+
+ Each of the DSI channels controls a separate DSI peripheral. The peripheral
+ driven by the first link (DSI-LINK1), left or even, is considered the primary
+ peripheral and controls the device. The 'link2' property contains a phandle
+ to the peripheral driven by the second link (DSI-LINK2, right or odd).
+
+ Note that in video mode the DSI-LINK1 interface always provides the left/even
+ pixels and DSI-LINK2 always provides the right/odd pixels. In command mode it
+ is possible to program either link to drive the left/even or right/odd pixels
+ but for the sake of consistency this binding assumes that the same assignment
+ is chosen as for video mode.
+
+allOf:
+ - $ref: panel-common.yaml#
+
+properties:
+ compatible:
+ const: sharp,lq101r1sx01
+
+ reg: true
+ power-supply: true
+ backlight: true
+
+ link2:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: |
+ phandle to the DSI peripheral on the secondary link. Note that the
+ presence of this property marks the containing node as DSI-LINK1
+
+required:
+ - compatible
+ - reg
+
+if:
+ required:
+ - link2
+then:
+ required:
+ - power-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ dsi0: dsi@fd922800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xfd922800 0x200>;
+
+ panel: panel@0 {
+ compatible = "sharp,lq101r1sx01";
+ reg = <0>;
+
+ link2 = <&secondary>;
+
+ power-supply = <&power>;
+ backlight = <&backlight>;
+ };
+ };
+
+ dsi1: dsi@fd922a00 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xfd922a00 0x200>;
+
+ secondary: panel@0 {
+ compatible = "sharp,lq101r1sx01";
+ reg = <0>;
+ };
+ };
+
+...
diff --git a/Bindings/display/panel/visionox,rm69299.yaml b/Bindings/display/panel/visionox,rm69299.yaml
index b36f39f6b233..076b057b4af5 100644
--- a/Bindings/display/panel/visionox,rm69299.yaml
+++ b/Bindings/display/panel/visionox,rm69299.yaml
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Visionox model RM69299 Panels Device Tree Bindings.
maintainers:
- - Harigovindan P <harigovi@codeaurora.org>
+ - Harigovindan P <harigovi@codeaurora.org>
description: |
This binding is for display panels using a Visionox RM692999 panel.
diff --git a/Bindings/display/simple-framebuffer.yaml b/Bindings/display/simple-framebuffer.yaml
index 1db608c9eef5..eaf8c54fcf50 100644
--- a/Bindings/display/simple-framebuffer.yaml
+++ b/Bindings/display/simple-framebuffer.yaml
@@ -152,28 +152,28 @@ additionalProperties: false
examples:
- |
- aliases {
- display0 = &lcdc0;
+ / {
+ compatible = "foo";
+ model = "foo";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ chosen {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ framebuffer0: framebuffer@1d385000 {
+ compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
+ allwinner,pipeline = "de_be0-lcd0";
+ reg = <0x1d385000 3840000>;
+ width = <1600>;
+ height = <1200>;
+ stride = <3200>;
+ format = "r5g6b5";
+ clocks = <&ahb_gates 36>, <&ahb_gates 43>, <&ahb_gates 44>;
+ lcd-supply = <&reg_dc1sw>;
+ display = <&lcdc0>;
+ };
+ };
};
- chosen {
- #address-cells = <1>;
- #size-cells = <1>;
- stdout-path = "display0";
- framebuffer0: framebuffer@1d385000 {
- compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
- allwinner,pipeline = "de_be0-lcd0";
- reg = <0x1d385000 3840000>;
- width = <1600>;
- height = <1200>;
- stride = <3200>;
- format = "r5g6b5";
- clocks = <&ahb_gates 36>, <&ahb_gates 43>, <&ahb_gates 44>;
- lcd-supply = <&reg_dc1sw>;
- display = <&lcdc0>;
- };
- };
-
- lcdc0: lcdc { };
-
...
diff --git a/Bindings/display/st,stm32-dsi.yaml b/Bindings/display/st,stm32-dsi.yaml
index 3be76d15bf6c..69cc7e8bf15a 100644
--- a/Bindings/display/st,stm32-dsi.yaml
+++ b/Bindings/display/st,stm32-dsi.yaml
@@ -45,7 +45,7 @@ properties:
phy-dsi-supply:
description:
- Phandle of the regulator that provides the supply voltage.
+ Phandle of the regulator that provides the supply voltage.
ports:
type: object
@@ -147,4 +147,3 @@ examples:
...
-
diff --git a/Bindings/display/ti/ti,j721e-dss.yaml b/Bindings/display/ti/ti,j721e-dss.yaml
index bbd76591c180..173730d56334 100644
--- a/Bindings/display/ti/ti,j721e-dss.yaml
+++ b/Bindings/display/ti/ti,j721e-dss.yaml
@@ -78,7 +78,7 @@ properties:
- const: vp4
interrupts:
- items:
+ items:
- description: common_m DSS Master common
- description: common_s0 DSS Shared common 0
- description: common_s1 DSS Shared common 1
diff --git a/Bindings/display/tilcdc/tilcdc.txt b/Bindings/display/tilcdc/tilcdc.txt
index aac617acb64f..8b2a71395647 100644
--- a/Bindings/display/tilcdc/tilcdc.txt
+++ b/Bindings/display/tilcdc/tilcdc.txt
@@ -46,7 +46,7 @@ Optional nodes:
crossed and LCD_DATA[0:4] is for Red[3:7] and LCD_DATA[11:15] is
for Blue[3-7]. For more details see section 3.1.1 in AM335x
Silicon Errata:
- http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=sprz360
+ https://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=sprz360
Example:
diff --git a/Bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml b/Bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml
new file mode 100644
index 000000000000..7b9d468c3e52
--- /dev/null
+++ b/Bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml
@@ -0,0 +1,174 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/xlnx/xlnx,zynqmp-dpsub.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx ZynqMP DisplayPort Subsystem
+
+description: |
+ The DisplayPort subsystem of Xilinx ZynqMP (Zynq UltraScale+ MPSoC)
+ implements the display and audio pipelines based on the DisplayPort v1.2
+ standard. The subsystem includes multiple functional blocks as below:
+
+ +------------------------------------------------------------+
+ +--------+ | +----------------+ +-----------+ |
+ | DPDMA | --->| | --> | Video | Video +-------------+ |
+ | 4x vid | | | | | Rendering | -+--> | | | +------+
+ | 2x aud | | | Audio/Video | --> | Pipeline | | | DisplayPort |---> | PHY0 |
+ +--------+ | | Buffer Manager | +-----------+ | | Source | | +------+
+ | | and STC | +-----------+ | | Controller | | +------+
+ Live Video --->| | --> | Audio | Audio | |---> | PHY1 |
+ | | | | Mixer | --+-> | | | +------+
+ Live Audio --->| | --> | | || +-------------+ |
+ | +----------------+ +-----------+ || |
+ +---------------------------------------||-------------------+
+ vv
+ Blended Video and
+ Mixed Audio to PL
+
+ The Buffer Manager interacts with external interface such as DMA engines or
+ live audio/video streams from the programmable logic. The Video Rendering
+ Pipeline blends the video and graphics layers and performs colorspace
+ conversion. The Audio Mixer mixes the incoming audio streams. The DisplayPort
+ Source Controller handles the DisplayPort protocol and connects to external
+ PHYs.
+
+ The subsystem supports 2 video and 2 audio streams, and various pixel formats
+ and depths up to 4K@30 resolution.
+
+ Please refer to "Zynq UltraScale+ Device Technical Reference Manual"
+ (https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf)
+ for more details.
+
+maintainers:
+ - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+
+properties:
+ compatible:
+ const: xlnx,zynqmp-dpsub-1.7
+
+ reg:
+ maxItems: 4
+ reg-names:
+ items:
+ - const: dp
+ - const: blend
+ - const: av_buf
+ - const: aud
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ description:
+ The APB clock and at least one video clock are mandatory, the audio clock
+ is optional.
+ minItems: 2
+ maxItems: 4
+ items:
+ - description: dp_apb_clk is the APB clock
+ - description: dp_aud_clk is the Audio clock
+ - description:
+ dp_vtc_pixel_clk_in is the non-live video clock (from Processing
+ System)
+ - description:
+ dp_live_video_in_clk is the live video clock (from Programmable
+ Logic)
+ clock-names:
+ oneOf:
+ - minItems: 2
+ maxItems: 3
+ items:
+ - const: dp_apb_clk
+ - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]
+ - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]
+ - minItems: 3
+ maxItems: 4
+ items:
+ - const: dp_apb_clk
+ - const: dp_aud_clk
+ - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]
+ - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ dmas:
+ maxItems: 4
+ items:
+ - description: Video layer, plane 0 (RGB or luma)
+ - description: Video layer, plane 1 (U/V or U)
+ - description: Video layer, plane 2 (V)
+ - description: Graphics layer
+ dma-names:
+ items:
+ - const: vid0
+ - const: vid1
+ - const: vid2
+ - const: gfx0
+
+ phys:
+ description: PHYs for the DP data lanes
+ minItems: 1
+ maxItems: 2
+ phy-names:
+ minItems: 1
+ maxItems: 2
+ items:
+ - const: dp-phy0
+ - const: dp-phy1
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - clocks
+ - clock-names
+ - power-domains
+ - resets
+ - dmas
+ - dma-names
+ - phys
+ - phy-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/phy/phy.h>
+ #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
+
+ display@fd4a0000 {
+ compatible = "xlnx,zynqmp-dpsub-1.7";
+ reg = <0xfd4a0000 0x1000>,
+ <0xfd4aa000 0x1000>,
+ <0xfd4ab000 0x1000>,
+ <0xfd4ac000 0x1000>;
+ reg-names = "dp", "blend", "av_buf", "aud";
+ interrupts = <0 119 4>;
+ interrupt-parent = <&gic>;
+
+ clock-names = "dp_apb_clk", "dp_aud_clk", "dp_live_video_in_clk";
+ clocks = <&dp_aclk>, <&clkc 17>, <&si570_1>;
+
+ power-domains = <&pd_dp>;
+ resets = <&reset ZYNQMP_RESET_DP>;
+
+ dma-names = "vid0", "vid1", "vid2", "gfx0";
+ dmas = <&xlnx_dpdma 0>,
+ <&xlnx_dpdma 1>,
+ <&xlnx_dpdma 2>,
+ <&xlnx_dpdma 3>;
+
+ phys = <&psgtr 1 PHY_TYPE_DP 0 3 27000000>,
+ <&psgtr 0 PHY_TYPE_DP 1 3 27000000>;
+
+ phy-names = "dp-phy0", "dp-phy1";
+ };
+
+...
diff --git a/Bindings/dma/arm-pl330.txt b/Bindings/dma/arm-pl330.txt
index 2c7fd1941abb..315e90122afa 100644
--- a/Bindings/dma/arm-pl330.txt
+++ b/Bindings/dma/arm-pl330.txt
@@ -16,6 +16,7 @@ Optional properties:
- dma-channels: contains the total number of DMA channels supported by the DMAC
- dma-requests: contains the total number of DMA requests supported by the DMAC
- arm,pl330-broken-no-flushp: quirk for avoiding to execute DMAFLUSHP
+ - arm,pl330-periph-burst: quirk for performing burst transfer only
- resets: contains an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names: must contain at least "dma", and optional is "dma-ocp".
diff --git a/Bindings/dma/owl-dma.yaml b/Bindings/dma/owl-dma.yaml
new file mode 100644
index 000000000000..256d62af2c64
--- /dev/null
+++ b/Bindings/dma/owl-dma.yaml
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/owl-dma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Actions Semi Owl SoCs DMA controller
+
+description: |
+ The OWL DMA is a general-purpose direct memory access controller capable of
+ supporting 10 and 12 independent DMA channels for S700 and S900 SoCs
+ respectively.
+
+maintainers:
+ - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+allOf:
+ - $ref: "dma-controller.yaml#"
+
+properties:
+ compatible:
+ enum:
+ - actions,s900-dma
+ - actions,s700-dma
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description:
+ controller supports 4 interrupts, which are freely assignable to the
+ DMA channels.
+ maxItems: 4
+
+ "#dma-cells":
+ const: 1
+
+ dma-channels:
+ maximum: 12
+
+ dma-requests:
+ maximum: 46
+
+ clocks:
+ maxItems: 1
+ description:
+ Phandle and Specifier of the clock feeding the DMA controller.
+
+ power-domains:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - "#dma-cells"
+ - dma-channels
+ - dma-requests
+ - clocks
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ dma: dma-controller@e0260000 {
+ compatible = "actions,s900-dma";
+ reg = <0xe0260000 0x1000>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ dma-channels = <12>;
+ dma-requests = <46>;
+ clocks = <&clock 22>;
+ };
+
+...
diff --git a/Bindings/dma/renesas,rcar-dmac.yaml b/Bindings/dma/renesas,rcar-dmac.yaml
index b842dfd96a89..13f1a46be40d 100644
--- a/Bindings/dma/renesas,rcar-dmac.yaml
+++ b/Bindings/dma/renesas,rcar-dmac.yaml
@@ -23,6 +23,7 @@ properties:
- renesas,dmac-r8a774a1 # RZ/G2M
- renesas,dmac-r8a774b1 # RZ/G2N
- renesas,dmac-r8a774c0 # RZ/G2E
+ - renesas,dmac-r8a774e1 # RZ/G2H
- renesas,dmac-r8a7790 # R-Car H2
- renesas,dmac-r8a7791 # R-Car M2-W
- renesas,dmac-r8a7792 # R-Car V2H
diff --git a/Bindings/dma/renesas,usb-dmac.yaml b/Bindings/dma/renesas,usb-dmac.yaml
index 9ca6d8ddf232..ab287c652b2c 100644
--- a/Bindings/dma/renesas,usb-dmac.yaml
+++ b/Bindings/dma/renesas,usb-dmac.yaml
@@ -16,6 +16,7 @@ properties:
compatible:
items:
- enum:
+ - renesas,r8a7742-usb-dmac # RZ/G1H
- renesas,r8a7743-usb-dmac # RZ/G1M
- renesas,r8a7744-usb-dmac # RZ/G1N
- renesas,r8a7745-usb-dmac # RZ/G1E
@@ -23,6 +24,7 @@ properties:
- renesas,r8a774a1-usb-dmac # RZ/G2M
- renesas,r8a774b1-usb-dmac # RZ/G2N
- renesas,r8a774c0-usb-dmac # RZ/G2E
+ - renesas,r8a774e1-usb-dmac # RZ/G2H
- renesas,r8a7790-usb-dmac # R-Car H2
- renesas,r8a7791-usb-dmac # R-Car M2-W
- renesas,r8a7793-usb-dmac # R-Car M2-N
diff --git a/Bindings/dma/snps,dma-spear1340.yaml b/Bindings/dma/snps,dma-spear1340.yaml
new file mode 100644
index 000000000000..20870f5c14dd
--- /dev/null
+++ b/Bindings/dma/snps,dma-spear1340.yaml
@@ -0,0 +1,176 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/snps,dma-spear1340.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Synopsys Designware DMA Controller
+
+maintainers:
+ - Viresh Kumar <vireshk@kernel.org>
+ - Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+
+allOf:
+ - $ref: "dma-controller.yaml#"
+
+properties:
+ compatible:
+ const: snps,dma-spear1340
+
+ "#dma-cells":
+ const: 3
+ description: |
+ First cell is a phandle pointing to the DMA controller. Second one is
+ the DMA request line number. Third cell is the memory master identifier
+ for transfers on dynamically allocated channel. Fourth cell is the
+ peripheral master identifier for transfers on an allocated channel.
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ description: AHB interface reference clock.
+ const: hclk
+
+ dma-channels:
+ description: |
+ Number of DMA channels supported by the controller. In case if
+ not specified the driver will try to auto-detect this and
+ the rest of the optional parameters.
+ minimum: 1
+ maximum: 8
+
+ dma-requests:
+ minimum: 1
+ maximum: 16
+
+ dma-masters:
+ $ref: /schemas/types.yaml#definitions/uint32
+ description: |
+ Number of DMA masters supported by the controller. In case if
+ not specified the driver will try to auto-detect this and
+ the rest of the optional parameters.
+ minimum: 1
+ maximum: 4
+
+ chan_allocation_order:
+ $ref: /schemas/types.yaml#definitions/uint32
+ description: |
+ DMA channels allocation order specifier. Zero means ascending order
+ (first free allocated), while one - descending (last free allocated).
+ default: 0
+ enum: [0, 1]
+
+ chan_priority:
+ $ref: /schemas/types.yaml#definitions/uint32
+ description: |
+ DMA channels priority order. Zero means ascending channels priority
+ so the very first channel has the highest priority. While 1 means
+ descending priority (the last channel has the highest priority).
+ default: 0
+ enum: [0, 1]
+
+ block_size:
+ $ref: /schemas/types.yaml#definitions/uint32
+ description: Maximum block size supported by the DMA controller.
+ enum: [3, 7, 15, 31, 63, 127, 255, 511, 1023, 2047, 4095]
+
+ data-width:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: Data bus width per each DMA master in bytes.
+ items:
+ maxItems: 4
+ items:
+ enum: [4, 8, 16, 32]
+
+ data_width:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ deprecated: true
+ description: |
+ Data bus width per each DMA master in (2^n * 8) bits. This property is
+ deprecated. It' usage is discouraged in favor of data-width one. Moreover
+ the property incorrectly permits to define data-bus width of 8 and 16
+ bits, which is impossible in accordance with DW DMAC IP-core data book.
+ items:
+ maxItems: 4
+ items:
+ enum:
+ - 0 # 8 bits
+ - 1 # 16 bits
+ - 2 # 32 bits
+ - 3 # 64 bits
+ - 4 # 128 bits
+ - 5 # 256 bits
+ default: 0
+
+ multi-block:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: |
+ LLP-based multi-block transfer supported by hardware per
+ each DMA channel.
+ items:
+ maxItems: 8
+ items:
+ enum: [0, 1]
+ default: 1
+
+ snps,max-burst-len:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: |
+ Maximum length of the burst transactions supported by the controller.
+ This property defines the upper limit of the run-time burst setting
+ (CTLx.SRC_MSIZE/CTLx.DST_MSIZE fields) so the allowed burst length
+ will be from 1 to max-burst-len words. It's an array property with one
+ cell per channel in the units determined by the value set in the
+ CTLx.SRC_TR_WIDTH/CTLx.DST_TR_WIDTH fields (data width).
+ items:
+ maxItems: 8
+ items:
+ enum: [4, 8, 16, 32, 64, 128, 256]
+ default: 256
+
+ snps,dma-protection-control:
+ $ref: /schemas/types.yaml#definitions/uint32
+ description: |
+ Bits one-to-one passed to the AHB HPROT[3:1] bus. Each bit setting
+ indicates the following features: bit 0 - privileged mode,
+ bit 1 - DMA is bufferable, bit 2 - DMA is cacheable.
+ default: 0
+ minimum: 0
+ maximum: 7
+
+unevaluatedProperties: false
+
+required:
+ - compatible
+ - "#dma-cells"
+ - reg
+ - interrupts
+
+examples:
+ - |
+ dma-controller@fc000000 {
+ compatible = "snps,dma-spear1340";
+ reg = <0xfc000000 0x1000>;
+ interrupt-parent = <&vic1>;
+ interrupts = <12>;
+
+ dma-channels = <8>;
+ dma-requests = <16>;
+ dma-masters = <4>;
+ #dma-cells = <3>;
+
+ chan_allocation_order = <1>;
+ chan_priority = <1>;
+ block_size = <0xfff>;
+ data-width = <8 8>;
+ multi-block = <0 0 0 0 0 0 0 0>;
+ snps,max-burst-len = <16 16 4 4 4 4 4 4>;
+ };
+...
diff --git a/Bindings/dma/xilinx/xlnx,zynqmp-dpdma.yaml b/Bindings/dma/xilinx/xlnx,zynqmp-dpdma.yaml
new file mode 100644
index 000000000000..2a595b18ff6c
--- /dev/null
+++ b/Bindings/dma/xilinx/xlnx,zynqmp-dpdma.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dpdma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx ZynqMP DisplayPort DMA Controller Device Tree Bindings
+
+description: |
+ These bindings describe the DMA engine included in the Xilinx ZynqMP
+ DisplayPort Subsystem. The DMA engine supports up to 6 DMA channels (3
+ channels for a video stream, 1 channel for a graphics stream, and 2 channels
+ for an audio stream).
+
+maintainers:
+ - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+
+allOf:
+ - $ref: "../dma-controller.yaml#"
+
+properties:
+ "#dma-cells":
+ const: 1
+ description: |
+ The cell is the DMA channel ID (see dt-bindings/dma/xlnx-zynqmp-dpdma.h
+ for a list of channel IDs).
+
+ compatible:
+ const: xlnx,zynqmp-dpdma
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ description: The AXI clock
+ maxItems: 1
+
+ clock-names:
+ const: axi_clk
+
+required:
+ - "#dma-cells"
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ dma: dma-controller@fd4c0000 {
+ compatible = "xlnx,zynqmp-dpdma";
+ reg = <0xfd4c0000 0x1000>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&dpdma_clk>;
+ clock-names = "axi_clk";
+ #dma-cells = <1>;
+ };
+
+...
diff --git a/Bindings/dsp/fsl,dsp.yaml b/Bindings/dsp/fsl,dsp.yaml
index 3bbe9521c0bc..4cc011230153 100644
--- a/Bindings/dsp/fsl,dsp.yaml
+++ b/Bindings/dsp/fsl,dsp.yaml
@@ -56,8 +56,8 @@ properties:
memory-region:
description:
- phandle to a node describing reserved memory (System RAM memory)
- used by DSP (see bindings/reserved-memory/reserved-memory.txt)
+ phandle to a node describing reserved memory (System RAM memory)
+ used by DSP (see bindings/reserved-memory/reserved-memory.txt)
maxItems: 1
required:
diff --git a/Bindings/example-schema.yaml b/Bindings/example-schema.yaml
index c9534d2164a2..822975dbeafa 100644
--- a/Bindings/example-schema.yaml
+++ b/Bindings/example-schema.yaml
@@ -177,10 +177,10 @@ properties:
dependencies:
# 'vendor,bool-property' is only allowed when 'vendor,string-array-property'
# is present
- vendor,bool-property: [ vendor,string-array-property ]
+ vendor,bool-property: [ 'vendor,string-array-property' ]
# Expressing 2 properties in both orders means all of the set of properties
# must be present or none of them.
- vendor,string-array-property: [ vendor,bool-property ]
+ vendor,string-array-property: [ 'vendor,bool-property' ]
required:
- compatible
diff --git a/Bindings/firmware/qcom,scm.txt b/Bindings/firmware/qcom,scm.txt
index 354b448fc0c3..78456437df5f 100644
--- a/Bindings/firmware/qcom,scm.txt
+++ b/Bindings/firmware/qcom,scm.txt
@@ -11,10 +11,12 @@ Required properties:
* "qcom,scm-apq8084"
* "qcom,scm-ipq4019"
* "qcom,scm-ipq806x"
+ * "qcom,scm-ipq8074"
* "qcom,scm-msm8660"
* "qcom,scm-msm8916"
* "qcom,scm-msm8960"
* "qcom,scm-msm8974"
+ * "qcom,scm-msm8994"
* "qcom,scm-msm8996"
* "qcom,scm-msm8998"
* "qcom,scm-sc7180"
diff --git a/Bindings/fpga/fpga-region.txt b/Bindings/fpga/fpga-region.txt
index 8ab19d1d3f9a..e811cf825019 100644
--- a/Bindings/fpga/fpga-region.txt
+++ b/Bindings/fpga/fpga-region.txt
@@ -493,4 +493,4 @@ FPGA Bridges that exist on the FPGA fabric prior to the partial reconfiguration.
--
[1] www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_partrecon.pdf
[2] tspace.library.utoronto.ca/bitstream/1807/67932/1/Byma_Stuart_A_201411_MAS_thesis.pdf
-[3] http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/ug702.pdf
+[3] https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/ug702.pdf
diff --git a/Bindings/fpga/xilinx-slave-serial.txt b/Bindings/fpga/xilinx-slave-serial.txt
index cfa4ed42b62f..5ef659c1394d 100644
--- a/Bindings/fpga/xilinx-slave-serial.txt
+++ b/Bindings/fpga/xilinx-slave-serial.txt
@@ -1,11 +1,14 @@
Xilinx Slave Serial SPI FPGA Manager
-Xilinx Spartan-6 FPGAs support a method of loading the bitstream over
-what is referred to as "slave serial" interface.
+Xilinx Spartan-6 and 7 Series FPGAs support a method of loading the
+bitstream over what is referred to as "slave serial" interface.
The slave serial link is not technically SPI, and might require extra
circuits in order to play nicely with other SPI slaves on the same bus.
-See https://www.xilinx.com/support/documentation/user_guides/ug380.pdf
+See:
+- https://www.xilinx.com/support/documentation/user_guides/ug380.pdf
+- https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
+- https://www.xilinx.com/support/documentation/application_notes/xapp583-fpga-configuration.pdf
Required properties:
- compatible: should contain "xlnx,fpga-slave-serial"
@@ -13,6 +16,10 @@ Required properties:
- prog_b-gpios: config pin (referred to as PROGRAM_B in the manual)
- done-gpios: config status pin (referred to as DONE in the manual)
+Optional properties:
+- init-b-gpios: initialization status and configuration error pin
+ (referred to as INIT_B in the manual)
+
Example for full FPGA configuration:
fpga-region0 {
@@ -37,7 +44,8 @@ Example for full FPGA configuration:
spi-max-frequency = <60000000>;
spi-cpha;
reg = <0>;
- done-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
prog_b-gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
+ init-b-gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
+ done-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
};
};
diff --git a/Bindings/fsi/ibm,fsi2spi.yaml b/Bindings/fsi/ibm,fsi2spi.yaml
index 893d81e54caa..b26d4b4be743 100644
--- a/Bindings/fsi/ibm,fsi2spi.yaml
+++ b/Bindings/fsi/ibm,fsi2spi.yaml
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: IBM FSI-attached SPI controllers
maintainers:
- - Eddie James <eajames@linux.ibm.com>
+ - Eddie James <eajames@linux.ibm.com>
description: |
This binding describes an FSI CFAM engine called the FSI2SPI. Therefore this
diff --git a/Bindings/fuse/nvidia,tegra20-fuse.txt b/Bindings/fuse/nvidia,tegra20-fuse.txt
index 41372d441131..2aaf661c04ee 100644
--- a/Bindings/fuse/nvidia,tegra20-fuse.txt
+++ b/Bindings/fuse/nvidia,tegra20-fuse.txt
@@ -4,8 +4,9 @@ Required properties:
- compatible : For Tegra20, must contain "nvidia,tegra20-efuse". For Tegra30,
must contain "nvidia,tegra30-efuse". For Tegra114, must contain
"nvidia,tegra114-efuse". For Tegra124, must contain "nvidia,tegra124-efuse".
- Otherwise, must contain "nvidia,<chip>-efuse", plus one of the above, where
- <chip> is tegra132.
+ For Tegra132 must contain "nvidia,tegra132-efuse", "nvidia,tegra124-efuse".
+ For Tegra210 must contain "nvidia,tegra210-efuse". For Tegra186 must contain
+ "nvidia,tegra186-efuse". For Tegra194 must contain "nvidia,tegra194-efuse".
Details:
nvidia,tegra20-efuse: Tegra20 requires using APB DMA to read the fuse data
due to a hardware bug. Tegra20 also lacks certain information which is
diff --git a/Bindings/gpio/brcm,xgs-iproc-gpio.yaml b/Bindings/gpio/brcm,xgs-iproc-gpio.yaml
index 4f2cbd8307a7..c213cb9ddb9f 100644
--- a/Bindings/gpio/brcm,xgs-iproc-gpio.yaml
+++ b/Bindings/gpio/brcm,xgs-iproc-gpio.yaml
@@ -19,10 +19,8 @@ properties:
reg:
items:
- - description: the I/O address containing the GPIO controller
- registers.
- - description: the I/O address containing the Chip Common A interrupt
- registers.
+ - description: the I/O address containing the GPIO controller registers.
+ - description: the I/O address containing the Chip Common A interrupt registers.
gpio-controller: true
diff --git a/Bindings/gpio/gpio-mxs.yaml b/Bindings/gpio/gpio-mxs.yaml
index ccf5b50e798b..dfa1133f8c5e 100644
--- a/Bindings/gpio/gpio-mxs.yaml
+++ b/Bindings/gpio/gpio-mxs.yaml
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale MXS GPIO controller
maintainers:
- - Shawn Guo <shawn.guo@linaro.org>
+ - Shawn Guo <shawnguo@kernel.org>
- Anson Huang <Anson.Huang@nxp.com>
description: |
diff --git a/Bindings/gpio/gpio-pca953x.txt b/Bindings/gpio/gpio-pca953x.txt
index dab537c20def..3126c3817e2a 100644
--- a/Bindings/gpio/gpio-pca953x.txt
+++ b/Bindings/gpio/gpio-pca953x.txt
@@ -19,6 +19,7 @@ Required properties:
nxp,pca9698
nxp,pcal6416
nxp,pcal6524
+ nxp,pcal9535
nxp,pcal9555a
maxim,max7310
maxim,max7312
diff --git a/Bindings/gpio/gpio-pca9570.yaml b/Bindings/gpio/gpio-pca9570.yaml
new file mode 100644
index 000000000000..338c5312a106
--- /dev/null
+++ b/Bindings/gpio/gpio-pca9570.yaml
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/gpio-pca9570.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: PCA9570 I2C GPO expander
+
+maintainers:
+ - Sungbo Eo <mans0n@gorani.run>
+
+properties:
+ compatible:
+ enum:
+ - nxp,pca9570
+
+ reg:
+ maxItems: 1
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 2
+
+required:
+ - compatible
+ - reg
+ - gpio-controller
+ - "#gpio-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio@24 {
+ compatible = "nxp,pca9570";
+ reg = <0x24>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+
+...
diff --git a/Bindings/gpio/gpio-zynq.txt b/Bindings/gpio/gpio-zynq.txt
index 4fa4eb5507cd..f693e82b4c0f 100644
--- a/Bindings/gpio/gpio-zynq.txt
+++ b/Bindings/gpio/gpio-zynq.txt
@@ -6,7 +6,9 @@ Required properties:
- First cell is the GPIO line number
- Second cell is used to specify optional
parameters (unused)
-- compatible : Should be "xlnx,zynq-gpio-1.0" or "xlnx,zynqmp-gpio-1.0"
+- compatible : Should be "xlnx,zynq-gpio-1.0" or
+ "xlnx,zynqmp-gpio-1.0" or "xlnx,versal-gpio-1.0
+ or "xlnx,pmc-gpio-1.0
- clocks : Clock specifier (see clock bindings for details)
- gpio-controller : Marks the device node as a GPIO controller.
- interrupts : Interrupt specifier (see interrupt bindings for
diff --git a/Bindings/gpio/mrvl-gpio.yaml b/Bindings/gpio/mrvl-gpio.yaml
new file mode 100644
index 000000000000..4db3b8a3332c
--- /dev/null
+++ b/Bindings/gpio/mrvl-gpio.yaml
@@ -0,0 +1,173 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/mrvl-gpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Marvell PXA GPIO controller
+
+maintainers:
+ - Linus Walleij <linus.walleij@linaro.org>
+ - Bartosz Golaszewski <bgolaszewski@baylibre.com>
+ - Rob Herring <robh+dt@kernel.org>
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - intel,pxa25x-gpio
+ - intel,pxa26x-gpio
+ - intel,pxa27x-gpio
+ - intel,pxa3xx-gpio
+ then:
+ properties:
+ interrupts:
+ minItems: 3
+ maxItems: 3
+ interrupt-names:
+ items:
+ - const: gpio0
+ - const: gpio1
+ - const: gpio_mux
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - marvell,mmp-gpio
+ - marvell,mmp2-gpio
+ then:
+ properties:
+ interrupts:
+ maxItems: 1
+ interrupt-names:
+ items:
+ - const: gpio_mux
+
+properties:
+ $nodename:
+ pattern: '^gpio@[0-9a-f]+$'
+
+ compatible:
+ enum:
+ - intel,pxa25x-gpio
+ - intel,pxa26x-gpio
+ - intel,pxa27x-gpio
+ - intel,pxa3xx-gpio
+ - marvell,mmp-gpio
+ - marvell,mmp2-gpio
+ - marvell,pxa93x-gpio
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ ranges: true
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 1
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 2
+
+ gpio-ranges:
+ maxItems: 1
+
+ interrupts: true
+
+ interrupt-names: true
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 2
+
+patternProperties:
+ '^gpio@[0-9a-f]*$':
+ type: object
+ properties:
+ reg:
+ maxItems: 1
+
+ required:
+ - reg
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - '#address-cells'
+ - '#size-cells'
+ - reg
+ - gpio-controller
+ - '#gpio-cells'
+ - interrupts
+ - interrupt-names
+ - interrupt-controller
+ - '#interrupt-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/pxa-clock.h>
+ gpio@40e00000 {
+ compatible = "intel,pxa3xx-gpio";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x40e00000 0x10000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <8>, <9>, <10>;
+ interrupt-names = "gpio0", "gpio1", "gpio_mux";
+ clocks = <&clks CLK_GPIO>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ - |
+ #include <dt-bindings/clock/marvell,pxa910.h>
+ gpio@d4019000 {
+ compatible = "marvell,mmp-gpio";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xd4019000 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <49>;
+ interrupt-names = "gpio_mux";
+ clocks = <&soc_clocks PXA910_CLK_GPIO>;
+ resets = <&soc_clocks PXA910_CLK_GPIO>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ranges;
+
+ gpio@d4019000 {
+ reg = <0xd4019000 0x4>;
+ };
+
+ gpio@d4019004 {
+ reg = <0xd4019004 0x4>;
+ };
+
+ gpio@d4019008 {
+ reg = <0xd4019008 0x4>;
+ };
+
+ gpio@d4019100 {
+ reg = <0xd4019100 0x4>;
+ };
+ };
+
+...
diff --git a/Bindings/gpio/renesas,rcar-gpio.yaml b/Bindings/gpio/renesas,rcar-gpio.yaml
index 397d9383d15a..3ad229307bd5 100644
--- a/Bindings/gpio/renesas,rcar-gpio.yaml
+++ b/Bindings/gpio/renesas,rcar-gpio.yaml
@@ -13,39 +13,39 @@ properties:
compatible:
oneOf:
- items:
- - enum:
- - renesas,gpio-r8a7778 # R-Car M1
- - renesas,gpio-r8a7779 # R-Car H1
- - const: renesas,rcar-gen1-gpio # R-Car Gen1
+ - enum:
+ - renesas,gpio-r8a7778 # R-Car M1
+ - renesas,gpio-r8a7779 # R-Car H1
+ - const: renesas,rcar-gen1-gpio # R-Car Gen1
- items:
- - enum:
- - renesas,gpio-r8a7742 # RZ/G1H
- - renesas,gpio-r8a7743 # RZ/G1M
- - renesas,gpio-r8a7744 # RZ/G1N
- - renesas,gpio-r8a7745 # RZ/G1E
- - renesas,gpio-r8a77470 # RZ/G1C
- - renesas,gpio-r8a7790 # R-Car H2
- - renesas,gpio-r8a7791 # R-Car M2-W
- - renesas,gpio-r8a7792 # R-Car V2H
- - renesas,gpio-r8a7793 # R-Car M2-N
- - renesas,gpio-r8a7794 # R-Car E2
- - const: renesas,rcar-gen2-gpio # R-Car Gen2 or RZ/G1
+ - enum:
+ - renesas,gpio-r8a7742 # RZ/G1H
+ - renesas,gpio-r8a7743 # RZ/G1M
+ - renesas,gpio-r8a7744 # RZ/G1N
+ - renesas,gpio-r8a7745 # RZ/G1E
+ - renesas,gpio-r8a77470 # RZ/G1C
+ - renesas,gpio-r8a7790 # R-Car H2
+ - renesas,gpio-r8a7791 # R-Car M2-W
+ - renesas,gpio-r8a7792 # R-Car V2H
+ - renesas,gpio-r8a7793 # R-Car M2-N
+ - renesas,gpio-r8a7794 # R-Car E2
+ - const: renesas,rcar-gen2-gpio # R-Car Gen2 or RZ/G1
- items:
- - enum:
- - renesas,gpio-r8a774a1 # RZ/G2M
- - renesas,gpio-r8a774b1 # RZ/G2N
- - renesas,gpio-r8a774c0 # RZ/G2E
- - renesas,gpio-r8a7795 # R-Car H3
- - renesas,gpio-r8a7796 # R-Car M3-W
- - renesas,gpio-r8a77961 # R-Car M3-W+
- - renesas,gpio-r8a77965 # R-Car M3-N
- - renesas,gpio-r8a77970 # R-Car V3M
- - renesas,gpio-r8a77980 # R-Car V3H
- - renesas,gpio-r8a77990 # R-Car E3
- - renesas,gpio-r8a77995 # R-Car D3
- - const: renesas,rcar-gen3-gpio # R-Car Gen3 or RZ/G2
+ - enum:
+ - renesas,gpio-r8a774a1 # RZ/G2M
+ - renesas,gpio-r8a774b1 # RZ/G2N
+ - renesas,gpio-r8a774c0 # RZ/G2E
+ - renesas,gpio-r8a7795 # R-Car H3
+ - renesas,gpio-r8a7796 # R-Car M3-W
+ - renesas,gpio-r8a77961 # R-Car M3-W+
+ - renesas,gpio-r8a77965 # R-Car M3-N
+ - renesas,gpio-r8a77970 # R-Car V3M
+ - renesas,gpio-r8a77980 # R-Car V3H
+ - renesas,gpio-r8a77990 # R-Car E3
+ - renesas,gpio-r8a77995 # R-Car D3
+ - const: renesas,rcar-gen3-gpio # R-Car Gen3 or RZ/G2
reg:
maxItems: 1
diff --git a/Bindings/gpio/sgpio-aspeed.txt b/Bindings/gpio/sgpio-aspeed.txt
index d4d83916c09d..be329ea4794f 100644
--- a/Bindings/gpio/sgpio-aspeed.txt
+++ b/Bindings/gpio/sgpio-aspeed.txt
@@ -20,8 +20,9 @@ Required properties:
- gpio-controller : Marks the device node as a GPIO controller
- interrupts : Interrupt specifier, see interrupt-controller/interrupts.txt
- interrupt-controller : Mark the GPIO controller as an interrupt-controller
-- ngpios : number of GPIO lines, see gpio.txt
- (should be multiple of 8, up to 80 pins)
+- ngpios : number of *hardware* GPIO lines, see gpio.txt. This will expose
+ 2 software GPIOs per hardware GPIO: one for hardware input, one for hardware
+ output. Up to 80 pins, must be a multiple of 8.
- clocks : A phandle to the APB clock for SGPM clock division
- bus-frequency : SGPM CLK frequency
diff --git a/Bindings/gpu/nvidia,gk20a.txt b/Bindings/gpu/nvidia,gk20a.txt
index f32bbba4d3bc..662a3c8a7d29 100644
--- a/Bindings/gpu/nvidia,gk20a.txt
+++ b/Bindings/gpu/nvidia,gk20a.txt
@@ -6,6 +6,7 @@ Required properties:
- nvidia,gk20a
- nvidia,gm20b
- nvidia,gp10b
+ - nvidia,gv11b
- reg: Physical base address and length of the controller's registers.
Must contain two entries:
- first entry for bar0
@@ -25,6 +26,9 @@ Required properties:
If the compatible string is "nvidia,gm20b", then the following clock
is also required:
- ref
+If the compatible string is "nvidia,gv11b", then the following clock is also
+required:
+ - fuse
- resets: Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names: Must include the following entries:
@@ -88,3 +92,24 @@ Example for GP10B:
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
iommus = <&smmu TEGRA186_SID_GPU>;
};
+
+Example for GV11B:
+
+ gpu@17000000 {
+ compatible = "nvidia,gv11b";
+ reg = <0x17000000 0x10000000>,
+ <0x18000000 0x10000000>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "stall", "nonstall";
+ clocks = <&bpmp TEGRA194_CLK_GPCCLK>,
+ <&bpmp TEGRA194_CLK_GPU_PWR>,
+ <&bpmp TEGRA194_CLK_FUSE>;
+ clock-names = "gpu", "pwr", "fuse";
+ resets = <&bpmp TEGRA194_RESET_GPU>;
+ reset-names = "gpu";
+ dma-coherent;
+
+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>;
+ iommus = <&smmu TEGRA194_SID_GPU>;
+ };
diff --git a/Bindings/gpu/vivante,gc.yaml b/Bindings/gpu/vivante,gc.yaml
index e1ac6ff5a230..4843df1ddbb6 100644
--- a/Bindings/gpu/vivante,gc.yaml
+++ b/Bindings/gpu/vivante,gc.yaml
@@ -26,7 +26,8 @@ properties:
- description: AXI/master interface clock
- description: GPU core clock
- description: Shader clock (only required if GPU has feature PIPE_3D)
- - description: AHB/slave interface clock (only required if GPU can gate slave interface independently)
+ - description: AHB/slave interface clock (only required if GPU can gate
+ slave interface independently)
minItems: 1
maxItems: 4
diff --git a/Bindings/hwlock/qcom-hwspinlock.yaml b/Bindings/hwlock/qcom-hwspinlock.yaml
new file mode 100644
index 000000000000..1c7149f7d171
--- /dev/null
+++ b/Bindings/hwlock/qcom-hwspinlock.yaml
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/hwlock/qcom-hwspinlock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Hardware Mutex Block
+
+maintainers:
+ - Bjorn Andersson <bjorn.andersson@linaro.org>
+
+description:
+ The hardware block provides mutexes utilized between different processors on
+ the SoC as part of the communication protocol used by these processors.
+
+properties:
+ compatible:
+ enum:
+ - qcom,sfpb-mutex
+ - qcom,tcsr-mutex
+
+ reg:
+ maxItems: 1
+
+ '#hwlock-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - '#hwlock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ tcsr_mutex: hwlock@1f40000 {
+ compatible = "qcom,tcsr-mutex";
+ reg = <0x01f40000 0x40000>;
+ #hwlock-cells = <1>;
+ };
+...
diff --git a/Bindings/hwmon/adi,axi-fan-control.yaml b/Bindings/hwmon/adi,axi-fan-control.yaml
index af35b77053df..7898b9dba5a5 100644
--- a/Bindings/hwmon/adi,axi-fan-control.yaml
+++ b/Bindings/hwmon/adi,axi-fan-control.yaml
@@ -19,7 +19,7 @@ description: |+
properties:
compatible:
enum:
- - adi,axi-fan-control-1.00.a
+ - adi,axi-fan-control-1.00.a
reg:
maxItems: 1
diff --git a/Bindings/hwmon/gpio-fan.txt b/Bindings/hwmon/gpio-fan.txt
index 2becdcfdc840..f4cfa350f6a1 100644
--- a/Bindings/hwmon/gpio-fan.txt
+++ b/Bindings/hwmon/gpio-fan.txt
@@ -12,7 +12,8 @@ Optional properties:
- alarm-gpios: This pin going active indicates something is wrong with
the fan, and a udev event will be fired.
- #cooling-cells: If used as a cooling device, must be <2>
- Also see: Documentation/devicetree/bindings/thermal/thermal.txt
+ Also see:
+ Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml
min and max states are derived from the speed-map of the fan.
Note: At least one the "gpios" or "alarm-gpios" properties must be set.
diff --git a/Bindings/hwmon/lm90.txt b/Bindings/hwmon/lm90.txt
index c76a7ac47c34..398dcb965751 100644
--- a/Bindings/hwmon/lm90.txt
+++ b/Bindings/hwmon/lm90.txt
@@ -34,8 +34,8 @@ Optional properties:
LM90 "-ALERT" pin output.
See interrupt-controller/interrupts.txt for the format.
-- #thermal-sensor-cells: should be set to 1. See thermal/thermal.txt for
- details. See <include/dt-bindings/thermal/lm90.h> for the
+- #thermal-sensor-cells: should be set to 1. See thermal/thermal-sensor.yaml
+ for details. See <include/dt-bindings/thermal/lm90.h> for the
definition of the local, remote and 2nd remote sensor index
constants.
diff --git a/Bindings/hwmon/microchip,sparx5-temp.yaml b/Bindings/hwmon/microchip,sparx5-temp.yaml
new file mode 100644
index 000000000000..76be625d5646
--- /dev/null
+++ b/Bindings/hwmon/microchip,sparx5-temp.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/hwmon/microchip,sparx5-temp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip Sparx5 Temperature Monitor
+
+maintainers:
+ - Lars Povlsen <lars.povlsen@microchip.com>
+
+description: |
+ Microchip Sparx5 embedded temperature monitor
+
+properties:
+ compatible:
+ enum:
+ - microchip,sparx5-temp
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: AHB reference clock
+
+ '#thermal-sensor-cells':
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ tmon0: tmon@610508110 {
+ compatible = "microchip,sparx5-temp";
+ reg = <0x10508110 0xc>;
+ #thermal-sensor-cells = <0>;
+ clocks = <&ahb_clk>;
+ };
diff --git a/Bindings/hwmon/ti,tmp513.yaml b/Bindings/hwmon/ti,tmp513.yaml
index 90b2fa3f7752..c17e5d3ee3f1 100644
--- a/Bindings/hwmon/ti,tmp513.yaml
+++ b/Bindings/hwmon/ti,tmp513.yaml
@@ -18,8 +18,8 @@ description: |
consumption.
Datasheets:
- http://www.ti.com/lit/gpn/tmp513
- http://www.ti.com/lit/gpn/tmp512
+ https://www.ti.com/lit/gpn/tmp513
+ https://www.ti.com/lit/gpn/tmp512
properties:
diff --git a/Bindings/i2c/i2c-gpio.yaml b/Bindings/i2c/i2c-gpio.yaml
index da6129090a8e..78ffcab2428c 100644
--- a/Bindings/i2c/i2c-gpio.yaml
+++ b/Bindings/i2c/i2c-gpio.yaml
@@ -52,15 +52,15 @@ properties:
description: sda and scl gpio, alternative for {sda,scl}-gpios
i2c-gpio,sda-open-drain:
- # Generate a warning if present
- not: true
+ type: boolean
+ deprecated: true
description: this means that something outside of our control has put
the GPIO line used for SDA into open drain mode, and that something is
not the GPIO chip. It is essentially an inconsistency flag.
i2c-gpio,scl-open-drain:
- # Generate a warning if present
- not: true
+ type: boolean
+ deprecated: true
description: this means that something outside of our control has put the
GPIO line used for SCL into open drain mode, and that something is not
the GPIO chip. It is essentially an inconsistency flag.
diff --git a/Bindings/i2c/i2c-imx-lpi2c.yaml b/Bindings/i2c/i2c-imx-lpi2c.yaml
new file mode 100644
index 000000000000..ac0bc5dd64d6
--- /dev/null
+++ b/Bindings/i2c/i2c-imx-lpi2c.yaml
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/i2c-imx-lpi2c.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale Low Power Inter IC (LPI2C) for i.MX
+
+maintainers:
+ - Anson Huang <Anson.Huang@nxp.com>
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx7ulp-lpi2c
+ - fsl,imx8qxp-lpi2c
+ - fsl,imx8qm-lpi2c
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx7ulp-clock.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ lpi2c7@40a50000 {
+ compatible = "fsl,imx7ulp-lpi2c";
+ reg = <0x40A50000 0x10000>;
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7ULP_CLK_LPI2C7>;
+ };
diff --git a/Bindings/i2c/i2c-imx.yaml b/Bindings/i2c/i2c-imx.yaml
new file mode 100644
index 000000000000..810536953177
--- /dev/null
+++ b/Bindings/i2c/i2c-imx.yaml
@@ -0,0 +1,103 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/i2c-imx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale Inter IC (I2C) and High Speed Inter IC (HS-I2C) for i.MX
+
+maintainers:
+ - Wolfram Sang <wolfram@the-dreams.de>
+
+properties:
+ compatible:
+ oneOf:
+ - const: fsl,imx1-i2c
+ - const: fsl,imx21-i2c
+ - const: fsl,vf610-i2c
+ - items:
+ - const: fsl,imx35-i2c
+ - const: fsl,imx1-i2c
+ - items:
+ - enum:
+ - fsl,imx25-i2c
+ - fsl,imx27-i2c
+ - fsl,imx31-i2c
+ - fsl,imx50-i2c
+ - fsl,imx51-i2c
+ - fsl,imx53-i2c
+ - fsl,imx6q-i2c
+ - fsl,imx6sl-i2c
+ - fsl,imx6sx-i2c
+ - fsl,imx6sll-i2c
+ - fsl,imx6ul-i2c
+ - fsl,imx7s-i2c
+ - fsl,imx8mq-i2c
+ - fsl,imx8mm-i2c
+ - fsl,imx8mn-i2c
+ - fsl,imx8mp-i2c
+ - const: fsl,imx21-i2c
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: ipg
+
+ clock-frequency:
+ enum: [ 100000, 400000 ]
+
+ dmas:
+ items:
+ - description: DMA controller phandle and request line for RX
+ - description: DMA controller phandle and request line for TX
+
+ dma-names:
+ items:
+ - const: rx
+ - const: tx
+
+ sda-gpios:
+ maxItems: 1
+
+ scl-gpios:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx5-clock.h>
+ #include <dt-bindings/clock/vf610-clock.h>
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ i2c@83fc4000 {
+ compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
+ reg = <0x83fc4000 0x4000>;
+ interrupts = <63>;
+ clocks = <&clks IMX5_CLK_I2C2_GATE>;
+ };
+
+ i2c@40066000 {
+ compatible = "fsl,vf610-i2c";
+ reg = <0x40066000 0x1000>;
+ interrupts = <71 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks VF610_CLK_I2C0>;
+ clock-names = "ipg";
+ dmas = <&edma0 0 50>,
+ <&edma0 0 51>;
+ dma-names = "rx", "tx";
+ };
diff --git a/Bindings/i2c/i2c-mt65xx.txt b/Bindings/i2c/i2c-mt65xx.txt
index 88b71c1b32c9..7f0194fdd0cc 100644
--- a/Bindings/i2c/i2c-mt65xx.txt
+++ b/Bindings/i2c/i2c-mt65xx.txt
@@ -14,6 +14,7 @@ Required properties:
"mediatek,mt7629-i2c", "mediatek,mt2712-i2c": for MediaTek MT7629
"mediatek,mt8173-i2c": for MediaTek MT8173
"mediatek,mt8183-i2c": for MediaTek MT8183
+ "mediatek,mt8192-i2c": for MediaTek MT8192
"mediatek,mt8516-i2c", "mediatek,mt2712-i2c": for MediaTek MT8516
- reg: physical base address of the controller and dma base, length of memory
mapped region.
diff --git a/Bindings/i2c/i2c-mxs.yaml b/Bindings/i2c/i2c-mxs.yaml
new file mode 100644
index 000000000000..21ae7bce038e
--- /dev/null
+++ b/Bindings/i2c/i2c-mxs.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/i2c-mxs.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale MXS Inter IC (I2C) Controller
+
+maintainers:
+ - Shawn Guo <shawnguo@kernel.org>
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx23-i2c
+ - fsl,imx28-i2c
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clock-frequency:
+ enum: [ 100000, 400000 ]
+
+ dmas:
+ maxItems: 1
+
+ dma-names:
+ const: rx-tx
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - dmas
+ - dma-names
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c@80058000 {
+ compatible = "fsl,imx28-i2c";
+ reg = <0x80058000 2000>;
+ interrupts = <111>;
+ clock-frequency = <100000>;
+ dmas = <&dma_apbx 6>;
+ dma-names = "rx-tx";
+ };
diff --git a/Bindings/i2c/i2c-pxa.yaml b/Bindings/i2c/i2c-pxa.yaml
new file mode 100644
index 000000000000..015885dd02d3
--- /dev/null
+++ b/Bindings/i2c/i2c-pxa.yaml
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/i2c-pxa.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Marvell MMP I2C controller bindings
+
+maintainers:
+ - Rob Herring <robh+dt@kernel.org>
+
+allOf:
+ - $ref: /schemas/i2c/i2c-controller.yaml#
+ - if:
+ not:
+ required:
+ - mrvl,i2c-polling
+ then:
+ required:
+ - interrupts
+
+properties:
+ compatible:
+ enum:
+ - mrvl,mmp-twsi
+ - mrvl,pxa-i2c
+ - marvell,armada-3700-i2c
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+
+ resets:
+ minItems: 1
+
+ mrvl,i2c-polling:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: |
+ Disable interrupt of i2c controller. Polling status register of i2c
+ controller instead.
+
+ mrvl,i2c-fast-mode:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: Enable fast mode of i2c controller.
+
+unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - '#address-cells'
+ - '#size-cells'
+
+examples:
+ - |
+ #include <dt-bindings/clock/marvell,mmp2.h>
+ i2c@d4011000 {
+ compatible = "mrvl,mmp-twsi";
+ reg = <0xd4011000 0x1000>;
+ interrupts = <7>;
+ clocks = <&soc_clocks MMP2_CLK_TWSI1>;
+ mrvl,i2c-fast-mode;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+...
diff --git a/Bindings/i2c/i2c.txt b/Bindings/i2c/i2c.txt
index 438ae123107e..a21c359b9f02 100644
--- a/Bindings/i2c/i2c.txt
+++ b/Bindings/i2c/i2c.txt
@@ -72,6 +72,16 @@ wants to support one of the below features, it should adapt these bindings.
this information to adapt power management to keep the arbitration awake
all the time, for example. Can not be combined with 'single-master'.
+- pinctrl
+ add extra pinctrl to configure SCL/SDA pins to GPIO function for bus
+ recovery, call it "gpio" or "recovery" (deprecated) state
+
+- scl-gpios
+ specify the gpio related to SCL pin. Used for GPIO bus recovery.
+
+- sda-gpios
+ specify the gpio related to SDA pin. Optional for GPIO bus recovery.
+
- single-master
states that there is no other master active on this bus. The OS can use
this information to detect a stalled bus more reliably, for example.
diff --git a/Bindings/i2c/marvell,mv64xxx-i2c.yaml b/Bindings/i2c/marvell,mv64xxx-i2c.yaml
index 2ceb05ba2df5..5b5ae402f97a 100644
--- a/Bindings/i2c/marvell,mv64xxx-i2c.yaml
+++ b/Bindings/i2c/marvell,mv64xxx-i2c.yaml
@@ -27,6 +27,9 @@ properties:
- const: allwinner,sun50i-a64-i2c
- const: allwinner,sun6i-a31-i2c
- items:
+ - const: allwinner,sun50i-a100-i2c
+ - const: allwinner,sun6i-a31-i2c
+ - items:
- const: allwinner,sun50i-h6-i2c
- const: allwinner,sun6i-a31-i2c
diff --git a/Bindings/i2c/nvidia,tegra20-i2c.txt b/Bindings/i2c/nvidia,tegra20-i2c.txt
index 18c0de362451..3f2f990c2e62 100644
--- a/Bindings/i2c/nvidia,tegra20-i2c.txt
+++ b/Bindings/i2c/nvidia,tegra20-i2c.txt
@@ -35,12 +35,12 @@ Required properties:
Due to above changes, Tegra114 I2C driver makes incompatible with
previous hardware driver. Hence, tegra114 I2C controller is compatible
with "nvidia,tegra114-i2c".
- nvidia,tegra210-i2c-vi: Tegra210 has one I2C controller that is part of the
- host1x domain and typically used for camera use-cases. This VI I2C
- controller is mostly compatible with the programming model of the
- regular I2C controllers with a few exceptions. The I2C registers start
- at an offset of 0xc00 (instead of 0), registers are 16 bytes apart
- (rather than 4) and the controller does not support slave mode.
+ nvidia,tegra210-i2c-vi: Tegra210 has one I2C controller that is on host1x bus
+ and is part of VE power domain and typically used for camera use-cases.
+ This VI I2C controller is mostly compatible with the programming model
+ of the regular I2C controllers with a few exceptions. The I2C registers
+ start at an offset of 0xc00 (instead of 0), registers are 16 bytes
+ apart (rather than 4) and the controller does not support slave mode.
- reg: Should contain I2C controller registers physical address and length.
- interrupts: Should contain I2C controller interrupts.
- address-cells: Address cells for I2C device address.
@@ -53,10 +53,17 @@ Required properties:
- fast-clk
Tegra114:
- div-clk
+ Tegra210:
+ - div-clk
+ - slow (only for nvidia,tegra210-i2c-vi compatible node)
- resets: Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names: Must include the following entries:
- i2c
+- power-domains: Only for nvidia,tegra210-i2c-vi compatible node and must
+ include venc powergate node as vi i2c is part of VE power domain.
+ tegra210-i2c-vi:
+ - pd_venc
- dmas: Must contain an entry for each entry in clock-names.
See ../dma/dma.txt for details.
- dma-names: Must include the following entries:
diff --git a/Bindings/i2c/renesas,i2c.txt b/Bindings/i2c/renesas,i2c.txt
index a03f9f5cb378..96d869ac3839 100644
--- a/Bindings/i2c/renesas,i2c.txt
+++ b/Bindings/i2c/renesas,i2c.txt
@@ -10,6 +10,7 @@ Required properties:
"renesas,i2c-r8a774a1" if the device is a part of a R8A774A1 SoC.
"renesas,i2c-r8a774b1" if the device is a part of a R8A774B1 SoC.
"renesas,i2c-r8a774c0" if the device is a part of a R8A774C0 SoC.
+ "renesas,i2c-r8a774e1" if the device is a part of a R8A774E1 SoC.
"renesas,i2c-r8a7778" if the device is a part of a R8A7778 SoC.
"renesas,i2c-r8a7779" if the device is a part of a R8A7779 SoC.
"renesas,i2c-r8a7790" if the device is a part of a R8A7790 SoC.
diff --git a/Bindings/i2c/renesas,iic.txt b/Bindings/i2c/renesas,iic.txt
index 89facb09337a..93d412832e66 100644
--- a/Bindings/i2c/renesas,iic.txt
+++ b/Bindings/i2c/renesas,iic.txt
@@ -11,6 +11,7 @@ Required properties:
- "renesas,iic-r8a774a1" (RZ/G2M)
- "renesas,iic-r8a774b1" (RZ/G2N)
- "renesas,iic-r8a774c0" (RZ/G2E)
+ - "renesas,iic-r8a774e1" (RZ/G2H)
- "renesas,iic-r8a7790" (R-Car H2)
- "renesas,iic-r8a7791" (R-Car M2-W)
- "renesas,iic-r8a7792" (R-Car V2H)
diff --git a/Bindings/iio/accel/adi,adxl345.yaml b/Bindings/iio/accel/adi,adxl345.yaml
index d124eba1ce54..fd4eaa3d0ab4 100644
--- a/Bindings/iio/accel/adi,adxl345.yaml
+++ b/Bindings/iio/accel/adi,adxl345.yaml
@@ -12,8 +12,8 @@ maintainers:
description: |
Analog Devices ADXL345/ADXL375 3-Axis Digital Accelerometers that supports
both I2C & SPI interfaces.
- http://www.analog.com/en/products/mems/accelerometers/adxl345.html
- http://www.analog.com/en/products/sensors-mems/accelerometers/adxl375.html
+ https://www.analog.com/en/products/mems/accelerometers/adxl345.html
+ https://www.analog.com/en/products/sensors-mems/accelerometers/adxl375.html
properties:
compatible:
diff --git a/Bindings/iio/accel/kionix,kxsd9.yaml b/Bindings/iio/accel/kionix,kxsd9.yaml
new file mode 100644
index 000000000000..d61ab4fa3d71
--- /dev/null
+++ b/Bindings/iio/accel/kionix,kxsd9.yaml
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/accel/kionix,kxsd9.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Kionix KXSD9 Accelerometer
+
+maintainers:
+ - Jonathan Cameron <jic23@kernel.org>
+
+description: |
+ 3 axis 12 bit accelerometer with +-8G range on all axes. Also has a
+ 12 bit auxiliary ADC channel. Interface is either SPI or I2C.
+
+properties:
+ compatible:
+ const: kionix,kxsd9
+
+ reg:
+ maxItems: 1
+
+ vdd-supply: true
+ iovdd-supply: true
+
+ interrupts:
+ maxItems: 1
+
+ mount-matrix:
+ description: an optional 3x3 mounting rotation matrix.
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ # include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ accel@18 {
+ compatible = "kionix,kxsd9";
+ reg = <0x18>;
+ iovdd-supply = <&iovdd>;
+ vdd-supply = <&vdd>;
+ interrupts = <57 IRQ_TYPE_EDGE_FALLING>;
+ mount-matrix = "-0.984807753012208", "0", "-0.173648177666930",
+ "0", "-1", "0",
+ "-0.173648177666930", "0", "0.984807753012208";
+ };
+ };
+ - |
+ # include <dt-bindings/interrupt-controller/irq.h>
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ accel@0 {
+ compatible = "kionix,kxsd9";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+ };
+ };
+...
diff --git a/Bindings/iio/adc/adi,ad7606.yaml b/Bindings/iio/adc/adi,ad7606.yaml
index 5117ad68a584..cbb8819d7069 100644
--- a/Bindings/iio/adc/adi,ad7606.yaml
+++ b/Bindings/iio/adc/adi,ad7606.yaml
@@ -53,10 +53,10 @@ properties:
standby-gpios:
description:
- Must be the device tree identifier of the STBY pin. This pin is used
- to place the AD7606 into one of two power-down modes, Standby mode or
- Shutdown mode. As the line is active low, it should be marked
- GPIO_ACTIVE_LOW.
+ Must be the device tree identifier of the STBY pin. This pin is used
+ to place the AD7606 into one of two power-down modes, Standby mode or
+ Shutdown mode. As the line is active low, it should be marked
+ GPIO_ACTIVE_LOW.
maxItems: 1
adi,first-data-gpios:
diff --git a/Bindings/iio/adc/ingenic,adc.yaml b/Bindings/iio/adc/ingenic,adc.yaml
new file mode 100644
index 000000000000..9f414dbdae86
--- /dev/null
+++ b/Bindings/iio/adc/ingenic,adc.yaml
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2019-2020 Artur Rojek
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/iio/adc/ingenic,adc.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Ingenic JZ47xx ADC controller IIO bindings
+
+maintainers:
+ - Artur Rojek <contact@artur-rojek.eu>
+
+description: >
+ Industrial I/O subsystem bindings for ADC controller found in
+ Ingenic JZ47xx SoCs.
+
+ ADC clients must use the format described in iio-bindings.txt, giving
+ a phandle and IIO specifier pair ("io-channels") to the ADC controller.
+
+properties:
+ compatible:
+ enum:
+ - ingenic,jz4725b-adc
+ - ingenic,jz4740-adc
+ - ingenic,jz4770-adc
+
+ '#io-channel-cells':
+ const: 1
+ description:
+ Must be set to <1> to indicate channels are selected by index.
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: adc
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - '#io-channel-cells'
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/jz4740-cgu.h>
+ #include <dt-bindings/iio/adc/ingenic,adc.h>
+
+ adc@10070000 {
+ compatible = "ingenic,jz4740-adc";
+ #io-channel-cells = <1>;
+
+ reg = <0x10070000 0x30>;
+
+ clocks = <&cgu JZ4740_CLK_ADC>;
+ clock-names = "adc";
+
+ interrupt-parent = <&intc>;
+ interrupts = <18>;
+ };
diff --git a/Bindings/iio/adc/maxim,max1238.yaml b/Bindings/iio/adc/maxim,max1238.yaml
index a0ebb4680140..cccd3033a55b 100644
--- a/Bindings/iio/adc/maxim,max1238.yaml
+++ b/Bindings/iio/adc/maxim,max1238.yaml
@@ -10,7 +10,7 @@ maintainers:
- Jonathan Cameron <jic23@kernel.org>
description: |
- Family of simple ADCs with i2c inteface and internal references.
+ Family of simple ADCs with i2c inteface and internal references.
properties:
compatible:
diff --git a/Bindings/iio/adc/qcom,spmi-vadc.yaml b/Bindings/iio/adc/qcom,spmi-vadc.yaml
new file mode 100644
index 000000000000..0ca992465a21
--- /dev/null
+++ b/Bindings/iio/adc/qcom,spmi-vadc.yaml
@@ -0,0 +1,276 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/qcom,spmi-vadc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm's SPMI PMIC ADC
+
+maintainers:
+ - Andy Gross <agross@kernel.org>
+ - Bjorn Andersson <bjorn.andersson@linaro.org>
+
+description: |
+ SPMI PMIC voltage ADC (VADC) provides interface to clients to read
+ voltage. The VADC is a 15-bit sigma-delta ADC.
+ SPMI PMIC5/PMIC7 voltage ADC (ADC) provides interface to clients to read
+ voltage. The VADC is a 16-bit sigma-delta ADC.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: qcom,pms405-adc
+ - const: qcom,spmi-adc-rev2
+
+ - items:
+ - enum:
+ - qcom,spmi-vadc
+ - qcom,spmi-adc5
+ - qcom,spmi-adc-rev2
+ - qcom,spmi-adc7
+
+ reg:
+ description: VADC base address in the SPMI PMIC register map
+ maxItems: 1
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ '#io-channel-cells':
+ const: 1
+
+ interrupts:
+ maxItems: 1
+ description:
+ End of conversion interrupt.
+
+required:
+ - compatible
+ - reg
+ - '#address-cells'
+ - '#size-cells'
+ - '#io-channel-cells'
+
+patternProperties:
+ "^.*@[0-9a-f]+$":
+ type: object
+ description: |
+ Represents the external channels which are connected to the ADC.
+ For compatible property "qcom,spmi-vadc" following channels, also known as
+ reference point channels, are used for result calibration and their channel
+ configuration nodes should be defined:
+ VADC_REF_625MV and/or VADC_SPARE1(based on PMIC version) VADC_REF_1250MV,
+ VADC_GND_REF and VADC_VDD_VADC.
+
+ properties:
+ reg:
+ description: |
+ ADC channel number.
+ See include/dt-bindings/iio/qcom,spmi-vadc.h
+ For PMIC7 ADC, the channel numbers are specified separately per PMIC
+ in the PMIC-specific files in include/dt-bindings/iio/.
+
+ label:
+ $ref: /schemas/types.yaml#/definitions/string
+ description: |
+ ADC input of the platform as seen in the schematics.
+ For thermistor inputs connected to generic AMUX or GPIO inputs
+ these can vary across platform for the same pins. Hence select
+ the platform schematics name for this channel.
+
+ qcom,decimation:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ This parameter is used to decrease ADC sampling rate.
+ Quicker measurements can be made by reducing decimation ratio.
+
+ qcom,pre-scaling:
+ description: |
+ Used for scaling the channel input signal before the signal is
+ fed to VADC. The configuration for this node is to know the
+ pre-determined ratio and use it for post scaling. It is a pair of
+ integers, denoting the numerator and denominator of the fraction by which
+ input signal is multiplied. For example, <1 3> indicates the signal is scaled
+ down to 1/3 of its value before ADC measurement.
+ If property is not found default value depending on chip will be used.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ oneOf:
+ - items:
+ - const: 1
+ - enum: [ 1, 3, 4, 6, 20, 8, 10 ]
+ - items:
+ - const: 10
+ - const: 81
+
+ qcom,ratiometric:
+ description: |
+ Channel calibration type.
+ - For compatible property "qcom,spmi-vadc", if this property is
+ specified VADC will use the VDD reference (1.8V) and GND for
+ channel calibration. If property is not found, channel will be
+ calibrated with 0.625V and 1.25V reference channels, also
+ known as absolute calibration.
+ - For compatible property "qcom,spmi-adc5", "qcom,spmi-adc7" and
+ "qcom,spmi-adc-rev2", if this property is specified VADC will use
+ the VDD reference (1.875V) and GND for channel calibration. If
+ property is not found, channel will be calibrated with 0V and 1.25V
+ reference channels, also known as absolute calibration.
+ type: boolean
+
+ qcom,hw-settle-time:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Time between AMUX getting configured and the ADC starting
+ conversion. The 'hw_settle_time' is an index used from valid values
+ and programmed in hardware to achieve the hardware settling delay.
+
+ qcom,avg-samples:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Number of samples to be used for measurement.
+ Averaging provides the option to obtain a single measurement
+ from the ADC that is an average of multiple samples. The value
+ selected is 2^(value).
+
+ required:
+ - reg
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: qcom,spmi-vadc
+
+ then:
+ patternProperties:
+ "^.*@[0-9a-f]+$":
+ properties:
+ qcom,decimation:
+ enum: [ 512, 1024, 2048, 4096 ]
+ default: 512
+
+ qcom,hw-settle-time:
+ enum: [ 0, 100, 200, 300, 400, 500, 600, 700, 800, 900, 1, 2,
+ 4, 6, 8, 10 ]
+ default: 0
+
+ qcom,avg-samples:
+ enum: [ 1, 2, 4, 8, 16, 32, 64, 128, 256, 512 ]
+ default: 1
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: qcom,spmi-adc-rev2
+
+ then:
+ patternProperties:
+ "^.*@[0-9a-f]+$":
+ properties:
+ qcom,decimation:
+ enum: [ 256, 512, 1024 ]
+ default: 1024
+
+ qcom,hw-settle-time:
+ enum: [ 0, 100, 200, 300, 400, 500, 600, 700, 800, 900, 1, 2,
+ 4, 6, 8, 10 ]
+ default: 0
+
+ qcom,avg-samples:
+ enum: [ 1, 2, 4, 8, 16 ]
+ default: 1
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: qcom,spmi-adc5
+
+ then:
+ patternProperties:
+ "^.*@[0-9a-f]+$":
+ properties:
+ qcom,decimation:
+ enum: [ 250, 420, 840 ]
+ default: 840
+
+ qcom,hw-settle-time:
+ enum: [ 15, 100, 200, 300, 400, 500, 600, 700, 800, 900, 1, 2,
+ 4, 6, 8, 10, 16, 32, 64, 128 ]
+ default: 15
+
+ qcom,avg-samples:
+ enum: [ 1, 2, 4, 8, 16 ]
+ default: 1
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: qcom,spmi-adc7
+
+ then:
+ patternProperties:
+ "^.*@[0-9a-f]+$":
+ properties:
+ qcom,decimation:
+ enum: [ 85, 340, 1360 ]
+ default: 1360
+
+ qcom,hw-settle-time:
+ enum: [ 15, 100, 200, 300, 400, 500, 600, 700, 1000, 2000, 4000,
+ 8000, 16000, 32000, 64000, 128000 ]
+ default: 15
+
+ qcom,avg-samples:
+ enum: [ 1, 2, 4, 8, 16 ]
+ default: 1
+
+examples:
+ - |
+ spmi_bus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* VADC node */
+ pmic_vadc: adc@3100 {
+ compatible = "qcom,spmi-vadc";
+ reg = <0x3100>;
+ interrupts = <0x0 0x31 0x0 0x1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+ io-channel-ranges;
+
+ /* Channel node */
+ adc-chan@39 {
+ reg = <0x39>;
+ qcom,decimation = <512>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,avg-samples = <1>;
+ qcom,pre-scaling = <1 3>;
+ };
+
+ adc-chan@9 {
+ reg = <0x9>;
+ };
+
+ adc-chan@a {
+ reg = <0xa>;
+ };
+
+ adc-chan@e {
+ reg = <0xe>;
+ };
+
+ adc-chan@f {
+ reg = <0xf>;
+ };
+ };
+ };
diff --git a/Bindings/iio/adc/rockchip-saradc.yaml b/Bindings/iio/adc/rockchip-saradc.yaml
index bcff82a423bc..1bb76197787b 100644
--- a/Bindings/iio/adc/rockchip-saradc.yaml
+++ b/Bindings/iio/adc/rockchip-saradc.yaml
@@ -17,10 +17,10 @@ properties:
- const: rockchip,rk3399-saradc
- items:
- enum:
- - rockchip,px30-saradc
- - rockchip,rk3308-saradc
- - rockchip,rk3328-saradc
- - rockchip,rv1108-saradc
+ - rockchip,px30-saradc
+ - rockchip,rk3308-saradc
+ - rockchip,rk3328-saradc
+ - rockchip,rv1108-saradc
- const: rockchip,rk3399-saradc
reg:
diff --git a/Bindings/iio/adc/ti,ads8688.yaml b/Bindings/iio/adc/ti,ads8688.yaml
new file mode 100644
index 000000000000..97fe6cbb2efa
--- /dev/null
+++ b/Bindings/iio/adc/ti,ads8688.yaml
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/ti,ads8688.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments' ADS8684 and ADS8688 ADC chip
+
+maintainers:
+ - Sean Nyekjaer <sean@geanix.com>
+
+description: |
+ SPI 16bit ADCs with 4/8 channels.
+
+properties:
+ compatible:
+ enum:
+ - ti,ads8684
+ - ti,ads8688
+
+ reg:
+ maxItems: 1
+
+ vref-supply:
+ description: Optional external reference. If not supplied, assume
+ REFSEL input tied low to enable the internal reference.
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "ti,ads8688";
+ reg = <0>;
+ vref-supply = <&vdd_supply>;
+ spi-max-frequency = <1000000>;
+ };
+ };
+...
diff --git a/Bindings/iio/amplifiers/adi,hmc425a.yaml b/Bindings/iio/amplifiers/adi,hmc425a.yaml
index 1c6d49685e9f..5342360e96b1 100644
--- a/Bindings/iio/amplifiers/adi,hmc425a.yaml
+++ b/Bindings/iio/amplifiers/adi,hmc425a.yaml
@@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: HMC425A 6-bit Digital Step Attenuator
maintainers:
-- Michael Hennerich <michael.hennerich@analog.com>
-- Beniamin Bia <beniamin.bia@analog.com>
+ - Michael Hennerich <michael.hennerich@analog.com>
+ - Beniamin Bia <beniamin.bia@analog.com>
description: |
Digital Step Attenuator IIO device with gpio interface.
diff --git a/Bindings/iio/chemical/atlas,sensor.yaml b/Bindings/iio/chemical/atlas,sensor.yaml
index 69e8931e0ae8..9a89b34bdd8f 100644
--- a/Bindings/iio/chemical/atlas,sensor.yaml
+++ b/Bindings/iio/chemical/atlas,sensor.yaml
@@ -31,10 +31,10 @@ properties:
- atlas,co2-ezo
reg:
- maxItems: 1
+ maxItems: 1
interrupts:
- maxItems: 1
+ maxItems: 1
required:
- compatible
diff --git a/Bindings/iio/chemical/sensirion,scd30.yaml b/Bindings/iio/chemical/sensirion,scd30.yaml
new file mode 100644
index 000000000000..40d87346ff4c
--- /dev/null
+++ b/Bindings/iio/chemical/sensirion,scd30.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/chemical/sensirion,scd30.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sensirion SCD30 carbon dioxide sensor
+
+maintainers:
+ - Tomasz Duszynski <tomasz.duszynski@octakon.com>
+
+description: |
+ Air quality sensor capable of measuring co2 concentration, temperature
+ and relative humidity.
+
+properties:
+ compatible:
+ enum:
+ - sensirion,scd30
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ vdd-supply: true
+
+ sensirion,sel-gpios:
+ description: GPIO connected to the SEL line
+ maxItems: 1
+
+ sensirion,pwm-gpios:
+ description: GPIO connected to the PWM line
+ maxItems: 1
+
+required:
+ - compatible
+
+additionalProperties: false
+
+examples:
+ - |
+ # include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ co2-sensor@61 {
+ compatible = "sensirion,scd30";
+ reg = <0x61>;
+ vdd-supply = <&vdd>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+ - |
+ # include <dt-bindings/interrupt-controller/irq.h>
+ serial {
+ co2-sensor {
+ compatible = "sensirion,scd30";
+ vdd-supply = <&vdd>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+...
diff --git a/Bindings/iio/dac/adi,ad5770r.yaml b/Bindings/iio/dac/adi,ad5770r.yaml
index 58d81ca43460..82424e06be27 100644
--- a/Bindings/iio/dac/adi,ad5770r.yaml
+++ b/Bindings/iio/dac/adi,ad5770r.yaml
@@ -61,17 +61,17 @@ properties:
const: 0
adi,range-microamp:
- description: Output range of the channel.
- oneOf:
- - items:
- - const: 0
- - const: 300000
- - items:
- - const: -60000
- - const: 0
- - items:
- - const: -60000
- - const: 300000
+ description: Output range of the channel.
+ oneOf:
+ - items:
+ - const: 0
+ - const: 300000
+ - items:
+ - const: -60000
+ - const: 0
+ - items:
+ - const: -60000
+ - const: 300000
channel@1:
description: Represents an external channel which are
@@ -84,10 +84,10 @@ properties:
const: 1
adi,range-microamp:
- description: Output range of the channel.
- items:
- - const: 0
- - enum: [ 140000, 250000 ]
+ description: Output range of the channel.
+ items:
+ - const: 0
+ - enum: [140000, 250000]
channel@2:
description: Represents an external channel which are
@@ -100,10 +100,10 @@ properties:
const: 2
adi,range-microamp:
- description: Output range of the channel.
- items:
- - const: 0
- - enum: [ 55000, 150000 ]
+ description: Output range of the channel.
+ items:
+ - const: 0
+ - enum: [55000, 150000]
patternProperties:
"^channel@([3-5])$":
@@ -116,19 +116,19 @@ patternProperties:
maximum: 5
adi,range-microamp:
- description: Output range of the channel.
- items:
- - const: 0
- - enum: [ 45000, 100000 ]
+ description: Output range of the channel.
+ items:
+ - const: 0
+ - enum: [45000, 100000]
required:
-- reg
-- channel@0
-- channel@1
-- channel@2
-- channel@3
-- channel@4
-- channel@5
+ - reg
+ - channel@0
+ - channel@1
+ - channel@2
+ - channel@3
+ - channel@4
+ - channel@5
examples:
- |
diff --git a/Bindings/iio/dac/ti,dac7612.txt b/Bindings/iio/dac/ti,dac7612.txt
index 639c94ed83e9..17af395b99d9 100644
--- a/Bindings/iio/dac/ti,dac7612.txt
+++ b/Bindings/iio/dac/ti,dac7612.txt
@@ -6,7 +6,7 @@ Is is programmable through an SPI interface.
The internal DACs are loaded when the LOADDACS pin is pulled down.
-http://www.ti.com/lit/ds/sbas106/sbas106.pdf
+https://www.ti.com/lit/ds/sbas106/sbas106.pdf
Required Properties:
- compatible: Should be one of:
diff --git a/Bindings/iio/iio-bindings.txt b/Bindings/iio/iio-bindings.txt
index af33267727f4..aa63cac7323e 100644
--- a/Bindings/iio/iio-bindings.txt
+++ b/Bindings/iio/iio-bindings.txt
@@ -9,7 +9,7 @@ specifier is an array of one or more cells identifying the IIO
output on a device. The length of an IIO specifier is defined by the
value of a #io-channel-cells property in the IIO provider node.
-[1] http://marc.info/?l=linux-iio&m=135902119507483&w=2
+[1] https://marc.info/?l=linux-iio&m=135902119507483&w=2
==IIO providers==
diff --git a/Bindings/iio/imu/bosch,bmi160.yaml b/Bindings/iio/imu/bosch,bmi160.yaml
index 0d0ef84e22b9..33d8e9fd14b7 100644
--- a/Bindings/iio/imu/bosch,bmi160.yaml
+++ b/Bindings/iio/imu/bosch,bmi160.yaml
@@ -37,6 +37,15 @@ properties:
set if the specified interrupt pin should be configured as
open drain. If not set, defaults to push-pull.
+ vdd-supply:
+ description: provide VDD power to the sensor.
+
+ vddio-supply:
+ description: provide VDD IO power to the sensor.
+
+ mount-matrix:
+ description: an optional 3x3 mounting rotation matrix
+
required:
- compatible
- reg
@@ -52,9 +61,14 @@ examples:
bmi160@68 {
compatible = "bosch,bmi160";
reg = <0x68>;
+ vdd-supply = <&pm8916_l17>;
+ vddio-supply = <&pm8916_l6>;
interrupt-parent = <&gpio4>;
interrupts = <12 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "INT1";
+ mount-matrix = "0", "1", "0",
+ "-1", "0", "0",
+ "0", "0", "1";
};
};
- |
diff --git a/Bindings/iio/imu/invensense,icm42600.yaml b/Bindings/iio/imu/invensense,icm42600.yaml
new file mode 100644
index 000000000000..abd8d25e1136
--- /dev/null
+++ b/Bindings/iio/imu/invensense,icm42600.yaml
@@ -0,0 +1,90 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/imu/invensense,icm42600.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: InvenSense ICM-426xx Inertial Measurement Unit
+
+maintainers:
+ - Jean-Baptiste Maneyrol <jmaneyrol@invensense.com>
+
+description: |
+ 6-axis MotionTracking device that combines a 3-axis gyroscope and a 3-axis
+ accelerometer.
+
+ It has a configurable host interface that supports I3C, I2C and SPI serial
+ communication, features a 2kB FIFO and 2 programmable interrupts with
+ ultra-low-power wake-on-motion support to minimize system power consumption.
+
+ Other industry-leading features include InvenSense on-chip APEX Motion
+ Processing engine for gesture recognition, activity classification, and
+ pedometer, along with programmable digital filters, and an embedded
+ temperature sensor.
+
+ https://invensense.tdk.com/wp-content/uploads/2020/03/DS-000292-ICM-42605-v1.4.pdf
+
+properties:
+ compatible:
+ enum:
+ - invensense,icm42600
+ - invensense,icm42602
+ - invensense,icm42605
+ - invensense,icm42622
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ drive-open-drain:
+ type: boolean
+
+ vdd-supply:
+ description: Regulator that provides power to the sensor
+
+ vddio-supply:
+ description: Regulator that provides power to the bus
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ icm42605@68 {
+ compatible = "invensense,icm42605";
+ reg = <0x68>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
+ vdd-supply = <&vdd>;
+ vddio-supply = <&vddio>;
+ };
+ };
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ spi0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ icm42602@0 {
+ compatible = "invensense,icm42602";
+ reg = <0>;
+ spi-max-frequency = <24000000>;
+ spi-cpha;
+ spi-cpol;
+ interrupt-parent = <&gpio1>;
+ interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
+ vdd-supply = <&vdd>;
+ vddio-supply = <&vddio>;
+ };
+ };
diff --git a/Bindings/iio/light/apds9300.txt b/Bindings/iio/light/apds9300.txt
index aa199e09a493..3aa6db3ee99d 100644
--- a/Bindings/iio/light/apds9300.txt
+++ b/Bindings/iio/light/apds9300.txt
@@ -1,6 +1,6 @@
* Avago APDS9300 ambient light sensor
-http://www.avagotech.com/docs/AV02-1077EN
+https://www.avagotech.com/docs/AV02-1077EN
Required properties:
diff --git a/Bindings/iio/light/apds9960.txt b/Bindings/iio/light/apds9960.txt
index 3af325ad194b..c53ddb81c4aa 100644
--- a/Bindings/iio/light/apds9960.txt
+++ b/Bindings/iio/light/apds9960.txt
@@ -1,6 +1,6 @@
* Avago APDS9960 gesture/RGB/ALS/proximity sensor
-http://www.avagotech.com/docs/AV02-4191EN
+https://www.avagotech.com/docs/AV02-4191EN
Required properties:
diff --git a/Bindings/iio/light/opt3001.txt b/Bindings/iio/light/opt3001.txt
index 47b13eb8f4ec..9e6f2998e751 100644
--- a/Bindings/iio/light/opt3001.txt
+++ b/Bindings/iio/light/opt3001.txt
@@ -6,7 +6,7 @@ the optional generation of IIO events on rising/falling light threshold changes
requires the use of interrupts. Without interrupts, only the simple reading
of the current light value is supported through the IIO API.
-http://www.ti.com/product/opt3001
+https://www.ti.com/product/opt3001
Required properties:
- compatible: should be "ti,opt3001"
diff --git a/Bindings/iio/light/vishay,vcnl4000.yaml b/Bindings/iio/light/vishay,vcnl4000.yaml
index da8f2e872535..58887a4f9c15 100644
--- a/Bindings/iio/light/vishay,vcnl4000.yaml
+++ b/Bindings/iio/light/vishay,vcnl4000.yaml
@@ -36,15 +36,15 @@ required:
additionalProperties: false
examples:
-- |
- i2c {
- #address-cells = <1>;
- #size-cells = <0>;
-
- light-sensor@51 {
- compatible = "vishay,vcnl4200";
- reg = <0x51>;
- proximity-near-level = <220>;
- };
- };
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ light-sensor@51 {
+ compatible = "vishay,vcnl4200";
+ reg = <0x51>;
+ proximity-near-level = <220>;
+ };
+ };
...
diff --git a/Bindings/iio/light/vl6180.txt b/Bindings/iio/light/vl6180.txt
index 2c52952715a0..fb9137d85df9 100644
--- a/Bindings/iio/light/vl6180.txt
+++ b/Bindings/iio/light/vl6180.txt
@@ -1,6 +1,6 @@
STMicro VL6180 - ALS, range and proximity sensor
-Link to datasheet: http://www.st.com/resource/en/datasheet/vl6180x.pdf
+Link to datasheet: https://www.st.com/resource/en/datasheet/vl6180x.pdf
Required properties:
diff --git a/Bindings/iio/magnetometer/asahi-kasei,ak8975.yaml b/Bindings/iio/magnetometer/asahi-kasei,ak8975.yaml
new file mode 100644
index 000000000000..f0b336ac39c9
--- /dev/null
+++ b/Bindings/iio/magnetometer/asahi-kasei,ak8975.yaml
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/magnetometer/asahi-kasei,ak8975.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: AsahiKASEI AK8975 magnetometer sensor
+
+maintainers:
+ - Jonathan Albrieux <jonathan.albrieux@gmail.com>
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - asahi-kasei,ak8975
+ - asahi-kasei,ak8963
+ - asahi-kasei,ak09911
+ - asahi-kasei,ak09912
+ - enum:
+ - ak8975
+ - ak8963
+ - ak09911
+ - ak09912
+ deprecated: true
+
+ reg:
+ maxItems: 1
+
+ gpios:
+ maxItems: 1
+ description: |
+ AK8975 has a "Data ready" pin (DRDY) which informs that data
+ is ready to be read and is possible to listen on it. If used,
+ this should be active high. Prefer interrupt over this.
+
+ interrupts:
+ maxItems: 1
+ description: interrupt for DRDY pin. Triggered on rising edge.
+
+ vdd-supply:
+ description: |
+ an optional regulator that needs to be on to provide VDD power to
+ the sensor.
+
+ mount-matrix:
+ description: an optional 3x3 mounting rotation matrix.
+
+ reset-gpios:
+ description: |
+ an optional pin needed for AK09911 to set the reset state. This should
+ be usually active low
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/gpio/gpio.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ magnetometer@c {
+ compatible = "asahi-kasei,ak8975";
+ reg = <0x0c>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <15 IRQ_TYPE_EDGE_RISING>;
+ vdd-supply = <&ldo_3v3_gnss>;
+ reset-gpios = <&msmgpio 111 GPIO_ACTIVE_LOW>;
+ mount-matrix = "-0.984807753012208", /* x0 */
+ "0", /* y0 */
+ "-0.173648177666930", /* z0 */
+ "0", /* x1 */
+ "-1", /* y1 */
+ "0", /* z1 */
+ "-0.173648177666930", /* x2 */
+ "0", /* y2 */
+ "0.984807753012208"; /* z2 */
+ };
+ };
diff --git a/Bindings/iio/magnetometer/bmc150_magn.txt b/Bindings/iio/magnetometer/bmc150_magn.txt
index fd5fca90fb39..22912e43b60c 100644
--- a/Bindings/iio/magnetometer/bmc150_magn.txt
+++ b/Bindings/iio/magnetometer/bmc150_magn.txt
@@ -4,7 +4,11 @@ http://ae-bst.resource.bosch.com/media/products/dokumente/bmc150/BST-BMC150-DS00
Required properties:
- - compatible : should be "bosch,bmc150_magn"
+ - compatible : should be one of:
+ "bosch,bmc150_magn"
+ "bosch,bmc156_magn"
+ "bosch,bmm150"
+ "bosch,bmm150_magn" (DEPRECATED, use bosch,bmm150)
- reg : the I2C address of the magnetometer
Optional properties:
diff --git a/Bindings/iio/multiplexer/io-channel-mux.txt b/Bindings/iio/multiplexer/io-channel-mux.txt
index c82794002595..89647d714387 100644
--- a/Bindings/iio/multiplexer/io-channel-mux.txt
+++ b/Bindings/iio/multiplexer/io-channel-mux.txt
@@ -21,7 +21,7 @@ controller state. The mux controller state is described in
Example:
mux: mux-controller {
- compatible = "mux-gpio";
+ compatible = "gpio-mux";
#mux-control-cells = <0>;
mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>,
diff --git a/Bindings/iio/potentiometer/mcp41010.txt b/Bindings/iio/potentiometer/mcp41010.txt
index 566711b9950c..4f245e8469fd 100644
--- a/Bindings/iio/potentiometer/mcp41010.txt
+++ b/Bindings/iio/potentiometer/mcp41010.txt
@@ -1,7 +1,7 @@
* Microchip MCP41010/41050/41100/42010/42050/42100 Digital Potentiometer
Datasheet publicly available at:
-http://ww1.microchip.com/downloads/en/devicedoc/11195c.pdf
+https://ww1.microchip.com/downloads/en/devicedoc/11195c.pdf
The node for this driver must be a child node of a SPI controller, hence
all mandatory properties described in
diff --git a/Bindings/iio/potentiostat/lmp91000.txt b/Bindings/iio/potentiostat/lmp91000.txt
index e6d0c2eb345c..f3ab02b0dd41 100644
--- a/Bindings/iio/potentiostat/lmp91000.txt
+++ b/Bindings/iio/potentiostat/lmp91000.txt
@@ -1,7 +1,7 @@
* Texas Instruments LMP91000 series of potentiostats
-LMP91000: http://www.ti.com/lit/ds/symlink/lmp91000.pdf
-LMP91002: http://www.ti.com/lit/ds/symlink/lmp91002.pdf
+LMP91000: https://www.ti.com/lit/ds/symlink/lmp91000.pdf
+LMP91002: https://www.ti.com/lit/ds/symlink/lmp91002.pdf
Required properties:
diff --git a/Bindings/iio/pressure/asc,dlhl60d.yaml b/Bindings/iio/pressure/asc,dlhl60d.yaml
index 64c18f1693f0..be2be4b556db 100644
--- a/Bindings/iio/pressure/asc,dlhl60d.yaml
+++ b/Bindings/iio/pressure/asc,dlhl60d.yaml
@@ -13,7 +13,7 @@ description: |
Bindings for the All Sensors DLH series pressure sensors.
Specifications about the sensors can be found at:
- http://www.allsensors.com/cad/DS-0355_Rev_B.PDF
+ https://www.allsensors.com/cad/DS-0355_Rev_B.PDF
properties:
compatible:
diff --git a/Bindings/iio/proximity/devantech-srf04.yaml b/Bindings/iio/proximity/devantech-srf04.yaml
index f86f8b23ef18..ce795279839e 100644
--- a/Bindings/iio/proximity/devantech-srf04.yaml
+++ b/Bindings/iio/proximity/devantech-srf04.yaml
@@ -17,9 +17,9 @@ description: |
until it is received once again
Specifications about the devices can be found at:
- http://www.robot-electronics.co.uk/htm/srf04tech.htm
+ https://www.robot-electronics.co.uk/htm/srf04tech.htm
- http://www.maxbotix.com/documents/LV-MaxSonar-EZ_Datasheet.pdf
+ https://www.maxbotix.com/documents/LV-MaxSonar-EZ_Datasheet.pdf
properties:
compatible:
diff --git a/Bindings/iio/proximity/vishay,vcnl3020.yaml b/Bindings/iio/proximity/vishay,vcnl3020.yaml
index 4190253336ec..51dba64037f6 100644
--- a/Bindings/iio/proximity/vishay,vcnl3020.yaml
+++ b/Bindings/iio/proximity/vishay,vcnl3020.yaml
@@ -39,8 +39,8 @@ properties:
description:
The driver current for the LED used in proximity sensing.
enum: [0, 10000, 20000, 30000, 40000, 50000, 60000, 70000, 80000, 90000,
- 100000, 110000, 120000, 130000, 140000, 150000, 160000, 170000,
- 180000, 190000, 200000]
+ 100000, 110000, 120000, 130000, 140000, 150000, 160000, 170000,
+ 180000, 190000, 200000]
default: 20000
required:
diff --git a/Bindings/iio/temperature/adi,ltc2983.yaml b/Bindings/iio/temperature/adi,ltc2983.yaml
index 40ccbe7b5c13..0f79d9a01c49 100644
--- a/Bindings/iio/temperature/adi,ltc2983.yaml
+++ b/Bindings/iio/temperature/adi,ltc2983.yaml
@@ -307,7 +307,7 @@ patternProperties:
mode.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 250, 500, 1000, 5000, 10000, 25000, 50000, 100000, 250000,
- 500000, 1000000]
+ 500000, 1000000]
adi,custom-thermistor:
description:
diff --git a/Bindings/input/imx-keypad.yaml b/Bindings/input/imx-keypad.yaml
new file mode 100644
index 000000000000..f21db81206b4
--- /dev/null
+++ b/Bindings/input/imx-keypad.yaml
@@ -0,0 +1,85 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/input/imx-keypad.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX Keypad Port(KPP) device tree bindings
+
+maintainers:
+ - Liu Ying <gnuiyl@gmail.com>
+
+allOf:
+ - $ref: "/schemas/input/matrix-keymap.yaml#"
+
+description: |
+ The KPP is designed to interface with a keypad matrix with 2-point contact
+ or 3-point contact keys. The KPP is designed to simplify the software task
+ of scanning a keypad matrix. The KPP is capable of detecting, debouncing,
+ and decoding one or multiple keys pressed simultaneously on a keypad.
+
+properties:
+ compatible:
+ oneOf:
+ - const: fsl,imx21-kpp
+ - items:
+ - enum:
+ - fsl,imx25-kpp
+ - fsl,imx27-kpp
+ - fsl,imx31-kpp
+ - fsl,imx35-kpp
+ - fsl,imx51-kpp
+ - fsl,imx53-kpp
+ - fsl,imx50-kpp
+ - fsl,imx6q-kpp
+ - fsl,imx6sx-kpp
+ - fsl,imx6sl-kpp
+ - fsl,imx6sll-kpp
+ - fsl,imx6ul-kpp
+ - fsl,imx7d-kpp
+ - const: fsl,imx21-kpp
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - linux,keymap
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ keypad@73f94000 {
+ compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
+ reg = <0x73f94000 0x4000>;
+ interrupts = <60>;
+ clocks = <&clks 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_kpp_1>;
+ linux,keymap = <0x00000067 /* KEY_UP */
+ 0x0001006c /* KEY_DOWN */
+ 0x00020072 /* KEY_VOLUMEDOWN */
+ 0x00030066 /* KEY_HOME */
+ 0x0100006a /* KEY_RIGHT */
+ 0x01010069 /* KEY_LEFT */
+ 0x0102001c /* KEY_ENTER */
+ 0x01030073 /* KEY_VOLUMEUP */
+ 0x02000040 /* KEY_F6 */
+ 0x02010042 /* KEY_F8 */
+ 0x02020043 /* KEY_F9 */
+ 0x02030044 /* KEY_F10 */
+ 0x0300003b /* KEY_F1 */
+ 0x0301003c /* KEY_F2 */
+ 0x0302003d /* KEY_F3 */
+ 0x03030074>; /* KEY_POWER */
+ };
diff --git a/Bindings/input/matrix-keymap.txt b/Bindings/input/matrix-keymap.txt
index c54919fad17e..79f6d01aecaa 100644
--- a/Bindings/input/matrix-keymap.txt
+++ b/Bindings/input/matrix-keymap.txt
@@ -1,27 +1 @@
-A simple common binding for matrix-connected key boards. Currently targeted at
-defining the keys in the scope of linux key codes since that is a stable and
-standardized interface at this time.
-
-Required properties:
-- linux,keymap: an array of packed 1-cell entries containing the equivalent
- of row, column and linux key-code. The 32-bit big endian cell is packed
- as:
- row << 24 | column << 16 | key-code
-
-Optional properties:
-Properties for the number of rows and columns are optional because some
-drivers will use fixed values for these.
-- keypad,num-rows: Number of row lines connected to the keypad controller.
-- keypad,num-columns: Number of column lines connected to the keypad
- controller.
-
-Some users of this binding might choose to specify secondary keymaps for
-cases where there is a modifier key such as a Fn key. Proposed names
-for said properties are "linux,fn-keymap" or with another descriptive
-word for the modifier other from "Fn".
-
-Example:
- linux,keymap = < 0x00030012
- 0x0102003a >;
- keypad,num-rows = <2>;
- keypad,num-columns = <8>;
+This file has been moved to matrix-keymap.yaml
diff --git a/Bindings/input/matrix-keymap.yaml b/Bindings/input/matrix-keymap.yaml
new file mode 100644
index 000000000000..c3bf09156783
--- /dev/null
+++ b/Bindings/input/matrix-keymap.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/input/matrix-keymap.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Common key matrices binding for matrix-connected key boards
+
+maintainers:
+ - Olof Johansson <olof@lixom.net>
+
+description: |
+ A simple common binding for matrix-connected key boards. Currently targeted at
+ defining the keys in the scope of linux key codes since that is a stable and
+ standardized interface at this time.
+
+ Some users of this binding might choose to specify secondary keymaps for
+ cases where there is a modifier key such as a Fn key. Proposed names
+ for said properties are "linux,fn-keymap" or with another descriptive
+ word for the modifier other from "Fn".
+
+properties:
+ linux,keymap:
+ $ref: '/schemas/types.yaml#/definitions/uint32-array'
+ description: |
+ An array of packed 1-cell entries containing the equivalent of row,
+ column and linux key-code. The 32-bit big endian cell is packed as:
+ row << 24 | column << 16 | key-code
+
+ keypad,num-rows:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Number of row lines connected to the keypad controller.
+
+ keypad,num-columns:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Number of column lines connected to the keypad controller.
+
+examples:
+ - |
+ keypad {
+ /* ... */
+ linux,keymap = < 0x00030012
+ 0x0102003a >;
+ keypad,num-rows = <2>;
+ keypad,num-columns = <8>;
+ };
diff --git a/Bindings/input/touchscreen/cypress,cy8ctma140.yaml b/Bindings/input/touchscreen/cypress,cy8ctma140.yaml
index 8c73e5264312..3225c8d1fdaf 100644
--- a/Bindings/input/touchscreen/cypress,cy8ctma140.yaml
+++ b/Bindings/input/touchscreen/cypress,cy8ctma140.yaml
@@ -51,7 +51,7 @@ required:
- touchscreen-max-pressure
examples:
-- |
+ - |
#include <dt-bindings/interrupt-controller/irq.h>
i2c {
#address-cells = <1>;
diff --git a/Bindings/input/touchscreen/edt-ft5x06.yaml b/Bindings/input/touchscreen/edt-ft5x06.yaml
index 024b262a2ef7..4ce109476a0e 100644
--- a/Bindings/input/touchscreen/edt-ft5x06.yaml
+++ b/Bindings/input/touchscreen/edt-ft5x06.yaml
@@ -20,11 +20,11 @@ maintainers:
allOf:
- $ref: touchscreen.yaml#
- if:
- properties:
- compatible:
- contains:
- enum:
- - evervision,ev-ft5726
+ properties:
+ compatible:
+ contains:
+ enum:
+ - evervision,ev-ft5726
then:
properties:
diff --git a/Bindings/input/touchscreen/eeti,exc3000.yaml b/Bindings/input/touchscreen/eeti,exc3000.yaml
new file mode 100644
index 000000000000..007adbc89c14
--- /dev/null
+++ b/Bindings/input/touchscreen/eeti,exc3000.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/input/touchscreen/eeti,exc3000.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: EETI EXC3000 series touchscreen controller
+
+maintainers:
+ - Dmitry Torokhov <dmitry.torokhov@gmail.com>
+
+allOf:
+ - $ref: touchscreen.yaml#
+
+properties:
+ compatible:
+ enum:
+ - eeti,exc3000
+ - eeti,exc80h60
+ - eeti,exc80h84
+ reg:
+ const: 0x2a
+ interrupts:
+ maxItems: 1
+ reset-gpios:
+ maxItems: 1
+ touchscreen-size-x: true
+ touchscreen-size-y: true
+ touchscreen-inverted-x: true
+ touchscreen-inverted-y: true
+ touchscreen-swapped-x-y: true
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - touchscreen-size-x
+ - touchscreen-size-y
+
+additionalProperties: false
+
+examples:
+ - |
+ #include "dt-bindings/interrupt-controller/irq.h"
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ touchscreen@2a {
+ compatible = "eeti,exc3000";
+ reg = <0x2a>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
+ touchscreen-size-x = <4096>;
+ touchscreen-size-y = <4096>;
+ touchscreen-inverted-x;
+ touchscreen-swapped-x-y;
+ };
+ };
diff --git a/Bindings/input/touchscreen/goodix.yaml b/Bindings/input/touchscreen/goodix.yaml
index e81cfa56f25a..da5b0d87e16d 100644
--- a/Bindings/input/touchscreen/goodix.yaml
+++ b/Bindings/input/touchscreen/goodix.yaml
@@ -35,9 +35,8 @@ properties:
maxItems: 1
irq-gpios:
- description: GPIO pin used for IRQ.
- The driver uses the interrupt gpio pin as
- output to reset the device.
+ description: GPIO pin used for IRQ. The driver uses the interrupt gpio pin
+ as output to reset the device.
maxItems: 1
reset-gpios:
diff --git a/Bindings/input/touchscreen/touchscreen.yaml b/Bindings/input/touchscreen/touchscreen.yaml
index d7dac16a3960..36dc7b56a453 100644
--- a/Bindings/input/touchscreen/touchscreen.yaml
+++ b/Bindings/input/touchscreen/touchscreen.yaml
@@ -33,8 +33,8 @@ properties:
$ref: /schemas/types.yaml#/definitions/uint32
touchscreen-min-pressure:
- description: minimum pressure on the touchscreen to be achieved in order for the
- touchscreen driver to report a touch event.
+ description: minimum pressure on the touchscreen to be achieved in order
+ for the touchscreen driver to report a touch event.
$ref: /schemas/types.yaml#/definitions/uint32
touchscreen-fuzz-x:
@@ -46,13 +46,13 @@ properties:
$ref: /schemas/types.yaml#/definitions/uint32
touchscreen-fuzz-pressure:
- description: pressure noise value of the absolute input device (arbitrary range
- dependent on the controller)
+ description: pressure noise value of the absolute input device (arbitrary
+ range dependent on the controller)
$ref: /schemas/types.yaml#/definitions/uint32
touchscreen-average-samples:
- description: Number of data samples which are averaged for each read (valid values
- dependent on the controller)
+ description: Number of data samples which are averaged for each read (valid
+ values dependent on the controller)
$ref: /schemas/types.yaml#/definitions/uint32
touchscreen-inverted-x:
diff --git a/Bindings/interconnect/fsl,imx8m-noc.yaml b/Bindings/interconnect/fsl,imx8m-noc.yaml
index ff09550ad959..a8873739d61a 100644
--- a/Bindings/interconnect/fsl,imx8m-noc.yaml
+++ b/Bindings/interconnect/fsl,imx8m-noc.yaml
@@ -25,17 +25,17 @@ properties:
compatible:
oneOf:
- items:
- - enum:
- - fsl,imx8mn-nic
- - fsl,imx8mm-nic
- - fsl,imx8mq-nic
- - const: fsl,imx8m-nic
+ - enum:
+ - fsl,imx8mn-nic
+ - fsl,imx8mm-nic
+ - fsl,imx8mq-nic
+ - const: fsl,imx8m-nic
- items:
- - enum:
- - fsl,imx8mn-noc
- - fsl,imx8mm-noc
- - fsl,imx8mq-noc
- - const: fsl,imx8m-noc
+ - enum:
+ - fsl,imx8mn-noc
+ - fsl,imx8mm-noc
+ - fsl,imx8mq-noc
+ - const: fsl,imx8m-noc
- const: fsl,imx8m-nic
reg:
diff --git a/Bindings/interconnect/qcom,sc7180.yaml b/Bindings/interconnect/qcom,sc7180.yaml
index d01bac80d416..8659048f92a7 100644
--- a/Bindings/interconnect/qcom,sc7180.yaml
+++ b/Bindings/interconnect/qcom,sc7180.yaml
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/interconnect/qcom,sc7180.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Qualcomm SC7180 Network-On-Chip Interconnect
+title: Qualcomm SC7180 Network-On-Chip Interconnect
maintainers:
- Odelu Kukatla <okukatla@codeaurora.org>
diff --git a/Bindings/interconnect/qcom,sdm845.yaml b/Bindings/interconnect/qcom,sdm845.yaml
index 74536747b51d..dab17c0716ce 100644
--- a/Bindings/interconnect/qcom,sdm845.yaml
+++ b/Bindings/interconnect/qcom,sdm845.yaml
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/interconnect/qcom,sdm845.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Qualcomm SDM845 Network-On-Chip Interconnect
+title: Qualcomm SDM845 Network-On-Chip Interconnect
maintainers:
- Georgi Djakov <georgi.djakov@linaro.org>
diff --git a/Bindings/interrupt-controller/arm,gic.yaml b/Bindings/interrupt-controller/arm,gic.yaml
index 96f8803ff4e6..06889963dfb7 100644
--- a/Bindings/interrupt-controller/arm,gic.yaml
+++ b/Bindings/interrupt-controller/arm,gic.yaml
@@ -42,8 +42,8 @@ properties:
- items:
- const: arm,gic-400
- enum:
- - arm,cortex-a15-gic
- - arm,cortex-a7-gic
+ - arm,cortex-a15-gic
+ - arm,cortex-a7-gic
- items:
- const: arm,arm1176jzf-devchip-gic
diff --git a/Bindings/interrupt-controller/brcm,l2-intc.txt b/Bindings/interrupt-controller/brcm,l2-intc.txt
index d514ec060a4a..021cf822395c 100644
--- a/Bindings/interrupt-controller/brcm,l2-intc.txt
+++ b/Bindings/interrupt-controller/brcm,l2-intc.txt
@@ -2,7 +2,10 @@ Broadcom Generic Level 2 Interrupt Controller
Required properties:
-- compatible: should be "brcm,l2-intc" for latched interrupt controllers
+- compatible: should be one of:
+ "brcm,hif-spi-l2-intc" or
+ "brcm,upg-aux-aon-l2-intc" or
+ "brcm,l2-intc" for latched interrupt controllers
should be "brcm,bcm7271-l2-intc" for level interrupt controllers
- reg: specifies the base physical address and size of the registers
- interrupt-controller: identifies the node as an interrupt controller
diff --git a/Bindings/interrupt-controller/ingenic,intc.yaml b/Bindings/interrupt-controller/ingenic,intc.yaml
index 28b27e1a6e9d..02a3cf470518 100644
--- a/Bindings/interrupt-controller/ingenic,intc.yaml
+++ b/Bindings/interrupt-controller/ingenic,intc.yaml
@@ -16,20 +16,20 @@ properties:
compatible:
oneOf:
- enum:
- - ingenic,jz4740-intc
- - ingenic,jz4760-intc
- - ingenic,jz4780-intc
+ - ingenic,jz4740-intc
+ - ingenic,jz4760-intc
+ - ingenic,jz4780-intc
- items:
- - enum:
- - ingenic,jz4775-intc
- - ingenic,jz4770-intc
- - const: ingenic,jz4760-intc
+ - enum:
+ - ingenic,jz4775-intc
+ - ingenic,jz4770-intc
+ - const: ingenic,jz4760-intc
- items:
- - const: ingenic,x1000-intc
- - const: ingenic,jz4780-intc
+ - const: ingenic,x1000-intc
+ - const: ingenic,jz4780-intc
- items:
- - const: ingenic,jz4725b-intc
- - const: ingenic,jz4740-intc
+ - const: ingenic,jz4725b-intc
+ - const: ingenic,jz4740-intc
"#interrupt-cells":
const: 1
diff --git a/Bindings/interrupt-controller/loongson,htvec.yaml b/Bindings/interrupt-controller/loongson,htvec.yaml
index e865cd8f96a9..87a74558204f 100644
--- a/Bindings/interrupt-controller/loongson,htvec.yaml
+++ b/Bindings/interrupt-controller/loongson,htvec.yaml
@@ -22,8 +22,8 @@ properties:
interrupts:
minItems: 1
- maxItems: 4
- description: Four parent interrupts that receive chained interrupts.
+ maxItems: 8
+ description: Eight parent interrupts that receive chained interrupts.
interrupt-controller: true
diff --git a/Bindings/interrupt-controller/loongson,liointc.yaml b/Bindings/interrupt-controller/loongson,liointc.yaml
index b1db21ed44e9..03fc4f5b4b39 100644
--- a/Bindings/interrupt-controller/loongson,liointc.yaml
+++ b/Bindings/interrupt-controller/loongson,liointc.yaml
@@ -51,8 +51,8 @@ properties:
description: |
This property points how the children interrupts will be mapped into CPU
interrupt lines. Each cell refers to a parent interrupt line from 0 to 3
- and each bit in the cell refers to a children interrupt fron 0 to 31.
- If a CPU interrupt line didn't connected with liointc, then keep it's
+ and each bit in the cell refers to a child interrupt from 0 to 31.
+ If a CPU interrupt line didn't connect with liointc, then keep its
cell with zero.
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 4
diff --git a/Bindings/interrupt-controller/mrvl,intc.yaml b/Bindings/interrupt-controller/mrvl,intc.yaml
new file mode 100644
index 000000000000..372ccbfae771
--- /dev/null
+++ b/Bindings/interrupt-controller/mrvl,intc.yaml
@@ -0,0 +1,134 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/mrvl,intc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Marvell MMP/Orion Interrupt controller bindings
+
+maintainers:
+ - Thomas Gleixner <tglx@linutronix.de>
+ - Jason Cooper <jason@lakedaemon.net>
+ - Marc Zyngier <maz@kernel.org>
+ - Rob Herring <robh+dt@kernel.org>
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ not:
+ contains:
+ const: marvell,orion-intc
+ then:
+ required:
+ - mrvl,intc-nr-irqs
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - mrvl,mmp-intc
+ - mrvl,mmp2-intc
+ then:
+ properties:
+ reg:
+ maxItems: 1
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - marvell,mmp3-intc
+ - mrvl,mmp2-mux-intc
+ then:
+ properties:
+ reg:
+ minItems: 2
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: mrvl,mmp2-mux-intc
+ then:
+ properties:
+ interrupts:
+ maxItems: 1
+ reg-names:
+ items:
+ - const: 'mux status'
+ - const: 'mux mask'
+ required:
+ - interrupts
+ else:
+ properties:
+ interrupts: false
+
+properties:
+ '#interrupt-cells':
+ const: 1
+
+ compatible:
+ enum:
+ - mrvl,mmp-intc
+ - mrvl,mmp2-intc
+ - marvell,mmp3-intc
+ - marvell,orion-intc
+ - mrvl,mmp2-mux-intc
+
+ reg:
+ minItems: 1
+ maxItems: 2
+
+ reg-names: true
+
+ interrupts: true
+
+ interrupt-controller: true
+
+ mrvl,intc-nr-irqs:
+ description: |
+ Specifies the number of interrupts in the interrupt controller.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ mrvl,clr-mfp-irq:
+ description: |
+ Specifies the interrupt that needs to clear MFP edge detection first.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+required:
+ - '#interrupt-cells'
+ - compatible
+ - reg
+ - interrupt-controller
+
+additionalProperties: false
+
+examples:
+ - |
+ interrupt-controller@d4282000 {
+ compatible = "mrvl,mmp2-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0xd4282000 0x1000>;
+ mrvl,intc-nr-irqs = <64>;
+ };
+
+ interrupt-controller@d4282150 {
+ compatible = "mrvl,mmp2-mux-intc";
+ interrupts = <4>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x150 0x4>, <0x168 0x4>;
+ reg-names = "mux status", "mux mask";
+ mrvl,intc-nr-irqs = <2>;
+ };
+ - |
+ interrupt-controller@fed20204 {
+ compatible = "marvell,orion-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0xfed20204 0x04>,
+ <0xfed20214 0x04>;
+ };
+
+...
diff --git a/Bindings/interrupt-controller/mti,gic.yaml b/Bindings/interrupt-controller/mti,gic.yaml
new file mode 100644
index 000000000000..ce6aaff15214
--- /dev/null
+++ b/Bindings/interrupt-controller/mti,gic.yaml
@@ -0,0 +1,146 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MIPS Global Interrupt Controller
+
+maintainers:
+ - Paul Burton <paulburton@kernel.org>
+ - Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+
+description: |
+ The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
+ It also supports local (per-processor) interrupts and software-generated
+ interrupts which can be used as IPIs. The GIC also includes a free-running
+ global timer, per-CPU count/compare timers, and a watchdog.
+
+properties:
+ compatible:
+ const: mti,gic
+
+ "#interrupt-cells":
+ const: 3
+ description: |
+ The 1st cell is the type of interrupt: local or shared defined in the
+ file 'dt-bindings/interrupt-controller/mips-gic.h'. The 2nd cell is the
+ GIC interrupt number. The 3d cell encodes the interrupt flags setting up
+ the IRQ trigger modes, which are defined in the file
+ 'dt-bindings/interrupt-controller/irq.h'.
+
+ reg:
+ description: |
+ Base address and length of the GIC registers space. If not present,
+ the base address reported by the hardware GCR_GIC_BASE will be used.
+ maxItems: 1
+
+ interrupt-controller: true
+
+ mti,reserved-cpu-vectors:
+ description: |
+ Specifies the list of CPU interrupt vectors to which the GIC may not
+ route interrupts. This property is ignored if the CPU is started in EIC
+ mode.
+ $ref: /schemas/types.yaml#definitions/uint32-array
+ minItems: 1
+ maxItems: 6
+ uniqueItems: true
+ items:
+ minimum: 2
+ maximum: 7
+
+ mti,reserved-ipi-vectors:
+ description: |
+ Specifies the range of GIC interrupts that are reserved for IPIs.
+ It accepts two values: the 1st is the starting interrupt and the 2nd is
+ the size of the reserved range. If not specified, the driver will
+ allocate the last (2 * number of VPEs in the system).
+ $ref: /schemas/types.yaml#definitions/uint32-array
+ items:
+ - minimum: 0
+ maximum: 254
+ - minimum: 2
+ maximum: 254
+
+ timer:
+ type: object
+ description: |
+ MIPS GIC includes a free-running global timer, per-CPU count/compare
+ timers, and a watchdog. Currently only the GIC Timer is supported.
+ properties:
+ compatible:
+ const: mti,gic-timer
+
+ interrupts:
+ description: |
+ Interrupt for the GIC local timer, so normally it's suppose to be of
+ <GIC_LOCAL X IRQ_TYPE_NONE> format.
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-frequency: true
+
+ required:
+ - compatible
+ - interrupts
+
+ oneOf:
+ - required:
+ - clocks
+ - required:
+ - clock-frequency
+
+ additionalProperties: false
+
+unevaluatedProperties: false
+
+required:
+ - compatible
+ - "#interrupt-cells"
+ - interrupt-controller
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/mips-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ interrupt-controller@1bdc0000 {
+ compatible = "mti,gic";
+ reg = <0x1bdc0000 0x20000>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ mti,reserved-cpu-vectors = <7>;
+ mti,reserved-ipi-vectors = <40 8>;
+
+ timer {
+ compatible = "mti,gic-timer";
+ interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
+ clock-frequency = <50000000>;
+ };
+ };
+ - |
+ #include <dt-bindings/interrupt-controller/mips-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ interrupt-controller@1bdc0000 {
+ compatible = "mti,gic";
+ reg = <0x1bdc0000 0x20000>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
+ timer {
+ compatible = "mti,gic-timer";
+ interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
+ clocks = <&cpu_pll>;
+ };
+ };
+ - |
+ interrupt-controller {
+ compatible = "mti,gic";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+...
diff --git a/Bindings/interrupt-controller/renesas,rza1-irqc.yaml b/Bindings/interrupt-controller/renesas,rza1-irqc.yaml
new file mode 100644
index 000000000000..755cdfabfcd0
--- /dev/null
+++ b/Bindings/interrupt-controller/renesas,rza1-irqc.yaml
@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/renesas,rza1-irqc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/A1 Interrupt Controller
+
+maintainers:
+ - Chris Brandt <chris.brandt@renesas.com>
+ - Geert Uytterhoeven <geert+renesas@glider.be>
+
+description: |
+ The RZ/A1 Interrupt Controller is a front-end for the GIC found on Renesas RZ/A1 and
+ RZ/A2 SoCs:
+ - IRQ sense select for 8 external interrupts, 1:1-mapped to 8 GIC SPI interrupts,
+ - NMI edge select.
+
+allOf:
+ - $ref: /schemas/interrupt-controller.yaml#
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - renesas,r7s72100-irqc # RZ/A1H
+ - renesas,r7s9210-irqc # RZ/A2M
+ - const: renesas,rza1-irqc
+
+ '#interrupt-cells':
+ const: 2
+
+ '#address-cells':
+ const: 0
+
+ interrupt-controller: true
+
+ reg:
+ maxItems: 1
+
+ interrupt-map:
+ maxItems: 8
+ description: Specifies the mapping from external interrupts to GIC interrupts.
+
+ interrupt-map-mask:
+ items:
+ - const: 7
+ - const: 0
+
+required:
+ - compatible
+ - '#interrupt-cells'
+ - '#address-cells'
+ - interrupt-controller
+ - reg
+ - interrupt-map
+ - interrupt-map-mask
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ irqc: interrupt-controller@fcfef800 {
+ compatible = "renesas,r7s72100-irqc", "renesas,rza1-irqc";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0xfcfef800 0x6>;
+ interrupt-map =
+ <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <7 0>;
+ };
diff --git a/Bindings/interrupt-controller/ti,sci-inta.yaml b/Bindings/interrupt-controller/ti,sci-inta.yaml
new file mode 100644
index 000000000000..c7cd05656a3e
--- /dev/null
+++ b/Bindings/interrupt-controller/ti,sci-inta.yaml
@@ -0,0 +1,98 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/ti,sci-inta.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments K3 Interrupt Aggregator
+
+maintainers:
+ - Lokesh Vutla <lokeshvutla@ti.com>
+
+allOf:
+ - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
+
+description: |
+ The Interrupt Aggregator (INTA) provides a centralized machine
+ which handles the termination of system events to that they can
+ be coherently processed by the host(s) in the system. A maximum
+ of 64 events can be mapped to a single interrupt.
+
+ Interrupt Aggregator
+ +-----------------------------------------+
+ | Intmap VINT |
+ | +--------------+ +------------+ |
+ m ------>| | vint | bit | | 0 |.....|63| vint0 |
+ . | +--------------+ +------------+ | +------+
+ . | . . | | HOST |
+ Globalevents ------>| . . |----->| IRQ |
+ . | . . | | CTRL |
+ . | . . | +------+
+ n ------>| +--------------+ +------------+ |
+ | | vint | bit | | 0 |.....|63| vintx |
+ | +--------------+ +------------+ |
+ | |
+ +-----------------------------------------+
+
+ Configuration of these Intmap registers that maps global events to vint is
+ done by a system controller (like the Device Memory and Security Controller
+ on AM654 SoC). Driver should request the system controller to get the range
+ of global events and vints assigned to the requesting host. Management
+ of these requested resources should be handled by driver and requests
+ system controller to map specific global event to vint, bit pair.
+
+ Communication between the host processor running an OS and the system
+ controller happens through a protocol called TI System Control Interface
+ (TISCI protocol).
+
+properties:
+ compatible:
+ const: ti,sci-inta
+
+ reg:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ msi-controller: true
+
+ ti,interrupt-ranges:
+ $ref: /schemas/types.yaml#/definitions/uint32-matrix
+ description: |
+ Interrupt ranges that converts the INTA output hw irq numbers
+ to parents's input interrupt numbers.
+ items:
+ items:
+ - description: |
+ "output_irq" specifies the base for inta output irq
+ - description: |
+ "parent's input irq" specifies the base for parent irq
+ - description: |
+ "limit" specifies the limit for translation
+
+required:
+ - compatible
+ - reg
+ - interrupt-controller
+ - msi-controller
+ - ti,sci
+ - ti,sci-dev-id
+ - ti,interrupt-ranges
+
+examples:
+ - |
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ main_udmass_inta: msi-controller@33d00000 {
+ compatible = "ti,sci-inta";
+ reg = <0x0 0x33d00000 0x0 0x100000>;
+ interrupt-controller;
+ msi-controller;
+ interrupt-parent = <&main_navss_intr>;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <179>;
+ ti,interrupt-ranges = <0 0 256>;
+ };
+ };
diff --git a/Bindings/interrupt-controller/ti,sci-intr.yaml b/Bindings/interrupt-controller/ti,sci-intr.yaml
new file mode 100644
index 000000000000..cff6a956afb4
--- /dev/null
+++ b/Bindings/interrupt-controller/ti,sci-intr.yaml
@@ -0,0 +1,102 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/ti,sci-intr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments K3 Interrupt Router
+
+maintainers:
+ - Lokesh Vutla <lokeshvutla@ti.com>
+
+allOf:
+ - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
+
+description: |
+ The Interrupt Router (INTR) module provides a mechanism to mux M
+ interrupt inputs to N interrupt outputs, where all M inputs are selectable
+ to be driven per N output. An Interrupt Router can either handle edge
+ triggered or level triggered interrupts and that is fixed in hardware.
+
+ Interrupt Router
+ +----------------------+
+ | Inputs Outputs |
+ +-------+ | +------+ +-----+ |
+ | GPIO |----------->| | irq0 | | 0 | | Host IRQ
+ +-------+ | +------+ +-----+ | controller
+ | . . | +-------+
+ +-------+ | . . |----->| IRQ |
+ | INTA |----------->| . . | +-------+
+ +-------+ | . +-----+ |
+ | +------+ | N | |
+ | | irqM | +-----+ |
+ | +------+ |
+ | |
+ +----------