diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2015-09-06 18:37:19 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2015-09-06 18:37:19 +0000 |
| commit | 85d8ef8f1f0e0e063a8571944302be2d2026f823 (patch) | |
| tree | 9d2de4884bec31a1e16bbf0b5a6bfb90d96e16af | |
| parent | 027f1c9655391dcb2b0117f931f720211ac933db (diff) | |
| download | src-85d8ef8f1f0e0e063a8571944302be2d2026f823.tar.gz src-85d8ef8f1f0e0e063a8571944302be2d2026f823.zip | |
Import stripped lldb 3.7.0 release (r246257).vendor/lldb/lldb-release_370-r246257
Notes
Notes:
svn path=/vendor/lldb/dist/; revision=287514
svn path=/vendor/lldb/lldb-release_370-r246257/; revision=287515; tag=vendor/lldb/lldb-release_370-r246257
27 files changed, 1199 insertions, 364 deletions
diff --git a/include/lldb/Core/ArchSpec.h b/include/lldb/Core/ArchSpec.h index 0cadd8d8dec6..0b818a0c7123 100644 --- a/include/lldb/Core/ArchSpec.h +++ b/include/lldb/Core/ArchSpec.h @@ -48,7 +48,26 @@ public: eMIPSSubType_mips64r2el, eMIPSSubType_mips64r6el, }; - + + // Masks for the ases word of an ABI flags structure. + enum MIPSASE + { + eMIPSAse_dsp = 0x00000001, // DSP ASE + eMIPSAse_dspr2 = 0x00000002, // DSP R2 ASE + eMIPSAse_eva = 0x00000004, // Enhanced VA Scheme + eMIPSAse_mcu = 0x00000008, // MCU (MicroController) ASE + eMIPSAse_mdmx = 0x00000010, // MDMX ASE + eMIPSAse_mips3d = 0x00000020, // MIPS-3D ASE + eMIPSAse_mt = 0x00000040, // MT ASE + eMIPSAse_smartmips = 0x00000080, // SmartMIPS ASE + eMIPSAse_virt = 0x00000100, // VZ ASE + eMIPSAse_msa = 0x00000200, // MSA ASE + eMIPSAse_mips16 = 0x00000400, // MIPS16 ASE + eMIPSAse_micromips = 0x00000800, // MICROMIPS ASE + eMIPSAse_xpa = 0x00001000, // XPA ASE + eMIPSAse_mask = 0x00001fff + }; + enum Core { eCore_arm_generic, @@ -546,6 +565,18 @@ public: StopInfoOverrideCallbackType GetStopInfoOverrideCallback () const; + uint32_t + GetFlags () const + { + return m_flags; + } + + void + SetFlags (uint32_t flags) + { + m_flags = flags; + } + protected: bool IsEqualTo (const ArchSpec& rhs, bool exact_match) const; @@ -554,6 +585,11 @@ protected: Core m_core; lldb::ByteOrder m_byte_order; + // Additional arch flags which we cannot get from triple and core + // For MIPS these are application specific extensions like + // micromips, mips16 etc. + uint32_t m_flags; + ConstString m_distribution_id; // Called when m_def or m_entry are changed. Fills in all remaining diff --git a/include/lldb/Host/common/NativeRegisterContext.h b/include/lldb/Host/common/NativeRegisterContext.h index 098f148f95d0..be79bdff1c91 100644 --- a/include/lldb/Host/common/NativeRegisterContext.h +++ b/include/lldb/Host/common/NativeRegisterContext.h @@ -111,6 +111,19 @@ public: virtual lldb::addr_t GetWatchpointAddress (uint32_t wp_index); + // MIPS Linux kernel returns a masked address (last 3bits are masked) + // when a HW watchpoint is hit. However user may not have set a watchpoint + // on this address. This function emulates the instruction at PC and + // finds the base address used in the load/store instruction. This gives the + // exact address used to read/write the variable being watched. + // For example: + // 'n' is at 0x120010d00 and 'm' is 0x120010d04. When a watchpoint is set at 'm', + // then watch exception is generated even when 'n' is read/written. This function + // returns address of 'n' so that client can check whether a watchpoint is set + // on this address or not. + virtual lldb::addr_t + GetWatchpointHitAddress (uint32_t wp_index); + virtual bool HardwareSingleStep (bool enable); diff --git a/include/lldb/Target/StopInfo.h b/include/lldb/Target/StopInfo.h index d09900f7637d..2553887fa3d9 100644 --- a/include/lldb/Target/StopInfo.h +++ b/include/lldb/Target/StopInfo.h @@ -161,7 +161,7 @@ public: CreateStopReasonWithBreakpointSiteID (Thread &thread, lldb::break_id_t break_id, bool should_stop); static lldb::StopInfoSP - CreateStopReasonWithWatchpointID (Thread &thread, lldb::break_id_t watch_id); + CreateStopReasonWithWatchpointID (Thread &thread, lldb::break_id_t watch_id, lldb::addr_t watch_hit_addr = LLDB_INVALID_ADDRESS); static lldb::StopInfoSP CreateStopReasonWithSignal (Thread &thread, int signo, const char *description = nullptr); diff --git a/source/Core/ArchSpec.cpp b/source/Core/ArchSpec.cpp index 36344307743e..2dc001a9047f 100644 --- a/source/Core/ArchSpec.cpp +++ b/source/Core/ArchSpec.cpp @@ -90,28 +90,28 @@ static const CoreDefinition g_core_definitions[] = { eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64, ArchSpec::eCore_arm_aarch64 , "aarch64" }, // mips32, mips32r2, mips32r3, mips32r5, mips32r6 - { eByteOrderBig , 4, 4, 4, llvm::Triple::mips , ArchSpec::eCore_mips32 , "mips" }, - { eByteOrderBig , 4, 4, 4, llvm::Triple::mips , ArchSpec::eCore_mips32r2 , "mipsr2" }, - { eByteOrderBig , 4, 4, 4, llvm::Triple::mips , ArchSpec::eCore_mips32r3 , "mipsr3" }, - { eByteOrderBig , 4, 4, 4, llvm::Triple::mips , ArchSpec::eCore_mips32r5 , "mipsr5" }, - { eByteOrderBig , 4, 4, 4, llvm::Triple::mips , ArchSpec::eCore_mips32r6 , "mipsr6" }, - { eByteOrderLittle, 4, 4, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32el , "mipsel" }, - { eByteOrderLittle, 4, 4, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32r2el , "mipsr2el" }, - { eByteOrderLittle, 4, 4, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32r3el , "mipsr3el" }, - { eByteOrderLittle, 4, 4, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32r5el , "mipsr5el" }, - { eByteOrderLittle, 4, 4, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32r6el , "mipsr6el" }, + { eByteOrderBig , 4, 2, 4, llvm::Triple::mips , ArchSpec::eCore_mips32 , "mips" }, + { eByteOrderBig , 4, 2, 4, llvm::Triple::mips , ArchSpec::eCore_mips32r2 , "mipsr2" }, + { eByteOrderBig , 4, 2, 4, llvm::Triple::mips , ArchSpec::eCore_mips32r3 , "mipsr3" }, + { eByteOrderBig , 4, 2, 4, llvm::Triple::mips , ArchSpec::eCore_mips32r5 , "mipsr5" }, + { eByteOrderBig , 4, 2, 4, llvm::Triple::mips , ArchSpec::eCore_mips32r6 , "mipsr6" }, + { eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32el , "mipsel" }, + { eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32r2el , "mipsr2el" }, + { eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32r3el , "mipsr3el" }, + { eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32r5el , "mipsr5el" }, + { eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32r6el , "mipsr6el" }, // mips64, mips64r2, mips64r3, mips64r5, mips64r6 - { eByteOrderBig , 8, 4, 4, llvm::Triple::mips64 , ArchSpec::eCore_mips64 , "mips64" }, - { eByteOrderBig , 8, 4, 4, llvm::Triple::mips64 , ArchSpec::eCore_mips64r2 , "mips64r2" }, - { eByteOrderBig , 8, 4, 4, llvm::Triple::mips64 , ArchSpec::eCore_mips64r3 , "mips64r3" }, - { eByteOrderBig , 8, 4, 4, llvm::Triple::mips64 , ArchSpec::eCore_mips64r5 , "mips64r5" }, - { eByteOrderBig , 8, 4, 4, llvm::Triple::mips64 , ArchSpec::eCore_mips64r6 , "mips64r6" }, - { eByteOrderLittle, 8, 4, 4, llvm::Triple::mips64el, ArchSpec::eCore_mips64el , "mips64el" }, - { eByteOrderLittle, 8, 4, 4, llvm::Triple::mips64el, ArchSpec::eCore_mips64r2el , "mips64r2el" }, - { eByteOrderLittle, 8, 4, 4, llvm::Triple::mips64el, ArchSpec::eCore_mips64r3el , "mips64r3el" }, - { eByteOrderLittle, 8, 4, 4, llvm::Triple::mips64el, ArchSpec::eCore_mips64r5el , "mips64r5el" }, - { eByteOrderLittle, 8, 4, 4, llvm::Triple::mips64el, ArchSpec::eCore_mips64r6el , "mips64r6el" }, + { eByteOrderBig , 8, 2, 4, llvm::Triple::mips64 , ArchSpec::eCore_mips64 , "mips64" }, + { eByteOrderBig , 8, 2, 4, llvm::Triple::mips64 , ArchSpec::eCore_mips64r2 , "mips64r2" }, + { eByteOrderBig , 8, 2, 4, llvm::Triple::mips64 , ArchSpec::eCore_mips64r3 , "mips64r3" }, + { eByteOrderBig , 8, 2, 4, llvm::Triple::mips64 , ArchSpec::eCore_mips64r5 , "mips64r5" }, + { eByteOrderBig , 8, 2, 4, llvm::Triple::mips64 , ArchSpec::eCore_mips64r6 , "mips64r6" }, + { eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, ArchSpec::eCore_mips64el , "mips64el" }, + { eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, ArchSpec::eCore_mips64r2el , "mips64r2el" }, + { eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, ArchSpec::eCore_mips64r3el , "mips64r3el" }, + { eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, ArchSpec::eCore_mips64r5el , "mips64r5el" }, + { eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el, ArchSpec::eCore_mips64r6el , "mips64r6el" }, { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_generic , "powerpc" }, { eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc601 , "ppc601" }, @@ -419,7 +419,8 @@ ArchSpec::ArchSpec() : m_triple (), m_core (kCore_invalid), m_byte_order (eByteOrderInvalid), - m_distribution_id () + m_distribution_id (), + m_flags (0) { } @@ -427,7 +428,8 @@ ArchSpec::ArchSpec (const char *triple_cstr, Platform *platform) : m_triple (), m_core (kCore_invalid), m_byte_order (eByteOrderInvalid), - m_distribution_id () + m_distribution_id (), + m_flags (0) { if (triple_cstr) SetTriple(triple_cstr, platform); @@ -438,7 +440,8 @@ ArchSpec::ArchSpec (const char *triple_cstr) : m_triple (), m_core (kCore_invalid), m_byte_order (eByteOrderInvalid), - m_distribution_id () + m_distribution_id (), + m_flags (0) { if (triple_cstr) SetTriple(triple_cstr); @@ -448,7 +451,8 @@ ArchSpec::ArchSpec(const llvm::Triple &triple) : m_triple (), m_core (kCore_invalid), m_byte_order (eByteOrderInvalid), - m_distribution_id () + m_distribution_id (), + m_flags (0) { SetTriple(triple); } @@ -457,7 +461,8 @@ ArchSpec::ArchSpec (ArchitectureType arch_type, uint32_t cpu, uint32_t subtype) m_triple (), m_core (kCore_invalid), m_byte_order (eByteOrderInvalid), - m_distribution_id () + m_distribution_id (), + m_flags (0) { SetArchitecture (arch_type, cpu, subtype); } @@ -478,6 +483,7 @@ ArchSpec::operator= (const ArchSpec& rhs) m_core = rhs.m_core; m_byte_order = rhs.m_byte_order; m_distribution_id = rhs.m_distribution_id; + m_flags = rhs.m_flags; } return *this; } @@ -489,6 +495,7 @@ ArchSpec::Clear() m_core = kCore_invalid; m_byte_order = eByteOrderInvalid; m_distribution_id.Clear (); + m_flags = 0; } //===----------------------------------------------------------------------===// diff --git a/source/Host/common/NativeRegisterContext.cpp b/source/Host/common/NativeRegisterContext.cpp index 37040efc4ece..e67c07964a48 100644 --- a/source/Host/common/NativeRegisterContext.cpp +++ b/source/Host/common/NativeRegisterContext.cpp @@ -334,6 +334,12 @@ NativeRegisterContext::GetWatchpointAddress (uint32_t wp_index) return LLDB_INVALID_ADDRESS; } +lldb::addr_t +NativeRegisterContext::GetWatchpointHitAddress (uint32_t wp_index) +{ + return LLDB_INVALID_ADDRESS; +} + bool NativeRegisterContext::HardwareSingleStep (bool enable) { diff --git a/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp b/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp index 75ee8aa4c580..d20219f6d1eb 100644 --- a/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp +++ b/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp @@ -415,7 +415,7 @@ protected: -DisassemblerLLVMC::LLVMCDisassembler::LLVMCDisassembler (const char *triple, const char *cpu, unsigned flavor, DisassemblerLLVMC &owner): +DisassemblerLLVMC::LLVMCDisassembler::LLVMCDisassembler (const char *triple, const char *cpu, const char *features_str, unsigned flavor, DisassemblerLLVMC &owner): m_is_valid(true) { std::string Error; @@ -429,8 +429,6 @@ DisassemblerLLVMC::LLVMCDisassembler::LLVMCDisassembler (const char *triple, con m_instr_info_ap.reset(curr_target->createMCInstrInfo()); m_reg_info_ap.reset (curr_target->createMCRegInfo(triple)); - std::string features_str; - m_subtarget_info_ap.reset(curr_target->createMCSubtargetInfo(triple, cpu, features_str)); @@ -674,8 +672,25 @@ DisassemblerLLVMC::DisassemblerLLVMC (const ArchSpec &arch, const char *flavor_s default: cpu = ""; break; } + + std::string features_str = ""; + if (arch.GetTriple().getArch() == llvm::Triple::mips || arch.GetTriple().getArch() == llvm::Triple::mipsel + || arch.GetTriple().getArch() == llvm::Triple::mips64 || arch.GetTriple().getArch() == llvm::Triple::mips64el) + { + uint32_t arch_flags = arch.GetFlags (); + if (arch_flags & ArchSpec::eMIPSAse_msa) + features_str += "+msa,"; + if (arch_flags & ArchSpec::eMIPSAse_dsp) + features_str += "+dsp,"; + if (arch_flags & ArchSpec::eMIPSAse_dspr2) + features_str += "+dspr2,"; + if (arch_flags & ArchSpec::eMIPSAse_mips16) + features_str += "+mips16,"; + if (arch_flags & ArchSpec::eMIPSAse_micromips) + features_str += "+micromips,"; + } - m_disasm_ap.reset (new LLVMCDisassembler(triple, cpu, flavor, *this)); + m_disasm_ap.reset (new LLVMCDisassembler(triple, cpu, features_str.c_str(), flavor, *this)); if (!m_disasm_ap->IsValid()) { // We use m_disasm_ap.get() to tell whether we are valid or not, so if this isn't good for some reason, @@ -687,7 +702,7 @@ DisassemblerLLVMC::DisassemblerLLVMC (const ArchSpec &arch, const char *flavor_s if (arch.GetTriple().getArch() == llvm::Triple::arm) { std::string thumb_triple(thumb_arch.GetTriple().getTriple()); - m_alternate_disasm_ap.reset(new LLVMCDisassembler(thumb_triple.c_str(), "", flavor, *this)); + m_alternate_disasm_ap.reset(new LLVMCDisassembler(thumb_triple.c_str(), "", "", flavor, *this)); if (!m_alternate_disasm_ap->IsValid()) { m_disasm_ap.reset(); diff --git a/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.h b/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.h index 4c32e25781d3..56cec03994ef 100644 --- a/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.h +++ b/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.h @@ -41,7 +41,7 @@ class DisassemblerLLVMC : public lldb_private::Disassembler class LLVMCDisassembler { public: - LLVMCDisassembler (const char *triple, const char *cpu, unsigned flavor, DisassemblerLLVMC &owner); + LLVMCDisassembler (const char *triple, const char *cpu, const char *features_str, unsigned flavor, DisassemblerLLVMC &owner); ~LLVMCDisassembler(); diff --git a/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp b/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp index 1af25dc817c5..66866c73a5cb 100644 --- a/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp +++ b/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp @@ -33,7 +33,7 @@ #include "llvm/ADT/STLExtras.h" #include "Plugins/Process/Utility/InstructionUtils.h" -#include "Plugins/Process/Utility/RegisterContext_mips64.h" //mips32 has same registers nos as mips64 +#include "Plugins/Process/Utility/RegisterContext_mips.h" //mips32 has same registers nos as mips64 using namespace lldb; using namespace lldb_private; @@ -124,6 +124,19 @@ EmulateInstructionMIPS::EmulateInstructionMIPS (const lldb_private::ArchSpec &ar cpu = "generic"; break; } + std::string features = ""; + uint32_t arch_flags = arch.GetFlags (); + if (arch_flags & ArchSpec::eMIPSAse_msa) + features += "+msa,"; + if (arch_flags & ArchSpec::eMIPSAse_dsp) + features += "+dsp,"; + if (arch_flags & ArchSpec::eMIPSAse_dspr2) + features += "+dspr2,"; + if (arch_flags & ArchSpec::eMIPSAse_mips16) + features += "+mips16,"; + if (arch_flags & ArchSpec::eMIPSAse_micromips) + features += "+micromips,"; + m_reg_info.reset (target->createMCRegInfo (triple.getTriple())); assert (m_reg_info.get()); @@ -131,7 +144,7 @@ EmulateInstructionMIPS::EmulateInstructionMIPS (const lldb_private::ArchSpec &ar assert (m_insn_info.get()); m_asm_info.reset (target->createMCAsmInfo (*m_reg_info, triple.getTriple())); - m_subtype_info.reset (target->createMCSubtargetInfo (triple.getTriple(), cpu, "")); + m_subtype_info.reset (target->createMCSubtargetInfo (triple.getTriple(), cpu, features)); assert (m_asm_info.get() && m_subtype_info.get()); m_context.reset (new llvm::MCContext (m_asm_info.get(), m_reg_info.get(), nullptr)); @@ -289,38 +302,38 @@ EmulateInstructionMIPS::GetRegisterName (unsigned reg_num, bool alternate_name) case gcc_dwarf_bad_mips: return "bad"; case gcc_dwarf_cause_mips: return "cause"; case gcc_dwarf_pc_mips: return "pc"; - case gcc_dwarf_f0_mips: return "fp_reg[0]"; - case gcc_dwarf_f1_mips: return "fp_reg[1]"; - case gcc_dwarf_f2_mips: return "fp_reg[2]"; - case gcc_dwarf_f3_mips: return "fp_reg[3]"; - case gcc_dwarf_f4_mips: return "fp_reg[4]"; - case gcc_dwarf_f5_mips: return "fp_reg[5]"; - case gcc_dwarf_f6_mips: return "fp_reg[6]"; - case gcc_dwarf_f7_mips: return "fp_reg[7]"; - case gcc_dwarf_f8_mips: return "fp_reg[8]"; - case gcc_dwarf_f9_mips: return "fp_reg[9]"; - case gcc_dwarf_f10_mips: return "fp_reg[10]"; - case gcc_dwarf_f11_mips: return "fp_reg[11]"; - case gcc_dwarf_f12_mips: return "fp_reg[12]"; - case gcc_dwarf_f13_mips: return "fp_reg[13]"; - case gcc_dwarf_f14_mips: return "fp_reg[14]"; - case gcc_dwarf_f15_mips: return "fp_reg[15]"; - case gcc_dwarf_f16_mips: return "fp_reg[16]"; - case gcc_dwarf_f17_mips: return "fp_reg[17]"; - case gcc_dwarf_f18_mips: return "fp_reg[18]"; - case gcc_dwarf_f19_mips: return "fp_reg[19]"; - case gcc_dwarf_f20_mips: return "fp_reg[20]"; - case gcc_dwarf_f21_mips: return "fp_reg[21]"; - case gcc_dwarf_f22_mips: return "fp_reg[22]"; - case gcc_dwarf_f23_mips: return "fp_reg[23]"; - case gcc_dwarf_f24_mips: return "fp_reg[24]"; - case gcc_dwarf_f25_mips: return "fp_reg[25]"; - case gcc_dwarf_f26_mips: return "fp_reg[26]"; - case gcc_dwarf_f27_mips: return "fp_reg[27]"; - case gcc_dwarf_f28_mips: return "fp_reg[28]"; - case gcc_dwarf_f29_mips: return "fp_reg[29]"; - case gcc_dwarf_f30_mips: return "fp_reg[30]"; - case gcc_dwarf_f31_mips: return "fp_reg[31]"; + case gcc_dwarf_f0_mips: return "f0"; + case gcc_dwarf_f1_mips: return "f1"; + case gcc_dwarf_f2_mips: return "f2"; + case gcc_dwarf_f3_mips: return "f3"; + case gcc_dwarf_f4_mips: return "f4"; + case gcc_dwarf_f5_mips: return "f5"; + case gcc_dwarf_f6_mips: return "f6"; + case gcc_dwarf_f7_mips: return "f7"; + case gcc_dwarf_f8_mips: return "f8"; + case gcc_dwarf_f9_mips: return "f9"; + case gcc_dwarf_f10_mips: return "f10"; + case gcc_dwarf_f11_mips: return "f11"; + case gcc_dwarf_f12_mips: return "f12"; + case gcc_dwarf_f13_mips: return "f13"; + case gcc_dwarf_f14_mips: return "f14"; + case gcc_dwarf_f15_mips: return "f15"; + case gcc_dwarf_f16_mips: return "f16"; + case gcc_dwarf_f17_mips: return "f17"; + case gcc_dwarf_f18_mips: return "f18"; + case gcc_dwarf_f19_mips: return "f19"; + case gcc_dwarf_f20_mips: return "f20"; + case gcc_dwarf_f21_mips: return "f21"; + case gcc_dwarf_f22_mips: return "f22"; + case gcc_dwarf_f23_mips: return "f23"; + case gcc_dwarf_f24_mips: return "f24"; + case gcc_dwarf_f25_mips: return "f25"; + case gcc_dwarf_f26_mips: return "f26"; + case gcc_dwarf_f27_mips: return "f27"; + case gcc_dwarf_f28_mips: return "f28"; + case gcc_dwarf_f29_mips: return "f29"; + case gcc_dwarf_f30_mips: return "f30"; + case gcc_dwarf_f31_mips: return "f31"; case gcc_dwarf_fcsr_mips: return "fcsr"; case gcc_dwarf_fir_mips: return "fir"; } diff --git a/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp b/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp index 7abf687342c1..a574e7d348e1 100644 --- a/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp +++ b/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp @@ -33,7 +33,7 @@ #include "llvm/ADT/STLExtras.h" #include "Plugins/Process/Utility/InstructionUtils.h" -#include "Plugins/Process/Utility/RegisterContext_mips64.h" +#include "Plugins/Process/Utility/RegisterContext_mips.h" using namespace lldb; using namespace lldb_private; @@ -124,6 +124,19 @@ EmulateInstructionMIPS64::EmulateInstructionMIPS64 (const lldb_private::ArchSpec cpu = "generic"; break; } + std::string features = ""; + uint32_t arch_flags = arch.GetFlags (); + if (arch_flags & ArchSpec::eMIPSAse_msa) + features += "+msa,"; + if (arch_flags & ArchSpec::eMIPSAse_dsp) + features += "+dsp,"; + if (arch_flags & ArchSpec::eMIPSAse_dspr2) + features += "+dspr2,"; + if (arch_flags & ArchSpec::eMIPSAse_mips16) + features += "+mips16,"; + if (arch_flags & ArchSpec::eMIPSAse_micromips) + features += "+micromips,"; + m_reg_info.reset (target->createMCRegInfo (triple.getTriple())); assert (m_reg_info.get()); @@ -131,7 +144,7 @@ EmulateInstructionMIPS64::EmulateInstructionMIPS64 (const lldb_private::ArchSpec assert (m_insn_info.get()); m_asm_info.reset (target->createMCAsmInfo (*m_reg_info, triple.getTriple())); - m_subtype_info.reset (target->createMCSubtargetInfo (triple.getTriple(), cpu, "")); + m_subtype_info.reset (target->createMCSubtargetInfo (triple.getTriple(), cpu, features)); assert (m_asm_info.get() && m_subtype_info.get()); m_context.reset (new llvm::MCContext (m_asm_info.get(), m_reg_info.get(), nullptr)); @@ -289,38 +302,38 @@ EmulateInstructionMIPS64::GetRegisterName (unsigned reg_num, bool alternate_name case gcc_dwarf_bad_mips64: return "bad"; case gcc_dwarf_cause_mips64: return "cause"; case gcc_dwarf_pc_mips64: return "pc"; - case gcc_dwarf_f0_mips64: return "fp_reg[0]"; - case gcc_dwarf_f1_mips64: return "fp_reg[1]"; - case gcc_dwarf_f2_mips64: return "fp_reg[2]"; - case gcc_dwarf_f3_mips64: return "fp_reg[3]"; - case gcc_dwarf_f4_mips64: return "fp_reg[4]"; - case gcc_dwarf_f5_mips64: return "fp_reg[5]"; - case gcc_dwarf_f6_mips64: return "fp_reg[6]"; - case gcc_dwarf_f7_mips64: return "fp_reg[7]"; - case gcc_dwarf_f8_mips64: return "fp_reg[8]"; - case gcc_dwarf_f9_mips64: return "fp_reg[9]"; - case gcc_dwarf_f10_mips64: return "fp_reg[10]"; - case gcc_dwarf_f11_mips64: return "fp_reg[11]"; - case gcc_dwarf_f12_mips64: return "fp_reg[12]"; - case gcc_dwarf_f13_mips64: return "fp_reg[13]"; - case gcc_dwarf_f14_mips64: return "fp_reg[14]"; - case gcc_dwarf_f15_mips64: return "fp_reg[15]"; - case gcc_dwarf_f16_mips64: return "fp_reg[16]"; - case gcc_dwarf_f17_mips64: return "fp_reg[17]"; - case gcc_dwarf_f18_mips64: return "fp_reg[18]"; - case gcc_dwarf_f19_mips64: return "fp_reg[19]"; - case gcc_dwarf_f20_mips64: return "fp_reg[20]"; - case gcc_dwarf_f21_mips64: return "fp_reg[21]"; - case gcc_dwarf_f22_mips64: return "fp_reg[22]"; - case gcc_dwarf_f23_mips64: return "fp_reg[23]"; - case gcc_dwarf_f24_mips64: return "fp_reg[24]"; - case gcc_dwarf_f25_mips64: return "fp_reg[25]"; - case gcc_dwarf_f26_mips64: return "fp_reg[26]"; - case gcc_dwarf_f27_mips64: return "fp_reg[27]"; - case gcc_dwarf_f28_mips64: return "fp_reg[28]"; - case gcc_dwarf_f29_mips64: return "fp_reg[29]"; - case gcc_dwarf_f30_mips64: return "fp_reg[30]"; - case gcc_dwarf_f31_mips64: return "fp_reg[31]"; + case gcc_dwarf_f0_mips64: return "f0"; + case gcc_dwarf_f1_mips64: return "f1"; + case gcc_dwarf_f2_mips64: return "f2"; + case gcc_dwarf_f3_mips64: return "f3"; + case gcc_dwarf_f4_mips64: return "f4"; + case gcc_dwarf_f5_mips64: return "f5"; + case gcc_dwarf_f6_mips64: return "f6"; + case gcc_dwarf_f7_mips64: return "f7"; + case gcc_dwarf_f8_mips64: return "f8"; + case gcc_dwarf_f9_mips64: return "f9"; + case gcc_dwarf_f10_mips64: return "f10"; + case gcc_dwarf_f11_mips64: return "f11"; + case gcc_dwarf_f12_mips64: return "f12"; + case gcc_dwarf_f13_mips64: return "f13"; + case gcc_dwarf_f14_mips64: return "f14"; + case gcc_dwarf_f15_mips64: return "f15"; + case gcc_dwarf_f16_mips64: return "f16"; + case gcc_dwarf_f17_mips64: return "f17"; + case gcc_dwarf_f18_mips64: return "f18"; + case gcc_dwarf_f19_mips64: return "f19"; + case gcc_dwarf_f20_mips64: return "f20"; + case gcc_dwarf_f21_mips64: return "f21"; + case gcc_dwarf_f22_mips64: return "f22"; + case gcc_dwarf_f23_mips64: return "f23"; + case gcc_dwarf_f24_mips64: return "f24"; + case gcc_dwarf_f25_mips64: return "f25"; + case gcc_dwarf_f26_mips64: return "f26"; + case gcc_dwarf_f27_mips64: return "f27"; + case gcc_dwarf_f28_mips64: return "f28"; + case gcc_dwarf_f29_mips64: return "f29"; + case gcc_dwarf_f30_mips64: return "f30"; + case gcc_dwarf_f31_mips64: return "f31"; case gcc_dwarf_fcsr_mips64: return "fcsr"; case gcc_dwarf_fir_mips64: return "fir"; } @@ -397,6 +410,9 @@ EmulateInstructionMIPS64::GetOpcodeForInstruction (const char *op_name) { "SD", &EmulateInstructionMIPS64::Emulate_SD, "SD rt,offset(rs)" }, { "LD", &EmulateInstructionMIPS64::Emulate_LD, "LD rt,offset(base)" }, + { "SW", &EmulateInstructionMIPS64::Emulate_SW, "SW rt,offset(rs)" }, + { "LW", &EmulateInstructionMIPS64::Emulate_LW, "LW rt,offset(rs)" }, + //---------------------------------------------------------------------- // Branch instructions //---------------------------------------------------------------------- @@ -644,35 +660,95 @@ EmulateInstructionMIPS64::Emulate_DADDiu (llvm::MCInst& insn) } bool +EmulateInstructionMIPS64::Emulate_SW (llvm::MCInst& insn) +{ + bool success = false; + uint32_t base; + int64_t imm, address; + Context bad_vaddr_context; + + base = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); + imm = insn.getOperand(2).getImm(); + + RegisterInfo reg_info_base; + if (!GetRegisterInfo (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + base, reg_info_base)) + return false; + + /* read base register */ + address = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + base, 0, &success); + if (!success) + return false; + + /* destination address */ + address = address + imm; + + /* Set the bad_vaddr register with base address used in the instruction */ + bad_vaddr_context.type = eContextInvalid; + WriteRegisterUnsigned (bad_vaddr_context, eRegisterKindDWARF, gcc_dwarf_bad_mips64, address); + + return true; +} + +bool +EmulateInstructionMIPS64::Emulate_LW (llvm::MCInst& insn) +{ + bool success = false; + uint32_t base; + int64_t imm, address; + Context bad_vaddr_context; + + base = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); + imm = insn.getOperand(2).getImm(); + + RegisterInfo reg_info_base; + if (!GetRegisterInfo (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + base, reg_info_base)) + return false; + + /* read base register */ + address = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + base, 0, &success); + if (!success) + return false; + + /* destination address */ + address = address + imm; + + /* Set the bad_vaddr register with base address used in the instruction */ + bad_vaddr_context.type = eContextInvalid; + WriteRegisterUnsigned (bad_vaddr_context, eRegisterKindDWARF, gcc_dwarf_bad_mips64, address); + + return true; +} + +bool EmulateInstructionMIPS64::Emulate_SD (llvm::MCInst& insn) { + uint64_t address; + RegisterInfo reg_info_base; + RegisterInfo reg_info_src; bool success = false; uint32_t imm16 = insn.getOperand(2).getImm(); uint64_t imm = SignedBits(imm16, 15, 0); uint32_t src, base; + Context bad_vaddr_context; src = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); base = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); - /* We look for sp based non-volatile register stores */ - if (base == gcc_dwarf_sp_mips64 && nonvolatile_reg_p (src)) - { - uint64_t address; - RegisterInfo reg_info_base; - RegisterInfo reg_info_src; - - if (!GetRegisterInfo (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + base, reg_info_base) - || !GetRegisterInfo (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + src, reg_info_src)) - return false; + if (!GetRegisterInfo (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + base, reg_info_base) + || !GetRegisterInfo (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + src, reg_info_src)) + return false; - /* read SP */ - address = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + base, 0, &success); - if (!success) - return false; + /* read SP */ + address = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + base, 0, &success); + if (!success) + return false; - /* destination address */ - address = address + imm; + /* destination address */ + address = address + imm; + /* We look for sp based non-volatile register stores */ + if (base == gcc_dwarf_sp_mips64 && nonvolatile_reg_p (src)) + { Context context; RegisterValue data_src; context.type = eContextPushRegisterOnStack; @@ -689,11 +765,13 @@ EmulateInstructionMIPS64::Emulate_SD (llvm::MCInst& insn) if (!WriteMemory (context, address, buffer, reg_info_src.byte_size)) return false; - - return true; } - return false; + /* Set the bad_vaddr register with base address used in the instruction */ + bad_vaddr_context.type = eContextInvalid; + WriteRegisterUnsigned (bad_vaddr_context, eRegisterKindDWARF, gcc_dwarf_bad_mips64, address); + + return true; } bool diff --git a/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h b/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h index 178417c196fa..faefd329a8e4 100644 --- a/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h +++ b/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h @@ -128,6 +128,12 @@ protected: Emulate_SD (llvm::MCInst& insn); bool + Emulate_SW (llvm::MCInst& insn); + + bool + Emulate_LW (llvm::MCInst& insn); + + bool Emulate_LD (llvm::MCInst& insn); bool diff --git a/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp b/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp index 5fc83f06157c..789fd4913301 100644 --- a/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp +++ b/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp @@ -1437,6 +1437,25 @@ ObjectFileELF::GetSectionHeaderInfo(SectionHeaderColl §ion_headers, assert(spec_ostype == ostype); } + if (arch_spec.GetMachine() == llvm::Triple::mips || arch_spec.GetMachine() == llvm::Triple::mipsel + || arch_spec.GetMachine() == llvm::Triple::mips64 || arch_spec.GetMachine() == llvm::Triple::mips64el) + { + switch (header.e_flags & llvm::ELF::EF_MIPS_ARCH_ASE) + { + case llvm::ELF::EF_MIPS_MICROMIPS: + arch_spec.SetFlags (ArchSpec::eMIPSAse_micromips); + break; + case llvm::ELF::EF_MIPS_ARCH_ASE_M16: + arch_spec.SetFlags (ArchSpec::eMIPSAse_mips16); + break; + case llvm::ELF::EF_MIPS_ARCH_ASE_MDMX: + arch_spec.SetFlags (ArchSpec::eMIPSAse_mdmx); + break; + default: + break; + } + } + // If there are no section headers we are done. if (header.e_shnum == 0) return 0; @@ -1483,6 +1502,22 @@ ObjectFileELF::GetSectionHeaderInfo(SectionHeaderColl §ion_headers, I->section_name = name; + if (arch_spec.GetMachine() == llvm::Triple::mips || arch_spec.GetMachine() == llvm::Triple::mipsel + || arch_spec.GetMachine() == llvm::Triple::mips64 || arch_spec.GetMachine() == llvm::Triple::mips64el) + { + if (header.sh_type == SHT_MIPS_ABIFLAGS) + { + DataExtractor data; + if (section_size && (data.SetData (object_data, header.sh_offset, section_size) == section_size)) + { + lldb::offset_t ase_offset = 12; // MIPS ABI Flags Version: 0 + uint32_t arch_flags = arch_spec.GetFlags (); + arch_flags |= data.GetU32 (&ase_offset); + arch_spec.SetFlags (arch_flags); + } + } + } + if (name == g_sect_name_gnu_debuglink) { DataExtractor data; diff --git a/source/Plugins/Process/Utility/RegisterContextFreeBSD_mips64.cpp b/source/Plugins/Process/Utility/RegisterContextFreeBSD_mips64.cpp index c31b0ee7de53..53fa4169bffc 100644 --- a/source/Plugins/Process/Utility/RegisterContextFreeBSD_mips64.cpp +++ b/source/Plugins/Process/Utility/RegisterContextFreeBSD_mips64.cpp @@ -57,7 +57,7 @@ typedef struct _GPR uint64_t pc; uint64_t ic; uint64_t dummy; -} GPR; +} GPR_freebsd_mips; //--------------------------------------------------------------------------- // Include RegisterInfos_mips64 to declare our g_register_infos_mips64 structure. @@ -74,7 +74,7 @@ RegisterContextFreeBSD_mips64::RegisterContextFreeBSD_mips64(const ArchSpec &tar size_t RegisterContextFreeBSD_mips64::GetGPRSize() const { - return sizeof(GPR); + return sizeof(GPR_freebsd_mips); } const RegisterInfo * diff --git a/source/Plugins/Process/Utility/RegisterContextLinux_mips.cpp b/source/Plugins/Process/Utility/RegisterContextLinux_mips.cpp index 948437f51280..4d58b85b5665 100644 --- a/source/Plugins/Process/Utility/RegisterContextLinux_mips.cpp +++ b/source/Plugins/Process/Utility/RegisterContextLinux_mips.cpp @@ -14,55 +14,14 @@ #include "RegisterContextLinux_mips.h" // Internal codes for mips registers -#include "lldb-mips64-register-enums.h" -#include "RegisterContext_mips64.h" +#include "lldb-mips-linux-register-enums.h" + +// For GP and FP buffers +#include "RegisterContext_mips.h" using namespace lldb_private; using namespace lldb; -// GP registers -typedef struct _GPR -{ - uint32_t zero; - uint32_t r1; - uint32_t r2; - uint32_t r3; - uint32_t r4; - uint32_t r5; - uint32_t r6; - uint32_t r7; - uint32_t r8; - uint32_t r9; - uint32_t r10; - uint32_t r11; - uint32_t r12; - uint32_t r13; - uint32_t r14; - uint32_t r15; - uint32_t r16; - uint32_t r17; - uint32_t r18; - uint32_t r19; - uint32_t r20; - uint32_t r21; - uint32_t r22; - uint32_t r23; - uint32_t r24; - uint32_t r25; - uint32_t r26; - uint32_t r27; - uint32_t gp; - uint32_t sp; - uint32_t r30; - uint32_t ra; - uint32_t mullo; - uint32_t mulhi; - uint32_t pc; - uint32_t badvaddr; - uint32_t sr; - uint32_t cause; -} GPR; - //--------------------------------------------------------------------------- // Include RegisterInfos_mips to declare our g_register_infos_mips structure. //--------------------------------------------------------------------------- @@ -78,7 +37,7 @@ RegisterContextLinux_mips::RegisterContextLinux_mips(const ArchSpec &target_arch size_t RegisterContextLinux_mips::GetGPRSize() const { - return sizeof(GPR); + return sizeof(GPR_linux_mips); } const RegisterInfo * @@ -100,3 +59,9 @@ RegisterContextLinux_mips::GetRegisterCount () const { return static_cast<uint32_t> (sizeof (g_register_infos_mips) / sizeof (g_register_infos_mips [0])); } + +uint32_t +RegisterContextLinux_mips::GetUserRegisterCount () const +{ + return static_cast<uint32_t> (k_num_user_registers_mips); +} diff --git a/source/Plugins/Process/Utility/RegisterContextLinux_mips.h b/source/Plugins/Process/Utility/RegisterContextLinux_mips.h index 815473e76ddb..bcc2d002c854 100644 --- a/source/Plugins/Process/Utility/RegisterContextLinux_mips.h +++ b/source/Plugins/Process/Utility/RegisterContextLinux_mips.h @@ -27,6 +27,9 @@ public: uint32_t GetRegisterCount () const override; + + uint32_t + GetUserRegisterCount () const override; }; #endif diff --git a/source/Plugins/Process/Utility/RegisterContextLinux_mips64.cpp b/source/Plugins/Process/Utility/RegisterContextLinux_mips64.cpp index a762930e8eb4..7f512f82be80 100644 --- a/source/Plugins/Process/Utility/RegisterContextLinux_mips64.cpp +++ b/source/Plugins/Process/Utility/RegisterContextLinux_mips64.cpp @@ -15,63 +15,22 @@ // For GDB, GCC and DWARF Register numbers #include "RegisterContextLinux_mips64.h" -// Internal codes for all mips64 registers -#include "lldb-mips64-register-enums.h" -#include "RegisterContext_mips64.h" +// For GP and FP buffers +#include "RegisterContext_mips.h" + +// Internal codes for all mips32 and mips64 registers +#include "lldb-mips-linux-register-enums.h" using namespace lldb; using namespace lldb_private; -// GP registers -typedef struct _GPR -{ - uint64_t zero; - uint64_t r1; - uint64_t r2; - uint64_t r3; - uint64_t r4; - uint64_t r5; - uint64_t r6; - uint64_t r7; - uint64_t r8; - uint64_t r9; - uint64_t r10; - uint64_t r11; - uint64_t r12; - uint64_t r13; - uint64_t r14; - uint64_t r15; - uint64_t r16; - uint64_t r17; - uint64_t r18; - uint64_t r19; - uint64_t r20; - uint64_t r21; - uint64_t r22; - uint64_t r23; - uint64_t r24; - uint64_t r25; - uint64_t r26; - uint64_t r27; - uint64_t gp; - uint64_t sp; - uint64_t r30; - uint64_t ra; - uint64_t mullo; - uint64_t mulhi; - uint64_t pc; - uint64_t badvaddr; - uint64_t sr; - uint64_t cause; - uint64_t ic; - uint64_t dummy; -} GPR; - //--------------------------------------------------------------------------- // Include RegisterInfos_mips64 to declare our g_register_infos_mips64 structure. //--------------------------------------------------------------------------- #define DECLARE_REGISTER_INFOS_MIPS64_STRUCT +#define LINUX_MIPS64 #include "RegisterInfos_mips64.h" +#undef LINUX_MIPS64 #undef DECLARE_REGISTER_INFOS_MIPS64_STRUCT //--------------------------------------------------------------------------- @@ -115,17 +74,35 @@ GetRegisterInfoCount (const ArchSpec &target_arch) } } +uint32_t +GetUserRegisterInfoCount (const ArchSpec &target_arch) +{ + switch (target_arch.GetMachine()) + { + case llvm::Triple::mips: + case llvm::Triple::mipsel: + return static_cast<uint32_t> (k_num_user_registers_mips); + case llvm::Triple::mips64el: + case llvm::Triple::mips64: + return static_cast<uint32_t> (k_num_user_registers_mips64); + default: + assert(false && "Unhandled target architecture."); + return 0; + } +} + RegisterContextLinux_mips64::RegisterContextLinux_mips64(const ArchSpec &target_arch) : lldb_private::RegisterInfoInterface(target_arch), m_register_info_p (GetRegisterInfoPtr (target_arch)), - m_register_info_count (GetRegisterInfoCount (target_arch)) + m_register_info_count (GetRegisterInfoCount (target_arch)), + m_user_register_count (GetUserRegisterInfoCount (target_arch)) { } size_t RegisterContextLinux_mips64::GetGPRSize() const { - return sizeof(GPR); + return sizeof(GPR_linux_mips); } const RegisterInfo * @@ -140,4 +117,10 @@ RegisterContextLinux_mips64::GetRegisterCount () const return m_register_info_count; } +uint32_t +RegisterContextLinux_mips64::GetUserRegisterCount () const +{ + return m_user_register_count; +} + #endif diff --git a/source/Plugins/Process/Utility/RegisterContextLinux_mips64.h b/source/Plugins/Process/Utility/RegisterContextLinux_mips64.h index 546d148eb693..86c662c52cea 100644 --- a/source/Plugins/Process/Utility/RegisterContextLinux_mips64.h +++ b/source/Plugins/Process/Utility/RegisterContextLinux_mips64.h @@ -30,9 +30,13 @@ public: uint32_t GetRegisterCount () const override; + uint32_t + GetUserRegisterCount () const override; + private: const lldb_private::RegisterInfo *m_register_info_p; uint32_t m_register_info_count; + uint32_t m_user_register_count; }; #endif diff --git a/source/Plugins/Process/Utility/RegisterContextPOSIX_mips64.h b/source/Plugins/Process/Utility/RegisterContextPOSIX_mips64.h index 2a61685f12ac..612a03466983 100644 --- a/source/Plugins/Process/Utility/RegisterContextPOSIX_mips64.h +++ b/source/Plugins/Process/Utility/RegisterContextPOSIX_mips64.h @@ -12,8 +12,8 @@ #include "lldb/Core/Log.h" #include "RegisterContextPOSIX.h" -#include "RegisterContext_mips64.h" -#include "lldb-mips64-register-enums.h" +#include "RegisterContext_mips.h" +#include "lldb-mips-freebsd-register-enums.h" using namespace lldb_private; diff --git a/source/Plugins/Process/Utility/RegisterContext_mips64.h b/source/Plugins/Process/Utility/RegisterContext_mips.h index 96ce2a0acc5b..de2b4d6dccee 100644 --- a/source/Plugins/Process/Utility/RegisterContext_mips64.h +++ b/source/Plugins/Process/Utility/RegisterContext_mips.h @@ -1,4 +1,4 @@ -//===-- RegisterContext_mips64.h --------------------------------*- C++ -*-===// +//===-- RegisterContext_mips.h --------------------------------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -10,7 +10,8 @@ #ifndef liblldb_RegisterContext_mips64_H_ #define liblldb_RegisterContext_mips64_H_ -// GCC and DWARF Register numbers (eRegisterKindGCC & eRegisterKindDWARF) +// eh_frame and DWARF Register numbers (eRegisterKindEHFrame & eRegisterKindDWARF) + enum { // GP Registers @@ -46,12 +47,12 @@ enum gcc_dwarf_sp_mips, gcc_dwarf_r30_mips, gcc_dwarf_ra_mips, + gcc_dwarf_sr_mips, gcc_dwarf_lo_mips, gcc_dwarf_hi_mips, - gcc_dwarf_pc_mips, gcc_dwarf_bad_mips, - gcc_dwarf_sr_mips, gcc_dwarf_cause_mips, + gcc_dwarf_pc_mips, gcc_dwarf_f0_mips, gcc_dwarf_f1_mips, gcc_dwarf_f2_mips, @@ -86,6 +87,41 @@ enum gcc_dwarf_f31_mips, gcc_dwarf_fcsr_mips, gcc_dwarf_fir_mips, + gcc_dwarf_w0_mips, + gcc_dwarf_w1_mips, + gcc_dwarf_w2_mips, + gcc_dwarf_w3_mips, + gcc_dwarf_w4_mips, + gcc_dwarf_w5_mips, + gcc_dwarf_w6_mips, + gcc_dwarf_w7_mips, + gcc_dwarf_w8_mips, + gcc_dwarf_w9_mips, + gcc_dwarf_w10_mips, + gcc_dwarf_w11_mips, + gcc_dwarf_w12_mips, + gcc_dwarf_w13_mips, + gcc_dwarf_w14_mips, + gcc_dwarf_w15_mips, + gcc_dwarf_w16_mips, + gcc_dwarf_w17_mips, + gcc_dwarf_w18_mips, + gcc_dwarf_w19_mips, + gcc_dwarf_w20_mips, + gcc_dwarf_w21_mips, + gcc_dwarf_w22_mips, + gcc_dwarf_w23_mips, + gcc_dwarf_w24_mips, + gcc_dwarf_w25_mips, + gcc_dwarf_w26_mips, + gcc_dwarf_w27_mips, + gcc_dwarf_w28_mips, + gcc_dwarf_w29_mips, + gcc_dwarf_w30_mips, + gcc_dwarf_w31_mips, + gcc_dwarf_mcsr_mips, + gcc_dwarf_mir_mips, + gcc_dwarf_config5_mips, gcc_dwarf_ic_mips, gcc_dwarf_dummy_mips }; @@ -165,7 +201,42 @@ enum gcc_dwarf_fcsr_mips64, gcc_dwarf_fir_mips64, gcc_dwarf_ic_mips64, - gcc_dwarf_dummy_mips64 + gcc_dwarf_dummy_mips64, + gcc_dwarf_w0_mips64, + gcc_dwarf_w1_mips64, + gcc_dwarf_w2_mips64, + gcc_dwarf_w3_mips64, + gcc_dwarf_w4_mips64, + gcc_dwarf_w5_mips64, + gcc_dwarf_w6_mips64, + gcc_dwarf_w7_mips64, + gcc_dwarf_w8_mips64, + gcc_dwarf_w9_mips64, + gcc_dwarf_w10_mips64, + gcc_dwarf_w11_mips64, + gcc_dwarf_w12_mips64, + gcc_dwarf_w13_mips64, + gcc_dwarf_w14_mips64, + gcc_dwarf_w15_mips64, + gcc_dwarf_w16_mips64, + gcc_dwarf_w17_mips64, + gcc_dwarf_w18_mips64, + gcc_dwarf_w19_mips64, + gcc_dwarf_w20_mips64, + gcc_dwarf_w21_mips64, + gcc_dwarf_w22_mips64, + gcc_dwarf_w23_mips64, + gcc_dwarf_w24_mips64, + gcc_dwarf_w25_mips64, + gcc_dwarf_w26_mips64, + gcc_dwarf_w27_mips64, + gcc_dwarf_w28_mips64, + gcc_dwarf_w29_mips64, + gcc_dwarf_w30_mips64, + gcc_dwarf_w31_mips64, + gcc_dwarf_mcsr_mips64, + gcc_dwarf_mir_mips64, + gcc_dwarf_config5_mips64, }; // GDB Register numbers (eRegisterKindGDB) @@ -203,12 +274,12 @@ enum gdb_sp_mips, gdb_r30_mips, gdb_ra_mips, + gdb_sr_mips, gdb_lo_mips, gdb_hi_mips, - gdb_pc_mips, gdb_bad_mips, - gdb_sr_mips, gdb_cause_mips, + gdb_pc_mips, gdb_f0_mips, gdb_f1_mips, gdb_f2_mips, @@ -243,6 +314,41 @@ enum gdb_f31_mips, gdb_fcsr_mips, gdb_fir_mips, + gdb_w0_mips, + gdb_w1_mips, + gdb_w2_mips, + gdb_w3_mips, + gdb_w4_mips, + gdb_w5_mips, + gdb_w6_mips, + gdb_w7_mips, + gdb_w8_mips, + gdb_w9_mips, + gdb_w10_mips, + gdb_w11_mips, + gdb_w12_mips, + gdb_w13_mips, + gdb_w14_mips, + gdb_w15_mips, + gdb_w16_mips, + gdb_w17_mips, + gdb_w18_mips, + gdb_w19_mips, + gdb_w20_mips, + gdb_w21_mips, + gdb_w22_mips, + gdb_w23_mips, + gdb_w24_mips, + gdb_w25_mips, + gdb_w26_mips, + gdb_w27_mips, + gdb_w28_mips, + gdb_w29_mips, + gdb_w30_mips, + gdb_w31_mips, + gdb_mcsr_mips, + gdb_mir_mips, + gdb_config5_mips, gdb_ic_mips, gdb_dummy_mips }; @@ -322,15 +428,184 @@ enum gdb_fcsr_mips64, gdb_fir_mips64, gdb_ic_mips64, - gdb_dummy_mips64 + gdb_dummy_mips64, + gdb_w0_mips64, + gdb_w1_mips64, + gdb_w2_mips64, + gdb_w3_mips64, + gdb_w4_mips64, + gdb_w5_mips64, + gdb_w6_mips64, + gdb_w7_mips64, + gdb_w8_mips64, + gdb_w9_mips64, + gdb_w10_mips64, + gdb_w11_mips64, + gdb_w12_mips64, + gdb_w13_mips64, + gdb_w14_mips64, + gdb_w15_mips64, + gdb_w16_mips64, + gdb_w17_mips64, + gdb_w18_mips64, + gdb_w19_mips64, + gdb_w20_mips64, + gdb_w21_mips64, + gdb_w22_mips64, + gdb_w23_mips64, + gdb_w24_mips64, + gdb_w25_mips64, + gdb_w26_mips64, + gdb_w27_mips64, + gdb_w28_mips64, + gdb_w29_mips64, + gdb_w30_mips64, + gdb_w31_mips64, + gdb_mcsr_mips64, + gdb_mir_mips64, + gdb_config5_mips64, +}; + +struct IOVEC_mips +{ + void *iov_base; + size_t iov_len; +}; + +// GP registers +struct GPR_linux_mips +{ + uint64_t zero; + uint64_t r1; + uint64_t r2; + uint64_t r3; + uint64_t r4; + uint64_t r5; + uint64_t r6; + uint64_t r7; + uint64_t r8; + uint64_t r9; + uint64_t r10; + uint64_t r11; + uint64_t r12; + uint64_t r13; + uint64_t r14; + uint64_t r15; + uint64_t r16; + uint64_t r17; + uint64_t r18; + uint64_t r19; + uint64_t r20; + uint64_t r21; + uint64_t r22; + uint64_t r23; + uint64_t r24; + uint64_t r25; + uint64_t r26; + uint64_t r27; + uint64_t gp; + uint64_t sp; + uint64_t r30; + uint64_t ra; + uint64_t mullo; + uint64_t mulhi; + uint64_t pc; + uint64_t badvaddr; + uint64_t sr; + uint64_t cause; + uint64_t config5; +}; + +struct FPR_linux_mips +{ + uint64_t f0; + uint64_t f1; + uint64_t f2; + uint64_t f3; + uint64_t f4; + uint64_t f5; + uint64_t f6; + uint64_t f7; + uint64_t f8; + uint64_t f9; + uint64_t f10; + uint64_t f11; + uint64_t f12; + uint64_t f13; + uint64_t f14; + uint64_t f15; + uint64_t f16; + uint64_t f17; + uint64_t f18; + uint64_t f19; + uint64_t f20; + uint64_t f21; + uint64_t f22; + uint64_t f23; + uint64_t f24; + uint64_t f25; + uint64_t f26; + uint64_t f27; + uint64_t f28; + uint64_t f29; + uint64_t f30; + uint64_t f31; + uint32_t fcsr; + uint32_t fir; + uint32_t config5; +}; + +struct MSAReg +{ + uint8_t byte[16]; +}; + +struct MSA_linux_mips +{ + MSAReg w0; + MSAReg w1; + MSAReg w2; + MSAReg w3; + MSAReg w4; + MSAReg w5; + MSAReg w6; + MSAReg w7; + MSAReg w8; + MSAReg w9; + MSAReg w10; + MSAReg w11; + MSAReg w12; + MSAReg w13; + MSAReg w14; + MSAReg w15; + MSAReg w16; + MSAReg w17; + MSAReg w18; + MSAReg w19; + MSAReg w20; + MSAReg w21; + MSAReg w22; + MSAReg w23; + MSAReg w24; + MSAReg w25; + MSAReg w26; + MSAReg w27; + MSAReg w28; + MSAReg w29; + MSAReg w30; + MSAReg w31; + uint32_t fcsr; /* FPU control status register */ + uint32_t fir; /* FPU implementaion revision */ + uint32_t mcsr; /* MSA control status register */ + uint32_t mir; /* MSA implementation revision */ + uint32_t config5; /* Config5 register */ }; -// FP registers -struct FPR_mips +struct UserArea { - uint64_t fp_reg[32]; - uint32_t fcsr; /* FPU status register */ - uint32_t fir; /* FPU control register */ + GPR_linux_mips gpr; // General purpose registers. + FPR_linux_mips fpr; // Floating point registers. + MSA_linux_mips msa; // MSA registers. }; #endif // liblldb_RegisterContext_mips64_H_ diff --git a/source/Plugins/Process/Utility/RegisterInfos_mips.h b/source/Plugins/Process/Utility/RegisterInfos_mips.h index 0956b2ca9eca..83ce6f0d4327 100644 --- a/source/Plugins/Process/Utility/RegisterInfos_mips.h +++ b/source/Plugins/Process/Utility/RegisterInfos_mips.h @@ -14,24 +14,35 @@ // Computes the offset of the given GPR in the user data area. #define GPR_OFFSET(regname) \ - (LLVM_EXTENSION offsetof(GPR, regname)) + (LLVM_EXTENSION offsetof(UserArea, gpr) + \ + LLVM_EXTENSION offsetof(GPR_linux_mips, regname)) // Computes the offset of the given FPR in the extended data area. #define FPR_OFFSET(regname) \ - (LLVM_EXTENSION offsetof(FPR_mips, regname)) + (LLVM_EXTENSION offsetof(UserArea, fpr) + \ + LLVM_EXTENSION offsetof(FPR_linux_mips, regname)) + +// Computes the offset of the given MSA in the extended data area. +#define MSA_OFFSET(regname) \ + (LLVM_EXTENSION offsetof(UserArea, msa) + \ + LLVM_EXTENSION offsetof(MSA_linux_mips, regname)) // Note that the size and offset will be updated by platform-specific classes. #define DEFINE_GPR(reg, alt, kind1, kind2, kind3, kind4) \ - { #reg, alt, sizeof(((GPR*)NULL)->reg), GPR_OFFSET(reg), eEncodingUint, \ + { #reg, alt, sizeof(((GPR_linux_mips*)NULL)->reg) / 2, GPR_OFFSET(reg), eEncodingUint, \ eFormatHex, { kind1, kind2, kind3, kind4, gpr_##reg##_mips }, NULL, NULL } -#define DEFINE_FPR(member, reg, alt, kind1, kind2, kind3, kind4) \ - { #reg, alt, sizeof(((FPR_mips*)NULL)->member) / 2, FPR_OFFSET(member), eEncodingUint, \ +#define DEFINE_FPR(reg, alt, kind1, kind2, kind3, kind4) \ + { #reg, alt, sizeof(((FPR_linux_mips*)NULL)->reg), FPR_OFFSET(reg), eEncodingUint, \ eFormatHex, { kind1, kind2, kind3, kind4, fpr_##reg##_mips }, NULL, NULL } -#define DEFINE_FPR_INFO(member, reg, alt, kind1, kind2, kind3, kind4) \ - { #reg, alt, sizeof(((FPR_mips*)NULL)->member), FPR_OFFSET(member), eEncodingUint, \ - eFormatHex, { kind1, kind2, kind3, kind4, fpr_##reg##_mips }, NULL, NULL } +#define DEFINE_MSA(reg, alt, kind1, kind2, kind3, kind4) \ + { #reg, alt, sizeof(((MSA_linux_mips*)0)->reg), MSA_OFFSET(reg), eEncodingVector, \ + eFormatVectorOfUInt8, { kind1, kind2, kind3, kind4, msa_##reg##_mips }, NULL, NULL } + +#define DEFINE_MSA_INFO(reg, alt, kind1, kind2, kind3, kind4) \ + { #reg, alt, sizeof(((MSA_linux_mips*)0)->reg), MSA_OFFSET(reg), eEncodingUint, \ + eFormatHex, { kind1, kind2, kind3, kind4, msa_##reg##_mips }, NULL, NULL } // RegisterKind: GCC, DWARF, Generic, GDB, LLDB @@ -70,53 +81,95 @@ g_register_infos_mips[] = DEFINE_GPR (sp, "sp", gcc_dwarf_sp_mips, gcc_dwarf_sp_mips, LLDB_REGNUM_GENERIC_SP, gdb_sp_mips), DEFINE_GPR (r30, "fp", gcc_dwarf_r30_mips, gcc_dwarf_r30_mips, LLDB_REGNUM_GENERIC_FP, gdb_r30_mips), DEFINE_GPR (ra, "ra", gcc_dwarf_ra_mips, gcc_dwarf_ra_mips, LLDB_REGNUM_GENERIC_RA, gdb_ra_mips), + DEFINE_GPR (sr, "status", gcc_dwarf_sr_mips, gcc_dwarf_sr_mips, LLDB_REGNUM_GENERIC_FLAGS, LLDB_INVALID_REGNUM), DEFINE_GPR (mullo, NULL, gcc_dwarf_lo_mips, gcc_dwarf_lo_mips, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), DEFINE_GPR (mulhi, NULL, gcc_dwarf_hi_mips, gcc_dwarf_hi_mips, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), - DEFINE_GPR (pc, NULL, gcc_dwarf_pc_mips, gcc_dwarf_pc_mips, LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_REGNUM), DEFINE_GPR (badvaddr, NULL, gcc_dwarf_bad_mips, gcc_dwarf_bad_mips, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), - DEFINE_GPR (sr, "status", gcc_dwarf_sr_mips, gcc_dwarf_sr_mips, LLDB_REGNUM_GENERIC_FLAGS, LLDB_INVALID_REGNUM), DEFINE_GPR (cause, NULL, gcc_dwarf_cause_mips, gcc_dwarf_cause_mips, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), - DEFINE_FPR (fp_reg[0], f0, NULL, gcc_dwarf_f0_mips, gcc_dwarf_f0_mips, LLDB_INVALID_REGNUM, gdb_f0_mips), - DEFINE_FPR (fp_reg[1], f1, NULL, gcc_dwarf_f1_mips, gcc_dwarf_f1_mips, LLDB_INVALID_REGNUM, gdb_f1_mips), - DEFINE_FPR (fp_reg[2], f2, NULL, gcc_dwarf_f2_mips, gcc_dwarf_f2_mips, LLDB_INVALID_REGNUM, gdb_f2_mips), - DEFINE_FPR (fp_reg[3], f3, NULL, gcc_dwarf_f3_mips, gcc_dwarf_f3_mips, LLDB_INVALID_REGNUM, gdb_f3_mips), - DEFINE_FPR (fp_reg[4], f4, NULL, gcc_dwarf_f4_mips, gcc_dwarf_f4_mips, LLDB_INVALID_REGNUM, gdb_f4_mips), - DEFINE_FPR (fp_reg[5], f5, NULL, gcc_dwarf_f5_mips, gcc_dwarf_f5_mips, LLDB_INVALID_REGNUM, gdb_f5_mips), - DEFINE_FPR (fp_reg[6], f6, NULL, gcc_dwarf_f6_mips, gcc_dwarf_f6_mips, LLDB_INVALID_REGNUM, gdb_f6_mips), - DEFINE_FPR (fp_reg[7], f7, NULL, gcc_dwarf_f7_mips, gcc_dwarf_f7_mips, LLDB_INVALID_REGNUM, gdb_f7_mips), - DEFINE_FPR (fp_reg[8], f8, NULL, gcc_dwarf_f8_mips, gcc_dwarf_f8_mips, LLDB_INVALID_REGNUM, gdb_f8_mips), - DEFINE_FPR (fp_reg[9], f9, NULL, gcc_dwarf_f9_mips, gcc_dwarf_f9_mips, LLDB_INVALID_REGNUM, gdb_f9_mips), - DEFINE_FPR (fp_reg[10], f10, NULL, gcc_dwarf_f10_mips, gcc_dwarf_f10_mips, LLDB_INVALID_REGNUM, gdb_f10_mips), - DEFINE_FPR (fp_reg[11], f11, NULL, gcc_dwarf_f11_mips, gcc_dwarf_f11_mips, LLDB_INVALID_REGNUM, gdb_f11_mips), - DEFINE_FPR (fp_reg[12], f12, NULL, gcc_dwarf_f12_mips, gcc_dwarf_f12_mips, LLDB_INVALID_REGNUM, gdb_f12_mips), - DEFINE_FPR (fp_reg[13], f13, NULL, gcc_dwarf_f13_mips, gcc_dwarf_f13_mips, LLDB_INVALID_REGNUM, gdb_f13_mips), - DEFINE_FPR (fp_reg[14], f14, NULL, gcc_dwarf_f14_mips, gcc_dwarf_f14_mips, LLDB_INVALID_REGNUM, gdb_f14_mips), - DEFINE_FPR (fp_reg[15], f15, NULL, gcc_dwarf_f15_mips, gcc_dwarf_f15_mips, LLDB_INVALID_REGNUM, gdb_f15_mips), - DEFINE_FPR (fp_reg[16], f16, NULL, gcc_dwarf_f16_mips, gcc_dwarf_f16_mips, LLDB_INVALID_REGNUM, gdb_f16_mips), - DEFINE_FPR (fp_reg[17], f17, NULL, gcc_dwarf_f17_mips, gcc_dwarf_f17_mips, LLDB_INVALID_REGNUM, gdb_f17_mips), - DEFINE_FPR (fp_reg[18], f18, NULL, gcc_dwarf_f18_mips, gcc_dwarf_f18_mips, LLDB_INVALID_REGNUM, gdb_f18_mips), - DEFINE_FPR (fp_reg[19], f19, NULL, gcc_dwarf_f19_mips, gcc_dwarf_f19_mips, LLDB_INVALID_REGNUM, gdb_f19_mips), - DEFINE_FPR (fp_reg[20], f20, NULL, gcc_dwarf_f20_mips, gcc_dwarf_f20_mips, LLDB_INVALID_REGNUM, gdb_f20_mips), - DEFINE_FPR (fp_reg[21], f21, NULL, gcc_dwarf_f21_mips, gcc_dwarf_f21_mips, LLDB_INVALID_REGNUM, gdb_f21_mips), - DEFINE_FPR (fp_reg[22], f22, NULL, gcc_dwarf_f22_mips, gcc_dwarf_f22_mips, LLDB_INVALID_REGNUM, gdb_f22_mips), - DEFINE_FPR (fp_reg[23], f23, NULL, gcc_dwarf_f23_mips, gcc_dwarf_f23_mips, LLDB_INVALID_REGNUM, gdb_f23_mips), - DEFINE_FPR (fp_reg[24], f24, NULL, gcc_dwarf_f24_mips, gcc_dwarf_f24_mips, LLDB_INVALID_REGNUM, gdb_f24_mips), - DEFINE_FPR (fp_reg[25], f25, NULL, gcc_dwarf_f25_mips, gcc_dwarf_f25_mips, LLDB_INVALID_REGNUM, gdb_f25_mips), - DEFINE_FPR (fp_reg[26], f26, NULL, gcc_dwarf_f26_mips, gcc_dwarf_f26_mips, LLDB_INVALID_REGNUM, gdb_f26_mips), - DEFINE_FPR (fp_reg[27], f27, NULL, gcc_dwarf_f27_mips, gcc_dwarf_f27_mips, LLDB_INVALID_REGNUM, gdb_f27_mips), - DEFINE_FPR (fp_reg[28], f28, NULL, gcc_dwarf_f28_mips, gcc_dwarf_f28_mips, LLDB_INVALID_REGNUM, gdb_f28_mips), - DEFINE_FPR (fp_reg[29], f29, NULL, gcc_dwarf_f29_mips, gcc_dwarf_f29_mips, LLDB_INVALID_REGNUM, gdb_f29_mips), - DEFINE_FPR (fp_reg[30], f30, NULL, gcc_dwarf_f30_mips, gcc_dwarf_f30_mips, LLDB_INVALID_REGNUM, gdb_f30_mips), - DEFINE_FPR (fp_reg[31], f31, NULL, gcc_dwarf_f31_mips, gcc_dwarf_f31_mips, LLDB_INVALID_REGNUM, gdb_f31_mips), - DEFINE_FPR_INFO (fcsr, fcsr, NULL, gcc_dwarf_fcsr_mips, gcc_dwarf_fcsr_mips, LLDB_INVALID_REGNUM, gdb_fcsr_mips), - DEFINE_FPR_INFO (fir, fir, NULL, gcc_dwarf_fir_mips, gcc_dwarf_fir_mips, LLDB_INVALID_REGNUM, gdb_fir_mips) + DEFINE_GPR (pc, NULL, gcc_dwarf_pc_mips, gcc_dwarf_pc_mips, LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_REGNUM), + DEFINE_GPR (config5, NULL, gcc_dwarf_config5_mips, gcc_dwarf_config5_mips, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), + DEFINE_FPR (f0, NULL, gcc_dwarf_f0_mips, gcc_dwarf_f0_mips, LLDB_INVALID_REGNUM, gdb_f0_mips), + DEFINE_FPR (f1, NULL, gcc_dwarf_f1_mips, gcc_dwarf_f1_mips, LLDB_INVALID_REGNUM, gdb_f1_mips), + DEFINE_FPR (f2, NULL, gcc_dwarf_f2_mips, gcc_dwarf_f2_mips, LLDB_INVALID_REGNUM, gdb_f2_mips), + DEFINE_FPR (f3, NULL, gcc_dwarf_f3_mips, gcc_dwarf_f3_mips, LLDB_INVALID_REGNUM, gdb_f3_mips), + DEFINE_FPR (f4, NULL, gcc_dwarf_f4_mips, gcc_dwarf_f4_mips, LLDB_INVALID_REGNUM, gdb_f4_mips), + DEFINE_FPR (f5, NULL, gcc_dwarf_f5_mips, gcc_dwarf_f5_mips, LLDB_INVALID_REGNUM, gdb_f5_mips), + DEFINE_FPR (f6, NULL, gcc_dwarf_f6_mips, gcc_dwarf_f6_mips, LLDB_INVALID_REGNUM, gdb_f6_mips), + DEFINE_FPR (f7, NULL, gcc_dwarf_f7_mips, gcc_dwarf_f7_mips, LLDB_INVALID_REGNUM, gdb_f7_mips), + DEFINE_FPR (f8, NULL, gcc_dwarf_f8_mips, gcc_dwarf_f8_mips, LLDB_INVALID_REGNUM, gdb_f8_mips), + DEFINE_FPR (f9, NULL, gcc_dwarf_f9_mips, gcc_dwarf_f9_mips, LLDB_INVALID_REGNUM, gdb_f9_mips), + DEFINE_FPR (f10, NULL, gcc_dwarf_f10_mips, gcc_dwarf_f10_mips, LLDB_INVALID_REGNUM, gdb_f10_mips), + DEFINE_FPR (f11, NULL, gcc_dwarf_f11_mips, gcc_dwarf_f11_mips, LLDB_INVALID_REGNUM, gdb_f11_mips), + DEFINE_FPR (f12, NULL, gcc_dwarf_f12_mips, gcc_dwarf_f12_mips, LLDB_INVALID_REGNUM, gdb_f12_mips), + DEFINE_FPR (f13, NULL, gcc_dwarf_f13_mips, gcc_dwarf_f13_mips, LLDB_INVALID_REGNUM, gdb_f13_mips), + DEFINE_FPR (f14, NULL, gcc_dwarf_f14_mips, gcc_dwarf_f14_mips, LLDB_INVALID_REGNUM, gdb_f14_mips), + DEFINE_FPR (f15, NULL, gcc_dwarf_f15_mips, gcc_dwarf_f15_mips, LLDB_INVALID_REGNUM, gdb_f15_mips), + DEFINE_FPR (f16, NULL, gcc_dwarf_f16_mips, gcc_dwarf_f16_mips, LLDB_INVALID_REGNUM, gdb_f16_mips), + DEFINE_FPR (f17, NULL, gcc_dwarf_f17_mips, gcc_dwarf_f17_mips, LLDB_INVALID_REGNUM, gdb_f17_mips), + DEFINE_FPR (f18, NULL, gcc_dwarf_f18_mips, gcc_dwarf_f18_mips, LLDB_INVALID_REGNUM, gdb_f18_mips), + DEFINE_FPR (f19, NULL, gcc_dwarf_f19_mips, gcc_dwarf_f19_mips, LLDB_INVALID_REGNUM, gdb_f19_mips), + DEFINE_FPR (f20, NULL, gcc_dwarf_f20_mips, gcc_dwarf_f20_mips, LLDB_INVALID_REGNUM, gdb_f20_mips), + DEFINE_FPR (f21, NULL, gcc_dwarf_f21_mips, gcc_dwarf_f21_mips, LLDB_INVALID_REGNUM, gdb_f21_mips), + DEFINE_FPR (f22, NULL, gcc_dwarf_f22_mips, gcc_dwarf_f22_mips, LLDB_INVALID_REGNUM, gdb_f22_mips), + DEFINE_FPR (f23, NULL, gcc_dwarf_f23_mips, gcc_dwarf_f23_mips, LLDB_INVALID_REGNUM, gdb_f23_mips), + DEFINE_FPR (f24, NULL, gcc_dwarf_f24_mips, gcc_dwarf_f24_mips, LLDB_INVALID_REGNUM, gdb_f24_mips), + DEFINE_FPR (f25, NULL, gcc_dwarf_f25_mips, gcc_dwarf_f25_mips, LLDB_INVALID_REGNUM, gdb_f25_mips), + DEFINE_FPR (f26, NULL, gcc_dwarf_f26_mips, gcc_dwarf_f26_mips, LLDB_INVALID_REGNUM, gdb_f26_mips), + DEFINE_FPR (f27, NULL, gcc_dwarf_f27_mips, gcc_dwarf_f27_mips, LLDB_INVALID_REGNUM, gdb_f27_mips), + DEFINE_FPR (f28, NULL, gcc_dwarf_f28_mips, gcc_dwarf_f28_mips, LLDB_INVALID_REGNUM, gdb_f28_mips), + DEFINE_FPR (f29, NULL, gcc_dwarf_f29_mips, gcc_dwarf_f29_mips, LLDB_INVALID_REGNUM, gdb_f29_mips), + DEFINE_FPR (f30, NULL, gcc_dwarf_f30_mips, gcc_dwarf_f30_mips, LLDB_INVALID_REGNUM, gdb_f30_mips), + DEFINE_FPR (f31, NULL, gcc_dwarf_f31_mips, gcc_dwarf_f31_mips, LLDB_INVALID_REGNUM, gdb_f31_mips), + DEFINE_FPR (fcsr, NULL, gcc_dwarf_fcsr_mips, gcc_dwarf_fcsr_mips, LLDB_INVALID_REGNUM, gdb_fcsr_mips), + DEFINE_FPR (fir, NULL, gcc_dwarf_fir_mips, gcc_dwarf_fir_mips, LLDB_INVALID_REGNUM, gdb_fir_mips), + DEFINE_FPR (config5, NULL, gcc_dwarf_config5_mips, gcc_dwarf_config5_mips, LLDB_INVALID_REGNUM, gdb_config5_mips), + DEFINE_MSA (w0, NULL, gcc_dwarf_w0_mips, gcc_dwarf_w0_mips, LLDB_INVALID_REGNUM, gdb_w0_mips), + DEFINE_MSA (w1, NULL, gcc_dwarf_w1_mips, gcc_dwarf_w1_mips, LLDB_INVALID_REGNUM, gdb_w1_mips), + DEFINE_MSA (w2, NULL, gcc_dwarf_w2_mips, gcc_dwarf_w2_mips, LLDB_INVALID_REGNUM, gdb_w2_mips), + DEFINE_MSA (w3, NULL, gcc_dwarf_w3_mips, gcc_dwarf_w3_mips, LLDB_INVALID_REGNUM, gdb_w3_mips), + DEFINE_MSA (w4, NULL, gcc_dwarf_w4_mips, gcc_dwarf_w4_mips, LLDB_INVALID_REGNUM, gdb_w4_mips), + DEFINE_MSA (w5, NULL, gcc_dwarf_w5_mips, gcc_dwarf_w5_mips, LLDB_INVALID_REGNUM, gdb_w5_mips), + DEFINE_MSA (w6, NULL, gcc_dwarf_w6_mips, gcc_dwarf_w6_mips, LLDB_INVALID_REGNUM, gdb_w6_mips), + DEFINE_MSA (w7, NULL, gcc_dwarf_w7_mips, gcc_dwarf_w7_mips, LLDB_INVALID_REGNUM, gdb_w7_mips), + DEFINE_MSA (w8, NULL, gcc_dwarf_w8_mips, gcc_dwarf_w8_mips, LLDB_INVALID_REGNUM, gdb_w8_mips), + DEFINE_MSA (w9, NULL, gcc_dwarf_w9_mips, gcc_dwarf_w9_mips, LLDB_INVALID_REGNUM, gdb_w9_mips), + DEFINE_MSA (w10, NULL, gcc_dwarf_w10_mips, gcc_dwarf_w10_mips, LLDB_INVALID_REGNUM, gdb_w10_mips), + DEFINE_MSA (w11, NULL, gcc_dwarf_w11_mips, gcc_dwarf_w11_mips, LLDB_INVALID_REGNUM, gdb_w11_mips), + DEFINE_MSA (w12, NULL, gcc_dwarf_w12_mips, gcc_dwarf_w12_mips, LLDB_INVALID_REGNUM, gdb_w12_mips), + DEFINE_MSA (w13, NULL, gcc_dwarf_w13_mips, gcc_dwarf_w13_mips, LLDB_INVALID_REGNUM, gdb_w13_mips), + DEFINE_MSA (w14, NULL, gcc_dwarf_w14_mips, gcc_dwarf_w14_mips, LLDB_INVALID_REGNUM, gdb_w14_mips), + DEFINE_MSA (w15, NULL, gcc_dwarf_w15_mips, gcc_dwarf_w15_mips, LLDB_INVALID_REGNUM, gdb_w15_mips), + DEFINE_MSA (w16, NULL, gcc_dwarf_w16_mips, gcc_dwarf_w16_mips, LLDB_INVALID_REGNUM, gdb_w16_mips), + DEFINE_MSA (w17, NULL, gcc_dwarf_w17_mips, gcc_dwarf_w17_mips, LLDB_INVALID_REGNUM, gdb_w17_mips), + DEFINE_MSA (w18, NULL, gcc_dwarf_w18_mips, gcc_dwarf_w18_mips, LLDB_INVALID_REGNUM, gdb_w18_mips), + DEFINE_MSA (w19, NULL, gcc_dwarf_w19_mips, gcc_dwarf_w19_mips, LLDB_INVALID_REGNUM, gdb_w19_mips), + DEFINE_MSA (w20, NULL, gcc_dwarf_w10_mips, gcc_dwarf_w20_mips, LLDB_INVALID_REGNUM, gdb_w20_mips), + DEFINE_MSA (w21, NULL, gcc_dwarf_w21_mips, gcc_dwarf_w21_mips, LLDB_INVALID_REGNUM, gdb_w21_mips), + DEFINE_MSA (w22, NULL, gcc_dwarf_w22_mips, gcc_dwarf_w22_mips, LLDB_INVALID_REGNUM, gdb_w22_mips), + DEFINE_MSA (w23, NULL, gcc_dwarf_w23_mips, gcc_dwarf_w23_mips, LLDB_INVALID_REGNUM, gdb_w23_mips), + DEFINE_MSA (w24, NULL, gcc_dwarf_w24_mips, gcc_dwarf_w24_mips, LLDB_INVALID_REGNUM, gdb_w24_mips), + DEFINE_MSA (w25, NULL, gcc_dwarf_w25_mips, gcc_dwarf_w25_mips, LLDB_INVALID_REGNUM, gdb_w25_mips), + DEFINE_MSA (w26, NULL, gcc_dwarf_w26_mips, gcc_dwarf_w26_mips, LLDB_INVALID_REGNUM, gdb_w26_mips), + DEFINE_MSA (w27, NULL, gcc_dwarf_w27_mips, gcc_dwarf_w27_mips, LLDB_INVALID_REGNUM, gdb_w27_mips), + DEFINE_MSA (w28, NULL, gcc_dwarf_w28_mips, gcc_dwarf_w28_mips, LLDB_INVALID_REGNUM, gdb_w28_mips), + DEFINE_MSA (w29, NULL, gcc_dwarf_w29_mips, gcc_dwarf_w29_mips, LLDB_INVALID_REGNUM, gdb_w29_mips), + DEFINE_MSA (w30, NULL, gcc_dwarf_w30_mips, gcc_dwarf_w30_mips, LLDB_INVALID_REGNUM, gdb_w30_mips), + DEFINE_MSA (w31, NULL, gcc_dwarf_w31_mips, gcc_dwarf_w31_mips, LLDB_INVALID_REGNUM, gdb_w31_mips), + DEFINE_MSA_INFO (mcsr, NULL, gcc_dwarf_mcsr_mips, gcc_dwarf_mcsr_mips, LLDB_INVALID_REGNUM, gdb_mcsr_mips), + DEFINE_MSA_INFO (mir, NULL, gcc_dwarf_mir_mips, gcc_dwarf_mir_mips, LLDB_INVALID_REGNUM, gdb_mir_mips), + DEFINE_MSA_INFO (fcsr, NULL, gcc_dwarf_fcsr_mips, gcc_dwarf_fcsr_mips, LLDB_INVALID_REGNUM, gdb_fcsr_mips), + DEFINE_MSA_INFO (fir, NULL, gcc_dwarf_fir_mips, gcc_dwarf_fir_mips, LLDB_INVALID_REGNUM, gdb_fir_mips), + DEFINE_MSA_INFO (config5, NULL, gcc_dwarf_config5_mips, gcc_dwarf_config5_mips, LLDB_INVALID_REGNUM, gdb_config5_mips) }; static_assert((sizeof(g_register_infos_mips) / sizeof(g_register_infos_mips[0])) == k_num_registers_mips, "g_register_infos_mips has wrong number of register infos"); #undef GPR_OFFSET #undef FPR_OFFSET +#undef MSA_OFFSET #undef DEFINE_GPR #undef DEFINE_FPR +#undef DEFINE_MSA +#undef DEFINE_MSA_INFO #endif // DECLARE_REGISTER_INFOS_MIPS_STRUCT diff --git a/source/Plugins/Process/Utility/RegisterInfos_mips64.h b/source/Plugins/Process/Utility/RegisterInfos_mips64.h index e03aea4e3f2c..101842e66d49 100644 --- a/source/Plugins/Process/Utility/RegisterInfos_mips64.h +++ b/source/Plugins/Process/Utility/RegisterInfos_mips64.h @@ -13,28 +13,59 @@ #ifdef DECLARE_REGISTER_INFOS_MIPS64_STRUCT // Computes the offset of the given GPR in the user data area. -#define GPR_OFFSET(regname) \ - (LLVM_EXTENSION offsetof(GPR, regname)) +#ifdef LINUX_MIPS64 + #define GPR_OFFSET(regname) \ + (LLVM_EXTENSION offsetof(UserArea, gpr) + \ + LLVM_EXTENSION offsetof(GPR_linux_mips, regname)) +#else + #define GPR_OFFSET(regname) \ + (LLVM_EXTENSION offsetof(GPR_freebsd_mips, regname)) +#endif // Computes the offset of the given FPR in the extended data area. #define FPR_OFFSET(regname) \ - LLVM_EXTENSION offsetof(FPR_mips, regname) \ + (LLVM_EXTENSION offsetof(UserArea, fpr) + \ + LLVM_EXTENSION offsetof(FPR_linux_mips, regname)) + +// Computes the offset of the given MSA in the extended data area. +#define MSA_OFFSET(regname) \ + (LLVM_EXTENSION offsetof(UserArea, msa) + \ + LLVM_EXTENSION offsetof(MSA_linux_mips, regname)) // RegisterKind: GCC, DWARF, Generic, GDB, LLDB // Note that the size and offset will be updated by platform-specific classes. -#define DEFINE_GPR(reg, alt, kind1, kind2, kind3, kind4) \ - { #reg, alt, sizeof(((GPR*)0)->reg), GPR_OFFSET(reg), eEncodingUint, \ +#ifdef LINUX_MIPS64 + #define DEFINE_GPR(reg, alt, kind1, kind2, kind3, kind4) \ + { #reg, alt, sizeof(((GPR_linux_mips*)0)->reg), GPR_OFFSET(reg), eEncodingUint, \ + eFormatHex, { kind1, kind2, kind3, kind4, gpr_##reg##_mips64 }, NULL, NULL } +#else + #define DEFINE_GPR(reg, alt, kind1, kind2, kind3, kind4) \ + { #reg, alt, sizeof(((GPR_freebsd_mips*)0)->reg), GPR_OFFSET(reg), eEncodingUint, \ + eFormatHex, { kind1, kind2, kind3, kind4, gpr_##reg##_mips64 }, NULL, NULL } +#endif + +#define DEFINE_GPR_INFO(reg, alt, kind1, kind2, kind3, kind4) \ + { #reg, alt, sizeof(((GPR_linux_mips*)0)->reg) / 2, GPR_OFFSET(reg), eEncodingUint, \ eFormatHex, { kind1, kind2, kind3, kind4, gpr_##reg##_mips64 }, NULL, NULL } -#define DEFINE_FPR(member, reg, alt, kind1, kind2, kind3, kind4) \ - { #reg, alt, sizeof(((FPR_mips*)0)->member), FPR_OFFSET(member), eEncodingUint, \ +#define DEFINE_FPR(reg, alt, kind1, kind2, kind3, kind4) \ + { #reg, alt, sizeof(((FPR_linux_mips*)0)->reg), FPR_OFFSET(reg), eEncodingUint, \ eFormatHex, { kind1, kind2, kind3, kind4, fpr_##reg##_mips64 }, NULL, NULL } +#define DEFINE_MSA(reg, alt, kind1, kind2, kind3, kind4) \ + { #reg, alt, sizeof(((MSA_linux_mips*)0)->reg), MSA_OFFSET(reg), eEncodingVector, \ + eFormatVectorOfUInt8, { kind1, kind2, kind3, kind4, msa_##reg##_mips64 }, NULL, NULL } + +#define DEFINE_MSA_INFO(reg, alt, kind1, kind2, kind3, kind4) \ + { #reg, alt, sizeof(((MSA_linux_mips*)0)->reg), MSA_OFFSET(reg), eEncodingUint, \ + eFormatHex, { kind1, kind2, kind3, kind4, msa_##reg##_mips64 }, NULL, NULL } + static RegisterInfo g_register_infos_mips64[] = { // General purpose registers. GCC, DWARF, Generic, GDB +#ifndef LINUX_MIPS64 DEFINE_GPR(zero, "r0", gcc_dwarf_zero_mips64, gcc_dwarf_zero_mips64, LLDB_INVALID_REGNUM, gdb_zero_mips64), DEFINE_GPR(r1, NULL, gcc_dwarf_r1_mips64, gcc_dwarf_r1_mips64, LLDB_INVALID_REGNUM, gdb_r1_mips64), DEFINE_GPR(r2, NULL, gcc_dwarf_r2_mips64, gcc_dwarf_r2_mips64, LLDB_INVALID_REGNUM, gdb_r2_mips64), @@ -67,56 +98,140 @@ g_register_infos_mips64[] = DEFINE_GPR(sp, "r29", gcc_dwarf_sp_mips64, gcc_dwarf_sp_mips64, LLDB_REGNUM_GENERIC_SP, gdb_sp_mips64), DEFINE_GPR(r30, NULL, gcc_dwarf_r30_mips64, gcc_dwarf_r30_mips64, LLDB_REGNUM_GENERIC_FP, gdb_r30_mips64), DEFINE_GPR(ra, "r31", gcc_dwarf_ra_mips64, gcc_dwarf_ra_mips64, LLDB_REGNUM_GENERIC_RA, gdb_ra_mips64), + DEFINE_GPR(sr, NULL, gcc_dwarf_sr_mips64, gcc_dwarf_sr_mips64, LLDB_REGNUM_GENERIC_FLAGS, LLDB_INVALID_REGNUM), DEFINE_GPR(mullo, NULL, gcc_dwarf_lo_mips64, gcc_dwarf_lo_mips64, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), DEFINE_GPR(mulhi, NULL, gcc_dwarf_hi_mips64, gcc_dwarf_hi_mips64, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), - DEFINE_GPR(pc, "pc", gcc_dwarf_pc_mips64, gcc_dwarf_pc_mips64, LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_REGNUM), DEFINE_GPR(badvaddr, NULL, gcc_dwarf_bad_mips64, gcc_dwarf_bad_mips64, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), - DEFINE_GPR(sr, NULL, gcc_dwarf_sr_mips64, gcc_dwarf_sr_mips64, LLDB_REGNUM_GENERIC_FLAGS, LLDB_INVALID_REGNUM), DEFINE_GPR(cause, NULL, gcc_dwarf_cause_mips64, gcc_dwarf_cause_mips64, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), + DEFINE_GPR(pc, "pc", gcc_dwarf_pc_mips64, gcc_dwarf_pc_mips64, LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_REGNUM), DEFINE_GPR(ic, NULL, gcc_dwarf_ic_mips64, gcc_dwarf_ic_mips64, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), DEFINE_GPR(dummy, NULL, gcc_dwarf_dummy_mips64, gcc_dwarf_dummy_mips64, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), +#else - DEFINE_FPR (fp_reg[0], f0, NULL, gcc_dwarf_f0_mips64, gcc_dwarf_f0_mips64, LLDB_INVALID_REGNUM, gdb_f0_mips64), - DEFINE_FPR (fp_reg[1], f1, NULL, gcc_dwarf_f1_mips64, gcc_dwarf_f1_mips64, LLDB_INVALID_REGNUM, gdb_f1_mips64), - DEFINE_FPR (fp_reg[2], f2, NULL, gcc_dwarf_f2_mips64, gcc_dwarf_f2_mips64, LLDB_INVALID_REGNUM, gdb_f2_mips64), - DEFINE_FPR (fp_reg[3], f3, NULL, gcc_dwarf_f3_mips64, gcc_dwarf_f3_mips64, LLDB_INVALID_REGNUM, gdb_f3_mips64), - DEFINE_FPR (fp_reg[4], f4, NULL, gcc_dwarf_f4_mips64, gcc_dwarf_f4_mips64, LLDB_INVALID_REGNUM, gdb_f4_mips64), - DEFINE_FPR (fp_reg[5], f5, NULL, gcc_dwarf_f5_mips64, gcc_dwarf_f5_mips64, LLDB_INVALID_REGNUM, gdb_f5_mips64), - DEFINE_FPR (fp_reg[6], f6, NULL, gcc_dwarf_f6_mips64, gcc_dwarf_f6_mips64, LLDB_INVALID_REGNUM, gdb_f6_mips64), - DEFINE_FPR (fp_reg[7], f7, NULL, gcc_dwarf_f7_mips64, gcc_dwarf_f7_mips64, LLDB_INVALID_REGNUM, gdb_f7_mips64), - DEFINE_FPR (fp_reg[8], f8, NULL, gcc_dwarf_f8_mips64, gcc_dwarf_f8_mips64, LLDB_INVALID_REGNUM, gdb_f8_mips64), - DEFINE_FPR (fp_reg[9], f9, NULL, gcc_dwarf_f9_mips64, gcc_dwarf_f9_mips64, LLDB_INVALID_REGNUM, gdb_f9_mips64), - DEFINE_FPR (fp_reg[10], f10, NULL, gcc_dwarf_f10_mips64, gcc_dwarf_f10_mips64, LLDB_INVALID_REGNUM, gdb_f10_mips64), - DEFINE_FPR (fp_reg[11], f11, NULL, gcc_dwarf_f11_mips64, gcc_dwarf_f11_mips64, LLDB_INVALID_REGNUM, gdb_f11_mips64), - DEFINE_FPR (fp_reg[12], f12, NULL, gcc_dwarf_f12_mips64, gcc_dwarf_f12_mips64, LLDB_INVALID_REGNUM, gdb_f12_mips64), - DEFINE_FPR (fp_reg[13], f13, NULL, gcc_dwarf_f13_mips64, gcc_dwarf_f13_mips64, LLDB_INVALID_REGNUM, gdb_f13_mips64), - DEFINE_FPR (fp_reg[14], f14, NULL, gcc_dwarf_f14_mips64, gcc_dwarf_f14_mips64, LLDB_INVALID_REGNUM, gdb_f14_mips64), - DEFINE_FPR (fp_reg[15], f15, NULL, gcc_dwarf_f15_mips64, gcc_dwarf_f15_mips64, LLDB_INVALID_REGNUM, gdb_f15_mips64), - DEFINE_FPR (fp_reg[16], f16, NULL, gcc_dwarf_f16_mips64, gcc_dwarf_f16_mips64, LLDB_INVALID_REGNUM, gdb_f16_mips64), - DEFINE_FPR (fp_reg[17], f17, NULL, gcc_dwarf_f17_mips64, gcc_dwarf_f17_mips64, LLDB_INVALID_REGNUM, gdb_f17_mips64), - DEFINE_FPR (fp_reg[18], f18, NULL, gcc_dwarf_f18_mips64, gcc_dwarf_f18_mips64, LLDB_INVALID_REGNUM, gdb_f18_mips64), - DEFINE_FPR (fp_reg[19], f19, NULL, gcc_dwarf_f19_mips64, gcc_dwarf_f19_mips64, LLDB_INVALID_REGNUM, gdb_f19_mips64), - DEFINE_FPR (fp_reg[20], f20, NULL, gcc_dwarf_f20_mips64, gcc_dwarf_f20_mips64, LLDB_INVALID_REGNUM, gdb_f20_mips64), - DEFINE_FPR (fp_reg[21], f21, NULL, gcc_dwarf_f21_mips64, gcc_dwarf_f21_mips64, LLDB_INVALID_REGNUM, gdb_f21_mips64), - DEFINE_FPR (fp_reg[22], f22, NULL, gcc_dwarf_f22_mips64, gcc_dwarf_f22_mips64, LLDB_INVALID_REGNUM, gdb_f22_mips64), - DEFINE_FPR (fp_reg[23], f23, NULL, gcc_dwarf_f23_mips64, gcc_dwarf_f23_mips64, LLDB_INVALID_REGNUM, gdb_f23_mips64), - DEFINE_FPR (fp_reg[24], f24, NULL, gcc_dwarf_f24_mips64, gcc_dwarf_f24_mips64, LLDB_INVALID_REGNUM, gdb_f24_mips64), - DEFINE_FPR (fp_reg[25], f25, NULL, gcc_dwarf_f25_mips64, gcc_dwarf_f25_mips64, LLDB_INVALID_REGNUM, gdb_f25_mips64), - DEFINE_FPR (fp_reg[26], f26, NULL, gcc_dwarf_f26_mips64, gcc_dwarf_f26_mips64, LLDB_INVALID_REGNUM, gdb_f26_mips64), - DEFINE_FPR (fp_reg[27], f27, NULL, gcc_dwarf_f27_mips64, gcc_dwarf_f27_mips64, LLDB_INVALID_REGNUM, gdb_f27_mips64), - DEFINE_FPR (fp_reg[28], f28, NULL, gcc_dwarf_f28_mips64, gcc_dwarf_f28_mips64, LLDB_INVALID_REGNUM, gdb_f28_mips64), - DEFINE_FPR (fp_reg[29], f29, NULL, gcc_dwarf_f29_mips64, gcc_dwarf_f29_mips64, LLDB_INVALID_REGNUM, gdb_f29_mips64), - DEFINE_FPR (fp_reg[30], f30, NULL, gcc_dwarf_f30_mips64, gcc_dwarf_f30_mips64, LLDB_INVALID_REGNUM, gdb_f30_mips64), - DEFINE_FPR (fp_reg[31], f31, NULL, gcc_dwarf_f31_mips64, gcc_dwarf_f31_mips64, LLDB_INVALID_REGNUM, gdb_f31_mips64), - DEFINE_FPR (fcsr, fcsr, NULL, gcc_dwarf_fcsr_mips64, gcc_dwarf_fcsr_mips64, LLDB_INVALID_REGNUM, gdb_fcsr_mips64), - DEFINE_FPR (fir, fir, NULL, gcc_dwarf_fir_mips64, gcc_dwarf_fir_mips64, LLDB_INVALID_REGNUM, gdb_fir_mips64) + DEFINE_GPR(zero, "r0", gcc_dwarf_zero_mips64, gcc_dwarf_zero_mips64, LLDB_INVALID_REGNUM, gdb_zero_mips64), + DEFINE_GPR(r1, NULL, gcc_dwarf_r1_mips64, gcc_dwarf_r1_mips64, LLDB_INVALID_REGNUM, gdb_r1_mips64), + DEFINE_GPR(r2, NULL, gcc_dwarf_r2_mips64, gcc_dwarf_r2_mips64, LLDB_INVALID_REGNUM, gdb_r2_mips64), + DEFINE_GPR(r3, NULL, gcc_dwarf_r3_mips64, gcc_dwarf_r3_mips64, LLDB_INVALID_REGNUM, gdb_r3_mips64), + DEFINE_GPR(r4, NULL, gcc_dwarf_r4_mips64, gcc_dwarf_r4_mips64, LLDB_REGNUM_GENERIC_ARG1, gdb_r4_mips64), + DEFINE_GPR(r5, NULL, gcc_dwarf_r5_mips64, gcc_dwarf_r5_mips64, LLDB_REGNUM_GENERIC_ARG2, gdb_r5_mips64), + DEFINE_GPR(r6, NULL, gcc_dwarf_r6_mips64, gcc_dwarf_r6_mips64, LLDB_REGNUM_GENERIC_ARG3, gdb_r6_mips64), + DEFINE_GPR(r7, NULL, gcc_dwarf_r7_mips64, gcc_dwarf_r7_mips64, LLDB_REGNUM_GENERIC_ARG4, gdb_r7_mips64), + DEFINE_GPR(r8, NULL, gcc_dwarf_r8_mips64, gcc_dwarf_r8_mips64, LLDB_REGNUM_GENERIC_ARG5, gdb_r8_mips64), + DEFINE_GPR(r9, NULL, gcc_dwarf_r9_mips64, gcc_dwarf_r9_mips64, LLDB_REGNUM_GENERIC_ARG6, gdb_r9_mips64), + DEFINE_GPR(r10, NULL, gcc_dwarf_r10_mips64, gcc_dwarf_r10_mips64, LLDB_REGNUM_GENERIC_ARG7, gdb_r10_mips64), + DEFINE_GPR(r11, NULL, gcc_dwarf_r11_mips64, gcc_dwarf_r11_mips64, LLDB_REGNUM_GENERIC_ARG8, gdb_r11_mips64), + DEFINE_GPR(r12, NULL, gcc_dwarf_r12_mips64, gcc_dwarf_r12_mips64, LLDB_INVALID_REGNUM, gdb_r12_mips64), + DEFINE_GPR(r13, NULL, gcc_dwarf_r13_mips64, gcc_dwarf_r13_mips64, LLDB_INVALID_REGNUM, gdb_r13_mips64), + DEFINE_GPR(r14, NULL, gcc_dwarf_r14_mips64, gcc_dwarf_r14_mips64, LLDB_INVALID_REGNUM, gdb_r14_mips64), + DEFINE_GPR(r15, NULL, gcc_dwarf_r15_mips64, gcc_dwarf_r15_mips64, LLDB_INVALID_REGNUM, gdb_r15_mips64), + DEFINE_GPR(r16, NULL, gcc_dwarf_r16_mips64, gcc_dwarf_r16_mips64, LLDB_INVALID_REGNUM, gdb_r16_mips64), + DEFINE_GPR(r17, NULL, gcc_dwarf_r17_mips64, gcc_dwarf_r17_mips64, LLDB_INVALID_REGNUM, gdb_r17_mips64), + DEFINE_GPR(r18, NULL, gcc_dwarf_r18_mips64, gcc_dwarf_r18_mips64, LLDB_INVALID_REGNUM, gdb_r18_mips64), + DEFINE_GPR(r19, NULL, gcc_dwarf_r19_mips64, gcc_dwarf_r19_mips64, LLDB_INVALID_REGNUM, gdb_r19_mips64), + DEFINE_GPR(r20, NULL, gcc_dwarf_r20_mips64, gcc_dwarf_r20_mips64, LLDB_INVALID_REGNUM, gdb_r20_mips64), + DEFINE_GPR(r21, NULL, gcc_dwarf_r21_mips64, gcc_dwarf_r21_mips64, LLDB_INVALID_REGNUM, gdb_r21_mips64), + DEFINE_GPR(r22, NULL, gcc_dwarf_r22_mips64, gcc_dwarf_r22_mips64, LLDB_INVALID_REGNUM, gdb_r22_mips64), + DEFINE_GPR(r23, NULL, gcc_dwarf_r23_mips64, gcc_dwarf_r23_mips64, LLDB_INVALID_REGNUM, gdb_r23_mips64), + DEFINE_GPR(r24, NULL, gcc_dwarf_r24_mips64, gcc_dwarf_r24_mips64, LLDB_INVALID_REGNUM, gdb_r24_mips64), + DEFINE_GPR(r25, NULL, gcc_dwarf_r25_mips64, gcc_dwarf_r25_mips64, LLDB_INVALID_REGNUM, gdb_r25_mips64), + DEFINE_GPR(r26, NULL, gcc_dwarf_r26_mips64, gcc_dwarf_r26_mips64, LLDB_INVALID_REGNUM, gdb_r26_mips64), + DEFINE_GPR(r27, NULL, gcc_dwarf_r27_mips64, gcc_dwarf_r27_mips64, LLDB_INVALID_REGNUM, gdb_r27_mips64), + DEFINE_GPR(gp, "r28", gcc_dwarf_gp_mips64, gcc_dwarf_gp_mips64, LLDB_INVALID_REGNUM, gdb_gp_mips64), + DEFINE_GPR(sp, "r29", gcc_dwarf_sp_mips64, gcc_dwarf_sp_mips64, LLDB_REGNUM_GENERIC_SP, gdb_sp_mips64), + DEFINE_GPR(r30, NULL, gcc_dwarf_r30_mips64, gcc_dwarf_r30_mips64, LLDB_REGNUM_GENERIC_FP, gdb_r30_mips64), + DEFINE_GPR(ra, "r31", gcc_dwarf_ra_mips64, gcc_dwarf_ra_mips64, LLDB_REGNUM_GENERIC_RA, gdb_ra_mips64), + DEFINE_GPR_INFO(sr, NULL, gcc_dwarf_sr_mips64, gcc_dwarf_sr_mips64, LLDB_REGNUM_GENERIC_FLAGS, LLDB_INVALID_REGNUM), + DEFINE_GPR(mullo, NULL, gcc_dwarf_lo_mips64, gcc_dwarf_lo_mips64, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), + DEFINE_GPR(mulhi, NULL, gcc_dwarf_hi_mips64, gcc_dwarf_hi_mips64, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), + DEFINE_GPR(badvaddr, NULL, gcc_dwarf_bad_mips64, gcc_dwarf_bad_mips64, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), + DEFINE_GPR_INFO(cause, NULL, gcc_dwarf_cause_mips64, gcc_dwarf_cause_mips64, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), + DEFINE_GPR(pc, "pc", gcc_dwarf_pc_mips64, gcc_dwarf_pc_mips64, LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_REGNUM), + DEFINE_GPR_INFO(config5, NULL, gcc_dwarf_config5_mips64, gcc_dwarf_config5_mips64, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM), + DEFINE_FPR (f0, NULL, gcc_dwarf_f0_mips64, gcc_dwarf_f0_mips64, LLDB_INVALID_REGNUM, gdb_f0_mips64), + DEFINE_FPR (f1, NULL, gcc_dwarf_f1_mips64, gcc_dwarf_f1_mips64, LLDB_INVALID_REGNUM, gdb_f1_mips64), + DEFINE_FPR (f2, NULL, gcc_dwarf_f2_mips64, gcc_dwarf_f2_mips64, LLDB_INVALID_REGNUM, gdb_f2_mips64), + DEFINE_FPR (f3, NULL, gcc_dwarf_f3_mips64, gcc_dwarf_f3_mips64, LLDB_INVALID_REGNUM, gdb_f3_mips64), + DEFINE_FPR (f4, NULL, gcc_dwarf_f4_mips64, gcc_dwarf_f4_mips64, LLDB_INVALID_REGNUM, gdb_f4_mips64), + DEFINE_FPR (f5, NULL, gcc_dwarf_f5_mips64, gcc_dwarf_f5_mips64, LLDB_INVALID_REGNUM, gdb_f5_mips64), + DEFINE_FPR (f6, NULL, gcc_dwarf_f6_mips64, gcc_dwarf_f6_mips64, LLDB_INVALID_REGNUM, gdb_f6_mips64), + DEFINE_FPR (f7, NULL, gcc_dwarf_f7_mips64, gcc_dwarf_f7_mips64, LLDB_INVALID_REGNUM, gdb_f7_mips64), + DEFINE_FPR (f8, NULL, gcc_dwarf_f8_mips64, gcc_dwarf_f8_mips64, LLDB_INVALID_REGNUM, gdb_f8_mips64), + DEFINE_FPR (f9, NULL, gcc_dwarf_f9_mips64, gcc_dwarf_f9_mips64, LLDB_INVALID_REGNUM, gdb_f9_mips64), + DEFINE_FPR (f10, NULL, gcc_dwarf_f10_mips64, gcc_dwarf_f10_mips64, LLDB_INVALID_REGNUM, gdb_f10_mips64), + DEFINE_FPR (f11, NULL, gcc_dwarf_f11_mips64, gcc_dwarf_f11_mips64, LLDB_INVALID_REGNUM, gdb_f11_mips64), + DEFINE_FPR (f12, NULL, gcc_dwarf_f12_mips64, gcc_dwarf_f12_mips64, LLDB_INVALID_REGNUM, gdb_f12_mips64), + DEFINE_FPR (f13, NULL, gcc_dwarf_f13_mips64, gcc_dwarf_f13_mips64, LLDB_INVALID_REGNUM, gdb_f13_mips64), + DEFINE_FPR (f14, NULL, gcc_dwarf_f14_mips64, gcc_dwarf_f14_mips64, LLDB_INVALID_REGNUM, gdb_f14_mips64), + DEFINE_FPR (f15, NULL, gcc_dwarf_f15_mips64, gcc_dwarf_f15_mips64, LLDB_INVALID_REGNUM, gdb_f15_mips64), + DEFINE_FPR (f16, NULL, gcc_dwarf_f16_mips64, gcc_dwarf_f16_mips64, LLDB_INVALID_REGNUM, gdb_f16_mips64), + DEFINE_FPR (f17, NULL, gcc_dwarf_f17_mips64, gcc_dwarf_f17_mips64, LLDB_INVALID_REGNUM, gdb_f17_mips64), + DEFINE_FPR (f18, NULL, gcc_dwarf_f18_mips64, gcc_dwarf_f18_mips64, LLDB_INVALID_REGNUM, gdb_f18_mips64), + DEFINE_FPR (f19, NULL, gcc_dwarf_f19_mips64, gcc_dwarf_f19_mips64, LLDB_INVALID_REGNUM, gdb_f19_mips64), + DEFINE_FPR (f20, NULL, gcc_dwarf_f20_mips64, gcc_dwarf_f20_mips64, LLDB_INVALID_REGNUM, gdb_f20_mips64), + DEFINE_FPR (f21, NULL, gcc_dwarf_f21_mips64, gcc_dwarf_f21_mips64, LLDB_INVALID_REGNUM, gdb_f21_mips64), + DEFINE_FPR (f22, NULL, gcc_dwarf_f22_mips64, gcc_dwarf_f22_mips64, LLDB_INVALID_REGNUM, gdb_f22_mips64), + DEFINE_FPR (f23, NULL, gcc_dwarf_f23_mips64, gcc_dwarf_f23_mips64, LLDB_INVALID_REGNUM, gdb_f23_mips64), + DEFINE_FPR (f24, NULL, gcc_dwarf_f24_mips64, gcc_dwarf_f24_mips64, LLDB_INVALID_REGNUM, gdb_f24_mips64), + DEFINE_FPR (f25, NULL, gcc_dwarf_f25_mips64, gcc_dwarf_f25_mips64, LLDB_INVALID_REGNUM, gdb_f25_mips64), + DEFINE_FPR (f26, NULL, gcc_dwarf_f26_mips64, gcc_dwarf_f26_mips64, LLDB_INVALID_REGNUM, gdb_f26_mips64), + DEFINE_FPR (f27, NULL, gcc_dwarf_f27_mips64, gcc_dwarf_f27_mips64, LLDB_INVALID_REGNUM, gdb_f27_mips64), + DEFINE_FPR (f28, NULL, gcc_dwarf_f28_mips64, gcc_dwarf_f28_mips64, LLDB_INVALID_REGNUM, gdb_f28_mips64), + DEFINE_FPR (f29, NULL, gcc_dwarf_f29_mips64, gcc_dwarf_f29_mips64, LLDB_INVALID_REGNUM, gdb_f29_mips64), + DEFINE_FPR (f30, NULL, gcc_dwarf_f30_mips64, gcc_dwarf_f30_mips64, LLDB_INVALID_REGNUM, gdb_f30_mips64), + DEFINE_FPR (f31, NULL, gcc_dwarf_f31_mips64, gcc_dwarf_f31_mips64, LLDB_INVALID_REGNUM, gdb_f31_mips64), + DEFINE_FPR (fcsr, NULL, gcc_dwarf_fcsr_mips64, gcc_dwarf_fcsr_mips64, LLDB_INVALID_REGNUM, gdb_fcsr_mips64), + DEFINE_FPR (fir, NULL, gcc_dwarf_fir_mips64, gcc_dwarf_fir_mips64, LLDB_INVALID_REGNUM, gdb_fir_mips64), + DEFINE_FPR (config5, NULL, gcc_dwarf_config5_mips64, gcc_dwarf_config5_mips64, LLDB_INVALID_REGNUM, gdb_config5_mips64), + DEFINE_MSA (w0, NULL, gcc_dwarf_w0_mips64, gcc_dwarf_w0_mips64, LLDB_INVALID_REGNUM, gdb_w0_mips64), + DEFINE_MSA (w1, NULL, gcc_dwarf_w1_mips64, gcc_dwarf_w1_mips64, LLDB_INVALID_REGNUM, gdb_w1_mips64), + DEFINE_MSA (w2, NULL, gcc_dwarf_w2_mips64, gcc_dwarf_w2_mips64, LLDB_INVALID_REGNUM, gdb_w2_mips64), + DEFINE_MSA (w3, NULL, gcc_dwarf_w3_mips64, gcc_dwarf_w3_mips64, LLDB_INVALID_REGNUM, gdb_w3_mips64), + DEFINE_MSA (w4, NULL, gcc_dwarf_w4_mips64, gcc_dwarf_w4_mips64, LLDB_INVALID_REGNUM, gdb_w4_mips64), + DEFINE_MSA (w5, NULL, gcc_dwarf_w5_mips64, gcc_dwarf_w5_mips64, LLDB_INVALID_REGNUM, gdb_w5_mips64), + DEFINE_MSA (w6, NULL, gcc_dwarf_w6_mips64, gcc_dwarf_w6_mips64, LLDB_INVALID_REGNUM, gdb_w6_mips64), + DEFINE_MSA (w7, NULL, gcc_dwarf_w7_mips64, gcc_dwarf_w7_mips64, LLDB_INVALID_REGNUM, gdb_w7_mips64), + DEFINE_MSA (w8, NULL, gcc_dwarf_w8_mips64, gcc_dwarf_w8_mips64, LLDB_INVALID_REGNUM, gdb_w8_mips64), + DEFINE_MSA (w9, NULL, gcc_dwarf_w9_mips64, gcc_dwarf_w9_mips64, LLDB_INVALID_REGNUM, gdb_w9_mips64), + DEFINE_MSA (w10, NULL, gcc_dwarf_w10_mips64, gcc_dwarf_w10_mips64, LLDB_INVALID_REGNUM, gdb_w10_mips64), + DEFINE_MSA (w11, NULL, gcc_dwarf_w11_mips64, gcc_dwarf_w11_mips64, LLDB_INVALID_REGNUM, gdb_w11_mips64), + DEFINE_MSA (w12, NULL, gcc_dwarf_w12_mips64, gcc_dwarf_w12_mips64, LLDB_INVALID_REGNUM, gdb_w12_mips64), + DEFINE_MSA (w13, NULL, gcc_dwarf_w13_mips64, gcc_dwarf_w13_mips64, LLDB_INVALID_REGNUM, gdb_w13_mips64), + DEFINE_MSA (w14, NULL, gcc_dwarf_w14_mips64, gcc_dwarf_w14_mips64, LLDB_INVALID_REGNUM, gdb_w14_mips64), + DEFINE_MSA (w15, NULL, gcc_dwarf_w15_mips64, gcc_dwarf_w15_mips64, LLDB_INVALID_REGNUM, gdb_w15_mips64), + DEFINE_MSA (w16, NULL, gcc_dwarf_w16_mips64, gcc_dwarf_w16_mips64, LLDB_INVALID_REGNUM, gdb_w16_mips64), + DEFINE_MSA (w17, NULL, gcc_dwarf_w17_mips64, gcc_dwarf_w17_mips64, LLDB_INVALID_REGNUM, gdb_w17_mips64), + DEFINE_MSA (w18, NULL, gcc_dwarf_w18_mips64, gcc_dwarf_w18_mips64, LLDB_INVALID_REGNUM, gdb_w18_mips64), + DEFINE_MSA (w19, NULL, gcc_dwarf_w19_mips64, gcc_dwarf_w19_mips64, LLDB_INVALID_REGNUM, gdb_w19_mips64), + DEFINE_MSA (w20, NULL, gcc_dwarf_w10_mips64, gcc_dwarf_w20_mips64, LLDB_INVALID_REGNUM, gdb_w20_mips64), + DEFINE_MSA (w21, NULL, gcc_dwarf_w21_mips64, gcc_dwarf_w21_mips64, LLDB_INVALID_REGNUM, gdb_w21_mips64), + DEFINE_MSA (w22, NULL, gcc_dwarf_w22_mips64, gcc_dwarf_w22_mips64, LLDB_INVALID_REGNUM, gdb_w22_mips64), + DEFINE_MSA (w23, NULL, gcc_dwarf_w23_mips64, gcc_dwarf_w23_mips64, LLDB_INVALID_REGNUM, gdb_w23_mips64), + DEFINE_MSA (w24, NULL, gcc_dwarf_w24_mips64, gcc_dwarf_w24_mips64, LLDB_INVALID_REGNUM, gdb_w24_mips64), + DEFINE_MSA (w25, NULL, gcc_dwarf_w25_mips64, gcc_dwarf_w25_mips64, LLDB_INVALID_REGNUM, gdb_w25_mips64), + DEFINE_MSA (w26, NULL, gcc_dwarf_w26_mips64, gcc_dwarf_w26_mips64, LLDB_INVALID_REGNUM, gdb_w26_mips64), + DEFINE_MSA (w27, NULL, gcc_dwarf_w27_mips64, gcc_dwarf_w27_mips64, LLDB_INVALID_REGNUM, gdb_w27_mips64), + DEFINE_MSA (w28, NULL, gcc_dwarf_w28_mips64, gcc_dwarf_w28_mips64, LLDB_INVALID_REGNUM, gdb_w28_mips64), + DEFINE_MSA (w29, NULL, gcc_dwarf_w29_mips64, gcc_dwarf_w29_mips64, LLDB_INVALID_REGNUM, gdb_w29_mips64), + DEFINE_MSA (w30, NULL, gcc_dwarf_w30_mips64, gcc_dwarf_w30_mips64, LLDB_INVALID_REGNUM, gdb_w30_mips64), + DEFINE_MSA (w31, NULL, gcc_dwarf_w31_mips64, gcc_dwarf_w31_mips64, LLDB_INVALID_REGNUM, gdb_w31_mips64), + DEFINE_MSA_INFO (mcsr, NULL, gcc_dwarf_mcsr_mips64, gcc_dwarf_mcsr_mips64, LLDB_INVALID_REGNUM, gdb_mcsr_mips64), + DEFINE_MSA_INFO (mir, NULL, gcc_dwarf_mir_mips64, gcc_dwarf_mir_mips64, LLDB_INVALID_REGNUM, gdb_mir_mips64), + DEFINE_MSA_INFO (fcsr, NULL, gcc_dwarf_fcsr_mips64, gcc_dwarf_fcsr_mips64, LLDB_INVALID_REGNUM, gdb_fcsr_mips64), + DEFINE_MSA_INFO (fir, NULL, gcc_dwarf_fir_mips64, gcc_dwarf_fir_mips64, LLDB_INVALID_REGNUM, gdb_fir_mips64), + DEFINE_MSA_INFO (config5, NULL, gcc_dwarf_config5_mips64, gcc_dwarf_config5_mips64, LLDB_INVALID_REGNUM, gdb_config5_mips64) +#endif }; + static_assert((sizeof(g_register_infos_mips64) / sizeof(g_register_infos_mips64[0])) == k_num_registers_mips64, "g_register_infos_mips64 has wrong number of register infos"); #undef DEFINE_GPR +#undef DEFINE_GPR_INFO #undef DEFINE_FPR +#undef DEFINE_MSA +#undef DEFINE_MSA_INFO #undef GPR_OFFSET #undef FPR_OFFSET +#undef MSA_OFFSET #endif // DECLARE_REGISTER_INFOS_MIPS64_STRUCT diff --git a/source/Plugins/Process/Utility/lldb-mips-freebsd-register-enums.h b/source/Plugins/Process/Utility/lldb-mips-freebsd-register-enums.h new file mode 100644 index 000000000000..69dc9efac32b --- /dev/null +++ b/source/Plugins/Process/Utility/lldb-mips-freebsd-register-enums.h @@ -0,0 +1,70 @@ +//===-- lldb-mips-frebsd-register-enums.h -------------------------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#ifndef lldb_mips_freebsd_register_enums_h +#define lldb_mips_freebsd_register_enums_h + +namespace lldb_private +{ + // LLDB register codes (e.g. RegisterKind == eRegisterKindLLDB) + + //--------------------------------------------------------------------------- + // Internal codes for all mips registers. + //--------------------------------------------------------------------------- + enum + { + k_first_gpr_mips64, + gpr_zero_mips64 = k_first_gpr_mips64, + gpr_r1_mips64, + gpr_r2_mips64, + gpr_r3_mips64, + gpr_r4_mips64, + gpr_r5_mips64, + gpr_r6_mips64, + gpr_r7_mips64, + gpr_r8_mips64, + gpr_r9_mips64, + gpr_r10_mips64, + gpr_r11_mips64, + gpr_r12_mips64, + gpr_r13_mips64, + gpr_r14_mips64, + gpr_r15_mips64, + gpr_r16_mips64, + gpr_r17_mips64, + gpr_r18_mips64, + gpr_r19_mips64, + gpr_r20_mips64, + gpr_r21_mips64, + gpr_r22_mips64, + gpr_r23_mips64, + gpr_r24_mips64, + gpr_r25_mips64, + gpr_r26_mips64, + gpr_r27_mips64, + gpr_gp_mips64, + gpr_sp_mips64, + gpr_r30_mips64, + gpr_ra_mips64, + gpr_sr_mips64, + gpr_mullo_mips64, + gpr_mulhi_mips64, + gpr_badvaddr_mips64, + gpr_cause_mips64, + gpr_pc_mips64, + gpr_ic_mips64, + gpr_dummy_mips64, + k_last_gpr_mips64 = gpr_dummy_mips64, + + k_num_registers_mips64, + + k_num_gpr_registers_mips64 = k_last_gpr_mips64 - k_first_gpr_mips64 + 1 + }; +} +#endif // #ifndef lldb_mips_freebsd_register_enums_h diff --git a/source/Plugins/Process/Utility/lldb-mips64-register-enums.h b/source/Plugins/Process/Utility/lldb-mips-linux-register-enums.h index e8c93a6ec521..6c00025edfdf 100644 --- a/source/Plugins/Process/Utility/lldb-mips64-register-enums.h +++ b/source/Plugins/Process/Utility/lldb-mips-linux-register-enums.h @@ -1,4 +1,4 @@ -//===-- lldb-mips64-register-enums.h -------------------------------*- C++ -*-===// +//===-- lldb-mips-linux-register-enums.h -------------------------------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -7,8 +7,8 @@ // //===----------------------------------------------------------------------===// -#ifndef lldb_mips64_register_enums_h -#define lldb_mips64_register_enums_h +#ifndef lldb_mips_linux_register_enums_h +#define lldb_mips_linux_register_enums_h namespace lldb_private { @@ -52,14 +52,15 @@ namespace lldb_private gpr_sp_mips, gpr_r30_mips, gpr_ra_mips, + gpr_sr_mips, gpr_mullo_mips, gpr_mulhi_mips, - gpr_pc_mips, gpr_badvaddr_mips, - gpr_sr_mips, gpr_cause_mips, + gpr_pc_mips, + gpr_config5_mips, - k_last_gpr_mips = gpr_cause_mips, + k_last_gpr_mips = gpr_config5_mips, k_first_fpr_mips, fpr_f0_mips = k_first_fpr_mips, @@ -96,12 +97,55 @@ namespace lldb_private fpr_f31_mips, fpr_fcsr_mips, fpr_fir_mips, - k_last_fpr_mips = fpr_fir_mips, + fpr_config5_mips, + k_last_fpr_mips = fpr_config5_mips, + + k_first_msa_mips, + msa_w0_mips = k_first_msa_mips, + msa_w1_mips, + msa_w2_mips, + msa_w3_mips, + msa_w4_mips, + msa_w5_mips, + msa_w6_mips, + msa_w7_mips, + msa_w8_mips, + msa_w9_mips, + msa_w10_mips, + msa_w11_mips, + msa_w12_mips, + msa_w13_mips, + msa_w14_mips, + msa_w15_mips, + msa_w16_mips, + msa_w17_mips, + msa_w18_mips, + msa_w19_mips, + msa_w20_mips, + msa_w21_mips, + msa_w22_mips, + msa_w23_mips, + msa_w24_mips, + msa_w25_mips, + msa_w26_mips, + msa_w27_mips, + msa_w28_mips, + msa_w29_mips, + msa_w30_mips, + msa_w31_mips, + msa_fcsr_mips, + msa_fir_mips, + msa_mcsr_mips, + msa_mir_mips, + msa_config5_mips, + k_last_msa_mips = msa_config5_mips, k_num_registers_mips, + k_num_gpr_registers_mips = k_last_gpr_mips - k_first_gpr_mips + 1, k_num_fpr_registers_mips = k_last_fpr_mips - k_first_fpr_mips + 1, - k_num_user_registers_mips = k_num_gpr_registers_mips + k_num_fpr_registers_mips, + k_num_msa_registers_mips = k_last_msa_mips - k_first_msa_mips + 1, + k_num_user_registers_mips = k_num_gpr_registers_mips + k_num_fpr_registers_mips + k_num_msa_registers_mips }; //--------------------------------------------------------------------------- @@ -142,16 +186,14 @@ namespace lldb_private gpr_sp_mips64, gpr_r30_mips64, gpr_ra_mips64, + gpr_sr_mips64, gpr_mullo_mips64, gpr_mulhi_mips64, - gpr_pc_mips64, gpr_badvaddr_mips64, - gpr_sr_mips64, gpr_cause_mips64, - gpr_ic_mips64, - gpr_dummy_mips64, - - k_last_gpr_mips64 = gpr_dummy_mips64, + gpr_pc_mips64, + gpr_config5_mips64, + k_last_gpr_mips64 = gpr_config5_mips64, k_first_fpr_mips64, fpr_f0_mips64 = k_first_fpr_mips64, @@ -188,12 +230,56 @@ namespace lldb_private fpr_f31_mips64, fpr_fcsr_mips64, fpr_fir_mips64, - k_last_fpr_mips64 = fpr_fir_mips64, + fpr_config5_mips64, + k_last_fpr_mips64 = fpr_config5_mips64, + + k_first_msa_mips64, + msa_w0_mips64 = k_first_msa_mips64, + msa_w1_mips64, + msa_w2_mips64, + msa_w3_mips64, + msa_w4_mips64, + msa_w5_mips64, + msa_w6_mips64, + msa_w7_mips64, + msa_w8_mips64, + msa_w9_mips64, + msa_w10_mips64, + msa_w11_mips64, + msa_w12_mips64, + msa_w13_mips64, + msa_w14_mips64, + msa_w15_mips64, + msa_w16_mips64, + msa_w17_mips64, + msa_w18_mips64, + msa_w19_mips64, + msa_w20_mips64, + msa_w21_mips64, + msa_w22_mips64, + msa_w23_mips64, + msa_w24_mips64, + msa_w25_mips64, + msa_w26_mips64, + msa_w27_mips64, + msa_w28_mips64, + msa_w29_mips64, + msa_w30_mips64, + msa_w31_mips64, + msa_fcsr_mips64, + msa_fir_mips64, + msa_mcsr_mips64, + msa_mir_mips64, + msa_config5_mips64, + k_last_msa_mips64 = msa_config5_mips64, k_num_registers_mips64, + k_num_gpr_registers_mips64 = k_last_gpr_mips64 - k_first_gpr_mips64 + 1, k_num_fpr_registers_mips64 = k_last_fpr_mips64 - k_first_fpr_mips64 + 1, + k_num_msa_registers_mips64 = k_last_msa_mips64 - k_first_msa_mips64 + 1, + k_num_user_registers_mips64 = k_num_gpr_registers_mips64 + k_num_fpr_registers_mips64 + k_num_msa_registers_mips64 }; } -#endif // #ifndef fpr_mips64_register_enums_h +#endif // #ifndef lldb_mips_linux_register_enums_h diff --git a/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp b/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp index 2a253c5a99e8..b8c67c593b1f 100644 --- a/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp +++ b/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp @@ -1459,6 +1459,21 @@ GDBRemoteCommunicationClient::GetCurrentProcessID (bool allow_lazy) } } } + + // If we don't get a response for $qC, check if $qfThreadID gives us a result. + if (m_curr_pid == LLDB_INVALID_PROCESS_ID) + { + std::vector<lldb::tid_t> thread_ids; + bool sequence_mutex_unavailable; + size_t size; + size = GetCurrentThreadIDs (thread_ids, sequence_mutex_unavailable); + if (size && sequence_mutex_unavailable == false) + { + m_curr_pid = thread_ids.front(); + m_curr_pid_is_valid = eLazyBoolYes; + return m_curr_pid; + } + } } return LLDB_INVALID_PROCESS_ID; @@ -2472,26 +2487,45 @@ GDBRemoteCommunicationClient::GetWatchpointSupportInfo (uint32_t &num) } lldb_private::Error -GDBRemoteCommunicationClient::GetWatchpointSupportInfo (uint32_t &num, bool& after) +GDBRemoteCommunicationClient::GetWatchpointSupportInfo (uint32_t &num, bool& after, const ArchSpec &arch) { Error error(GetWatchpointSupportInfo(num)); if (error.Success()) - error = GetWatchpointsTriggerAfterInstruction(after); + error = GetWatchpointsTriggerAfterInstruction(after, arch); return error; } lldb_private::Error -GDBRemoteCommunicationClient::GetWatchpointsTriggerAfterInstruction (bool &after) +GDBRemoteCommunicationClient::GetWatchpointsTriggerAfterInstruction (bool &after, const ArchSpec &arch) { Error error; + llvm::Triple::ArchType atype = arch.GetMachine(); // we assume watchpoints will happen after running the relevant opcode // and we only want to override this behavior if we have explicitly // received a qHostInfo telling us otherwise if (m_qHostInfo_is_valid != eLazyBoolYes) - after = true; + { + // On targets like MIPS, watchpoint exceptions are always generated + // before the instruction is executed. The connected target may not + // support qHostInfo or qWatchpointSupportInfo packets. + if (atype == llvm::Triple::mips || atype == llvm::Triple::mipsel + || atype == llvm::Triple::mips64 || atype == llvm::Triple::mips64el) + after = false; + else + after = true; + } else + { + // For MIPS, set m_watchpoints_trigger_after_instruction to eLazyBoolNo + // if it is not calculated before. + if (m_watchpoints_trigger_after_instruction == eLazyBoolCalculate && + (atype == llvm::Triple::mips || atype == llvm::Triple::mipsel + || atype == llvm::Triple::mips64 || atype == llvm::Triple::mips64el)) + m_watchpoints_trigger_after_instruction = eLazyBoolNo; + after = (m_watchpoints_trigger_after_instruction != eLazyBoolNo); + } return error; } diff --git a/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.h b/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.h index deb41b066b45..b08ff0647797 100644 --- a/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.h +++ b/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.h @@ -287,10 +287,10 @@ public: GetWatchpointSupportInfo (uint32_t &num); Error - GetWatchpointSupportInfo (uint32_t &num, bool& after); + GetWatchpointSupportInfo (uint32_t &num, bool& after, const ArchSpec &arch); Error - GetWatchpointsTriggerAfterInstruction (bool &after); + GetWatchpointsTriggerAfterInstruction (bool &after, const ArchSpec &arch); const ArchSpec & GetHostArchitecture (); diff --git a/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp b/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp index 0bcc8ca4e5e3..1e150b1dda9f 100644 --- a/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp +++ b/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp @@ -371,7 +371,7 @@ ProcessGDBRemote::ProcessGDBRemote(Target& target, Listener &listener) : m_flags (0), m_gdb_comm (), m_debugserver_pid (LLDB_INVALID_PROCESS_ID), - m_last_stop_packet_mutex (Mutex::eMutexTypeNormal), + m_last_stop_packet_mutex (Mutex::eMutexTypeRecursive), m_register_info (), m_async_broadcaster (NULL, "lldb.process.gdb-remote.async-broadcaster"), m_async_thread_state_mutex(Mutex::eMutexTypeRecursive), @@ -822,7 +822,13 @@ ProcessGDBRemote::DoConnectRemote (Stream *strm, const char *remote_url) log->Printf ("ProcessGDBRemote::%s pid %" PRIu64 ": normalized target architecture triple: %s", __FUNCTION__, GetID (), GetTarget ().GetArchitecture ().GetTriple ().getTriple ().c_str ()); if (error.Success()) - SetUnixSignals(std::make_shared<GDBRemoteSignals>(GetTarget().GetPlatform()->GetUnixSignals())); + { + PlatformSP platform_sp = GetTarget().GetPlatform(); + if (platform_sp && platform_sp->IsConnected()) + SetUnixSignals(platform_sp->GetUnixSignals()); + else + SetUnixSignals(UnixSignals::Create(GetTarget().GetArchitecture())); + } return error; } @@ -1984,6 +1990,7 @@ ProcessGDBRemote::SetThreadStopInfo (lldb::tid_t tid, StringExtractor desc_extractor(description.c_str()); addr_t wp_addr = desc_extractor.GetU64(LLDB_INVALID_ADDRESS); uint32_t wp_index = desc_extractor.GetU32(LLDB_INVALID_INDEX32); + addr_t wp_hit_addr = desc_extractor.GetU64(LLDB_INVALID_ADDRESS); watch_id_t watch_id = LLDB_INVALID_WATCH_ID; if (wp_addr != LLDB_INVALID_ADDRESS) { @@ -1999,7 +2006,7 @@ ProcessGDBRemote::SetThreadStopInfo (lldb::tid_t tid, Log *log (ProcessGDBRemoteLog::GetLogIfAllCategoriesSet (GDBR_LOG_WATCHPOINTS)); if (log) log->Printf ("failed to find watchpoint"); } - thread_sp->SetStopInfo (StopInfo::CreateStopReasonWithWatchpointID (*thread_sp, watch_id)); + thread_sp->SetStopInfo (StopInfo::CreateStopReasonWithWatchpointID (*thread_sp, watch_id, wp_hit_addr)); handled = true; } else if (reason.compare("exception") == 0) @@ -2433,6 +2440,21 @@ ProcessGDBRemote::SetThreadStopInfo (StringExtractor& stop_packet) } } } + else if (key.compare("watch") == 0 || key.compare("rwatch") == 0 || key.compare("awatch") == 0) + { + // Support standard GDB remote stop reply packet 'TAAwatch:addr' + lldb::addr_t wp_addr = StringConvert::ToUInt64 (value.c_str(), LLDB_INVALID_ADDRESS, 16); + WatchpointSP wp_sp = GetTarget().GetWatchpointList().FindByAddress(wp_addr); + uint32_t wp_index = LLDB_INVALID_INDEX32; + + if (wp_sp) + wp_index = wp_sp->GetHardwareIndex(); + + reason = "watchpoint"; + StreamString ostr; + ostr.Printf("%" PRIu64 " %" PRIu32, wp_addr, wp_index); + description = ostr.GetString().c_str(); + } else if (key.size() == 2 && ::isxdigit(key[0]) && ::isxdigit(key[1])) { uint32_t reg = StringConvert::ToUInt32 (key.c_str(), UINT32_MAX, 16); @@ -2441,6 +2463,18 @@ ProcessGDBRemote::SetThreadStopInfo (StringExtractor& stop_packet) } } + if (tid == LLDB_INVALID_THREAD_ID) + { + // A thread id may be invalid if the response is old style 'S' packet which does not provide the + // thread information. So update the thread list and choose the first one. + UpdateThreadIDList (); + + if (!m_thread_ids.empty ()) + { + tid = m_thread_ids.front (); + } + } + ThreadSP thread_sp = SetThreadStopInfo (tid, expedited_register_map, signo, @@ -2455,19 +2489,6 @@ ProcessGDBRemote::SetThreadStopInfo (StringExtractor& stop_packet) queue_kind, queue_serial); - // If the response is old style 'S' packet which does not provide us with thread information - // then update the thread list and choose the first one. - if (!thread_sp) - { - UpdateThreadIDList (); - - if (!m_thread_ids.empty ()) - { - Mutex::Locker locker (m_thread_list_real.GetMutex ()); - thread_sp = m_thread_list_real.FindThreadByProtocolID (m_thread_ids.front (), false); - } - } - return eStateStopped; } break; @@ -3006,7 +3027,7 @@ ProcessGDBRemote::GetWatchpointSupportInfo (uint32_t &num) Error ProcessGDBRemote::GetWatchpointSupportInfo (uint32_t &num, bool& after) { - Error error (m_gdb_comm.GetWatchpointSupportInfo (num, after)); + Error error (m_gdb_comm.GetWatchpointSupportInfo (num, after, GetTarget().GetArchitecture())); return error; } diff --git a/source/Target/StopInfo.cpp b/source/Target/StopInfo.cpp index 4f6ef7a92949..9bbb00dbf0da 100644 --- a/source/Target/StopInfo.cpp +++ b/source/Target/StopInfo.cpp @@ -615,10 +615,11 @@ public: Watchpoint *watchpoint; }; - StopInfoWatchpoint (Thread &thread, break_id_t watch_id) : + StopInfoWatchpoint (Thread &thread, break_id_t watch_id, lldb::addr_t watch_hit_addr) : StopInfo(thread, watch_id), m_should_stop(false), - m_should_stop_is_valid(false) + m_should_stop_is_valid(false), + m_watch_hit_addr(watch_hit_addr) { } @@ -745,6 +746,21 @@ protected: } } + /* + * MIPS: Last 3bits of the watchpoint address are masked by the kernel. For example: + * 'n' is at 0x120010d00 and 'm' is 0x120010d04. When a watchpoint is set at 'm', then + * watch exception is generated even when 'n' is read/written. To handle this case, + * server emulates the instruction at PC and finds the base address of the load/store + * instruction and appends it in the description of the stop-info packet. If watchpoint + * is not set on this address by user then this do not stop. + */ + if (m_watch_hit_addr != LLDB_INVALID_ADDRESS) + { + WatchpointSP wp_hit_sp = thread_sp->CalculateTarget()->GetWatchpointList().FindByAddress(m_watch_hit_addr); + if (!wp_hit_sp) + m_should_stop = false; + } + if (m_should_stop && wp_sp->GetConditionText() != NULL) { // We need to make sure the user sees any parse errors in their condition, so we'll hook the @@ -857,6 +873,7 @@ protected: private: bool m_should_stop; bool m_should_stop_is_valid; + lldb::addr_t m_watch_hit_addr; }; @@ -1154,9 +1171,9 @@ StopInfo::CreateStopReasonWithBreakpointSiteID (Thread &thread, break_id_t break } StopInfoSP -StopInfo::CreateStopReasonWithWatchpointID (Thread &thread, break_id_t watch_id) +StopInfo::CreateStopReasonWithWatchpointID (Thread &thread, break_id_t watch_id, lldb::addr_t watch_hit_addr) { - return StopInfoSP (new StopInfoWatchpoint (thread, watch_id)); + return StopInfoSP (new StopInfoWatchpoint (thread, watch_id, watch_hit_addr)); } StopInfoSP diff --git a/tools/lldb-mi/MICmdCmdData.cpp b/tools/lldb-mi/MICmdCmdData.cpp index 0b950d5a4c4b..21036f865d9e 100644 --- a/tools/lldb-mi/MICmdCmdData.cpp +++ b/tools/lldb-mi/MICmdCmdData.cpp @@ -1789,7 +1789,7 @@ CMICmdCmdDataInfoLine::Acknowledge(void) // ^ -- line const size_t nLineStartPos = nFileEndPos + 1; const size_t nLineEndPos = rLine.find(':', nLineStartPos); - const size_t nLineLen = nLineEndPos != std::string::npos ? nLineEndPos - nLineStartPos - 1 + const size_t nLineLen = nLineEndPos != std::string::npos ? nLineEndPos - nLineStartPos : std::string::npos; const CMIUtilString strLine(rLine.substr(nLineStartPos, nLineLen).c_str()); const CMICmnMIValueConst miValueConst4(strLine); |