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authorNavdeep Parhar <np@FreeBSD.org>2021-02-19 22:18:08 +0000
committerNavdeep Parhar <np@FreeBSD.org>2021-02-19 22:23:58 +0000
commit0460a45062dfeb98b1f1f7a3a7b9268662b61545 (patch)
tree48b99a85f839829a38d279131290c51aa4de0426
parentc91dda5ad923f24ef2e538b8dc180fa98598b4db (diff)
downloadsrc-0460a45062dfeb98b1f1f7a3a7b9268662b61545.tar.gz
src-0460a45062dfeb98b1f1f7a3a7b9268662b61545.zip
cxgbe(4): Use the correct filter width for T5+.
T5 and above have extra bits for the optional filter fields. This is a correctness issue and not just a waste because a filter mode valid on a T4 (36b) may not be valid on a T5+ (40b). MFC after: 2 weeks Sponsored by: Chelsio Communications
-rw-r--r--sys/dev/cxgbe/common/common.h1
-rw-r--r--sys/dev/cxgbe/common/t4_hw.c5
-rw-r--r--sys/dev/cxgbe/common/t4_hw.h1
3 files changed, 6 insertions, 1 deletions
diff --git a/sys/dev/cxgbe/common/common.h b/sys/dev/cxgbe/common/common.h
index 53be2fa2588a..e04101c9adc5 100644
--- a/sys/dev/cxgbe/common/common.h
+++ b/sys/dev/cxgbe/common/common.h
@@ -309,6 +309,7 @@ struct chip_params {
u8 cng_ch_bits_log; /* congestion channel map bits width */
u8 nsched_cls;
u8 cim_num_obq;
+ u8 filter_opt_len;
u16 mps_rplc_size;
u16 vfcount;
u32 sge_fl_db;
diff --git a/sys/dev/cxgbe/common/t4_hw.c b/sys/dev/cxgbe/common/t4_hw.c
index 8b22f2e4f5ba..b3934381ba7a 100644
--- a/sys/dev/cxgbe/common/t4_hw.c
+++ b/sys/dev/cxgbe/common/t4_hw.c
@@ -9241,6 +9241,7 @@ const struct chip_params *t4_get_chip_params(int chipid)
.cng_ch_bits_log = 2,
.nsched_cls = 15,
.cim_num_obq = CIM_NUM_OBQ,
+ .filter_opt_len = FILTER_OPT_LEN,
.mps_rplc_size = 128,
.vfcount = 128,
.sge_fl_db = F_DBPRIO,
@@ -9254,6 +9255,7 @@ const struct chip_params *t4_get_chip_params(int chipid)
.cng_ch_bits_log = 2,
.nsched_cls = 16,
.cim_num_obq = CIM_NUM_OBQ_T5,
+ .filter_opt_len = T5_FILTER_OPT_LEN,
.mps_rplc_size = 128,
.vfcount = 128,
.sge_fl_db = F_DBPRIO | F_DBTYPE,
@@ -9267,6 +9269,7 @@ const struct chip_params *t4_get_chip_params(int chipid)
.cng_ch_bits_log = 3,
.nsched_cls = 16,
.cim_num_obq = CIM_NUM_OBQ_T5,
+ .filter_opt_len = T5_FILTER_OPT_LEN,
.mps_rplc_size = 256,
.vfcount = 256,
.sge_fl_db = 0,
@@ -10863,7 +10866,7 @@ int t4_set_filter_cfg(struct adapter *adap, int mode, int mask, int vnic_mode)
int i, nbits, rc;
uint32_t param, val;
uint16_t fmode, fmask;
- const int maxbits = FILTER_OPT_LEN;
+ const int maxbits = adap->chip_params->filter_opt_len;
if (mode != -1 || mask != -1) {
if (mode != -1) {
diff --git a/sys/dev/cxgbe/common/t4_hw.h b/sys/dev/cxgbe/common/t4_hw.h
index 36ce6271dad6..c0625b752962 100644
--- a/sys/dev/cxgbe/common/t4_hw.h
+++ b/sys/dev/cxgbe/common/t4_hw.h
@@ -55,6 +55,7 @@ enum {
NTRACE = 4, /* # of tracing filters */
TRACE_LEN = 112, /* length of trace data and mask */
FILTER_OPT_LEN = 36, /* filter tuple width of optional components */
+ T5_FILTER_OPT_LEN = 40,
NWOL_PAT = 8, /* # of WoL patterns */
WOL_PAT_LEN = 128, /* length of WoL patterns */
UDBS_SEG_SIZE = 128, /* Segment size of BAR2 doorbells */