arm64/vmm: Fix vgic_v3 dropping EOI for disabled IRQs

Now that IRQs can properly be disabled by GICD_ICENABLERn, an EOI for a
disabled IRQ ends up being lost, since we don't assign it to a list
register and don't enable maintenance interrupts for such cases. As a
result, we keep the IRQ active, which stops it from ever being delivered
again (which would be true even if we supported the active and pending
state). Keep disabled but active IRQs around in list registers so we can
see the EOI having taken place in a future sync (noting that since we
already don't create list registers in active and pending state there
are no concerns with causing a disabled IRQ to be delivered).

Fixes:		47e073941f4e ("Import the kernel parts of bhyve/arm64")
MFC after:	1 week

1 files changed, 7 insertions, 1 deletions

diff --git a/sys/arm64/vmm/io/vgic_v3.c b/sys/arm64/vmm/io/vgic_v3.c
index ee96cc975755..09d1448c1803 100644
--- a/sys/arm64/vmm/io/vgic_v3.c
+++ b/sys/arm64/vmm/io/vgic_v3.c
@@ -2136,7 +2136,13 @@ vgic_v3_flush_hwstate(device_t dev, struct hypctx *hypctx)
 		if (i == hypctx->vgic_v3.ich_lr_num)
 			break;
 
-		if (!irq->enabled)
+		/*
+		 * NB: Disabled active interrupts are kept around for EOI to
+		 * make them inactive, since we don't enable maintenace
+		 * interrupts to intercept EOIs for interrupts not in a list
+		 * register.
+		 */
+		if (!irq->enabled && !irq->active)
 			continue;
 
 		hypctx_write_sys_reg(hypctx, HOST_ICH_LR_EL2(i),