23 files changed, 0 insertions, 2729 deletions

diff --git a/sys/contrib/device-tree/include/dt-bindings/clock/cv181x-clock.h b/sys/contrib/device-tree/include/dt-bindings/clock/cv181x-clock.h
deleted file mode 100644
index ed76e4d8ef95..000000000000
--- a/sys/contrib/device-tree/include/dt-bindings/clock/cv181x-clock.h
+++ /dev/null
@@ -1,175 +0,0 @@
-/*
- * Copyright (C) Cvitek Co., Ltd. 2019-2021. All rights reserved.
- *
- * File Name: cv181x-clock.h
- * Description:
- */
-
-#ifndef __DT_BINDINGS_CLK_CV181X_H__
-#define __DT_BINDINGS_CLK_CV181X_H__
-
-#define CV181X_CLK_MPLL				0
-#define CV181X_CLK_TPLL				1
-#define CV181X_CLK_FPLL				2
-#define CV181X_CLK_MIPIMPLL			3
-#define CV181X_CLK_A0PLL				4
-#define CV181X_CLK_DISPPLL			5
-#define CV181X_CLK_CAM0PLL			6
-#define CV181X_CLK_CAM1PLL			7
-
-#define CV181X_CLK_MIPIMPLL_D3			8
-#define CV181X_CLK_CAM0PLL_D2			9
-#define CV181X_CLK_CAM0PLL_D3			10
-
-#define CV181X_CLK_A53				11
-#define CV181X_CLK_CPU_AXI0			12
-#define CV181X_CLK_CPU_GIC			13
-#define CV181X_CLK_XTAL_A53			14
-#define CV181X_CLK_TPU				15
-#define CV181X_CLK_TPU_FAB			16
-#define CV181X_CLK_AHB_ROM			17
-#define CV181X_CLK_DDR_AXI_REG			18
-#define CV181X_CLK_RTC_25M			19
-#define CV181X_CLK_TEMPSEN			20
-#define CV181X_CLK_SARADC				21
-#define CV181X_CLK_EFUSE				22
-#define CV181X_CLK_APB_EFUSE			23
-#define CV181X_CLK_DEBUG				24
-#define CV181X_CLK_XTAL_MISC			25
-#define CV181X_CLK_AXI4_EMMC			26
-#define CV181X_CLK_EMMC				27
-#define CV181X_CLK_100K_EMMC			28
-#define CV181X_CLK_AXI4_SD0			29
-#define CV181X_CLK_SD0				30
-#define CV181X_CLK_100K_SD0			31
-#define CV181X_CLK_AXI4_SD1			32
-#define CV181X_CLK_SD1				33
-#define CV181X_CLK_100K_SD1			34
-#define CV181X_CLK_SPI_NAND			35
-#define CV181X_CLK_500M_ETH0			36
-#define CV181X_CLK_AXI4_ETH0			37
-#define CV181X_CLK_500M_ETH1			38
-#define CV181X_CLK_AXI4_ETH1			39
-#define CV181X_CLK_APB_GPIO			40
-#define CV181X_CLK_APB_GPIO_INTR			41
-#define CV181X_CLK_GPIO_DB			42
-#define CV181X_CLK_AHB_SF				43
-#define CV181X_CLK_SDMA_AXI			44
-#define CV181X_CLK_SDMA_AUD0			45
-#define CV181X_CLK_SDMA_AUD1			46
-#define CV181X_CLK_SDMA_AUD2			47
-#define CV181X_CLK_SDMA_AUD3			48
-#define CV181X_CLK_APB_I2C			49
-#define CV181X_CLK_APB_WDT			50
-#define CV181X_CLK_PWM				51
-#define CV181X_CLK_APB_SPI0			52
-#define CV181X_CLK_APB_SPI1			53
-#define CV181X_CLK_APB_SPI2			54
-#define CV181X_CLK_APB_SPI3			55
-#define CV181X_CLK_CAM0_200			56
-#define CV181X_CLK_UART0				57
-#define CV181X_CLK_APB_UART0			58
-#define CV181X_CLK_UART1				59
-#define CV181X_CLK_APB_UART1			60
-#define CV181X_CLK_UART2				61
-#define CV181X_CLK_APB_UART2			62
-#define CV181X_CLK_UART3				63
-#define CV181X_CLK_APB_UART3			64
-#define CV181X_CLK_UART4				65
-#define CV181X_CLK_APB_UART4			66
-#define CV181X_CLK_APB_I2S0			67
-#define CV181X_CLK_APB_I2S1			68
-#define CV181X_CLK_APB_I2S2			69
-#define CV181X_CLK_APB_I2S3			70
-#define CV181X_CLK_AXI4_USB			71
-#define CV181X_CLK_APB_USB			72
-#define CV181X_CLK_125M_USB			73
-#define CV181X_CLK_33K_USB			74
-#define CV181X_CLK_12M_USB			75
-#define CV181X_CLK_AXI4				76
-#define CV181X_CLK_AXI6				77
-#define CV181X_CLK_DSI_ESC			78
-#define CV181X_CLK_AXI_VIP			79
-#define CV181X_CLK_SRC_VIP_SYS_0			80
-#define CV181X_CLK_SRC_VIP_SYS_1			81
-#define CV181X_CLK_DISP_SRC_VIP			82
-#define CV181X_CLK_AXI_VIDEO_CODEC		83
-#define CV181X_CLK_VC_SRC0			84
-#define CV181X_CLK_H264C				85
-#define CV181X_CLK_H265C				86
-#define CV181X_CLK_JPEG				87
-#define CV181X_CLK_APB_JPEG			88
-#define CV181X_CLK_APB_H264C			89
-#define CV181X_CLK_APB_H265C			90
-#define CV181X_CLK_CAM0				91
-#define CV181X_CLK_CAM1				92
-#define CV181X_CLK_CSI_MAC0_VIP			93
-#define CV181X_CLK_CSI_MAC1_VIP			94
-#define CV181X_CLK_ISP_TOP_VIP			95
-#define CV181X_CLK_IMG_D_VIP			96
-#define CV181X_CLK_IMG_V_VIP			97
-#define CV181X_CLK_SC_TOP_VIP			98
-#define CV181X_CLK_SC_D_VIP			99
-#define CV181X_CLK_SC_V1_VIP			100
-#define CV181X_CLK_SC_V2_VIP			101
-#define CV181X_CLK_SC_V3_VIP			102
-#define CV181X_CLK_DWA_VIP			103
-#define CV181X_CLK_BT_VIP				104
-#define CV181X_CLK_DISP_VIP			105
-#define CV181X_CLK_DSI_MAC_VIP			106
-#define CV181X_CLK_LVDS0_VIP			107
-#define CV181X_CLK_LVDS1_VIP			108
-#define CV181X_CLK_CSI0_RX_VIP			109
-#define CV181X_CLK_CSI1_RX_VIP			110
-#define CV181X_CLK_PAD_VI_VIP			111
-#define CV181X_CLK_1M				112
-#define CV181X_CLK_SPI				113
-#define CV181X_CLK_I2C				114
-#define CV181X_CLK_PM				115
-#define CV181X_CLK_TIMER0				116
-#define CV181X_CLK_TIMER1				117
-#define CV181X_CLK_TIMER2				118
-#define CV181X_CLK_TIMER3				119
-#define CV181X_CLK_TIMER4				120
-#define CV181X_CLK_TIMER5				121
-#define CV181X_CLK_TIMER6				122
-#define CV181X_CLK_TIMER7				123
-#define CV181X_CLK_APB_I2C0			124
-#define CV181X_CLK_APB_I2C1			125
-#define CV181X_CLK_APB_I2C2			126
-#define CV181X_CLK_APB_I2C3			127
-#define CV181X_CLK_APB_I2C4			128
-#define CV181X_CLK_WGN				129
-#define CV181X_CLK_WGN0				130
-#define CV181X_CLK_WGN1				131
-#define CV181X_CLK_WGN2				132
-#define CV181X_CLK_KEYSCAN			133
-#define CV181X_CLK_AHB_SF1			134
-#define CV181X_CLK_VC_SRC1			135
-#define CV181X_CLK_SRC_VIP_SYS_2			136
-#define CV181X_CLK_PAD_VI1_VIP			137
-#define CV181X_CLK_CFG_REG_VIP			138
-#define CV181X_CLK_CFG_REG_VC			139
-#define CV181X_CLK_AUDSRC				140
-#define CV181X_CLK_APB_AUDSRC			141
-#define CV181X_CLK_VC_SRC2			142
-#define CV181X_CLK_PWM_SRC			143
-#define CV181X_CLK_AP_DEBUG			144
-#define CV181X_CLK_SRC_RTC_SYS_0			145
-#define CV181X_CLK_PAD_VI2_VIP			146
-#define CV181X_CLK_CSI_BE_VIP			147
-#define CV181X_CLK_VIP_IP0			148
-#define CV181X_CLK_VIP_IP1			149
-#define CV181X_CLK_VIP_IP2			150
-#define CV181X_CLK_VIP_IP3			151
-#define CV181X_CLK_C906_0				152
-#define CV181X_CLK_C906_1				153
-#define CV181X_CLK_SRC_VIP_SYS_3			154
-#define CV181X_CLK_SRC_VIP_SYS_4			155
-#define CV181X_CLK_IVE_VIP			156
-#define CV181X_CLK_RAW_VIP			157
-#define CV181X_CLK_OSDC_VIP			158
-#define CV181X_CLK_CSI_MAC2_VIP			159
-#define CV181X_CLK_CAM0_VIP			160
-
-#endif /* __DT_BINDINGS_CLK_CV181X_H__ */
diff --git a/sys/contrib/device-tree/include/dt-bindings/dma/cv181x-dmamap.h b/sys/contrib/device-tree/include/dt-bindings/dma/cv181x-dmamap.h
deleted file mode 100644
index 84a4c3664ee1..000000000000
--- a/sys/contrib/device-tree/include/dt-bindings/dma/cv181x-dmamap.h
+++ /dev/null
@@ -1,48 +0,0 @@
-#ifndef __DT_BINDINGS_CV181X_DMAMAP_H__
-#define __DT_BINDINGS_CV181X_DMAMAP_H__
-
-#define CVI_I2S0_RX     0
-#define CVI_I2S0_TX     1
-#define CVI_I2S1_RX     2
-#define CVI_I2S1_TX     3
-#define CVI_I2S2_RX     4
-#define CVI_I2S2_TX     5
-#define CVI_I2S3_RX     6
-#define CVI_I2S3_TX     7
-#define CVI_UART0_RX    8
-#define CVI_UART0_TX    9
-#define CVI_UART1_RX    10
-#define CVI_UART1_TX    11
-#define CVI_UART2_RX    12
-#define CVI_UART2_TX    13
-#define CVI_UART3_RX    14
-#define CVI_UART3_TX    15
-#define CVI_SPI0_RX     16
-#define CVI_SPI0_TX     17
-#define CVI_SPI1_RX     18
-#define CVI_SPI1_TX     19
-#define CVI_SPI2_RX     20
-#define CVI_SPI2_TX     21
-#define CVI_SPI3_RX     22
-#define CVI_SPI3_TX     23
-#define CVI_I2C0_RX     24
-#define CVI_I2C0_TX     25
-#define CVI_I2C1_RX     26
-#define CVI_I2C1_TX     27
-#define CVI_I2C2_RX     28
-#define CVI_I2C2_TX     29
-#define CVI_I2C3_RX     30
-#define CVI_I2C3_TX     31
-#define CVI_I2C4_RX     32
-#define CVI_I2C4_TX     33
-#define CVI_TDM0_RX     34
-#define CVI_TDM0_TX     35
-#define CVI_TDM1_RX     36
-#define CVI_AUDSRC      37
-#define CVI_SPI_NAND    38
-#define CVI_SPI_NOR     39
-#define CVI_UART4_RX    40
-#define CVI_UART4_TX    41
-#define CVI_SPI_NOR1    42
-
-#endif
diff --git a/sys/contrib/device-tree/include/dt-bindings/reset/cv181x-resets.h b/sys/contrib/device-tree/include/dt-bindings/reset/cv181x-resets.h
deleted file mode 100644
index e10d33b35446..000000000000
--- a/sys/contrib/device-tree/include/dt-bindings/reset/cv181x-resets.h
+++ /dev/null
@@ -1,172 +0,0 @@
-/*
- * Copyright (C) Cvitek Co., Ltd. 2019-2020. All rights reserved.
- *
- * File Name: cvi_template.h
- * Description:
- */
-
-#ifndef __DT_BINDINGS_RST_CV181X_H__
-#define __DT_BINDINGS_RST_CV181X_H__
-
-#define RST_MAINRST_AP	0
-#define RST_SECONDRST_AP	1
-#define RST_DDR	2
-#define RST_H264C	3
-#define RST_JPEG	4
-#define RST_H265C	5
-#define RST_VIPSYS	6
-#define RST_TDMA	7
-#define RST_TPU	8
-#define RST_TPUSYS	9
-#define RST_TSM	10
-#define RST_USB	11
-#define RST_ETH0	12
-#define RST_ETH1	13
-#define RST_NAND	14
-#define RST_EMMC	15
-#define RST_SD0	16
-#define RST_SD1	17
-#define RST_SDMA	18
-#define RST_I2S0	19
-#define RST_I2S1	20
-#define RST_I2S2	21
-#define RST_I2S3	22
-#define RST_UART0	23
-#define RST_UART1	24
-#define RST_UART2	25
-#define RST_UART3	26
-#define RST_I2C0	27
-#define RST_I2C1	28
-#define RST_I2C2	29
-#define RST_I2C3	30
-#define RST_I2C4	31
-#define RST_PWM0	32
-#define RST_PWM1	33
-#define RST_PWM2	34
-#define RST_PWM3	35
-#define RST_PWM4	36
-#define RST_PWM5	37
-#define RST_PWM6	38
-#define RST_PWM7	39
-#define RST_SPI0	40
-#define RST_SPI1	41
-#define RST_SPI2	42
-#define RST_SPI3	43
-#define RST_GPIO0	44
-#define RST_GPIO1	45
-#define RST_GPIO2	46
-#define RST_EFUSE	47
-#define RST_WDT	48
-#define RST_AHBRST_ROM	49
-#define RST_SPIC	50
-#define RST_TEMPSEN	51
-#define RST_SARADC	52
-#define RST_PCIERST_CDMA	53
-#define RST_PCIERST_SMMU	54
-#define RST_PCIERST_PCIE	55
-#define RST_PCIERST_FABS	56
-#define RST_PCIERST_IRQ	57
-#define RST_COMBORST_PHY0	58
-#define RST_COMBORST_PHY1	59
-#define RST_USB1	60
-#define RST_SPIRST_NAND	61
-#define RST_SE	62
-#define RST_RTCRST_SWRST_ONLY	63
-#define RST_CPUCORE0	64
-#define RST_CPUCORE1	65
-#define RST_CPUCORE2	66
-#define RST_CPUCORE3	67
-#define RST_DSIPHY	68
-#define RST_DSIPHYRST_APB	69
-#define RST_CSIPHY0	70
-#define RST_CSIPHY0RST_APB	71
-#define RST_CSIPHY1	72
-#define RST_CSIPHY1RST_APB	73
-#define RST_UART4	74
-#define RST_GPIO3	75
-#define RST_SYSTEM	76
-#define RST_TIMER	77
-#define RST_TIMER0	78
-#define RST_TIMER1	79
-#define RST_TIMER2	80
-#define RST_TIMER3	81
-#define RST_TIMER4	82
-#define RST_TIMER5	83
-#define RST_TIMER6	84
-#define RST_TIMER7	85
-#define RST_WGN0	86
-#define RST_WGN1	87
-#define RST_WGN2	88
-#define RST_KEYSCAN	89
-#define RST_SPIC1	90
-#define RST_AUDDAC	91
-#define RST_AUDDACRST_APB	92
-#define RST_AUDADC	93
-#define RST_AUDADCRST_APB	94
-#define RST_VCSYS	95
-#define RST_ETHPHY	96
-#define RST_ETHPHYRST_APB	97
-#define RST_AUDSRC	98
-#define RST_AUTO_CLEAR_CPUCORE0	99
-#define RST_AUTO_CLEAR_CPUCORE1	100
-#define RST_AUTO_CLEAR_CPUCORE2	101
-#define RST_AUTO_CLEAR_CPUCORE3	102
-#define RST_AUTO_CLEAR_MAINRST_AP	103
-#define RST_AUTO_CLEAR_SECONDRST_AP	104
-
-#define CLK_RST_A53		0
-#define CLK_RST_50M_A53		1
-#define CLK_RST_AHB_ROM		2
-#define CLK_RST_AXI_SRAM	3
-#define CLK_RST_DDR_AXI		4
-#define CLK_RST_EFUSE		5
-#define CLK_RST_APB_EFUSE	6
-#define CLK_RST_AXI_EMMC	7
-#define CLK_RST_EMMC		8
-#define CLK_RST_100K_EMMC	9
-#define CLK_RST_AXI_SD		10
-#define CLK_RST_SD		11
-#define CLK_RST_100K_SD		12
-#define CLK_RST_500M_ETH0	13
-#define CLK_RST_AXI_ETH0	14
-#define CLK_RST_500M_ETH1	15
-#define CLK_RST_AXI_ETH1	16
-#define CLK_RST_AXI_GDMA	17
-#define CLK_RST_APB_GPIO	18
-#define CLK_RST_APB_GPIO_INTR	19
-#define CLK_RST_GPIO_DB		20
-#define CLK_RST_AXI_MINER	21
-#define CLK_RST_AHB_SF		22
-#define CLK_RST_SDMA_AXI	23
-#define CLK_RST_SDMA_AUD	24
-#define CLK_RST_APB_I2C		25
-#define CLK_RST_APB_WDT		26
-#define CLK_RST_APB_JPEG	27
-#define CLK_RST_JPEG_AXI	28
-#define CLK_RST_AXI_NF		29
-#define CLK_RST_APB_NF		30
-#define CLK_RST_NF		31
-#define CLK_RST_APB_PWM		32
-#define CLK_RST_RV		33
-#define CLK_RST_APB_SPI		34
-#define CLK_RST_TPU_AXI		35
-#define CLK_RST_UART_500M	36
-#define CLK_RST_APB_UART	37
-#define CLK_RST_APB_I2S		38
-#define CLK_RST_AXI_USB		39
-#define CLK_RST_APB_USB		40
-#define CLK_RST_125M_USB	41
-#define CLK_RST_33K_USB		42
-#define CLK_RST_12M_USB		43
-#define CLK_RST_APB_VIDEO	44
-#define CLK_RST_VIDEO_AXI	45
-#define CLK_RST_VPP_AXI		46
-#define CLK_RST_APB_VPP		47
-#define CLK_RST_AXI1		48
-#define CLK_RST_AXI2		49
-#define CLK_RST_AXI3		50
-#define CLK_RST_AXI4		51
-#define CLK_RST_AXI5		52
-#define CLK_RST_AXI6		53
-
-#endif /* _DT_BINDINGS_RST_CV1835_H_ */
diff --git a/sys/contrib/device-tree/src/riscv/sophgo/cv181x_asic_bga.dtsi b/sys/contrib/device-tree/src/riscv/sophgo/cv181x_asic_bga.dtsi
deleted file mode 100644
index 93039e182782..000000000000
--- a/sys/contrib/device-tree/src/riscv/sophgo/cv181x_asic_bga.dtsi
+++ /dev/null
@@ -1,56 +0,0 @@
-&dac{
-	mute-gpio-l = <&porta 15 GPIO_ACTIVE_LOW>;
-	mute-gpio-r = <&porta 30 GPIO_ACTIVE_LOW>;
-};
-
-&spi0 {
-	status = "disabled";
-	num-cs = <1>;
-	spidev@0 {
-		compatible = "rohm,dh2228fv";
-		spi-max-frequency = <1000000>;
-		reg = <0>;
-	};
-};
-
-&spi1 {
-	status = "disabled";
-	num-cs = <1>;
-	spidev@0 {
-		compatible = "rohm,dh2228fv";
-		spi-max-frequency = <1000000>;
-		reg = <0>;
-	};
-};
-
-&spi2 {
-	status = "disabled";
-	num-cs = <1>;
-	spidev@0 {
-		compatible = "rohm,dh2228fv";
-		spi-max-frequency = <1000000>;
-		reg = <0>;
-	};
-};
-
-&spi3 {
-	status = "okay";
-	num-cs = <1>;
-	spidev@0 {
-		compatible = "rohm,dh2228fv";
-		spi-max-frequency = <1000000>;
-		reg = <0>;
-	};
-};
-
-&i2c1 {
-	status = "disabled";
-};
-
-/ {
-	/delete-node/ i2s@04110000;
-	/delete-node/ i2s@04120000;
-	/delete-node/ sound_ext1;
-	/delete-node/ sound_ext2;
-	/delete-node/ sound_PDM;
-};
diff --git a/sys/contrib/device-tree/src/riscv/sophgo/cv181x_asic_emmc.dtsi b/sys/contrib/device-tree/src/riscv/sophgo/cv181x_asic_emmc.dtsi
deleted file mode 100644
index 507a3a46b342..000000000000
--- a/sys/contrib/device-tree/src/riscv/sophgo/cv181x_asic_emmc.dtsi
+++ /dev/null
@@ -1,4 +0,0 @@
-/ {
-	/delete-node/ cvi-spif@10000000;
-	/delete-node/ cv-spinf@4060000;
-};
diff --git a/sys/contrib/device-tree/src/riscv/sophgo/cv181x_asic_qfn.dtsi b/sys/contrib/device-tree/src/riscv/sophgo/cv181x_asic_qfn.dtsi
deleted file mode 100644
index 5d81e8c2cedc..000000000000
--- a/sys/contrib/device-tree/src/riscv/sophgo/cv181x_asic_qfn.dtsi
+++ /dev/null
@@ -1,120 +0,0 @@
-&sd {
-	no-1-8-v;
-};
-
-&mipi_rx{
-	snsr-reset = <&portc 13 GPIO_ACTIVE_LOW>, <&portc 13 GPIO_ACTIVE_LOW>, <&portc 13 GPIO_ACTIVE_LOW>;
-};
-
-&mipi_tx {
-	reset-gpio = <&porta 15 GPIO_ACTIVE_LOW>;
-	pwm-gpio = <&porta 18 GPIO_ACTIVE_HIGH>;
-	power-ct-gpio = <&porta 19 GPIO_ACTIVE_HIGH>;
-};
-
-&dac{
-	mute-gpio-r = <&porte 2 GPIO_ACTIVE_LOW>;
-};
-
-&spi0 {
-	status = "disabled";
-	num-cs = <1>;
-	spidev@0 {
-		compatible = "rohm,dh2228fv";
-		spi-max-frequency = <1000000>;
-		reg = <0>;
-	};
-};
-
-&spi1 {
-	status = "disabled";
-	num-cs = <1>;
-	spidev@0 {
-		compatible = "rohm,dh2228fv";
-		spi-max-frequency = <1000000>;
-		reg = <0>;
-	};
-};
-
-&spi2 {
-	status = "disabled";
-	num-cs = <1>;
-	spidev@0 {
-	compatible = "rohm,dh2228fv";
-		spi-max-frequency = <1000000>;
-		reg = <0>;
-	};
-};
-
-&spi3 {
-	status = "okay";
-	num-cs = <1>;
-	spidev@0 {
-		compatible = "rohm,dh2228fv";
-		spi-max-frequency = <1000000>;
-		reg = <0>;
-	};
-};
-
-#ifndef CONFIG_PM
-&i2c0 {
-	/* FMUX_GPIO_REG iic_func_sel gpio_func_sel */
-	scl-pinmux = <0x03001070 0x0 0x3>;	// IIC0_SCL/IIC0_SCL/XGPIOA[28]
-	sda-pinmux = <0x03001074 0x0 0x3>;	// IIC0_SDA/IIC0_SDA/XGPIOA[29]
-	/* gpio port */
-	scl-gpios = <&porta 28 GPIO_ACTIVE_HIGH>;
-	sda-gpios = <&porta 29 GPIO_ACTIVE_HIGH>;
-};
-
-&i2c1 {
-	/* FMUX_GPIO_REG iic_func_sel gpio_func_sel */
-	scl-pinmux = <0x03009408 0x2 0x3>;	// SPI1_MOSI/IIC1_SCL/XGPIOB[7]
-	sda-pinmux = <0x0300940c 0x2 0x3>;	// SPI1_MISO/IIC1_SDA/XGPIOB[8]
-	/* gpio port */
-	scl-gpios = <&portb 7 GPIO_ACTIVE_HIGH>;
-	sda-gpios = <&portb 8 GPIO_ACTIVE_HIGH>;
-};
-
-&i2c2 {
-	/* FMUX_GPIO_REG iic_func_sel gpio_func_sel */
-	scl-pinmux = <0x030011a0 0x4 0x3>;	// PAD_MIPI_TXP1/IIC2_SCL/XGPIOC[15]
-	sda-pinmux = <0x0300119c 0x4 0x3>;	// PAD_MIPI_TXM1/IIC2_SDA/XGPIOC[14]
-	/* gpio port */
-	scl-gpios = <&portc 15 GPIO_ACTIVE_HIGH>;
-	sda-gpios = <&portc 14 GPIO_ACTIVE_HIGH>;
-};
-
-&i2c3 {
-	/* FMUX_GPIO_REG iic_func_sel gpio_func_sel */
-	scl-pinmux = <0x03001014 0x0 0x3>;	// IIC3_SCL/IIC3_SCL/XGPIOA[5]
-	sda-pinmux = <0x03001018 0x0 0x3>;	// IIC3_SDA/IIC3_SDA/XGPIOA[6]
-	/* gpio port */
-	scl-gpios = <&porta 5 GPIO_ACTIVE_HIGH>;
-	sda-gpios = <&porta 6 GPIO_ACTIVE_HIGH>;
-};
-
-&i2c4 {
-	/* FMUX_GPIO_REG iic_func_sel gpio_func_sel */
-	scl-pinmux = <0x030010f0 0x2 0x3>;	// ADC3/IIC4_SCL/XGPIOB[1]
-	sda-pinmux = <0x030010f4 0x2 0x3>;	// ADC2/IIC4_SDA/XGPIOB[2]
-	/* gpio port */
-	scl-gpios = <&portb 1 GPIO_ACTIVE_HIGH>;
-	sda-gpios = <&portb 2 GPIO_ACTIVE_HIGH>;
-};
-#endif
-
-/ {
-	/delete-node/ wifi-sd@4320000;
-	/delete-node/ i2s@04110000;
-	/delete-node/ i2s@04120000;
-	/delete-node/ sound_ext1;
-	/delete-node/ sound_ext2;
-	/delete-node/ sound_PDM;
-
-	wifi_pin {
-		compatible = "cvitek,wifi-pin";
-		poweron-gpio = <&porte 2 GPIO_ACTIVE_HIGH>;
-		wakeup-gpio = <&porte 6 GPIO_ACTIVE_HIGH>;
-	};
-
-};
diff --git a/sys/contrib/device-tree/src/riscv/sophgo/cv181x_asic_sd.dtsi b/sys/contrib/device-tree/src/riscv/sophgo/cv181x_asic_sd.dtsi
deleted file mode 100644
index 5af9620d8630..000000000000
--- a/sys/contrib/device-tree/src/riscv/sophgo/cv181x_asic_sd.dtsi
+++ /dev/null
@@ -1,4 +0,0 @@
-/ {
-	/delete-node/ cv-emmc@4300000;
-	/delete-node/ cv-spinf@4060000;
-};
diff --git a/sys/contrib/device-tree/src/riscv/sophgo/cv181x_asic_spinand.dtsi b/sys/contrib/device-tree/src/riscv/sophgo/cv181x_asic_spinand.dtsi
deleted file mode 100644
index 2c3c6065caa3..000000000000
--- a/sys/contrib/device-tree/src/riscv/sophgo/cv181x_asic_spinand.dtsi
+++ /dev/null
@@ -1,5 +0,0 @@
-/ {
-	/delete-node/ cvi-spif@10000000;
-	/delete-node/ cv-emmc@4300000;
-};
-
diff --git a/sys/contrib/device-tree/src/riscv/sophgo/cv181x_asic_spinor.dtsi b/sys/contrib/device-tree/src/riscv/sophgo/cv181x_asic_spinor.dtsi
deleted file mode 100644
index cd125408284a..000000000000
--- a/sys/contrib/device-tree/src/riscv/sophgo/cv181x_asic_spinor.dtsi
+++ /dev/null
@@ -1,5 +0,0 @@
-/ {
-	/delete-node/ cv-emmc@4300000;
-	/delete-node/ cv-spinf@4060000;
-};
-
diff --git a/sys/contrib/device-tree/src/riscv/sophgo/cv181x_base.dtsi b/sys/contrib/device-tree/src/riscv/sophgo/cv181x_base.dtsi
deleted file mode 100644
index 13747090dfa6..000000000000
--- a/sys/contrib/device-tree/src/riscv/sophgo/cv181x_base.dtsi
+++ /dev/null
@@ -1,932 +0,0 @@
-
-/ {
-	compatible = "cvitek,cv181x";
-
-	#size-cells = <0x2>;
-	#address-cells = <0x2>;
-
-	top_misc:top_misc_ctrl@3000000 {
-		compatible = "syscon";
-		reg = <0x0 0x03000000 0x0 0x8000>;
-	};
-
-	clk_rst: clk-reset-controller {
-		#reset-cells = <1>;
-		compatible = "cvitek,clk-reset";
-		reg = <0x0 0x03002000 0x0 0x8>;
-	};
-
-	osc: oscillator {
-		#clock-cells = <0>;
-		compatible = "fixed-clock";
-		clock-frequency = <25000000>;
-		clock-output-names = "osc";
-	};
-
-	clk: clock-controller {
-		compatible = "cvitek,cv181x-clk";
-		reg = <0x0 0x03002000 0x0 0x1000>;
-		clocks = <&osc>;
-		#clock-cells = <1>;
-	};
-
-	rst: reset-controller {
-		#reset-cells = <1>;
-		compatible = "cvitek,reset";
-		reg = <0x0 0x03003000 0x0 0x10>;
-	};
-
-	restart: restart-controller {
-		compatible = "cvitek,restart";
-		reg = <0x0 0x05025000 0x0 0x2000>;
-	};
-
-	tpu {
-		compatible = "cvitek,tpu";
-		reg-names = "tdma", "tiu";
-		reg = <0x0 0x0C100000 0x0 0x1000>,
-			  <0x0 0x0C101000 0x0 0x1000>;
-		clocks = <&clk CV181X_CLK_TPU>, <&clk CV181X_CLK_TPU_FAB>;
-		clock-names = "clk_tpu_axi", "clk_tpu_fab";
-		resets = <&rst RST_TDMA>, <&rst RST_TPU>, <&rst RST_TPUSYS>;
-		reset-names = "res_tdma", "res_tpu", "res_tpusys";
-	};
-
-	mon {
-		compatible = "cvitek,mon";
-		reg-names = "pcmon", "ddr_ctrl", "ddr_phyd", "ddr_aximon", "ddr_top";
-		reg = <0x0 0x01040000 0x0 0x1000>,
-					<0x0 0x08004000 0x0 0x1000>,
-					<0x0 0x08006000 0x0 0x1000>,
-					<0x0 0x08008000 0x0 0x1000>,
-					<0x0 0x0800A000 0x0 0x1000>;
-	};
-
-	wiegand0 {
-		compatible = "cvitek,wiegand";
-		reg-names = "wiegand";
-		reg = <0x0 0x03030000 0x0 0x1000>;
-		clocks = <&clk CV181X_CLK_WGN>, <&clk CV181X_CLK_WGN0>;
-		clock-names = "clk_wgn", "clk_wgn1";
-		resets = <&rst RST_WGN0>;
-		reset-names = "res_wgn";
-	};
-
-	wiegand1 {
-		compatible = "cvitek,wiegand";
-		reg-names = "wiegand";
-		reg = <0x0 0x03031000 0x0 0x1000>;
-		clocks = <&clk CV181X_CLK_WGN>, <&clk CV181X_CLK_WGN1>;
-		clock-names = "clk_wgn", "clk_wgn1";
-		resets = <&rst RST_WGN1>;
-		reset-names = "res_wgn";
-	};
-
-	wiegand2 {
-		compatible = "cvitek,wiegand";
-		reg-names = "wiegand";
-		reg = <0x0 0x03032000 0x0 0x1000>;
-		clocks = <&clk CV181X_CLK_WGN>, <&clk CV181X_CLK_WGN2>;
-		clock-names = "clk_wgn", "clk_wgn1";
-		resets = <&rst RST_WGN2>;
-		reset-names = "res_wgn";
-	};
-
-	saradc {
-		compatible = "cvitek,saradc";
-		reg-names = "top_domain_saradc", "rtc_domain_saradc";
-		reg = <0x0 0x030F0000 0x0 0x1000>, <0x0 0x0502c000 0x0 0x1000>;
-		clocks = <&clk CV181X_CLK_SARADC>;
-		clock-names = "clk_saradc";
-		resets = <&rst RST_SARADC>;
-		reset-names = "res_saradc";
-	};
-
-	rtc {
-		compatible = "cvitek,rtc";
-		reg = <0x0 0x05026000 0x0 0x1000>,<0x0 0x05025000 0x0 0x1000>;
-		clocks = <&clk CV181X_CLK_RTC_25M>;
-		clock-names = "clk_rtc";
-	};
-
-	cvitek-ion {
-		compatible = "cvitek,cvitek-ion";
-
-		heap_carveout@0 {
-			compatible = "cvitek,carveout";
-			memory-region = <&ion_reserved>;
-		};
-	};
-
-	sysdma_remap {
-		compatible = "cvitek,sysdma_remap";
-		reg = <0x0 0x03000154 0x0 0x10>;
-		ch-remap = <CVI_I2S0_RX CVI_I2S2_TX CVI_I2S1_RX CVI_I2S1_TX
-					CVI_SPI_NAND CVI_SPI_NAND CVI_I2S2_RX CVI_I2S3_TX>;
-		int_mux_base = <0x03000298>;
-	};
-
-	dmac: dma@0x4330000 {
-		compatible = "snps,dmac-bm";
-		reg = <0x0 0x04330000 0x0 0x1000>;
-		clock-names = "clk_sdma_axi";
-		clocks = <&clk CV181X_CLK_SDMA_AXI>;
-
-		dma-channels = /bits/ 8 <8>;
-		#dma-cells = <3>;
-		dma-requests = /bits/ 8 <16>;
-		chan_allocation_order = /bits/ 8 <0>;
-		chan_priority = /bits/ 8 <1>;
-		block_size = <1024>;
-		dma-masters = /bits/ 8 <2>;
-		data-width = <4 4>; /* bytes */
-		axi_tr_width = <4>; /* bytes */
-		block-ts = <15>;
-	};
-
-
-	watchdog0: cv-wd@0x3010000 {
-		compatible = "snps,dw-wdt";
-		reg = <0x0 0x03010000 0x0 0x1000>;
-		resets = <&rst RST_WDT>;
-		clocks = <&pclk>;
-	};
-
-	pwm0: pwm@3060000 {
-		compatible = "cvitek,cvi-pwm";
-		reg = <0x0 0x3060000 0x0 0x1000>;
-		clocks = <&clk CV181X_CLK_PWM>;
-		#pwm-cells = <1>;
-	};
-
-	pwm1: pwm@3061000 {
-		compatible = "cvitek,cvi-pwm";
-		reg = <0x0 0x3061000 0x0 0x1000>;
-		clocks = <&clk CV181X_CLK_PWM>;
-		#pwm-cells = <2>;
-	};
-
-	pwm2: pwm@3062000 {
-		compatible = "cvitek,cvi-pwm";
-		reg = <0x0 0x3062000 0x0 0x1000>;
-		clocks = <&clk CV181X_CLK_PWM>;
-		#pwm-cells = <3>;
-	};
-
-	pwm3: pwm@3063000 {
-		compatible = "cvitek,cvi-pwm";
-		reg = <0x0 0x3063000 0x0 0x1000>;
-		clocks = <&clk CV181X_CLK_PWM>;
-		#pwm-cells = <4>;
-	};
-
-	pclk: pclk {
-		#clock-cells = <0>;
-		compatible = "fixed-clock";
-		clock-frequency = <25000000>;
-	};
-
-	spinand:cv-spinf@4060000 {
-		compatible = "cvitek,cv1835-spinf";
-		reg = <0x0 0x4060000 0x0 0x1000>;
-		reg-names = "core_mem";
-		bus-width = <4>;
-		dmas = <&dmac 4 1 1
-			&dmac 5 1 1>;
-		dma-names = "rx","tx";
-	};
-
-	spif:cvi-spif@10000000 {
-		compatible = "cvitek,cvi-spif";
-		bus-num = <0>;
-		reg = <0x0 0x10000000 0x0 0x10000000>;
-		reg-names = "spif";
-		sck-div = <3>;
-		sck_mhz = <300>;
-		spi-max-frequency = <75000000>;
-		spiflash {
-			compatible = "jedec,spi-nor";
-			spi-rx-bus-width = <4>;
-			spi-tx-bus-width = <4>;
-		};
-	};
-
-	spi0:spi0@04180000 {
-		compatible = "snps,dw-apb-ssi";
-		reg = <0x0 0x04180000 0x0 0x10000>;
-		clocks = <&clk CV181X_CLK_SPI>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-	};
-
-	spi1:spi1@04190000 {
-		compatible = "snps,dw-apb-ssi";
-		reg = <0x0 0x04190000 0x0 0x10000>;
-		clocks = <&clk CV181X_CLK_SPI>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-	};
-
-	spi2:spi2@041A0000 {
-		compatible = "snps,dw-apb-ssi";
-		reg = <0x0 0x041A0000 0x0 0x10000>;
-		clocks = <&clk CV181X_CLK_SPI>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-	};
-
-	spi3:spi3@041B0000 {
-		compatible = "snps,dw-apb-ssi";
-		reg = <0x0 0x041B0000 0x0 0x10000>;
-		clocks = <&clk CV181X_CLK_SPI>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-#if 0
-		dmas = <&dmac 2 1 1
-			&dmac 3 1 1>;
-		dma-names = "rx", "tx";
-		capability = "txrx";
-#endif
-	};
-
-	uart0: serial@04140000 {
-		compatible = "snps,dw-apb-uart";
-		reg = <0x0 0x04140000 0x0 0x1000>;
-		clock-frequency = <25000000>;
-		reg-shift = <2>;
-		reg-io-width = <4>;
-		status = "okay";
-	};
-
-	uart1: serial@04150000 {
-		compatible = "snps,dw-apb-uart";
-		reg = <0x0 0x04150000 0x0 0x1000>;
-		clock-frequency = <25000000>;
-		reg-shift = <2>;
-		reg-io-width = <4>;
-		status = "disabled";
-	};
-
-	uart2: serial@04160000 {
-		compatible = "snps,dw-apb-uart";
-		reg = <0x0 0x04160000 0x0 0x1000>;
-		clock-frequency = <25000000>;
-		reg-shift = <2>;
-		reg-io-width = <4>;
-		status = "disabled";
-	};
-
-	uart3: serial@04170000 {
-		compatible = "snps,dw-apb-uart";
-		reg = <0x0 0x04170000 0x0 0x1000>;
-		clock-frequency = <25000000>;
-		reg-shift = <2>;
-		reg-io-width = <4>;
-		status = "disabled";
-	};
-
-	uart4: serial@041C0000 {
-		compatible = "snps,dw-apb-uart";
-		reg = <0x0 0x041C0000 0x0 0x1000>;
-		clock-frequency = <25000000>;
-		reg-shift = <2>;
-		reg-io-width = <4>;
-		status = "disabled";
-	};
-
-	gpio0: gpio@03020000 {
-		compatible = "snps,dw-apb-gpio";
-		reg = <0x0 0x03020000 0x0 0x1000>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		porta: gpio-controller@0 {
-			compatible = "snps,dw-apb-gpio-port";
-			bank-name = "porta";
-			gpio-controller;
-			#gpio-cells = <2>;
-			snps,nr-gpios = <32>;
-			reg = <0>;
-		};
-	};
-
-	gpio1: gpio@03021000 {
-		compatible = "snps,dw-apb-gpio";
-		reg = <0x0 0x03021000 0x0 0x1000>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		portb: gpio-controller@1 {
-			compatible = "snps,dw-apb-gpio-port";
-			bank-name = "portb";
-			gpio-controller;
-			#gpio-cells = <2>;
-			snps,nr-gpios = <32>;
-			reg = <0>;
-		};
-	};
-
-	gpio2: gpio@03022000 {
-		compatible = "snps,dw-apb-gpio";
-		reg = <0x0 0x03022000 0x0 0x1000>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		portc: gpio-controller@2 {
-			compatible = "snps,dw-apb-gpio-port";
-			bank-name = "portc";
-			gpio-controller;
-			#gpio-cells = <2>;
-			snps,nr-gpios = <32>;
-			reg = <0>;
-		};
-	};
-
-	gpio3: gpio@03023000 {
-		compatible = "snps,dw-apb-gpio";
-		reg = <0x0 0x03023000 0x0 0x1000>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		portd: gpio-controller@3 {
-			compatible = "snps,dw-apb-gpio-port";
-			bank-name = "portd";
-			gpio-controller;
-			#gpio-cells = <2>;
-			snps,nr-gpios = <32>;
-			reg = <0>;
-		};
-	};
-
-	gpio4: gpio@05021000 {
-		compatible = "snps,dw-apb-gpio";
-		reg = <0x0 0x05021000 0x0 0x1000>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		porte: gpio-controller@4 {
-			compatible = "snps,dw-apb-gpio-port";
-			bank-name = "porte";
-			gpio-controller;
-			#gpio-cells = <2>;
-			snps,nr-gpios = <32>;
-			reg = <0>;
-		};
-	};
-
-	i2c0: i2c@04000000 {
-		compatible = "snps,designware-i2c";
-		clocks = <&clk CV181X_CLK_I2C>;
-		reg = <0x0 0x04000000 0x0 0x1000>;
-		clock-frequency = <400000>;
-
-		#size-cells = <0x0>;
-		#address-cells = <0x1>;
-		resets = <&rst RST_I2C0>;
-		reset-names = "i2c0";
-	};
-
-	i2c1: i2c@04010000 {
-		compatible = "snps,designware-i2c";
-		clocks = <&clk CV181X_CLK_I2C>;
-		reg = <0x0 0x04010000 0x0 0x1000>;
-		clock-frequency = <400000>;
-
-		#size-cells = <0x0>;
-		#address-cells = <0x1>;
-		resets = <&rst RST_I2C1>;
-		reset-names = "i2c1";
-	};
-
-	i2c2: i2c@04020000 {
-		compatible = "snps,designware-i2c";
-		clocks = <&clk CV181X_CLK_I2C>;
-		reg = <0x0 0x04020000 0x0 0x1000>;
-		clock-frequency = <100000>;
-		resets = <&rst RST_I2C2>;
-		reset-names = "i2c2";
-	};
-
-	i2c3: i2c@04030000 {
-		compatible = "snps,designware-i2c";
-		clocks = <&clk CV181X_CLK_I2C>;
-		reg = <0x0 0x04030000 0x0 0x1000>;
-		clock-frequency = <400000>;
-		resets = <&rst RST_I2C3>;
-		reset-names = "i2c3";
-	};
-
-	i2c4: i2c@04040000 {
-		compatible = "snps,designware-i2c";
-		clocks = <&clk CV181X_CLK_I2C>;
-		reg = <0x0 0x04040000 0x0 0x1000>;
-		clock-frequency = <400000>;
-		resets = <&rst RST_I2C4>;
-		reset-names = "i2c4";
-	};
-
-	eth_csrclk: eth_csrclk {
-		clock-output-names = "eth_csrclk";
-		clock-frequency = <250000000>;
-		#clock-cells = <0x0>;
-		compatible = "fixed-clock";
-	};
-
-	eth_ptpclk: eth_ptpclk {
-		clock-output-names = "eth_ptpclk";
-		clock-frequency = <50000000>;
-		#clock-cells = <0x0>;
-		compatible = "fixed-clock";
-	};
-
-	stmmac_axi_setup: stmmac-axi-config {
-		snps,wr_osr_lmt = <1>;
-		snps,rd_osr_lmt = <2>;
-		snps,blen = <4 8 16 0 0 0 0>;
-	};
-
-	mtl_rx_setup: rx-queues-config {
-		snps,rx-queues-to-use = <1>;
-		queue0 {};
-	};
-
-	mtl_tx_setup: tx-queues-config {
-		snps,tx-queues-to-use = <1>;
-		queue0 {};
-	};
-
-	ethernet0: ethernet@4070000 {
-		compatible = "cvitek,ethernet";
-		reg = <0x0 0x04070000 0x0 0x10000>;
-		clock-names = "stmmaceth", "ptp_ref";
-		clocks = <&eth_csrclk>, <&eth_ptpclk>;
-		//phy-reset-gpios = <&porta 26 0>;
-
-		tx-fifo-depth = <8192>;
-		rx-fifo-depth = <8192>;
-		/* no hash filter and perfect filter support */
-		snps,multicast-filter-bins = <0>;
-		snps,perfect-filter-entries = <1>;
-
-		snps,txpbl = <8>;
-		snps,rxpbl = <8>;
-		snps,aal;
-
-		snps,axi-config = <&stmmac_axi_setup>;
-		snps,mtl-rx-config = <&mtl_rx_setup>;
-		snps,mtl-tx-config = <&mtl_tx_setup>;
-
-		phy-mode = "rmii";
-	};
-
-	emmc:cv-emmc@4300000 {
-		compatible = "cvitek,cv181x-emmc";
-		reg = <0x0 0x4300000 0x0 0x1000>;
-		reg-names = "core_mem";
-		bus-width = <4>;
-		non-removable;
-		no-sdio;
-		no-sd;
-		src-frequency = <375000000>;
-		min-frequency = <400000>;
-		max-frequency = <200000000>;
-		64_addressing;
-		reset_tx_rx_phy;
-		pll_index = <0x5>;
-		pll_reg = <0x3002064>;
-	};
-
-	sd:cv-sd@4310000 {
-		compatible = "cvitek,cv181x-sd";
-		reg = <0x0 0x4310000 0x0 0x1000>;
-		reg-names = "core_mem";
-		bus-width = <4>;
-		cap-sd-highspeed;
-		cap-mmc-highspeed;
-		sd-uhs-sdr12;
-		sd-uhs-sdr25;
-		sd-uhs-sdr50;
-		sd-uhs-sdr104;
-		no-sdio;
-		no-mmc;
-		/*no-1-8-v;*/
-		src-frequency = <375000000>;
-		min-frequency = <400000>;
-		max-frequency = <200000000>;
-		64_addressing;
-		reset_tx_rx_phy;
-		reset-names = "sdhci";
-		pll_index = <0x6>;
-		pll_reg = <0x3002070>;
-		cvi-cd-gpios = <&porta 13 GPIO_ACTIVE_LOW>;
-	};
-
-	wifisd:wifi-sd@4320000 {
-		compatible = "cvitek,cv181x-sdio";
-		bus-width = <4>;
-		reg = <0x0 0x4320000 0x0 0x1000>;
-		reg_names = "core_mem";
-		src-frequency = <375000000>;
-		min-frequency = <400000>;
-		max-frequency = <50000000>;
-		64_addressing;
-		reset_tx_rx_phy;
-		non-removable;
-		pll_index = <0x7>;
-		pll_reg = <0x300207C>;
-		no-mmc;
-		no-sd;
-		status = "disabled";
-	};
-
-	i2s_mclk: i2s_mclk {
-		clock-output-names = "i2s_mclk";
-		clock-frequency = <24576000>;
-		#clock-cells = <0x0>;
-		compatible = "fixed-clock";
-	};
-
-	i2s_subsys {
-		compatible = "cvitek,i2s_tdm_subsys";
-		reg = <0x0 0x04108000 0x0 0x100>;
-		clocks = <&i2s_mclk>, <&clk CV181X_CLK_A0PLL>,
-			<&clk CV181X_CLK_SDMA_AUD0>, <&clk CV181X_CLK_SDMA_AUD1>,
-			<&clk CV181X_CLK_SDMA_AUD2>, <&clk CV181X_CLK_SDMA_AUD3>;
-		clock-names = "i2sclk", "clk_a0pll",
-			"clk_sdma_aud0", "clk_sdma_aud1",
-			"clk_sdma_aud2", "clk_sdma_aud3";
-		master_base = <0x04110000>; /* I2S1 is master, only useful while using multi I2S IPs work on same IO */
-	};
-
-	i2s0: i2s@04100000 {
-		compatible = "cvitek,cv1835-i2s";
-		reg = <0x0 0x04100000 0x0 0x2000>;
-		clocks = <&i2s_mclk 0>;
-		clock-names = "i2sclk";
-		dev-id = <0>;
-		#sound-dai-cells = <0>;
-		dmas = <&dmac 0 1 1>; /* read channel */
-		dma-names = "rx";
-		capability = "rx"; /* I2S0 connect to internal ADC as RX */
-		mclk_out = "false";
-	};
-
-	i2s1: i2s@04110000 {
-		compatible = "cvitek,cv1835-i2s";
-		reg = <0x0 0x04110000 0x0 0x2000>;
-		clocks = <&i2s_mclk 0>;
-		clock-names = "i2sclk";
-		dev-id = <1>;
-		#sound-dai-cells = <0>;
-		dmas = <&dmac 2 1 1 /* read channel */
-			&dmac 3 1 1>; /* write channel */
-		dma-names = "rx", "tx";
-		capability = "txrx";
-		mclk_out = "false";
-	};
-
-	i2s2: i2s@04120000 {
-		compatible = "cvitek,cv1835-i2s";
-		reg = <0x0 0x04120000 0x0 0x2000>;
-		clocks = <&i2s_mclk 0>;
-		clock-names = "i2sclk";
-		dev-id = <2>;
-		#sound-dai-cells = <0>;
-		dmas = <&dmac 6 1 1 /* read channel */
-			&dmac 1 1 1>; /* write channel */
-		dma-names = "rx", "tx";
-		capability = "txrx";
-		mclk_out = "false";
-
-	};
-
-	i2s3: i2s@04130000 {
-		compatible = "cvitek,cv1835-i2s";
-		reg = <0x0 0x04130000 0x0 0x2000>;
-		clocks = <&i2s_mclk 0>;
-		clock-names = "i2sclk";
-		dev-id = <3>;
-		#sound-dai-cells = <0>;
-		dmas = <&dmac 7 1 1>; /* write channel */
-		dma-names = "tx";
-		capability = "tx"; /* I2S3 connect to internal DAC as TX */
-		mclk_out = "true";
-	};
-
-	adc: adc@0300A100 {
-		compatible = "cvitek,cv182xaadc";
-		reg = <0x0 0x0300A100 0x0 0x100>;
-		clocks = <&i2s_mclk 0>;
-		clock-names = "i2sclk";
-		clk_source = <0x04130000>; /* MCLK source is I2S3 */
-	};
-
-	dac: dac@0300A000 {
-		compatible = "cvitek,cv182xadac";
-		reg = <0x0 0x0300A000 0x0 0x100>;
-		clocks = <&i2s_mclk 0>;
-		clock-names = "i2sclk";
-	};
-
-	pdm: pdm@0x041D0C00 {
-		compatible = "cvitek,cv1835pdm";
-		reg = <0x0 0x041D0C00 0x0 0x100>;
-		clocks = <&i2s_mclk 0>;
-		clock-names = "i2sclk";
-	};
-
-	sound_adc {
-		compatible = "cvitek,cv182xa-adc";
-		cvi,model = "CV182XA";
-		cvi,card_name = "cv182xa_adc";
-	};
-
-	sound_dac {
-		compatible = "cvitek,cv182xa-dac";
-		cvi,model = "CV182XA";
-		cvi,card_name = "cv182xa_dac";
-	};
-
-	sound_PDM {
-		compatible = "cvitek,cv182x-pdm";
-		cvi,model = "CV182X";
-		cvi,card_name = "cv182x_internal_PDM";
-	};
-
-	wifi_pin {
-		compatible = "cvitek,wifi-pin";
-		poweron-gpio = <&porta 18 GPIO_ACTIVE_HIGH>;
-		wakeup-gpio = <&porte 7 GPIO_ACTIVE_HIGH>;
-	};
-
-	bt_pin {
-		compatible = "cvitek,bt-pin";
-		poweron-gpio = <&porte 9 GPIO_ACTIVE_HIGH>;
-	};
-
-	mipi_rx: cif {
-		compatible = "cvitek,cif";
-		reg = <0x0 0x0a0c2000 0x0 0x2000>, <0x0 0x0a0d0000 0x0 0x1000>,
-		      <0x0 0x0a0c4000 0x0 0x2000>, <0x0 0x0a0c6000 0x0 0x2000>,
-		      <0x0 0x03001c30 0x0 0x30>;
-		reg-names = "csi_mac0", "csi_wrap0", "csi_mac1", "csi_mac2", "pad_ctrl";
-		snsr-reset = <&porta 2 GPIO_ACTIVE_LOW>, <&porta 2 GPIO_ACTIVE_LOW>, <&porta 2 GPIO_ACTIVE_LOW>;
-		resets = <&rst RST_CSIPHY0>, <&rst RST_CSIPHY1>,
-			<&rst RST_CSIPHY0RST_APB>, <&rst RST_CSIPHY1RST_APB>;
-		reset-names = "phy0", "phy1", "phy-apb0", "phy-apb1";
-		clocks = <&clk CV181X_CLK_CAM0>, <&clk CV181X_CLK_CAM1>, <&clk CV181X_CLK_SRC_VIP_SYS_2>,
-			 <&clk CV181X_CLK_MIPIMPLL>, <&clk CV181X_CLK_DISPPLL>, <&clk CV181X_CLK_FPLL>;
-		clock-names = "clk_cam0", "clk_cam1", "clk_sys_2",
-			      "clk_mipimpll", "clk_disppll", "clk_fpll";
-	};
-
-	mipi_tx: mipi_tx {
-		compatible = "cvitek,mipi_tx";
-		reset-gpio = <&porte 2 GPIO_ACTIVE_LOW>;
-		pwm-gpio = <&porte 0 GPIO_ACTIVE_HIGH>;
-		power-ct-gpio = <&porte 1 GPIO_ACTIVE_HIGH>;
-		clocks = <&clk CV181X_CLK_DISP_VIP>, <&clk CV181X_CLK_DSI_MAC_VIP>;
-		clock-names = "clk_disp", "clk_dsi";
-	};
-
-	sys {
-		compatible = "cvitek,sys";
-	};
-
-	base {
-		compatible = "cvitek,base";
-		reg = <0x0 0x0a0c8000 0x0 0x20>;
-		reg-names = "vip_sys";
-	};
-
-	vi {
-		compatible = "cvitek,vi";
-		reg = <0x0 0x0a000000 0x0 0x80000>;
-		clocks = <&clk CV181X_CLK_SRC_VIP_SYS_0>, <&clk CV181X_CLK_SRC_VIP_SYS_1>,
-				<&clk CV181X_CLK_SRC_VIP_SYS_2>, <&clk CV181X_CLK_SRC_VIP_SYS_3>,
-				<&clk CV181X_CLK_AXI_VIP>, <&clk CV181X_CLK_CSI_BE_VIP>,
-				<&clk CV181X_CLK_RAW_VIP>, <&clk CV181X_CLK_ISP_TOP_VIP>,
-				<&clk CV181X_CLK_CSI_MAC0_VIP>, <&clk CV181X_CLK_CSI_MAC1_VIP>,
-				<&clk CV181X_CLK_CSI_MAC2_VIP>;
-		clock-names = "clk_sys_0", "clk_sys_1", "clk_sys_2", "clk_sys_3",
-					"clk_axi", "clk_csi_be", "clk_raw", "clk_isp_top",
-					"clk_csi_mac0", "clk_csi_mac1", "clk_csi_mac2";
-		clock-freq-vip-sys1 = <300000000>;
-	};
-
-	vpss {
-		compatible = "cvitek,vpss";
-		reg = <0x0 0x0a080000 0x0 0x10000>, <0x0 0x0a0d1000 0x0 0x100>;
-		reg-names = "sc";
-		clocks = <&clk CV181X_CLK_SRC_VIP_SYS_0>,	<&clk CV181X_CLK_SRC_VIP_SYS_1>,
-			<&clk CV181X_CLK_SRC_VIP_SYS_2>, <&clk CV181X_CLK_IMG_D_VIP>,
-			<&clk CV181X_CLK_IMG_V_VIP>, <&clk CV181X_CLK_SC_TOP_VIP>,
-			<&clk CV181X_CLK_SC_D_VIP>, <&clk CV181X_CLK_SC_V1_VIP>,
-			<&clk CV181X_CLK_SC_V2_VIP>, <&clk CV181X_CLK_SC_V3_VIP>;
-		clock-names = "clk_sys_0", "clk_sys_1",
-			"clk_sys_2", "clk_img_d",
-			"clk_img_v", "clk_sc_top",
-			"clk_sc_d", "clk_sc_v1",
-			"clk_sc_v2", "clk_sc_v3";
-		clock-freq-vip-sys1 = <300000000>;
-	};
-
-	ive {
-		compatible = "cvitek,ive";
-		reg = <0x0 0x0A0A0000 0x0 0x3100>;
-		reg-names = "ive_base";
-	};
-
-	vo:vo {
-		compatible = "cvitek,vo";
-		reg = <0x0 0x0a080000 0x0 0x10000>, <0x0 0x0a0c8000 0x0 0xa0>, <0x0 0x0a0d1000 0x0 0x100>;
-		reg-names = "sc", "vip_sys", "dphy";
-		clocks = <&clk CV181X_CLK_DISP_VIP>, <&clk CV181X_CLK_DSI_MAC_VIP>, <&clk CV181X_CLK_BT_VIP>;
-		reset-gpio = <&porte 2 GPIO_ACTIVE_LOW>;
-		pwm-gpio = <&porte 0 GPIO_ACTIVE_HIGH>;
-		power-ct-gpio = <&porte 1 GPIO_ACTIVE_HIGH>;
-		clock-names = "clk_disp", "clk_dsi", "clk_bt";
-	};
-
-#if (CVIMMAP_FRAMEBUFFER_SIZE > 0)
-	reserved-memory {
-	  #size-cells = <0x2>;
-	  #address-cells = <0x2>;
-	  ranges;
-
-		fb_reserved: cvifb {
-			alloc-ranges = <0x0 CVIMMAP_FRAMEBUFFER_ADDR 0 CVIMMAP_FRAMEBUFFER_SIZE>;
-			size = <0x0 CVIMMAP_FRAMEBUFFER_SIZE>;
-		};
-	};
-
-	cvifb {
-		compatible = "cvitek,fb";
-		memory-region = <&fb_reserved>;
-		reg = <0x0 0x0a088000 0x0 0x1000>;
-		reg-names = "disp";
-	};
-#endif
-	dwa {
-		compatible = "cvitek,dwa";
-		reg = <0x0 0x0a0c0000 0x0 0x1000>;
-		reg-names = "dwa";
-		clocks = <&clk CV181X_CLK_SRC_VIP_SYS_0>, <&clk CV181X_CLK_SRC_VIP_SYS_1>,
-			<&clk CV181X_CLK_SRC_VIP_SYS_2>, <&clk CV181X_CLK_SRC_VIP_SYS_3>,
-			<&clk CV181X_CLK_SRC_VIP_SYS_4>, <&clk CV181X_CLK_DWA_VIP>;
-		clock-names = "clk_sys_0", "clk_sys_1",
-			"clk_sys_2", "clk_sys_3",
-			"clk_sys_4", "clk_dwa";
-		clock-freq-vip-sys1 = <300000000>;
-	};
-
-	rgn {
-		compatible = "cvitek,rgn";
-	};
-
-	vcodec {
-		compatible = "cvitek,asic-vcodec";
-		reg = <0x0 0x0B020000 0x0 0x10000>,<0x0 0x0B010000 0x0 0x10000>,<0x0 0x0B030000 0x0 0x100>,
-		      <0x0 0x0B058000 0x0 0x100>,<0x0 0x0B050000 0x0 0x400>;
-		reg-names = "h265","h264","vc_ctrl","vc_sbm","vc_addr_remap";
-		clocks = <&clk CV181X_CLK_AXI_VIDEO_CODEC>,
-			<&clk CV181X_CLK_H264C>, <&clk CV181X_CLK_APB_H264C>,
-			<&clk CV181X_CLK_H265C>, <&clk CV181X_CLK_APB_H265C>,
-			<&clk CV181X_CLK_VC_SRC0>, <&clk CV181X_CLK_VC_SRC1>,
-			<&clk CV181X_CLK_VC_SRC2>, <&clk CV181X_CLK_CFG_REG_VC>;
-		clock-names = "clk_axi_video_codec",
-			"clk_h264c", "clk_apb_h264c",
-			"clk_h265c", "clk_apb_h265c",
-			"clk_vc_src0", "clk_vc_src1",
-			"clk_vc_src2", "clk_cfg_reg_vc";
-	};
-
-	jpu {
-		compatible = "cvitek,asic-jpeg";
-		reg = <0x0 0x0B000000 0x0 0x300>,<0x0 0x0B030000 0x0 0x100>,<0x0 0x0B058000 0x0 0x100>;
-		reg-names = "jpeg","vc_ctrl","vc_sbm";
-		clocks = <&clk CV181X_CLK_AXI_VIDEO_CODEC>,
-			<&clk CV181X_CLK_JPEG>, <&clk CV181X_CLK_APB_JPEG>,
-			<&clk CV181X_CLK_VC_SRC0>, <&clk CV181X_CLK_VC_SRC1>,
-			<&clk CV181X_CLK_VC_SRC2>, <&clk CV181X_CLK_CFG_REG_VC>;
-		clock-names = "clk_axi_video_codec",
-			"clk_jpeg", "clk_apb_jpeg",
-			"clk_vc_src0", "clk_vc_src1",
-			"clk_vc_src2", "clk_cfg_reg_vc";
-		resets = <&rst RST_JPEG>;
-		reset-names = "jpeg";
-	};
-
-	cvi_vc_drv {
-		compatible = "cvitek,cvi_vc_drv";
-		reg = <0x0 0x0B030000 0x0 0x100>,<0x0 0x0B058000 0x0 0x100>,<0x0 0x0B050000 0x0 0x400>;
-		reg-names = "vc_ctrl","vc_sbm","vc_addr_remap";
-	};
-
-	rtos_cmdqu {
-		compatible = "cvitek,rtos_cmdqu";
-		reg = <0x0 0x01900000 0x0 0x1000>;
-		reg-names = "mailbox";
-	};
-
-	usb: usb@04340000 {
-		compatible = "cvitek,cv182x-usb";
-		reg = <0x0 0x04340000 0x0 0x10000>,
-			<0x0 0x03006000 0x0 0x58>;	//USB 2.0 PHY
-		dr_mode = "otg";
-		g-use-dma;
-		g-rx-fifo-size = <536>;
-		g-np-tx-fifo-size = <32>;
-		g-tx-fifo-size = <768 512 512 384 128 128>;
-		clocks = <&clk CV181X_CLK_AXI4_USB>,
-				<&clk CV181X_CLK_APB_USB>,
-				<&clk CV181X_CLK_125M_USB>,
-				<&clk CV181X_CLK_33K_USB>,
-				<&clk CV181X_CLK_12M_USB>;
-		clock-names = "clk_axi", "clk_apb", "clk_125m", "clk_33k", "clk_12m";
-		vbus-gpio = <&portb 6 0>;
-		status = "okay";
-	};
-
-	thermal:thermal@030E0000 {
-		compatible = "cvitek,cv181x-thermal";
-		reg = <0x0 0x030E0000 0x0 0x10000>;
-		clocks = <&clk CV181X_CLK_TEMPSEN>;
-		clock-names = "clk_tempsen";
-		reset-names = "tempsen";
-		#thermal-sensor-cells = <1>;
-	};
-
-	thermal-zones {
-		soc_thermal_0: soc_thermal_0 {
-			polling-delay-passive = <1000>; /* milliseconds */
-			polling-delay = <1000>; /* milliseconds */
-			thermal-sensors = <&thermal 0>;
-
-			trips {
-				soc_thermal_trip_0: soc_thermal_trip_0 {
-					temperature = <100000>; /* millicelsius */
-					hysteresis = <5000>; /* millicelsius */
-					type = "passive";
-				};
-
-				soc_thermal_trip_1: soc_thermal_trip_1 {
-					temperature = <110000>; /* millicelsius */
-					hysteresis = <5000>; /* millicelsius */
-					type = "passive";
-				};
-
-				soc_thermal_crtical_0: soc_thermal_crtical_0 {
-					temperature = <130000>; /* millicelsius */
-					hysteresis = <0>; /* millicelsius */
-					type = "critical";
-				};
-			};
-		};
-	};
-
-#if 0
-	cvipctrl: pinctrl@3001000 {
-		compatible = "cvitek,pinctrl-cv182x";
-		reg = <0 0x03001000 0 0x1000>;
-	};
-#endif
-
-	cviaudio_core {
-		compatible = "cvitek,audio";
-	};
-
-	audio_clock: audio_clock {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-#if 0
-		clock-frequency = <12288000>;
-#else
-		clock-frequency = <24576000>;
-#endif
-		};
-
-
-	aliases {
-		i2c0 = &i2c0;
-		i2c1 = &i2c1;
-		i2c2 = &i2c2;
-		i2c3 = &i2c3;
-		i2c4 = &i2c4;
-		//spi0 = &spi0;
-		//spi1 = &spi1;
-		//spi2 = &spi2;
-		//spi3 = &spi3;
-		serial0 = &uart0;
-		serial1 = &uart1;
-		serial2 = &uart2;
-		serial3 = &uart3;
-		serial4 = &uart4;
-		ethernet0 = &ethernet0;
-	};
-
-	chosen {
-		stdout-path = "serial0";
-	};
-};
-
diff --git a/sys/contrib/device-tree/src/riscv/sophgo/cv181x_base_arm.dtsi b/sys/contrib/device-tree/src/riscv/sophgo/cv181x_base_arm.dtsi
deleted file mode 100644
index 2993b9da32b2..000000000000
--- a/sys/contrib/device-tree/src/riscv/sophgo/cv181x_base_arm.dtsi
+++ /dev/null
@@ -1,320 +0,0 @@
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/reset/cv181x-resets.h>
-#include <dt-bindings/clock/cv181x-clock.h>
-#include <dt-bindings/thermal/thermal.h>
-#include <dt-bindings/dma/cv181x-dmamap.h>
-#include "cv181x_base.dtsi"
-
-/ {
-	model = "Cvitek. CV181X ASIC. ARM.";
-	interrupt-parent = <&gic>;
-
-	#size-cells = <0x2>;
-	#address-cells = <0x2>;
-
-	gic: interrupt-controller {
-		compatible = "arm,cortex-a15-gic";
-		ranges;
-		#size-cells = <0x2>;
-		#address-cells = <0x2>;
-		interrupt-controller;
-		#interrupt-cells = <0x3>;
-		reg = <0x0 0x01F01000 0x0 0x1000>,
-		      <0x0 0x01F02000 0x0 0x2000>;
-	};
-
-	pmu_a53 {
-		compatible = "arm,cortex-a53-pmu";
-		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-affinity = <&A53_0>;
-	};
-
-	psci {
-		migrate = <0xc4000005>;
-		cpu_on = <0xc4000003>;
-		cpu_off = <0x84000002>;
-		cpu_suspend = <0xc4000001>;
-		sys_poweroff = <0x84000008>;
-		sys_reset = <0x84000009>;
-		method = "smc";
-		compatible = "arm,psci-0.2", "arm,psci";
-	};
-
-	cpus {
-		#size-cells = <0x0>;
-		#address-cells = <0x1>;
-
-		A53_0: cpu@0 {
-			reg = <0x0>;
-			enable-method = "psci";
-			compatible = "arm,cortex-a53";
-			device_type = "cpu";
-			next-level-cache = <&CA53_L2>;
-		};
-
-		CA53_L2: l2-cache0 {
-			compatible = "cache";
-		};
-	};
-
-	timer {
-		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
-		always-on;
-		clock-frequency = <25000000>;
-		compatible = "arm,armv8-timer";
-	};
-
-	firmware {
-		optee {
-			compatible = "linaro,optee-tz";
-			method = "smc";
-		};
-	};
-
-	cv181x_cooling:cv181x_cooling {
-		clocks = <&clk CV181X_CLK_A53>, <&clk CV181X_CLK_TPU>;
-		clock-names = "clk_cpu", "clk_tpu_axi";
-		dev-freqs = <800000000 500000000>,
-			<400000000 375000000>,
-			<400000000 300000000>;
-		compatible = "cvitek,cv181x-cooling";
-		#cooling-cells = <2>;
-	};
-
-	tpu {
-		interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>,
-			     <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>;
-	};
-
-	mon {
-		interrupts = <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>;
-	};
-
-	wiegand0 {
-		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	wiegand1 {
-		interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	wiegand2 {
-		interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	saradc {
-		interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
-	};
-
-	rtc {
-		interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	sysdma_remap {
-		int_mux = <0x1FF>; /* enable bit [0..8] for CPU0(CA53) */
-	};
-
-	dmac: dma@0x4330000 {
-		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-#if 0
-	watchdog0: cv-wd@0x3010000 {
-		interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
-	};
-#endif
-	trng: dw_trng@0x02070000 {
-		reg = <0x0 0x02070000 0x0 0x1000>;
-		compatible = "snps,dw-trng";
-	};
-	
-	spinand:cv-spinf@4060000 {
-		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	spif:cvi-spif@10000000 {
-		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	spi0:spi0@04180000 {
-		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	spi1:spi1@04190000 {
-		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	spi2:spi2@041A0000 {
-		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	spi3:spi3@041B0000 {
-		interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	uart0: serial@04140000 {
-		interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	uart1: serial@04150000 {
-		interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	uart2: serial@04160000 {
-		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	uart3: serial@04170000 {
-		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	uart4: serial@041C0000 {
-		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	gpio0: gpio@03020000 {
-		porta: gpio-controller@0 {
-			interrupt-controller;
-			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
-		};
-	};
-
-	gpio1: gpio@03021000 {
-		portb: gpio-controller@1 {
-			interrupt-controller;
-			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
-		};
-	};
-
-	gpio2: gpio@03022000 {
-		portc: gpio-controller@2 {
-			interrupt-controller;
-			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
-		};
-	};
-
-	gpio3: gpio@03023000 {
-		portd: gpio-controller@3 {
-			interrupt-controller;
-			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
-		};
-	};
-
-	gpio4: gpio@05021000 {
-		porte: gpio-controller@4 {
-			interrupt-controller;
-			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
-		};
-	};
-
-	i2c0: i2c@04000000 {
-		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	i2c1: i2c@04010000 {
-		interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	i2c2: i2c@04020000 {
-		interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	i2c3: i2c@04030000 {
-		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	i2c4: i2c@04040000 {
-		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	ethernet0: ethernet@4070000 {
-		interrupt-names = "macirq";
-		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	emmc:cv-emmc@4300000 {
-		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	sd:cv-sd@4310000 {
-		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	i2s0: i2s@04100000 {
-		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	i2s1: i2s@04110000 {
-		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	i2s2: i2s@04120000 {
-		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	i2s3: i2s@04130000 {
-		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	wifisd:wifi-sd@4320000 {
-		interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	mipi_rx: cif {
-		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "csi0", "csi1";
-	};
-
-	vi {
-		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "isp";
-	};
-
-	ive {
-		interrupt-names = "ive_irq";
-		interrupts = <GIC_SPI 81 IRQ_TYPE_EDGE_RISING>;
-	};
-
-	vpss {
-		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "sc";
-	};
-
-	dwa {
-		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "dwa";
-	};
-
-	vcodec {
-		interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "h265","h264","sbm";
-	};
-
-	jpu {
-		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "jpeg";
-	};
-
-	rtos_cmdqu {
-		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "mailbox";
-	};
-
-	usb: usb@04340000 {
-		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	thermal:thermal@030E0000 {
-		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "tempsen";
-	};
-
-};
diff --git a/sys/contrib/device-tree/src/riscv/sophgo/cv181x_base_riscv.dtsi b/sys/contrib/device-tree/src/riscv/sophgo/cv181x_base_riscv.dtsi
deleted file mode 100644
index f21444c72b1a..000000000000
--- a/sys/contrib/device-tree/src/riscv/sophgo/cv181x_base_riscv.dtsi
+++ /dev/null
@@ -1,378 +0,0 @@
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/reset/cv181x-resets.h>
-#include <dt-bindings/clock/cv181x-clock.h>
-#include <dt-bindings/thermal/thermal.h>
-#include <dt-bindings/dma/cv181x-dmamap.h>
-#include "cv181x_base.dtsi"
-
-/ {
-	model = "Cvitek. CV181X ASIC. C906.";
-
-	#size-cells = <0x2>;
-	#address-cells = <0x2>;
-
-	cpus {
-		#address-cells = <0x01>;
-		#size-cells = <0x00>;
-		timebase-frequency = <25000000>;
-		u-boot,dm-spl;
-		cpu-map {
-			u-boot,dm-spl;
-			cluster0 {
-
-				core0 {
-					cpu = <0x01>;
-				};
-			};
-		};
-
-		cpu0: cpu@0 {
-			u-boot,dm-spl;
-			device_type = "cpu";
-			reg = <0x00>;
-			status = "okay";
-			compatible = "riscv";
-			riscv,isa = "rv64imafdvcsu";
-			mmu-type = "riscv,sv39";
-			clock-frequency = <25000000>;
-
-			cpu0_intc: interrupt-controller {
-				#interrupt-cells = <0x01>;
-				interrupt-controller;
-				compatible = "riscv,cpu-intc";
-			};
-		};
-	};
-
-	soc {
-		#address-cells = <0x02>;
-		#size-cells = <0x02>;
-		compatible = "simple-bus";
-		ranges;
-
-		plic0: interrupt-controller@70000000 {
-			riscv,ndev = <101>;
-			riscv,max-priority = <0x07>;
-			reg-names = "control";
-			reg = <0x00 0x70000000 0x00 0x4000000>;
-			interrupts-extended = <&cpu0_intc 0xffffffff &cpu0_intc 0x09>;
-			interrupt-controller;
-			compatible = "riscv,plic0";
-			#interrupt-cells = <0x02>;
-			#address-cells = <0x00>;
-		};
-
-		clint@74000000 {
-			interrupts-extended = <&cpu0_intc 0x03 &cpu0_intc 0x07>;
-			reg = <0x00 0x74000000 0x00 0x10000>;
-			compatible = "riscv,clint0";
-			clint,has-no-64bit-mmio;
-		};
-
-	};
-
-	cv181x_cooling:cv181x_cooling {
-		clocks = <&clk CV181X_CLK_C906_0>, <&clk CV181X_CLK_TPU>;
-		clock-names = "clk_cpu", "clk_tpu_axi";
-		dev-freqs = <850000000 500000000>,
-			<425000000 375000000>,
-			<425000000 300000000>;
-		compatible = "cvitek,cv181x-cooling";
-		#cooling-cells = <2>;
-	};
-
-	tpu {
-		interrupts = <75 IRQ_TYPE_LEVEL_HIGH>,
-				<76 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "tiu_irq", "tdma_irq";
-		interrupt-parent = <&plic0>;
-	};
-
-	mon {
-		interrupts = <93 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "mon_irq";
-		interrupt-parent = <&plic0>;
-	};
-
-	wiegand0 {
-		interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&plic0>;
-	};
-
-	wiegand1 {
-		interrupts = <65 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&plic0>;
-	};
-
-	wiegand2 {
-		interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&plic0>;
-	};
-
-	saradc {
-		interrupts = <100 IRQ_TYPE_EDGE_RISING>;
-		interrupt-parent = <&plic0>;
-	};
-
-	rtc {
-		interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&plic0>;
-	};
-
-	sysdma_remap {
-		int_mux = <0x7FC00>; /* enable bit [10..18] for CPU1(906B) */
-	};
-
-	dmac: dma@0x4330000 {
-		interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&plic0>;
-	};
-
-	watchdog0: cv-wd@0x3010000 {
-		interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
-	};
-	trng: dw_trng@0x02070000 {
-		reg = <0x0 0x02070000 0x0 0x1000>;
-		compatible = "snps,dw-trng";
-	};
-	spacc: cvi_spacc@02060000 {
-		interrupts = <91 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&plic0>;
-	};
-
-	spinand:cv-spinf@4060000 {
-		interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&plic0>;
-	};
-
-	spif:cvi-spif@10000000 {
-		interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&plic0>;
-	};
-
-	spi0:spi0@04180000 {
-		interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&plic0>;
-	};
-
-	spi1:spi1@04190000 {
-		interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&plic0>;
-	};
-
-	spi2:spi2@041A0000 {
-		interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&plic0>;
-	};
-
-	spi3:spi3@041B0000 {
-		interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&plic0>;
-	};
-
-	uart0: serial@04140000 {
-		interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&plic0>;
-	};
-
-	uart1: serial@04150000 {
-		interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&plic0>;
-	};
-
-	uart2: serial@04160000 {
-		interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&plic0>;
-	};
-
-	uart3: serial@04170000 {
-		interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&plic0>;
-	};
-
-	uart4: serial@041C0000 {
-		interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&plic0>;
-	};
-
-	gpio0: gpio@03020000 {
-		porta: gpio-controller@0 {
-			interrupt-controller;
-			interrupts = <60 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-parent = <&plic0>;
-		};
-	};
-
-	gpio1: gpio@03021000 {
-		portb: gpio-controller@1 {
-			interrupt-controller;
-			interrupts = <61 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-parent = <&plic0>;
-		};
-	};
-
-	gpio2: gpio@03022000 {
-		portc: gpio-controller@2 {
-			interrupt-controller;
-			interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-parent = <&plic0>;
-		};
-	};
-
-	gpio3: gpio@03023000 {
-		portd: gpio-controller@3 {
-			interrupt-controller;
-			interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-parent = <&plic0>;
-		};
-	};
-
-	gpio4: gpio@05021000 {
-		porte: gpio-controller@4 {
-			interrupt-controller;
-			interrupts = <70 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-parent = <&plic0>;
-		};
-	};
-
-	i2c0: i2c@04000000 {
-		interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&plic0>;
-	};
-
-	i2c1: i2c@04010000 {
-		interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&plic0>;
-	};
-
-	i2c2: i2c@04020000 {
-		interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&plic0>;
-	};
-
-	i2c3: i2c@04030000 {
-		interrupts = <52 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&plic0>;
-	};
-
-	i2c4: i2c@04040000 {
-		interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&plic0>;
-	};
-
-	ethernet0: ethernet@4070000 {
-		interrupt-names = "macirq";
-		interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&plic0>;
-	};
-
-	emmc:cv-emmc@4300000 {
-		interrupts = <34 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&plic0>;
-	};
-
-	sd:cv-sd@4310000 {
-		interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&plic0>;
-	};
-
-	i2s0: i2s@04100000 {
-		interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&plic0>;
-	};
-
-	i2s1: i2s@04110000 {
-		interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&plic0>;
-	};
-
-	i2s2: i2s@04120000 {
-		interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&plic0>;
-	};
-
-	i2s3: i2s@04130000 {
-		interrupts = <43 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&plic0>;
-	};
-
-	vi {
-		interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&plic0>;
-		interrupt-names = "isp";
-	};
-
-	vcodec {
-		interrupts = <22 IRQ_TYPE_LEVEL_HIGH>,
-			     <21 IRQ_TYPE_LEVEL_HIGH>,
-			     <23 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "h265","h264","sbm";
-		interrupt-parent = <&plic0>;
-	};
-
-	jpu {
-		interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "jpeg";
-		interrupt-parent = <&plic0>;
-	};
-
-	rtos_cmdqu {
-		interrupts = <101 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "mailbox";
-		interrupt-parent = <&plic0>;
-	};
-
-	wifisd:wifi-sd@4320000 {
-		interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&plic0>;
-	};
-
-	mipi_rx: cif {
-		interrupts = <26 IRQ_TYPE_LEVEL_HIGH>,
-			     <27 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "csi0", "csi1";
-		interrupt-parent = <&plic0>;
-	};
-
-	ive {
-		interrupt-names = "ive_irq";
-		interrupt-parent = <&plic0>;
-		interrupts = <97 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
-	vpss {
-		interrupts = <25 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "sc";
-		interrupt-parent = <&plic0>;
-	};
-
-	dwa {
-		interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "dwa";
-		interrupt-parent = <&plic0>;
-	};
-
-	usb: usb@04340000 {
-		interrupts = <30 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&plic0>;
-	};
-
-	thermal:thermal@030E0000 {
-		interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "tempsen";
-	};
-
-	chosen {
-		opensbi-domain{
-			compatible = "opensbi,dimain,config";
-
-			tdomain: trusted-domain {
-				compatible = "opensbi,domain,instance";
-				possible-harts = <&cpu0>;
-				system-suspend-allowed;
-			};
-		};
-	};	
-
-};
diff --git a/sys/contrib/device-tree/src/riscv/sophgo/cv181x_default_memmap.dtsi b/sys/contrib/device-tree/src/riscv/sophgo/cv181x_default_memmap.dtsi
deleted file mode 100644
index bb362511c57b..000000000000
--- a/sys/contrib/device-tree/src/riscv/sophgo/cv181x_default_memmap.dtsi
+++ /dev/null
@@ -1,25 +0,0 @@
-/ {
-	memory@80000000 {
-		device_type = "memory";
-		reg = <0x00 CVIMMAP_KERNEL_MEMORY_ADDR 0x00 CVIMMAP_KERNEL_MEMORY_SIZE>;
-	};
-
-
-	fast_image {
-		compatible = "cvitek,rtos_image";
-		reg-names = "rtos_region";
-		reg = <0x0 CVIMMAP_FREERTOS_ADDR 0x0 CVIMMAP_FREERTOS_SIZE>;
-		ion-size = <CVIMMAP_FREERTOS_RESERVED_ION_SIZE>;	//reserved ion size for freertos
-	};
-
-	reserved-memory {
-		#size-cells = <0x2>;
-		#address-cells = <0x2>;
-		ranges;
-
-		ion_reserved: ion {
-			compatible = "ion-region";
-			size = <0x0 CVIMMAP_ION_SIZE>;
-		};
-	};
-};
diff --git a/sys/contrib/device-tree/src/riscv/sophgo/sg2000_milkv_duos_glibc_arm64_emmc.dts b/sys/contrib/device-tree/src/riscv/sophgo/sg2000_milkv_duos_glibc_arm64_emmc.dts
deleted file mode 100644
index f06a08c43da6..000000000000
--- a/sys/contrib/device-tree/src/riscv/sophgo/sg2000_milkv_duos_glibc_arm64_emmc.dts
+++ /dev/null
@@ -1,108 +0,0 @@
-/dts-v1/;
-#include "cv181x_base_arm.dtsi"
-#include "cv181x_asic_bga.dtsi"
-#include "cv181x_asic_emmc.dtsi"
-
-/ {
-	model = "Milk-V DuoS";
-};
-
-&mipi_rx {
-	snsr-reset = <&porta 2 GPIO_ACTIVE_LOW>, <&porta 2 GPIO_ACTIVE_LOW>, <&porta 2 GPIO_ACTIVE_LOW>;
-};
-
-&i2c0 {
-	status = "disabled";
-};
-
-&i2c1 {
-	status = "okay";
-};
-
-&i2c2 {
-	status = "okay";
-};
-
-&i2c3 {
-	status = "okay";
-};
-
-&i2c4 {
-	status = "okay";
-
-	gt9xx: gt9xx@14 {
-		compatible = "goodix,gt9xx";
-		reg = <0x14>;
-		goodix,irq-gpio = <&porta 18 0>;
-		goodix,rst-gpio = <&porta 19 GPIO_ACTIVE_HIGH>;
-		status = "okay";
-	};
-};
-
-&spi3 {
-	status = "okay";
-
-	spidev@0 {
-		status = "okay";
-	};
-};
-
-&dac {
-	/delete-property/ mute-gpio-l;
-	/delete-property/ mute-gpio-r;
-};
-
-/* mipi dsi for u-boot */
-&vo {
-	compatible = "cvitek,vo";
-	reset-gpio = <&porte 2 GPIO_ACTIVE_LOW>;
-	pwm-gpio = <&porte 0 GPIO_ACTIVE_HIGH>;
-	power-ct-gpio = <&porte 1 GPIO_ACTIVE_HIGH>;
-	status = "okay";
-};
-
-/* mipi dsi for kernel */
-&mipi_tx {
-	compatible = "cvitek,mipi_tx";
-	reset-gpio = <&porte 2 GPIO_ACTIVE_LOW>;
-	pwm-gpio = <&porte 0 GPIO_ACTIVE_HIGH>;
-	power-ct-gpio = <&porte 1 GPIO_ACTIVE_HIGH>;
-	status = "okay";
-};
-
-&wifisd {
-	status = "okay";
-	cap-sd-highspeed;
-	sd-uhs-sdr25;
-	sd-uhs-ddr50;
-	sd-uhs-sdr104;
-	min-frequency = <400000>;
-	max-frequency = <187500000>;
-};
-
-&wifi_pin {
-	status = "okay";
-	compatible = "cvitek,wifi-pin";
-	poweron-gpio = <&porta 15 GPIO_ACTIVE_HIGH>;
-	wakeup-gpio = <&porte 7 GPIO_ACTIVE_HIGH>;
-};
-
-&usb {
-	vbus-gpio = <&portb 6 0>;
-};
-
-&uart1 {
-	status = "okay";
-};
-
-&uart2 {
-	status = "okay";
-};
-
-&uart3 {
-	status = "okay";
-};
-
-&uart4 {
-	status = "okay";
-};
diff --git a/sys/contrib/device-tree/src/riscv/sophgo/sg2000_milkv_duos_glibc_arm64_sd.dts b/sys/contrib/device-tree/src/riscv/sophgo/sg2000_milkv_duos_glibc_arm64_sd.dts
deleted file mode 100644
index d4decec7a53e..000000000000
--- a/sys/contrib/device-tree/src/riscv/sophgo/sg2000_milkv_duos_glibc_arm64_sd.dts
+++ /dev/null
@@ -1,112 +0,0 @@
-/dts-v1/;
-#include "cv181x_base_arm.dtsi"
-#include "cv181x_asic_bga.dtsi"
-#include "cv181x_asic_sd.dtsi"
-
-/ {
-	model = "Milk-V DuoS";
-
-	sd:cv-sd@4310000 {
-		max-frequency = <10000000>;
-	};
-};
-
-&mipi_rx {
-	snsr-reset = <&porta 2 GPIO_ACTIVE_LOW>, <&porta 2 GPIO_ACTIVE_LOW>, <&porta 2 GPIO_ACTIVE_LOW>;
-};
-
-&i2c0 {
-	status = "disabled";
-};
-
-&i2c1 {
-	status = "okay";
-};
-
-&i2c2 {
-	status = "okay";
-};
-
-&i2c3 {
-	status = "okay";
-};
-
-&i2c4 {
-	status = "okay";
-
-	gt9xx: gt9xx@14 {
-		compatible = "goodix,gt9xx";
-		reg = <0x14>;
-		goodix,irq-gpio = <&porta 18 0>;
-		goodix,rst-gpio = <&porta 19 GPIO_ACTIVE_HIGH>;
-		status = "okay";
-	};
-};
-
-&spi3 {
-	status = "okay";
-
-	spidev@0 {
-		status = "okay";
-	};
-};
-
-&dac {
-	/delete-property/ mute-gpio-l;
-	/delete-property/ mute-gpio-r;
-};
-
-/* mipi dsi for u-boot */
-&vo {
-	compatible = "cvitek,vo";
-	reset-gpio = <&porte 2 GPIO_ACTIVE_LOW>;
-	pwm-gpio = <&porte 0 GPIO_ACTIVE_HIGH>;
-	power-ct-gpio = <&porte 1 GPIO_ACTIVE_HIGH>;
-	status = "okay";
-};
-
-/* mipi dsi for kernel */
-&mipi_tx {
-	compatible = "cvitek,mipi_tx";
-	reset-gpio = <&porte 2 GPIO_ACTIVE_LOW>;
-	pwm-gpio = <&porte 0 GPIO_ACTIVE_HIGH>;
-	power-ct-gpio = <&porte 1 GPIO_ACTIVE_HIGH>;
-	status = "okay";
-};
-
-&wifisd {
-	status = "okay";
-	cap-sd-highspeed;
-	sd-uhs-sdr25;
-	sd-uhs-ddr50;
-	sd-uhs-sdr104;
-	min-frequency = <400000>;
-	max-frequency = <187500000>;
-};
-
-&wifi_pin {
-	status = "okay";
-	compatible = "cvitek,wifi-pin";
-	poweron-gpio = <&porta 15 GPIO_ACTIVE_HIGH>;
-	wakeup-gpio = <&porte 7 GPIO_ACTIVE_HIGH>;
-};
-
-&usb {
-	vbus-gpio = <&portb 6 0>;
-};
-
-&uart1 {
-	status = "okay";
-};
-
-&uart2 {
-	status = "okay";
-};
-
-&uart3 {
-	status = "okay";
-};
-
-&uart4 {
-	status = "okay";
-};
diff --git a/sys/contrib/device-tree/src/riscv/sophgo/sg2000_milkv_duos_musl_riscv64_emmc.dts b/sys/contrib/device-tree/src/riscv/sophgo/sg2000_milkv_duos_musl_riscv64_emmc.dts
deleted file mode 100644
index 5b28bbd087c7..000000000000
--- a/sys/contrib/device-tree/src/riscv/sophgo/sg2000_milkv_duos_musl_riscv64_emmc.dts
+++ /dev/null
@@ -1,108 +0,0 @@
-/dts-v1/;
-#include "cv181x_base_riscv.dtsi"
-#include "cv181x_asic_bga.dtsi"
-#include "cv181x_asic_emmc.dtsi"
-
-/ {
-	model = "Milk-V DuoS";
-};
-
-&mipi_rx {
-	snsr-reset = <&porta 2 GPIO_ACTIVE_LOW>, <&porta 2 GPIO_ACTIVE_LOW>, <&porta 2 GPIO_ACTIVE_LOW>;
-};
-
-&i2c0 {
-	status = "disabled";
-};
-
-&i2c1 {
-	status = "okay";
-};
-
-&i2c2 {
-	status = "okay";
-};
-
-&i2c3 {
-	status = "okay";
-};
-
-&i2c4 {
-	status = "okay";
-
-	gt9xx: gt9xx@14 {
-		compatible = "goodix,gt9xx";
-		reg = <0x14>;
-		goodix,irq-gpio = <&porta 18 0>;
-		goodix,rst-gpio = <&porta 19 GPIO_ACTIVE_HIGH>;
-		status = "okay";
-	};
-};
-
-&spi3 {
-	status = "okay";
-
-	spidev@0 {
-		status = "okay";
-	};
-};
-
-&dac {
-	/delete-property/ mute-gpio-l;
-	/delete-property/ mute-gpio-r;
-};
-
-/* mipi dsi for u-boot */
-&vo {
-	compatible = "cvitek,vo";
-	reset-gpio = <&porte 2 GPIO_ACTIVE_LOW>;
-	pwm-gpio = <&porte 0 GPIO_ACTIVE_HIGH>;
-	power-ct-gpio = <&porte 1 GPIO_ACTIVE_HIGH>;
-	status = "okay";
-};
-
-/* mipi dsi for kernel */
-&mipi_tx {
-	compatible = "cvitek,mipi_tx";
-	reset-gpio = <&porte 2 GPIO_ACTIVE_LOW>;
-	pwm-gpio = <&porte 0 GPIO_ACTIVE_HIGH>;
-	power-ct-gpio = <&porte 1 GPIO_ACTIVE_HIGH>;
-	status = "okay";
-};
-
-&wifisd {
-	status = "okay";
-	cap-sd-highspeed;
-	sd-uhs-sdr25;
-	sd-uhs-ddr50;
-	sd-uhs-sdr104;
-	min-frequency = <400000>;
-	max-frequency = <187500000>;
-};
-
-&wifi_pin {
-	status = "okay";
-	compatible = "cvitek,wifi-pin";
-	poweron-gpio = <&porta 15 GPIO_ACTIVE_HIGH>;
-	wakeup-gpio = <&porte 7 GPIO_ACTIVE_HIGH>;
-};
-
-&usb {
-	vbus-gpio = <&portb 6 0>;
-};
-
-&uart1 {
-	status = "okay";
-};
-
-&uart2 {
-	status = "okay";
-};
-
-&uart3 {
-	status = "okay";
-};
-
-&uart4 {
-	status = "okay";
-};
diff --git a/sys/contrib/device-tree/src/riscv/sophgo/sg2000_milkv_duos_musl_riscv64_sd.dts b/sys/contrib/device-tree/src/riscv/sophgo/sg2000_milkv_duos_musl_riscv64_sd.dts
deleted file mode 100644
index af3d56ff3903..000000000000
--- a/sys/contrib/device-tree/src/riscv/sophgo/sg2000_milkv_duos_musl_riscv64_sd.dts
+++ /dev/null
@@ -1,108 +0,0 @@
-/dts-v1/;
-#include "cv181x_base_riscv.dtsi"
-#include "cv181x_asic_bga.dtsi"
-#include "cv181x_asic_sd.dtsi"
-
-/ {
-	model = "Milk-V DuoS";
-};
-
-&mipi_rx {
-	snsr-reset = <&porta 2 GPIO_ACTIVE_LOW>, <&porta 2 GPIO_ACTIVE_LOW>, <&porta 2 GPIO_ACTIVE_LOW>;
-};
-
-&i2c0 {
-	status = "disabled";
-};
-
-&i2c1 {
-	status = "okay";
-};
-
-&i2c2 {
-	status = "okay";
-};
-
-&i2c3 {
-	status = "okay";
-};
-
-&i2c4 {
-	status = "okay";
-
-	gt9xx: gt9xx@14 {
-		compatible = "goodix,gt9xx";
-		reg = <0x14>;
-		goodix,irq-gpio = <&porta 18 0>;
-		goodix,rst-gpio = <&porta 19 GPIO_ACTIVE_HIGH>;
-		status = "okay";
-	};
-};
-
-&spi3 {
-	status = "okay";
-
-	spidev@0 {
-		status = "okay";
-	};
-};
-
-&dac {
-	/delete-property/ mute-gpio-l;
-	/delete-property/ mute-gpio-r;
-};
-
-/* mipi dsi for u-boot */
-&vo {
-	compatible = "cvitek,vo";
-	reset-gpio = <&porte 2 GPIO_ACTIVE_LOW>;
-	pwm-gpio = <&porte 0 GPIO_ACTIVE_HIGH>;
-	power-ct-gpio = <&porte 1 GPIO_ACTIVE_HIGH>;
-	status = "okay";
-};
-
-/* mipi dsi for kernel */
-&mipi_tx {
-	compatible = "cvitek,mipi_tx";
-	reset-gpio = <&porte 2 GPIO_ACTIVE_LOW>;
-	pwm-gpio = <&porte 0 GPIO_ACTIVE_HIGH>;
-	power-ct-gpio = <&porte 1 GPIO_ACTIVE_HIGH>;
-	status = "okay";
-};
-
-&wifisd {
-	status = "okay";
-	cap-sd-highspeed;
-	sd-uhs-sdr25;
-	sd-uhs-ddr50;
-	sd-uhs-sdr104;
-	min-frequency = <400000>;
-	max-frequency = <187500000>;
-};
-
-&wifi_pin {
-	status = "okay";
-	compatible = "cvitek,wifi-pin";
-	poweron-gpio = <&porta 15 GPIO_ACTIVE_HIGH>;
-	wakeup-gpio = <&porte 7 GPIO_ACTIVE_HIGH>;
-};
-
-&usb {
-	vbus-gpio = <&portb 6 0>;
-};
-
-&uart1 {
-	status = "okay";
-};
-
-&uart2 {
-	status = "okay";
-};
-
-&uart3 {
-	status = "okay";
-};
-
-&uart4 {
-	status = "okay";
-};
diff --git a/sys/contrib/device-tree/src/riscv/sophgo/sg2000_wevb_arm64_sd.dts b/sys/contrib/device-tree/src/riscv/sophgo/sg2000_wevb_arm64_sd.dts
deleted file mode 100644
index 0eac8fbd4a8a..000000000000
--- a/sys/contrib/device-tree/src/riscv/sophgo/sg2000_wevb_arm64_sd.dts
+++ /dev/null
@@ -1,13 +0,0 @@
-/dts-v1/;
-#include "cv181x_base_arm.dtsi"
-#include "cv181x_asic_bga.dtsi"
-#include "cv181x_asic_sd.dtsi"
-#include "cv181x_default_memmap.dtsi"
-
-/ {
-
-	sd:cv-sd@4310000 {
-		max-frequency = <10000000>;
-	};
-};
-
diff --git a/sys/contrib/device-tree/src/riscv/sophgo/sg2000_wevb_riscv64_sd.dts b/sys/contrib/device-tree/src/riscv/sophgo/sg2000_wevb_riscv64_sd.dts
deleted file mode 100644
index 9b649d734853..000000000000
--- a/sys/contrib/device-tree/src/riscv/sophgo/sg2000_wevb_riscv64_sd.dts
+++ /dev/null
@@ -1,10 +0,0 @@
-/dts-v1/;
-#include "cv181x_base_riscv.dtsi"
-#include "cv181x_asic_bga.dtsi"
-#include "cv181x_asic_sd.dtsi"
-#include "cv181x_default_memmap.dtsi"
-
-/ {
-
-};
-
diff --git a/sys/modules/dtb/sophgo/Makefile b/sys/modules/dtb/sophgo/Makefile
deleted file mode 100644
index 89a1834bfa8f..000000000000
--- a/sys/modules/dtb/sophgo/Makefile
+++ /dev/null
@@ -1,15 +0,0 @@
-.if ${MACHINE_ARCH} == "aarch64"
-DTS=	\
-	sophgo/sg2000_milkv_duos_glibc_arm64_emmc.dts \
-	sophgo/sg2000_milkv_duos_glibc_arm64_sd.dts \
-	sophgo/sg2000_wevb_arm64_sd.dts
-
-.elif ${MACHINE_ARCH} == "riscv"
-DTS=	\
-	sophgo/sg2000_milkv_duos_musl_riscv64_emmc.dts \
-	sophgo/sg2000_milkv_duos_musl_riscv64_sd.dts \
-	sophgo/sg2000_wevb_riscv64_sd.dts
-
-.endif
-
-.include <bsd.dtb.mk>
diff --git a/sys/riscv/conf/GENERIC b/sys/riscv/conf/GENERIC
index 8f9a5e1aec63..7a2c88c0b4cb 100644
--- a/sys/riscv/conf/GENERIC
+++ b/sys/riscv/conf/GENERIC
@@ -220,4 +220,3 @@ include		"std.cvitek"
 include		"std.eswin"
 include		"std.sifive"
 include		"std.starfive"
-include		"std.sophgo"
diff --git a/sys/riscv/conf/std.sophgo b/sys/riscv/conf/std.sophgo
deleted file mode 100644
index bcb9a4426acb..000000000000
--- a/sys/riscv/conf/std.sophgo
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Sophgo SoC support
-#
-
-# DTBs
-makeoptions	MODULES_EXTRA+="dtb/sophgo"
-
-files		"../sophgo/files.sophgo"
diff --git a/sys/riscv/sophgo/files.sophgo b/sys/riscv/sophgo/files.sophgo
deleted file mode 100644
index 1ce0e7a190df..000000000000
--- a/sys/riscv/sophgo/files.sophgo
+++ /dev/null
@@ -1,2 +0,0 @@
-dev/dwc/if_dwc_cvitek.c			optional fdt dwc_cvitek
-dev/sdhci/sdhci_fdt_cvitek.c		optional fdt sdhci sdhci_cvitek regulator
\ No newline at end of file