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authorRuslan Bukin <br@FreeBSD.org>2017-11-17 17:54:10 +0000
committerRuslan Bukin <br@FreeBSD.org>2017-11-17 17:54:10 +0000
commit3b418d1b9a4a846fac2502e56d1edad13f7c9dd7 (patch)
tree908e0f192b0849c096d9c08ce542f4e6f22e505b
parent41edb6080c7e7f1d0356d527a159262dc00d7dbf (diff)
downloadsrc-3b418d1b9a4a846fac2502e56d1edad13f7c9dd7.tar.gz
src-3b418d1b9a4a846fac2502e56d1edad13f7c9dd7.zip
Add Intel Processor Trace registers for:
- CPUID - Table of Physical Addresses (ToPA). Sponsored by: DARPA, AFRL
Notes
Notes: svn path=/head/; revision=325952
-rw-r--r--sys/x86/include/specialreg.h52
1 files changed, 52 insertions, 0 deletions
diff --git a/sys/x86/include/specialreg.h b/sys/x86/include/specialreg.h
index 39d511330669..e56cc474666a 100644
--- a/sys/x86/include/specialreg.h
+++ b/sys/x86/include/specialreg.h
@@ -188,6 +188,35 @@
#define CPUTPM1_ARAT 0x00000004
#define CPUTPM2_EFFREQ 0x00000001
+/* Intel Processor Trace CPUID. */
+
+/* Leaf 0 ebx. */
+#define CPUPT_CR3 (1 << 0) /* CR3 Filtering Support */
+#define CPUPT_PSB (1 << 1) /* Configurable PSB and Cycle-Accurate Mode Supported */
+#define CPUPT_IPF (1 << 2) /* IP Filtering and TraceStop supported */
+#define CPUPT_MTC (1 << 3) /* MTC Supported */
+#define CPUPT_PRW (1 << 4) /* PTWRITE Supported */
+#define CPUPT_PWR (1 << 5) /* Power Event Trace Supported */
+
+/* Leaf 0 ecx. */
+#define CPUPT_TOPA (1 << 0) /* ToPA Output Supported */
+#define CPUPT_TOPA_MULTI (1 << 1) /* ToPA Tables Allow Multiple Output Entries */
+#define CPUPT_SINGLE (1 << 2) /* Single-Range Output Supported */
+#define CPUPT_TT_OUT (1 << 3) /* Output to Trace Transport Subsystem Supported */
+#define CPUPT_LINEAR_IP (1 << 31) /* IP Payloads are Linear IP, otherwise IP is effective */
+
+/* Leaf 1 eax. */
+#define CPUPT_NADDR_S 0 /* Number of Address Ranges */
+#define CPUPT_NADDR_M (0x7 << CPUPT_NADDR_S)
+#define CPUPT_MTC_BITMAP_S 16 /* Bitmap of supported MTC Period Encodings */
+#define CPUPT_MTC_BITMAP_M (0xffff << CPUPT_MTC_BITMAP_S)
+
+/* Leaf 1 ebx. */
+#define CPUPT_CT_BITMAP_S 0 /* Bitmap of supported Cycle Threshold values */
+#define CPUPT_CT_BITMAP_M (0xffff << CPUPT_CT_BITMAP_S)
+#define CPUPT_PFE_BITMAP_S 16 /* Bitmap of supported Configurable PSB Frequency encoding */
+#define CPUPT_PFE_BITMAP_M (0xffff << CPUPT_PFE_BITMAP_S)
+
/*
* Important bits in the AMD extended cpuid flags
*/
@@ -602,6 +631,29 @@
#define MSR_IA32_RTIT_ADDR3_A 0x586 /* Region 3 Start Address (R/W) */
#define MSR_IA32_RTIT_ADDR3_B 0x587 /* Region 3 End Address (R/W) */
+/* Intel Processor Trace Table of Physical Addresses (ToPA). */
+#define TOPA_SIZE_S 6
+#define TOPA_SIZE_M (0xf << TOPA_SIZE_S)
+#define TOPA_SIZE_4K (0 << TOPA_SIZE_S)
+#define TOPA_SIZE_8K (1 << TOPA_SIZE_S)
+#define TOPA_SIZE_16K (2 << TOPA_SIZE_S)
+#define TOPA_SIZE_32K (3 << TOPA_SIZE_S)
+#define TOPA_SIZE_64K (4 << TOPA_SIZE_S)
+#define TOPA_SIZE_128K (5 << TOPA_SIZE_S)
+#define TOPA_SIZE_256K (6 << TOPA_SIZE_S)
+#define TOPA_SIZE_512K (7 << TOPA_SIZE_S)
+#define TOPA_SIZE_1M (8 << TOPA_SIZE_S)
+#define TOPA_SIZE_2M (9 << TOPA_SIZE_S)
+#define TOPA_SIZE_4M (10 << TOPA_SIZE_S)
+#define TOPA_SIZE_8M (11 << TOPA_SIZE_S)
+#define TOPA_SIZE_16M (12 << TOPA_SIZE_S)
+#define TOPA_SIZE_32M (13 << TOPA_SIZE_S)
+#define TOPA_SIZE_64M (14 << TOPA_SIZE_S)
+#define TOPA_SIZE_128M (15 << TOPA_SIZE_S)
+#define TOPA_STOP (1 << 4)
+#define TOPA_INT (1 << 2)
+#define TOPA_END (1 << 0)
+
/*
* Constants related to MSR's.
*/