sfxge: add 7xxx NICs family support

Support 7xxx adapters including firmware-assisted TSO and VLAN tagging:

  - Solarflare Flareon Ultra 7000 series 10/40G adapters:
    - Solarflare SFN7042Q QSFP+ Server Adapter
    - Solarflare SFN7142Q QSFP+ Server Adapter

  - Solarflare Flareon Ultra 7000 series 10G adapters:
    - Solarflare SFN7022F SFP+ Server Adapter
    - Solarflare SFN7122F SFP+ Server Adapter
    - Solarflare SFN7322F Precision Time Synchronization Server Adapter

  - Solarflare Flareon 7000 series 10G adapters:
    - Solarflare SFN7002F SFP+ Server Adapter

Support utilities to configure adapters and update firmware.

The work is done by Solarflare developers
(Andy Moreton, Andrew Lee and many others),
Artem V. Andreev <Artem.Andreev at oktetlabs.ru> and me.

Sponsored by:   Solarflare Communications, Inc.
MFC after:      2 weeks
Causually read by: gnn
Differential Revision: https://reviews.freebsd.org/D2618

73 files changed, 32780 insertions, 6471 deletions

diff --git a/share/man/man4/sfxge.4 b/share/man/man4/sfxge.4
index c745368ead16..462b62062a8d 100644
--- a/share/man/man4/sfxge.4
+++ b/share/man/man4/sfxge.4
@@ -1,26 +1,30 @@
-.\" Copyright (c) 2011 Solarflare Communications, Inc.
+.\" Copyright (c) 2011-2015 Solarflare Communications Inc.
 .\" All rights reserved.
 .\"
 .\" Redistribution and use in source and binary forms, with or without
-.\" modification, are permitted provided that the following conditions
-.\" are met:
-.\" 1. Redistributions of source code must retain the above copyright
-.\"    notice, this list of conditions and the following disclaimer.
-.\" 2. Redistributions in binary form must reproduce the above copyright
-.\"    notice, this list of conditions and the following disclaimer in the
-.\"    documentation and/or other materials provided with the distribution.
+.\" modification, are permitted provided that the following conditions are met:
 .\"
-.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
-.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-.\" ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
-.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
-.\" SUCH DAMAGE.
+.\" 1. Redistributions of source code must retain the above copyright notice,
+.\"    this list of conditions and the following disclaimer.
+.\" 2. Redistributions in binary form must reproduce the above copyright notice,
+.\"    this list of conditions and the following disclaimer in the documentation
+.\"    and/or other materials provided with the distribution.
+.\"
+.\" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+.\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+.\" THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+.\" PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+.\" CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+.\" EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+.\" PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+.\" OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+.\" WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+.\" OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+.\" EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+.\"
+.\" The views and conclusions contained in the software and documentation are
+.\" those of the authors and should not be interpreted as representing official
+.\" policies, either expressed or implied, of the FreeBSD Project.
 .\"
 .\" $FreeBSD$
 .\"
@@ -116,6 +120,9 @@ If a packet is dropped, the
 .Va tx_put_overflow
 counter is incremented and the local sender receives ENOBUFS.
 The value must be greater than or equal to 0.
+.It Va hw.sfxge.tso_fw_assisted
+Enable/disable usage of FW-assisted TSO if supported by NIC firmware.
+Enabled by default.
 .It Va hw.sfxge.N.max_rss_channels
 The maximum number of allocated RSS channels for the Nth adapter.
 If set to 0 or unset, the number of channels is determined by the number
diff --git a/sys/conf/files b/sys/conf/files
index 8d51fe55e9c5..0a63a1c2dd2d 100644
--- a/sys/conf/files
+++ b/sys/conf/files
@@ -2156,37 +2156,6 @@ dev/sdhci/sdhci.c		optional sdhci
 dev/sdhci/sdhci_if.m		optional sdhci
 dev/sdhci/sdhci_pci.c		optional sdhci pci
 dev/sf/if_sf.c			optional sf pci
-dev/sfxge/common/efx_bootcfg.c	optional sfxge pci
-dev/sfxge/common/efx_ev.c	optional sfxge pci
-dev/sfxge/common/efx_filter.c	optional sfxge pci
-dev/sfxge/common/efx_intr.c	optional sfxge pci
-dev/sfxge/common/efx_mac.c	optional sfxge pci
-dev/sfxge/common/efx_mcdi.c	optional sfxge pci
-dev/sfxge/common/efx_mon.c	optional sfxge pci
-dev/sfxge/common/efx_nic.c	optional sfxge pci
-dev/sfxge/common/efx_nvram.c	optional sfxge pci
-dev/sfxge/common/efx_phy.c	optional sfxge pci
-dev/sfxge/common/efx_port.c	optional sfxge pci
-dev/sfxge/common/efx_rx.c	optional sfxge pci
-dev/sfxge/common/efx_sram.c	optional sfxge pci
-dev/sfxge/common/efx_tx.c	optional sfxge pci
-dev/sfxge/common/efx_vpd.c	optional sfxge pci
-dev/sfxge/common/efx_wol.c	optional sfxge pci
-dev/sfxge/common/siena_mac.c	optional sfxge pci
-dev/sfxge/common/siena_mon.c	optional sfxge pci
-dev/sfxge/common/siena_nic.c	optional sfxge pci
-dev/sfxge/common/siena_nvram.c	optional sfxge pci
-dev/sfxge/common/siena_phy.c	optional sfxge pci
-dev/sfxge/common/siena_sram.c	optional sfxge pci
-dev/sfxge/common/siena_vpd.c	optional sfxge pci
-dev/sfxge/sfxge.c		optional sfxge pci
-dev/sfxge/sfxge_dma.c		optional sfxge pci
-dev/sfxge/sfxge_ev.c		optional sfxge pci
-dev/sfxge/sfxge_intr.c		optional sfxge pci
-dev/sfxge/sfxge_mcdi.c		optional sfxge pci
-dev/sfxge/sfxge_port.c		optional sfxge pci
-dev/sfxge/sfxge_rx.c		optional sfxge pci
-dev/sfxge/sfxge_tx.c		optional sfxge pci
 dev/sge/if_sge.c		optional sge pci
 dev/si/si.c			optional si
 dev/si/si2_z280.c		optional si
diff --git a/sys/conf/files.amd64 b/sys/conf/files.amd64
index eae8bc66954f..f1a4e97a25aa 100644
--- a/sys/conf/files.amd64
+++ b/sys/conf/files.amd64
@@ -304,37 +304,52 @@ dev/qlxgbe/ql_isr.c		optional	qlxgbe pci
 dev/qlxgbe/ql_misc.c		optional	qlxgbe pci
 dev/qlxgbe/ql_os.c		optional	qlxgbe pci
 dev/qlxgbe/ql_reset.c		optional	qlxgbe pci
-dev/sfxge/common/efx_bootcfg.c	optional sfxge inet pci
-dev/sfxge/common/efx_ev.c	optional sfxge inet pci
-dev/sfxge/common/efx_filter.c	optional sfxge inet pci
-dev/sfxge/common/efx_intr.c	optional sfxge inet pci
-dev/sfxge/common/efx_mac.c	optional sfxge inet pci
-dev/sfxge/common/efx_mcdi.c	optional sfxge inet pci
-dev/sfxge/common/efx_mon.c	optional sfxge inet pci
-dev/sfxge/common/efx_nic.c	optional sfxge inet pci
-dev/sfxge/common/efx_nvram.c	optional sfxge inet pci
-dev/sfxge/common/efx_phy.c	optional sfxge inet pci
-dev/sfxge/common/efx_port.c	optional sfxge inet pci
-dev/sfxge/common/efx_rx.c	optional sfxge inet pci
-dev/sfxge/common/efx_sram.c	optional sfxge inet pci
-dev/sfxge/common/efx_tx.c	optional sfxge inet pci
-dev/sfxge/common/efx_vpd.c	optional sfxge inet pci
-dev/sfxge/common/efx_wol.c	optional sfxge inet pci
-dev/sfxge/common/siena_mac.c	optional sfxge inet pci
-dev/sfxge/common/siena_mon.c	optional sfxge inet pci
-dev/sfxge/common/siena_nic.c	optional sfxge inet pci
-dev/sfxge/common/siena_nvram.c	optional sfxge inet pci
-dev/sfxge/common/siena_phy.c	optional sfxge inet pci
-dev/sfxge/common/siena_sram.c	optional sfxge inet pci
-dev/sfxge/common/siena_vpd.c	optional sfxge inet pci
-dev/sfxge/sfxge.c		optional sfxge inet pci
-dev/sfxge/sfxge_dma.c		optional sfxge inet pci
-dev/sfxge/sfxge_ev.c		optional sfxge inet pci
-dev/sfxge/sfxge_intr.c		optional sfxge inet pci
-dev/sfxge/sfxge_mcdi.c		optional sfxge inet pci
-dev/sfxge/sfxge_port.c		optional sfxge inet pci
-dev/sfxge/sfxge_rx.c		optional sfxge inet pci
-dev/sfxge/sfxge_tx.c		optional sfxge inet pci
+dev/sfxge/common/efx_bootcfg.c	optional	sfxge pci
+dev/sfxge/common/efx_crc32.c	optional	sfxge pci
+dev/sfxge/common/efx_ev.c	optional	sfxge pci
+dev/sfxge/common/efx_filter.c	optional	sfxge pci
+dev/sfxge/common/efx_hash.c	optional	sfxge pci
+dev/sfxge/common/efx_intr.c	optional	sfxge pci
+dev/sfxge/common/efx_mac.c	optional	sfxge pci
+dev/sfxge/common/efx_mcdi.c	optional	sfxge pci
+dev/sfxge/common/efx_mon.c	optional	sfxge pci
+dev/sfxge/common/efx_nic.c	optional	sfxge pci
+dev/sfxge/common/efx_nvram.c	optional	sfxge pci
+dev/sfxge/common/efx_phy.c	optional	sfxge pci
+dev/sfxge/common/efx_port.c	optional	sfxge pci
+dev/sfxge/common/efx_rx.c	optional	sfxge pci
+dev/sfxge/common/efx_sram.c	optional	sfxge pci
+dev/sfxge/common/efx_tx.c	optional	sfxge pci
+dev/sfxge/common/efx_vpd.c	optional	sfxge pci
+dev/sfxge/common/efx_wol.c	optional	sfxge pci
+dev/sfxge/common/hunt_ev.c	optional	sfxge pci
+dev/sfxge/common/hunt_filter.c	optional	sfxge pci
+dev/sfxge/common/hunt_intr.c	optional	sfxge pci
+dev/sfxge/common/hunt_mac.c	optional	sfxge pci
+dev/sfxge/common/hunt_mcdi.c	optional	sfxge pci
+dev/sfxge/common/hunt_nic.c	optional	sfxge pci
+dev/sfxge/common/hunt_nvram.c	optional	sfxge pci
+dev/sfxge/common/hunt_phy.c	optional	sfxge pci
+dev/sfxge/common/hunt_rx.c	optional	sfxge pci
+dev/sfxge/common/hunt_sram.c	optional	sfxge pci
+dev/sfxge/common/hunt_tx.c	optional	sfxge pci
+dev/sfxge/common/hunt_vpd.c	optional	sfxge pci
+dev/sfxge/common/siena_mac.c	optional	sfxge pci
+dev/sfxge/common/siena_mcdi.c	optional	sfxge pci
+dev/sfxge/common/siena_nic.c	optional	sfxge pci
+dev/sfxge/common/siena_nvram.c	optional	sfxge pci
+dev/sfxge/common/siena_phy.c	optional	sfxge pci
+dev/sfxge/common/siena_sram.c	optional	sfxge pci
+dev/sfxge/common/siena_vpd.c	optional	sfxge pci
+dev/sfxge/sfxge.c		optional	sfxge pci
+dev/sfxge/sfxge_dma.c		optional	sfxge pci
+dev/sfxge/sfxge_ev.c		optional	sfxge pci
+dev/sfxge/sfxge_intr.c		optional	sfxge pci
+dev/sfxge/sfxge_mcdi.c		optional	sfxge pci
+dev/sfxge/sfxge_nvram.c		optional	sfxge pci
+dev/sfxge/sfxge_port.c		optional	sfxge pci
+dev/sfxge/sfxge_rx.c		optional	sfxge pci
+dev/sfxge/sfxge_tx.c		optional	sfxge pci
 dev/sio/sio.c			optional	sio
 dev/sio/sio_isa.c		optional	sio isa
 dev/sio/sio_pccard.c		optional	sio pccard
diff --git a/sys/dev/sfxge/common/ef10_tlv_layout.h b/sys/dev/sfxge/common/ef10_tlv_layout.h
new file mode 100644
index 000000000000..e413a5d8c70b
--- /dev/null
+++ b/sys/dev/sfxge/common/ef10_tlv_layout.h
@@ -0,0 +1,691 @@
+/*-
+ * Copyright (c) 2012-2015 Solarflare Communications Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are
+ * those of the authors and should not be interpreted as representing official
+ * policies, either expressed or implied, of the FreeBSD Project.
+ *
+ * $FreeBSD$
+ */
+
+/* These structures define the layouts for the TLV items stored in static and
+ * dynamic configuration partitions in NVRAM for EF10 (Huntington etc.).
+ *
+ * They contain the same sort of information that was kept in the
+ * siena_mc_static_config_hdr_t and siena_mc_dynamic_config_hdr_t structures
+ * (defined in <ci/mgmt/mc_flash_layout.h> and <ci/mgmt/mc_dynamic_cfg.h>) for
+ * Siena.
+ *
+ * These are used directly by the MC and should also be usable directly on host
+ * systems which are little-endian and do not do strange things with structure
+ * padding.  (Big-endian host systems will require some byte-swapping.)
+ *
+ *                                    -----
+ *
+ * Please refer to SF-108797-SW for a general overview of the TLV partition
+ * format.
+ *
+ *                                    -----
+ *
+ * The current tag IDs have a general structure: with the exception of the
+ * special values defined in the document, they are of the form 0xLTTTNNNN,
+ * where:
+ *
+ *   -  L is a location, indicating where this tag is expected to be found:
+ *      0 for static configuration, or 1 for dynamic configuration.   Other
+ *      values are reserved.
+ *
+ *   -  TTT is a type, which is just a unique value.  The same type value
+ *      might appear in both locations, indicating a relationship between
+ *      the items (e.g. static and dynamic VPD below).
+ *
+ *   -  NNNN is an index of some form.  Some item types are per-port, some
+ *      are per-PF, some are per-partition-type.
+ *
+ *                                    -----
+ *
+ * As with the previous Siena structures, each structure here is laid out
+ * carefully: values are aligned to their natural boundary, with explicit
+ * padding fields added where necessary.  (No, technically this does not
+ * absolutely guarantee portability.  But, in practice, compilers are generally
+ * sensible enough not to introduce completely pointless padding, and it works
+ * well enough.)
+ */
+
+
+#ifndef CI_MGMT_TLV_LAYOUT_H
+#define CI_MGMT_TLV_LAYOUT_H
+
+
+/* ----------------------------------------------------------------------------
+ *  General structure (defined by SF-108797-SW)
+ * ----------------------------------------------------------------------------
+ */
+
+
+/* The "end" tag.
+ *
+ * (Note that this is *not* followed by length or value fields: anything after
+ * the tag itself is irrelevant.)
+ */
+
+#define TLV_TAG_END                     (0xEEEEEEEE)
+
+
+/* Other special reserved tag values.
+ */
+
+#define TLV_TAG_SKIP                    (0x00000000)
+#define TLV_TAG_INVALID                 (0xFFFFFFFF)
+
+
+/* TLV partition header.
+ *
+ * In a TLV partition, this must be the first item in the sequence, at offset
+ * 0.
+ */
+
+#define TLV_TAG_PARTITION_HEADER        (0xEF10DA7A)
+
+struct tlv_partition_header {
+  uint32_t tag;
+  uint32_t length;
+  uint16_t type_id;
+  uint16_t reserved;
+  uint32_t generation;
+  uint32_t total_length;
+};
+
+
+/* TLV partition trailer.
+ *
+ * In a TLV partition, this must be the last item in the sequence, immediately
+ * preceding the TLV_TAG_END word.
+ */
+
+#define TLV_TAG_PARTITION_TRAILER       (0xEF101A57)
+
+struct tlv_partition_trailer {
+  uint32_t tag;
+  uint32_t length;
+  uint32_t generation;
+  uint32_t checksum;
+};
+
+
+/* Appendable TLV partition header.
+ *
+ * In an appendable TLV partition, this must be the first item in the sequence,
+ * at offset 0.  (Note that, unlike the configuration partitions, there is no
+ * trailer before the TLV_TAG_END word.)
+ */
+
+#define TLV_TAG_APPENDABLE_PARTITION_HEADER (0xEF10ADA7)
+
+struct tlv_appendable_partition_header {
+  uint32_t tag;
+  uint32_t length;
+  uint16_t type_id;
+  uint16_t reserved;
+};
+
+
+/* ----------------------------------------------------------------------------
+ *  Configuration items
+ * ----------------------------------------------------------------------------
+ */
+
+
+/* NIC global capabilities.
+ */
+
+#define TLV_TAG_GLOBAL_CAPABILITIES     (0x00010000)
+
+struct tlv_global_capabilities {
+  uint32_t tag;
+  uint32_t length;
+  uint32_t flags;
+};
+
+
+/* Siena-style per-port MAC address allocation.
+ *
+ * There are <count> addresses, starting at <base_address> and incrementing
+ * by adding <stride> to the low-order byte(s).
+ *
+ * (See also TLV_TAG_GLOBAL_MAC for an alternative, specifying a global pool
+ * of contiguous MAC addresses for the firmware to allocate as it sees fit.)
+ */
+
+#define TLV_TAG_PORT_MAC(port)          (0x00020000 + (port))
+
+struct tlv_port_mac {
+  uint32_t tag;
+  uint32_t length;
+  uint8_t  base_address[6];
+  uint16_t reserved;
+  uint16_t count;
+  uint16_t stride;
+};
+
+
+/* Static VPD.
+ *
+ * This is the portion of VPD which is set at manufacturing time and not
+ * expected to change.  It is formatted as a standard PCI VPD block.
+ */
+
+#define TLV_TAG_PF_STATIC_VPD(pf)       (0x00030000 + (pf))
+
+struct tlv_pf_static_vpd {
+  uint32_t tag;
+  uint32_t length;
+  uint8_t  bytes[];
+};
+
+
+/* Dynamic VPD.
+ *
+ * This is the portion of VPD which may be changed (e.g. by firmware updates).
+ * It is formatted as a standard PCI VPD block.
+ */
+
+#define TLV_TAG_PF_DYNAMIC_VPD(pf)      (0x10030000 + (pf))
+
+struct tlv_pf_dynamic_vpd {
+  uint32_t tag;
+  uint32_t length;
+  uint8_t  bytes[];
+};
+
+
+/* "DBI" PCI config space changes.
+ *
+ * This is a set of edits made to the default PCI config space values before
+ * the device is allowed to enumerate.
+ */
+
+#define TLV_TAG_PF_DBI(pf)              (0x00040000 + (pf))
+
+struct tlv_pf_dbi {
+  uint32_t tag;
+  uint32_t length;
+  struct {
+    uint16_t addr;
+    uint16_t byte_enables;
+    uint32_t value;
+  } items[];
+};
+
+
+/* Partition subtype codes.
+ *
+ * A subtype may optionally be stored for each type of partition present in
+ * the NVRAM.  For example, this may be used to allow a generic firmware update
+ * utility to select a specific variant of firmware for a specific variant of
+ * board.
+ *
+ * The description[] field is an optional string which is returned in the
+ * MC_CMD_NVRAM_METADATA response if present.
+ */
+
+#define TLV_TAG_PARTITION_SUBTYPE(type) (0x00050000 + (type))
+
+struct tlv_partition_subtype {
+  uint32_t tag;
+  uint32_t length;
+  uint32_t subtype;
+  uint8_t  description[];
+};
+
+
+/* Partition version codes.
+ *
+ * A version may optionally be stored for each type of partition present in
+ * the NVRAM.  This provides a standard way of tracking the currently stored
+ * version of each of the various component images.
+ */
+
+#define TLV_TAG_PARTITION_VERSION(type) (0x10060000 + (type))
+
+struct tlv_partition_version {
+  uint32_t tag;
+  uint32_t length;
+  uint16_t version_w;
+  uint16_t version_x;
+  uint16_t version_y;
+  uint16_t version_z;
+};
+
+/* Global PCIe configuration */
+
+#define TLV_TAG_GLOBAL_PCIE_CONFIG (0x10070000)
+
+struct tlv_pcie_config {
+  uint32_t tag;
+  uint32_t length;
+  int16_t max_pf_number;                        /**< Largest PF RID (lower PFs may be hidden) */
+  uint16_t pf_aper;                             /**< BIU aperture for PF BAR2 */
+  uint16_t vf_aper;                             /**< BIU aperture for VF BAR0 */
+  uint16_t int_aper;                            /**< BIU aperture for PF BAR4 and VF BAR2 */  
+#define TLV_MAX_PF_DEFAULT (-1)                 /* Use FW default for largest PF RID  */
+#define TLV_APER_DEFAULT (0xFFFF)               /* Use FW default for a given aperture */
+};
+
+/* Per-PF configuration. Note that not all these fields are necessarily useful
+ * as the apertures are constrained by the BIU settings (the one case we do
+ * use is to make BAR2 bigger than the BIU thinks to reserve space), but we can
+ * tidy things up later */
+
+#define TLV_TAG_PF_PCIE_CONFIG(pf)  (0x10080000 + (pf))
+
+struct tlv_per_pf_pcie_config {
+  uint32_t tag;
+  uint32_t length;
+  uint8_t vfs_total;
+  uint8_t port_allocation;  
+  uint16_t vectors_per_pf;
+  uint16_t vectors_per_vf;
+  uint8_t pf_bar0_aperture;
+  uint8_t pf_bar2_aperture;
+  uint8_t vf_bar0_aperture;
+  uint8_t vf_base;  
+  uint16_t supp_pagesz;
+  uint16_t msix_vec_base;
+};
+
+
+/* Development ONLY. This is a single TLV tag for all the gubbins
+ * that can be set through the MC command-line other than the PCIe
+ * settings. This is a temporary measure. */
+#define TLV_TAG_TMP_GUBBINS (0x10090000)
+
+struct tlv_tmp_gubbins {
+  uint32_t tag;
+  uint32_t length;
+  /* Consumed by dpcpu.c */
+  uint64_t tx0_tags;     /* Bitmap */
+  uint64_t tx1_tags;     /* Bitmap */
+  uint64_t dl_tags;      /* Bitmap */
+  uint32_t flags;
+#define TLV_DPCPU_TX_STRIPE (1) /* TX striping is on */
+#define TLV_DPCPU_BIU_TAGS  (2) /* Use BIU tag manager */
+#define TLV_DPCPU_TX0_TAGS  (4) /* tx0_tags is valid */
+#define TLV_DPCPU_TX1_TAGS  (8) /* tx1_tags is valid */
+#define TLV_DPCPU_DL_TAGS  (16) /* dl_tags is valid */
+  /* Consumed by features.c */
+  uint32_t dut_features;        /* All 1s -> leave alone */
+  int8_t with_rmon;             /* 0 -> off, 1 -> on, -1 -> leave alone */
+  /* Consumed by clocks_hunt.c */
+  int8_t clk_mode;             /* 0 -> off, 1 -> on, -1 -> leave alone */
+  /* Consumed by sram.c */
+  int8_t rx_dc_size;           /* -1 -> leave alone */
+  int8_t tx_dc_size;
+  int16_t num_q_allocs;
+};
+
+/* Global port configuration
+ *
+ * This is now deprecated in favour of a platform-provided default
+ * and dynamic config override via tlv_global_port_options.
+ */
+#define TLV_TAG_GLOBAL_PORT_CONFIG      (0x000a0000)
+
+struct tlv_global_port_config {
+  uint32_t tag;
+  uint32_t length;
+  uint32_t ports_per_core;
+  uint32_t max_port_speed;
+};
+
+
+/* Firmware options.
+ *
+ * This is intended for user-configurable selection of optional firmware
+ * features and variants.
+ *
+ * Initially, this consists only of the satellite CPU firmware variant
+ * selection, but this tag could be extended in the future (using the
+ * tag length to determine whether additional fields are present).
+ */
+
+#define TLV_TAG_FIRMWARE_OPTIONS        (0x100b0000)
+
+struct tlv_firmware_options {
+  uint32_t tag;
+  uint32_t length;
+  uint32_t firmware_variant;
+#define TLV_FIRMWARE_VARIANT_DRIVER_SELECTED (0xffffffff)
+
+/* These are the values for overriding the driver's choice; the definitions
+ * are taken from MCDI so that they don't get out of step.  Include
+ * <ci/mgmt/mc_driver_pcol.h> or the equivalent from your driver's tree if
+ * you need to use these constants.
+ */
+#define TLV_FIRMWARE_VARIANT_FULL_FEATURED   MC_CMD_FW_FULL_FEATURED
+#define TLV_FIRMWARE_VARIANT_LOW_LATENCY     MC_CMD_FW_LOW_LATENCY
+#define TLV_FIRMWARE_VARIANT_PACKED_STREAM   MC_CMD_FW_PACKED_STREAM
+#define TLV_FIRMWARE_VARIANT_HIGH_TX_RATE    MC_CMD_FW_HIGH_TX_RATE
+#define TLV_FIRMWARE_VARIANT_PACKED_STREAM_HASH_MODE_1 \
+                                             MC_CMD_FW_PACKED_STREAM_HASH_MODE_1
+};
+
+/* Voltage settings
+ * 
+ * Intended for boards with A0 silicon where the core voltage may
+ * need tweaking. Most likely set once when the pass voltage is 
+ * determined. */
+
+#define TLV_TAG_0V9_SETTINGS (0x000c0000)
+
+struct tlv_0v9_settings {
+  uint32_t tag;
+  uint32_t length;  
+  uint16_t flags; /* Boards with high 0v9 settings may need active cooling */
+#define TLV_TAG_0V9_REQUIRES_FAN (1)
+  uint16_t target_voltage; /* In millivolts */
+  /* Since the limits are meant to be centred to the target (and must at least
+   * contain it) they need setting as well. */
+  uint16_t warn_low;       /* In millivolts */
+  uint16_t warn_high;      /* In millivolts */
+  uint16_t panic_low;      /* In millivolts */
+  uint16_t panic_high;     /* In millivolts */   
+};
+
+
+/* Clock configuration */
+
+#define TLV_TAG_CLOCK_CONFIG            (0x000d0000)
+
+struct tlv_clock_config {
+  uint32_t tag;
+  uint32_t length;  
+  uint16_t clk_sys;        /* MHz */
+  uint16_t clk_dpcpu;      /* MHz */
+  uint16_t clk_icore;      /* MHz */
+  uint16_t clk_pcs;        /* MHz */
+};
+
+#define TLV_TAG_CLOCK_CONFIG_MEDFORD      (0x00100000)
+
+struct tlv_clock_config_medford {
+  uint32_t tag;
+  uint32_t length;
+  uint16_t clk_sys;        /* MHz */
+  uint16_t clk_mc;         /* MHz */
+  uint16_t clk_rmon;       /* MHz */
+  uint16_t clk_vswitch;    /* MHz */
+  uint16_t clk_dpcpu;      /* MHz */
+  uint16_t clk_pcs;        /* MHz */
+};
+
+
+/* EF10-style global pool of MAC addresses.
+ *
+ * There are <count> addresses, starting at <base_address>, which are
+ * contiguous.  Firmware is responsible for allocating addresses from this
+ * pool to ports / PFs as appropriate.
+ */
+
+#define TLV_TAG_GLOBAL_MAC              (0x000e0000)
+
+struct tlv_global_mac {
+  uint32_t tag;
+  uint32_t length;
+  uint8_t  base_address[6];
+  uint16_t reserved1;
+  uint16_t count;
+  uint16_t reserved2;
+};
+
+#define TLV_TAG_ATB_0V9_TARGET           (0x000f0000)
+
+/* The target value for the 0v9 power rail measured on-chip at the
+ * analogue test bus */
+struct tlv_0v9_atb_target {
+  uint32_t tag;
+  uint32_t length;
+  uint16_t millivolts;
+  uint16_t reserved;
+};
+
+/* Global PCIe configuration, second revision. This represents the visible PFs
+ * by a bitmap rather than having the number of the highest visible one. As such
+ * it can (for a 16-PF chip) represent a superset of what TLV_TAG_GLOBAL_PCIE_CONFIG
+ * can and it should be used in place of that tag in future (but compatibility with
+ * the old tag will be left in the firmware indefinitely).  */
+
+#define TLV_TAG_GLOBAL_PCIE_CONFIG_R2 (0x10100000)
+
+struct tlv_pcie_config_r2 {
+  uint32_t tag;
+  uint32_t length;
+  uint16_t visible_pfs;                         /**< Bitmap of visible PFs */
+  uint16_t pf_aper;                             /**< BIU aperture for PF BAR2 */
+  uint16_t vf_aper;                             /**< BIU aperture for VF BAR0 */
+  uint16_t int_aper;                            /**< BIU aperture for PF BAR4 and VF BAR2 */  
+};
+
+/* Dynamic port mode.
+ *
+ * Allows selecting alternate port configuration for platforms that support it
+ * (e.g. 1x40G vs 2x10G on Milano, 1x40G vs 4x10G on Medford). This affects the
+ * number of externally visible ports (and, hence, PF to port mapping), so must
+ * be done at boot time.
+ *
+ * This tag supercedes tlv_global_port_config.
+ */
+
+#define TLV_TAG_GLOBAL_PORT_MODE         (0x10110000)
+
+struct tlv_global_port_mode {
+  uint32_t tag;
+  uint32_t length;
+  uint32_t port_mode;
+#define TLV_PORT_MODE_DEFAULT           (0xffffffff) /* Default for given platform */
+#define TLV_PORT_MODE_10G                        (0) /* 10G, single SFP/10G-KR */
+#define TLV_PORT_MODE_40G                        (1) /* 40G, single QSFP/40G-KR */
+#define TLV_PORT_MODE_10G_10G                    (2) /* 2x10G, dual SFP/10G-KR or single QSFP */
+#define TLV_PORT_MODE_40G_40G                    (3) /* 40G + 40G, dual QSFP/40G-KR (Greenport, Medford) */
+#define TLV_PORT_MODE_10G_10G_10G_10G            (4) /* 2x10G + 2x10G, quad SFP/10G-KR or dual QSFP (Greenport, Medford) */
+#define TLV_PORT_MODE_10G_10G_10G_10G_Q          (5) /* 4x10G, single QSFP, cage 0 (Medford) */
+#define TLV_PORT_MODE_40G_10G_10G                (6) /* 1x40G + 2x10G, dual QSFP (Greenport, Medford) */
+#define TLV_PORT_MODE_10G_10G_40G                (7) /* 2x10G + 1x40G, dual QSFP (Greenport, Medford) */
+#define TLV_PORT_MODE_10G_10G_10G_10G_Q2         (8) /* 4x10G, single QSFP, cage 1 (Medford) */
+#define TLV_PORT_MODE_MAX TLV_PORT_MODE_10G_10G_10G_10G_Q2
+};
+
+/* Type of the v-switch created implicitly by the firmware */
+
+#define TLV_TAG_VSWITCH_TYPE(port)       (0x10120000 + (port))
+
+struct tlv_vswitch_type {
+  uint32_t tag;
+  uint32_t length;
+  uint32_t vswitch_type;
+#define TLV_VSWITCH_TYPE_DEFAULT        (0xffffffff) /* Firmware default; equivalent to no TLV present for a given port */
+#define TLV_VSWITCH_TYPE_NONE                    (0)
+#define TLV_VSWITCH_TYPE_VLAN                    (1)
+#define TLV_VSWITCH_TYPE_VEB                     (2)
+#define TLV_VSWITCH_TYPE_VEPA                    (3)
+#define TLV_VSWITCH_TYPE_MUX                     (4)
+#define TLV_VSWITCH_TYPE_TEST                    (5)
+};
+
+/* A VLAN tag for the v-port created implicitly by the firmware */
+
+#define TLV_TAG_VPORT_VLAN_TAG(pf)               (0x10130000 + (pf))
+
+struct tlv_vport_vlan_tag {
+  uint32_t tag;
+  uint32_t length;
+  uint32_t vlan_tag;
+#define TLV_VPORT_NO_VLAN_TAG                    (0xFFFFFFFF) /* Default in the absence of TLV for a given PF */
+};
+
+/* Offset to be applied to the 0v9 setting, wherever it came from */
+
+#define TLV_TAG_ATB_0V9_OFFSET           (0x10140000)
+
+struct tlv_0v9_atb_offset {
+  uint32_t tag;
+  uint32_t length;
+  int16_t  offset_millivolts;
+  uint16_t reserved;
+};
+
+/* A privilege mask given on reset to all non-admin PCIe functions (that is other than first-PF-per-port).
+ * The meaning of particular bits is defined in mcdi_ef10.yml under MC_CMD_PRIVILEGE_MASK, see also bug 44583.
+ * TLV_TAG_PRIVILEGE_MASK_ADD specifies bits that should be added (ORed) to firmware default while
+ * TLV_TAG_PRIVILEGE_MASK_REM specifies bits that should be removed (ANDed) from firmware default:
+ * Initial_privilege_mask = (firmware_default_mask | privilege_mask_add) & ~privilege_mask_rem */
+
+#define TLV_TAG_PRIVILEGE_MASK          (0x10150000) /* legacy symbol - do not use */
+
+struct tlv_privilege_mask {                          /* legacy structure - do not use */
+  uint32_t tag;
+  uint32_t length;
+  uint32_t privilege_mask;
+};
+
+#define TLV_TAG_PRIVILEGE_MASK_ADD      (0x10150000)
+
+struct tlv_privilege_mask_add {
+  uint32_t tag;
+  uint32_t length;
+  uint32_t privilege_mask_add;
+};
+
+#define TLV_TAG_PRIVILEGE_MASK_REM      (0x10160000)
+
+struct tlv_privilege_mask_rem {
+  uint32_t tag;
+  uint32_t length;
+  uint32_t privilege_mask_rem;
+};
+
+/* Additional privileges given to all PFs.
+ * This tag takes precedence over TLV_TAG_PRIVILEGE_MASK_REM. */
+
+#define TLV_TAG_PRIVILEGE_MASK_ADD_ALL_PFS         (0x10190000)
+
+struct tlv_privilege_mask_add_all_pfs {
+  uint32_t tag;
+  uint32_t length;
+  uint32_t privilege_mask_add;
+};
+
+/* Additional privileges given to a selected PF.
+ * This tag takes precedence over TLV_TAG_PRIVILEGE_MASK_REM. */
+
+#define TLV_TAG_PRIVILEGE_MASK_ADD_SINGLE_PF(pf)   (0x101A0000 + (pf))
+
+struct tlv_privilege_mask_add_single_pf {
+  uint32_t tag;
+  uint32_t length;
+  uint32_t privilege_mask_add;
+};
+
+/* Turning on/off the PFIOV mode.
+ * This tag only takes effect if TLV_TAG_VSWITCH_TYPE is missing or set to DEFAULT. */
+
+#define TLV_TAG_PFIOV(port)             (0x10170000 + (port))
+
+struct tlv_pfiov {
+  uint32_t tag;
+  uint32_t length;
+  uint32_t pfiov;
+#define TLV_PFIOV_OFF                    (0) /* Default */
+#define TLV_PFIOV_ON                     (1)
+};
+
+/* Multicast filter chaining mode selection.
+ *
+ * When enabled, multicast packets are delivered to all recipients of all
+ * matching multicast filters, with the exception that IP multicast filters
+ * will steal traffic from MAC multicast filters on a per-function basis.
+ * (New behaviour.)
+ *
+ * When disabled, multicast packets will always be delivered only to the
+ * recipients of the highest priority matching multicast filter.
+ * (Legacy behaviour.)
+ *
+ * The DEFAULT mode (which is the same as the tag not being present at all)
+ * is equivalent to ENABLED in production builds, and DISABLED in eftest
+ * builds.
+ *
+ * This option is intended to provide run-time control over this feature
+ * while it is being stabilised and may be withdrawn at some point in the
+ * future; the new behaviour is intended to become the standard behaviour.
+ */
+
+#define TLV_TAG_MCAST_FILTER_CHAINING   (0x10180000)
+
+struct tlv_mcast_filter_chaining {
+  uint32_t tag;
+  uint32_t length;
+  uint32_t mode;
+#define TLV_MCAST_FILTER_CHAINING_DEFAULT  (0xffffffff)
+#define TLV_MCAST_FILTER_CHAINING_DISABLED (0)
+#define TLV_MCAST_FILTER_CHAINING_ENABLED  (1)
+};
+
+
+/* Pacer rate limit per PF */
+#define TLV_TAG_RATE_LIMIT(pf)    (0x101b0000 + (pf))
+
+struct tlv_rate_limit {
+  uint32_t tag;
+  uint32_t length;
+  uint32_t rate_mbps;
+};
+
+
+/* OCSD Enable/Disable
+ *
+ * This setting allows OCSD to be disabled. This is a requirement for HP
+ * servers to support PCI passthrough for virtualization.
+ *
+ * The DEFAULT mode (which is the same as the tag not being present) is
+ * equivalent to ENABLED.
+ *
+ * This option is not used by the MCFW, and is entirely handled by the various
+ * drivers that support OCSD, by reading the setting before they attempt
+ * to enable OCSD.
+ *
+ * bit0: OCSD Disabled/Enabled
+ */
+
+#define TLV_TAG_OCSD (0x101C0000)
+
+struct tlv_ocsd {
+  uint32_t tag;
+  uint32_t length;
+  uint32_t mode;
+#define TLV_OCSD_DISABLED 0
+#define TLV_OCSD_ENABLED 1 /* Default */
+};
+
+#endif /* CI_MGMT_TLV_LAYOUT_H */
diff --git a/sys/dev/sfxge/common/efsys.h b/sys/dev/sfxge/common/efsys.h
index d911c43c51fa..0a7b1ad6cd3f 100644
--- a/sys/dev/sfxge/common/efsys.h
+++ b/sys/dev/sfxge/common/efsys.h
@@ -1,30 +1,34 @@
 /*-
- * Copyright (c) 2010-2011 Solarflare Communications, Inc.
+ * Copyright (c) 2010-2015 Solarflare Communications Inc.
  * All rights reserved.
  *
  * This software was developed in part by Philip Paeps under contract for
  * Solarflare Communications, Inc.
  *
  * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
+ * modification, are permitted provided that the following conditions are met:
  *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are
+ * those of the authors and should not be interpreted as representing official
+ * policies, either expressed or implied, of the FreeBSD Project.
  *
  * $FreeBSD$
  */
@@ -56,6 +60,7 @@ extern "C" {
 #else
 #define	EFSYS_USE_UINT64 0
 #endif
+#define	EFSYS_HAS_SSE2_M128 0
 #if _BYTE_ORDER == _BIG_ENDIAN
 #define	EFSYS_IS_BIG_ENDIAN 1
 #define	EFSYS_IS_LITTLE_ENDIAN 0
@@ -90,6 +95,10 @@ extern "C" {
 #define	P2ROUNDUP(x, align)	(-(-(x) & -(align)))
 #endif
 
+#ifndef P2ALIGN
+#define	P2ALIGN(_x, _a)		((_x) & -(_a))
+#endif
+
 #ifndef IS2P
 #define	ISP2(x)			(((x) & ((x) - 1)) == 0)
 #endif
@@ -176,7 +185,7 @@ prefetch_read_once(void *addr)
 #endif
 static __inline void
 sfxge_map_mbuf_fast(bus_dma_tag_t tag, bus_dmamap_t map,
-    struct mbuf *m, bus_dma_segment_t *seg)
+		    struct mbuf *m, bus_dma_segment_t *seg)
 {
 #if defined(__i386__) || defined(__amd64__)
 	seg->ds_addr = pmap_kextract(mtod(m, vm_offset_t));
@@ -188,10 +197,6 @@ sfxge_map_mbuf_fast(bus_dma_tag_t tag, bus_dmamap_t map,
 #endif
 }
 
-/* Modifiers used for DOS builds */
-#define	__cs
-#define	__far
-
 /* Modifiers used for Windows builds */
 #define	__in
 #define	__in_opt
@@ -231,6 +236,7 @@ sfxge_map_mbuf_fast(bus_dma_tag_t tag, bus_dmamap_t map,
 #define	EFSYS_OPT_FALCON 0
 #define	EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE 0
 #define	EFSYS_OPT_SIENA 1
+#define	EFSYS_OPT_HUNTINGTON 1
 #ifdef DEBUG
 #define	EFSYS_OPT_CHECK_REG 1
 #else
@@ -248,19 +254,19 @@ sfxge_map_mbuf_fast(bus_dma_tag_t tag, bus_dmamap_t map,
 #define	EFSYS_OPT_MON_NULL 0
 #define	EFSYS_OPT_MON_LM87 0
 #define	EFSYS_OPT_MON_MAX6647 0
-#define	EFSYS_OPT_MON_SIENA 0
+#define	EFSYS_OPT_MON_MCDI 0
 #define	EFSYS_OPT_MON_STATS 0
 
 #define	EFSYS_OPT_PHY_NULL 0
 #define	EFSYS_OPT_PHY_QT2022C2 0
 #define	EFSYS_OPT_PHY_SFX7101 0
 #define	EFSYS_OPT_PHY_TXC43128 0
-#define	EFSYS_OPT_PHY_PM8358 0
 #define	EFSYS_OPT_PHY_SFT9001 0
 #define	EFSYS_OPT_PHY_QT2025C 0
 #define	EFSYS_OPT_PHY_STATS 1
 #define	EFSYS_OPT_PHY_PROPS 0
-#define	EFSYS_OPT_PHY_BIST 1
+#define	EFSYS_OPT_PHY_BIST 0
+#define	EFSYS_OPT_BIST 1
 #define	EFSYS_OPT_PHY_LED_CONTROL 1
 #define	EFSYS_OPT_PHY_FLAGS 0
 
@@ -276,7 +282,8 @@ sfxge_map_mbuf_fast(bus_dma_tag_t tag, bus_dmamap_t map,
 #define	EFSYS_OPT_WOL 1
 #define	EFSYS_OPT_RX_SCALE 1
 #define	EFSYS_OPT_QSTATS 1
-#define	EFSYS_OPT_FILTER 0
+#define	EFSYS_OPT_FILTER 1
+#define	EFSYS_OPT_MCAST_FILTER_LIST 1
 #define	EFSYS_OPT_RX_SCATTER 0
 #define	EFSYS_OPT_RX_HDR_SPLIT 0
 
@@ -618,6 +625,9 @@ typedef struct efsys_mem_s {
 #define	EFSYS_MEM_ADDR(_esmp)						\
 	((_esmp)->esm_addr)
 
+#define	EFSYS_MEM_IS_NULL(_esmp)					\
+	((_esmp)->esm_base == NULL)
+
 /* BAR */
 
 #define	SFXGE_LOCK_NAME_MAX	16
@@ -880,6 +890,24 @@ typedef struct efsys_bar_s {
 	} while (B_FALSE)
 #endif
 
+/*
+ * Guarantees 64bit aligned 64bit writes to write combined BAR mapping
+ * (required by PIO hardware)
+ */
+#define	EFSYS_BAR_WC_WRITEQ(_esbp, _offset, _eqp)			\
+	do {								\
+		_NOTE(CONSTANTCONDITION)				\
+		KASSERT(IS_P2ALIGNED(_offset, sizeof (efx_qword_t)),	\
+		    ("not power of 2 aligned"));			\
+									\
+		(void) (_esbp);						\
+									\
+		/* FIXME: Perform a 64-bit write */			\
+		KASSERT(0, ("not implemented"));			\
+									\
+	_NOTE(CONSTANTCONDITION)					\
+	} while (B_FALSE)
+
 #if defined(SFXGE_USE_BUS_SPACE_8)
 #define	EFSYS_BAR_WRITEO(_esbp, _offset, _eop, _lock)			\
 	do {								\
@@ -979,6 +1007,13 @@ typedef struct efsys_bar_s {
 	} while (B_FALSE)
 #endif
 
+/* Use the standard octo-word write for doorbell writes */
+#define	EFSYS_BAR_DOORBELL_WRITEO(_esbp, _offset, _eop)			\
+	do {								\
+		EFSYS_BAR_WRITEO((_esbp), (_offset), (_eop), B_FALSE);	\
+	_NOTE(CONSTANTCONDITION)					\
+	} while (B_FALSE)
+
 /* SPIN */
 
 #define	EFSYS_SPIN(_us)							\
@@ -994,6 +1029,23 @@ typedef struct efsys_bar_s {
 #define	EFSYS_MEM_READ_BARRIER()	rmb()
 #define	EFSYS_PIO_WRITE_BARRIER()
 
+/* DMA SYNC */
+#define	EFSYS_DMA_SYNC_FOR_KERNEL(_esmp, _offset, _size)		\
+	do {								\
+		bus_dmamap_sync((_esmp)->esm_tag,			\
+		    (_esmp)->esm_map,					\
+		    BUS_DMASYNC_POSTREAD);				\
+	_NOTE(CONSTANTCONDITION)					\
+	} while (B_FALSE)
+
+#define	EFSYS_DMA_SYNC_FOR_DEVICE(_esmp, _offset, _size)		\
+	do {								\
+		bus_dmamap_sync((_esmp)->esm_tag,			\
+		    (_esmp)->esm_map,					\
+		    BUS_DMASYNC_PREWRITE);				\
+	_NOTE(CONSTANTCONDITION)					\
+	} while (B_FALSE)
+
 /* TIMESTAMP */
 
 typedef	clock_t	efsys_timestamp_t;
@@ -1150,7 +1202,7 @@ extern void	sfxge_err(efsys_identifier_t *, unsigned int,
 
 #define	EFSYS_ASSERT(_exp) do {						\
 	if (!(_exp))							\
-		panic(#_exp);						\
+		panic("%s", #_exp);					\
 	} while (0)
 
 #define	EFSYS_ASSERT3(_x, _op, _y, _t) do {				\
@@ -1164,6 +1216,10 @@ extern void	sfxge_err(efsys_identifier_t *, unsigned int,
 #define	EFSYS_ASSERT3S(_x, _op, _y)	EFSYS_ASSERT3(_x, _op, _y, int64_t)
 #define	EFSYS_ASSERT3P(_x, _op, _y)	EFSYS_ASSERT3(_x, _op, _y, uintptr_t)
 
+/* ROTATE */
+
+#define	EFSYS_HAS_ROTL_DWORD 0
+
 #ifdef	__cplusplus
 }
 #endif
diff --git a/sys/dev/sfxge/common/efx.h b/sys/dev/sfxge/common/efx.h
index c5ef44877582..3435951e58fb 100644
--- a/sys/dev/sfxge/common/efx.h
+++ b/sys/dev/sfxge/common/efx.h
@@ -1,26 +1,31 @@
 /*-
- * Copyright 2006-2009 Solarflare Communications Inc.  All rights reserved.
+ * Copyright (c) 2006-2015 Solarflare Communications Inc.
+ * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
+ * modification, are permitted provided that the following conditions are met:
  *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are
+ * those of the authors and should not be interpreted as representing official
+ * policies, either expressed or implied, of the FreeBSD Project.
  *
  * $FreeBSD$
  */
@@ -29,6 +34,7 @@
 #define	_SYS_EFX_H
 
 #include "efsys.h"
+#include "efx_phy_ids.h"
 
 #ifdef	__cplusplus
 extern "C" {
@@ -38,14 +44,13 @@ extern "C" {
 
 #define	EFX_ARRAY_SIZE(_array) (sizeof(_array) / sizeof((_array)[0]))
 
-#ifndef EFSYS_MEM_IS_NULL
-#define	EFSYS_MEM_IS_NULL(_esmp) ((_esmp)->esm_base == NULL)
-#endif
+#define	EFX_FIELD_OFFSET(_type, _field) ((size_t) &(((_type *)0)->_field))
 
 typedef enum efx_family_e {
 	EFX_FAMILY_INVALID,
 	EFX_FAMILY_FALCON,
 	EFX_FAMILY_SIENA,
+	EFX_FAMILY_HUNTINGTON,
 	EFX_FAMILY_NTYPES
 } efx_family_t;
 
@@ -60,11 +65,23 @@ efx_infer_family(
 	__in		efsys_bar_t *esbp,
 	__out		efx_family_t *efp);
 
-#define	EFX_PCI_VENID_SFC		0x1924
-#define	EFX_PCI_DEVID_FALCON		0x0710
-#define	EFX_PCI_DEVID_BETHPAGE		0x0803
-#define	EFX_PCI_DEVID_SIENA		0x0813
-#define	EFX_PCI_DEVID_SIENA_F1_UNINIT	0x0810
+#define	EFX_PCI_VENID_SFC			0x1924
+
+#define	EFX_PCI_DEVID_FALCON			0x0710	/* SFC4000 */
+
+#define	EFX_PCI_DEVID_BETHPAGE			0x0803	/* SFC9020 */
+#define	EFX_PCI_DEVID_SIENA			0x0813	/* SFL9021 */
+#define	EFX_PCI_DEVID_SIENA_F1_UNINIT		0x0810
+
+#define	EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT	0x0901
+#define	EFX_PCI_DEVID_FARMINGDALE		0x0903	/* SFC9120 PF */
+#define	EFX_PCI_DEVID_HUNTINGTON		0x0913	/* SFL9122 PF */
+#define	EFX_PCI_DEVID_GREENPORT			0x0923	/* SFC9140 PF */
+
+#define	EFX_PCI_DEVID_FARMINGDALE_VF		0x1903	/* SFC9120 VF */
+#define	EFX_PCI_DEVID_HUNTINGTON_VF		0x1913	/* SFL9122 VF */
+#define	EFX_PCI_DEVID_GREENPORT_VF		0x1923	/* SFC9140 VF */
+
 
 #define	EFX_MEM_BAR	2
 
@@ -86,10 +103,27 @@ enum {
 	EFX_ERR_NCODES
 };
 
+/* Calculate the IEEE 802.3 CRC32 of a MAC addr */
+extern	__checkReturn		uint32_t
+efx_crc32_calculate(
+	__in			uint32_t crc_init,
+	__in_ecount(length)	uint8_t const *input,
+	__in			int length);
+
+
+/* Type prototypes */
+
+typedef struct efx_rxq_s	efx_rxq_t;
+
 /* NIC */
 
 typedef struct efx_nic_s	efx_nic_t;
 
+#define	EFX_NIC_FUNC_PRIMARY	0x00000001
+#define	EFX_NIC_FUNC_LINKCTRL	0x00000002
+#define	EFX_NIC_FUNC_TRUSTED	0x00000004
+
+
 extern	__checkReturn	int
 efx_nic_create(
 	__in		efx_family_t family,
@@ -145,6 +179,11 @@ efx_nic_destroy(
 
 #if EFSYS_OPT_MCDI
 
+#if EFSYS_OPT_HUNTINGTON
+/* Huntington requires MCDIv2 commands */
+#define	WITH_MCDI_V2 1
+#endif
+
 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
 
 typedef enum efx_mcdi_exception_e {
@@ -154,6 +193,7 @@ typedef enum efx_mcdi_exception_e {
 
 typedef struct efx_mcdi_transport_s {
 	void		*emt_context;
+	efsys_mem_t	*emt_dma_mem;
 	void		(*emt_execute)(void *, efx_mcdi_req_t *);
 	void		(*emt_ev_cpl)(void *);
 	void		(*emt_exception)(void *, efx_mcdi_exception_t);
@@ -168,6 +208,10 @@ extern	__checkReturn	int
 efx_mcdi_reboot(
 	__in		efx_nic_t *enp);
 
+			void
+efx_mcdi_new_epoch(
+	__in		efx_nic_t *enp);
+
 extern			void
 efx_mcdi_request_start(
 	__in		efx_nic_t *enp,
@@ -251,7 +295,7 @@ efx_intr_fini(
 
 #if EFSYS_OPT_MAC_STATS
 
-/* START MKCONFIG GENERATED EfxHeaderMacBlock bb8d39428b6fdcf5 */
+/* START MKCONFIG GENERATED EfxHeaderMacBlock e323546097fd7c65 */
 typedef enum efx_mac_stat_e {
 	EFX_MAC_RX_OCTETS,
 	EFX_MAC_RX_PKTS,
@@ -304,6 +348,36 @@ typedef enum efx_mac_stat_e {
 	EFX_MAC_TX_LATE_COL_PKTS,
 	EFX_MAC_TX_DEF_PKTS,
 	EFX_MAC_TX_EX_DEF_PKTS,
+	EFX_MAC_PM_TRUNC_BB_OVERFLOW,
+	EFX_MAC_PM_DISCARD_BB_OVERFLOW,
+	EFX_MAC_PM_TRUNC_VFIFO_FULL,
+	EFX_MAC_PM_DISCARD_VFIFO_FULL,
+	EFX_MAC_PM_TRUNC_QBB,
+	EFX_MAC_PM_DISCARD_QBB,
+	EFX_MAC_PM_DISCARD_MAPPING,
+	EFX_MAC_RXDP_Q_DISABLED_PKTS,
+	EFX_MAC_RXDP_DI_DROPPED_PKTS,
+	EFX_MAC_RXDP_STREAMING_PKTS,
+	EFX_MAC_RXDP_HLB_FETCH,
+	EFX_MAC_RXDP_HLB_WAIT,
+	EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
+	EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
+	EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
+	EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
+	EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
+	EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
+	EFX_MAC_VADAPTER_RX_BAD_PACKETS,
+	EFX_MAC_VADAPTER_RX_BAD_BYTES,
+	EFX_MAC_VADAPTER_RX_OVERFLOW,
+	EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
+	EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
+	EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
+	EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
+	EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
+	EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
+	EFX_MAC_VADAPTER_TX_BAD_PACKETS,
+	EFX_MAC_VADAPTER_TX_BAD_BYTES,
+	EFX_MAC_VADAPTER_TX_OVERFLOW,
 	EFX_MAC_NSTATS
 } efx_mac_stat_t;
 
@@ -321,9 +395,16 @@ typedef enum efx_link_mode_e {
 	EFX_LINK_1000HDX,
 	EFX_LINK_1000FDX,
 	EFX_LINK_10000FDX,
+	EFX_LINK_40000FDX,
 	EFX_LINK_NMODES
 } efx_link_mode_t;
 
+#define	EFX_MAC_ADDR_LEN 6
+
+#define	EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t*)_address)[0] & 0x01)
+
+#define	EFX_MAC_MULTICAST_LIST_MAX	256
+
 #define	EFX_MAC_SDU_MAX	9202
 
 #define	EFX_MAC_PDU(_sdu) 				\
@@ -347,11 +428,29 @@ efx_mac_addr_set(
 	__in		efx_nic_t *enp,
 	__in		uint8_t *addr);
 
-extern	__checkReturn	int
+extern	__checkReturn			int
 efx_mac_filter_set(
+	__in				efx_nic_t *enp,
+	__in				boolean_t all_unicst,
+	__in				boolean_t mulcst,
+	__in				boolean_t all_mulcst,
+	__in				boolean_t brdcst);
+
+extern	__checkReturn	int
+efx_mac_multicast_list_set(
+	__in				efx_nic_t *enp,
+	__in_ecount(6*count)		uint8_t const *addrs,
+	__in				int count);
+
+extern	__checkReturn	int
+efx_mac_filter_default_rxq_set(
 	__in		efx_nic_t *enp,
-	__in		boolean_t unicst,
-	__in		boolean_t brdcst);
+	__in		efx_rxq_t *erp,
+	__in		boolean_t using_rss);
+
+extern			void
+efx_mac_filter_default_rxq_clear(
+	__in		efx_nic_t *enp);
 
 extern	__checkReturn	int
 efx_mac_drain(
@@ -381,15 +480,41 @@ efx_mac_fcntl_get(
 #define	EFX_MAC_HASH_BITS	(1 << 8)
 
 extern	__checkReturn			int
+efx_pktfilter_init(
+	__in				efx_nic_t *enp);
+
+extern					void
+efx_pktfilter_fini(
+	__in				efx_nic_t *enp);
+
+extern	__checkReturn			int
+efx_pktfilter_set(
+	__in		efx_nic_t *enp,
+	__in		boolean_t unicst,
+	__in		boolean_t brdcst);
+
+extern	__checkReturn			int
 efx_mac_hash_set(
 	__in				efx_nic_t *enp,
 	__in_ecount(EFX_MAC_HASH_BITS)	unsigned int const *bucket);
 
+#if EFSYS_OPT_MCAST_FILTER_LIST
+extern	__checkReturn			int
+efx_pktfilter_mcast_list_set(
+	__in				efx_nic_t *enp,
+	__in				uint8_t const *addrs,
+	__in				int count);
+#endif /* EFSYS_OPT_MCAST_FILTER_LIST */
+
+extern	__checkReturn			int
+efx_pktfilter_mcast_all(
+	__in				efx_nic_t *enp);
+
 #if EFSYS_OPT_MAC_STATS
 
 #if EFSYS_OPT_NAMES
 
-extern	__checkReturn			const char __cs *
+extern	__checkReturn			const char *
 efx_mac_stat_name(
 	__in				efx_nic_t *enp,
 	__in				unsigned int id);
@@ -440,12 +565,13 @@ typedef enum efx_mon_type_e {
 	EFX_MON_LM87,
 	EFX_MON_MAX6647,
 	EFX_MON_SFC90X0,
+	EFX_MON_SFC91X0,
 	EFX_MON_NTYPES
 } efx_mon_type_t;
 
 #if EFSYS_OPT_NAMES
 
-extern		const char __cs *
+extern		const char *
 efx_mon_name(
 	__in	efx_nic_t *enp);
 
@@ -457,9 +583,10 @@ efx_mon_init(
 
 #if EFSYS_OPT_MON_STATS
 
-#define	EFX_MON_STATS_SIZE 0x100
+#define	EFX_MON_STATS_PAGE_SIZE 0x100
+#define	EFX_MON_MASK_ELEMENT_SIZE 32
 
-/* START MKCONFIG GENERATED MonitorHeaderStatsBlock 58706a378332aeee */
+/* START MKCONFIG GENERATED MonitorHeaderStatsBlock c79c86b62a144846 */
 typedef enum efx_mon_stat_e {
 	EFX_MON_STAT_2_5V,
 	EFX_MON_STAT_VCCP1,
@@ -491,6 +618,45 @@ typedef enum efx_mon_stat_e {
 	EFX_MON_STAT_VAOE_IN,
 	EFX_MON_STAT_IAOE,
 	EFX_MON_STAT_IAOE_IN,
+	EFX_MON_STAT_NIC_POWER,
+	EFX_MON_STAT_0_9V,
+	EFX_MON_STAT_I0_9V,
+	EFX_MON_STAT_I1_2V,
+	EFX_MON_STAT_0_9V_ADC,
+	EFX_MON_STAT_INT_TEMP2,
+	EFX_MON_STAT_VREG_TEMP,
+	EFX_MON_STAT_VREG_0_9V_TEMP,
+	EFX_MON_STAT_VREG_1_2V_TEMP,
+	EFX_MON_STAT_INT_VPTAT,
+	EFX_MON_STAT_INT_ADC_TEMP,
+	EFX_MON_STAT_EXT_VPTAT,
+	EFX_MON_STAT_EXT_ADC_TEMP,
+	EFX_MON_STAT_AMBIENT_TEMP,
+	EFX_MON_STAT_AIRFLOW,
+	EFX_MON_STAT_VDD08D_VSS08D_CSR,
+	EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
+	EFX_MON_STAT_HOTPOINT_TEMP,
+	EFX_MON_STAT_PHY_POWER_SWITCH_PORT0,
+	EFX_MON_STAT_PHY_POWER_SWITCH_PORT1,
+	EFX_MON_STAT_MUM_VCC,
+	EFX_MON_STAT_0V9_A,
+	EFX_MON_STAT_I0V9_A,
+	EFX_MON_STAT_0V9_A_TEMP,
+	EFX_MON_STAT_0V9_B,
+	EFX_MON_STAT_I0V9_B,
+	EFX_MON_STAT_0V9_B_TEMP,
+	EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
+	EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC,
+	EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
+	EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC,
+	EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
+	EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
+	EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC,
+	EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC,
+	EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
+	EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
+	EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC,
+	EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC,
 	EFX_MON_NSTATS
 } efx_mon_stat_t;
 
@@ -501,16 +667,17 @@ typedef enum efx_mon_stat_state_e {
 	EFX_MON_STAT_STATE_WARNING = 1,
 	EFX_MON_STAT_STATE_FATAL = 2,
 	EFX_MON_STAT_STATE_BROKEN = 3,
+	EFX_MON_STAT_STATE_NO_READING = 4,
 } efx_mon_stat_state_t;
 
-typedef struct efx_mon_stat_value_t {
+typedef struct efx_mon_stat_value_s {
 	uint16_t	emsv_value;
 	uint16_t	emsv_state;
 } efx_mon_stat_value_t;
 
 #if EFSYS_OPT_NAMES
 
-extern					const char __cs *
+extern					const char *
 efx_mon_stat_name(
 	__in				efx_nic_t *enp,
 	__in				efx_mon_stat_t id);
@@ -540,16 +707,6 @@ efx_mon_fini(
 
 #define	MAXMMD		((1 << 5) - 1)
 
-/* PHY types */
-#define	EFX_PHY_NULL		0x0
-#define	EFX_PHY_TXC43128	0x1
-#define	EFX_PHY_SFX7101		0x3
-#define	EFX_PHY_QT2022C2	0x4
-#define	EFX_PHY_SFT9001A	0x8
-#define	EFX_PHY_QT2025C		0x9
-#define	EFX_PHY_SFT9001B	0xa
-#define	EFX_PHY_QLX111V		0xc
-
 extern	__checkReturn	int
 efx_phy_verify(
 	__in		efx_nic_t *enp);
@@ -596,26 +753,38 @@ typedef enum efx_loopback_type_e {
 	EFX_LOOPBACK_PHY_XS = 15,
 	EFX_LOOPBACK_PCS = 16,
 	EFX_LOOPBACK_PMA_PMD = 17,
+	EFX_LOOPBACK_XPORT = 18,
+	EFX_LOOPBACK_XGMII_WS = 19,
+	EFX_LOOPBACK_XAUI_WS = 20,
+	EFX_LOOPBACK_XAUI_WS_FAR = 21,
+	EFX_LOOPBACK_XAUI_WS_NEAR = 22,
+	EFX_LOOPBACK_GMII_WS = 23,
+	EFX_LOOPBACK_XFI_WS = 24,
+	EFX_LOOPBACK_XFI_WS_FAR = 25,
+	EFX_LOOPBACK_PHYXS_WS = 26,
+	EFX_LOOPBACK_PMA_INT = 27,
+	EFX_LOOPBACK_SD_NEAR = 28,
+	EFX_LOOPBACK_SD_FAR = 29,
+	EFX_LOOPBACK_PMA_INT_WS = 30,
+	EFX_LOOPBACK_SD_FEP2_WS = 31,
+	EFX_LOOPBACK_SD_FEP1_5_WS = 32,
+	EFX_LOOPBACK_SD_FEP_WS = 33,
+	EFX_LOOPBACK_SD_FES_WS = 34,
 	EFX_LOOPBACK_NTYPES
 } efx_loopback_type_t;
 
-#define	EFX_LOOPBACK_MAC_MASK			\
-	((1 << EFX_LOOPBACK_DATA) |		\
-	    (1 << EFX_LOOPBACK_GMAC) | 		\
-	    (1 << EFX_LOOPBACK_XGMII) | 	\
-	    (1 << EFX_LOOPBACK_XGXS) | 		\
-	    (1 << EFX_LOOPBACK_XAUI) |		\
-	    (1 << EFX_LOOPBACK_GMII) |		\
-	    (1 << EFX_LOOPBACK_SGMII) |		\
-	    (1 << EFX_LOOPBACK_XGBR) |		\
-	    (1 << EFX_LOOPBACK_XFI) |		\
-	    (1 << EFX_LOOPBACK_XAUI_FAR) |	\
-	    (1 << EFX_LOOPBACK_GMII_FAR) |	\
-	    (1 << EFX_LOOPBACK_SGMII_FAR) |	\
-	    (1 << EFX_LOOPBACK_XFI_FAR))
-
-#define EFX_LOOPBACK_MASK			\
-	((1 << EFX_LOOPBACK_NTYPES) - 1)
+typedef enum efx_loopback_kind_e {
+	EFX_LOOPBACK_KIND_OFF = 0,
+	EFX_LOOPBACK_KIND_ALL,
+	EFX_LOOPBACK_KIND_MAC,
+	EFX_LOOPBACK_KIND_PHY,
+	EFX_LOOPBACK_NKINDS
+} efx_loopback_kind_t;
+
+extern			void
+efx_loopback_mask(
+	__in	efx_loopback_kind_t loopback_kind,
+	__out	efx_qword_t *maskp);
 
 extern	__checkReturn	int
 efx_port_loopback_set(
@@ -625,7 +794,7 @@ efx_port_loopback_set(
 
 #if EFSYS_OPT_NAMES
 
-extern	__checkReturn	const char __cs *
+extern	__checkReturn	const char *
 efx_loopback_type_name(
 	__in		efx_nic_t *enp,
 	__in		efx_loopback_type_t type);
@@ -637,7 +806,7 @@ efx_loopback_type_name(
 extern	__checkReturn	int
 efx_port_poll(
 	__in		efx_nic_t *enp,
-	__out		efx_link_mode_t	*link_modep);
+	__out_opt	efx_link_mode_t	*link_modep);
 
 extern 		void
 efx_port_fini(
@@ -655,6 +824,7 @@ typedef enum efx_phy_cap_type_e {
 	EFX_PHY_CAP_PAUSE,
 	EFX_PHY_CAP_ASYM,
 	EFX_PHY_CAP_AN,
+	EFX_PHY_CAP_40000FDX,
 	EFX_PHY_CAP_NTYPES
 } efx_phy_cap_type_t;
 
@@ -692,6 +862,7 @@ typedef enum efx_phy_media_type_e {
 	EFX_PHY_MEDIA_XFP,
 	EFX_PHY_MEDIA_SFP_PLUS,
 	EFX_PHY_MEDIA_BASE_T,
+	EFX_PHY_MEDIA_QSFP_PLUS,
 	EFX_PHY_MEDIA_NTYPES
 } efx_phy_media_type_t;
 
@@ -762,7 +933,7 @@ typedef enum efx_phy_stat_e {
 
 #if EFSYS_OPT_NAMES
 
-extern					const char __cs *
+extern					const char *
 efx_phy_stat_name(
 	__in				efx_nic_t *enp,
 	__in				efx_phy_stat_t stat);
@@ -783,7 +954,7 @@ efx_phy_stats_update(
 
 #if EFSYS_OPT_NAMES
 
-extern		const char __cs *
+extern		const char *
 efx_phy_prop_name(
 	__in	efx_nic_t *enp,
 	__in	unsigned int id);
@@ -807,22 +978,25 @@ efx_phy_prop_set(
 
 #endif	/* EFSYS_OPT_PHY_PROPS */
 
-#if EFSYS_OPT_PHY_BIST
-
-typedef enum efx_phy_bist_type_e {
-	EFX_PHY_BIST_TYPE_UNKNOWN,
-	EFX_PHY_BIST_TYPE_NORMAL,
-	EFX_PHY_BIST_TYPE_CABLE_SHORT,
-	EFX_PHY_BIST_TYPE_CABLE_LONG,
-	EFX_PHY_BIST_TYPE_NTYPES,
-} efx_phy_bist_type_t;
-
-typedef enum efx_phy_bist_result_e {
-	EFX_PHY_BIST_RESULT_UNKNOWN,
-	EFX_PHY_BIST_RESULT_RUNNING,
-	EFX_PHY_BIST_RESULT_PASSED,
-	EFX_PHY_BIST_RESULT_FAILED,
-} efx_phy_bist_result_t;
+#if EFSYS_OPT_BIST
+
+typedef enum efx_bist_type_e {
+	EFX_BIST_TYPE_UNKNOWN,
+	EFX_BIST_TYPE_PHY_NORMAL,
+	EFX_BIST_TYPE_PHY_CABLE_SHORT,
+	EFX_BIST_TYPE_PHY_CABLE_LONG,
+	EFX_BIST_TYPE_MC_MEM,	/* Test the MC DMEM and IMEM */
+	EFX_BIST_TYPE_SAT_MEM,	/* Test the DMEM and IMEM of satellite cpus*/
+	EFX_BIST_TYPE_REG,	/* Test the register memories */
+	EFX_BIST_TYPE_NTYPES,
+} efx_bist_type_t;
+
+typedef enum efx_bist_result_e {
+	EFX_BIST_RESULT_UNKNOWN,
+	EFX_BIST_RESULT_RUNNING,
+	EFX_BIST_RESULT_PASSED,
+	EFX_BIST_RESULT_FAILED,
+} efx_bist_result_t;
 
 typedef enum efx_phy_cable_status_e {
 	EFX_PHY_CABLE_STATUS_OK,
@@ -833,39 +1007,53 @@ typedef enum efx_phy_cable_status_e {
 	EFX_PHY_CABLE_STATUS_BUSY,
 } efx_phy_cable_status_t;
 
-typedef enum efx_phy_bist_value_e {
-	EFX_PHY_BIST_CABLE_LENGTH_A,
-	EFX_PHY_BIST_CABLE_LENGTH_B,
-	EFX_PHY_BIST_CABLE_LENGTH_C,
-	EFX_PHY_BIST_CABLE_LENGTH_D,
-	EFX_PHY_BIST_CABLE_STATUS_A,
-	EFX_PHY_BIST_CABLE_STATUS_B,
-	EFX_PHY_BIST_CABLE_STATUS_C,
-	EFX_PHY_BIST_CABLE_STATUS_D,
-	EFX_PHY_BIST_FAULT_CODE,
-	EFX_PHY_BIST_NVALUES,
-} efx_phy_bist_value_t;
+typedef enum efx_bist_value_e {
+	EFX_BIST_PHY_CABLE_LENGTH_A,
+	EFX_BIST_PHY_CABLE_LENGTH_B,
+	EFX_BIST_PHY_CABLE_LENGTH_C,
+	EFX_BIST_PHY_CABLE_LENGTH_D,
+	EFX_BIST_PHY_CABLE_STATUS_A,
+	EFX_BIST_PHY_CABLE_STATUS_B,
+	EFX_BIST_PHY_CABLE_STATUS_C,
+	EFX_BIST_PHY_CABLE_STATUS_D,
+	EFX_BIST_FAULT_CODE,
+	/* Memory BIST specific values. These match to the MC_CMD_BIST_POLL
+	 * response. */
+	EFX_BIST_MEM_TEST,
+	EFX_BIST_MEM_ADDR,
+	EFX_BIST_MEM_BUS,
+	EFX_BIST_MEM_EXPECT,
+	EFX_BIST_MEM_ACTUAL,
+	EFX_BIST_MEM_ECC,
+	EFX_BIST_MEM_ECC_PARITY,
+	EFX_BIST_MEM_ECC_FATAL,
+	EFX_BIST_NVALUES,
+} efx_bist_value_t;
+
+extern	__checkReturn		int
+efx_bist_enable_offline(
+	__in			efx_nic_t *enp);
 
 extern	__checkReturn		int
-efx_phy_bist_start(
+efx_bist_start(
 	__in			efx_nic_t *enp,
-	__in			efx_phy_bist_type_t type);
+	__in			efx_bist_type_t type);
 
 extern	__checkReturn		int
-efx_phy_bist_poll(
+efx_bist_poll(
 	__in			efx_nic_t *enp,
-	__in			efx_phy_bist_type_t type,
-	__out			efx_phy_bist_result_t *resultp,
+	__in			efx_bist_type_t type,
+	__out			efx_bist_result_t *resultp,
 	__out_opt		uint32_t *value_maskp,
 	__out_ecount_opt(count)	unsigned long *valuesp,
 	__in			size_t count);
 
 extern				void
-efx_phy_bist_stop(
+efx_bist_stop(
 	__in			efx_nic_t *enp,
-	__in			efx_phy_bist_type_t type);
+	__in			efx_bist_type_t type);
 
-#endif	/* EFSYS_OPT_PHY_BIST */
+#endif	/* EFSYS_OPT_BIST */
 
 #define	EFX_FEATURE_IPV6		0x00000001
 #define	EFX_FEATURE_LFSR_HASH_INSERT	0x00000002
@@ -876,6 +1064,10 @@ efx_phy_bist_stop(
 #define	EFX_FEATURE_LOOKAHEAD_SPLIT	0x00000040
 #define	EFX_FEATURE_MAC_HEADER_FILTERS	0x00000080
 #define	EFX_FEATURE_TURBO		0x00000100
+#define	EFX_FEATURE_MCDI_DMA		0x00000200
+#define	EFX_FEATURE_TX_SRC_FILTERS	0x00000400
+#define	EFX_FEATURE_PIO_BUFFERS		0x00000800
+#define	EFX_FEATURE_FW_ASSISTED_TSO	0x00001000
 
 typedef struct efx_nic_cfg_s {
 	uint32_t		enc_board_type;
@@ -886,20 +1078,29 @@ typedef struct efx_nic_cfg_s {
 	char			enc_phy_revision[21];
 	efx_mon_type_t		enc_mon_type;
 #if EFSYS_OPT_MON_STATS
-	uint32_t		enc_mon_stat_mask;
+	uint32_t		enc_mon_stat_dma_buf_size;
+	uint32_t		enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
 #endif
 	unsigned int		enc_features;
 	uint8_t			enc_mac_addr[6];
-	uint8_t			enc_port;
+	uint8_t			enc_port;	/* PHY port number */
+	uint32_t		enc_func_flags;
+	uint32_t		enc_intr_vec_base;
+	uint32_t		enc_intr_limit;
 	uint32_t		enc_evq_limit;
 	uint32_t		enc_txq_limit;
 	uint32_t		enc_rxq_limit;
 	uint32_t		enc_buftbl_limit;
+	uint32_t		enc_piobuf_limit;
+	uint32_t		enc_piobuf_size;
 	uint32_t		enc_evq_timer_quantum_ns;
 	uint32_t		enc_evq_timer_max_us;
 	uint32_t		enc_clk_mult;
+	uint32_t		enc_rx_prefix_size;
+	uint32_t		enc_rx_buf_align_start;
+	uint32_t		enc_rx_buf_align_end;
 #if EFSYS_OPT_LOOPBACK
-	uint32_t		enc_loopback_types[EFX_LINK_NMODES];
+	efx_qword_t		enc_loopback_types[EFX_LINK_NMODES];
 #endif	/* EFSYS_OPT_LOOPBACK */
 #if EFSYS_OPT_PHY_FLAGS
 	uint32_t		enc_phy_flags_mask;
@@ -914,23 +1115,100 @@ typedef struct efx_nic_cfg_s {
 	unsigned int		enc_phy_nprops;
 #endif	/* EFSYS_OPT_PHY_PROPS */
 #if EFSYS_OPT_SIENA
-	uint8_t			enc_siena_channel;
+	uint8_t			enc_mcdi_mdio_channel;
 #if EFSYS_OPT_PHY_STATS
-	uint32_t		enc_siena_phy_stat_mask;
+	uint32_t		enc_mcdi_phy_stat_mask;
 #endif	/* EFSYS_OPT_PHY_STATS */
+#endif /* EFSYS_OPT_SIENA */
+#if (EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON)
 #if EFSYS_OPT_MON_STATS
-	uint32_t		enc_siena_mon_stat_mask;
+	uint32_t		*enc_mcdi_sensor_maskp;
+	uint32_t		enc_mcdi_sensor_mask_size;
 #endif	/* EFSYS_OPT_MON_STATS */
-#endif	/* EFSYS_OPT_SIENA */
-#if EFSYS_OPT_PHY_BIST
+#endif	/* (EFSYS_OPT_SIENA | EFSYS_OPT_HUNTINGTON) */
+#if EFSYS_OPT_BIST
 	uint32_t		enc_bist_mask;
-#endif	/* EFSYS_OPT_PHY_BIST */
+#endif	/* EFSYS_OPT_BIST */
+#if EFSYS_OPT_HUNTINGTON
+	uint32_t		enc_pf;
+	uint32_t		enc_vf;
+	uint32_t		enc_privilege_mask;
+#endif /* EFSYS_OPT_HUNTINGTON */
+	boolean_t		enc_bug26807_workaround;
+	boolean_t		enc_bug35388_workaround;
+	boolean_t		enc_bug41750_workaround;
+	boolean_t		enc_rx_batching_enabled;
+	/* Maximum number of descriptors completed in an rx event. */
+	uint32_t		enc_rx_batch_max;
+        /* Number of rx descriptors the hardware requires for a push. */
+        uint32_t		enc_rx_push_align;
+	/*
+	 * Maximum number of bytes into the packet the TCP header can start for
+	 * the hardware to apply TSO packet edits.
+	 */
+	uint32_t                enc_tx_tso_tcp_header_offset_limit;
+	boolean_t               enc_fw_assisted_tso_enabled;
+	boolean_t               enc_hw_tx_insert_vlan_enabled;
+	/* Datapath firmware vadapter/vport/vswitch support */
+	boolean_t		enc_datapath_cap_evb;
+	/* External port identifier */
+	uint8_t			enc_external_port;
 } efx_nic_cfg_t;
 
+#define	EFX_PCI_FUNCTION_IS_PF(_encp)	((_encp)->enc_vf == 0xffff)
+#define	EFX_PCI_FUNCTION_IS_VF(_encp)	((_encp)->enc_vf != 0xffff)
+
+#define	EFX_PCI_FUNCTION(_encp)	\
+	(EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
+
+#define	EFX_PCI_VF_PARENT(_encp)	((_encp)->enc_pf)
+
 extern			const efx_nic_cfg_t *
 efx_nic_cfg_get(
 	__in		efx_nic_t *enp);
 
+/* Driver resource limits (minimum required/maximum usable). */
+typedef struct efx_drv_limits_s
+{
+	uint32_t	edl_min_evq_count;
+	uint32_t	edl_max_evq_count;
+
+	uint32_t	edl_min_rxq_count;
+	uint32_t	edl_max_rxq_count;
+
+	uint32_t	edl_min_txq_count;
+	uint32_t	edl_max_txq_count;
+
+	/* PIO blocks (sub-allocated from piobuf) */
+	uint32_t	edl_min_pio_alloc_size;
+	uint32_t	edl_max_pio_alloc_count;
+} efx_drv_limits_t;
+
+extern	__checkReturn	int
+efx_nic_set_drv_limits(
+	__inout		efx_nic_t *enp,
+	__in		efx_drv_limits_t *edlp);
+
+typedef enum efx_nic_region_e {
+	EFX_REGION_VI,			/* Memory BAR UC mapping */
+	EFX_REGION_PIO_WRITE_VI,	/* Memory BAR WC mapping */
+} efx_nic_region_t;
+
+extern	__checkReturn	int
+efx_nic_get_bar_region(
+	__in		efx_nic_t *enp,
+	__in		efx_nic_region_t region,
+	__out		uint32_t *offsetp,
+	__out		size_t *sizep);
+
+extern	__checkReturn	int
+efx_nic_get_vi_pool(
+	__in		efx_nic_t *enp,
+	__out		uint32_t *evq_countp,
+	__out		uint32_t *rxq_countp,
+	__out		uint32_t *txq_countp);
+
+
 #if EFSYS_OPT_VPD
 
 typedef enum efx_vpd_tag_e {
@@ -1029,6 +1307,7 @@ typedef enum efx_nvram_type_e {
 	EFX_NVRAM_FCFW,
 	EFX_NVRAM_CPLD,
 	EFX_NVRAM_FPGA_BACKUP,
+	EFX_NVRAM_DYNAMIC_CFG,
 	EFX_NVRAM_NTYPES,
 } efx_nvram_type_t;
 
@@ -1080,7 +1359,15 @@ extern	__checkReturn		int
 efx_nvram_set_version(
 	__in			efx_nic_t *enp,
 	__in			efx_nvram_type_t type,
-	__out			uint16_t version[4]);
+	__in_ecount(4)		uint16_t version[4]);
+
+/* Validate contents of TLV formatted partition */
+extern	__checkReturn		int
+efx_nvram_tlv_validate(
+	__in			efx_nic_t *enp,
+	__in			uint32_t partn,
+	__in_bcount(partn_size)	caddr_t partn_data,
+	__in			size_t partn_size);
 
 extern	 __checkReturn		int
 efx_nvram_erase(
@@ -1246,12 +1533,11 @@ typedef struct efx_evq_s	efx_evq_t;
 
 #if EFSYS_OPT_QSTATS
 
-/* START MKCONFIG GENERATED EfxHeaderEventQueueBlock d5614a5d669c8ca3 */
+/* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
 typedef enum efx_ev_qstat_e {
 	EV_ALL,
 	EV_RX,
 	EV_RX_OK,
-	EV_RX_RECOVERY,
 	EV_RX_FRM_TRUNC,
 	EV_RX_TOBE_DISC,
 	EV_RX_PAUSE_FRM_ERR,
@@ -1269,16 +1555,14 @@ typedef enum efx_ev_qstat_e {
 	EV_RX_OTHER_IPV4,
 	EV_RX_OTHER_IPV6,
 	EV_RX_NON_IP,
-	EV_RX_OVERRUN,
+	EV_RX_BATCH,
 	EV_TX,
 	EV_TX_WQ_FF_FULL,
 	EV_TX_PKT_ERR,
 	EV_TX_PKT_TOO_BIG,
 	EV_TX_UNEXPECTED,
 	EV_GLOBAL,
-	EV_GLOBAL_PHY,
 	EV_GLOBAL_MNT,
-	EV_GLOBAL_RX_RECOVERY,
 	EV_DRIVER,
 	EV_DRIVER_SRM_UPD_DONE,
 	EV_DRIVER_TX_DESCQ_FLS_DONE,
@@ -1303,13 +1587,9 @@ extern		void
 efx_ev_fini(
 	__in		efx_nic_t *enp);
 
-#define	EFX_MASK(_max, _min)	(-((_max) << 1) ^ -(_min))
-
 #define	EFX_EVQ_MAXNEVS		32768
 #define	EFX_EVQ_MINNEVS		512
 
-#define	EFX_EVQ_NEVS_MASK	EFX_MASK(EFX_EVQ_MAXNEVS, EFX_EVQ_MINNEVS)
-
 #define	EFX_EVQ_SIZE(_nevs)	((_nevs) * sizeof (efx_qword_t))
 #define	EFX_EVQ_NBUFS(_nevs)	(EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
 
@@ -1345,6 +1625,7 @@ typedef __checkReturn	boolean_t
 #define	EFX_PKT_IPV4		0x0800
 
 #define	EFX_PKT_IPV6		0x1000
+#define	EFX_PKT_PREFIX_LEN	0x2000
 #define	EFX_ADDR_MISMATCH	0x4000
 #define	EFX_DISCARD		0x8000
 
@@ -1371,6 +1652,9 @@ typedef	__checkReturn	boolean_t
 #define	EFX_EXCEPTION_UNKNOWN_SENSOREVT	0x00000004
 #define	EFX_EXCEPTION_FWALERT_SRAM	0x00000005
 #define	EFX_EXCEPTION_UNKNOWN_FWALERT	0x00000006
+#define	EFX_EXCEPTION_RX_ERROR		0x00000007
+#define	EFX_EXCEPTION_TX_ERROR		0x00000008
+#define	EFX_EXCEPTION_EV_ERROR		0x00000009
 
 typedef	__checkReturn	boolean_t
 (*efx_exception_ev_t)(
@@ -1460,7 +1744,7 @@ typedef struct efx_ev_callbacks_s {
 #endif	/* EFSYS_OPT_MON_STATS */
 #if EFSYS_OPT_MAC_STATS
 	efx_mac_stats_ev_t		eec_mac_stats;
-#endif	/* EFSYS_OPT_MON_STATS */
+#endif	/* EFSYS_OPT_MAC_STATS */
 } efx_ev_callbacks_t;
 
 extern	__checkReturn	boolean_t
@@ -1498,7 +1782,7 @@ efx_ev_qprime(
 
 #if EFSYS_OPT_NAMES
 
-extern		const char __cs *
+extern		const char *
 efx_ev_qstat_name(
 	__in	efx_nic_t *enp,
 	__in	unsigned int id);
@@ -1518,11 +1802,9 @@ efx_ev_qdestroy(
 
 /* RX */
 
-typedef struct efx_rxq_s	efx_rxq_t;
-
 extern	__checkReturn	int
 efx_rx_init(
-	__in		efx_nic_t *enp);
+	__inout		efx_nic_t *enp);
 
 extern		void
 efx_rx_fini(
@@ -1558,10 +1840,32 @@ typedef enum efx_rx_hash_type_e {
 	EFX_RX_HASH_TCPIPV6,
 } efx_rx_hash_type_t;
 
+typedef enum efx_rx_hash_support_e {
+	EFX_RX_HASH_UNAVAILABLE = 0,	/* Hardware hash not inserted */
+	EFX_RX_HASH_AVAILABLE		/* Insert hash with/without RSS */
+} efx_rx_hash_support_t;
+
 #define	EFX_RSS_TBL_SIZE	128	/* Rows in RX indirection table */
 #define	EFX_MAXRSS	    	64	/* RX indirection entry range */
 #define	EFX_MAXRSS_LEGACY   	16 	/* See bug16611 and bug17213 */
 
+typedef enum efx_rx_scale_support_e {
+	EFX_RX_SCALE_UNAVAILABLE = 0,	/* Not supported */
+	EFX_RX_SCALE_EXCLUSIVE,		/* Writable key/indirection table */
+	EFX_RX_SCALE_SHARED		/* Read-only key/indirection table */
+} efx_rx_scale_support_t;
+
+ extern	__checkReturn	int
+efx_rx_hash_support_get(
+	__in		efx_nic_t *enp,
+	__out		efx_rx_hash_support_t *supportp);
+
+
+extern	__checkReturn	int
+efx_rx_scale_support_get(
+	__in		efx_nic_t *enp,
+	__out		efx_rx_scale_support_t *supportp);
+
 extern	__checkReturn	int
 efx_rx_scale_mode_set(
 	__in	efx_nic_t *enp,
@@ -1576,54 +1880,28 @@ efx_rx_scale_tbl_set(
 	__in		size_t n);
 
 extern	__checkReturn	int
-efx_rx_scale_toeplitz_ipv4_key_set(
+efx_rx_scale_key_set(
 	__in		efx_nic_t *enp,
 	__in_ecount(n)	uint8_t *key,
 	__in		size_t n);
 
-extern	__checkReturn	int
-efx_rx_scale_toeplitz_ipv6_key_set(
+extern uint32_t
+efx_psuedo_hdr_hash_get(
 	__in		efx_nic_t *enp,
-	__in_ecount(n)	uint8_t *key,
-	__in		size_t n);
-
-/*
- * The prefix is a byte array of one of the forms:
- *
- *  0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15
- * XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.TT.TT.TT.TT
- * XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.LL.LL
- *
- * where:
- *
- * TT.TT.TT.TT is a 32-bit Toeplitz hash
- * LL.LL is a 16-bit LFSR hash
- *
- * Hash values are in network (big-endian) byte order.
- */
-
-#define	EFX_RX_PREFIX_SIZE	16
-
-#define	EFX_RX_HASH_VALUE(_func, _buffer)				\
-	(((_func) == EFX_RX_HASHALG_LFSR) ?				\
-		((uint16_t)(((_buffer)[14] << 8) | (_buffer)[15])) :	\
-		((uint32_t)(((_buffer)[12] << 24) |			\
-		    ((_buffer)[13] << 16) |				\
-		    ((_buffer)[14] << 8) |				\
-		    (_buffer)[15])))
-
-#define	EFX_RX_HASH_SIZE(_func)						\
-	(((_func) == EFX_RX_HASHALG_LFSR) ?				\
-		sizeof (uint16_t) : 					\
-		sizeof (uint32_t))
+	__in		efx_rx_hash_alg_t func,
+	__in		uint8_t *buffer);
 
 #endif	/* EFSYS_OPT_RX_SCALE */
 
+extern	__checkReturn	int
+efx_psuedo_hdr_pkt_length_get(
+	__in		efx_nic_t *enp,
+	__in		uint8_t *buffer,
+	__out		uint16_t *pkt_lengthp);
+
 #define	EFX_RXQ_MAXNDESCS		4096
 #define	EFX_RXQ_MINNDESCS		512
 
-#define	EFX_RXQ_NDESCS_MASK		EFX_MASK(EFX_RXQ_MAXNDESCS, EFX_RXQ_MINNDESCS)
-
 #define	EFX_RXQ_SIZE(_ndescs)		((_ndescs) * sizeof (efx_qword_t))
 #define	EFX_RXQ_NBUFS(_ndescs)		(EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
 #define	EFX_RXQ_LIMIT(_ndescs)		((_ndescs) - 16)
@@ -1655,6 +1933,10 @@ typedef struct efx_buffer_s {
 	boolean_t		eb_eop;
 } efx_buffer_t;
 
+typedef struct efx_desc_s {
+	efx_qword_t ed_eq;
+} efx_desc_t;
+
 extern			void
 efx_rx_qpost(
 	__in		efx_rxq_t *erp,
@@ -1667,9 +1949,10 @@ efx_rx_qpost(
 extern		void
 efx_rx_qpush(
 	__in	efx_rxq_t *erp,
-	__in	unsigned int added);
+	__in	unsigned int added,
+	__inout	unsigned int *pushedp);
 
-extern		void
+extern	__checkReturn	int
 efx_rx_qflush(
 	__in	efx_rxq_t *erp);
 
@@ -1687,10 +1970,10 @@ typedef struct efx_txq_s	efx_txq_t;
 
 #if EFSYS_OPT_QSTATS
 
-/* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 536c5fa5014944bf */
+/* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
 typedef enum efx_tx_qstat_e {
 	TX_POST,
-	TX_UNALIGNED_SPLIT,
+	TX_POST_PIO,
 	TX_NQSTATS
 } efx_tx_qstat_t;
 
@@ -1706,16 +1989,21 @@ extern		void
 efx_tx_fini(
 	__in	efx_nic_t *enp);
 
-#define	EFX_TXQ_MAXNDESCS		4096
-#define	EFX_TXQ_MINNDESCS		512
+#define	EFX_BUG35388_WORKAROUND(_encp)					\
+	(((_encp) == NULL) ? 1 : ((_encp)->enc_bug35388_workaround != 0))
+
+#define	EFX_TXQ_MAXNDESCS(_encp)					\
+	((EFX_BUG35388_WORKAROUND(_encp)) ? 2048 : 4096)
 
-#define	EFX_TXQ_NDESCS_MASK		EFX_MASK(EFX_TXQ_MAXNDESCS, EFX_TXQ_MINNDESCS)
+#define	EFX_TXQ_MINNDESCS		512
 
 #define	EFX_TXQ_SIZE(_ndescs)		((_ndescs) * sizeof (efx_qword_t))
 #define	EFX_TXQ_NBUFS(_ndescs)		(EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
 #define	EFX_TXQ_LIMIT(_ndescs)		((_ndescs) - 16)
 #define	EFX_TXQ_DC_NDESCS(_dcsize)	(8 << _dcsize)
 
+#define	EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
+
 extern	__checkReturn	int
 efx_tx_qcreate(
 	__in		efx_nic_t *enp,
@@ -1726,7 +2014,8 @@ efx_tx_qcreate(
 	__in		uint32_t id,
 	__in		uint16_t flags,
 	__in		efx_evq_t *eep,
-	__deref_out	efx_txq_t **etpp);
+	__deref_out	efx_txq_t **etpp,
+	__out		unsigned int *addedp);
 
 extern	__checkReturn	int
 efx_tx_qpost(
@@ -1741,24 +2030,77 @@ efx_tx_qpace(
 	__in		efx_txq_t *etp,
 	__in		unsigned int ns);
 
-extern		void
+extern			void
 efx_tx_qpush(
-	__in	efx_txq_t *etp,
-	__in	unsigned int added);
+	__in		efx_txq_t *etp,
+	__in		unsigned int added,
+	__in		unsigned int pushed);
 
-extern		void
+extern	__checkReturn	int
 efx_tx_qflush(
-	__in	efx_txq_t *etp);
+	__in		efx_txq_t *etp);
 
-extern		void
+extern			void
 efx_tx_qenable(
-	__in	efx_txq_t *etp);
+	__in		efx_txq_t *etp);
+
+extern	__checkReturn	int
+efx_tx_qpio_enable(
+	__in		efx_txq_t *etp);
+
+extern			void
+efx_tx_qpio_disable(
+	__in		efx_txq_t *etp);
+
+extern	__checkReturn	int
+efx_tx_qpio_write(
+	__in			efx_txq_t *etp,
+	__in_ecount(buf_length)	uint8_t *buffer,
+	__in			size_t buf_length,
+	__in                    size_t pio_buf_offset);
+
+extern	__checkReturn	int
+efx_tx_qpio_post(
+	__in			efx_txq_t *etp,
+	__in			size_t pkt_length,
+	__in			unsigned int completed,
+	__inout			unsigned int *addedp);
+
+extern	__checkReturn	int
+efx_tx_qdesc_post(
+	__in		efx_txq_t *etp,
+	__in_ecount(n)	efx_desc_t *ed,
+	__in		unsigned int n,
+	__in		unsigned int completed,
+	__inout		unsigned int *addedp);
+
+extern	void
+efx_tx_qdesc_dma_create(
+	__in	efx_txq_t *etp,
+	__in	efsys_dma_addr_t addr,
+	__in	size_t size,
+	__in	boolean_t eop,
+	__out	efx_desc_t *edp);
+
+extern	void
+efx_tx_qdesc_tso_create(
+	__in	efx_txq_t *etp,
+	__in	uint16_t ipv4_id,
+	__in	uint32_t tcp_seq,
+	__in	uint8_t  tcp_flags,
+	__out	efx_desc_t *edp);
+
+extern	void
+efx_tx_qdesc_vlantci_create(
+	__in	efx_txq_t *etp,
+	__in	uint16_t tci,
+	__out	efx_desc_t *edp);
 
 #if EFSYS_OPT_QSTATS
 
 #if EFSYS_OPT_NAMES
 
-extern		const char __cs *
+extern		const char *
 efx_tx_qstat_name(
 	__in	efx_nic_t *etp,
 	__in	unsigned int id);
@@ -1781,21 +2123,89 @@ efx_tx_qdestroy(
 
 #if EFSYS_OPT_FILTER
 
+#define	EFX_ETHER_TYPE_IPV4 0x0800
+#define	EFX_ETHER_TYPE_IPV6 0x86DD
+
+#define	EFX_IPPROTO_TCP 6
+#define	EFX_IPPROTO_UDP 17
+
 typedef enum efx_filter_flag_e {
 	EFX_FILTER_FLAG_RX_RSS = 0x01,		/* use RSS to spread across
 						 * multiple queues */
 	EFX_FILTER_FLAG_RX_SCATTER = 0x02,	/* enable RX scatter */
-	EFX_FILTER_FLAG_RX_OVERRIDE_IP = 0x04,	/* MAC filter overrides
-						 * any matching IP filter */
+	EFX_FILTER_FLAG_RX_OVER_AUTO = 0x04,	/* Override an automatic filter
+						 * (priority EFX_FILTER_PRI_AUTO).
+						 * May only be set by the filter
+						 * implementation for each type.
+						 * A removal request will
+						 * restore the automatic filter
+						 * in its place. */
+	EFX_FILTER_FLAG_RX = 0x08,		/* Filter is for RX */
+	EFX_FILTER_FLAG_TX = 0x10,		/* Filter is for TX */
 } efx_filter_flag_t;
 
+typedef enum efx_filter_match_flags_e {
+	EFX_FILTER_MATCH_REM_HOST = 0x0001,	/* Match by remote IP host
+						 * address */
+	EFX_FILTER_MATCH_LOC_HOST = 0x0002,	/* Match by local IP host
+						 * address */
+	EFX_FILTER_MATCH_REM_MAC = 0x0004,	/* Match by remote MAC address */
+	EFX_FILTER_MATCH_REM_PORT = 0x0008,	/* Match by remote TCP/UDP port */
+	EFX_FILTER_MATCH_LOC_MAC = 0x0010,	/* Match by remote TCP/UDP port */
+	EFX_FILTER_MATCH_LOC_PORT = 0x0020,	/* Match by local TCP/UDP port */
+	EFX_FILTER_MATCH_ETHER_TYPE = 0x0040,	/* Match by Ether-type */
+	EFX_FILTER_MATCH_INNER_VID = 0x0080,	/* Match by inner VLAN ID */
+	EFX_FILTER_MATCH_OUTER_VID = 0x0100,	/* Match by outer VLAN ID */
+	EFX_FILTER_MATCH_IP_PROTO = 0x0200,	/* Match by IP transport
+						 * protocol */
+	EFX_FILTER_MATCH_LOC_MAC_IG = 0x0400,	/* Match by local MAC address
+						 * I/G bit. Used for RX default
+						 * unicast and multicast/
+						 * broadcast filters. */
+} efx_filter_match_flags_t;
+
+typedef enum efx_filter_priority_s {
+	EFX_FILTER_PRI_HINT = 0,	/* Performance hint */
+	EFX_FILTER_PRI_AUTO,		/* Automatic filter based on device
+					 * address list or hardware
+					 * requirements. This may only be used
+					 * by the filter implementation for
+					 * each NIC type. */
+	EFX_FILTER_PRI_MANUAL,		/* Manually configured filter */
+	EFX_FILTER_PRI_REQUIRED,	/* Required for correct behaviour of the
+					 * client (e.g. SR-IOV, HyperV VMQ etc.)
+					 */
+} efx_filter_priority_t;
+
+/*
+ * FIXME: All these fields are assumed to be in little-endian byte order.
+ * It may be better for some to be big-endian. See bug42804.
+ */
+
 typedef struct efx_filter_spec_s {
-	uint8_t		efs_type;
-	uint8_t		efs_flags;
-	uint16_t	efs_dmaq_id;
-	uint32_t	efs_dword[3];
+	uint32_t	efs_match_flags:12;
+	uint32_t	efs_priority:2;
+	uint32_t	efs_flags:6;
+	uint32_t	efs_dmaq_id:12;
+	uint32_t	efs_rss_context;
+	uint16_t	efs_outer_vid;
+	uint16_t	efs_inner_vid;
+	uint8_t		efs_loc_mac[EFX_MAC_ADDR_LEN];
+	uint8_t		efs_rem_mac[EFX_MAC_ADDR_LEN];
+	uint16_t	efs_ether_type;
+	uint8_t		efs_ip_proto;
+	uint16_t	efs_loc_port;
+	uint16_t	efs_rem_port;
+	efx_oword_t	efs_rem_host;
+	efx_oword_t	efs_loc_host;
 } efx_filter_spec_t;
 
+
+/* Default values for use in filter specifications */
+#define	EFX_FILTER_SPEC_RSS_CONTEXT_DEFAULT	0xffffffff
+#define	EFX_FILTER_SPEC_RX_DMAQ_ID_DROP		0xfff
+#define	EFX_FILTER_SPEC_VID_UNSPEC		0xffff
+
 extern	__checkReturn	int
 efx_filter_init(
 	__in		efx_nic_t *enp);
@@ -1805,115 +2215,82 @@ efx_filter_fini(
 	__in		efx_nic_t *enp);
 
 extern	__checkReturn	int
-efx_rx_filter_insert(
-	__in		efx_rxq_t *erp,
+efx_filter_insert(
+	__in		efx_nic_t *enp,
 	__inout		efx_filter_spec_t *spec);
 
 extern	__checkReturn	int
-efx_rx_filter_remove(
-	__in		efx_rxq_t *erp,
+efx_filter_remove(
+	__in		efx_nic_t *enp,
 	__inout		efx_filter_spec_t *spec);
 
-			void
+extern	__checkReturn	int
 efx_filter_restore(
 	__in		efx_nic_t *enp);
 
-extern			void
-efx_filter_spec_rx_ipv4_tcp_full(
-	__inout		efx_filter_spec_t *spec,
-	__in		unsigned int flags,
-	__in		uint32_t src_ip,
-	__in		uint16_t src_tcp,
-	__in		uint32_t dest_ip,
-	__in		uint16_t dest_tcp);
+extern	__checkReturn	int
+efx_filter_supported_filters(
+	__in		efx_nic_t *enp,
+	__out		uint32_t *list,
+	__out		size_t *length);
 
 extern			void
-efx_filter_spec_rx_ipv4_tcp_wild(
+efx_filter_spec_init_rx(
 	__inout		efx_filter_spec_t *spec,
-	__in		unsigned int flags,
-	__in		uint32_t dest_ip,
-	__in		uint16_t dest_tcp);
+	__in		efx_filter_priority_t priority,
+	__in		efx_filter_flag_t flags,
+	__in		efx_rxq_t *erp);
 
 extern			void
-efx_filter_spec_rx_ipv4_udp_full(
+efx_filter_spec_init_tx(
 	__inout		efx_filter_spec_t *spec,
-	__in		unsigned int flags,
-	__in		uint32_t src_ip,
-	__in		uint16_t src_udp,
-	__in		uint32_t dest_ip,
-	__in		uint16_t dest_udp);
+	__in		efx_txq_t *etp);
 
-extern			void
-efx_filter_spec_rx_ipv4_udp_wild(
+extern	__checkReturn	int
+efx_filter_spec_set_ipv4_local(
 	__inout		efx_filter_spec_t *spec,
-	__in		unsigned int flags,
-	__in		uint32_t dest_ip,
-	__in		uint16_t dest_udp);
+	__in		uint8_t proto,
+	__in		uint32_t host,
+	__in		uint16_t port);
 
-extern			void
-efx_filter_spec_rx_mac_full(
+extern	__checkReturn	int
+efx_filter_spec_set_ipv4_full(
 	__inout		efx_filter_spec_t *spec,
-	__in		unsigned int flags,
-	__in		uint16_t vlan_id,
-	__in		uint8_t *dest_mac);
+	__in		uint8_t proto,
+	__in		uint32_t lhost,
+	__in		uint16_t lport,
+	__in		uint32_t rhost,
+	__in		uint16_t rport);
 
-extern			void
-efx_filter_spec_rx_mac_wild(
+extern	__checkReturn	int
+efx_filter_spec_set_eth_local(
 	__inout		efx_filter_spec_t *spec,
-	__in		unsigned int flags,
-	__in		uint8_t *dest_mac);
-
+	__in		uint16_t vid,
+	__in		const uint8_t *addr);
 
 extern	__checkReturn	int
-efx_tx_filter_insert(
-	__in		efx_txq_t *etp,
+efx_filter_spec_set_uc_def(
 	__inout		efx_filter_spec_t *spec);
 
 extern	__checkReturn	int
-efx_tx_filter_remove(
-	__in		efx_txq_t *etp,
+efx_filter_spec_set_mc_def(
 	__inout		efx_filter_spec_t *spec);
 
-extern			void
-efx_filter_spec_tx_ipv4_tcp_full(
-	__inout		efx_filter_spec_t *spec,
-	__in		uint32_t src_ip,
-	__in		uint16_t src_tcp,
-	__in		uint32_t dest_ip,
-	__in		uint16_t dest_tcp);
-
-extern			void
-efx_filter_spec_tx_ipv4_tcp_wild(
-	__inout		efx_filter_spec_t *spec,
-	__in		uint32_t src_ip,
-	__in		uint16_t src_tcp);
-
-extern			void
-efx_filter_spec_tx_ipv4_udp_full(
-	__inout		efx_filter_spec_t *spec,
-	__in		uint32_t src_ip,
-	__in		uint16_t src_udp,
-	__in		uint32_t dest_ip,
-	__in		uint16_t dest_udp);
-
-extern			void
-efx_filter_spec_tx_ipv4_udp_wild(
-	__inout		efx_filter_spec_t *spec,
-	__in		uint32_t src_ip,
-	__in		uint16_t src_udp);
+#endif	/* EFSYS_OPT_FILTER */
 
-extern			void
-efx_filter_spec_tx_mac_full(
-	__inout		efx_filter_spec_t *spec,
-	__in		uint16_t vlan_id,
-	__in		uint8_t *src_mac);
+/* HASH */
 
-extern			void
-efx_filter_spec_tx_mac_wild(
-	__inout		efx_filter_spec_t *spec,
-	__in		uint8_t *src_mac);
+extern	__checkReturn		uint32_t
+efx_hash_dwords(
+	__in_ecount(count)	uint32_t const *input,
+	__in			size_t count,
+	__in			uint32_t init);
 
-#endif	/* EFSYS_OPT_FILTER */
+extern	__checkReturn		uint32_t
+efx_hash_bytes(
+	__in_ecount(length)	uint8_t const *input,
+	__in			size_t length,
+	__in			uint32_t init);
 
 
 #ifdef	__cplusplus
diff --git a/sys/dev/sfxge/common/efx_bootcfg.c b/sys/dev/sfxge/common/efx_bootcfg.c
index d770a5c3cad0..330f69dbd5a9 100644
--- a/sys/dev/sfxge/common/efx_bootcfg.c
+++ b/sys/dev/sfxge/common/efx_bootcfg.c
@@ -1,26 +1,31 @@
 /*-
- * Copyright 2009 Solarflare Communications Inc.  All rights reserved.
+ * Copyright (c) 2009-2015 Solarflare Communications Inc.
+ * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
+ * modification, are permitted provided that the following conditions are met:
  *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are
+ * those of the authors and should not be interpreted as representing official
+ * policies, either expressed or implied, of the FreeBSD Project.
  */
 
 #include <sys/cdefs.h>
@@ -64,7 +69,7 @@ efx_bootcfg_verify(
 	__in			efx_nic_t *enp,
 	__in_bcount(size)	caddr_t data,
 	__in			size_t size,
-	__out			size_t *usedp)
+	__out_opt		size_t *usedp)
 {
 	size_t offset = 0;
 	size_t used = 0;
diff --git a/sys/dev/sfxge/common/efx_check.h b/sys/dev/sfxge/common/efx_check.h
new file mode 100644
index 000000000000..9e590a41d967
--- /dev/null
+++ b/sys/dev/sfxge/common/efx_check.h
@@ -0,0 +1,388 @@
+/*-
+ * Copyright (c) 2012-2015 Solarflare Communications Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are
+ * those of the authors and should not be interpreted as representing official
+ * policies, either expressed or implied, of the FreeBSD Project.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef _SYS_EFX_CHECK_H
+#define	_SYS_EFX_CHECK_H
+
+#include "efsys.h"
+
+/*
+ * Check that the efsys.h header in client code has a valid combination of
+ * EFSYS_OPT_xxx options.
+ *
+ * NOTE: Keep checks for obsolete options here to ensure that they are removed
+ * from client code (and do not reappear in merges from other branches).
+ */
+
+/* Support NVRAM based boot config */
+#if EFSYS_OPT_BOOTCFG
+# if !EFSYS_OPT_NVRAM
+#  error "BOOTCFG requires NVRAM"
+# endif
+#endif /* EFSYS_OPT_BOOTCFG */
+
+/* Verify chip implements accessed registers */
+#if EFSYS_OPT_CHECK_REG
+# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON)
+#  error "CHECK_REG requires FALCON or SIENA or HUNTINGTON"
+# endif
+#endif /* EFSYS_OPT_CHECK_REG */
+
+/* Decode fatal errors */
+#if EFSYS_OPT_DECODE_INTR_FATAL
+# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA)
+#  if EFSYS_OPT_HUNTINGTON
+#   error "INTR_FATAL not supported on HUNTINGTON"
+#  endif
+#  error "INTR_FATAL requires FALCON or SIENA"
+# endif
+#endif /* EFSYS_OPT_DECODE_INTR_FATAL */
+
+/* Support diagnostic hardware tests */
+#if EFSYS_OPT_DIAG
+# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON)
+#  error "DIAG requires FALCON or SIENA or HUNTINGTON"
+# endif
+#endif /* EFSYS_OPT_DIAG */
+
+/* Support optimized EVQ data access */
+#if EFSYS_OPT_EV_PREFETCH
+# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON)
+#  error "EV_PREFETCH requires FALCON or SIENA or HUNTINGTON"
+# endif
+#endif /* EFSYS_OPT_EV_PREFETCH */
+
+/* Support overriding the NVRAM and VPD configuration */
+#if EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE
+# if !EFSYS_OPT_FALCON
+#  error "FALCON_NIC_CFG_OVERRIDE requires FALCON"
+# endif
+#endif /* EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE */
+
+/* Support hardware packet filters */
+#if EFSYS_OPT_FILTER
+# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON)
+#  error "FILTER requires FALCON or SIENA or HUNTINGTON"
+# endif
+#endif /* EFSYS_OPT_FILTER */
+
+#if EFSYS_OPT_HUNTINGTON
+# if !EFSYS_OPT_FILTER
+#  error "HUNTINGTON requires FILTER"
+# endif
+#endif /* EFSYS_OPT_HUNTINGTON */
+
+/* Support hardware loopback modes */
+#if EFSYS_OPT_LOOPBACK
+# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON)
+#  error "LOOPBACK requires FALCON or SIENA or HUNTINGTON"
+# endif
+#endif /* EFSYS_OPT_LOOPBACK */
+
+/* Support Falcon GMAC */
+#if EFSYS_OPT_MAC_FALCON_GMAC
+# if !EFSYS_OPT_FALCON
+#  error "MAC_FALCON_GMAC requires FALCON"
+# endif
+#endif /* EFSYS_OPT_MAC_FALCON_GMAC */
+
+/* Support Falcon XMAC */
+#if EFSYS_OPT_MAC_FALCON_XMAC
+# if !EFSYS_OPT_FALCON
+#  error "MAC_FALCON_XMAC requires FALCON"
+# endif
+#endif /* EFSYS_OPT_MAC_FALCON_XMAC */
+
+/* Support MAC statistics */
+#if EFSYS_OPT_MAC_STATS
+# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON)
+#  error "MAC_STATS requires FALCON or SIENA or HUNTINGTON"
+# endif
+#endif /* EFSYS_OPT_MAC_STATS */
+
+/* Support management controller messages */
+#if EFSYS_OPT_MCDI
+# if !(EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON)
+#  if EFSYS_OPT_FALCON
+#   error "MCDI not supported on FALCON"
+#  endif
+#  error "MCDI requires SIENA or HUNTINGTON"
+# endif
+#endif /* EFSYS_OPT_MCDI */
+
+#if EFSYS_OPT_SIENA && !EFSYS_OPT_MCDI
+# error "SIENA requires MCDI"
+#endif
+#if EFSYS_OPT_HUNTINGTON && !EFSYS_OPT_MCDI
+# error "HUNTINGTON requires MCDI"
+#endif
+
+/* Support LM87 monitor */
+#if EFSYS_OPT_MON_LM87
+# if !EFSYS_OPT_FALCON
+#  error "MON_LM87 requires FALCON"
+# endif
+#endif /* EFSYS_OPT_MON_LM87 */
+
+/* Support MAX6647 monitor */
+#if EFSYS_OPT_MON_MAX6647
+# if !EFSYS_OPT_FALCON
+#  error "MON_MAX6647 requires FALCON"
+# endif
+#endif /* EFSYS_OPT_MON_MAX6647 */
+
+/* Support null monitor */
+#if EFSYS_OPT_MON_NULL
+# if !EFSYS_OPT_FALCON
+#  error "MON_NULL requires FALCON"
+# endif
+#endif /* EFSYS_OPT_MON_NULL */
+
+/* Support Siena monitor */
+#ifdef EFSYS_OPT_MON_SIENA
+#  error "MON_SIENA is obsolete use MON_MCDI"
+#endif /* EFSYS_OPT_MON_SIENA*/
+
+/* Support Huntington monitor */
+#ifdef EFSYS_OPT_MON_HUNTINGTON
+#  error "MON_HUNTINGTON is obsolete use MON_MCDI"
+#endif /* EFSYS_OPT_MON_HUNTINGTON*/
+
+/* Support monitor statistics (voltage/temperature) */
+#if EFSYS_OPT_MON_STATS
+# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON)
+#  error "MON_STATS requires FALCON or SIENA or HUNTINGTON"
+# endif
+#endif /* EFSYS_OPT_MON_STATS */
+
+/* Support Monitor via mcdi */
+#if EFSYS_OPT_MON_MCDI
+# if !(EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON)
+#  error "MON_MCDI requires SIENA or HUNTINGTON"
+# endif
+#endif /* EFSYS_OPT_MON_MCDI*/
+
+/* Support printable names for statistics */
+#if EFSYS_OPT_NAMES
+# if !(EFSYS_OPT_LOOPBACK || EFSYS_OPT_MAC_STATS || EFSYS_OPT_MCDI || \
+	EFSYS_MON_STATS || EFSYS_OPT_PHY_PROPS || EFSYS_OPT_PHY_STATS || \
+	EFSYS_OPT_QSTATS)
+#  error "NAMES requires LOOPBACK or xxxSTATS or MCDI or PHY_PROPS"
+# endif
+#endif /* EFSYS_OPT_NAMES */
+
+/* Support non volatile configuration */
+#if EFSYS_OPT_NVRAM
+# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON)
+#  error "NVRAM requires FALCON or SIENA or HUNTINGTON"
+# endif
+#endif /* EFSYS_OPT_NVRAM */
+
+/* Support Falcon bootrom */
+#if EFSYS_OPT_NVRAM_FALCON_BOOTROM
+# if !EFSYS_OPT_NVRAM
+#  error "NVRAM_FALCON_BOOTROM requires NVRAM"
+# endif
+# if !EFSYS_OPT_FALCON
+#  error "NVRAM_FALCON_BOOTROM requires FALCON"
+# endif
+#endif /* EFSYS_OPT_NVRAM_FALCON_BOOTROM */
+
+/* Support NVRAM config for SFT9001 */
+#if EFSYS_OPT_NVRAM_SFT9001
+# if !EFSYS_OPT_NVRAM
+#  error "NVRAM_SFT9001 requires NVRAM"
+# endif
+# if !EFSYS_OPT_FALCON
+#  error "NVRAM_SFT9001 requires FALCON"
+# endif
+#endif /* EFSYS_OPT_NVRAM_SFT9001 */
+
+/* Support NVRAM config for SFX7101 */
+#if EFSYS_OPT_NVRAM_SFX7101
+# if !EFSYS_OPT_NVRAM
+#  error "NVRAM_SFX7101 requires NVRAM"
+# endif
+# if !EFSYS_OPT_FALCON
+#  error "NVRAM_SFX7101 requires FALCON"
+# endif
+#endif /* EFSYS_OPT_NVRAM_SFX7101 */
+
+/* Support PCIe interface tuning */
+#if EFSYS_OPT_PCIE_TUNE
+# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA)
+#  error "PCIE_TUNE requires FALCON or SIENA"
+# endif
+#endif /* EFSYS_OPT_PCIE_TUNE */
+
+/* Support PHY BIST diagnostics */
+#if EFSYS_OPT_PHY_BIST
+#  error "PHY_BIST is obsolete. It has been replaced by the BIST option."
+#endif /* EFSYS_OPT_PHY_BIST */
+
+/* Support PHY flags */
+#if EFSYS_OPT_PHY_FLAGS
+# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA)
+#  error "PHY_FLAGS requires FALCON or SIENA"
+# endif
+#endif /* EFSYS_OPT_PHY_FLAGS */
+
+/* Support for PHY LED control */
+#if EFSYS_OPT_PHY_LED_CONTROL
+# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA)
+#  error "PHY_LED_CONTROL requires FALCON or SIENA"
+# endif
+#endif /* EFSYS_OPT_PHY_LED_CONTROL */
+
+/* Support NULL PHY */
+#if EFSYS_OPT_PHY_NULL
+# if !EFSYS_OPT_FALCON
+#  error "PHY_NULL requires FALCON"
+# endif
+#endif /* EFSYS_OPT_PHY_NULL */
+
+/* Obsolete option */
+#ifdef EFSYS_OPT_PHY_PM8358
+# error "EFSYS_OPT_PHY_PM8358 is obsolete and is not supported."
+#endif
+
+/* Support PHY properties */
+#if EFSYS_OPT_PHY_PROPS
+# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA)
+#  error "PHY_PROPS requires FALCON or SIENA"
+# endif
+#endif /* EFSYS_OPT_PHY_PROPS */
+
+/* Support QT2022C2 PHY */
+#if EFSYS_OPT_PHY_QT2022C2
+# if !EFSYS_OPT_FALCON
+#  error "PHY_QT2022C2 requires FALCON"
+# endif
+#endif /* EFSYS_OPT_PHY_QT2022C2 */
+
+/* Support QT2025C PHY (Wakefield NIC) */
+#if EFSYS_OPT_PHY_QT2025C
+# if !EFSYS_OPT_FALCON
+#  error "PHY_QT2025C requires FALCON"
+# endif
+#endif /* EFSYS_OPT_PHY_QT2025C */
+
+/* Support SFT9001 PHY (Starbolt NIC) */
+#if EFSYS_OPT_PHY_SFT9001
+# if !EFSYS_OPT_FALCON
+#  error "PHY_SFT9001 requires FALCON"
+# endif
+#endif /* EFSYS_OPT_PHY_SFT9001 */
+
+/* Support SFX7101 PHY (SFE4001 NIC) */
+#if EFSYS_OPT_PHY_SFX7101
+# if !EFSYS_OPT_FALCON
+#  error "PHY_SFX7101 requires FALCON"
+# endif
+#endif /* EFSYS_OPT_PHY_SFX7101 */
+
+/* Support PHY statistics */
+#if EFSYS_OPT_PHY_STATS
+# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA)
+#  error "PHY_STATS requires FALCON or SIENA"
+# endif
+#endif /* EFSYS_OPT_PHY_STATS */
+
+/* Support TXC43128 PHY (SFE4003 NIC) */
+#if EFSYS_OPT_PHY_TXC43128
+# if !EFSYS_OPT_FALCON
+#  error "PHY_TXC43128 requires FALCON"
+# endif
+#endif /* EFSYS_OPT_PHY_TXC43128 */
+
+/* Support EVQ/RXQ/TXQ statistics */
+#if EFSYS_OPT_QSTATS
+# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON)
+#  error "QSTATS requires FALCON or SIENA or HUNTINGTON"
+# endif
+#endif /* EFSYS_OPT_QSTATS */
+
+/* Support receive header split */
+#if EFSYS_OPT_RX_HDR_SPLIT
+# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON)
+#  error "RX_HDR_SPLIT requires FALCON or SIENA or HUNTINGTON"
+# endif
+#endif /* EFSYS_OPT_RX_HDR_SPLIT */
+
+/* Support receive scaling (RSS) */
+#if EFSYS_OPT_RX_SCALE
+# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON)
+#  error "RX_SCALE requires FALCON or SIENA or HUNTINGTON"
+# endif
+#endif /* EFSYS_OPT_RX_SCALE */
+
+/* Support receive scatter DMA */
+#if EFSYS_OPT_RX_SCATTER
+# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON)
+#  error "RX_SCATTER requires FALCON or SIENA or HUNTINGTON"
+# endif
+#endif /* EFSYS_OPT_RX_SCATTER */
+
+/* Obsolete option */
+#ifdef EFSYS_OPT_STAT_NAME
+# error "EFSYS_OPT_STAT_NAME is obsolete (replaced by EFSYS_OPT_NAMES)."
+#endif
+
+/* Support PCI Vital Product Data (VPD) */
+#if EFSYS_OPT_VPD
+# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON)
+#  error "VPD requires FALCON or SIENA or HUNTINGTON"
+# endif
+#endif /* EFSYS_OPT_VPD */
+
+/* Support Wake on LAN */
+#if EFSYS_OPT_WOL
+# if !EFSYS_OPT_SIENA
+#  error "WOL requires SIENA"
+# endif
+#endif /* EFSYS_OPT_WOL */
+
+/* Support calculating multicast pktfilter in common code */
+#if EFSYS_OPT_MCAST_FILTER_LIST
+# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON)
+#  error "MCAST_FILTER_LIST requires FALCON or SIENA or HUNTINGTON"
+# endif
+#endif /* EFSYS_OPT_MCAST_FILTER_LIST */
+
+/* Support BIST */
+#if EFSYS_OPT_BIST
+# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON)
+#  error "BIST requires FALCON or SIENA or HUNTINGTON"
+# endif
+#endif /* EFSYS_OPT_BIST */
+
+#endif /* _SYS_EFX_CHECK_H */
diff --git a/sys/dev/sfxge/common/efx_crc32.c b/sys/dev/sfxge/common/efx_crc32.c
new file mode 100644
index 000000000000..7e4cfc451336
--- /dev/null
+++ b/sys/dev/sfxge/common/efx_crc32.c
@@ -0,0 +1,127 @@
+/*-
+ * Copyright (c) 2013-2015 Solarflare Communications Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are
+ * those of the authors and should not be interpreted as representing official
+ * policies, either expressed or implied, of the FreeBSD Project.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include "efsys.h"
+#include "efx.h"
+#include "efx_types.h"
+#include "efx_impl.h"
+
+/*
+ * Precomputed table for computing IEEE 802.3 CRC32
+ * with polynomial 0x04c11db7 (bit-reversed 0xedb88320)
+ */
+
+static const uint32_t crc32_table[256] = {
+    0x00000000, 0x77073096, 0xee0e612c, 0x990951ba,
+    0x076dc419, 0x706af48f, 0xe963a535, 0x9e6495a3,
+    0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988,
+    0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91,
+    0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de,
+    0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,
+    0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec,
+    0x14015c4f, 0x63066cd9, 0xfa0f3d63, 0x8d080df5,
+    0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172,
+    0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b,
+    0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940,
+    0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,
+    0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116,
+    0x21b4f4b5, 0x56b3c423, 0xcfba9599, 0xb8bda50f,
+    0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924,
+    0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d,
+    0x76dc4190, 0x01db7106, 0x98d220bc, 0xefd5102a,
+    0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433,
+    0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818,
+    0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01,
+    0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e,
+    0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457,
+    0x65b0d9c6, 0x12b7e950, 0x8bbeb8ea, 0xfcb9887c,
+    0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,
+    0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2,
+    0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb,
+    0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0,
+    0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9,
+    0x5005713c, 0x270241aa, 0xbe0b1010, 0xc90c2086,
+    0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,
+    0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4,
+    0x59b33d17, 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad,
+    0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a,
+    0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683,
+    0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8,
+    0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1,
+    0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe,
+    0xf762575d, 0x806567cb, 0x196c3671, 0x6e6b06e7,
+    0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc,
+    0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5,
+    0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252,
+    0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,
+    0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60,
+    0xdf60efc3, 0xa867df55, 0x316e8eef, 0x4669be79,
+    0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,
+    0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f,
+    0xc5ba3bbe, 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04,
+    0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,
+    0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a,
+    0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713,
+    0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38,
+    0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21,
+    0x86d3d2d4, 0xf1d4e242, 0x68ddb3f8, 0x1fda836e,
+    0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,
+    0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c,
+    0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45,
+    0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2,
+    0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db,
+    0xaed16a4a, 0xd9d65adc, 0x40df0b66, 0x37d83bf0,
+    0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,
+    0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6,
+    0xbad03605, 0xcdd70693, 0x54de5729, 0x23d967bf,
+    0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94,
+    0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d
+};
+
+/* Calculate the IEEE 802.3 CRC32 of a MAC addr */
+	__checkReturn		uint32_t
+efx_crc32_calculate(
+	__in			uint32_t crc_init,
+	__in_ecount(length)	uint8_t const *input,
+	__in			int length)
+{
+	int index;
+	uint32_t crc = crc_init;
+
+	for (index = 0; index < length; index++) {
+		uint32_t data = *(input++);
+		crc = (crc >> 8) ^ crc32_table[(crc ^ data) & 0xff];
+	}
+
+	return (crc);
+}
diff --git a/sys/dev/sfxge/common/efx_ev.c b/sys/dev/sfxge/common/efx_ev.c
index fff7803a13d1..9669fc450c2c 100644
--- a/sys/dev/sfxge/common/efx_ev.c
+++ b/sys/dev/sfxge/common/efx_ev.c
@@ -1,26 +1,31 @@
 /*-
- * Copyright 2007-2009 Solarflare Communications Inc.  All rights reserved.
+ * Copyright (c) 2007-2015 Solarflare Communications Inc.
+ * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
+ * modification, are permitted provided that the following conditions are met:
  *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are
+ * those of the authors and should not be interpreted as representing official
+ * policies, either expressed or implied, of the FreeBSD Project.
  */
 
 #include <sys/cdefs.h>
@@ -31,6 +36,7 @@ __FBSDID("$FreeBSD$");
 #include "efx_types.h"
 #include "efx_regs.h"
 #include "efx_impl.h"
+#include "mcdi_mon.h"
 
 #if EFSYS_OPT_QSTATS
 #define	EFX_EV_QSTAT_INCR(_eep, _stat)					\
@@ -42,11 +48,118 @@ __FBSDID("$FreeBSD$");
 #define	EFX_EV_QSTAT_INCR(_eep, _stat)
 #endif
 
+#define	EFX_EV_PRESENT(_qword)						\
+	(EFX_QWORD_FIELD((_qword), EFX_DWORD_0) != 0xffffffff &&	\
+	EFX_QWORD_FIELD((_qword), EFX_DWORD_1) != 0xffffffff)
+
+
+
+#if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA
+
+static	__checkReturn	int
+falconsiena_ev_init(
+	__in		efx_nic_t *enp);
+
+static			void
+falconsiena_ev_fini(
+	__in		efx_nic_t *enp);
+
+static	__checkReturn	int
+falconsiena_ev_qcreate(
+	__in		efx_nic_t *enp,
+	__in		unsigned int index,
+	__in		efsys_mem_t *esmp,
+	__in		size_t n,
+	__in		uint32_t id,
+	__in		efx_evq_t *eep);
+
+static			void
+falconsiena_ev_qdestroy(
+	__in		efx_evq_t *eep);
+
+static	__checkReturn	int
+falconsiena_ev_qprime(
+	__in		efx_evq_t *eep,
+	__in		unsigned int count);
+
+static			void
+falconsiena_ev_qpoll(
+	__in		efx_evq_t *eep,
+	__inout		unsigned int *countp,
+	__in		const efx_ev_callbacks_t *eecp,
+	__in_opt	void *arg);
+
+static			void
+falconsiena_ev_qpost(
+	__in	efx_evq_t *eep,
+	__in	uint16_t data);
+
+static	__checkReturn	int
+falconsiena_ev_qmoderate(
+	__in		efx_evq_t *eep,
+	__in		unsigned int us);
+
+#if EFSYS_OPT_QSTATS
+static			void
+falconsiena_ev_qstats_update(
+	__in				efx_evq_t *eep,
+	__inout_ecount(EV_NQSTATS)	efsys_stat_t *stat);
+
+#endif
+
+#endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */
+
+#if EFSYS_OPT_FALCON
+static efx_ev_ops_t	__efx_ev_falcon_ops = {
+	falconsiena_ev_init,			/* eevo_init */
+	falconsiena_ev_fini,			/* eevo_fini */
+	falconsiena_ev_qcreate,			/* eevo_qcreate */
+	falconsiena_ev_qdestroy,		/* eevo_qdestroy */
+	falconsiena_ev_qprime,			/* eevo_qprime */
+	falconsiena_ev_qpost,			/* eevo_qpost */
+	falconsiena_ev_qmoderate,		/* eevo_qmoderate */
+#if EFSYS_OPT_QSTATS
+	falconsiena_ev_qstats_update,		/* eevo_qstats_update */
+#endif
+};
+#endif /* EFSYS_OPT_FALCON */
+
+#if EFSYS_OPT_SIENA
+static efx_ev_ops_t	__efx_ev_siena_ops = {
+	falconsiena_ev_init,			/* eevo_init */
+	falconsiena_ev_fini,			/* eevo_fini */
+	falconsiena_ev_qcreate,			/* eevo_qcreate */
+	falconsiena_ev_qdestroy,		/* eevo_qdestroy */
+	falconsiena_ev_qprime,			/* eevo_qprime */
+	falconsiena_ev_qpost,			/* eevo_qpost */
+	falconsiena_ev_qmoderate,		/* eevo_qmoderate */
+#if EFSYS_OPT_QSTATS
+	falconsiena_ev_qstats_update,		/* eevo_qstats_update */
+#endif
+};
+#endif /* EFSYS_OPT_SIENA */
+
+#if EFSYS_OPT_HUNTINGTON
+static efx_ev_ops_t	__efx_ev_hunt_ops = {
+	hunt_ev_init,				/* eevo_init */
+	hunt_ev_fini,				/* eevo_fini */
+	hunt_ev_qcreate,			/* eevo_qcreate */
+	hunt_ev_qdestroy,			/* eevo_qdestroy */
+	hunt_ev_qprime,				/* eevo_qprime */
+	hunt_ev_qpost,				/* eevo_qpost */
+	hunt_ev_qmoderate,			/* eevo_qmoderate */
+#if EFSYS_OPT_QSTATS
+	hunt_ev_qstats_update,			/* eevo_qstats_update */
+#endif
+};
+#endif /* EFSYS_OPT_HUNTINGTON */
+
+
 	__checkReturn	int
 efx_ev_init(
 	__in		efx_nic_t *enp)
 {
-	efx_oword_t oword;
+	efx_ev_ops_t *eevop;
 	int rc;
 
 	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
@@ -57,8 +170,290 @@ efx_ev_init(
 		goto fail1;
 	}
 
+	switch (enp->en_family) {
+#if EFSYS_OPT_FALCON
+	case EFX_FAMILY_FALCON:
+		eevop = (efx_ev_ops_t *)&__efx_ev_falcon_ops;
+		break;
+#endif /* EFSYS_OPT_FALCON */
+
+#if EFSYS_OPT_SIENA
+	case EFX_FAMILY_SIENA:
+		eevop = (efx_ev_ops_t *)&__efx_ev_siena_ops;
+		break;
+#endif /* EFSYS_OPT_SIENA */
+
+#if EFSYS_OPT_HUNTINGTON
+	case EFX_FAMILY_HUNTINGTON:
+		eevop = (efx_ev_ops_t *)&__efx_ev_hunt_ops;
+		break;
+#endif /* EFSYS_OPT_HUNTINGTON */
+
+	default:
+		EFSYS_ASSERT(0);
+		rc = ENOTSUP;
+		goto fail1;
+	}
+
 	EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
 
+	if ((rc = eevop->eevo_init(enp)) != 0)
+		goto fail2;
+
+	enp->en_eevop = eevop;
+	enp->en_mod_flags |= EFX_MOD_EV;
+	return (0);
+
+fail2:
+	EFSYS_PROBE(fail2);
+
+fail1:
+	EFSYS_PROBE1(fail1, int, rc);
+
+	enp->en_eevop = NULL;
+	enp->en_mod_flags &= ~EFX_MOD_EV;
+	return (rc);
+}
+
+		void
+efx_ev_fini(
+	__in	efx_nic_t *enp)
+{
+	efx_ev_ops_t *eevop = enp->en_eevop;
+
+	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
+	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
+	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
+	EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
+	EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
+	EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
+
+	eevop->eevo_fini(enp);
+
+	enp->en_eevop = NULL;
+	enp->en_mod_flags &= ~EFX_MOD_EV;
+}
+
+
+	__checkReturn	int
+efx_ev_qcreate(
+	__in		efx_nic_t *enp,
+	__in		unsigned int index,
+	__in		efsys_mem_t *esmp,
+	__in		size_t n,
+	__in		uint32_t id,
+	__deref_out	efx_evq_t **eepp)
+{
+	efx_ev_ops_t *eevop = enp->en_eevop;
+	efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
+	efx_evq_t *eep;
+	int rc;
+
+	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
+	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
+
+	EFSYS_ASSERT3U(enp->en_ev_qcount + 1, <, encp->enc_evq_limit);
+
+	/* Allocate an EVQ object */
+	EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_evq_t), eep);
+	if (eep == NULL) {
+		rc = ENOMEM;
+		goto fail1;
+	}
+
+	eep->ee_magic = EFX_EVQ_MAGIC;
+	eep->ee_enp = enp;
+	eep->ee_index = index;
+	eep->ee_mask = n - 1;
+	eep->ee_esmp = esmp;
+
+	if ((rc = eevop->eevo_qcreate(enp, index, esmp, n, id, eep)) != 0)
+		goto fail2;
+
+	enp->en_ev_qcount++;
+	*eepp = eep;
+
+	return (0);
+
+fail2:
+	EFSYS_PROBE(fail2);
+	EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
+fail1:
+	EFSYS_PROBE1(fail1, int, rc);
+	return (rc);
+}
+
+		void
+efx_ev_qdestroy(
+	__in	efx_evq_t *eep)
+{
+	efx_nic_t *enp = eep->ee_enp;
+	efx_ev_ops_t *eevop = enp->en_eevop;
+
+	EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
+
+	EFSYS_ASSERT(enp->en_ev_qcount != 0);
+	--enp->en_ev_qcount;
+
+	eevop->eevo_qdestroy(eep);
+
+	/* Free the EVQ object */
+	EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
+}
+
+	__checkReturn	int
+efx_ev_qprime(
+	__in		efx_evq_t *eep,
+	__in		unsigned int count)
+{
+	efx_nic_t *enp = eep->ee_enp;
+	efx_ev_ops_t *eevop = enp->en_eevop;
+	int rc;
+
+	EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
+
+	if (!(enp->en_mod_flags & EFX_MOD_INTR)) {
+		rc = EINVAL;
+		goto fail1;
+	}
+
+	if ((rc = eevop->eevo_qprime(eep, count)) != 0)
+		goto fail2;
+
+	return (0);
+
+fail2:
+	EFSYS_PROBE(fail2);
+fail1:
+	EFSYS_PROBE1(fail1, int, rc);
+	return (rc);
+}
+
+	__checkReturn	boolean_t
+efx_ev_qpending(
+	__in		efx_evq_t *eep,
+	__in		unsigned int count)
+{
+	size_t offset;
+	efx_qword_t qword;
+
+	EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
+
+	offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
+	EFSYS_MEM_READQ(eep->ee_esmp, offset, &qword);
+
+	return (EFX_EV_PRESENT(qword));
+}
+
+#if EFSYS_OPT_EV_PREFETCH
+
+			void
+efx_ev_qprefetch(
+	__in		efx_evq_t *eep,
+	__in		unsigned int count)
+{
+	efx_nic_t *enp = eep->ee_enp;
+	unsigned int offset;
+
+	EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
+
+	offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
+	EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
+}
+
+#endif	/* EFSYS_OPT_EV_PREFETCH */
+
+			void
+efx_ev_qpoll(
+	__in		efx_evq_t *eep,
+	__inout		unsigned int *countp,
+	__in		const efx_ev_callbacks_t *eecp,
+	__in_opt	void *arg)
+{
+	EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
+
+	/*
+	 * FIXME: Huntington will require support for hardware event batching
+	 * and merging, which will need a different ev_qpoll implementation.
+	 *
+	 * Without those features the Falcon/Siena code can be used unchanged.
+	 */
+	EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_LBN == FSF_AZ_EV_CODE_LBN);
+	EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_WIDTH == FSF_AZ_EV_CODE_WIDTH);
+
+	EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_RX_EV == FSE_AZ_EV_CODE_RX_EV);
+	EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_TX_EV == FSE_AZ_EV_CODE_TX_EV);
+	EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRIVER_EV == FSE_AZ_EV_CODE_DRIVER_EV);
+	EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRV_GEN_EV ==
+	    FSE_AZ_EV_CODE_DRV_GEN_EV);
+#if EFSYS_OPT_MCDI
+	EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_MCDI_EV ==
+	    FSE_AZ_EV_CODE_MCDI_EVRESPONSE);
+#endif
+	falconsiena_ev_qpoll(eep, countp, eecp, arg);
+}
+
+			void
+efx_ev_qpost(
+	__in	efx_evq_t *eep,
+	__in	uint16_t data)
+{
+	efx_nic_t *enp = eep->ee_enp;
+	efx_ev_ops_t *eevop = enp->en_eevop;
+
+	EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
+
+	EFSYS_ASSERT(eevop != NULL &&
+	    eevop->eevo_qpost != NULL);
+
+	eevop->eevo_qpost(eep, data);
+}
+
+	__checkReturn	int
+efx_ev_qmoderate(
+	__in		efx_evq_t *eep,
+	__in		unsigned int us)
+{
+	efx_nic_t *enp = eep->ee_enp;
+	efx_ev_ops_t *eevop = enp->en_eevop;
+	int rc;
+
+	EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
+
+	if ((rc = eevop->eevo_qmoderate(eep, us)) != 0)
+		goto fail1;
+
+	return (0);
+
+fail1:
+	EFSYS_PROBE1(fail1, int, rc);
+	return (rc);
+}
+
+#if EFSYS_OPT_QSTATS
+					void
+efx_ev_qstats_update(
+	__in				efx_evq_t *eep,
+	__inout_ecount(EV_NQSTATS)	efsys_stat_t *stat)
+
+{	efx_nic_t *enp = eep->ee_enp;
+	efx_ev_ops_t *eevop = enp->en_eevop;
+
+	EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
+
+	eevop->eevo_qstats_update(eep, stat);
+}
+
+#endif	/* EFSYS_OPT_QSTATS */
+
+#if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA
+
+static	__checkReturn	int
+falconsiena_ev_init(
+	__in		efx_nic_t *enp)
+{
+	efx_oword_t oword;
+
 	/*
 	 * Program the event queue for receive and transmit queue
 	 * flush events.
@@ -67,17 +462,12 @@ efx_ev_init(
 	EFX_SET_OWORD_FIELD(oword, FRF_AZ_FLS_EVQ_ID, 0);
 	EFX_BAR_WRITEO(enp, FR_AZ_DP_CTRL_REG, &oword);
 
-	enp->en_mod_flags |= EFX_MOD_EV;
 	return (0);
 
-fail1:
-	EFSYS_PROBE1(fail1, int, rc);
-
-	return (rc);
 }
 
 static  __checkReturn   boolean_t
-efx_ev_rx_not_ok(
+falconsiena_ev_rx_not_ok(
 	__in		efx_evq_t *eep,
 	__in		efx_qword_t *eqp,
 	__in		uint32_t label,
@@ -167,7 +557,7 @@ efx_ev_rx_not_ok(
 }
 
 static	__checkReturn	boolean_t
-efx_ev_rx(
+falconsiena_ev_rx(
 	__in		efx_evq_t *eep,
 	__in		efx_qword_t *eqp,
 	__in		const efx_ev_callbacks_t *eecp,
@@ -264,7 +654,7 @@ efx_ev_rx(
 
 	/* Detect errors included in the FSF_AZ_RX_EV_PKT_OK indication */
 	if (!ok) {
-		ignore = efx_ev_rx_not_ok(eep, eqp, label, id, &flags);
+		ignore = falconsiena_ev_rx_not_ok(eep, eqp, label, id, &flags);
 		if (ignore) {
 			EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
 			    uint32_t, size, uint16_t, flags);
@@ -323,7 +713,7 @@ efx_ev_rx(
 }
 
 static	__checkReturn	boolean_t
-efx_ev_tx(
+falconsiena_ev_tx(
 	__in		efx_evq_t *eep,
 	__in		efx_qword_t *eqp,
 	__in		const efx_ev_callbacks_t *eecp,
@@ -370,7 +760,7 @@ efx_ev_tx(
 }
 
 static	__checkReturn	boolean_t
-efx_ev_global(
+falconsiena_ev_global(
 	__in		efx_evq_t *eep,
 	__in		efx_qword_t *eqp,
 	__in		const efx_ev_callbacks_t *eecp,
@@ -396,7 +786,7 @@ efx_ev_global(
 }
 
 static	__checkReturn	boolean_t
-efx_ev_driver(
+falconsiena_ev_driver(
 	__in		efx_evq_t *eep,
 	__in		efx_qword_t *eqp,
 	__in		const efx_ev_callbacks_t *eecp,
@@ -437,7 +827,8 @@ efx_ev_driver(
 
 			EFSYS_PROBE1(rx_descq_fls_failed, uint32_t, rxq_index);
 
-			should_abort = eecp->eec_rxq_flush_failed(arg, rxq_index);
+			should_abort = eecp->eec_rxq_flush_failed(arg,
+								    rxq_index);
 		} else {
 			EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_DONE);
 
@@ -524,7 +915,7 @@ efx_ev_driver(
 }
 
 static	__checkReturn	boolean_t
-efx_ev_drv_gen(
+falconsiena_ev_drv_gen(
 	__in		efx_evq_t *eep,
 	__in		efx_qword_t *eqp,
 	__in		const efx_ev_callbacks_t *eecp,
@@ -552,7 +943,7 @@ efx_ev_drv_gen(
 #if EFSYS_OPT_MCDI
 
 static	__checkReturn	boolean_t
-efx_ev_mcdi(
+falconsiena_ev_mcdi(
 	__in		efx_evq_t *eep,
 	__in		efx_qword_t *eqp,
 	__in		const efx_ev_callbacks_t *eecp,
@@ -583,9 +974,9 @@ efx_ev_mcdi(
 
 	case MCDI_EVENT_CODE_CMDDONE:
 		efx_mcdi_ev_cpl(enp,
-				MCDI_EV_FIELD(eqp, CMDDONE_SEQ),
-				MCDI_EV_FIELD(eqp, CMDDONE_DATALEN),
-				MCDI_EV_FIELD(eqp, CMDDONE_ERRNO));
+		    MCDI_EV_FIELD(eqp, CMDDONE_SEQ),
+		    MCDI_EV_FIELD(eqp, CMDDONE_DATALEN),
+		    MCDI_EV_FIELD(eqp, CMDDONE_ERRNO));
 		break;
 
 	case MCDI_EVENT_CODE_LINKCHANGE: {
@@ -601,7 +992,7 @@ efx_ev_mcdi(
 		efx_mon_stat_value_t value;
 		int rc;
 
-		if ((rc = siena_mon_ev(enp, eqp, &id, &value)) == 0)
+		if ((rc = mcdi_mon_ev(enp, eqp, &id, &value)) == 0)
 			should_abort = eecp->eec_monitor(arg, id, value);
 		else if (rc == ENOTSUP) {
 			should_abort = eecp->eec_exception(arg,
@@ -656,22 +1047,14 @@ out:
 
 #endif	/* EFSYS_OPT_MCDI */
 
-	__checkReturn	int
-efx_ev_qprime(
+static	__checkReturn	int
+falconsiena_ev_qprime(
 	__in		efx_evq_t *eep,
 	__in		unsigned int count)
 {
 	efx_nic_t *enp = eep->ee_enp;
 	uint32_t rptr;
 	efx_dword_t dword;
-	int rc;
-
-	EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
-
-	if (!(enp->en_mod_flags & EFX_MOD_INTR)) {
-		rc = EINVAL;
-		goto fail1;
-	}
 
 	rptr = count & eep->ee_mask;
 
@@ -681,55 +1064,12 @@ efx_ev_qprime(
 			    &dword, B_FALSE);
 
 	return (0);
-
-fail1:
-	EFSYS_PROBE1(fail1, int, rc);
-
-	return (rc);
-}
-
-	__checkReturn	boolean_t
-efx_ev_qpending(
-	__in		efx_evq_t *eep,
-	__in		unsigned int count)
-{
-	size_t offset;
-	efx_qword_t qword;
-
-	EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
-
-	offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
-	EFSYS_MEM_READQ(eep->ee_esmp, offset, &qword);
-
-	return (EFX_QWORD_FIELD(qword, EFX_DWORD_0) != 0xffffffff &&
-		EFX_QWORD_FIELD(qword, EFX_DWORD_1) != 0xffffffff);
-}
-
-#if EFSYS_OPT_EV_PREFETCH
-
-			void
-efx_ev_qprefetch(
-	__in		efx_evq_t *eep,
-	__in		unsigned int count)
-{
-	unsigned int offset;
-
-	EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
-
-	offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
-	EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
 }
 
-#endif	/* EFSYS_OPT_EV_PREFETCH */
-
 #define	EFX_EV_BATCH	8
 
-#define	EFX_EV_PRESENT(_qword)						\
-	(EFX_QWORD_FIELD((_qword), EFX_DWORD_0) != 0xffffffff &&	\
-	EFX_QWORD_FIELD((_qword), EFX_DWORD_1) != 0xffffffff)
-
-			void
-efx_ev_qpoll(
+static			void
+falconsiena_ev_qpoll(
 	__in		efx_evq_t *eep,
 	__inout		unsigned int *countp,
 	__in		const efx_ev_callbacks_t *eecp,
@@ -742,7 +1082,6 @@ efx_ev_qpoll(
 	unsigned int index;
 	size_t offset;
 
-	EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 	EFSYS_ASSERT(countp != NULL);
 	EFSYS_ASSERT(eecp != NULL);
 
@@ -778,7 +1117,6 @@ efx_ev_qpoll(
 		for (index = 0; index < total; ++index) {
 			boolean_t should_abort;
 			uint32_t code;
-			efx_ev_handler_t handler;
 
 #if EFSYS_OPT_EV_PREFETCH
 			/* Prefetch if we've now reached the batch period */
@@ -794,9 +1132,49 @@ efx_ev_qpoll(
 			EFX_EV_QSTAT_INCR(eep, EV_ALL);
 
 			code = EFX_QWORD_FIELD(ev[index], FSF_AZ_EV_CODE);
-			handler = eep->ee_handler[code];
-			EFSYS_ASSERT(handler != NULL);
-			should_abort = handler(eep, &(ev[index]), eecp, arg);
+			switch (code) {
+			case FSE_AZ_EV_CODE_RX_EV:
+				should_abort = eep->ee_rx(eep,
+				    &(ev[index]), eecp, arg);
+				break;
+			case FSE_AZ_EV_CODE_TX_EV:
+				should_abort = eep->ee_tx(eep,
+				    &(ev[index]), eecp, arg);
+				break;
+			case FSE_AZ_EV_CODE_DRIVER_EV:
+				should_abort = eep->ee_driver(eep,
+				    &(ev[index]), eecp, arg);
+				break;
+			case FSE_AZ_EV_CODE_DRV_GEN_EV:
+				should_abort = eep->ee_drv_gen(eep,
+				    &(ev[index]), eecp, arg);
+				break;
+#if EFSYS_OPT_MCDI
+			case FSE_AZ_EV_CODE_MCDI_EVRESPONSE:
+				should_abort = eep->ee_mcdi(eep,
+				    &(ev[index]), eecp, arg);
+				break;
+#endif
+			case FSE_AZ_EV_CODE_GLOBAL_EV:
+				if (eep->ee_global) {
+					should_abort = eep->ee_global(eep,
+					    &(ev[index]), eecp, arg);
+					break;
+				}
+				/* else fallthrough */
+			default:
+				EFSYS_PROBE3(bad_event,
+				    unsigned int, eep->ee_index,
+				    uint32_t,
+				    EFX_QWORD_FIELD(ev[index], EFX_DWORD_1),
+				    uint32_t,
+				    EFX_QWORD_FIELD(ev[index], EFX_DWORD_0));
+
+				EFSYS_ASSERT(eecp->eec_exception != NULL);
+				(void) eecp->eec_exception(arg,
+					EFX_EXCEPTION_EV_ERROR, code);
+				should_abort = B_TRUE;
+			}
 			if (should_abort) {
 				/* Ignore subsequent events */
 				total = index + 1;
@@ -823,8 +1201,8 @@ efx_ev_qpoll(
 	*countp = count;
 }
 
-		void
-efx_ev_qpost(
+static		void
+falconsiena_ev_qpost(
 	__in	efx_evq_t *eep,
 	__in	uint16_t data)
 {
@@ -832,8 +1210,6 @@ efx_ev_qpost(
 	efx_qword_t ev;
 	efx_oword_t oword;
 
-	EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
-
 	EFX_POPULATE_QWORD_2(ev, FSF_AZ_EV_CODE, FSE_AZ_EV_CODE_DRV_GEN_EV,
 	    FSF_AZ_EV_DATA_DW0, (uint32_t)data);
 
@@ -844,8 +1220,8 @@ efx_ev_qpost(
 	EFX_BAR_WRITEO(enp, FR_AZ_DRV_EV_REG, &oword);
 }
 
-	__checkReturn	int
-efx_ev_qmoderate(
+static	__checkReturn	int
+falconsiena_ev_qmoderate(
 	__in		efx_evq_t *eep,
 	__in		unsigned int us)
 {
@@ -855,8 +1231,6 @@ efx_ev_qmoderate(
 	efx_dword_t dword;
 	int rc;
 
-	EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
-
 	if (us > encp->enc_evq_timer_max_us) {
 		rc = EINVAL;
 		goto fail1;
@@ -905,27 +1279,24 @@ fail1:
 	return (rc);
 }
 
-	__checkReturn	int
-efx_ev_qcreate(
+static	__checkReturn	int
+falconsiena_ev_qcreate(
 	__in		efx_nic_t *enp,
 	__in		unsigned int index,
 	__in		efsys_mem_t *esmp,
 	__in		size_t n,
 	__in		uint32_t id,
-	__deref_out	efx_evq_t **eepp)
+	__in		efx_evq_t *eep)
 {
 	efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
 	uint32_t size;
-	efx_evq_t *eep;
 	efx_oword_t oword;
 	int rc;
 
-	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
-	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
+	EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MAXNEVS));
+	EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MINNEVS));
 
-	EFSYS_ASSERT3U(enp->en_ev_qcount + 1, <, encp->enc_evq_limit);
-
-	if (!ISP2(n) || !(n & EFX_EVQ_NEVS_MASK)) {
+	if (!ISP2(n) || (n < EFX_EVQ_MINNEVS) || (n > EFX_EVQ_MAXNEVS)) {
 		rc = EINVAL;
 		goto fail1;
 	}
@@ -949,46 +1320,29 @@ efx_ev_qcreate(
 		goto fail4;
 	}
 
-	/* Allocate an EVQ object */
-	EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_evq_t), eep);
-	if (eep == NULL) {
-		rc = ENOMEM;
-		goto fail5;
-	}
-
-	eep->ee_magic = EFX_EVQ_MAGIC;
-	eep->ee_enp = enp;
-	eep->ee_index = index;
-	eep->ee_mask = n - 1;
-	eep->ee_esmp = esmp;
-
 	/* Set up the handler table */
-	eep->ee_handler[FSE_AZ_EV_CODE_RX_EV] = efx_ev_rx;
-	eep->ee_handler[FSE_AZ_EV_CODE_TX_EV] = efx_ev_tx;
-	eep->ee_handler[FSE_AZ_EV_CODE_DRIVER_EV] = efx_ev_driver;
-	eep->ee_handler[FSE_AZ_EV_CODE_GLOBAL_EV] = efx_ev_global;
-	eep->ee_handler[FSE_AZ_EV_CODE_DRV_GEN_EV] = efx_ev_drv_gen;
+	eep->ee_rx	= falconsiena_ev_rx;
+	eep->ee_tx	= falconsiena_ev_tx;
+	eep->ee_driver	= falconsiena_ev_driver;
+	eep->ee_global	= falconsiena_ev_global;
+	eep->ee_drv_gen	= falconsiena_ev_drv_gen;
 #if EFSYS_OPT_MCDI
-	eep->ee_handler[FSE_AZ_EV_CODE_MCDI_EVRESPONSE] = efx_ev_mcdi;
+	eep->ee_mcdi	= falconsiena_ev_mcdi;
 #endif	/* EFSYS_OPT_MCDI */
 
 	/* Set up the new event queue */
 	if (enp->en_family != EFX_FAMILY_FALCON) {
 		EFX_POPULATE_OWORD_1(oword, FRF_CZ_TIMER_Q_EN, 1);
-		EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, index, &oword);
+		EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, index, &oword, B_TRUE);
 	}
 
 	EFX_POPULATE_OWORD_3(oword, FRF_AZ_EVQ_EN, 1, FRF_AZ_EVQ_SIZE, size,
 	    FRF_AZ_EVQ_BUF_BASE_ID, id);
 
-	EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL, index, &oword);
+	EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL, index, &oword, B_TRUE);
 
-	enp->en_ev_qcount++;
-	*eepp = eep;
 	return (0);
 
-fail5:
-	EFSYS_PROBE(fail5);
 fail4:
 	EFSYS_PROBE(fail4);
 #if EFSYS_OPT_RX_SCALE
@@ -1003,14 +1357,15 @@ fail1:
 	return (rc);
 }
 
+#endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */
+
 #if EFSYS_OPT_QSTATS
 #if EFSYS_OPT_NAMES
-/* START MKCONFIG GENERATED EfxEventQueueStatNamesBlock 67e9bdcd920059bd */
-static const char 	__cs * __cs __efx_ev_qstat_name[] = {
+/* START MKCONFIG GENERATED EfxEventQueueStatNamesBlock b693ddf85aee1bfd */
+static const char 	*__efx_ev_qstat_name[] = {
 	"all",
 	"rx",
 	"rx_ok",
-	"rx_recovery",
 	"rx_frm_trunc",
 	"rx_tobe_disc",
 	"rx_pause_frm_err",
@@ -1028,16 +1383,14 @@ static const char 	__cs * __cs __efx_ev_qstat_name[] = {
 	"rx_other_ipv4",
 	"rx_other_ipv6",
 	"rx_non_ip",
-	"rx_overrun",
+	"rx_batch",
 	"tx",
 	"tx_wq_ff_full",
 	"tx_pkt_err",
 	"tx_pkt_too_big",
 	"tx_unexpected",
 	"global",
-	"global_phy",
 	"global_mnt",
-	"global_rx_recovery",
 	"driver",
 	"driver_srm_upd_done",
 	"driver_tx_descq_fls_done",
@@ -1050,7 +1403,7 @@ static const char 	__cs * __cs __efx_ev_qstat_name[] = {
 };
 /* END MKCONFIG GENERATED EfxEventQueueStatNamesBlock */
 
-		const char __cs *
+		const char *
 efx_ev_qstat_name(
 	__in	efx_nic_t *enp,
 	__in	unsigned int id)
@@ -1063,16 +1416,16 @@ efx_ev_qstat_name(
 #endif	/* EFSYS_OPT_NAMES */
 #endif	/* EFSYS_OPT_QSTATS */
 
+#if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA
+
 #if EFSYS_OPT_QSTATS
-					void
-efx_ev_qstats_update(
+static					void
+falconsiena_ev_qstats_update(
 	__in				efx_evq_t *eep,
 	__inout_ecount(EV_NQSTATS)	efsys_stat_t *stat)
 {
 	unsigned int id;
 
-	EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
-
 	for (id = 0; id < EV_NQSTATS; id++) {
 		efsys_stat_t *essp = &stat[id];
 
@@ -1082,44 +1435,31 @@ efx_ev_qstats_update(
 }
 #endif	/* EFSYS_OPT_QSTATS */
 
-		void
-efx_ev_qdestroy(
+static		void
+falconsiena_ev_qdestroy(
 	__in	efx_evq_t *eep)
 {
 	efx_nic_t *enp = eep->ee_enp;
 	efx_oword_t oword;
 
-	EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
-
-	EFSYS_ASSERT(enp->en_ev_qcount != 0);
-	--enp->en_ev_qcount;
-
 	/* Purge event queue */
 	EFX_ZERO_OWORD(oword);
 
 	EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL,
-	    eep->ee_index, &oword);
+	    eep->ee_index, &oword, B_TRUE);
 
 	if (enp->en_family != EFX_FAMILY_FALCON) {
 		EFX_ZERO_OWORD(oword);
 		EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL,
-		    eep->ee_index, &oword);
+		    eep->ee_index, &oword, B_TRUE);
 	}
-
-	/* Free the EVQ object */
-	EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
 }
 
-		void
-efx_ev_fini(
+static		void
+falconsiena_ev_fini(
 	__in	efx_nic_t *enp)
 {
-	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
-	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
-	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
-	EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
-	EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
-	EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
-
-	enp->en_mod_flags &= ~EFX_MOD_EV;
+	_NOTE(ARGUNUSED(enp))
 }
+
+#endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */
diff --git a/sys/dev/sfxge/common/efx_filter.c b/sys/dev/sfxge/common/efx_filter.c
index e8455db47c32..7ae7ea583e8f 100644
--- a/sys/dev/sfxge/common/efx_filter.c
+++ b/sys/dev/sfxge/common/efx_filter.c
@@ -1,26 +1,31 @@
 /*-
- * Copyright 2007-2009 Solarflare Communications Inc.  All rights reserved.
+ * Copyright (c) 2007-2015 Solarflare Communications Inc.
+ * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
+ * modification, are permitted provided that the following conditions are met:
  *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are
+ * those of the authors and should not be interpreted as representing official
+ * policies, either expressed or implied, of the FreeBSD Project.
  */
 
 #include <sys/cdefs.h>
@@ -35,24 +40,569 @@ __FBSDID("$FreeBSD$");
 
 #if EFSYS_OPT_FILTER
 
-/* "Fudge factors" - difference between programmed value and actual depth.
+#if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA
+
+static	__checkReturn	int
+falconsiena_filter_init(
+	__in		efx_nic_t *enp);
+
+static			void
+falconsiena_filter_fini(
+	__in		efx_nic_t *enp);
+
+static	__checkReturn	int
+falconsiena_filter_restore(
+	__in		efx_nic_t *enp);
+
+static	__checkReturn	int
+falconsiena_filter_add(
+	__in		efx_nic_t *enp,
+	__inout		efx_filter_spec_t *spec,
+	__in		boolean_t may_replace);
+
+static	__checkReturn	int
+falconsiena_filter_delete(
+	__in		efx_nic_t *enp,
+	__inout		efx_filter_spec_t *spec);
+
+static	__checkReturn	int
+falconsiena_filter_supported_filters(
+	__in		efx_nic_t *enp,
+	__out		uint32_t *list,
+	__out		size_t *length);
+
+#endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */
+
+#if EFSYS_OPT_FALCON
+static efx_filter_ops_t	__efx_filter_falcon_ops = {
+	falconsiena_filter_init,		/* efo_init */
+	falconsiena_filter_fini,		/* efo_fini */
+	falconsiena_filter_restore,		/* efo_restore */
+	falconsiena_filter_add,			/* efo_add */
+	falconsiena_filter_delete,		/* efo_delete */
+	falconsiena_filter_supported_filters,	/* efo_supported_filters */
+	NULL,					/* efo_reconfigure */
+};
+#endif /* EFSYS_OPT_FALCON */
+
+#if EFSYS_OPT_SIENA
+static efx_filter_ops_t	__efx_filter_siena_ops = {
+	falconsiena_filter_init,		/* efo_init */
+	falconsiena_filter_fini,		/* efo_fini */
+	falconsiena_filter_restore,		/* efo_restore */
+	falconsiena_filter_add,			/* efo_add */
+	falconsiena_filter_delete,		/* efo_delete */
+	falconsiena_filter_supported_filters,	/* efo_supported_filters */
+	NULL,					/* efo_reconfigure */
+};
+#endif /* EFSYS_OPT_SIENA */
+
+#if EFSYS_OPT_HUNTINGTON
+static efx_filter_ops_t	__efx_filter_hunt_ops = {
+	hunt_filter_init,		/* efo_init */
+	hunt_filter_fini,		/* efo_fini */
+	hunt_filter_restore,		/* efo_restore */
+	hunt_filter_add,		/* efo_add */
+	hunt_filter_delete,		/* efo_delete */
+	hunt_filter_supported_filters,	/* efo_supported_filters */
+	hunt_filter_reconfigure,	/* efo_reconfigure */
+};
+#endif /* EFSYS_OPT_HUNTINGTON */
+
+	__checkReturn	int
+efx_filter_insert(
+	__in		efx_nic_t *enp,
+	__inout		efx_filter_spec_t *spec)
+{
+	efx_filter_ops_t *efop = enp->en_efop;
+
+	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_FILTER);
+	EFSYS_ASSERT3P(spec, !=, NULL);
+	EFSYS_ASSERT3U(spec->efs_flags, &, EFX_FILTER_FLAG_RX);
+
+	return (efop->efo_add(enp, spec, B_FALSE));
+}
+
+	__checkReturn	int
+efx_filter_remove(
+	__in		efx_nic_t *enp,
+	__inout		efx_filter_spec_t *spec)
+{
+	efx_filter_ops_t *efop = enp->en_efop;
+
+	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_FILTER);
+	EFSYS_ASSERT3P(spec, !=, NULL);
+	EFSYS_ASSERT3U(spec->efs_flags, &, EFX_FILTER_FLAG_RX);
+
+#if EFSYS_OPT_RX_SCALE
+	spec->efs_rss_context = enp->en_rss_context;
+#endif
+
+	return (efop->efo_delete(enp, spec));
+}
+
+	__checkReturn	int
+efx_filter_restore(
+	__in		efx_nic_t *enp)
+{
+	int rc;
+
+	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_FILTER);
+
+	if ((rc = enp->en_efop->efo_restore(enp)) != 0)
+		goto fail1;
+
+	return (0);
+
+fail1:
+	EFSYS_PROBE1(fail1, int, rc);
+
+	return (rc);
+}
+
+	__checkReturn	int
+efx_filter_init(
+	__in		efx_nic_t *enp)
+{
+	efx_filter_ops_t *efop;
+	int rc;
+
+	/* Check that efx_filter_spec_t is 64 bytes. */
+	EFX_STATIC_ASSERT(sizeof (efx_filter_spec_t) == 64);
+
+	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
+	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
+	EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_FILTER));
+
+	switch (enp->en_family) {
+#if EFSYS_OPT_FALCON
+	case EFX_FAMILY_FALCON:
+		efop = (efx_filter_ops_t *)&__efx_filter_falcon_ops;
+		break;
+#endif /* EFSYS_OPT_FALCON */
+
+#if EFSYS_OPT_SIENA
+	case EFX_FAMILY_SIENA:
+		efop = (efx_filter_ops_t *)&__efx_filter_siena_ops;
+		break;
+#endif /* EFSYS_OPT_SIENA */
+
+#if EFSYS_OPT_HUNTINGTON
+	case EFX_FAMILY_HUNTINGTON:
+		efop = (efx_filter_ops_t *)&__efx_filter_hunt_ops;
+		break;
+#endif /* EFSYS_OPT_HUNTINGTON */
+
+	default:
+		EFSYS_ASSERT(0);
+		rc = ENOTSUP;
+		goto fail1;
+	}
+
+	if ((rc = efop->efo_init(enp)) != 0)
+		goto fail2;
+
+	enp->en_efop = efop;
+	enp->en_mod_flags |= EFX_MOD_FILTER;
+	return (0);
+
+fail2:
+	EFSYS_PROBE(fail2);
+fail1:
+	EFSYS_PROBE1(fail1, int, rc);
+
+	enp->en_efop = NULL;
+	enp->en_mod_flags &= ~EFX_MOD_FILTER;
+	return (rc);
+}
+
+			void
+efx_filter_fini(
+	__in		efx_nic_t *enp)
+{
+	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
+	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
+	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_FILTER);
+
+	enp->en_efop->efo_fini(enp);
+
+	enp->en_efop = NULL;
+	enp->en_mod_flags &= ~EFX_MOD_FILTER;
+}
+
+	__checkReturn	int
+efx_filter_supported_filters(
+	__in		efx_nic_t *enp,
+	__out		uint32_t *list,
+	__out		size_t *length)
+{
+	int rc;
+
+	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
+	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
+	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_FILTER);
+	EFSYS_ASSERT(enp->en_efop->efo_supported_filters != NULL);
+
+	if ((rc = enp->en_efop->efo_supported_filters(enp, list, length)) != 0)
+		goto fail1;
+
+	return (0);
+
+fail1:
+	EFSYS_PROBE1(fail1, int, rc);
+
+	return (rc);
+}
+
+	__checkReturn	int
+efx_filter_reconfigure(
+	__in				efx_nic_t *enp,
+	__in_ecount(6)			uint8_t const *mac_addr,
+	__in				boolean_t all_unicst,
+	__in				boolean_t mulcst,
+	__in				boolean_t all_mulcst,
+	__in				boolean_t brdcst,
+	__in_ecount(6*count)		uint8_t const *addrs,
+	__in				int count)
+{
+	int rc;
+
+	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
+	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
+	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_FILTER);
+
+	if (enp->en_efop->efo_reconfigure != NULL) {
+		if ((rc = enp->en_efop->efo_reconfigure(enp, mac_addr,
+							all_unicst, mulcst,
+							all_mulcst, brdcst,
+							addrs, count)) != 0)
+			goto fail1;
+	}
+
+	return (0);
+
+fail1:
+	EFSYS_PROBE1(fail1, int, rc);
+
+	return (rc);
+}
+
+		void
+efx_filter_spec_init_rx(
+	__inout		efx_filter_spec_t *spec,
+	__in		efx_filter_priority_t priority,
+	__in		efx_filter_flag_t flags,
+	__in		efx_rxq_t *erp)
+{
+	EFSYS_ASSERT3P(spec, !=, NULL);
+	EFSYS_ASSERT3P(erp, !=, NULL);
+	EFSYS_ASSERT((flags & ~(EFX_FILTER_FLAG_RX_RSS |
+				EFX_FILTER_FLAG_RX_SCATTER)) == 0);
+
+	memset(spec, 0, sizeof (*spec));
+	spec->efs_priority = priority;
+	spec->efs_flags = EFX_FILTER_FLAG_RX | flags;
+	spec->efs_rss_context = EFX_FILTER_SPEC_RSS_CONTEXT_DEFAULT;
+	spec->efs_dmaq_id = (uint16_t)erp->er_index;
+}
+
+		void
+efx_filter_spec_init_tx(
+	__inout		efx_filter_spec_t *spec,
+	__in		efx_txq_t *etp)
+{
+	EFSYS_ASSERT3P(spec, !=, NULL);
+	EFSYS_ASSERT3P(etp, !=, NULL);
+
+	memset(spec, 0, sizeof (*spec));
+	spec->efs_priority = EFX_FILTER_PRI_REQUIRED;
+	spec->efs_flags = EFX_FILTER_FLAG_TX;
+	spec->efs_dmaq_id = (uint16_t)etp->et_index;
+}
+
+
+/*
+ *  Specify IPv4 host, transport protocol and port in a filter specification
+ */
+__checkReturn		int
+efx_filter_spec_set_ipv4_local(
+	__inout		efx_filter_spec_t *spec,
+	__in		uint8_t proto,
+	__in		uint32_t host,
+	__in		uint16_t port)
+{
+	EFSYS_ASSERT3P(spec, !=, NULL);
+
+	spec->efs_match_flags |=
+		EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO |
+		EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT;
+	spec->efs_ether_type = EFX_ETHER_TYPE_IPV4;
+	spec->efs_ip_proto = proto;
+	spec->efs_loc_host.eo_u32[0] = host;
+	spec->efs_loc_port = port;
+	return (0);
+}
+
+/*
+ * Specify IPv4 hosts, transport protocol and ports in a filter specification
+ */
+__checkReturn		int
+efx_filter_spec_set_ipv4_full(
+	__inout		efx_filter_spec_t *spec,
+	__in		uint8_t proto,
+	__in		uint32_t lhost,
+	__in		uint16_t lport,
+	__in		uint32_t rhost,
+	__in		uint16_t rport)
+{
+	EFSYS_ASSERT3P(spec, !=, NULL);
+
+	spec->efs_match_flags |=
+		EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO |
+		EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT |
+		EFX_FILTER_MATCH_REM_HOST | EFX_FILTER_MATCH_REM_PORT;
+	spec->efs_ether_type = EFX_ETHER_TYPE_IPV4;
+	spec->efs_ip_proto = proto;
+	spec->efs_loc_host.eo_u32[0] = lhost;
+	spec->efs_loc_port = lport;
+	spec->efs_rem_host.eo_u32[0] = rhost;
+	spec->efs_rem_port = rport;
+	return (0);
+}
+
+/*
+ * Specify local Ethernet address and/or VID in filter specification
+ */
+__checkReturn		int
+efx_filter_spec_set_eth_local(
+	__inout		efx_filter_spec_t *spec,
+	__in		uint16_t vid,
+	__in		const uint8_t *addr)
+{
+	EFSYS_ASSERT3P(spec, !=, NULL);
+	EFSYS_ASSERT3P(addr, !=, NULL);
+
+	if (vid == EFX_FILTER_SPEC_VID_UNSPEC && addr == NULL)
+		return (EINVAL);
+
+	if (vid != EFX_FILTER_SPEC_VID_UNSPEC) {
+		spec->efs_match_flags |= EFX_FILTER_MATCH_OUTER_VID;
+		spec->efs_outer_vid = vid;
+	}
+	if (addr != NULL) {
+		spec->efs_match_flags |= EFX_FILTER_MATCH_LOC_MAC;
+		memcpy(spec->efs_loc_mac, addr, EFX_MAC_ADDR_LEN);
+	}
+	return (0);
+}
+
+/*
+ * Specify matching otherwise-unmatched unicast in a filter specification
+ */
+__checkReturn		int
+efx_filter_spec_set_uc_def(
+	__inout		efx_filter_spec_t *spec)
+{
+	EFSYS_ASSERT3P(spec, !=, NULL);
+
+	spec->efs_match_flags |= EFX_FILTER_MATCH_LOC_MAC_IG;
+	return (0);
+}
+
+/*
+ * Specify matching otherwise-unmatched multicast in a filter specification
+ */
+__checkReturn		int
+efx_filter_spec_set_mc_def(
+	__inout		efx_filter_spec_t *spec)
+{
+	EFSYS_ASSERT3P(spec, !=, NULL);
+
+	spec->efs_match_flags |= EFX_FILTER_MATCH_LOC_MAC_IG;
+	spec->efs_loc_mac[0] = 1;
+	return (0);
+}
+
+
+
+#if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA
+
+/*
+ * "Fudge factors" - difference between programmed value and actual depth.
  * Due to pipelined implementation we need to program H/W with a value that
  * is larger than the hop limit we want.
  */
-#define FILTER_CTL_SRCH_FUDGE_WILD 3
-#define FILTER_CTL_SRCH_FUDGE_FULL 1
+#define	FILTER_CTL_SRCH_FUDGE_WILD 3
+#define	FILTER_CTL_SRCH_FUDGE_FULL 1
 
-/* Hard maximum hop limit.  Hardware will time-out beyond 200-something.
+/*
+ * Hard maximum hop limit.  Hardware will time-out beyond 200-something.
  * We also need to avoid infinite loops in efx_filter_search() when the
  * table is full.
  */
-#define FILTER_CTL_SRCH_MAX 200
+#define	FILTER_CTL_SRCH_MAX 200
 
-/* The filter hash function is LFSR polynomial x^16 + x^3 + 1 of a 32-bit
- * key derived from the n-tuple. */
+static	__checkReturn	int
+falconsiena_filter_spec_from_gen_spec(
+	__out		falconsiena_filter_spec_t *fs_spec,
+	__in		efx_filter_spec_t *gen_spec)
+{
+	int rc;
+	boolean_t is_full = B_FALSE;
+
+	if (gen_spec->efs_flags & EFX_FILTER_FLAG_TX)
+		EFSYS_ASSERT3U(gen_spec->efs_flags, ==, EFX_FILTER_FLAG_TX);
+	else
+		EFSYS_ASSERT3U(gen_spec->efs_flags, &, EFX_FILTER_FLAG_RX);
+
+	/* Falconsiena only has one RSS context */
+	if ((gen_spec->efs_flags & EFX_FILTER_FLAG_RX_RSS) &&
+	    gen_spec->efs_rss_context != 0) {
+		rc = EINVAL;
+		goto fail1;
+	}
+
+	fs_spec->fsfs_flags = gen_spec->efs_flags;
+	fs_spec->fsfs_dmaq_id = gen_spec->efs_dmaq_id;
+
+	switch (gen_spec->efs_match_flags) {
+	case EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO |
+	    EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT |
+	    EFX_FILTER_MATCH_REM_HOST | EFX_FILTER_MATCH_REM_PORT:
+		is_full = B_TRUE;
+		/* Fall through */
+	case EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO |
+	    EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT: {
+		uint32_t rhost, host1, host2;
+		uint16_t rport, port1, port2;
+
+		if (gen_spec->efs_ether_type != EFX_ETHER_TYPE_IPV4) {
+			rc = ENOTSUP;
+			goto fail2;
+		}
+		if (gen_spec->efs_loc_port == 0 ||
+		    (is_full && gen_spec->efs_rem_port == 0)) {
+			rc = EINVAL;
+			goto fail3;
+		}
+		switch (gen_spec->efs_ip_proto) {
+		case EFX_IPPROTO_TCP:
+			if (gen_spec->efs_flags & EFX_FILTER_FLAG_TX) {
+				fs_spec->fsfs_type = (is_full ?
+				    EFX_FS_FILTER_TX_TCP_FULL :
+				    EFX_FS_FILTER_TX_TCP_WILD);
+			} else {
+				fs_spec->fsfs_type = (is_full ?
+				    EFX_FS_FILTER_RX_TCP_FULL :
+				    EFX_FS_FILTER_RX_TCP_WILD);
+			}
+			break;
+		case EFX_IPPROTO_UDP:
+			if (gen_spec->efs_flags & EFX_FILTER_FLAG_TX) {
+				fs_spec->fsfs_type = (is_full ?
+				    EFX_FS_FILTER_TX_UDP_FULL :
+				    EFX_FS_FILTER_TX_UDP_WILD);
+			} else {
+				fs_spec->fsfs_type = (is_full ?
+				    EFX_FS_FILTER_RX_UDP_FULL :
+				    EFX_FS_FILTER_RX_UDP_WILD);
+			}
+			break;
+		default:
+			rc = ENOTSUP;
+			goto fail4;
+		}
+		/*
+		 * The filter is constructed in terms of source and destination,
+		 * with the odd wrinkle that the ports are swapped in a UDP
+		 * wildcard filter. We need to convert from local and remote
+		 * addresses (zero for a wildcard).
+		 */
+		rhost = is_full ? gen_spec->efs_rem_host.eo_u32[0] : 0;
+		rport = is_full ? gen_spec->efs_rem_port : 0;
+		if (gen_spec->efs_flags & EFX_FILTER_FLAG_TX) {
+			host1 = gen_spec->efs_loc_host.eo_u32[0];
+			host2 = rhost;
+		} else {
+			host1 = rhost;
+			host2 = gen_spec->efs_loc_host.eo_u32[0];
+		}
+		if (gen_spec->efs_flags & EFX_FILTER_FLAG_TX) {
+			if (fs_spec->fsfs_type == EFX_FS_FILTER_TX_UDP_WILD) {
+				port1 = rport;
+				port2 = gen_spec->efs_loc_port;
+			} else {
+				port1 = gen_spec->efs_loc_port;
+				port2 = rport;
+			}
+		} else {
+			if (fs_spec->fsfs_type == EFX_FS_FILTER_RX_UDP_WILD) {
+				port1 = gen_spec->efs_loc_port;
+				port2 = rport;
+			} else {
+				port1 = rport;
+				port2 = gen_spec->efs_loc_port;
+			}
+		}
+		fs_spec->fsfs_dword[0] = (host1 << 16) | port1;
+		fs_spec->fsfs_dword[1] = (port2 << 16) | (host1 >> 16);
+		fs_spec->fsfs_dword[2] = host2;
+		break;
+	}
+
+	case EFX_FILTER_MATCH_LOC_MAC | EFX_FILTER_MATCH_OUTER_VID:
+		is_full = B_TRUE;
+		/* Fall through */
+	case EFX_FILTER_MATCH_LOC_MAC:
+		if (gen_spec->efs_flags & EFX_FILTER_FLAG_TX) {
+			fs_spec->fsfs_type = (is_full ?
+			    EFX_FS_FILTER_TX_MAC_FULL :
+			    EFX_FS_FILTER_TX_MAC_WILD);
+		} else {
+			fs_spec->fsfs_type = (is_full ?
+			    EFX_FS_FILTER_RX_MAC_FULL :
+			    EFX_FS_FILTER_RX_MAC_WILD);
+		}
+		fs_spec->fsfs_dword[0] = is_full ? gen_spec->efs_outer_vid : 0;
+		fs_spec->fsfs_dword[1] =
+		    gen_spec->efs_loc_mac[2] << 24 |
+		    gen_spec->efs_loc_mac[3] << 16 |
+		    gen_spec->efs_loc_mac[4] <<  8 |
+		    gen_spec->efs_loc_mac[5];
+		fs_spec->fsfs_dword[2] =
+		    gen_spec->efs_loc_mac[0] << 8 |
+		    gen_spec->efs_loc_mac[1];
+		break;
+
+	default:
+		EFSYS_ASSERT(B_FALSE);
+		rc = ENOTSUP;
+		goto fail5;
+	}
+
+	return (0);
+
+fail5:
+	EFSYS_PROBE(fail5);
+fail4:
+	EFSYS_PROBE(fail4);
+fail3:
+	EFSYS_PROBE(fail3);
+fail2:
+	EFSYS_PROBE(fail2);
+fail1:
+	EFSYS_PROBE1(fail1, int, rc);
+
+	return (rc);
+}
+
+/*
+ * The filter hash function is LFSR polynomial x^16 + x^3 + 1 of a 32-bit
+ * key derived from the n-tuple.
+ */
 static			uint16_t
-efx_filter_tbl_hash(
-	__in 		uint32_t key)
+falconsiena_filter_tbl_hash(
+	__in		uint32_t key)
 {
 	uint16_t tmp;
 
@@ -69,119 +619,119 @@ efx_filter_tbl_hash(
 	return (tmp);
 }
 
-
-/* To allow for hash collisions, filter search continues at these
- * increments from the first possible entry selected by the hash. */
+/*
+ * To allow for hash collisions, filter search continues at these
+ * increments from the first possible entry selected by the hash.
+ */
 static			uint16_t
-efx_filter_tbl_increment(
+falconsiena_filter_tbl_increment(
 	__in		uint32_t key)
 {
 	return ((uint16_t)(key * 2 - 1));
 }
 
 static	__checkReturn	boolean_t
-efx_filter_test_used(
-	__in		efx_filter_tbl_t *eftp,
+falconsiena_filter_test_used(
+	__in		falconsiena_filter_tbl_t *fsftp,
 	__in		unsigned int index)
 {
-	EFSYS_ASSERT3P(eftp->eft_bitmap, !=, NULL);
-	return ((eftp->eft_bitmap[index / 32] & (1 << (index % 32))) != 0);
+	EFSYS_ASSERT3P(fsftp->fsft_bitmap, !=, NULL);
+	return ((fsftp->fsft_bitmap[index / 32] & (1 << (index % 32))) != 0);
 }
 
 static			void
-efx_filter_set_used(
-	__in		efx_filter_tbl_t *eftp,
+falconsiena_filter_set_used(
+	__in		falconsiena_filter_tbl_t *fsftp,
 	__in		unsigned int index)
 {
-	EFSYS_ASSERT3P(eftp->eft_bitmap, !=, NULL);
-	eftp->eft_bitmap[index / 32] |= (1 << (index % 32));
-	++eftp->eft_used;
+	EFSYS_ASSERT3P(fsftp->fsft_bitmap, !=, NULL);
+	fsftp->fsft_bitmap[index / 32] |= (1 << (index % 32));
+	++fsftp->fsft_used;
 }
 
 static			void
-efx_filter_clear_used(
-	__in		efx_filter_tbl_t *eftp,
+falconsiena_filter_clear_used(
+	__in		falconsiena_filter_tbl_t *fsftp,
 	__in		unsigned int index)
 {
-	EFSYS_ASSERT3P(eftp->eft_bitmap, !=, NULL);
-	eftp->eft_bitmap[index / 32] &= ~(1 << (index % 32));
+	EFSYS_ASSERT3P(fsftp->fsft_bitmap, !=, NULL);
+	fsftp->fsft_bitmap[index / 32] &= ~(1 << (index % 32));
 
-	--eftp->eft_used;
-	EFSYS_ASSERT3U(eftp->eft_used, >=, 0);
+	--fsftp->fsft_used;
+	EFSYS_ASSERT3U(fsftp->fsft_used, >=, 0);
 }
 
 
-static 			efx_filter_tbl_id_t
-efx_filter_tbl_id(
-	__in		efx_filter_type_t type)
+static			falconsiena_filter_tbl_id_t
+falconsiena_filter_tbl_id(
+	__in		falconsiena_filter_type_t type)
 {
-	efx_filter_tbl_id_t tbl_id;
-
-	switch (type)
-	{
-	case EFX_FILTER_RX_TCP_FULL:
-	case EFX_FILTER_RX_TCP_WILD:
-	case EFX_FILTER_RX_UDP_FULL:
-	case EFX_FILTER_RX_UDP_WILD:
-		tbl_id = EFX_FILTER_TBL_RX_IP;
+	falconsiena_filter_tbl_id_t tbl_id;
+
+	switch (type) {
+	case EFX_FS_FILTER_RX_TCP_FULL:
+	case EFX_FS_FILTER_RX_TCP_WILD:
+	case EFX_FS_FILTER_RX_UDP_FULL:
+	case EFX_FS_FILTER_RX_UDP_WILD:
+		tbl_id = EFX_FS_FILTER_TBL_RX_IP;
 		break;
 
 #if EFSYS_OPT_SIENA
-	case EFX_FILTER_RX_MAC_FULL:
-	case EFX_FILTER_RX_MAC_WILD:
-		tbl_id = EFX_FILTER_TBL_RX_MAC;
+	case EFX_FS_FILTER_RX_MAC_FULL:
+	case EFX_FS_FILTER_RX_MAC_WILD:
+		tbl_id = EFX_FS_FILTER_TBL_RX_MAC;
 		break;
 
-	case EFX_FILTER_TX_TCP_FULL:
-	case EFX_FILTER_TX_TCP_WILD:
-	case EFX_FILTER_TX_UDP_FULL:
-	case EFX_FILTER_TX_UDP_WILD:
-		tbl_id = EFX_FILTER_TBL_TX_IP;
+	case EFX_FS_FILTER_TX_TCP_FULL:
+	case EFX_FS_FILTER_TX_TCP_WILD:
+	case EFX_FS_FILTER_TX_UDP_FULL:
+	case EFX_FS_FILTER_TX_UDP_WILD:
+		tbl_id = EFX_FS_FILTER_TBL_TX_IP;
 		break;
 
-	case EFX_FILTER_TX_MAC_FULL:
-	case EFX_FILTER_TX_MAC_WILD:
-		tbl_id = EFX_FILTER_TBL_RX_MAC;
+	case EFX_FS_FILTER_TX_MAC_FULL:
+	case EFX_FS_FILTER_TX_MAC_WILD:
+		tbl_id = EFX_FS_FILTER_TBL_TX_MAC;
 		break;
 #endif	/* EFSYS_OPT_SIENA */
 
 	default:
 		EFSYS_ASSERT(B_FALSE);
+		tbl_id = EFX_FS_FILTER_NTBLS;
 		break;
 	}
 	return (tbl_id);
 }
 
 static			void
-efx_filter_reset_search_depth(
-	__inout		efx_filter_t *efp,
-	__in		efx_filter_tbl_id_t tbl_id)
+falconsiena_filter_reset_search_depth(
+	__inout		falconsiena_filter_t *fsfp,
+	__in		falconsiena_filter_tbl_id_t tbl_id)
 {
-	switch (tbl_id)
-	{
-	case EFX_FILTER_TBL_RX_IP:
-		efp->ef_depth[EFX_FILTER_RX_TCP_FULL] = 0;
-		efp->ef_depth[EFX_FILTER_RX_TCP_WILD] = 0;
-		efp->ef_depth[EFX_FILTER_RX_UDP_FULL] = 0;
-		efp->ef_depth[EFX_FILTER_RX_UDP_WILD] = 0;
+	switch (tbl_id) {
+	case EFX_FS_FILTER_TBL_RX_IP:
+		fsfp->fsf_depth[EFX_FS_FILTER_RX_TCP_FULL] = 0;
+		fsfp->fsf_depth[EFX_FS_FILTER_RX_TCP_WILD] = 0;
+		fsfp->fsf_depth[EFX_FS_FILTER_RX_UDP_FULL] = 0;
+		fsfp->fsf_depth[EFX_FS_FILTER_RX_UDP_WILD] = 0;
 		break;
 
 #if EFSYS_OPT_SIENA
-	case EFX_FILTER_TBL_RX_MAC:
-		efp->ef_depth[EFX_FILTER_RX_MAC_FULL] = 0;
-		efp->ef_depth[EFX_FILTER_RX_MAC_WILD] = 0;
+	case EFX_FS_FILTER_TBL_RX_MAC:
+		fsfp->fsf_depth[EFX_FS_FILTER_RX_MAC_FULL] = 0;
+		fsfp->fsf_depth[EFX_FS_FILTER_RX_MAC_WILD] = 0;
 		break;
 
-	case EFX_FILTER_TBL_TX_IP:
-		efp->ef_depth[EFX_FILTER_TX_TCP_FULL] = 0;
-		efp->ef_depth[EFX_FILTER_TX_TCP_WILD] = 0;
-		efp->ef_depth[EFX_FILTER_TX_UDP_FULL] = 0;
-		efp->ef_depth[EFX_FILTER_TX_UDP_WILD] = 0;
+	case EFX_FS_FILTER_TBL_TX_IP:
+		fsfp->fsf_depth[EFX_FS_FILTER_TX_TCP_FULL] = 0;
+		fsfp->fsf_depth[EFX_FS_FILTER_TX_TCP_WILD] = 0;
+		fsfp->fsf_depth[EFX_FS_FILTER_TX_UDP_FULL] = 0;
+		fsfp->fsf_depth[EFX_FS_FILTER_TX_UDP_WILD] = 0;
 		break;
 
-	case EFX_FILTER_TBL_TX_MAC:
-		efp->ef_depth[EFX_FILTER_TX_MAC_FULL] = 0;
-		efp->ef_depth[EFX_FILTER_TX_MAC_WILD] = 0;
+	case EFX_FS_FILTER_TBL_TX_MAC:
+		fsfp->fsf_depth[EFX_FS_FILTER_TX_MAC_FULL] = 0;
+		fsfp->fsf_depth[EFX_FS_FILTER_TX_MAC_WILD] = 0;
 		break;
 #endif	/* EFSYS_OPT_SIENA */
 
@@ -192,36 +742,36 @@ efx_filter_reset_search_depth(
 }
 
 static			void
-efx_filter_push_rx_limits(
+falconsiena_filter_push_rx_limits(
 	__in		efx_nic_t *enp)
 {
-	efx_filter_t *efp = &enp->en_filter;
+	falconsiena_filter_t *fsfp = enp->en_filter.ef_falconsiena_filter;
 	efx_oword_t oword;
 
 	EFX_BAR_READO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
 
 	EFX_SET_OWORD_FIELD(oword, FRF_AZ_TCP_FULL_SRCH_LIMIT,
-	    efp->ef_depth[EFX_FILTER_RX_TCP_FULL] +
+	    fsfp->fsf_depth[EFX_FS_FILTER_RX_TCP_FULL] +
 	    FILTER_CTL_SRCH_FUDGE_FULL);
 	EFX_SET_OWORD_FIELD(oword, FRF_AZ_TCP_WILD_SRCH_LIMIT,
-	    efp->ef_depth[EFX_FILTER_RX_TCP_WILD] +
+	    fsfp->fsf_depth[EFX_FS_FILTER_RX_TCP_WILD] +
 	    FILTER_CTL_SRCH_FUDGE_WILD);
 	EFX_SET_OWORD_FIELD(oword, FRF_AZ_UDP_FULL_SRCH_LIMIT,
-	    efp->ef_depth[EFX_FILTER_RX_UDP_FULL] +
+	    fsfp->fsf_depth[EFX_FS_FILTER_RX_UDP_FULL] +
 	    FILTER_CTL_SRCH_FUDGE_FULL);
 	EFX_SET_OWORD_FIELD(oword, FRF_AZ_UDP_WILD_SRCH_LIMIT,
-	    efp->ef_depth[EFX_FILTER_RX_UDP_WILD] +
+	    fsfp->fsf_depth[EFX_FS_FILTER_RX_UDP_WILD] +
 	    FILTER_CTL_SRCH_FUDGE_WILD);
 
 #if EFSYS_OPT_SIENA
-	if (efp->ef_tbl[EFX_FILTER_TBL_RX_MAC].eft_size) {
+	if (fsfp->fsf_tbl[EFX_FS_FILTER_TBL_RX_MAC].fsft_size) {
 		EFX_SET_OWORD_FIELD(oword,
 		    FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT,
-		    efp->ef_depth[EFX_FILTER_RX_MAC_FULL] +
+		    fsfp->fsf_depth[EFX_FS_FILTER_RX_MAC_FULL] +
 		    FILTER_CTL_SRCH_FUDGE_FULL);
 		EFX_SET_OWORD_FIELD(oword,
 		    FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT,
-		    efp->ef_depth[EFX_FILTER_RX_MAC_WILD] +
+		    fsfp->fsf_depth[EFX_FS_FILTER_RX_MAC_WILD] +
 		    FILTER_CTL_SRCH_FUDGE_WILD);
 	}
 #endif /* EFSYS_OPT_SIENA */
@@ -230,150 +780,177 @@ efx_filter_push_rx_limits(
 }
 
 static			void
-efx_filter_push_tx_limits(
+falconsiena_filter_push_tx_limits(
 	__in		efx_nic_t *enp)
 {
-	efx_filter_t *efp = &enp->en_filter;
+	falconsiena_filter_t *fsfp = enp->en_filter.ef_falconsiena_filter;
 	efx_oword_t oword;
 
-	if (efp->ef_tbl[EFX_FILTER_TBL_TX_IP].eft_size == 0)
-		return;
-
 	EFX_BAR_READO(enp, FR_AZ_TX_CFG_REG, &oword);
 
-	EFX_SET_OWORD_FIELD(oword, FRF_CZ_TX_TCPIP_FILTER_FULL_SEARCH_RANGE,
-	    efp->ef_depth[EFX_FILTER_TX_TCP_FULL] +
-	    FILTER_CTL_SRCH_FUDGE_FULL);
-	EFX_SET_OWORD_FIELD(oword, FRF_CZ_TX_TCPIP_FILTER_WILD_SEARCH_RANGE,
-	    efp->ef_depth[EFX_FILTER_TX_TCP_WILD] +
-	    FILTER_CTL_SRCH_FUDGE_WILD);
-	EFX_SET_OWORD_FIELD(oword, FRF_CZ_TX_UDPIP_FILTER_FULL_SEARCH_RANGE,
-	    efp->ef_depth[EFX_FILTER_TX_UDP_FULL] +
-	    FILTER_CTL_SRCH_FUDGE_FULL);
-	EFX_SET_OWORD_FIELD(oword, FRF_CZ_TX_UDPIP_FILTER_WILD_SEARCH_RANGE,
-	    efp->ef_depth[EFX_FILTER_TX_UDP_WILD] +
-	    FILTER_CTL_SRCH_FUDGE_WILD);
+	if (fsfp->fsf_tbl[EFX_FS_FILTER_TBL_TX_IP].fsft_size != 0) {
+		EFX_SET_OWORD_FIELD(oword,
+		    FRF_CZ_TX_TCPIP_FILTER_FULL_SEARCH_RANGE,
+		    fsfp->fsf_depth[EFX_FS_FILTER_TX_TCP_FULL] +
+		    FILTER_CTL_SRCH_FUDGE_FULL);
+		EFX_SET_OWORD_FIELD(oword,
+		    FRF_CZ_TX_TCPIP_FILTER_WILD_SEARCH_RANGE,
+		    fsfp->fsf_depth[EFX_FS_FILTER_TX_TCP_WILD] +
+		    FILTER_CTL_SRCH_FUDGE_WILD);
+		EFX_SET_OWORD_FIELD(oword,
+		    FRF_CZ_TX_UDPIP_FILTER_FULL_SEARCH_RANGE,
+		    fsfp->fsf_depth[EFX_FS_FILTER_TX_UDP_FULL] +
+		    FILTER_CTL_SRCH_FUDGE_FULL);
+		EFX_SET_OWORD_FIELD(oword,
+		    FRF_CZ_TX_UDPIP_FILTER_WILD_SEARCH_RANGE,
+		    fsfp->fsf_depth[EFX_FS_FILTER_TX_UDP_WILD] +
+		    FILTER_CTL_SRCH_FUDGE_WILD);
+	}
+
+	if (fsfp->fsf_tbl[EFX_FS_FILTER_TBL_TX_MAC].fsft_size != 0) {
+		EFX_SET_OWORD_FIELD(
+			oword, FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE,
+			fsfp->fsf_depth[EFX_FS_FILTER_TX_MAC_FULL] +
+			FILTER_CTL_SRCH_FUDGE_FULL);
+		EFX_SET_OWORD_FIELD(
+			oword, FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE,
+			fsfp->fsf_depth[EFX_FS_FILTER_TX_MAC_WILD] +
+			FILTER_CTL_SRCH_FUDGE_WILD);
+	}
 
 	EFX_BAR_WRITEO(enp, FR_AZ_TX_CFG_REG, &oword);
 }
 
 /* Build a filter entry and return its n-tuple key. */
 static	__checkReturn	uint32_t
-efx_filter_build(
+falconsiena_filter_build(
 	__out		efx_oword_t *filter,
-	__in		efx_filter_spec_t *spec)
+	__in		falconsiena_filter_spec_t *spec)
 {
 	uint32_t dword3;
 	uint32_t key;
-	uint8_t  type  = spec->efs_type;
-	uint8_t  flags = spec->efs_flags;
+	uint8_t  type  = spec->fsfs_type;
+	uint32_t flags = spec->fsfs_flags;
 
-	switch (efx_filter_tbl_id(type)) {
-	case EFX_FILTER_TBL_RX_IP: {
-		boolean_t is_udp = (type == EFX_FILTER_RX_UDP_FULL ||
-		    type == EFX_FILTER_RX_UDP_WILD);
+	switch (falconsiena_filter_tbl_id(type)) {
+	case EFX_FS_FILTER_TBL_RX_IP: {
+		boolean_t is_udp = (type == EFX_FS_FILTER_RX_UDP_FULL ||
+		    type == EFX_FS_FILTER_RX_UDP_WILD);
 		EFX_POPULATE_OWORD_7(*filter,
-		    FRF_BZ_RSS_EN,     (flags & EFX_FILTER_FLAG_RX_RSS) ? 1 : 0,
-		    FRF_BZ_SCATTER_EN, (flags & EFX_FILTER_FLAG_RX_SCATTER) ? 1 : 0,
+		    FRF_BZ_RSS_EN,
+		    (flags & EFX_FILTER_FLAG_RX_RSS) ? 1 : 0,
+		    FRF_BZ_SCATTER_EN,
+		    (flags & EFX_FILTER_FLAG_RX_SCATTER) ? 1 : 0,
 		    FRF_AZ_TCP_UDP, is_udp,
-		    FRF_AZ_RXQ_ID, spec->efs_dmaq_id,
-		    EFX_DWORD_2, spec->efs_dword[2],
-		    EFX_DWORD_1, spec->efs_dword[1],
-		    EFX_DWORD_0, spec->efs_dword[0]);
+		    FRF_AZ_RXQ_ID, spec->fsfs_dmaq_id,
+		    EFX_DWORD_2, spec->fsfs_dword[2],
+		    EFX_DWORD_1, spec->fsfs_dword[1],
+		    EFX_DWORD_0, spec->fsfs_dword[0]);
 		dword3 = is_udp;
 		break;
 	}
 
 #if EFSYS_OPT_SIENA
-	case EFX_FILTER_TBL_RX_MAC: {
-		boolean_t is_wild = (type == EFX_FILTER_RX_MAC_WILD);
-		EFX_POPULATE_OWORD_8(*filter,
-		    FRF_CZ_RMFT_RSS_EN, (flags & EFX_FILTER_FLAG_RX_RSS) ? 1 : 0,
-		    FRF_CZ_RMFT_SCATTER_EN, (flags & EFX_FILTER_FLAG_RX_SCATTER) ? 1 : 0,
-		    FRF_CZ_RMFT_IP_OVERRIDE, (flags & EFX_FILTER_FLAG_RX_OVERRIDE_IP) ? 1 : 0,
-		    FRF_CZ_RMFT_RXQ_ID, spec->efs_dmaq_id,
+	case EFX_FS_FILTER_TBL_RX_MAC: {
+		boolean_t is_wild = (type == EFX_FS_FILTER_RX_MAC_WILD);
+		EFX_POPULATE_OWORD_7(*filter,
+		    FRF_CZ_RMFT_RSS_EN,
+		    (flags & EFX_FILTER_FLAG_RX_RSS) ? 1 : 0,
+		    FRF_CZ_RMFT_SCATTER_EN,
+		    (flags & EFX_FILTER_FLAG_RX_SCATTER) ? 1 : 0,
+		    FRF_CZ_RMFT_RXQ_ID, spec->fsfs_dmaq_id,
 		    FRF_CZ_RMFT_WILDCARD_MATCH, is_wild,
-		    FRF_CZ_RMFT_DEST_MAC_DW1, spec->efs_dword[2],
-		    FRF_CZ_RMFT_DEST_MAC_DW0, spec->efs_dword[1],
-		    FRF_CZ_RMFT_VLAN_ID, spec->efs_dword[0]);
+		    FRF_CZ_RMFT_DEST_MAC_DW1, spec->fsfs_dword[2],
+		    FRF_CZ_RMFT_DEST_MAC_DW0, spec->fsfs_dword[1],
+		    FRF_CZ_RMFT_VLAN_ID, spec->fsfs_dword[0]);
 		dword3 = is_wild;
 		break;
 	}
 #endif /* EFSYS_OPT_SIENA */
 
-	case EFX_FILTER_TBL_TX_IP: {
-		boolean_t is_udp = (type == EFX_FILTER_TX_UDP_FULL ||
-		    type == EFX_FILTER_TX_UDP_WILD);
+	case EFX_FS_FILTER_TBL_TX_IP: {
+		boolean_t is_udp = (type == EFX_FS_FILTER_TX_UDP_FULL ||
+		    type == EFX_FS_FILTER_TX_UDP_WILD);
 		EFX_POPULATE_OWORD_5(*filter,
 		    FRF_CZ_TIFT_TCP_UDP, is_udp,
-		    FRF_CZ_TIFT_TXQ_ID, spec->efs_dmaq_id,
-		    EFX_DWORD_2, spec->efs_dword[2],
-		    EFX_DWORD_1, spec->efs_dword[1],
-		    EFX_DWORD_0, spec->efs_dword[0]);
-		dword3 = is_udp | spec->efs_dmaq_id << 1;
+		    FRF_CZ_TIFT_TXQ_ID, spec->fsfs_dmaq_id,
+		    EFX_DWORD_2, spec->fsfs_dword[2],
+		    EFX_DWORD_1, spec->fsfs_dword[1],
+		    EFX_DWORD_0, spec->fsfs_dword[0]);
+		dword3 = is_udp | spec->fsfs_dmaq_id << 1;
 		break;
 	}
 
 #if EFSYS_OPT_SIENA
-	case EFX_FILTER_TBL_TX_MAC: {
-		boolean_t is_wild = (type == EFX_FILTER_TX_MAC_WILD);
+	case EFX_FS_FILTER_TBL_TX_MAC: {
+		boolean_t is_wild = (type == EFX_FS_FILTER_TX_MAC_WILD);
 		EFX_POPULATE_OWORD_5(*filter,
-		    FRF_CZ_TMFT_TXQ_ID, spec->efs_dmaq_id,
+		    FRF_CZ_TMFT_TXQ_ID, spec->fsfs_dmaq_id,
 		    FRF_CZ_TMFT_WILDCARD_MATCH, is_wild,
-		    FRF_CZ_TMFT_SRC_MAC_DW1, spec->efs_dword[2],
-		    FRF_CZ_TMFT_SRC_MAC_DW0, spec->efs_dword[1],
-		    FRF_CZ_TMFT_VLAN_ID, spec->efs_dword[0]);
-		dword3 = is_wild | spec->efs_dmaq_id << 1;
+		    FRF_CZ_TMFT_SRC_MAC_DW1, spec->fsfs_dword[2],
+		    FRF_CZ_TMFT_SRC_MAC_DW0, spec->fsfs_dword[1],
+		    FRF_CZ_TMFT_VLAN_ID, spec->fsfs_dword[0]);
+		dword3 = is_wild | spec->fsfs_dmaq_id << 1;
 		break;
 	}
 #endif /* EFSYS_OPT_SIENA */
 
 	default:
 		EFSYS_ASSERT(B_FALSE);
+		return (0);
 	}
 
-	key = spec->efs_dword[0] ^ spec->efs_dword[1] ^ spec->efs_dword[2] ^ dword3;
+	key =
+	    spec->fsfs_dword[0] ^
+	    spec->fsfs_dword[1] ^
+	    spec->fsfs_dword[2] ^
+	    dword3;
+
 	return (key);
 }
 
 static	__checkReturn		int
-efx_filter_push_entry(
+falconsiena_filter_push_entry(
 	__inout			efx_nic_t *enp,
-	__in			efx_filter_type_t type,
+	__in			falconsiena_filter_type_t type,
 	__in			int index,
 	__in			efx_oword_t *eop)
 {
 	int rc;
 
-	switch (type)
-	{
-	case EFX_FILTER_RX_TCP_FULL:
-	case EFX_FILTER_RX_TCP_WILD:
-	case EFX_FILTER_RX_UDP_FULL:
-	case EFX_FILTER_RX_UDP_WILD:
-		EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_FILTER_TBL0, index, eop);
+	switch (type) {
+	case EFX_FS_FILTER_RX_TCP_FULL:
+	case EFX_FS_FILTER_RX_TCP_WILD:
+	case EFX_FS_FILTER_RX_UDP_FULL:
+	case EFX_FS_FILTER_RX_UDP_WILD:
+		EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_FILTER_TBL0, index,
+		    eop, B_TRUE);
 		break;
 
 #if EFSYS_OPT_SIENA
-	case EFX_FILTER_RX_MAC_FULL:
-	case EFX_FILTER_RX_MAC_WILD:
-		EFX_BAR_TBL_WRITEO(enp, FR_CZ_RX_MAC_FILTER_TBL0, index, eop);
+	case EFX_FS_FILTER_RX_MAC_FULL:
+	case EFX_FS_FILTER_RX_MAC_WILD:
+		EFX_BAR_TBL_WRITEO(enp, FR_CZ_RX_MAC_FILTER_TBL0, index,
+		    eop, B_TRUE);
 		break;
 
-	case EFX_FILTER_TX_TCP_FULL:
-	case EFX_FILTER_TX_TCP_WILD:
-	case EFX_FILTER_TX_UDP_FULL:
-	case EFX_FILTER_TX_UDP_WILD:
-		EFX_BAR_TBL_WRITEO(enp, FR_CZ_TX_FILTER_TBL0, index, eop);
+	case EFX_FS_FILTER_TX_TCP_FULL:
+	case EFX_FS_FILTER_TX_TCP_WILD:
+	case EFX_FS_FILTER_TX_UDP_FULL:
+	case EFX_FS_FILTER_TX_UDP_WILD:
+		EFX_BAR_TBL_WRITEO(enp, FR_CZ_TX_FILTER_TBL0, index,
+		    eop, B_TRUE);
 		break;
 
-	case EFX_FILTER_TX_MAC_FULL:
-	case EFX_FILTER_TX_MAC_WILD:
-		EFX_BAR_TBL_WRITEO(enp, FR_CZ_TX_MAC_FILTER_TBL0, index, eop);
+	case EFX_FS_FILTER_TX_MAC_FULL:
+	case EFX_FS_FILTER_TX_MAC_WILD:
+		EFX_BAR_TBL_WRITEO(enp, FR_CZ_TX_MAC_FILTER_TBL0, index,
+		    eop, B_TRUE);
 		break;
 #endif	/* EFSYS_OPT_SIENA */
 
 	default:
+		EFSYS_ASSERT(B_FALSE);
 		rc = ENOTSUP;
 		goto fail1;
 	}
@@ -385,30 +962,34 @@ fail1:
 
 
 static	__checkReturn	boolean_t
-efx_filter_equal(
-	__in		const efx_filter_spec_t *left,
-	__in		const efx_filter_spec_t *right)
+falconsiena_filter_equal(
+	__in		const falconsiena_filter_spec_t *left,
+	__in		const falconsiena_filter_spec_t *right)
 {
-	efx_filter_tbl_id_t tbl_id = efx_filter_tbl_id(left->efs_type);
+	falconsiena_filter_tbl_id_t tbl_id;
 
-	if (left->efs_type != right->efs_type)
+	tbl_id = falconsiena_filter_tbl_id(left->fsfs_type);
+
+
+	if (left->fsfs_type != right->fsfs_type)
 		return (B_FALSE);
 
-	if (memcmp(left->efs_dword, right->efs_dword, sizeof(left->efs_dword)))
+	if (memcmp(left->fsfs_dword, right->fsfs_dword,
+		sizeof (left->fsfs_dword)))
 		return (B_FALSE);
 
-	if ((tbl_id == EFX_FILTER_TBL_TX_IP ||
-	     tbl_id == EFX_FILTER_TBL_TX_MAC) &&
-	    left->efs_dmaq_id != right->efs_dmaq_id)
+	if ((tbl_id == EFX_FS_FILTER_TBL_TX_IP ||
+		tbl_id == EFX_FS_FILTER_TBL_TX_MAC) &&
+	    left->fsfs_dmaq_id != right->fsfs_dmaq_id)
 		return (B_FALSE);
 
 	return (B_TRUE);
 }
 
 static	__checkReturn	int
-efx_filter_search(
-	__in		efx_filter_tbl_t *eftp,
-	__in		efx_filter_spec_t *spec,
+falconsiena_filter_search(
+	__in		falconsiena_filter_tbl_t *fsftp,
+	__in		falconsiena_filter_spec_t *spec,
 	__in		uint32_t key,
 	__in		boolean_t for_insert,
 	__out		int *filter_index,
@@ -416,18 +997,20 @@ efx_filter_search(
 {
 	unsigned hash, incr, filter_idx, depth;
 
-	hash = efx_filter_tbl_hash(key);
-	incr = efx_filter_tbl_increment(key);
+	hash = falconsiena_filter_tbl_hash(key);
+	incr = falconsiena_filter_tbl_increment(key);
 
-	filter_idx = hash & (eftp->eft_size - 1);
+	filter_idx = hash & (fsftp->fsft_size - 1);
 	depth = 1;
 
 	for (;;) {
-		/* Return success if entry is used and matches this spec
+		/*
+		 * Return success if entry is used and matches this spec
 		 * or entry is unused and we are trying to insert.
 		 */
-		if (efx_filter_test_used(eftp, filter_idx) ?
-		    efx_filter_equal(spec, &eftp->eft_spec[filter_idx]) :
+		if (falconsiena_filter_test_used(fsftp, filter_idx) ?
+		    falconsiena_filter_equal(spec,
+		    &fsftp->fsft_spec[filter_idx]) :
 		    for_insert) {
 			*filter_index = filter_idx;
 			*depth_required = depth;
@@ -436,594 +1019,421 @@ efx_filter_search(
 
 		/* Return failure if we reached the maximum search depth */
 		if (depth == FILTER_CTL_SRCH_MAX)
-			return for_insert ? EBUSY : ENOENT;
+			return (for_insert ? EBUSY : ENOENT);
 
-		filter_idx = (filter_idx + incr) & (eftp->eft_size - 1);
+		filter_idx = (filter_idx + incr) & (fsftp->fsft_size - 1);
 		++depth;
 	}
 }
 
-	__checkReturn	int
-efx_filter_insert_filter(
-	__in		efx_nic_t *enp,
-	__in		efx_filter_spec_t *spec,
-	__in		boolean_t replace)
-{
-	efx_filter_t *efp = &enp->en_filter;
-	efx_filter_tbl_id_t tbl_id = efx_filter_tbl_id(spec->efs_type);
-	efx_filter_tbl_t *eftp = &efp->ef_tbl[tbl_id];
-	efx_filter_spec_t *saved_spec;
-	efx_oword_t filter;
-	int filter_idx;
-	unsigned int depth;
-	int state;
-	uint32_t key;
-	int rc;
-
-	if (eftp->eft_size == 0)
-		return (EINVAL);
-
-	key = efx_filter_build(&filter, spec);
-
-	EFSYS_LOCK(enp->en_eslp, state);
-
-	rc = efx_filter_search(eftp, spec, key, B_TRUE, &filter_idx, &depth);
-	if (rc != 0)
-		goto done;
-
-	EFSYS_ASSERT3U(filter_idx, <, eftp->eft_size);
-	saved_spec = &eftp->eft_spec[filter_idx];
-
-	if (efx_filter_test_used(eftp, filter_idx)) {
-		if (replace == B_FALSE) {
-			rc = EEXIST;
-			goto done;
-		}
-	}
-	efx_filter_set_used(eftp, filter_idx);
-	*saved_spec = *spec;
-
-	if (efp->ef_depth[spec->efs_type] < depth) {
-		efp->ef_depth[spec->efs_type] = depth;
-		if (tbl_id == EFX_FILTER_TBL_TX_IP ||
-		    tbl_id == EFX_FILTER_TBL_TX_MAC)
-			efx_filter_push_tx_limits(enp);
-		else
-			efx_filter_push_rx_limits(enp);
-	}
-
-	efx_filter_push_entry(enp, spec->efs_type, filter_idx, &filter);
-
-done:
-	EFSYS_UNLOCK(enp->en_eslp, state);
-	return (rc);
-}
-
 static			void
-efx_filter_clear_entry(
+falconsiena_filter_clear_entry(
 	__in		efx_nic_t *enp,
-	__in		efx_filter_tbl_t *eftp,
+	__in		falconsiena_filter_tbl_t *fsftp,
 	__in		int index)
 {
 	efx_oword_t filter;
 
-	if (efx_filter_test_used(eftp, index)) {
-		efx_filter_clear_used(eftp, index);
+	if (falconsiena_filter_test_used(fsftp, index)) {
+		falconsiena_filter_clear_used(fsftp, index);
 
 		EFX_ZERO_OWORD(filter);
-		efx_filter_push_entry(enp, eftp->eft_spec[index].efs_type,
+		falconsiena_filter_push_entry(enp,
+		    fsftp->fsft_spec[index].fsfs_type,
 		    index, &filter);
 
-		memset(&eftp->eft_spec[index], 0, sizeof(eftp->eft_spec[0]));
+		memset(&fsftp->fsft_spec[index],
+		    0, sizeof (fsftp->fsft_spec[0]));
 	}
 }
 
-	__checkReturn	int
-efx_filter_remove_filter(
-	__in		efx_nic_t *enp,
-	__in		efx_filter_spec_t *spec)
-{
-	efx_filter_t *efp = &enp->en_filter;
-	efx_filter_tbl_id_t tbl_id = efx_filter_tbl_id(spec->efs_type);
-	efx_filter_tbl_t *eftp = &efp->ef_tbl[tbl_id];
-	efx_filter_spec_t *saved_spec;
-	efx_oword_t filter;
-	int filter_idx;
-	unsigned int depth;
-	int state;
-	uint32_t key;
-	int rc;
-
-	key = efx_filter_build(&filter, spec);
-
-	EFSYS_LOCK(enp->en_eslp, state);
-
-	rc = efx_filter_search(eftp, spec, key, B_FALSE, &filter_idx, &depth);
-	if (rc != 0)
-		goto out;
-
-	saved_spec = &eftp->eft_spec[filter_idx];
-
-	efx_filter_clear_entry(enp, eftp, filter_idx);
-	if (eftp->eft_used == 0)
-		efx_filter_reset_search_depth(efp, tbl_id);
-
-	rc = 0;
-
-out:
-	EFSYS_UNLOCK(enp->en_eslp, state);
-	return (rc);
-}
-
-			void
-efx_filter_remove_index(
-	__inout		efx_nic_t *enp,
-	__in		efx_filter_type_t type,
-	__in		int index)
-{
-	efx_filter_t *efp = &enp->en_filter;
-	efx_filter_tbl_id_t tbl_id = efx_filter_tbl_id(type);
-	efx_filter_tbl_t *eftp = &efp->ef_tbl[tbl_id];
-	int state;
-
-	if (index < 0)
-		return;
-
-	EFSYS_LOCK(enp->en_eslp, state);
-
-	efx_filter_clear_entry(enp, eftp, index);
-	if (eftp->eft_used == 0)
-		efx_filter_reset_search_depth(efp, tbl_id);
-
-	EFSYS_UNLOCK(enp->en_eslp, state);
-}
-
 			void
-efx_filter_tbl_clear(
-	__inout		efx_nic_t *enp,
-	__in		efx_filter_tbl_id_t tbl_id)
+falconsiena_filter_tbl_clear(
+	__in		efx_nic_t *enp,
+	__in		falconsiena_filter_tbl_id_t tbl_id)
 {
-	efx_filter_t *efp = &enp->en_filter;
-	efx_filter_tbl_t *eftp = &efp->ef_tbl[tbl_id];
+	falconsiena_filter_t *fsfp = enp->en_filter.ef_falconsiena_filter;
+	falconsiena_filter_tbl_t *fsftp = &fsfp->fsf_tbl[tbl_id];
 	int index;
 	int state;
 
 	EFSYS_LOCK(enp->en_eslp, state);
 
-	for (index = 0; index < eftp->eft_size; ++index) {
-		efx_filter_clear_entry(enp, eftp, index);
+	for (index = 0; index < fsftp->fsft_size; ++index) {
+		falconsiena_filter_clear_entry(enp, fsftp, index);
 	}
 
-	if (eftp->eft_used == 0)
-		efx_filter_reset_search_depth(efp, tbl_id);
+	if (fsftp->fsft_used == 0)
+		falconsiena_filter_reset_search_depth(fsfp, tbl_id);
 
 	EFSYS_UNLOCK(enp->en_eslp, state);
 }
 
-/* Restore filter state after a reset */
-			void
-efx_filter_restore(
+static	__checkReturn	int
+falconsiena_filter_init(
 	__in		efx_nic_t *enp)
 {
-	efx_filter_t *efp = &enp->en_filter;
-	efx_filter_tbl_id_t tbl_id;
-	efx_filter_tbl_t *eftp;
-	efx_filter_spec_t *spec;
-	efx_oword_t filter;
-	int filter_idx;
-	int state;
-
-	EFSYS_LOCK(enp->en_eslp, state);
+	falconsiena_filter_t *fsfp;
+	falconsiena_filter_tbl_t *fsftp;
+	int tbl_id;
+	int rc;
 
-	for (tbl_id = 0; tbl_id < EFX_FILTER_NTBLS; tbl_id++) {
-		eftp = &efp->ef_tbl[tbl_id];
-		for (filter_idx = 0; filter_idx < eftp->eft_size; filter_idx++) {
-			if (!efx_filter_test_used(eftp, filter_idx))
-				continue;
+	EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (falconsiena_filter_t), fsfp);
 
-			spec = &eftp->eft_spec[filter_idx];
-			efx_filter_build(&filter, spec);
-			efx_filter_push_entry(enp, spec->efs_type,
-			    filter_idx, &filter);
-		}
+	if (!fsfp) {
+		rc = ENOMEM;
+		goto fail1;
 	}
 
-	efx_filter_push_rx_limits(enp);
-	efx_filter_push_tx_limits(enp);
-
-	EFSYS_UNLOCK(enp->en_eslp, state);
-}
-
-			void
-efx_filter_redirect_index(
-	__inout		efx_nic_t *enp,
-	__in		efx_filter_type_t type,
-	__in		int filter_index,
-	__in		int rxq_index)
-{
-	efx_filter_t *efp = &enp->en_filter;
-	efx_filter_tbl_t *eftp =
-		&efp->ef_tbl[efx_filter_tbl_id(type)];
-	efx_filter_spec_t *spec;
-	efx_oword_t filter;
-	int state;
-
-	EFSYS_LOCK(enp->en_eslp, state);
+	enp->en_filter.ef_falconsiena_filter = fsfp;
 
-	spec = &eftp->eft_spec[filter_index];
-	spec->efs_dmaq_id = (uint16_t)rxq_index;
-
-	efx_filter_build(&filter, spec);
-	efx_filter_push_entry(enp, spec->efs_type, filter_index, &filter);
-
-	EFSYS_UNLOCK(enp->en_eslp, state);
-}
-
-	__checkReturn	int
-efx_filter_init(
-	__in		efx_nic_t *enp)
-{
-	efx_filter_t *efp = &enp->en_filter;
-	efx_filter_tbl_t *eftp;
-	int tbl_id;
-	int rc;
-
-	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
-	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
-	EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_FILTER));
-
-	switch (enp->en_family)
-	{
+	switch (enp->en_family) {
 #if EFSYS_OPT_FALCON
 	case EFX_FAMILY_FALCON:
-		eftp = &efp->ef_tbl[EFX_FILTER_TBL_RX_IP];
-		eftp->eft_size = FR_AZ_RX_FILTER_TBL0_ROWS;
+		fsftp = &fsfp->fsf_tbl[EFX_FS_FILTER_TBL_RX_IP];
+		fsftp->fsft_size = FR_AZ_RX_FILTER_TBL0_ROWS;
 		break;
 #endif	/* EFSYS_OPT_FALCON */
 
 #if EFSYS_OPT_SIENA
 	case EFX_FAMILY_SIENA:
-		eftp = &efp->ef_tbl[EFX_FILTER_TBL_RX_IP];
-		eftp->eft_size = FR_AZ_RX_FILTER_TBL0_ROWS;
+		fsftp = &fsfp->fsf_tbl[EFX_FS_FILTER_TBL_RX_IP];
+		fsftp->fsft_size = FR_AZ_RX_FILTER_TBL0_ROWS;
 
-		eftp = &efp->ef_tbl[EFX_FILTER_TBL_RX_MAC];
-		eftp->eft_size = FR_CZ_RX_MAC_FILTER_TBL0_ROWS;
+		fsftp = &fsfp->fsf_tbl[EFX_FS_FILTER_TBL_RX_MAC];
+		fsftp->fsft_size = FR_CZ_RX_MAC_FILTER_TBL0_ROWS;
 
-		eftp = &efp->ef_tbl[EFX_FILTER_TBL_TX_IP];
-		eftp->eft_size = FR_CZ_TX_FILTER_TBL0_ROWS;
+		fsftp = &fsfp->fsf_tbl[EFX_FS_FILTER_TBL_TX_IP];
+		fsftp->fsft_size = FR_CZ_TX_FILTER_TBL0_ROWS;
 
-		eftp = &efp->ef_tbl[EFX_FILTER_TBL_TX_MAC];
-		eftp->eft_size = FR_CZ_TX_MAC_FILTER_TBL0_ROWS;
+		fsftp = &fsfp->fsf_tbl[EFX_FS_FILTER_TBL_TX_MAC];
+		fsftp->fsft_size = FR_CZ_TX_MAC_FILTER_TBL0_ROWS;
 		break;
 #endif	/* EFSYS_OPT_SIENA */
 
 	default:
 		rc = ENOTSUP;
-		goto fail1;
+		goto fail2;
 	}
 
-	for (tbl_id = 0; tbl_id < EFX_FILTER_NTBLS; tbl_id++) {
+	for (tbl_id = 0; tbl_id < EFX_FS_FILTER_NTBLS; tbl_id++) {
 		unsigned int bitmap_size;
 
-		eftp = &efp->ef_tbl[tbl_id];
-		if (eftp->eft_size == 0)
+		fsftp = &fsfp->fsf_tbl[tbl_id];
+		if (fsftp->fsft_size == 0)
 			continue;
 
-		EFX_STATIC_ASSERT(sizeof(eftp->eft_bitmap[0]) == sizeof(uint32_t));
-		bitmap_size = (eftp->eft_size + (sizeof(uint32_t) * 8) - 1) / 8;
+		EFX_STATIC_ASSERT(sizeof (fsftp->fsft_bitmap[0]) ==
+		    sizeof (uint32_t));
+		bitmap_size =
+		    (fsftp->fsft_size + (sizeof (uint32_t) * 8) - 1) / 8;
 
-		EFSYS_KMEM_ALLOC(enp->en_esip, bitmap_size, eftp->eft_bitmap);
-		if (!eftp->eft_bitmap) {
+		EFSYS_KMEM_ALLOC(enp->en_esip, bitmap_size, fsftp->fsft_bitmap);
+		if (!fsftp->fsft_bitmap) {
 			rc = ENOMEM;
-			goto fail2;
+			goto fail3;
 		}
 
-		EFSYS_KMEM_ALLOC(enp->en_esip, eftp->eft_size * sizeof(*eftp->eft_spec),
-		    eftp->eft_spec);
-		if (!eftp->eft_spec) {
+		EFSYS_KMEM_ALLOC(enp->en_esip,
+		    fsftp->fsft_size * sizeof (*fsftp->fsft_spec),
+		    fsftp->fsft_spec);
+		if (!fsftp->fsft_spec) {
 			rc = ENOMEM;
-			goto fail3;
+			goto fail4;
 		}
-		memset(eftp->eft_spec, 0, eftp->eft_size * sizeof(*eftp->eft_spec));
+		memset(fsftp->fsft_spec, 0,
+		    fsftp->fsft_size * sizeof (*fsftp->fsft_spec));
 	}
-	enp->en_mod_flags |= EFX_MOD_FILTER;
 
 	return (0);
 
+fail4:
+	EFSYS_PROBE(fail4);
+
 fail3:
 	EFSYS_PROBE(fail3);
 
 fail2:
 	EFSYS_PROBE(fail2);
-	efx_filter_fini(enp);
+	falconsiena_filter_fini(enp);
 
 fail1:
 	EFSYS_PROBE1(fail1, int, rc);
 	return (rc);
 }
 
-			void
-efx_filter_fini(
+static			void
+falconsiena_filter_fini(
 	__in		efx_nic_t *enp)
 {
-	efx_filter_t *efp = &enp->en_filter;
-	efx_filter_tbl_id_t tbl_id;
+	falconsiena_filter_t *fsfp = enp->en_filter.ef_falconsiena_filter;
+	falconsiena_filter_tbl_id_t tbl_id;
 
 	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 
-	for (tbl_id = 0; tbl_id < EFX_FILTER_NTBLS; tbl_id++) {
-		efx_filter_tbl_t *eftp = &efp->ef_tbl[tbl_id];
+	if (fsfp == NULL)
+		return;
+
+	for (tbl_id = 0; tbl_id < EFX_FS_FILTER_NTBLS; tbl_id++) {
+		falconsiena_filter_tbl_t *fsftp = &fsfp->fsf_tbl[tbl_id];
 		unsigned int bitmap_size;
 
-		EFX_STATIC_ASSERT(sizeof(eftp->eft_bitmap[0]) == sizeof(uint32_t));
-		bitmap_size = (eftp->eft_size + (sizeof(uint32_t) * 8) - 1) / 8;
+		EFX_STATIC_ASSERT(sizeof (fsftp->fsft_bitmap[0]) ==
+		    sizeof (uint32_t));
+		bitmap_size =
+		    (fsftp->fsft_size + (sizeof (uint32_t) * 8) - 1) / 8;
 
-		if (eftp->eft_bitmap != NULL) {
+		if (fsftp->fsft_bitmap != NULL) {
 			EFSYS_KMEM_FREE(enp->en_esip, bitmap_size,
-			    eftp->eft_bitmap);
-			eftp->eft_bitmap = NULL;
+			    fsftp->fsft_bitmap);
+			fsftp->fsft_bitmap = NULL;
 		}
 
-		if (eftp->eft_spec != NULL) {
-			EFSYS_KMEM_FREE(enp->en_esip, eftp->eft_size *
-			    sizeof(*eftp->eft_spec), eftp->eft_spec);
-			eftp->eft_spec = NULL;
+		if (fsftp->fsft_spec != NULL) {
+			EFSYS_KMEM_FREE(enp->en_esip, fsftp->fsft_size *
+			    sizeof (*fsftp->fsft_spec), fsftp->fsft_spec);
+			fsftp->fsft_spec = NULL;
 		}
 	}
 
-	enp->en_mod_flags &= ~EFX_MOD_FILTER;
+	EFSYS_KMEM_FREE(enp->en_esip, sizeof (falconsiena_filter_t),
+	    enp->en_filter.ef_falconsiena_filter);
 }
 
-extern			void
-efx_filter_spec_rx_ipv4_tcp_full(
-	__inout		efx_filter_spec_t *spec,
-	__in		unsigned int flags,
-	__in		uint32_t src_ip,
-	__in		uint16_t src_tcp,
-	__in		uint32_t dest_ip,
-	__in		uint16_t dest_tcp)
+/* Restore filter state after a reset */
+static	__checkReturn	int
+falconsiena_filter_restore(
+	__in		efx_nic_t *enp)
 {
-	EFSYS_ASSERT3P(spec, !=, NULL);
-	EFSYS_ASSERT((flags & ~(EFX_FILTER_FLAG_RX_RSS |
-		    EFX_FILTER_FLAG_RX_SCATTER)) == 0);
+	falconsiena_filter_t *fsfp = enp->en_filter.ef_falconsiena_filter;
+	falconsiena_filter_tbl_id_t tbl_id;
+	falconsiena_filter_tbl_t *fsftp;
+	falconsiena_filter_spec_t *spec;
+	efx_oword_t filter;
+	int filter_idx;
+	int state;
+	int rc;
 
-	spec->efs_type = EFX_FILTER_RX_TCP_FULL;
-	spec->efs_flags = (uint8_t)flags;
-	spec->efs_dword[0] = src_tcp | src_ip << 16;
-	spec->efs_dword[1] = dest_tcp << 16 | src_ip >> 16;
-	spec->efs_dword[2] = dest_ip;
-}
+	EFSYS_LOCK(enp->en_eslp, state);
 
-extern			void
-efx_filter_spec_rx_ipv4_tcp_wild(
-	__inout		efx_filter_spec_t *spec,
-	__in		unsigned int flags,
-	__in		uint32_t dest_ip,
-	__in		uint16_t dest_tcp)
-{
-	EFSYS_ASSERT3P(spec, !=, NULL);
-	EFSYS_ASSERT((flags & ~(EFX_FILTER_FLAG_RX_RSS |
-		    EFX_FILTER_FLAG_RX_SCATTER)) == 0);
+	for (tbl_id = 0; tbl_id < EFX_FS_FILTER_NTBLS; tbl_id++) {
+		fsftp = &fsfp->fsf_tbl[tbl_id];
+		for (filter_idx = 0;
+			filter_idx < fsftp->fsft_size;
+			filter_idx++) {
+			if (!falconsiena_filter_test_used(fsftp, filter_idx))
+				continue;
 
-	spec->efs_type = EFX_FILTER_RX_TCP_WILD;
-	spec->efs_flags = (uint8_t)flags;
-	spec->efs_dword[0] = 0;
-	spec->efs_dword[1] = dest_tcp << 16;
-	spec->efs_dword[2] = dest_ip;
-}
+			spec = &fsftp->fsft_spec[filter_idx];
+			if ((rc = falconsiena_filter_build(&filter, spec)) != 0)
+				goto fail1;
+			if ((rc = falconsiena_filter_push_entry(enp,
+				    spec->fsfs_type, filter_idx, &filter)) != 0)
+				goto fail2;
+		}
+	}
 
-extern			void
-efx_filter_spec_rx_ipv4_udp_full(
-	__inout		efx_filter_spec_t *spec,
-	__in		unsigned int flags,
-	__in		uint32_t src_ip,
-	__in		uint16_t src_udp,
-	__in		uint32_t dest_ip,
-	__in		uint16_t dest_udp)
-{
-	EFSYS_ASSERT3P(spec, !=, NULL);
-	EFSYS_ASSERT((flags & ~(EFX_FILTER_FLAG_RX_RSS |
-		    EFX_FILTER_FLAG_RX_SCATTER)) == 0);
+	falconsiena_filter_push_rx_limits(enp);
+	falconsiena_filter_push_tx_limits(enp);
 
-	spec->efs_type = EFX_FILTER_RX_UDP_FULL;
-	spec->efs_flags = (uint8_t)flags;
-	spec->efs_dword[0] = src_udp | src_ip << 16;
-	spec->efs_dword[1] = dest_udp << 16 | src_ip >> 16;
-	spec->efs_dword[2] = dest_ip;
-}
+	EFSYS_UNLOCK(enp->en_eslp, state);
 
-extern			void
-efx_filter_spec_rx_ipv4_udp_wild(
-	__inout		efx_filter_spec_t *spec,
-	__in		unsigned int flags,
-	__in		uint32_t dest_ip,
-	__in		uint16_t dest_udp)
-{
-	EFSYS_ASSERT3P(spec, !=, NULL);
-	EFSYS_ASSERT((flags & ~(EFX_FILTER_FLAG_RX_RSS |
-		    EFX_FILTER_FLAG_RX_SCATTER)) == 0);
+	return (0);
 
-	spec->efs_type = EFX_FILTER_RX_UDP_WILD;
-	spec->efs_flags = (uint8_t)flags;
-	spec->efs_dword[0] = dest_udp;
-	spec->efs_dword[1] = 0;
-	spec->efs_dword[2] = dest_ip;
-}
+fail2:
+	EFSYS_PROBE(fail2);
 
-#if EFSYS_OPT_SIENA
-extern			void
-efx_filter_spec_rx_mac_full(
-	__inout		efx_filter_spec_t *spec,
-	__in		unsigned int flags,
-	__in		uint16_t vlan_id,
-	__in		uint8_t *dest_mac)
-{
-	EFSYS_ASSERT3P(spec, !=, NULL);
-	EFSYS_ASSERT3P(dest_mac, !=, NULL);
-	EFSYS_ASSERT((flags & ~(EFX_FILTER_FLAG_RX_RSS |
-		    EFX_FILTER_FLAG_RX_SCATTER |
-		    EFX_FILTER_FLAG_RX_OVERRIDE_IP)) == 0);
-
-	spec->efs_type = EFX_FILTER_RX_MAC_FULL;
-	spec->efs_flags = (uint8_t)flags;
-	spec->efs_dword[0] = vlan_id;
-	spec->efs_dword[1] =
-	    dest_mac[2] << 24 |
-	    dest_mac[3] << 16 |
-	    dest_mac[4] <<  8 |
-	    dest_mac[5];
- 	spec->efs_dword[2] =
-	    dest_mac[0] <<  8 |
-	    dest_mac[1];
-}
-#endif	/* EFSYS_OPT_SIENA */
+fail1:
+	EFSYS_PROBE1(fail1, int, rc);
 
-#if EFSYS_OPT_SIENA
-extern			void
-efx_filter_spec_rx_mac_wild(
-	__inout		efx_filter_spec_t *spec,
-	__in		unsigned int flags,
-	__in		uint8_t *dest_mac)
-{
-	EFSYS_ASSERT3P(spec, !=, NULL);
-	EFSYS_ASSERT3P(dest_mac, !=, NULL);
-	EFSYS_ASSERT((flags & ~(EFX_FILTER_FLAG_RX_RSS |
-		    EFX_FILTER_FLAG_RX_SCATTER |
-		    EFX_FILTER_FLAG_RX_OVERRIDE_IP)) == 0);
-
-	spec->efs_type = EFX_FILTER_RX_MAC_WILD;
-	spec->efs_flags = (uint8_t)flags;
-	spec->efs_dword[0] = 0;
-	spec->efs_dword[1] =
-	    dest_mac[2] << 24 |
-	    dest_mac[3] << 16 |
-	    dest_mac[4] <<  8 |
-	    dest_mac[5];
- 	spec->efs_dword[2] =
-	    dest_mac[0] <<  8 |
-	    dest_mac[1];
+	EFSYS_UNLOCK(enp->en_eslp, state);
+
+	return (rc);
 }
-#endif	/* EFSYS_OPT_SIENA */
 
-#if EFSYS_OPT_SIENA
-extern			void
-efx_filter_spec_tx_ipv4_tcp_full(
+static	 __checkReturn	int
+falconsiena_filter_add(
+	__in		efx_nic_t *enp,
 	__inout		efx_filter_spec_t *spec,
-	__in		uint32_t src_ip,
-	__in		uint16_t src_tcp,
-	__in		uint32_t dest_ip,
-	__in		uint16_t dest_tcp)
+	__in		boolean_t may_replace)
 {
-	EFSYS_ASSERT3P(spec, !=, NULL);
+	int rc;
+	falconsiena_filter_spec_t fs_spec;
+	falconsiena_filter_t *fsfp = enp->en_filter.ef_falconsiena_filter;
+	falconsiena_filter_tbl_id_t tbl_id;
+	falconsiena_filter_tbl_t *fsftp;
+	falconsiena_filter_spec_t *saved_fs_spec;
+	efx_oword_t filter;
+	int filter_idx;
+	unsigned int depth;
+	int state;
+	uint32_t key;
 
-	spec->efs_type = EFX_FILTER_TX_TCP_FULL;
-	spec->efs_flags = 0;
-	spec->efs_dword[0] = src_tcp | src_ip << 16;
-	spec->efs_dword[1] = dest_tcp << 16 | src_ip >> 16;
-	spec->efs_dword[2] = dest_ip;
-}
-#endif	/* EFSYS_OPT_SIENA */
 
-#if EFSYS_OPT_SIENA
-extern			void
-efx_filter_spec_tx_ipv4_tcp_wild(
-	__inout		efx_filter_spec_t *spec,
-	__in		uint32_t src_ip,
-	__in		uint16_t src_tcp)
-{
 	EFSYS_ASSERT3P(spec, !=, NULL);
 
-	spec->efs_type = EFX_FILTER_TX_TCP_WILD;
-	spec->efs_flags = 0;
-	spec->efs_dword[0] = 0;
-	spec->efs_dword[1] = src_tcp << 16;
-	spec->efs_dword[2] = src_ip;
-}
-#endif	/* EFSYS_OPT_SIENA */
+	if ((rc = falconsiena_filter_spec_from_gen_spec(&fs_spec, spec)) != 0)
+		goto fail1;
 
-#if EFSYS_OPT_SIENA
-extern			void
-efx_filter_spec_tx_ipv4_udp_full(
-	__inout		efx_filter_spec_t *spec,
-	__in		uint32_t src_ip,
-	__in		uint16_t src_udp,
-	__in		uint32_t dest_ip,
-	__in		uint16_t dest_udp)
-{
-	EFSYS_ASSERT3P(spec, !=, NULL);
+	tbl_id = falconsiena_filter_tbl_id(fs_spec.fsfs_type);
+	fsftp = &fsfp->fsf_tbl[tbl_id];
 
-	spec->efs_type = EFX_FILTER_TX_UDP_FULL;
-	spec->efs_flags = 0;
-	spec->efs_dword[0] = src_udp | src_ip << 16;
-	spec->efs_dword[1] = dest_udp << 16 | src_ip >> 16;
-	spec->efs_dword[2] = dest_ip;
-}
-#endif	/* EFSYS_OPT_SIENA */
+	if (fsftp->fsft_size == 0) {
+		rc = EINVAL;
+		goto fail2;
+	}
 
-#if EFSYS_OPT_SIENA
-extern			void
-efx_filter_spec_tx_ipv4_udp_wild(
-	__inout		efx_filter_spec_t *spec,
-	__in		uint32_t src_ip,
-	__in		uint16_t src_udp)
-{
-	EFSYS_ASSERT3P(spec, !=, NULL);
+	key = falconsiena_filter_build(&filter, &fs_spec);
+
+	EFSYS_LOCK(enp->en_eslp, state);
+
+	rc = falconsiena_filter_search(fsftp, &fs_spec, key, B_TRUE,
+	    &filter_idx, &depth);
+	if (rc != 0)
+		goto fail3;
+
+	EFSYS_ASSERT3U(filter_idx, <, fsftp->fsft_size);
+	saved_fs_spec = &fsftp->fsft_spec[filter_idx];
+
+	if (falconsiena_filter_test_used(fsftp, filter_idx)) {
+		if (may_replace == B_FALSE) {
+			rc = EEXIST;
+			goto fail4;
+		}
+	}
+	falconsiena_filter_set_used(fsftp, filter_idx);
+	*saved_fs_spec = fs_spec;
+
+	if (fsfp->fsf_depth[fs_spec.fsfs_type] < depth) {
+		fsfp->fsf_depth[fs_spec.fsfs_type] = depth;
+		if (tbl_id == EFX_FS_FILTER_TBL_TX_IP ||
+		    tbl_id == EFX_FS_FILTER_TBL_TX_MAC)
+			falconsiena_filter_push_tx_limits(enp);
+		else
+			falconsiena_filter_push_rx_limits(enp);
+	}
+
+	falconsiena_filter_push_entry(enp, fs_spec.fsfs_type,
+	    filter_idx, &filter);
+
+	EFSYS_UNLOCK(enp->en_eslp, state);
+	return (0);
+
+fail4:
+	EFSYS_PROBE(fail4);
 
-	spec->efs_type = EFX_FILTER_TX_UDP_WILD;
-	spec->efs_flags = 0;
-	spec->efs_dword[0] = src_udp;
-	spec->efs_dword[1] = 0;
-	spec->efs_dword[2] = src_ip;
+fail3:
+	EFSYS_UNLOCK(enp->en_eslp, state);
+	EFSYS_PROBE(fail3);
+
+fail2:
+	EFSYS_PROBE(fail2);
+
+fail1:
+	EFSYS_PROBE1(fail1, int, rc);
+	return (rc);
 }
-#endif	/* EFSYS_OPT_SIENA */
 
-#if EFSYS_OPT_SIENA
-extern			void
-efx_filter_spec_tx_mac_full(
-	__inout		efx_filter_spec_t *spec,
-	__in		uint16_t vlan_id,
-	__in		uint8_t *src_mac)
+static	 __checkReturn	int
+falconsiena_filter_delete(
+	__in		efx_nic_t *enp,
+	__inout		efx_filter_spec_t *spec)
 {
+	int rc;
+	falconsiena_filter_spec_t fs_spec;
+	falconsiena_filter_t *fsfp = enp->en_filter.ef_falconsiena_filter;
+	falconsiena_filter_tbl_id_t tbl_id;
+	falconsiena_filter_tbl_t *fsftp;
+	falconsiena_filter_spec_t *saved_spec;
+	efx_oword_t filter;
+	int filter_idx;
+	unsigned int depth;
+	int state;
+	uint32_t key;
+
 	EFSYS_ASSERT3P(spec, !=, NULL);
-	EFSYS_ASSERT3P(src_mac, !=, NULL);
-
-	spec->efs_type = EFX_FILTER_TX_MAC_FULL;
-	spec->efs_flags = 0;
-	spec->efs_dword[0] = vlan_id;
-	spec->efs_dword[1] =
-	    src_mac[2] << 24 |
-	    src_mac[3] << 16 |
-	    src_mac[4] <<  8 |
-	    src_mac[5];
- 	spec->efs_dword[2] =
-	    src_mac[0] <<  8 |
-	    src_mac[1];
+
+	if ((rc = falconsiena_filter_spec_from_gen_spec(&fs_spec, spec)) != 0)
+		goto fail1;
+
+	tbl_id = falconsiena_filter_tbl_id(fs_spec.fsfs_type);
+	fsftp = &fsfp->fsf_tbl[tbl_id];
+
+	key = falconsiena_filter_build(&filter, &fs_spec);
+
+	EFSYS_LOCK(enp->en_eslp, state);
+
+	rc = falconsiena_filter_search(fsftp, &fs_spec, key, B_FALSE,
+	    &filter_idx, &depth);
+	if (rc != 0)
+		goto fail2;
+
+	saved_spec = &fsftp->fsft_spec[filter_idx];
+
+	falconsiena_filter_clear_entry(enp, fsftp, filter_idx);
+	if (fsftp->fsft_used == 0)
+		falconsiena_filter_reset_search_depth(fsfp, tbl_id);
+
+	EFSYS_UNLOCK(enp->en_eslp, state);
+	return (0);
+
+fail2:
+	EFSYS_UNLOCK(enp->en_eslp, state);
+	EFSYS_PROBE(fail2);
+
+fail1:
+	EFSYS_PROBE1(fail1, int, rc);
+	return (rc);
 }
-#endif	/* EFSYS_OPT_SIENA */
 
-#if EFSYS_OPT_SIENA
-extern			void
-efx_filter_spec_tx_mac_wild(
-	__inout		efx_filter_spec_t *spec,
-	__in		uint8_t *src_mac)
+#define	MAX_SUPPORTED 4
+
+static	__checkReturn	int
+falconsiena_filter_supported_filters(
+	__in		efx_nic_t *enp,
+	__out		uint32_t *list,
+	__out		size_t *length)
 {
-	EFSYS_ASSERT3P(spec, !=, NULL);
-	EFSYS_ASSERT3P(src_mac, !=, NULL);
-
-	spec->efs_type = EFX_FILTER_TX_MAC_WILD;
-	spec->efs_flags = 0;
-	spec->efs_dword[0] = 0;
-	spec->efs_dword[1] =
-	    src_mac[2] << 24 |
-	    src_mac[3] << 16 |
-	    src_mac[4] <<  8 |
-	    src_mac[5];
- 	spec->efs_dword[2] =
-	    src_mac[0] <<  8 |
-	    src_mac[1];
+	int index = 0;
+	uint32_t rx_matches[MAX_SUPPORTED];
+	int rc;
+
+	if (list == NULL) {
+		rc = EINVAL;
+		goto fail1;
+	}
+
+	rx_matches[index++] =
+	    EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO |
+	    EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT |
+	    EFX_FILTER_MATCH_REM_HOST | EFX_FILTER_MATCH_REM_PORT;
+
+	rx_matches[index++] =
+	    EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO |
+	    EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT;
+
+	if (enp->en_features & EFX_FEATURE_MAC_HEADER_FILTERS) {
+		rx_matches[index++] =
+		    EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC;
+
+		rx_matches[index++] = EFX_FILTER_MATCH_LOC_MAC;
+	}
+
+	EFSYS_ASSERT3U(index, <=, MAX_SUPPORTED);
+
+	*length = index;
+	memcpy(list, rx_matches, *length);
+
+	return (0);
+
+fail1:
+
+	return (rc);
 }
-#endif	/* EFSYS_OPT_SIENA */
 
+#undef MAX_SUPPORTED
+
+#endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */
 
 #endif /* EFSYS_OPT_FILTER */
diff --git a/sys/dev/sfxge/common/efx_hash.c b/sys/dev/sfxge/common/efx_hash.c
new file mode 100644
index 000000000000..3005c1bb4738
--- /dev/null
+++ b/sys/dev/sfxge/common/efx_hash.c
@@ -0,0 +1,333 @@
+/*-
+ * Copyright 2006 Bob Jenkins
+ *
+ * Derived from public domain source, see
+ *     <http://burtleburtle.net/bob/c/lookup3.c>:
+ *
+ * "lookup3.c, by Bob Jenkins, May 2006, Public Domain.
+ *
+ *  These are functions for producing 32-bit hashes for hash table lookup...
+ *  ...You can use this free for any purpose.  It's in the public domain.
+ *  It has no warranty."
+ *
+ * Copyright (c) 2014-2015 Solarflare Communications Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are
+ * those of the authors and should not be interpreted as representing official
+ * policies, either expressed or implied, of the FreeBSD Project.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include "efsys.h"
+#include "efx.h"
+#include "efx_types.h"
+#include "efx_impl.h"
+
+/* Hash initial value */
+#define	EFX_HASH_INITIAL_VALUE	0xdeadbeef
+
+/*
+ * Rotate a 32-bit value left
+ *
+ * Allow platform to provide an intrinsic or optimised routine and
+ * fall-back to a simple shift based implementation.
+ */
+#if EFSYS_HAS_ROTL_DWORD
+
+#define	EFX_HASH_ROTATE(_value, _shift)					\
+	EFSYS_ROTL_DWORD(_value, _shift)
+
+#else
+
+#define	EFX_HASH_ROTATE(_value, _shift)					\
+	(((_value) << (_shift)) | ((_value) >> (32 - (_shift))))
+
+#endif
+
+/* Mix three 32-bit values reversibly */
+#define	EFX_HASH_MIX(_a, _b, _c)					\
+	do {								\
+		_a -= _c;						\
+		_a ^= EFX_HASH_ROTATE(_c, 4);				\
+		_c += _b;						\
+		_b -= _a;						\
+		_b ^= EFX_HASH_ROTATE(_a, 6);				\
+		_a += _c;						\
+		_c -= _b;						\
+		_c ^= EFX_HASH_ROTATE(_b, 8);				\
+		_b += _a;						\
+		_a -= _c;						\
+		_a ^= EFX_HASH_ROTATE(_c, 16);				\
+		_c += _b;						\
+		_b -= _a;						\
+		_b ^= EFX_HASH_ROTATE(_a, 19);				\
+		_a += _c;						\
+		_c -= _b;						\
+		_c ^= EFX_HASH_ROTATE(_b, 4);				\
+		_b += _a;						\
+	_NOTE(CONSTANTCONDITION)					\
+	} while (B_FALSE)
+
+/* Final mixing of three 32-bit values into one (_c) */
+#define	EFX_HASH_FINALISE(_a, _b, _c)					\
+	do {								\
+		_c ^= _b;						\
+		_c -= EFX_HASH_ROTATE(_b, 14);				\
+		_a ^= _c;						\
+		_a -= EFX_HASH_ROTATE(_c, 11);				\
+		_b ^= _a;						\
+		_b -= EFX_HASH_ROTATE(_a, 25);				\
+		_c ^= _b;						\
+		_c -= EFX_HASH_ROTATE(_b, 16);				\
+		_a ^= _c;						\
+		_a -= EFX_HASH_ROTATE(_c, 4);				\
+		_b ^= _a;						\
+		_b -= EFX_HASH_ROTATE(_a, 14);				\
+		_c ^= _b;						\
+		_c -= EFX_HASH_ROTATE(_b, 24);				\
+	_NOTE(CONSTANTCONDITION)					\
+	} while (B_FALSE)
+
+
+/* Produce a 32-bit hash from 32-bit aligned input */
+	__checkReturn		uint32_t
+efx_hash_dwords(
+	__in_ecount(count)	uint32_t const *input,
+	__in			size_t count,
+	__in			uint32_t init)
+{
+	uint32_t a;
+	uint32_t b;
+	uint32_t c;
+
+	/* Set up the initial internal state */
+	a = b = c = EFX_HASH_INITIAL_VALUE +
+		(((uint32_t)count) * sizeof (uint32_t)) + init;
+
+	/* Handle all but the last three dwords of the input */
+	while (count > 3) {
+		a += input[0];
+		b += input[1];
+		c += input[2];
+		EFX_HASH_MIX(a, b, c);
+
+		count -= 3;
+		input += 3;
+	}
+
+	/* Handle the left-overs */
+	switch (count) {
+	case 3:
+		c += input[2];
+		/* Fall-through */
+	case 2:
+		b += input[1];
+		/* Fall-through */
+	case 1:
+		a += input[0];
+		EFX_HASH_FINALISE(a, b, c);
+		break;
+
+	case 0:
+		/* Should only get here if count parameter was zero */
+		break;
+	}
+
+	return (c);
+}
+
+#if EFSYS_IS_BIG_ENDIAN
+
+/* Produce a 32-bit hash from arbitrarily aligned input */
+	__checkReturn		uint32_t
+efx_hash_bytes(
+	__in_ecount(length)	uint8_t const *input,
+	__in			size_t length,
+	__in			uint32_t init)
+{
+	uint32_t a;
+	uint32_t b;
+	uint32_t c;
+
+	/* Set up the initial internal state */
+	a = b = c = EFX_HASH_INITIAL_VALUE + (uint32_t)length + init;
+
+	/* Handle all but the last twelve bytes of the input */
+	while (length > 12) {
+		a += ((uint32_t)input[0]) << 24;
+		a += ((uint32_t)input[1]) << 16;
+		a += ((uint32_t)input[2]) << 8;
+		a += ((uint32_t)input[3]);
+		b += ((uint32_t)input[4]) << 24;
+		b += ((uint32_t)input[5]) << 16;
+		b += ((uint32_t)input[6]) << 8;
+		b += ((uint32_t)input[7]);
+		c += ((uint32_t)input[8]) << 24;
+		c += ((uint32_t)input[9]) << 16;
+		c += ((uint32_t)input[10]) << 8;
+		c += ((uint32_t)input[11]);
+		EFX_HASH_MIX(a, b, c);
+		length -= 12;
+		input += 12;
+	}
+
+	/* Handle the left-overs */
+	switch (length) {
+	case 12:
+		c += ((uint32_t)input[11]);
+		/* Fall-through */
+	case 11:
+		c += ((uint32_t)input[10]) << 8;
+		/* Fall-through */
+	case 10:
+		c += ((uint32_t)input[9]) << 16;
+		/* Fall-through */
+	case 9:
+		c += ((uint32_t)input[8]) << 24;
+		/* Fall-through */
+	case 8:
+		b += ((uint32_t)input[7]);
+		/* Fall-through */
+	case 7:
+		b += ((uint32_t)input[6]) << 8;
+		/* Fall-through */
+	case 6:
+		b += ((uint32_t)input[5]) << 16;
+		/* Fall-through */
+	case 5:
+		b += ((uint32_t)input[4]) << 24;
+		/* Fall-through */
+	case 4:
+		a += ((uint32_t)input[3]);
+		/* Fall-through */
+	case 3:
+		a += ((uint32_t)input[2]) << 8;
+		/* Fall-through */
+	case 2:
+		a += ((uint32_t)input[1]) << 16;
+		/* Fall-through */
+	case 1:
+		a += ((uint32_t)input[0]) << 24;
+		EFX_HASH_FINALISE(a, b, c);
+		break;
+
+	case 0:
+		/* Should only get here if length parameter was zero */
+		break;
+	}
+
+	return (c);
+}
+
+#elif EFSYS_IS_LITTLE_ENDIAN
+
+/* Produce a 32-bit hash from arbitrarily aligned input */
+	__checkReturn		uint32_t
+efx_hash_bytes(
+	__in_ecount(length)	uint8_t const *input,
+	__in			size_t length,
+	__in			uint32_t init)
+{
+	uint32_t a;
+	uint32_t b;
+	uint32_t c;
+
+	/* Set up the initial internal state */
+	a = b = c = EFX_HASH_INITIAL_VALUE + (uint32_t)length + init;
+
+	/* Handle all but the last twelve bytes of the input */
+	while (length > 12) {
+		a += ((uint32_t)input[0]);
+		a += ((uint32_t)input[1]) << 8;
+		a += ((uint32_t)input[2]) << 16;
+		a += ((uint32_t)input[3]) << 24;
+		b += ((uint32_t)input[4]);
+		b += ((uint32_t)input[5]) << 8;
+		b += ((uint32_t)input[6]) << 16;
+		b += ((uint32_t)input[7]) << 24;
+		c += ((uint32_t)input[8]);
+		c += ((uint32_t)input[9]) << 8;
+		c += ((uint32_t)input[10]) << 16;
+		c += ((uint32_t)input[11]) << 24;
+		EFX_HASH_MIX(a, b, c);
+		length -= 12;
+		input += 12;
+	}
+
+	/* Handle the left-overs */
+	switch (length) {
+	case 12:
+		c += ((uint32_t)input[11]) << 24;
+		/* Fall-through */
+	case 11:
+		c += ((uint32_t)input[10]) << 16;
+		/* Fall-through */
+	case 10:
+		c += ((uint32_t)input[9]) << 8;
+		/* Fall-through */
+	case 9:
+		c += ((uint32_t)input[8]);
+		/* Fall-through */
+	case 8:
+		b += ((uint32_t)input[7]) << 24;
+		/* Fall-through */
+	case 7:
+		b += ((uint32_t)input[6]) << 16;
+		/* Fall-through */
+	case 6:
+		b += ((uint32_t)input[5]) << 8;
+		/* Fall-through */
+	case 5:
+		b += ((uint32_t)input[4]);
+		/* Fall-through */
+	case 4:
+		a += ((uint32_t)input[3]) << 24;
+		/* Fall-through */
+	case 3:
+		a += ((uint32_t)input[2]) << 16;
+		/* Fall-through */
+	case 2:
+		a += ((uint32_t)input[1]) << 8;
+		/* Fall-through */
+	case 1:
+		a += ((uint32_t)input[0]);
+		EFX_HASH_FINALISE(a, b, c);
+		break;
+
+	case 0:
+		/* Should only get here if length parameter was zero */
+		break;
+	}
+
+	return (c);
+}
+
+#else
+
+#error "Neither of EFSYS_IS_{BIG,LITTLE}_ENDIAN is set"
+
+#endif
diff --git a/sys/dev/sfxge/common/efx_impl.h b/sys/dev/sfxge/common/efx_impl.h
index e7c2231b52fc..6f72d5fe2c38 100644
--- a/sys/dev/sfxge/common/efx_impl.h
+++ b/sys/dev/sfxge/common/efx_impl.h
@@ -1,26 +1,31 @@
 /*-
- * Copyright 2007-2009 Solarflare Communications Inc.  All rights reserved.
+ * Copyright (c) 2007-2015 Solarflare Communications Inc.
+ * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
+ * modification, are permitted provided that the following conditions are met:
  *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are
+ * those of the authors and should not be interpreted as representing official
+ * policies, either expressed or implied, of the FreeBSD Project.
  *
  * $FreeBSD$
  */
@@ -31,6 +36,15 @@
 #include "efsys.h"
 #include "efx.h"
 #include "efx_regs.h"
+#include "efx_regs_ef10.h"
+
+/* FIXME: Add definition for driver generated software events */
+#ifndef	ESE_DZ_EV_CODE_DRV_GEN_EV
+#define	ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
+#endif
+
+#include "efx_check.h"
+
 
 #if EFSYS_OPT_FALCON
 #include "falcon_impl.h"
@@ -40,40 +54,138 @@
 #include "siena_impl.h"
 #endif	/* EFSYS_OPT_SIENA */
 
+#if EFSYS_OPT_HUNTINGTON
+#include "hunt_impl.h"
+#endif	/* EFSYS_OPT_HUNTINGTON */
+
 #ifdef	__cplusplus
 extern "C" {
 #endif
 
-#define	EFX_MOD_MCDI	0x00000001
-#define	EFX_MOD_PROBE	0x00000002
-#define	EFX_MOD_NVRAM	0x00000004
-#define	EFX_MOD_VPD	0x00000008
-#define	EFX_MOD_NIC	0x00000010
-#define	EFX_MOD_INTR	0x00000020
-#define	EFX_MOD_EV	0x00000040
-#define	EFX_MOD_RX	0x00000080
-#define	EFX_MOD_TX	0x00000100
-#define	EFX_MOD_PORT	0x00000200
-#define	EFX_MOD_MON	0x00000400
-#define	EFX_MOD_WOL	0x00000800
-#define	EFX_MOD_FILTER	0x00001000
-
-#define	EFX_RESET_MAC	0x00000001
-#define	EFX_RESET_PHY	0x00000002
+#define	EFX_MOD_MCDI		0x00000001
+#define	EFX_MOD_PROBE		0x00000002
+#define	EFX_MOD_NVRAM		0x00000004
+#define	EFX_MOD_VPD		0x00000008
+#define	EFX_MOD_NIC		0x00000010
+#define	EFX_MOD_INTR		0x00000020
+#define	EFX_MOD_EV		0x00000040
+#define	EFX_MOD_RX		0x00000080
+#define	EFX_MOD_TX		0x00000100
+#define	EFX_MOD_PORT		0x00000200
+#define	EFX_MOD_MON		0x00000400
+#define	EFX_MOD_WOL		0x00000800
+#define	EFX_MOD_FILTER		0x00001000
+#define	EFX_MOD_PKTFILTER	0x00002000
+
+#define	EFX_RESET_MAC		0x00000001
+#define	EFX_RESET_PHY		0x00000002
+#define	EFX_RESET_RXQ_ERR	0x00000004
+#define	EFX_RESET_TXQ_ERR	0x00000008
 
 typedef enum efx_mac_type_e {
 	EFX_MAC_INVALID = 0,
 	EFX_MAC_FALCON_GMAC,
 	EFX_MAC_FALCON_XMAC,
 	EFX_MAC_SIENA,
+	EFX_MAC_HUNTINGTON,
 	EFX_MAC_NTYPES
 } efx_mac_type_t;
 
+typedef struct efx_ev_ops_s {
+	int		(*eevo_init)(efx_nic_t *);
+	void		(*eevo_fini)(efx_nic_t *);
+	int		(*eevo_qcreate)(efx_nic_t *, unsigned int,
+					  efsys_mem_t *, size_t, uint32_t,
+					  efx_evq_t *);
+	void		(*eevo_qdestroy)(efx_evq_t *);
+	int		(*eevo_qprime)(efx_evq_t *, unsigned int);
+	void		(*eevo_qpost)(efx_evq_t *, uint16_t);
+	int		(*eevo_qmoderate)(efx_evq_t *, unsigned int);
+#if EFSYS_OPT_QSTATS
+	void		(*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
+#endif
+} efx_ev_ops_t;
+
+typedef struct efx_tx_ops_s {
+	int		(*etxo_init)(efx_nic_t *);
+	void		(*etxo_fini)(efx_nic_t *);
+	int		(*etxo_qcreate)(efx_nic_t *,
+					unsigned int, unsigned int,
+					efsys_mem_t *, size_t,
+					uint32_t, uint16_t,
+					efx_evq_t *, efx_txq_t *,
+					unsigned int *);
+	void		(*etxo_qdestroy)(efx_txq_t *);
+	int		(*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
+				      unsigned int, unsigned int,
+				      unsigned int *);
+	void		(*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
+	int		(*etxo_qpace)(efx_txq_t *, unsigned int);
+	int		(*etxo_qflush)(efx_txq_t *);
+	void		(*etxo_qenable)(efx_txq_t *);
+	int		(*etxo_qpio_enable)(efx_txq_t *);
+	void		(*etxo_qpio_disable)(efx_txq_t *);
+	int		(*etxo_qpio_write)(efx_txq_t *,uint8_t *, size_t,
+					   size_t);
+	int		(*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
+					   unsigned int *);
+	int		(*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
+				      unsigned int, unsigned int,
+				      unsigned int *);
+	void		(*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
+						size_t, boolean_t,
+						efx_desc_t *);
+	void		(*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
+						uint32_t, uint8_t,
+						efx_desc_t *);
+	void		(*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
+						efx_desc_t *);
+#if EFSYS_OPT_QSTATS
+	void		(*etxo_qstats_update)(efx_txq_t *,
+					      efsys_stat_t *);
+#endif
+} efx_tx_ops_t;
+
+typedef struct efx_rx_ops_s {
+	int		(*erxo_init)(efx_nic_t *);
+	void		(*erxo_fini)(efx_nic_t *);
+#if EFSYS_OPT_RX_HDR_SPLIT
+	int		(*erxo_hdr_split_enable)(efx_nic_t *, unsigned int,
+						 unsigned int);
+#endif
+#if EFSYS_OPT_RX_SCATTER
+	int		(*erxo_scatter_enable)(efx_nic_t *, unsigned int);
+#endif
+#if EFSYS_OPT_RX_SCALE
+	int		(*erxo_scale_mode_set)(efx_nic_t *, efx_rx_hash_alg_t,
+					       efx_rx_hash_type_t, boolean_t);
+	int		(*erxo_scale_key_set)(efx_nic_t *, uint8_t *, size_t);
+	int		(*erxo_scale_tbl_set)(efx_nic_t *, unsigned int *,
+					      size_t);
+#endif
+	void		(*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
+				      unsigned int, unsigned int,
+				      unsigned int);
+	void		(*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
+	int		(*erxo_qflush)(efx_rxq_t *);
+	void		(*erxo_qenable)(efx_rxq_t *);
+	int		(*erxo_qcreate)(efx_nic_t *enp, unsigned int,
+					unsigned int, efx_rxq_type_t,
+					efsys_mem_t *, size_t, uint32_t,
+					efx_evq_t *, efx_rxq_t *);
+	void		(*erxo_qdestroy)(efx_rxq_t *);
+} efx_rx_ops_t;
+
 typedef struct efx_mac_ops_s {
 	int		(*emo_reset)(efx_nic_t *); /* optional */
 	int		(*emo_poll)(efx_nic_t *, efx_link_mode_t *);
 	int		(*emo_up)(efx_nic_t *, boolean_t *);
+	int		(*emo_addr_set)(efx_nic_t *);
 	int		(*emo_reconfigure)(efx_nic_t *);
+	int		(*emo_multicast_list_set)(efx_nic_t *);
+	int		(*emo_filter_default_rxq_set)(efx_nic_t *,
+						      efx_rxq_t *, boolean_t);
+	void		(*emo_filter_default_rxq_clear)(efx_nic_t *);
 #if EFSYS_OPT_LOOPBACK
 	int		(*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
 					    efx_loopback_type_t);
@@ -103,21 +215,59 @@ typedef struct efx_phy_ops_s {
 #endif	/* EFSYS_OPT_PHY_STATS */
 #if EFSYS_OPT_PHY_PROPS
 #if EFSYS_OPT_NAMES
-	const char	__cs *(*epo_prop_name)(efx_nic_t *, unsigned int);
+	const char	*(*epo_prop_name)(efx_nic_t *, unsigned int);
 #endif	/* EFSYS_OPT_PHY_PROPS */
 	int		(*epo_prop_get)(efx_nic_t *, unsigned int, uint32_t,
 					uint32_t *);
 	int		(*epo_prop_set)(efx_nic_t *, unsigned int, uint32_t);
 #endif	/* EFSYS_OPT_PHY_PROPS */
-#if EFSYS_OPT_PHY_BIST
-	int		(*epo_bist_start)(efx_nic_t *, efx_phy_bist_type_t);
-	int		(*epo_bist_poll)(efx_nic_t *, efx_phy_bist_type_t,
-					 efx_phy_bist_result_t *, uint32_t *,
+#if EFSYS_OPT_BIST
+	int		(*epo_bist_enable_offline)(efx_nic_t *);
+	int		(*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
+	int		(*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
+					 efx_bist_result_t *, uint32_t *,
 					 unsigned long *, size_t);
-	void		(*epo_bist_stop)(efx_nic_t *, efx_phy_bist_type_t);
-#endif	/* EFSYS_OPT_PHY_BIST */
+	void		(*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
+#endif	/* EFSYS_OPT_BIST */
 } efx_phy_ops_t;
 
+#if EFSYS_OPT_FILTER
+typedef struct efx_filter_ops_s {
+	int	(*efo_init)(efx_nic_t *);
+	void	(*efo_fini)(efx_nic_t *);
+	int	(*efo_restore)(efx_nic_t *);
+	int     (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
+	boolean_t may_replace);
+	int     (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
+	int	(*efo_supported_filters)(efx_nic_t *, uint32_t *, size_t *);
+	int	(*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
+				   boolean_t, boolean_t, boolean_t,
+				   uint8_t const *, int);
+} efx_filter_ops_t;
+
+extern	__checkReturn	int
+efx_filter_reconfigure(
+	__in				efx_nic_t *enp,
+	__in_ecount(6)			uint8_t const *mac_addr,
+	__in				boolean_t all_unicst,
+	__in				boolean_t mulcst,
+	__in				boolean_t all_mulcst,
+	__in				boolean_t brdcst,
+	__in_ecount(6*count)		uint8_t const *addrs,
+	__in				int count);
+
+#endif /* EFSYS_OPT_FILTER */
+
+typedef struct efx_pktfilter_ops_s {
+	int	(*epfo_set)(efx_nic_t *,
+				boolean_t unicst,
+				boolean_t brdcast);
+#if EFSYS_OPT_MCAST_FILTER_LIST
+	int	(*epfo_mcast_list_set)(efx_nic_t *, uint8_t const *addrs, int count);
+#endif /* EFSYS_OPT_MCAST_FILTER_LIST */
+	int	(*epfo_mcast_all)(efx_nic_t *);
+} efx_pktfilter_ops_t;
+
 typedef struct efx_port_s {
 	efx_mac_type_t		ep_mac_type;
 	uint32_t  		ep_phy_type;
@@ -125,11 +275,16 @@ typedef struct efx_port_s {
 	uint32_t		ep_mac_pdu;
 	uint8_t			ep_mac_addr[6];
 	efx_link_mode_t		ep_link_mode;
-	boolean_t		ep_unicst;
+	boolean_t		ep_all_unicst;
+	boolean_t		ep_mulcst;
+	boolean_t		ep_all_mulcst;
 	boolean_t		ep_brdcst;
 	unsigned int		ep_fcntl;
 	boolean_t		ep_fcntl_autoneg;
 	efx_oword_t		ep_multicst_hash[2];
+	uint8_t			ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
+						    EFX_MAC_MULTICAST_LIST_MAX];
+	uint32_t		ep_mulcst_addr_count;
 #if EFSYS_OPT_LOOPBACK
 	efx_loopback_type_t	ep_loopback_type;
 	efx_link_mode_t		ep_loopback_link_mode;
@@ -161,8 +316,8 @@ typedef struct efx_port_s {
 	uint32_t		ep_fwver; /* falcon only */
 	boolean_t		ep_mac_drain;
 	boolean_t		ep_mac_stats_pending;
-#if EFSYS_OPT_PHY_BIST
-	efx_phy_bist_type_t	ep_current_bist;
+#if EFSYS_OPT_BIST
+	efx_bist_type_t		ep_current_bist;
 #endif
 	efx_mac_ops_t		*ep_emop;
 	efx_phy_ops_t		*ep_epop;
@@ -182,16 +337,30 @@ typedef struct efx_mon_s {
 	efx_mon_ops_t	*em_emop;
 } efx_mon_t;
 
+typedef struct efx_intr_ops_s {
+	int		(*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
+	void		(*eio_enable)(efx_nic_t *);
+	void		(*eio_disable)(efx_nic_t *);
+	void		(*eio_disable_unlocked)(efx_nic_t *);
+	int		(*eio_trigger)(efx_nic_t *, unsigned int);
+	void		(*eio_fini)(efx_nic_t *);
+} efx_intr_ops_t;
+
 typedef struct efx_intr_s {
-	efx_intr_type_t	ei_type;
+	efx_intr_ops_t	*ei_eiop;
 	efsys_mem_t	*ei_esmp;
+	efx_intr_type_t	ei_type;
 	unsigned int	ei_level;
 } efx_intr_t;
 
 typedef struct efx_nic_ops_s {
 	int	(*eno_probe)(efx_nic_t *);
+	int	(*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
 	int	(*eno_reset)(efx_nic_t *);
 	int	(*eno_init)(efx_nic_t *);
+	int	(*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
+	int	(*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t, 
+					uint32_t *, size_t *);
 #if EFSYS_OPT_DIAG
 	int	(*eno_sram_test)(efx_nic_t *, efx_sram_pattern_fn_t);
 	int	(*eno_register_test)(efx_nic_t *);
@@ -201,94 +370,107 @@ typedef struct efx_nic_ops_s {
 } efx_nic_ops_t;
 
 #ifndef EFX_TXQ_LIMIT_TARGET
-# define EFX_TXQ_LIMIT_TARGET 259
+#define	EFX_TXQ_LIMIT_TARGET 259
 #endif
 #ifndef EFX_RXQ_LIMIT_TARGET
-# define EFX_RXQ_LIMIT_TARGET 512
+#define	EFX_RXQ_LIMIT_TARGET 512
 #endif
 #ifndef EFX_TXQ_DC_SIZE
-#define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
+#define	EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
 #endif
 #ifndef EFX_RXQ_DC_SIZE
-#define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
+#define	EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
 #endif
 
 #if EFSYS_OPT_FILTER
 
-typedef enum efx_filter_type_e {
-	EFX_FILTER_RX_TCP_FULL,	/* TCP/IPv4 4-tuple {dIP,dTCP,sIP,sTCP} */
-	EFX_FILTER_RX_TCP_WILD,	/* TCP/IPv4 dest    {dIP,dTCP,  -,   -} */
-	EFX_FILTER_RX_UDP_FULL,	/* UDP/IPv4 4-tuple {dIP,dUDP,sIP,sUDP} */
-	EFX_FILTER_RX_UDP_WILD,	/* UDP/IPv4 dest    {dIP,dUDP,  -,   -} */
+typedef struct falconsiena_filter_spec_s {
+	uint8_t		fsfs_type;
+	uint32_t	fsfs_flags;
+	uint32_t	fsfs_dmaq_id;
+	uint32_t	fsfs_dword[3];
+} falconsiena_filter_spec_t;
+
+typedef enum falconsiena_filter_type_e {
+	EFX_FS_FILTER_RX_TCP_FULL,	/* TCP/IPv4 4-tuple {dIP,dTCP,sIP,sTCP} */
+	EFX_FS_FILTER_RX_TCP_WILD,	/* TCP/IPv4 dest    {dIP,dTCP,  -,   -} */
+	EFX_FS_FILTER_RX_UDP_FULL,	/* UDP/IPv4 4-tuple {dIP,dUDP,sIP,sUDP} */
+	EFX_FS_FILTER_RX_UDP_WILD,	/* UDP/IPv4 dest    {dIP,dUDP,  -,   -} */
 
 #if EFSYS_OPT_SIENA
-	EFX_FILTER_RX_MAC_FULL,	/* Ethernet {dMAC,VLAN} */
-	EFX_FILTER_RX_MAC_WILD,	/* Ethernet {dMAC,   -} */
+	EFX_FS_FILTER_RX_MAC_FULL,	/* Ethernet {dMAC,VLAN} */
+	EFX_FS_FILTER_RX_MAC_WILD,	/* Ethernet {dMAC,   -} */
 
-	EFX_FILTER_TX_TCP_FULL,		/* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
-	EFX_FILTER_TX_TCP_WILD,		/* TCP/IPv4 {  -,   -,sIP,sTCP} */
-	EFX_FILTER_TX_UDP_FULL,		/* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
-	EFX_FILTER_TX_UDP_WILD,		/* UDP/IPv4 source (host, port) */
+	EFX_FS_FILTER_TX_TCP_FULL,		/* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
+	EFX_FS_FILTER_TX_TCP_WILD,		/* TCP/IPv4 {  -,   -,sIP,sTCP} */
+	EFX_FS_FILTER_TX_UDP_FULL,		/* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
+	EFX_FS_FILTER_TX_UDP_WILD,		/* UDP/IPv4 source (host, port) */
 
-	EFX_FILTER_TX_MAC_FULL,		/* Ethernet source (MAC address, VLAN ID) */
-	EFX_FILTER_TX_MAC_WILD,		/* Ethernet source (MAC address) */
+	EFX_FS_FILTER_TX_MAC_FULL,		/* Ethernet source (MAC address, VLAN ID) */
+	EFX_FS_FILTER_TX_MAC_WILD,		/* Ethernet source (MAC address) */
 #endif /* EFSYS_OPT_SIENA */
 
-	EFX_FILTER_NTYPES
-} efx_filter_type_t;
-
-typedef enum efx_filter_tbl_id_e {
-	EFX_FILTER_TBL_RX_IP = 0,
-	EFX_FILTER_TBL_RX_MAC,
-	EFX_FILTER_TBL_TX_IP,
-	EFX_FILTER_TBL_TX_MAC,
-	EFX_FILTER_NTBLS
-} efx_filter_tbl_id_t;
-
-typedef struct efx_filter_tbl_s {
-	int			eft_size;	/* number of entries */
-	int			eft_used;	/* active count */
-	uint32_t		*eft_bitmap;	/* active bitmap */
-	efx_filter_spec_t	*eft_spec;	/* array of saved specs */
-} efx_filter_tbl_t;
+	EFX_FS_FILTER_NTYPES
+} falconsiena_filter_type_t;
+
+typedef enum falconsiena_filter_tbl_id_e {
+	EFX_FS_FILTER_TBL_RX_IP = 0,
+	EFX_FS_FILTER_TBL_RX_MAC,
+	EFX_FS_FILTER_TBL_TX_IP,
+	EFX_FS_FILTER_TBL_TX_MAC,
+	EFX_FS_FILTER_NTBLS
+} falconsiena_filter_tbl_id_t;
+
+typedef struct falconsiena_filter_tbl_s {
+	int				fsft_size;	/* number of entries */
+	int				fsft_used;	/* active count */
+	uint32_t			*fsft_bitmap;	/* active bitmap */
+	falconsiena_filter_spec_t	*fsft_spec;	/* array of saved specs */
+} falconsiena_filter_tbl_t;
+
+typedef struct falconsiena_filter_s {
+	falconsiena_filter_tbl_t	fsf_tbl[EFX_FS_FILTER_NTBLS];
+	unsigned int			fsf_depth[EFX_FS_FILTER_NTYPES];
+} falconsiena_filter_t;
 
 typedef struct efx_filter_s {
-	efx_filter_tbl_t	ef_tbl[EFX_FILTER_NTBLS];
-	unsigned int		ef_depth[EFX_FILTER_NTYPES];
+#if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA
+	falconsiena_filter_t	*ef_falconsiena_filter;
+#endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */
+#if EFSYS_OPT_HUNTINGTON
+	hunt_filter_table_t	*ef_hunt_filter_table;
+#endif /* EFSYS_OPT_HUNTINGTON */
 } efx_filter_t;
 
-
-extern	__checkReturn	int
-efx_filter_insert_filter(
-	__in		efx_nic_t *enp,
-	__in		efx_filter_spec_t *spec,
-	__in		boolean_t replace);
-
-extern	__checkReturn	int
-efx_filter_remove_filter(
-	__in		efx_nic_t *enp,
-	__in		efx_filter_spec_t *spec);
-
-extern			void
-efx_filter_remove_index(
-	__inout		efx_nic_t *enp,
-	__in		efx_filter_type_t type,
-	__in		int filter_idx);
-
 extern			void
-efx_filter_redirect_index(
-	__inout		efx_nic_t *enp,
-	__in		efx_filter_type_t type,
-	__in		int filter_index,
-	__in		int rxq_index);
-
-extern	__checkReturn	int
-efx_filter_clear_tbl(
+falconsiena_filter_tbl_clear(
 	__in		efx_nic_t *enp,
-	__in		efx_filter_tbl_id_t tbl);
+	__in		falconsiena_filter_tbl_id_t tbl);
 
 #endif	/* EFSYS_OPT_FILTER */
 
+#if EFSYS_OPT_MCDI
+
+typedef struct efx_mcdi_ops_s {
+	int		(*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
+	void		(*emco_request_copyin)(efx_nic_t *, efx_mcdi_req_t *,
+					unsigned int, boolean_t, boolean_t);
+	boolean_t	(*emco_request_poll)(efx_nic_t *);
+	void		(*emco_request_copyout)(efx_nic_t *, efx_mcdi_req_t *);
+	int		(*emco_poll_reboot)(efx_nic_t *);
+	void		(*emco_fini)(efx_nic_t *);
+	int		(*emco_fw_update_supported)(efx_nic_t *, boolean_t *);
+	int		(*emco_macaddr_change_supported)(efx_nic_t *, boolean_t *);
+} efx_mcdi_ops_t;
+
+typedef struct efx_mcdi_s {
+	efx_mcdi_ops_t			*em_emcop;
+	const efx_mcdi_transport_t	*em_emtp;
+	efx_mcdi_iface_t		em_emip;
+} efx_mcdi_t;
+
+#endif /* EFSYS_OPT_MCDI */
+
 #if EFSYS_OPT_NVRAM
 typedef struct efx_nvram_ops_s {
 #if EFSYS_OPT_DIAG
@@ -325,6 +507,85 @@ typedef struct efx_vpd_ops_s {
 } efx_vpd_ops_t;
 #endif	/* EFSYS_OPT_VPD */
 
+#if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
+
+	__checkReturn		int
+efx_mcdi_nvram_partitions(
+	__in			efx_nic_t *enp,
+	__out_bcount(size)	caddr_t data,
+	__in			size_t size,
+	__out			unsigned int *npartnp);
+
+	__checkReturn		int
+efx_mcdi_nvram_metadata(
+	__in			efx_nic_t *enp,
+	__in			uint32_t partn,
+	__out			uint32_t *subtypep,
+	__out_ecount(4)		uint16_t version[4],
+	__out_bcount_opt(size)	char *descp,
+	__in			size_t size);
+
+	__checkReturn		int
+efx_mcdi_nvram_info(
+	__in			efx_nic_t *enp,
+	__in			uint32_t partn,
+	__out_opt		size_t *sizep,
+	__out_opt		uint32_t *addressp,
+	__out_opt		uint32_t *erase_sizep);
+
+	__checkReturn		int
+efx_mcdi_nvram_update_start(
+	__in			efx_nic_t *enp,
+	__in			uint32_t partn);
+
+	__checkReturn		int
+efx_mcdi_nvram_read(
+	__in			efx_nic_t *enp,
+	__in			uint32_t partn,
+	__in			uint32_t offset,
+	__out_bcount(size)	caddr_t data,
+	__in			size_t size);
+
+	__checkReturn		int
+efx_mcdi_nvram_erase(
+	__in			efx_nic_t *enp,
+	__in			uint32_t partn,
+	__in			uint32_t offset,
+	__in			size_t size);
+
+	__checkReturn		int
+efx_mcdi_nvram_write(
+	__in			efx_nic_t *enp,
+	__in			uint32_t partn,
+	__in			uint32_t offset,
+	__out_bcount(size)	caddr_t data,
+	__in			size_t size);
+
+	__checkReturn		int
+efx_mcdi_nvram_update_finish(
+	__in			efx_nic_t *enp,
+	__in			uint32_t partn,
+	__in			boolean_t reboot);
+
+#if EFSYS_OPT_DIAG
+
+	__checkReturn		int
+efx_mcdi_nvram_test(
+	__in			efx_nic_t *enp,
+	__in			uint32_t partn);
+
+#endif	/* EFSYS_OPT_DIAG */
+
+#endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
+
+typedef struct efx_drv_cfg_s {
+	uint32_t		edc_min_vi_count;
+	uint32_t		edc_max_vi_count;
+
+	uint32_t		edc_max_piobuf_count;
+	uint32_t		edc_pio_alloc_size;
+} efx_drv_cfg_t;
+
 struct efx_nic_s {
 	uint32_t		en_magic;
 	efx_family_t		en_family;
@@ -335,6 +596,7 @@ struct efx_nic_s {
 	unsigned int		en_mod_flags;
 	unsigned int		en_reset_flags;
 	efx_nic_cfg_t		en_nic_cfg;
+	efx_drv_cfg_t		en_drv_cfg;
 	efx_port_t		en_port;
 	efx_mon_t		en_mon;
 	efx_intr_t		en_intr;
@@ -342,9 +604,17 @@ struct efx_nic_s {
 	uint32_t		en_rx_qcount;
 	uint32_t		en_tx_qcount;
 	efx_nic_ops_t		*en_enop;
+	efx_ev_ops_t		*en_eevop;
+	efx_tx_ops_t		*en_etxop;
+	efx_rx_ops_t		*en_erxop;
 #if EFSYS_OPT_FILTER
 	efx_filter_t		en_filter;
+	efx_filter_ops_t	*en_efop;
 #endif	/* EFSYS_OPT_FILTER */
+	efx_pktfilter_ops_t	*en_epfop;
+#if EFSYS_OPT_MCDI
+	efx_mcdi_t		en_mcdi;
+#endif	/* EFSYS_OPT_MCDI */
 #if EFSYS_OPT_NVRAM
 	efx_nvram_type_t	en_nvram_locked;
 	efx_nvram_ops_t		*en_envop;
@@ -352,6 +622,12 @@ struct efx_nic_s {
 #if EFSYS_OPT_VPD
 	efx_vpd_ops_t		*en_evpdop;
 #endif	/* EFSYS_OPT_VPD */
+#if EFSYS_OPT_RX_SCALE
+	efx_rx_hash_support_t	en_hash_support;
+	efx_rx_scale_support_t	en_rss_support;
+	uint32_t		en_rss_context;
+#endif	/* EFSYS_OPT_RX_SCALE */
+	uint32_t		en_vport_id;
 	union {
 #if EFSYS_OPT_FALCON
 		struct {
@@ -373,9 +649,6 @@ struct efx_nic_s {
 #endif	/* EFSYS_OPT_FALCON */
 #if EFSYS_OPT_SIENA
 		struct {
-#if EFSYS_OPT_MCDI
-			efx_mcdi_iface_t	enu_mip;
-#endif	/* EFSYS_OPT_MCDI */
 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
 			unsigned int		enu_partn_mask;
 #endif	/* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
@@ -383,8 +656,28 @@ struct efx_nic_s {
 			caddr_t			enu_svpd;
 			size_t			enu_svpd_length;
 #endif	/* EFSYS_OPT_VPD */
+			int			enu_unused;
 		} siena;
 #endif	/* EFSYS_OPT_SIENA */
+#if EFSYS_OPT_HUNTINGTON
+		struct {
+			int			enu_vi_base;
+			int			enu_vi_count;
+#if EFSYS_OPT_VPD
+			caddr_t			enu_svpd;
+			size_t			enu_svpd_length;
+#endif	/* EFSYS_OPT_VPD */
+			efx_piobuf_handle_t	enu_piobuf_handle[HUNT_PIOBUF_NBUFS];
+			uint32_t		enu_piobuf_count;
+			uint32_t		enu_pio_alloc_map[HUNT_PIOBUF_NBUFS];
+			uint32_t		enu_pio_write_vi_base;
+			/* Memory BAR mapping regions */
+			uint32_t		enu_uc_mem_map_offset;
+			size_t			enu_uc_mem_map_size;
+			uint32_t		enu_wc_mem_map_offset;
+			size_t			enu_wc_mem_map_size;
+		} hunt;
+#endif	/* EFSYS_OPT_HUNTINGTON */
 	} en_u;
 };
 
@@ -394,6 +687,11 @@ struct efx_nic_s {
 typedef	boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
     const efx_ev_callbacks_t *, void *);
 
+typedef struct efx_evq_rxq_state_s {
+	unsigned int			eers_rx_read_ptr;
+	unsigned int			eers_rx_mask;
+} efx_evq_rxq_state_t;
+
 struct efx_evq_s {
 	uint32_t			ee_magic;
 	efx_nic_t			*ee_enp;
@@ -403,7 +701,17 @@ struct efx_evq_s {
 #if EFSYS_OPT_QSTATS
 	uint32_t			ee_stat[EV_NQSTATS];
 #endif	/* EFSYS_OPT_QSTATS */
-	efx_ev_handler_t		ee_handler[1 << FSF_AZ_EV_CODE_WIDTH];
+
+	efx_ev_handler_t		ee_rx;
+	efx_ev_handler_t		ee_tx;
+	efx_ev_handler_t		ee_driver;
+	efx_ev_handler_t		ee_global;
+	efx_ev_handler_t		ee_drv_gen;
+#if EFSYS_OPT_MCDI
+	efx_ev_handler_t		ee_mcdi;
+#endif	/* EFSYS_OPT_MCDI */
+
+	efx_evq_rxq_state_t		ee_rxq_state[EFX_EV_RX_NLABELS];
 };
 
 #define	EFX_EVQ_MAGIC	0x08081997
@@ -414,7 +722,9 @@ struct efx_evq_s {
 struct efx_rxq_s {
 	uint32_t			er_magic;
 	efx_nic_t			*er_enp;
+	efx_evq_t			*er_eep;
 	unsigned int			er_index;
+	unsigned int			er_label;
 	unsigned int			er_mask;
 	efsys_mem_t			*er_esmp;
 };
@@ -427,6 +737,13 @@ struct efx_txq_s {
 	unsigned int			et_index;
 	unsigned int			et_mask;
 	efsys_mem_t			*et_esmp;
+#if EFSYS_OPT_HUNTINGTON
+	uint32_t			et_pio_bufnum;
+	uint32_t			et_pio_blknum;
+	uint32_t			et_pio_write_offset;
+	uint32_t			et_pio_offset;
+	size_t				et_pio_size;
+#endif
 #if EFSYS_OPT_QSTATS
 	uint32_t			et_stat[TX_NQSTATS];
 #endif	/* EFSYS_OPT_QSTATS */
@@ -445,10 +762,19 @@ struct efx_txq_s {
 	_NOTE(CONSTANTCONDITION)					\
 	} while (B_FALSE)
 
+#define	EFX_MAC_BROADCAST_ADDR_SET(_dst)				\
+	do {								\
+		uint16_t *_d = (uint16_t *)(_dst);			\
+		_d[0] = 0xffff;						\
+		_d[1] = 0xffff;						\
+		_d[2] = 0xffff;						\
+	_NOTE(CONSTANTCONDITION)					\
+	} while (B_FALSE)
+
 #if EFSYS_OPT_CHECK_REG
 #define	EFX_CHECK_REG(_enp, _reg)					\
 	do {								\
-		const char __cs *name = #_reg;				\
+		const char *name = #_reg;				\
 		char min = name[4];					\
 		char max = name[5];					\
 		char rev;						\
@@ -462,6 +788,10 @@ struct efx_txq_s {
 			rev = 'C';					\
 			break;						\
 									\
+		case EFX_FAMILY_HUNTINGTON:				\
+			rev = 'D';					\
+			break;						\
+									\
 		default:						\
 			rev = '?';					\
 			break;						\
@@ -578,6 +908,21 @@ struct efx_txq_s {
 	_NOTE(CONSTANTCONDITION)					\
 	} while (B_FALSE)
 
+#define	EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock)		\
+	do {								\
+		EFX_CHECK_REG((_enp), (_reg));				\
+		EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,	\
+		    uint32_t, (_index),					\
+		    uint32_t, _reg ## _OFST,				\
+		    uint32_t, (_edp)->ed_u32[0]);			\
+		EFSYS_BAR_WRITED((_enp)->en_esbp,			\
+		    (_reg ## _OFST +					\
+		    (2 * sizeof (efx_dword_t)) + 			\
+		    ((_index) * _reg ## _STEP)),			\
+		    (_edp), (_lock));					\
+	_NOTE(CONSTANTCONDITION)					\
+	} while (B_FALSE)
+
 #define	EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock)		\
 	do {								\
 		EFX_CHECK_REG((_enp), (_reg));				\
@@ -621,12 +966,12 @@ struct efx_txq_s {
 	_NOTE(CONSTANTCONDITION)					\
 	} while (B_FALSE)
 
-#define	EFX_BAR_TBL_READO(_enp, _reg, _index, _eop)			\
+#define	EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock)		\
 	do {								\
 		EFX_CHECK_REG((_enp), (_reg));				\
 		EFSYS_BAR_READO((_enp)->en_esbp,			\
 		    (_reg ## _OFST + ((_index) * _reg ## _STEP)),	\
-		    (_eop), B_TRUE);					\
+		    (_eop), (_lock));					\
 		EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg,	\
 		    uint32_t, (_index),					\
 		    uint32_t, _reg ## _OFST,				\
@@ -637,7 +982,7 @@ struct efx_txq_s {
 	_NOTE(CONSTANTCONDITION)					\
 	} while (B_FALSE)
 
-#define	EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop)			\
+#define	EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock)		\
 	do {								\
 		EFX_CHECK_REG((_enp), (_reg));				\
 		EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg,	\
@@ -649,14 +994,71 @@ struct efx_txq_s {
 		    uint32_t, (_eop)->eo_u32[0]);			\
 		EFSYS_BAR_WRITEO((_enp)->en_esbp,			\
 		    (_reg ## _OFST + ((_index) * _reg ## _STEP)),	\
-		    (_eop), B_TRUE);					\
+		    (_eop), (_lock));					\
+	_NOTE(CONSTANTCONDITION)					\
+	} while (B_FALSE)
+
+/*
+ * Allow drivers to perform optimised 128-bit doorbell writes.
+ * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
+ * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
+ * the need for locking in the host, and are the only ones known to be safe to
+ * use 128-bites write with.
+ */
+#define	EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop)		\
+	do {								\
+		EFX_CHECK_REG((_enp), (_reg));				\
+		EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo,		\
+		    const char *,					\
+		    #_reg,						\
+		    uint32_t, (_index),					\
+		    uint32_t, _reg ## _OFST,				\
+		    uint32_t, (_eop)->eo_u32[3],			\
+		    uint32_t, (_eop)->eo_u32[2],			\
+		    uint32_t, (_eop)->eo_u32[1],			\
+		    uint32_t, (_eop)->eo_u32[0]);			\
+		EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp,		\
+		    (_reg ## _OFST + ((_index) * _reg ## _STEP)),	\
+		    (_eop));						\
+	_NOTE(CONSTANTCONDITION)					\
+	} while (B_FALSE)
+
+#define	EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr)	\
+	do {								\
+		unsigned int _new = (_wptr);				\
+		unsigned int _old = (_owptr);				\
+									\
+		if ((_new) >= (_old))					\
+			EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),		\
+			    (_old) * sizeof (efx_desc_t),		\
+			    ((_new) - (_old)) * sizeof (efx_desc_t));	\
+		else							\
+			/*						\
+			 * It is cheaper to sync entire map than sync	\
+			 * two parts especially when offset/size are	\
+			 * ignored and entire map is synced in any case.\
+			 */						\
+			EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),		\
+			    0,						\
+			    (_entries) * sizeof (efx_desc_t));		\
 	_NOTE(CONSTANTCONDITION)					\
 	} while (B_FALSE)
 
 extern	__checkReturn	int
+efx_nic_biu_test(
+	__in		efx_nic_t *enp);
+
+extern	__checkReturn	int
 efx_mac_select(
 	__in		efx_nic_t *enp);
 
+extern	void
+efx_mac_multicast_hash_compute(
+	__in_ecount(6*count)		uint8_t const *addrs,
+	__in				int count,
+	__out				efx_oword_t *hash_low,
+	__out				efx_oword_t *hash_high);
+
 extern	__checkReturn	int
 efx_phy_probe(
 	__in		efx_nic_t *enp);
@@ -683,7 +1085,7 @@ efx_vpd_hunk_verify(
 
 extern	__checkReturn		int
 efx_vpd_hunk_reinit(
-	__in			caddr_t data,
+	__in_bcount(size)	caddr_t data,
 	__in			size_t size,
 	__in			boolean_t wantpid);
 
@@ -716,7 +1118,7 @@ efx_vpd_hunk_set(
 
 #if EFSYS_OPT_DIAG
 
-extern	efx_sram_pattern_fn_t	__cs __efx_sram_pattern_fns[];
+extern	efx_sram_pattern_fn_t	__efx_sram_pattern_fns[];
 
 typedef struct efx_register_set_s {
 	unsigned int		address;
@@ -740,6 +1142,23 @@ efx_nic_test_tables(
 
 #endif	/* EFSYS_OPT_DIAG */
 
+#if EFSYS_OPT_MCDI
+
+extern	__checkReturn		int
+efx_mcdi_set_workaround(
+	__in			efx_nic_t *enp,
+	__in			uint32_t type,
+	__in			boolean_t enabled,
+	__out_opt		uint32_t *flagsp);
+
+extern	__checkReturn		int
+efx_mcdi_get_workarounds(
+	__in			efx_nic_t *enp,
+	__out_opt		uint32_t *implementedp,
+	__out_opt		uint32_t *enabledp);
+
+#endif /* EFSYS_OPT_MCDI */
+
 #ifdef	__cplusplus
 }
 #endif
diff --git a/sys/dev/sfxge/common/efx_intr.c b/sys/dev/sfxge/common/efx_intr.c
index 556728df7ba9..d40f57f0b037 100644
--- a/sys/dev/sfxge/common/efx_intr.c
+++ b/sys/dev/sfxge/common/efx_intr.c
@@ -1,26 +1,31 @@
 /*-
- * Copyright 2007-2009 Solarflare Communications Inc.  All rights reserved.
+ * Copyright (c) 2007-2015 Solarflare Communications Inc.
+ * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
+ * modification, are permitted provided that the following conditions are met:
  *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are
+ * those of the authors and should not be interpreted as representing official
+ * policies, either expressed or implied, of the FreeBSD Project.
  */
 
 #include <sys/cdefs.h>
@@ -32,6 +37,82 @@ __FBSDID("$FreeBSD$");
 #include "efx_regs.h"
 #include "efx_impl.h"
 
+
+#if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA
+
+static	__checkReturn	int
+falconsiena_intr_init(
+	__in		efx_nic_t *enp,
+	__in		efx_intr_type_t type,
+	__in		efsys_mem_t *esmp);
+
+static			void
+falconsiena_intr_enable(
+	__in		efx_nic_t *enp);
+
+static			void
+falconsiena_intr_disable(
+	__in		efx_nic_t *enp);
+
+static			void
+falconsiena_intr_disable_unlocked(
+	__in		efx_nic_t *enp);
+
+static	__checkReturn	int
+falconsiena_intr_trigger(
+	__in		efx_nic_t *enp,
+	__in		unsigned int level);
+
+static			void
+falconsiena_intr_fini(
+	__in		efx_nic_t *enp);
+
+
+static	__checkReturn	boolean_t
+falconsiena_intr_check_fatal(
+	__in		efx_nic_t *enp);
+
+static			void
+falconsiena_intr_fatal(
+	__in		efx_nic_t *enp);
+
+#endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */
+
+
+#if EFSYS_OPT_FALCON
+static efx_intr_ops_t	__efx_intr_falcon_ops = {
+	falconsiena_intr_init,			/* eio_init */
+	falconsiena_intr_enable,		/* eio_enable */
+	falconsiena_intr_disable,		/* eio_disable */
+	falconsiena_intr_disable_unlocked,	/* eio_disable_unlocked */
+	falconsiena_intr_trigger,		/* eio_trigger */
+	falconsiena_intr_fini,			/* eio_fini */
+};
+#endif	/* EFSYS_OPT_FALCON */
+
+#if EFSYS_OPT_SIENA
+static efx_intr_ops_t	__efx_intr_siena_ops = {
+	falconsiena_intr_init,			/* eio_init */
+	falconsiena_intr_enable,		/* eio_enable */
+	falconsiena_intr_disable,		/* eio_disable */
+	falconsiena_intr_disable_unlocked,	/* eio_disable_unlocked */
+	falconsiena_intr_trigger,		/* eio_trigger */
+	falconsiena_intr_fini,			/* eio_fini */
+};
+#endif	/* EFSYS_OPT_SIENA */
+
+#if EFSYS_OPT_HUNTINGTON
+static efx_intr_ops_t	__efx_intr_hunt_ops = {
+	hunt_intr_init,			/* eio_init */
+	hunt_intr_enable,		/* eio_enable */
+	hunt_intr_disable,		/* eio_disable */
+	hunt_intr_disable_unlocked,	/* eio_disable_unlocked */
+	hunt_intr_trigger,		/* eio_trigger */
+	hunt_intr_fini,			/* eio_fini */
+};
+#endif	/* EFSYS_OPT_HUNTINGTON */
+
+
 	__checkReturn	int
 efx_intr_init(
 	__in		efx_nic_t *enp,
@@ -39,7 +120,7 @@ efx_intr_init(
 	__in		efsys_mem_t *esmp)
 {
 	efx_intr_t *eip = &(enp->en_intr);
-	efx_oword_t oword;
+	efx_intr_ops_t *eiop;
 	int rc;
 
 	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
@@ -50,10 +131,219 @@ efx_intr_init(
 		goto fail1;
 	}
 
+	eip->ei_esmp = esmp;
+	eip->ei_type = type;
+	eip->ei_level = 0;
+
 	enp->en_mod_flags |= EFX_MOD_INTR;
 
-	eip->ei_type = type;
-	eip->ei_esmp = esmp;
+	switch (enp->en_family) {
+#if EFSYS_OPT_FALCON
+	case EFX_FAMILY_FALCON:
+		eiop = (efx_intr_ops_t *)&__efx_intr_falcon_ops;
+		break;
+#endif	/* EFSYS_OPT_FALCON */
+
+#if EFSYS_OPT_SIENA
+	case EFX_FAMILY_SIENA:
+		eiop = (efx_intr_ops_t *)&__efx_intr_siena_ops;
+		break;
+#endif	/* EFSYS_OPT_SIENA */
+
+#if EFSYS_OPT_HUNTINGTON
+	case EFX_FAMILY_HUNTINGTON:
+		eiop = (efx_intr_ops_t *)&__efx_intr_hunt_ops;
+		break;
+#endif	/* EFSYS_OPT_HUNTINGTON */
+
+	default:
+		EFSYS_ASSERT(B_FALSE);
+		rc = ENOTSUP;
+		goto fail2;
+	}
+
+	if ((rc = eiop->eio_init(enp, type, esmp)) != 0)
+		goto fail3;
+
+	eip->ei_eiop = eiop;
+
+	return (0);
+
+fail3:
+	EFSYS_PROBE(fail3);
+fail2:
+	EFSYS_PROBE(fail2);
+fail1:
+	EFSYS_PROBE1(fail1, int, rc);
+
+	return (rc);
+}
+
+		void
+efx_intr_fini(
+	__in	efx_nic_t *enp)
+{
+	efx_intr_t *eip = &(enp->en_intr);
+	efx_intr_ops_t *eiop = eip->ei_eiop;
+
+	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
+	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
+	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
+
+	eiop->eio_fini(enp);
+
+	enp->en_mod_flags &= ~EFX_MOD_INTR;
+}
+
+			void
+efx_intr_enable(
+	__in		efx_nic_t *enp)
+{
+	efx_intr_t *eip = &(enp->en_intr);
+	efx_intr_ops_t *eiop = eip->ei_eiop;
+
+	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
+	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
+
+	eiop->eio_enable(enp);
+}
+
+			void
+efx_intr_disable(
+	__in		efx_nic_t *enp)
+{
+	efx_intr_t *eip = &(enp->en_intr);
+	efx_intr_ops_t *eiop = eip->ei_eiop;
+
+	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
+	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
+
+	eiop->eio_disable(enp);
+}
+
+			void
+efx_intr_disable_unlocked(
+	__in		efx_nic_t *enp)
+{
+	efx_intr_t *eip = &(enp->en_intr);
+	efx_intr_ops_t *eiop = eip->ei_eiop;
+
+	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
+	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
+
+	eiop->eio_disable_unlocked(enp);
+}
+
+
+	__checkReturn	int
+efx_intr_trigger(
+	__in		efx_nic_t *enp,
+	__in		unsigned int level)
+{
+	efx_intr_t *eip = &(enp->en_intr);
+	efx_intr_ops_t *eiop = eip->ei_eiop;
+
+	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
+	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
+
+	return (eiop->eio_trigger(enp, level));
+}
+
+			void
+efx_intr_status_line(
+	__in		efx_nic_t *enp,
+	__out		boolean_t *fatalp,
+	__out		uint32_t *qmaskp)
+{
+	efx_intr_t *eip = &(enp->en_intr);
+	efx_dword_t dword;
+
+	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
+	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
+
+	/* Ensure Huntington and Falcon/Siena ISR at same location */
+	EFX_STATIC_ASSERT(FR_BZ_INT_ISR0_REG_OFST ==
+	    ER_DZ_BIU_INT_ISR_REG_OFST);
+
+	/*
+	 * Read the queue mask and implicitly acknowledge the
+	 * interrupt.
+	 */
+	EFX_BAR_READD(enp, FR_BZ_INT_ISR0_REG, &dword, B_FALSE);
+	*qmaskp = EFX_DWORD_FIELD(dword, EFX_DWORD_0);
+
+	EFSYS_PROBE1(qmask, uint32_t, *qmaskp);
+
+#if EFSYS_OPT_HUNTINGTON
+	if (enp->en_family == EFX_FAMILY_HUNTINGTON) {
+		/* Huntington reports fatal errors via events */
+		*fatalp = B_FALSE;
+		return;
+	}
+#endif
+	if (*qmaskp & (1U << eip->ei_level))
+		*fatalp = falconsiena_intr_check_fatal(enp);
+	else
+		*fatalp = B_FALSE;
+}
+
+			void
+efx_intr_status_message(
+	__in		efx_nic_t *enp,
+	__in		unsigned int message,
+	__out		boolean_t *fatalp)
+{
+	efx_intr_t *eip = &(enp->en_intr);
+
+	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
+	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
+
+#if EFSYS_OPT_HUNTINGTON
+	if (enp->en_family == EFX_FAMILY_HUNTINGTON) {
+		/* Huntington reports fatal errors via events */
+		*fatalp = B_FALSE;
+		return;
+	}
+#endif
+	if (message == eip->ei_level)
+		*fatalp = falconsiena_intr_check_fatal(enp);
+	else
+		*fatalp = B_FALSE;
+}
+
+		void
+efx_intr_fatal(
+	__in	efx_nic_t *enp)
+{
+	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
+	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
+
+#if EFSYS_OPT_HUNTINGTON
+	if (enp->en_family == EFX_FAMILY_HUNTINGTON) {
+		/* Huntington reports fatal errors via events */
+		return;
+	}
+#endif
+#if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA
+	falconsiena_intr_fatal(enp);
+#endif
+}
+
+
+/* ************************************************************************* */
+/* ************************************************************************* */
+/* ************************************************************************* */
+
+#if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA
+
+static	__checkReturn	int
+falconsiena_intr_init(
+	__in		efx_nic_t *enp,
+	__in		efx_intr_type_t type,
+	__in		efsys_mem_t *esmp)
+{
+	efx_intr_t *eip = &(enp->en_intr);
+	efx_oword_t oword;
 
 	/*
 	 * bug17213 workaround.
@@ -85,23 +375,15 @@ efx_intr_init(
 	EFX_BAR_WRITEO(enp, FR_AZ_INT_ADR_REG_KER, &oword);
 
 	return (0);
-
-fail1:
-	EFSYS_PROBE1(fail1, int, rc);
-
-	return (rc);
 }
 
-			void
-efx_intr_enable(
+static			void
+falconsiena_intr_enable(
 	__in		efx_nic_t *enp)
 {
 	efx_intr_t *eip = &(enp->en_intr);
 	efx_oword_t oword;
 
-	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
-	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
-
 	EFX_BAR_READO(enp, FR_AZ_INT_EN_REG_KER, &oword);
 
 	EFX_SET_OWORD_FIELD(oword, FRF_AZ_KER_INT_LEVE_SEL, eip->ei_level);
@@ -109,15 +391,12 @@ efx_intr_enable(
 	EFX_BAR_WRITEO(enp, FR_AZ_INT_EN_REG_KER, &oword);
 }
 
-			void
-efx_intr_disable(
+static			void
+falconsiena_intr_disable(
 	__in		efx_nic_t *enp)
 {
 	efx_oword_t oword;
 
-	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
-	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
-
 	EFX_BAR_READO(enp, FR_AZ_INT_EN_REG_KER, &oword);
 	EFX_SET_OWORD_FIELD(oword, FRF_AZ_DRV_INT_EN_KER, 0);
 	EFX_BAR_WRITEO(enp, FR_AZ_INT_EN_REG_KER, &oword);
@@ -125,15 +404,12 @@ efx_intr_disable(
 	EFSYS_SPIN(10);
 }
 
-			void
-efx_intr_disable_unlocked(
+static			void
+falconsiena_intr_disable_unlocked(
 	__in		efx_nic_t *enp)
 {
 	efx_oword_t oword;
 
-	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
-	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
-
 	EFSYS_BAR_READO(enp->en_esbp, FR_AZ_INT_EN_REG_KER_OFST,
 			&oword, B_FALSE);
 	EFX_SET_OWORD_FIELD(oword, FRF_AZ_DRV_INT_EN_KER, 0);
@@ -141,8 +417,8 @@ efx_intr_disable_unlocked(
 	    &oword, B_FALSE);
 }
 
-	__checkReturn	int
-efx_intr_trigger(
+static	__checkReturn	int
+falconsiena_intr_trigger(
 	__in		efx_nic_t *enp,
 	__in		unsigned int level)
 {
@@ -152,22 +428,19 @@ efx_intr_trigger(
 	uint32_t sel;
 	int rc;
 
-	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
-	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
-
 	/* bug16757: No event queues can be initialized */
 	EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
 
 	switch (enp->en_family) {
 	case EFX_FAMILY_FALCON:
-		if (level > EFX_NINTR_FALCON) {
+		if (level >= EFX_NINTR_FALCON) {
 			rc = EINVAL;
 			goto fail1;
 		}
 		break;
 
 	case EFX_FAMILY_SIENA:
-		if (level > EFX_NINTR_SIENA) {
+		if (level >= EFX_NINTR_SIENA) {
 			rc = EINVAL;
 			goto fail1;
 		}
@@ -213,7 +486,7 @@ fail1:
 }
 
 static	__checkReturn	boolean_t
-efx_intr_check_fatal(
+falconsiena_intr_check_fatal(
 	__in		efx_nic_t *enp)
 {
 	efx_intr_t *eip = &(enp->en_intr);
@@ -236,61 +509,14 @@ efx_intr_check_fatal(
 	return (B_FALSE);
 }
 
-			void
-efx_intr_status_line(
-	__in		efx_nic_t *enp,
-	__out		boolean_t *fatalp,
-	__out		uint32_t *qmaskp)
-{
-	efx_intr_t *eip = &(enp->en_intr);
-	efx_dword_t dword;
-
-	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
-	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
-
-	/*
-	 * Read the queue mask and implicitly acknowledge the
-	 * interrupt.
-	 */
-	EFX_BAR_READD(enp, FR_BZ_INT_ISR0_REG, &dword, B_FALSE);
-	*qmaskp = EFX_DWORD_FIELD(dword, EFX_DWORD_0);
-
-	EFSYS_PROBE1(qmask, uint32_t, *qmaskp);
-
-	if (*qmaskp & (1U << eip->ei_level))
-		*fatalp = efx_intr_check_fatal(enp);
-	else
-		*fatalp = B_FALSE;
-}
-
-			void
-efx_intr_status_message(
-	__in		efx_nic_t *enp,
-	__in		unsigned int message,
-	__out		boolean_t *fatalp)
-{
-	efx_intr_t *eip = &(enp->en_intr);
-
-	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
-	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
-
-	if (message == eip->ei_level)
-		*fatalp = efx_intr_check_fatal(enp);
-	else
-		*fatalp = B_FALSE;
-}
-
-		void
-efx_intr_fatal(
+static		void
+falconsiena_intr_fatal(
 	__in	efx_nic_t *enp)
 {
 #if EFSYS_OPT_DECODE_INTR_FATAL
 	efx_oword_t fatal;
 	efx_oword_t mem_per;
 
-	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
-	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
-
 	EFX_BAR_READO(enp, FR_AZ_FATAL_INTR_REG_KER, &fatal);
 	EFX_ZERO_OWORD(mem_per);
 
@@ -339,19 +565,15 @@ efx_intr_fatal(
 #endif
 }
 
-		void
-efx_intr_fini(
+static		void
+falconsiena_intr_fini(
 	__in	efx_nic_t *enp)
 {
 	efx_oword_t oword;
 
-	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
-	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
-	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
-
 	/* Clear the interrupt address register */
 	EFX_ZERO_OWORD(oword);
 	EFX_BAR_WRITEO(enp, FR_AZ_INT_ADR_REG_KER, &oword);
-
-	enp->en_mod_flags &= ~EFX_MOD_INTR;
 }
+
+#endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */
diff --git a/sys/dev/sfxge/common/efx_mac.c b/sys/dev/sfxge/common/efx_mac.c
index 3e9449ad70fb..a701797c80bb 100644
--- a/sys/dev/sfxge/common/efx_mac.c
+++ b/sys/dev/sfxge/common/efx_mac.c
@@ -1,26 +1,31 @@
 /*-
- * Copyright 2007-2009 Solarflare Communications Inc.  All rights reserved.
+ * Copyright (c) 2007-2015 Solarflare Communications Inc.
+ * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
+ * modification, are permitted provided that the following conditions are met:
  *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are
+ * those of the authors and should not be interpreted as representing official
+ * policies, either expressed or implied, of the FreeBSD Project.
  */
 
 #include <sys/cdefs.h>
@@ -39,74 +44,126 @@ __FBSDID("$FreeBSD$");
 #include "falcon_xmac.h"
 #endif
 
+#if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA
+
+static	__checkReturn	int
+falconsiena_mac_multicast_list_set(
+	__in				efx_nic_t *enp);
+
+#endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */
+
 #if EFSYS_OPT_MAC_FALCON_GMAC
-static efx_mac_ops_t	__cs __efx_falcon_gmac_ops = {
-	falcon_gmac_reset,		/* emo_reset */
-	falcon_mac_poll,		/* emo_poll */
-	falcon_mac_up,			/* emo_up */
-	falcon_gmac_reconfigure,	/* emo_reconfigure */
+static efx_mac_ops_t	__efx_falcon_gmac_ops = {
+	falcon_gmac_reset,			/* emo_reset */
+	falcon_mac_poll,			/* emo_poll */
+	falcon_mac_up,				/* emo_up */
+	falcon_gmac_reconfigure,		/* emo_addr_set */
+	falcon_gmac_reconfigure,		/* emo_reconfigure */
+	falconsiena_mac_multicast_list_set,	/* emo_multicast_list_set */
+	NULL,					/* emo_filter_set_default_rxq */
+	NULL,				/* emo_filter_default_rxq_clear */
 #if EFSYS_OPT_LOOPBACK
-	falcon_mac_loopback_set,	/* emo_loopback_set */
+	falcon_mac_loopback_set,		/* emo_loopback_set */
 #endif	/* EFSYS_OPT_LOOPBACK */
 #if EFSYS_OPT_MAC_STATS
-	falcon_mac_stats_upload,	/* emo_stats_upload */
-	NULL,				/* emo_stats_periodic */
-	falcon_gmac_stats_update	/* emo_stats_update */
+	falcon_mac_stats_upload,		/* emo_stats_upload */
+	NULL,					/* emo_stats_periodic */
+	falcon_gmac_stats_update		/* emo_stats_update */
 #endif	/* EFSYS_OPT_MAC_STATS */
 };
 #endif	/* EFSYS_OPT_MAC_FALCON_GMAC */
 
 #if EFSYS_OPT_MAC_FALCON_XMAC
-static efx_mac_ops_t	__cs __efx_falcon_xmac_ops = {
-	falcon_xmac_reset,		/* emo_reset */
-	falcon_mac_poll,		/* emo_poll */
-	falcon_mac_up,			/* emo_up */
-	falcon_xmac_reconfigure,	/* emo_reconfigure */
+static efx_mac_ops_t	__efx_falcon_xmac_ops = {
+	falcon_xmac_reset,			/* emo_reset */
+	falcon_mac_poll,			/* emo_poll */
+	falcon_mac_up,				/* emo_up */
+	falcon_xmac_reconfigure,		/* emo_addr_set */
+	falcon_xmac_reconfigure,		/* emo_reconfigure */
+	falconsiena_mac_multicast_list_set,	/* emo_multicast_list_set */
+	NULL,					/* emo_filter_set_default_rxq */
+	NULL,				/* emo_filter_default_rxq_clear */
 #if EFSYS_OPT_LOOPBACK
-	falcon_mac_loopback_set,	/* emo_loopback_set */
+	falcon_mac_loopback_set,		/* emo_loopback_set */
 #endif	/* EFSYS_OPT_LOOPBACK */
 #if EFSYS_OPT_MAC_STATS
-	falcon_mac_stats_upload,	/* emo_stats_upload */
-	NULL,				/* emo_stats_periodic */
-	falcon_xmac_stats_update	/* emo_stats_update */
+	falcon_mac_stats_upload,		/* emo_stats_upload */
+	NULL,					/* emo_stats_periodic */
+	falcon_xmac_stats_update		/* emo_stats_update */
 #endif	/* EFSYS_OPT_MAC_STATS */
 };
 #endif	/* EFSYS_OPT_MAC_FALCON_XMAC */
 
 #if EFSYS_OPT_SIENA
-static efx_mac_ops_t	__cs __efx_siena_mac_ops = {
-	NULL,				/* emo_reset */
-	siena_mac_poll,			/* emo_poll */
-	siena_mac_up,			/* emo_up */
-	siena_mac_reconfigure,		/* emo_reconfigure */
+static efx_mac_ops_t	__efx_siena_mac_ops = {
+	NULL,					/* emo_reset */
+	siena_mac_poll,				/* emo_poll */
+	siena_mac_up,				/* emo_up */
+	siena_mac_reconfigure,			/* emo_addr_set */
+	siena_mac_reconfigure,			/* emo_reconfigure */
+	falconsiena_mac_multicast_list_set,	/* emo_multicast_list_set */
+	NULL,					/* emo_filter_set_default_rxq */
+	NULL,				/* emo_filter_default_rxq_clear */
 #if EFSYS_OPT_LOOPBACK
-	siena_mac_loopback_set,		/* emo_loopback_set */
+	siena_mac_loopback_set,			/* emo_loopback_set */
 #endif	/* EFSYS_OPT_LOOPBACK */
 #if EFSYS_OPT_MAC_STATS
-	siena_mac_stats_upload,		/* emo_stats_upload */
-	siena_mac_stats_periodic,	/* emo_stats_periodic */
-	siena_mac_stats_update		/* emo_stats_update */
+	efx_mcdi_mac_stats_upload,		/* emo_stats_upload */
+	efx_mcdi_mac_stats_periodic,		/* emo_stats_periodic */
+	siena_mac_stats_update			/* emo_stats_update */
 #endif	/* EFSYS_OPT_MAC_STATS */
 };
 #endif	/* EFSYS_OPT_SIENA */
 
-static efx_mac_ops_t	__cs * __cs __efx_mac_ops[] = {
+#if EFSYS_OPT_HUNTINGTON
+static efx_mac_ops_t	__efx_hunt_mac_ops = {
+	NULL,					/* emo_reset */
+	hunt_mac_poll,				/* emo_poll */
+	hunt_mac_up,				/* emo_up */
+	hunt_mac_addr_set,			/* emo_addr_set */
+	hunt_mac_reconfigure,			/* emo_reconfigure */
+	hunt_mac_multicast_list_set,		/* emo_multicast_list_set */
+	hunt_mac_filter_default_rxq_set,	/* emo_filter_default_rxq_set */
+	hunt_mac_filter_default_rxq_clear,
+					/* emo_filter_default_rxq_clear */
+#if EFSYS_OPT_LOOPBACK
+	hunt_mac_loopback_set,			/* emo_loopback_set */
+#endif	/* EFSYS_OPT_LOOPBACK */
+#if EFSYS_OPT_MAC_STATS
+	efx_mcdi_mac_stats_upload,		/* emo_stats_upload */
+	efx_mcdi_mac_stats_periodic,		/* emo_stats_periodic */
+	hunt_mac_stats_update			/* emo_stats_update */
+#endif	/* EFSYS_OPT_MAC_STATS */
+};
+#endif	/* EFSYS_OPT_HUNTINGTON */
+
+static efx_mac_ops_t	*__efx_mac_ops[] = {
+	/* [EFX_MAC_INVALID] */
 	NULL,
+	/* [EFX_MAC_FALCON_GMAC] */
 #if EFSYS_OPT_MAC_FALCON_GMAC
 	&__efx_falcon_gmac_ops,
 #else
 	NULL,
-#endif	/* EFSYS_OPT_MAC_FALCON_GMAC */
+#endif
+	/* [EFX_MAC_FALCON_XMAC] */
 #if EFSYS_OPT_MAC_FALCON_XMAC
 	&__efx_falcon_xmac_ops,
 #else
 	NULL,
-#endif	/* EFSYS_OPT_MAC_FALCON_XMAC */
+#endif
+	/* [EFX_MAC_SIENA] */
 #if EFSYS_OPT_SIENA
 	&__efx_siena_mac_ops,
 #else
 	NULL,
-#endif	/* EFSYS_OPT_SIENA */
+#endif
+	/* [EFX_MAC_HUNTINGTON] */
+#if EFSYS_OPT_HUNTINGTON
+	&__efx_hunt_mac_ops,
+#else
+	NULL,
+#endif
 };
 
 	__checkReturn			int
@@ -167,7 +224,7 @@ efx_mac_addr_set(
 	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
 
-	if (addr[0] & 0x01) {
+	if (EFX_MAC_ADDR_IS_MULTICAST(addr)) {
 		rc = EINVAL;
 		goto fail1;
 	}
@@ -180,7 +237,7 @@ efx_mac_addr_set(
 
 	EFX_MAC_ADDR_COPY(old_addr, epp->ep_mac_addr);
 	EFX_MAC_ADDR_COPY(epp->ep_mac_addr, addr);
-	if ((rc = emop->emo_reconfigure(enp)) != 0)
+	if ((rc = emop->emo_addr_set(enp)) != 0)
 		goto fail3;
 
 	return (0);
@@ -201,22 +258,30 @@ fail1:
 	__checkReturn			int
 efx_mac_filter_set(
 	__in				efx_nic_t *enp,
-	__in				boolean_t unicst,
+	__in				boolean_t all_unicst,
+	__in				boolean_t mulcst,
+	__in				boolean_t all_mulcst,
 	__in				boolean_t brdcst)
 {
 	efx_port_t *epp = &(enp->en_port);
 	efx_mac_ops_t *emop = epp->ep_emop;
-	boolean_t old_unicst;
+	boolean_t old_all_unicst;
+	boolean_t old_mulcst;
+	boolean_t old_all_mulcst;
 	boolean_t old_brdcst;
 	int rc;
 
 	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
 
-	old_unicst = unicst;
-	old_brdcst = brdcst;
+	old_all_unicst = epp->ep_all_unicst;
+	old_mulcst = epp->ep_mulcst;
+	old_all_mulcst = epp->ep_all_mulcst;
+	old_brdcst = epp->ep_brdcst;
 
-	epp->ep_unicst = unicst;
+	epp->ep_all_unicst = all_unicst;
+	epp->ep_mulcst = mulcst;
+	epp->ep_all_mulcst = all_mulcst;
 	epp->ep_brdcst = brdcst;
 
 	if ((rc = emop->emo_reconfigure(enp)) != 0)
@@ -227,7 +292,9 @@ efx_mac_filter_set(
 fail1:
 	EFSYS_PROBE1(fail1, int, rc);
 
-	epp->ep_unicst = old_unicst;
+	epp->ep_all_unicst = old_all_unicst;
+	epp->ep_mulcst = old_mulcst;
+	epp->ep_all_mulcst = old_all_mulcst;
 	epp->ep_brdcst = old_brdcst;
 
 	return (rc);
@@ -318,45 +385,45 @@ efx_mac_fcntl_set(
 	}
 
 	/*
-	 * Ignore a request to set flow control autonegotiation
+	 * Ignore a request to set flow control auto-negotiation
 	 * if the PHY doesn't support it.
 	 */
 	if (~epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_AN))
 		autoneg = B_FALSE;
 
 	old_fcntl = epp->ep_fcntl;
-	old_autoneg = autoneg;
+	old_autoneg = epp->ep_fcntl_autoneg;
 	old_adv_cap = epp->ep_adv_cap_mask;
 
 	epp->ep_fcntl = fcntl;
 	epp->ep_fcntl_autoneg = autoneg;
 
 	/*
-	 * If the PHY supports autonegotiation, then encode the flow control
-	 * settings in the advertised capabilities, and restart AN. Otherwise,
-	 * just push the new settings directly to the MAC.
+	 * Always encode the flow control settings in the advertised
+	 * capabilities even if we are not trying to auto-negotiate
+	 * them and reconfigure both the PHY and the MAC.
 	 */
-	if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_AN)) {
-		if (fcntl & EFX_FCNTL_RESPOND)
-			epp->ep_adv_cap_mask |=    (1 << EFX_PHY_CAP_PAUSE |
-						    1 << EFX_PHY_CAP_ASYM);
-		else
-			epp->ep_adv_cap_mask &=   ~(1 << EFX_PHY_CAP_PAUSE |
-						    1 << EFX_PHY_CAP_ASYM);
+	if (fcntl & EFX_FCNTL_RESPOND)
+		epp->ep_adv_cap_mask |=    (1 << EFX_PHY_CAP_PAUSE |
+					    1 << EFX_PHY_CAP_ASYM);
+	else
+		epp->ep_adv_cap_mask &=   ~(1 << EFX_PHY_CAP_PAUSE |
+					    1 << EFX_PHY_CAP_ASYM);
 
-		if (fcntl & EFX_FCNTL_GENERATE)
-			epp->ep_adv_cap_mask ^= (1 << EFX_PHY_CAP_ASYM);
+	if (fcntl & EFX_FCNTL_GENERATE)
+		epp->ep_adv_cap_mask ^= (1 << EFX_PHY_CAP_ASYM);
 
-		if ((rc = epop->epo_reconfigure(enp)) != 0)
-			goto fail2;
+	if ((rc = epop->epo_reconfigure(enp)) != 0)
+		goto fail2;
 
-	} else {
-		if ((rc = emop->emo_reconfigure(enp)) != 0)
-			goto fail2;
-	}
+	if ((rc = emop->emo_reconfigure(enp)) != 0)
+		goto fail3;
 
 	return (0);
 
+fail3:
+	EFSYS_PROBE(fail3);
+
 fail2:
 	EFSYS_PROBE(fail2);
 
@@ -377,29 +444,30 @@ efx_mac_fcntl_get(
 	__out		unsigned int *fcntl_linkp)
 {
 	efx_port_t *epp = &(enp->en_port);
-	unsigned int wanted;
+	unsigned int wanted = 0;
 
 	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
 
 	/*
-	 * If the PHY supports auto negotiation, then the requested flow
-	 * control settings are encoded in the advertised capabilities.
+	 * Decode the requested flow control settings from the PHY
+	 * advertised capabilities.
 	 */
-	if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_AN)) {
-		wanted = 0;
-
-		if (epp->ep_adv_cap_mask & (1 << EFX_PHY_CAP_PAUSE))
-			wanted = EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE;
-		if (epp->ep_adv_cap_mask & (1 << EFX_PHY_CAP_ASYM))
-			wanted ^= EFX_FCNTL_GENERATE;
-	} else
-		wanted = epp->ep_fcntl;
+	if (epp->ep_adv_cap_mask & (1 << EFX_PHY_CAP_PAUSE))
+		wanted = EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE;
+	if (epp->ep_adv_cap_mask & (1 << EFX_PHY_CAP_ASYM))
+		wanted ^= EFX_FCNTL_GENERATE;
 
 	*fcntl_linkp = epp->ep_fcntl;
 	*fcntl_wantedp = wanted;
 }
 
+/*
+ * FIXME: efx_mac_hash_set() should be deleted once all its callers have been
+ * updated to use efx_mac_multicast_list_set().
+ * Then efx_port_t.ep_multicst_hash could be made Falcon/Siena specific as
+ * well.
+ */
 	__checkReturn			int
 efx_mac_hash_set(
 	__in				efx_nic_t *enp,
@@ -443,12 +511,130 @@ fail1:
 	return (rc);
 }
 
+	__checkReturn	int
+efx_mac_multicast_list_set(
+	__in				efx_nic_t *enp,
+	__in_ecount(6*count)		uint8_t const *addrs,
+	__in				int count)
+{
+	efx_port_t *epp = &(enp->en_port);
+	efx_mac_ops_t *emop = epp->ep_emop;
+	uint8_t	*old_mulcst_addr_list = NULL;
+	uint32_t old_mulcst_addr_count;
+	int rc;
+
+	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
+	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
+
+	if (count > EFX_MAC_MULTICAST_LIST_MAX) {
+		rc = EINVAL;
+		goto fail1;
+	}
+
+	old_mulcst_addr_count = epp->ep_mulcst_addr_count;
+	if (old_mulcst_addr_count > 0) {
+		/* Allocate memory to store old list (instead of using stack) */
+		EFSYS_KMEM_ALLOC(enp->en_esip,
+				old_mulcst_addr_count * EFX_MAC_ADDR_LEN,
+				old_mulcst_addr_list);
+		if (old_mulcst_addr_list == NULL) {
+			rc = ENOMEM;
+			goto fail2;
+		}
+
+		/* Save the old list in case we need to rollback */
+		memcpy(old_mulcst_addr_list, epp->ep_mulcst_addr_list,
+			old_mulcst_addr_count * EFX_MAC_ADDR_LEN);
+	}
+
+	/* Store the new list */
+	memcpy(epp->ep_mulcst_addr_list, addrs,
+		count * EFX_MAC_ADDR_LEN);
+	epp->ep_mulcst_addr_count = count;
+
+	if ((rc = emop->emo_multicast_list_set(enp)) != 0)
+		goto fail3;
+
+	if (old_mulcst_addr_count > 0) {
+		EFSYS_KMEM_FREE(enp->en_esip,
+				old_mulcst_addr_count * EFX_MAC_ADDR_LEN,
+				old_mulcst_addr_list);
+	}
+
+	return (0);
+
+fail3:
+	EFSYS_PROBE(fail3);
+
+	/* Restore original list on failure */
+	epp->ep_mulcst_addr_count = old_mulcst_addr_count;
+	if (old_mulcst_addr_count > 0) {
+		memcpy(epp->ep_mulcst_addr_list, old_mulcst_addr_list,
+			old_mulcst_addr_count * EFX_MAC_ADDR_LEN);
+
+		EFSYS_KMEM_FREE(enp->en_esip,
+				old_mulcst_addr_count * EFX_MAC_ADDR_LEN,
+				old_mulcst_addr_list);
+	}
+
+fail2:
+	EFSYS_PROBE(fail2);
+
+fail1:
+	EFSYS_PROBE1(fail1, int, rc);
+
+	return (rc);
+
+}
+
+	__checkReturn	int
+efx_mac_filter_default_rxq_set(
+	__in		efx_nic_t *enp,
+	__in		efx_rxq_t *erp,
+	__in		boolean_t using_rss)
+{
+	efx_port_t *epp = &(enp->en_port);
+	efx_mac_ops_t *emop = epp->ep_emop;
+	int rc;
+
+	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
+	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
+
+	if (emop->emo_filter_default_rxq_set != NULL) {
+		rc = emop->emo_filter_default_rxq_set(enp, erp, using_rss);
+		if (rc != 0)
+			goto fail1;
+	}
+
+	return (0);
+
+fail1:
+	EFSYS_PROBE1(fail1, int, rc);
+
+	return (rc);
+}
+
+			void
+efx_mac_filter_default_rxq_clear(
+	__in		efx_nic_t *enp)
+{
+	efx_port_t *epp = &(enp->en_port);
+	efx_mac_ops_t *emop = epp->ep_emop;
+
+	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
+	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
+
+	if (emop->emo_filter_default_rxq_clear != NULL)
+		emop->emo_filter_default_rxq_clear(enp);
+}
+
+
 #if EFSYS_OPT_MAC_STATS
 
 #if EFSYS_OPT_NAMES
 
-/* START MKCONFIG GENERATED EfxMacStatNamesBlock adf707adba80813e */
-static const char 	__cs * __cs __efx_mac_stat_name[] = {
+/* START MKCONFIG GENERATED EfxMacStatNamesBlock 054d43a31d2d7a45 */
+static const char 	*__efx_mac_stat_name[] = {
 	"rx_octets",
 	"rx_pkts",
 	"rx_unicst_pkts",
@@ -500,10 +686,40 @@ static const char 	__cs * __cs __efx_mac_stat_name[] = {
 	"tx_late_col_pkts",
 	"tx_def_pkts",
 	"tx_ex_def_pkts",
+	"pm_trunc_bb_overflow",
+	"pm_discard_bb_overflow",
+	"pm_trunc_vfifo_full",
+	"pm_discard_vfifo_full",
+	"pm_trunc_qbb",
+	"pm_discard_qbb",
+	"pm_discard_mapping",
+	"rxdp_q_disabled_pkts",
+	"rxdp_di_dropped_pkts",
+	"rxdp_streaming_pkts",
+	"rxdp_hlb_fetch",
+	"rxdp_hlb_wait",
+	"vadapter_rx_unicast_packets",
+	"vadapter_rx_unicast_bytes",
+	"vadapter_rx_multicast_packets",
+	"vadapter_rx_multicast_bytes",
+	"vadapter_rx_broadcast_packets",
+	"vadapter_rx_broadcast_bytes",
+	"vadapter_rx_bad_packets",
+	"vadapter_rx_bad_bytes",
+	"vadapter_rx_overflow",
+	"vadapter_tx_unicast_packets",
+	"vadapter_tx_unicast_bytes",
+	"vadapter_tx_multicast_packets",
+	"vadapter_tx_multicast_bytes",
+	"vadapter_tx_broadcast_packets",
+	"vadapter_tx_broadcast_bytes",
+	"vadapter_tx_bad_packets",
+	"vadapter_tx_bad_bytes",
+	"vadapter_tx_overflow",
 };
 /* END MKCONFIG GENERATED EfxMacStatNamesBlock */
 
-	__checkReturn			const char __cs *
+	__checkReturn			const char *
 efx_mac_stat_name(
 	__in				efx_nic_t *enp,
 	__in				unsigned int id)
@@ -515,7 +731,7 @@ efx_mac_stat_name(
 	return (__efx_mac_stat_name[id]);
 }
 
-#endif	/* EFSYS_OPT_STAT_NAME */
+#endif	/* EFSYS_OPT_NAMES */
 
 	__checkReturn			int
 efx_mac_stats_upload(
@@ -588,7 +804,7 @@ efx_mac_stats_update(
 	__in				efx_nic_t *enp,
 	__in				efsys_mem_t *esmp,
 	__inout_ecount(EFX_MAC_NSTATS)	efsys_stat_t *essp,
-	__in				uint32_t *generationp)
+	__out_opt			uint32_t *generationp)
 {
 	efx_port_t *epp = &(enp->en_port);
 	efx_mac_ops_t *emop = epp->ep_emop;
@@ -616,6 +832,13 @@ efx_mac_select(
 	efx_mac_ops_t *emop;
 	int rc = EINVAL;
 
+#if EFSYS_OPT_HUNTINGTON
+	if (enp->en_family == EFX_FAMILY_HUNTINGTON) {
+		type = EFX_MAC_HUNTINGTON;
+		goto chosen;
+	}
+#endif
+
 #if EFSYS_OPT_SIENA
 	if (enp->en_family == EFX_FAMILY_SIENA) {
 		type = EFX_MAC_SIENA;
@@ -685,3 +908,71 @@ fail1:
 
 	return (rc);
 }
+
+
+#if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA
+
+/* Compute the multicast hash as used on Falcon and Siena. */
+static	void
+falconsiena_mac_multicast_hash_compute(
+	__in_ecount(6*count)		uint8_t const *addrs,
+	__in				int count,
+	__out				efx_oword_t *hash_low,
+	__out				efx_oword_t *hash_high)
+{
+	uint32_t crc, index;
+	int i;
+
+	EFSYS_ASSERT(hash_low != NULL);
+	EFSYS_ASSERT(hash_high != NULL);
+
+	EFX_ZERO_OWORD(*hash_low);
+	EFX_ZERO_OWORD(*hash_high);
+
+	for (i = 0; i < count; i++) {
+		/* Calculate hash bucket (IEEE 802.3 CRC32 of the MAC addr) */
+		crc = efx_crc32_calculate(0xffffffff, addrs, EFX_MAC_ADDR_LEN);
+		index = crc % EFX_MAC_HASH_BITS;
+		if (index < 128) {
+			EFX_SET_OWORD_BIT(*hash_low, index);
+		} else {
+			EFX_SET_OWORD_BIT(*hash_high, index - 128);
+		}
+
+		addrs += EFX_MAC_ADDR_LEN;
+	}
+}
+
+static	__checkReturn	int
+falconsiena_mac_multicast_list_set(
+	__in			efx_nic_t *enp)
+{
+	efx_port_t *epp = &(enp->en_port);
+	efx_mac_ops_t *emop = epp->ep_emop;
+	efx_oword_t old_hash[2];
+	int rc;
+
+	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
+	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
+
+	memcpy(old_hash, epp->ep_multicst_hash, sizeof (old_hash));
+
+	falconsiena_mac_multicast_hash_compute(epp->ep_mulcst_addr_list,
+				epp->ep_mulcst_addr_count,
+				&epp->ep_multicst_hash[0],
+				&epp->ep_multicst_hash[1]);
+
+	if ((rc = emop->emo_reconfigure(enp)) != 0)
+		goto fail1;
+
+	return (0);
+
+fail1:
+	EFSYS_PROBE1(fail1, int, rc);
+
+	memcpy(epp->ep_multicst_hash, old_hash, sizeof (old_hash));
+
+	return (rc);
+}
+
+#endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */
diff --git a/sys/dev/sfxge/common/efx_mcdi.c b/sys/dev/sfxge/common/efx_mcdi.c
index f389d57c7acc..e1c4b456dd59 100644
--- a/sys/dev/sfxge/common/efx_mcdi.c
+++ b/sys/dev/sfxge/common/efx_mcdi.c
@@ -1,26 +1,31 @@
 /*-
- * Copyright 2008-2009 Solarflare Communications Inc.  All rights reserved.
+ * Copyright (c) 2008-2015 Solarflare Communications Inc.
+ * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
+ * modification, are permitted provided that the following conditions are met:
  *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are
+ * those of the authors and should not be interpreted as representing official
+ * policies, either expressed or implied, of the FreeBSD Project.
  */
 
 #include <sys/cdefs.h>
@@ -35,12 +40,144 @@ __FBSDID("$FreeBSD$");
 
 #if EFSYS_OPT_MCDI
 
-/*
- * A reboot/assertion causes the MCDI status word to be set after the
- * command word is set or a REBOOT event is sent. If we notice a reboot
- * via these mechanisms then wait 10ms for the status word to be set.
- */
-#define	MCDI_STATUS_SLEEP_US	10000
+
+#if EFSYS_OPT_SIENA
+
+static efx_mcdi_ops_t	__efx_mcdi_siena_ops = {
+	siena_mcdi_init,		/* emco_init */
+	siena_mcdi_request_copyin,	/* emco_request_copyin */
+	siena_mcdi_request_poll,	/* emco_request_poll */
+	siena_mcdi_request_copyout,	/* emco_request_copyout */
+	siena_mcdi_poll_reboot,		/* emco_poll_reboot */
+	siena_mcdi_fini,		/* emco_fini */
+	siena_mcdi_fw_update_supported,	/* emco_fw_update_supported */
+	siena_mcdi_macaddr_change_supported,
+				/* emco_macaddr_change_supported */
+};
+
+#endif	/* EFSYS_OPT_SIENA */
+
+#if EFSYS_OPT_HUNTINGTON
+
+static efx_mcdi_ops_t	__efx_mcdi_hunt_ops = {
+	hunt_mcdi_init,			/* emco_init */
+	hunt_mcdi_request_copyin,	/* emco_request_copyin */
+	hunt_mcdi_request_poll,		/* emco_request_poll */
+	hunt_mcdi_request_copyout,	/* emco_request_copyout */
+	hunt_mcdi_poll_reboot,		/* emco_poll_reboot */
+	hunt_mcdi_fini,			/* emco_fini */
+	hunt_mcdi_fw_update_supported,	/* emco_fw_update_supported */
+	hunt_mcdi_macaddr_change_supported,
+				/* emco_macaddr_change_supported */
+};
+
+#endif	/* EFSYS_OPT_HUNTINGTON */
+
+
+
+	__checkReturn	int
+efx_mcdi_init(
+	__in		efx_nic_t *enp,
+	__in		const efx_mcdi_transport_t *emtp)
+{
+	efx_mcdi_ops_t *emcop;
+	int rc;
+
+	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
+	EFSYS_ASSERT3U(enp->en_mod_flags, ==, 0);
+
+	switch (enp->en_family) {
+#if EFSYS_OPT_FALCON
+	case EFX_FAMILY_FALCON:
+		emcop = NULL;
+		emtp = NULL;
+		break;
+#endif	/* EFSYS_OPT_FALCON */
+
+#if EFSYS_OPT_SIENA
+	case EFX_FAMILY_SIENA:
+		emcop = (efx_mcdi_ops_t *)&__efx_mcdi_siena_ops;
+		break;
+#endif	/* EFSYS_OPT_SIENA */
+
+#if EFSYS_OPT_HUNTINGTON
+	case EFX_FAMILY_HUNTINGTON:
+		emcop = (efx_mcdi_ops_t *)&__efx_mcdi_hunt_ops;
+		break;
+#endif	/* EFSYS_OPT_HUNTINGTON */
+
+	default:
+		EFSYS_ASSERT(0);
+		rc = ENOTSUP;
+		goto fail1;
+	}
+
+	if (enp->en_features & EFX_FEATURE_MCDI_DMA) {
+		/* MCDI requires a DMA buffer in host memory */
+		if ((emtp == NULL) || (emtp->emt_dma_mem) == NULL) {
+			rc = EINVAL;
+			goto fail2;
+		}
+	}
+	enp->en_mcdi.em_emtp = emtp;
+
+	if (emcop != NULL && emcop->emco_init != NULL) {
+		if ((rc = emcop->emco_init(enp, emtp)) != 0)
+			goto fail3;
+	}
+
+	enp->en_mcdi.em_emcop = emcop;
+	enp->en_mod_flags |= EFX_MOD_MCDI;
+
+	return (0);
+
+fail3:
+	EFSYS_PROBE(fail3);
+fail2:
+	EFSYS_PROBE(fail2);
+fail1:
+	EFSYS_PROBE1(fail1, int, rc);
+
+	enp->en_mcdi.em_emcop = NULL;
+	enp->en_mcdi.em_emtp = NULL;
+	enp->en_mod_flags &= ~EFX_MOD_MCDI;
+
+	return (rc);
+}
+
+			void
+efx_mcdi_fini(
+	__in		efx_nic_t *enp)
+{
+	efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
+	efx_mcdi_ops_t *emcop = enp->en_mcdi.em_emcop;
+
+	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
+	EFSYS_ASSERT3U(enp->en_mod_flags, ==, EFX_MOD_MCDI);
+
+	if (emcop != NULL && emcop->emco_fini != NULL)
+		emcop->emco_fini(enp);
+
+	emip->emi_port = 0;
+	emip->emi_aborted = 0;
+
+	enp->en_mcdi.em_emcop = NULL;
+	enp->en_mod_flags &= ~EFX_MOD_MCDI;
+}
+
+			void
+efx_mcdi_new_epoch(
+	__in		efx_nic_t *enp)
+{
+	efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
+	int state;
+
+	/* Start a new epoch (allow fresh MCDI requests to succeed) */
+	EFSYS_LOCK(enp->en_eslp, state);
+	emip->emi_new_epoch = B_TRUE;
+	EFSYS_UNLOCK(enp->en_eslp, state);
+}
+
 
 			void
 efx_mcdi_request_start(
@@ -48,32 +185,18 @@ efx_mcdi_request_start(
 	__in		efx_mcdi_req_t *emrp,
 	__in		boolean_t ev_cpl)
 {
-	efx_mcdi_iface_t *emip = &(enp->en_u.siena.enu_mip);
-	efx_dword_t dword;
+	efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
+	efx_mcdi_ops_t *emcop = enp->en_mcdi.em_emcop;
 	unsigned int seq;
-	unsigned int xflags;
-	unsigned int pdur;
-	unsigned int dbr;
-	unsigned int pos;
+	boolean_t new_epoch;
 	int state;
 
 	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
 	EFSYS_ASSERT3U(enp->en_features, &, EFX_FEATURE_MCDI);
 
-	switch (emip->emi_port)	{
-	case 1:
-		pdur = MC_SMEM_P0_PDU_OFST >> 2;
-		dbr = MC_SMEM_P0_DOORBELL_OFST >> 2;
-		break;
-	case 2:
-		pdur = MC_SMEM_P1_PDU_OFST >> 2;
-		dbr = MC_SMEM_P1_DOORBELL_OFST >> 2;
-		break;
-	default:
-		EFSYS_ASSERT(0);
-		pdur = dbr = 0;
-	};
+	if (emcop == NULL || emcop->emco_request_copyin == NULL)
+		return;
 
 	/*
 	 * efx_mcdi_request_start() is naturally serialised against both
@@ -92,68 +215,85 @@ efx_mcdi_request_start(
 	emip->emi_pending_req = emrp;
 	emip->emi_ev_cpl = ev_cpl;
 	emip->emi_poll_cnt = 0;
-	seq = emip->emi_seq++ & 0xf;
+	seq = emip->emi_seq++ & EFX_MASK32(MCDI_HEADER_SEQ);
+	new_epoch = emip->emi_new_epoch;
 	EFSYS_UNLOCK(enp->en_eslp, state);
 
-	xflags = 0;
-	if (ev_cpl)
-		xflags |= MCDI_HEADER_XFLAGS_EVREQ;
+	emcop->emco_request_copyin(enp, emrp, seq, ev_cpl, new_epoch);
+}
+
+	__checkReturn	boolean_t
+efx_mcdi_request_poll(
+	__in		efx_nic_t *enp)
+{
+	efx_mcdi_ops_t *emcop = enp->en_mcdi.em_emcop;
+	boolean_t completed;
+
+	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
+	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
+	EFSYS_ASSERT3U(enp->en_features, &, EFX_FEATURE_MCDI);
 
-	/* Construct the header in shared memory */
-	EFX_POPULATE_DWORD_6(dword,
-			    MCDI_HEADER_CODE, emrp->emr_cmd,
-			    MCDI_HEADER_RESYNC, 1,
-			    MCDI_HEADER_DATALEN, emrp->emr_in_length,
-			    MCDI_HEADER_SEQ, seq,
-			    MCDI_HEADER_RESPONSE, 0,
-			    MCDI_HEADER_XFLAGS, xflags);
-	EFX_BAR_TBL_WRITED(enp, FR_CZ_MC_TREG_SMEM, pdur, &dword, B_TRUE);
+	completed = B_FALSE;
 
-	for (pos = 0; pos < emrp->emr_in_length; pos += sizeof (efx_dword_t)) {
-		memcpy(&dword, MCDI_IN(*emrp, efx_dword_t, pos),
-		    MIN(sizeof (dword), emrp->emr_in_length - pos));
-		EFX_BAR_TBL_WRITED(enp, FR_CZ_MC_TREG_SMEM,
-		    pdur + 1 + (pos >> 2), &dword, B_FALSE);
-	}
+	if (emcop != NULL && emcop->emco_request_poll != NULL)
+		completed = emcop->emco_request_poll(enp);
 
-	/* Ring the doorbell */
-	EFX_POPULATE_DWORD_1(dword, EFX_DWORD_0, 0xd004be11);
-	EFX_BAR_TBL_WRITED(enp, FR_CZ_MC_TREG_SMEM, dbr, &dword, B_FALSE);
+	return (completed);
 }
 
-static			void
-efx_mcdi_request_copyout(
-	__in		efx_nic_t *enp,
-	__in		efx_mcdi_req_t *emrp)
-{
-	efx_mcdi_iface_t *emip = &(enp->en_u.siena.enu_mip);
-	unsigned int pos;
-	unsigned int pdur;
-	efx_dword_t data;
-
-	pdur = (emip->emi_port == 1)
-	    ? MC_SMEM_P0_PDU_OFST >> 2
-	    : MC_SMEM_P1_PDU_OFST >> 2;
-
-	/* Copy payload out if caller supplied buffer */
-	if (emrp->emr_out_buf != NULL) {
-		size_t bytes = MIN(emrp->emr_out_length_used,
-				    emrp->emr_out_length);
-		for (pos = 0; pos < bytes; pos += sizeof (efx_dword_t)) {
-			EFX_BAR_TBL_READD(enp, FR_CZ_MC_TREG_SMEM,
-			    pdur + 1 + (pos >> 2), &data, B_FALSE);
-			memcpy(MCDI_OUT(*emrp, efx_dword_t, pos), &data,
-			    MIN(sizeof (data), bytes - pos));
-		}
+	__checkReturn	boolean_t
+efx_mcdi_request_abort(
+	__in		efx_nic_t *enp)
+{
+	efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
+	efx_mcdi_req_t *emrp;
+	boolean_t aborted;
+	int state;
+
+	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
+	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
+	EFSYS_ASSERT3U(enp->en_features, &, EFX_FEATURE_MCDI);
+
+	/*
+	 * efx_mcdi_ev_* may have already completed this event, and be
+	 * spinning/blocked on the upper layer lock. So it *is* legitimate
+	 * to for emi_pending_req to be NULL. If there is a pending event
+	 * completed request, then provide a "credit" to allow
+	 * efx_mcdi_ev_cpl() to accept a single spurious completion.
+	 */
+	EFSYS_LOCK(enp->en_eslp, state);
+	emrp = emip->emi_pending_req;
+	aborted = (emrp != NULL);
+	if (aborted) {
+		emip->emi_pending_req = NULL;
+
+		/* Error the request */
+		emrp->emr_out_length_used = 0;
+		emrp->emr_rc = ETIMEDOUT;
+
+		/* Provide a credit for seqno/emr_pending_req mismatches */
+		if (emip->emi_ev_cpl)
+			++emip->emi_aborted;
+
+		/*
+		 * The upper layer has called us, so we don't
+		 * need to complete the request.
+		 */
 	}
+	EFSYS_UNLOCK(enp->en_eslp, state);
+
+	return (aborted);
 }
 
-static			int
+	__checkReturn	int
 efx_mcdi_request_errcode(
 	__in		unsigned int err)
 {
 
 	switch (err) {
+		/* MCDI v1 */
+	case MC_CMD_ERR_EPERM:
+		return (EACCES);
 	case MC_CMD_ERR_ENOENT:
 		return (ENOENT);
 	case MC_CMD_ERR_EINTR:
@@ -170,26 +310,55 @@ efx_mcdi_request_errcode(
 		return (ENOTSUP);
 	case MC_CMD_ERR_ETIME:
 		return (ETIMEDOUT);
-#ifdef WITH_MCDI_V2
+	case MC_CMD_ERR_ENOTSUP:
+		return (ENOTSUP);
+	case MC_CMD_ERR_EALREADY:
+		return (EALREADY);
+
+		/* MCDI v2 */
+#ifdef MC_CMD_ERR_EAGAIN
 	case MC_CMD_ERR_EAGAIN:
 		return (EAGAIN);
+#endif
+#ifdef MC_CMD_ERR_ENOSPC
 	case MC_CMD_ERR_ENOSPC:
 		return (ENOSPC);
 #endif
+
+	case MC_CMD_ERR_ALLOC_FAIL:
+		return (ENOMEM);
+	case MC_CMD_ERR_NO_VADAPTOR:
+		return (ENOENT);
+	case MC_CMD_ERR_NO_EVB_PORT:
+		return (ENOENT);
+	case MC_CMD_ERR_NO_VSWITCH:
+		return (ENODEV);
+	case MC_CMD_ERR_VLAN_LIMIT:
+		return (EINVAL);
+	case MC_CMD_ERR_BAD_PCI_FUNC:
+		return (ENODEV);
+	case MC_CMD_ERR_BAD_VLAN_MODE:
+		return (EINVAL);
+	case MC_CMD_ERR_BAD_VSWITCH_TYPE:
+		return (EINVAL);
+	case MC_CMD_ERR_BAD_VPORT_TYPE:
+		return (EINVAL);
+	case MC_CMD_ERR_MAC_EXIST:
+		return (EEXIST);
+
 	default:
 		EFSYS_PROBE1(mc_pcol_error, int, err);
 		return (EIO);
 	}
 }
 
-static			void
+			void
 efx_mcdi_raise_exception(
 	__in		efx_nic_t *enp,
 	__in_opt	efx_mcdi_req_t *emrp,
 	__in		int rc)
 {
-	efx_mcdi_iface_t *emip = &(enp->en_u.siena.enu_mip);
-	const efx_mcdi_transport_t *emtp = emip->emi_mtp;
+	const efx_mcdi_transport_t *emtp = enp->en_mcdi.em_emtp;
 	efx_mcdi_exception_t exception;
 
 	/* Reboot or Assertion failure only */
@@ -213,167 +382,37 @@ static			int
 efx_mcdi_poll_reboot(
 	__in		efx_nic_t *enp)
 {
-#ifndef EFX_GRACEFUL_MC_REBOOT
-	/*
-	 * This function is not being used properly.
-	 * Until its callers are fixed, it should always return 0.
-	 */
-	_NOTE(ARGUNUSED(enp))
-	return (0);
-#else
-	efx_mcdi_iface_t *emip = &(enp->en_u.siena.enu_mip);
-	unsigned int rebootr;
-	efx_dword_t dword;
-	uint32_t value;
-
-	EFSYS_ASSERT(emip->emi_port == 1 || emip->emi_port == 2);
-	rebootr = ((emip->emi_port == 1)
-	    ? MC_SMEM_P0_STATUS_OFST >> 2
-	    : MC_SMEM_P1_STATUS_OFST >> 2);
-
-	EFX_BAR_TBL_READD(enp, FR_CZ_MC_TREG_SMEM, rebootr, &dword, B_FALSE);
-	value = EFX_DWORD_FIELD(dword, EFX_DWORD_0);
-
-	if (value == 0)
-		return (0);
+	efx_mcdi_ops_t *emcop = enp->en_mcdi.em_emcop;
 
-	EFX_ZERO_DWORD(dword);
-	EFX_BAR_TBL_WRITED(enp, FR_CZ_MC_TREG_SMEM, rebootr, &dword, B_FALSE);
-
-	if (value == MC_STATUS_DWORD_ASSERT)
-		return (EINTR);
-	else
-		return (EIO);
-#endif
+	return (emcop->emco_poll_reboot(enp));
 }
 
-	__checkReturn	boolean_t
-efx_mcdi_request_poll(
-	__in		efx_nic_t *enp)
+
+			void
+efx_mcdi_execute(
+	__in		efx_nic_t *enp,
+	__inout		efx_mcdi_req_t *emrp)
 {
-	efx_mcdi_iface_t *emip = &(enp->en_u.siena.enu_mip);
-	efx_mcdi_req_t *emrp;
-	efx_dword_t dword;
-	unsigned int pdur;
-	unsigned int seq;
-	unsigned int length;
-	int state;
-	int rc;
+	const efx_mcdi_transport_t *emtp = enp->en_mcdi.em_emtp;
 
-	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
-	EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
 	EFSYS_ASSERT3U(enp->en_features, &, EFX_FEATURE_MCDI);
 
-	/* Serialise against post-watchdog efx_mcdi_ev* */
-	EFSYS_LOCK(enp->en_eslp, state);
-
-	EFSYS_ASSERT(emip->emi_pending_req != NULL);
-	EFSYS_ASSERT(!emip->emi_ev_cpl);
-	emrp = emip->emi_pending_req;
-
-	/* Check for reboot atomically w.r.t efx_mcdi_request_start */
-	if (emip->emi_poll_cnt++ == 0) {
-		if ((rc = efx_mcdi_poll_reboot(enp)) != 0) {
-			emip->emi_pending_req = NULL;
-			EFSYS_UNLOCK(enp->en_eslp, state);
-
-			goto fail1;
-		}
-	}
-
-	EFSYS_ASSERT(emip->emi_port == 1 || emip->emi_port == 2);
-	pdur = (emip->emi_port == 1)
-	    ? MC_SMEM_P0_PDU_OFST >> 2
-	    : MC_SMEM_P1_PDU_OFST >> 2;
-
-	/* Read the command header */
-	EFX_BAR_TBL_READD(enp, FR_CZ_MC_TREG_SMEM, pdur, &dword, B_FALSE);
-	if (EFX_DWORD_FIELD(dword, MCDI_HEADER_RESPONSE) == 0) {
-		EFSYS_UNLOCK(enp->en_eslp, state);
-		return (B_FALSE);
-	}
-
-	/* Request complete */
-	emip->emi_pending_req = NULL;
-	seq = (emip->emi_seq - 1) & 0xf;
-
-	/* Check for synchronous reboot */
-	if (EFX_DWORD_FIELD(dword, MCDI_HEADER_ERROR) != 0 &&
-	    EFX_DWORD_FIELD(dword, MCDI_HEADER_DATALEN) == 0) {
-		/* Consume status word */
-		EFSYS_SPIN(MCDI_STATUS_SLEEP_US);
-		efx_mcdi_poll_reboot(enp);
-		EFSYS_UNLOCK(enp->en_eslp, state);
-		rc = EIO;
-		goto fail2;
-	}
-
-	EFSYS_UNLOCK(enp->en_eslp, state);
-
-	/* Check that the returned data is consistent */
-	if (EFX_DWORD_FIELD(dword, MCDI_HEADER_CODE) != emrp->emr_cmd ||
-	    EFX_DWORD_FIELD(dword, MCDI_HEADER_SEQ) != seq) {
-		/* Response is for a different request */
-		rc = EIO;
-		goto fail3;
-	}
-
-	length = EFX_DWORD_FIELD(dword, MCDI_HEADER_DATALEN);
-	if (EFX_DWORD_FIELD(dword, MCDI_HEADER_ERROR)) {
-		efx_dword_t errdword;
-		int errcode;
-
-		EFSYS_ASSERT3U(length, ==, 4);
-		EFX_BAR_TBL_READD(enp, FR_CZ_MC_TREG_SMEM,
-		    pdur + 1 + (MC_CMD_ERR_CODE_OFST >> 2),
-		    &errdword, B_FALSE);
-		errcode = EFX_DWORD_FIELD(errdword, EFX_DWORD_0);
-		rc = efx_mcdi_request_errcode(errcode);
-		EFSYS_PROBE2(mcdi_err, int, emrp->emr_cmd, int, errcode);
-		goto fail4;
-
-	} else {
-		emrp->emr_out_length_used = length;
-		emrp->emr_rc = 0;
-		efx_mcdi_request_copyout(enp, emrp);
-	}
-
-	goto out;
-
-fail4:
-	EFSYS_PROBE(fail4);
-fail3:
-	EFSYS_PROBE(fail3);
-fail2:
-	EFSYS_PROBE(fail2);
-fail1:
-	EFSYS_PROBE1(fail1, int, rc);
-
-	/* Fill out error state */
-	emrp->emr_rc = rc;
-	emrp->emr_out_length_used = 0;
-
-	/* Reboot/Assertion */
-	if (rc == EIO || rc == EINTR)
-		efx_mcdi_raise_exception(enp, emrp, rc);
-
-out:
-	return (B_TRUE);
+	emrp->emr_quiet = B_FALSE;
+	emtp->emt_execute(emtp->emt_context, emrp);
 }
 
 			void
-efx_mcdi_execute(
+efx_mcdi_execute_quiet(
 	__in		efx_nic_t *enp,
-	__in		efx_mcdi_req_t *emrp)
+	__inout		efx_mcdi_req_t *emrp)
 {
-	efx_mcdi_iface_t *emip = &(enp->en_u.siena.enu_mip);
-	const efx_mcdi_transport_t *emtp = emip->emi_mtp;
+	const efx_mcdi_transport_t *emtp = enp->en_mcdi.em_emtp;
 
 	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
-	EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
 	EFSYS_ASSERT3U(enp->en_features, &, EFX_FEATURE_MCDI);
 
+	emrp->emr_quiet = B_TRUE;
 	emtp->emt_execute(emtp->emt_context, emrp);
 }
 
@@ -384,13 +423,13 @@ efx_mcdi_ev_cpl(
 	__in		unsigned int outlen,
 	__in		int errcode)
 {
-	efx_mcdi_iface_t *emip = &(enp->en_u.siena.enu_mip);
-	const efx_mcdi_transport_t *emtp = emip->emi_mtp;
+	efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
+	const efx_mcdi_transport_t *emtp = enp->en_mcdi.em_emtp;
+	efx_mcdi_ops_t *emcop = enp->en_mcdi.em_emcop;
 	efx_mcdi_req_t *emrp;
 	int state;
 
 	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
-	EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
 	EFSYS_ASSERT3U(enp->en_features, &, EFX_FEATURE_MCDI);
 
 	/*
@@ -399,7 +438,7 @@ efx_mcdi_ev_cpl(
 	 */
 	EFSYS_LOCK(enp->en_eslp, state);
 	if (emip->emi_pending_req == NULL || !emip->emi_ev_cpl ||
-	    (seq != ((emip->emi_seq - 1) & 0xf))) {
+	    (seq != ((emip->emi_seq - 1) & EFX_MASK32(MCDI_HEADER_SEQ)))) {
 		EFSYS_ASSERT(emip->emi_aborted > 0);
 		if (emip->emi_aborted > 0)
 			--emip->emi_aborted;
@@ -416,14 +455,17 @@ efx_mcdi_ev_cpl(
 	 * if the user supplied an output buffer.
 	 */
 	if (errcode != 0) {
-		EFSYS_PROBE2(mcdi_err, int, emrp->emr_cmd,
-		    int, errcode);
+		if (!emrp->emr_quiet) {
+			EFSYS_PROBE2(mcdi_err, int, emrp->emr_cmd,
+			    int, errcode);
+		}
 		emrp->emr_out_length_used = 0;
 		emrp->emr_rc = efx_mcdi_request_errcode(errcode);
 	} else {
 		emrp->emr_out_length_used = outlen;
 		emrp->emr_rc = 0;
-		efx_mcdi_request_copyout(enp, emrp);
+
+		emcop->emco_request_copyout(enp, emrp);
 	}
 
 	emtp->emt_ev_cpl(emtp->emt_context);
@@ -434,8 +476,8 @@ efx_mcdi_ev_death(
 	__in		efx_nic_t *enp,
 	__in		int rc)
 {
-	efx_mcdi_iface_t *emip = &(enp->en_u.siena.enu_mip);
-	const efx_mcdi_transport_t *emtp = emip->emi_mtp;
+	efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
+	const efx_mcdi_transport_t *emtp = enp->en_mcdi.em_emtp;
 	efx_mcdi_req_t *emrp = NULL;
 	boolean_t ev_cpl;
 	int state;
@@ -469,8 +511,9 @@ efx_mcdi_ev_death(
 	 * status word before dropping the lock.
 	 */
 	if (rc == EIO || rc == EINTR) {
-		EFSYS_SPIN(MCDI_STATUS_SLEEP_US);
+		EFSYS_SPIN(EFX_MCDI_STATUS_SLEEP_US);
 		(void) efx_mcdi_poll_reboot(enp);
+		emip->emi_new_epoch = B_TRUE;
 	}
 
 	EFSYS_UNLOCK(enp->en_eslp, state);
@@ -488,23 +531,24 @@ efx_mcdi_version(
 	__out_opt		uint32_t *buildp,
 	__out_opt		efx_mcdi_boot_t *statusp)
 {
-	uint8_t outbuf[MAX(MC_CMD_GET_VERSION_OUT_LEN,
-		    MC_CMD_GET_BOOT_STATUS_OUT_LEN)];
 	efx_mcdi_req_t req;
+	uint8_t payload[MAX(MAX(MC_CMD_GET_VERSION_IN_LEN,
+				MC_CMD_GET_VERSION_OUT_LEN),
+			    MAX(MC_CMD_GET_BOOT_STATUS_IN_LEN,
+				MC_CMD_GET_BOOT_STATUS_OUT_LEN))];
 	efx_word_t *ver_words;
 	uint16_t version[4];
 	uint32_t build;
 	efx_mcdi_boot_t status;
 	int rc;
 
-	EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
 	EFSYS_ASSERT3U(enp->en_features, &, EFX_FEATURE_MCDI);
 
-	EFX_STATIC_ASSERT(MC_CMD_GET_VERSION_IN_LEN == 0);
+	(void) memset(payload, 0, sizeof (payload));
 	req.emr_cmd = MC_CMD_GET_VERSION;
-	req.emr_in_buf = NULL;
-	req.emr_in_length = 0;
-	req.emr_out_buf = outbuf;
+	req.emr_in_buf = payload;
+	req.emr_in_length = MC_CMD_GET_VERSION_IN_LEN;
+	req.emr_out_buf = payload;
 	req.emr_out_length = MC_CMD_GET_VERSION_OUT_LEN;
 
 	efx_mcdi_execute(enp, &req);
@@ -536,19 +580,27 @@ efx_mcdi_version(
 
 version:
 	/* The bootrom doesn't understand BOOT_STATUS */
-	if (build == MC_CMD_GET_VERSION_OUT_FIRMWARE_SIENA_BOOTROM) {
+	if (MC_FW_VERSION_IS_BOOTLOADER(build)) {
 		status = EFX_MCDI_BOOT_ROM;
 		goto out;
 	}
 
+	(void) memset(payload, 0, sizeof (payload));
 	req.emr_cmd = MC_CMD_GET_BOOT_STATUS;
-	EFX_STATIC_ASSERT(MC_CMD_GET_BOOT_STATUS_IN_LEN == 0);
-	req.emr_in_buf = NULL;
-	req.emr_in_length = 0;
-	req.emr_out_buf = outbuf;
+	req.emr_in_buf = payload;
+	req.emr_in_length = MC_CMD_GET_BOOT_STATUS_IN_LEN;
+	req.emr_out_buf = payload;
 	req.emr_out_length = MC_CMD_GET_BOOT_STATUS_OUT_LEN;
 
-	efx_mcdi_execute(enp, &req);
+	efx_mcdi_execute_quiet(enp, &req);
+
+	if (req.emr_rc == EACCES) {
+		/* Unprivileged functions cannot access BOOT_STATUS */
+		status = EFX_MCDI_BOOT_PRIMARY;
+		version[0] = version[1] = version[2] = version[3] = 0;
+		build = 0;
+		goto out;
+	}
 
 	if (req.emr_rc != 0) {
 		rc = req.emr_rc;
@@ -588,86 +640,624 @@ fail1:
 	return (rc);
 }
 
-	__checkReturn	int
-efx_mcdi_init(
+static	__checkReturn	int
+efx_mcdi_do_reboot(
 	__in		efx_nic_t *enp,
-	__in		const efx_mcdi_transport_t *mtp)
+	__in		boolean_t after_assertion)
 {
-	efx_mcdi_iface_t *emip = &(enp->en_u.siena.enu_mip);
-	efx_oword_t oword;
-	unsigned int portnum;
+	uint8_t payload[MAX(MC_CMD_REBOOT_IN_LEN, MC_CMD_REBOOT_OUT_LEN)];
+	efx_mcdi_req_t req;
 	int rc;
 
-	EFSYS_ASSERT3U(enp->en_mod_flags, ==, 0);
-	enp->en_mod_flags |= EFX_MOD_MCDI;
+	/*
+	 * We could require the caller to have caused en_mod_flags=0 to
+	 * call this function. This doesn't help the other port though,
+	 * who's about to get the MC ripped out from underneath them.
+	 * Since they have to cope with the subsequent fallout of MCDI
+	 * failures, we should as well.
+	 */
+	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 
-	if (enp->en_family == EFX_FAMILY_FALCON)
-		return (0);
+	(void) memset(payload, 0, sizeof (payload));
+	req.emr_cmd = MC_CMD_REBOOT;
+	req.emr_in_buf = payload;
+	req.emr_in_length = MC_CMD_REBOOT_IN_LEN;
+	req.emr_out_buf = payload;
+	req.emr_out_length = MC_CMD_REBOOT_OUT_LEN;
 
-	emip->emi_mtp = mtp;
+	MCDI_IN_SET_DWORD(req, REBOOT_IN_FLAGS,
+	    (after_assertion ? MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION : 0));
 
-	/* Determine the port number to use for MCDI */
-	EFX_BAR_READO(enp, FR_AZ_CS_DEBUG_REG, &oword);
-	portnum = EFX_OWORD_FIELD(oword, FRF_CZ_CS_PORT_NUM);
+	efx_mcdi_execute_quiet(enp, &req);
 
-	if (portnum == 0) {
-		/* Presumably booted from ROM; only MCDI port 1 will work */
-		emip->emi_port = 1;
-	} else if (portnum <= 2) {
-		emip->emi_port = portnum;
-	} else {
-		rc = EINVAL;
+	if (req.emr_rc == EACCES) {
+		/* Unprivileged functions cannot reboot the MC. */
+		goto out;
+	}
+
+	/* A successful reboot request returns EIO. */
+	if (req.emr_rc != 0 && req.emr_rc != EIO) {
+		rc = req.emr_rc;
 		goto fail1;
 	}
 
+out:
+	return (0);
+
+fail1:
+	EFSYS_PROBE1(fail1, int, rc);
+
+	return (rc);
+}
+
+	__checkReturn	int
+efx_mcdi_reboot(
+	__in		efx_nic_t *enp)
+{
+	return (efx_mcdi_do_reboot(enp, B_FALSE));
+}
+
+	__checkReturn	int
+efx_mcdi_exit_assertion_handler(
+	__in		efx_nic_t *enp)
+{
+	return (efx_mcdi_do_reboot(enp, B_TRUE));
+}
+
+	__checkReturn	int
+efx_mcdi_read_assertion(
+	__in		efx_nic_t *enp)
+{
+	efx_mcdi_req_t req;
+	uint8_t payload[MAX(MC_CMD_GET_ASSERTS_IN_LEN,
+			    MC_CMD_GET_ASSERTS_OUT_LEN)];
+	const char *reason;
+	unsigned int flags;
+	unsigned int index;
+	unsigned int ofst;
+	int retry;
+	int rc;
+
 	/*
-	 * Wipe the atomic reboot status so subsequent MCDI requests succeed.
-	 * BOOT_STATUS is preserved so eno_nic_probe() can boot out of the
-	 * assertion handler.
+	 * Before we attempt to chat to the MC, we should verify that the MC
+	 * isn't in it's assertion handler, either due to a previous reboot,
+	 * or because we're reinitializing due to an eec_exception().
+	 *
+	 * Use GET_ASSERTS to read any assertion state that may be present.
+	 * Retry this command twice. Once because a boot-time assertion failure
+	 * might cause the 1st MCDI request to fail. And once again because
+	 * we might race with efx_mcdi_exit_assertion_handler() running on
+	 * partner port(s) on the same NIC.
 	 */
-	(void) efx_mcdi_poll_reboot(enp);
+	retry = 2;
+	do {
+		(void) memset(payload, 0, sizeof (payload));
+		req.emr_cmd = MC_CMD_GET_ASSERTS;
+		req.emr_in_buf = payload;
+		req.emr_in_length = MC_CMD_GET_ASSERTS_IN_LEN;
+		req.emr_out_buf = payload;
+		req.emr_out_length = MC_CMD_GET_ASSERTS_OUT_LEN;
+
+		MCDI_IN_SET_DWORD(req, GET_ASSERTS_IN_CLEAR, 1);
+		efx_mcdi_execute_quiet(enp, &req);
+
+	} while ((req.emr_rc == EINTR || req.emr_rc == EIO) && retry-- > 0);
+
+	if (req.emr_rc != 0) {
+		if (req.emr_rc == EACCES) {
+			/* Unprivileged functions cannot clear assertions. */
+			goto out;
+		}
+		rc = req.emr_rc;
+		goto fail1;
+	}
 
+	if (req.emr_out_length_used < MC_CMD_GET_ASSERTS_OUT_LEN) {
+		rc = EMSGSIZE;
+		goto fail2;
+	}
+
+	/* Print out any assertion state recorded */
+	flags = MCDI_OUT_DWORD(req, GET_ASSERTS_OUT_GLOBAL_FLAGS);
+	if (flags == MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS)
+		return (0);
+
+	reason = (flags == MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL)
+		? "system-level assertion"
+		: (flags == MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL)
+		? "thread-level assertion"
+		: (flags == MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED)
+		? "watchdog reset"
+		: (flags == MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP)
+		? "illegal address trap"
+		: "unknown assertion";
+	EFSYS_PROBE3(mcpu_assertion,
+	    const char *, reason, unsigned int,
+	    MCDI_OUT_DWORD(req, GET_ASSERTS_OUT_SAVED_PC_OFFS),
+	    unsigned int,
+	    MCDI_OUT_DWORD(req, GET_ASSERTS_OUT_THREAD_OFFS));
+
+	/* Print out the registers (r1 ... r31) */
+	ofst = MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST;
+	for (index = 1;
+		index < 1 + MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_NUM;
+		index++) {
+		EFSYS_PROBE2(mcpu_register, unsigned int, index, unsigned int,
+			    EFX_DWORD_FIELD(*MCDI_OUT(req, efx_dword_t, ofst),
+					    EFX_DWORD_0));
+		ofst += sizeof (efx_dword_t);
+	}
+	EFSYS_ASSERT(ofst <= MC_CMD_GET_ASSERTS_OUT_LEN);
+
+out:
 	return (0);
 
+fail2:
+	EFSYS_PROBE(fail2);
 fail1:
 	EFSYS_PROBE1(fail1, int, rc);
 
-	enp->en_mod_flags &= ~EFX_MOD_MCDI;
-
 	return (rc);
 }
 
 
+/*
+ * Internal routines for for specific MCDI requests.
+ */
+
 	__checkReturn	int
-efx_mcdi_reboot(
-	__in		efx_nic_t *enp)
+efx_mcdi_drv_attach(
+	__in		efx_nic_t *enp,
+	__in		boolean_t attach)
 {
-	uint8_t payload[MC_CMD_REBOOT_IN_LEN];
+	efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
 	efx_mcdi_req_t req;
+	uint8_t payload[MAX(MC_CMD_DRV_ATTACH_IN_LEN,
+			    MC_CMD_DRV_ATTACH_EXT_OUT_LEN)];
+	uint32_t flags;
 	int rc;
 
+	(void) memset(payload, 0, sizeof (payload));
+	req.emr_cmd = MC_CMD_DRV_ATTACH;
+	req.emr_in_buf = payload;
+	req.emr_in_length = MC_CMD_DRV_ATTACH_IN_LEN;
+	req.emr_out_buf = payload;
+	req.emr_out_length = MC_CMD_DRV_ATTACH_EXT_OUT_LEN;
+
 	/*
-	 * We could require the caller to have caused en_mod_flags=0 to
-	 * call this function. This doesn't help the other port though,
-	 * who's about to get the MC ripped out from underneath them.
-	 * Since they have to cope with the subsequent fallout of MCDI
-	 * failures, we should as well.
+	 * Use DONT_CARE for the datapath firmware type to ensure that the
+	 * driver can attach to an unprivileged function. The datapath firmware
+	 * type to use is controlled by the 'sfboot' utility.
 	 */
-	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
+	MCDI_IN_SET_DWORD(req, DRV_ATTACH_IN_NEW_STATE, attach ? 1 : 0);
+	MCDI_IN_SET_DWORD(req, DRV_ATTACH_IN_UPDATE, 1);
+	MCDI_IN_SET_DWORD(req, DRV_ATTACH_IN_FIRMWARE_ID, MC_CMD_FW_DONT_CARE);
 
-	req.emr_cmd = MC_CMD_REBOOT;
+	efx_mcdi_execute(enp, &req);
+
+	if (req.emr_rc != 0) {
+		rc = req.emr_rc;
+		goto fail1;
+	}
+
+	if (req.emr_out_length_used < MC_CMD_DRV_ATTACH_OUT_LEN) {
+		rc = EMSGSIZE;
+		goto fail2;
+	}
+
+	if (attach == B_FALSE) {
+		flags = 0;
+	} else if (enp->en_family == EFX_FAMILY_SIENA) {
+		efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
+
+		/* Create synthetic privileges for Siena functions */
+		flags = EFX_NIC_FUNC_LINKCTRL | EFX_NIC_FUNC_TRUSTED;
+		if (emip->emi_port == 1)
+			flags |= EFX_NIC_FUNC_PRIMARY;
+	} else {
+		EFX_STATIC_ASSERT(EFX_NIC_FUNC_PRIMARY ==
+		    (1u << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY));
+		EFX_STATIC_ASSERT(EFX_NIC_FUNC_LINKCTRL ==
+		    (1u << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL));
+		EFX_STATIC_ASSERT(EFX_NIC_FUNC_TRUSTED ==
+		    (1u << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED));
+
+		/* Save function privilege flags (EF10 and later) */
+		if (req.emr_out_length_used < MC_CMD_DRV_ATTACH_EXT_OUT_LEN) {
+			rc = EMSGSIZE;
+			goto fail3;
+		}
+		flags = MCDI_OUT_DWORD(req, DRV_ATTACH_EXT_OUT_FUNC_FLAGS);
+	}
+	encp->enc_func_flags = flags;
+
+	return (0);
+
+fail3:
+	EFSYS_PROBE(fail3);
+fail2:
+	EFSYS_PROBE(fail2);
+fail1:
+	EFSYS_PROBE1(fail1, int, rc);
+
+	return (rc);
+}
+
+	__checkReturn		int
+efx_mcdi_get_board_cfg(
+	__in			efx_nic_t *enp,
+	__out_opt		uint32_t *board_typep,
+	__out_opt		efx_dword_t *capabilitiesp,
+	__out_ecount_opt(6)	uint8_t mac_addrp[6])
+{
+	efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
+	efx_mcdi_req_t req;
+	uint8_t payload[MAX(MC_CMD_GET_BOARD_CFG_IN_LEN,
+			    MC_CMD_GET_BOARD_CFG_OUT_LENMIN)];
+	int rc;
+
+	(void) memset(payload, 0, sizeof (payload));
+	req.emr_cmd = MC_CMD_GET_BOARD_CFG;
 	req.emr_in_buf = payload;
-	req.emr_in_length = MC_CMD_REBOOT_IN_LEN;
+	req.emr_in_length = MC_CMD_GET_BOARD_CFG_IN_LEN;
+	req.emr_out_buf = payload;
+	req.emr_out_length = MC_CMD_GET_BOARD_CFG_OUT_LENMIN;
+
+	efx_mcdi_execute(enp, &req);
+
+	if (req.emr_rc != 0) {
+		rc = req.emr_rc;
+		goto fail1;
+	}
+
+	if (req.emr_out_length_used < MC_CMD_GET_BOARD_CFG_OUT_LENMIN) {
+		rc = EMSGSIZE;
+		goto fail2;
+	}
+
+	if (mac_addrp != NULL) {
+		uint8_t *addrp;
+
+		if (emip->emi_port == 1) {
+			addrp = MCDI_OUT2(req, uint8_t,
+			    GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0);
+		} else if (emip->emi_port == 2) {
+			addrp = MCDI_OUT2(req, uint8_t,
+			    GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1);
+		} else {
+			rc = EINVAL;
+			goto fail3;
+		}
+
+		EFX_MAC_ADDR_COPY(mac_addrp, addrp);
+	}
+
+	if (capabilitiesp != NULL) {
+		if (emip->emi_port == 1) {
+			*capabilitiesp = *MCDI_OUT2(req, efx_dword_t,
+			    GET_BOARD_CFG_OUT_CAPABILITIES_PORT0);
+		} else if (emip->emi_port == 2) {
+			*capabilitiesp = *MCDI_OUT2(req, efx_dword_t,
+			    GET_BOARD_CFG_OUT_CAPABILITIES_PORT1);
+		} else {
+			rc = EINVAL;
+			goto fail4;
+		}
+	}
+
+	if (board_typep != NULL) {
+		*board_typep = MCDI_OUT_DWORD(req,
+		    GET_BOARD_CFG_OUT_BOARD_TYPE);
+	}
+
+	return (0);
+
+fail4:
+	EFSYS_PROBE(fail4);
+fail3:
+	EFSYS_PROBE(fail3);
+fail2:
+	EFSYS_PROBE(fail2);
+fail1:
+	EFSYS_PROBE1(fail1, int, rc);
+
+	return (rc);
+}
+
+	__checkReturn	int
+efx_mcdi_get_resource_limits(
+	__in		efx_nic_t *enp,
+	__out_opt	uint32_t *nevqp,
+	__out_opt	uint32_t *nrxqp,
+	__out_opt	uint32_t *ntxqp)
+{
+	efx_mcdi_req_t req;
+	uint8_t payload[MAX(MC_CMD_GET_RESOURCE_LIMITS_IN_LEN,
+			    MC_CMD_GET_RESOURCE_LIMITS_OUT_LEN)];
+	int rc;
+
+	(void) memset(payload, 0, sizeof (payload));
+	req.emr_cmd = MC_CMD_GET_RESOURCE_LIMITS;
+	req.emr_in_buf = payload;
+	req.emr_in_length = MC_CMD_GET_RESOURCE_LIMITS_IN_LEN;
+	req.emr_out_buf = payload;
+	req.emr_out_length = MC_CMD_GET_RESOURCE_LIMITS_OUT_LEN;
+
+	efx_mcdi_execute(enp, &req);
+
+	if (req.emr_rc != 0) {
+		rc = req.emr_rc;
+		goto fail1;
+	}
+
+	if (req.emr_out_length_used < MC_CMD_GET_RESOURCE_LIMITS_OUT_LEN) {
+		rc = EMSGSIZE;
+		goto fail2;
+	}
+
+	if (nevqp != NULL)
+		*nevqp = MCDI_OUT_DWORD(req, GET_RESOURCE_LIMITS_OUT_EVQ);
+	if (nrxqp != NULL)
+		*nrxqp = MCDI_OUT_DWORD(req, GET_RESOURCE_LIMITS_OUT_RXQ);
+	if (ntxqp != NULL)
+		*ntxqp = MCDI_OUT_DWORD(req, GET_RESOURCE_LIMITS_OUT_TXQ);
+
+	return (0);
+
+fail2:
+	EFSYS_PROBE(fail2);
+fail1:
+	EFSYS_PROBE1(fail1, int, rc);
+
+	return (rc);
+}
+
+	__checkReturn	int
+efx_mcdi_get_phy_cfg(
+	__in		efx_nic_t *enp)
+{
+	efx_port_t *epp = &(enp->en_port);
+	efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
+	efx_mcdi_req_t req;
+	uint8_t payload[MAX(MC_CMD_GET_PHY_CFG_IN_LEN,
+			    MC_CMD_GET_PHY_CFG_OUT_LEN)];
+	int rc;
+
+	(void) memset(payload, 0, sizeof (payload));
+	req.emr_cmd = MC_CMD_GET_PHY_CFG;
+	req.emr_in_buf = payload;
+	req.emr_in_length = MC_CMD_GET_PHY_CFG_IN_LEN;
+	req.emr_out_buf = payload;
+	req.emr_out_length = MC_CMD_GET_PHY_CFG_OUT_LEN;
+
+	efx_mcdi_execute(enp, &req);
+
+	if (req.emr_rc != 0) {
+		rc = req.emr_rc;
+		goto fail1;
+	}
+
+	if (req.emr_out_length_used < MC_CMD_GET_PHY_CFG_OUT_LEN) {
+		rc = EMSGSIZE;
+		goto fail2;
+	}
+
+	encp->enc_phy_type = MCDI_OUT_DWORD(req, GET_PHY_CFG_OUT_TYPE);
+#if EFSYS_OPT_NAMES
+	(void) strncpy(encp->enc_phy_name,
+		MCDI_OUT2(req, char, GET_PHY_CFG_OUT_NAME),
+		MIN(sizeof (encp->enc_phy_name) - 1,
+		    MC_CMD_GET_PHY_CFG_OUT_NAME_LEN));
+#endif	/* EFSYS_OPT_NAMES */
+	(void) memset(encp->enc_phy_revision, 0,
+	    sizeof (encp->enc_phy_revision));
+	memcpy(encp->enc_phy_revision,
+		MCDI_OUT2(req, char, GET_PHY_CFG_OUT_REVISION),
+		MIN(sizeof (encp->enc_phy_revision) - 1,
+		    MC_CMD_GET_PHY_CFG_OUT_REVISION_LEN));
+#if EFSYS_OPT_PHY_LED_CONTROL
+	encp->enc_led_mask = ((1 << EFX_PHY_LED_DEFAULT) |
+			    (1 << EFX_PHY_LED_OFF) |
+			    (1 << EFX_PHY_LED_ON));
+#endif	/* EFSYS_OPT_PHY_LED_CONTROL */
+
+#if EFSYS_OPT_PHY_PROPS
+	encp->enc_phy_nprops  = 0;
+#endif	/* EFSYS_OPT_PHY_PROPS */
+
+	/* Get the media type of the fixed port, if recognised. */
+	EFX_STATIC_ASSERT(MC_CMD_MEDIA_XAUI == EFX_PHY_MEDIA_XAUI);
+	EFX_STATIC_ASSERT(MC_CMD_MEDIA_CX4 == EFX_PHY_MEDIA_CX4);
+	EFX_STATIC_ASSERT(MC_CMD_MEDIA_KX4 == EFX_PHY_MEDIA_KX4);
+	EFX_STATIC_ASSERT(MC_CMD_MEDIA_XFP == EFX_PHY_MEDIA_XFP);
+	EFX_STATIC_ASSERT(MC_CMD_MEDIA_SFP_PLUS == EFX_PHY_MEDIA_SFP_PLUS);
+	EFX_STATIC_ASSERT(MC_CMD_MEDIA_BASE_T == EFX_PHY_MEDIA_BASE_T);
+	EFX_STATIC_ASSERT(MC_CMD_MEDIA_QSFP_PLUS == EFX_PHY_MEDIA_QSFP_PLUS);
+	epp->ep_fixed_port_type =
+		MCDI_OUT_DWORD(req, GET_PHY_CFG_OUT_MEDIA_TYPE);
+	if (epp->ep_fixed_port_type >= EFX_PHY_MEDIA_NTYPES)
+		epp->ep_fixed_port_type = EFX_PHY_MEDIA_INVALID;
+
+	epp->ep_phy_cap_mask =
+		MCDI_OUT_DWORD(req, GET_PHY_CFG_OUT_SUPPORTED_CAP);
+#if EFSYS_OPT_PHY_FLAGS
+	encp->enc_phy_flags_mask = MCDI_OUT_DWORD(req, GET_PHY_CFG_OUT_FLAGS);
+#endif	/* EFSYS_OPT_PHY_FLAGS */
+
+	encp->enc_port = (uint8_t)MCDI_OUT_DWORD(req, GET_PHY_CFG_OUT_PRT);
+
+	/* Populate internal state */
+	encp->enc_mcdi_mdio_channel =
+		(uint8_t)MCDI_OUT_DWORD(req, GET_PHY_CFG_OUT_CHANNEL);
+
+#if EFSYS_OPT_PHY_STATS
+	encp->enc_mcdi_phy_stat_mask =
+		MCDI_OUT_DWORD(req, GET_PHY_CFG_OUT_STATS_MASK);
+#endif	/* EFSYS_OPT_PHY_STATS */
+
+#if EFSYS_OPT_BIST
+	encp->enc_bist_mask = 0;
+	if (MCDI_OUT_DWORD_FIELD(req, GET_PHY_CFG_OUT_FLAGS,
+	    GET_PHY_CFG_OUT_BIST_CABLE_SHORT))
+		encp->enc_bist_mask |= (1 << EFX_BIST_TYPE_PHY_CABLE_SHORT);
+	if (MCDI_OUT_DWORD_FIELD(req, GET_PHY_CFG_OUT_FLAGS,
+	    GET_PHY_CFG_OUT_BIST_CABLE_LONG))
+		encp->enc_bist_mask |= (1 << EFX_BIST_TYPE_PHY_CABLE_LONG);
+	if (MCDI_OUT_DWORD_FIELD(req, GET_PHY_CFG_OUT_FLAGS,
+	    GET_PHY_CFG_OUT_BIST))
+		encp->enc_bist_mask |= (1 << EFX_BIST_TYPE_PHY_NORMAL);
+#endif  /* EFSYS_OPT_BIST */
+
+	return (0);
+
+fail2:
+	EFSYS_PROBE(fail2);
+fail1:
+	EFSYS_PROBE1(fail1, int, rc);
+
+	return (rc);
+}
+
+
+	__checkReturn		int
+efx_mcdi_firmware_update_supported(
+	__in			efx_nic_t *enp,
+	__out			boolean_t *supportedp)
+{
+	efx_mcdi_ops_t *emcop = enp->en_mcdi.em_emcop;
+	int rc;
+
+	if (emcop != NULL && emcop->emco_fw_update_supported != NULL) {
+		if ((rc = emcop->emco_fw_update_supported(enp, supportedp))
+		    != 0)
+			goto fail1;
+	} else {
+		/* Earlier devices always supported updates */
+		*supportedp = B_TRUE;
+	}
+
+	return (0);
+
+fail1:
+	EFSYS_PROBE1(fail1, int, rc);
+
+	return (rc);
+}
+
+	__checkReturn		int
+efx_mcdi_macaddr_change_supported(
+	__in			efx_nic_t *enp,
+	__out			boolean_t *supportedp)
+{
+	efx_mcdi_ops_t *emcop = enp->en_mcdi.em_emcop;
+	int rc;
+
+	if (emcop != NULL && emcop->emco_macaddr_change_supported != NULL) {
+		if ((rc = emcop->emco_macaddr_change_supported(enp, supportedp))
+		    != 0)
+			goto fail1;
+	} else {
+		/* Earlier devices always supported MAC changes */
+		*supportedp = B_TRUE;
+	}
+
+	return (0);
+
+fail1:
+	EFSYS_PROBE1(fail1, int, rc);
+
+	return (rc);
+}
+
+#if EFSYS_OPT_BIST
+
+#if EFSYS_OPT_HUNTINGTON
+/*
+ * Enter bist offline mode. This is a fw mode which puts the NIC into a state
+ * where memory BIST tests can be run and not much else can interfere or happen.
+ * A reboot is required to exit this mode.
+ */
+	__checkReturn		int
+efx_mcdi_bist_enable_offline(
+	__in			efx_nic_t *enp)
+{
+	efx_mcdi_req_t req;
+	int rc;
+
+	EFX_STATIC_ASSERT(MC_CMD_ENABLE_OFFLINE_BIST_IN_LEN == 0);
+	EFX_STATIC_ASSERT(MC_CMD_ENABLE_OFFLINE_BIST_OUT_LEN == 0);
+
+	req.emr_cmd = MC_CMD_ENABLE_OFFLINE_BIST;
+	req.emr_in_buf = NULL;
+	req.emr_in_length = 0;
 	req.emr_out_buf = NULL;
 	req.emr_out_length = 0;
 
-	MCDI_IN_SET_DWORD(req, REBOOT_IN_FLAGS, 0);
+	efx_mcdi_execute(enp, &req);
+
+	if (req.emr_rc != 0) {
+		rc = req.emr_rc;
+		goto fail1;
+	}
+
+	return (0);
+
+fail1:
+	EFSYS_PROBE1(fail1, int, rc);
+
+	return (rc);
+}
+#endif /* EFSYS_OPT_HUNTINGTON */
+
+	__checkReturn		int
+efx_mcdi_bist_start(
+	__in			efx_nic_t *enp,
+	__in			efx_bist_type_t type)
+{
+	efx_mcdi_req_t req;
+	uint8_t payload[MAX(MC_CMD_START_BIST_IN_LEN,
+			    MC_CMD_START_BIST_OUT_LEN)];
+	int rc;
+
+	(void) memset(payload, 0, sizeof (payload));
+	req.emr_cmd = MC_CMD_START_BIST;
+	req.emr_in_buf = payload;
+	req.emr_in_length = MC_CMD_START_BIST_IN_LEN;
+	req.emr_out_buf = payload;
+	req.emr_out_length = MC_CMD_START_BIST_OUT_LEN;
+
+	switch (type) {
+	case EFX_BIST_TYPE_PHY_NORMAL:
+		MCDI_IN_SET_DWORD(req, START_BIST_IN_TYPE, MC_CMD_PHY_BIST);
+		break;
+	case EFX_BIST_TYPE_PHY_CABLE_SHORT:
+		MCDI_IN_SET_DWORD(req, START_BIST_IN_TYPE,
+		    MC_CMD_PHY_BIST_CABLE_SHORT);
+		break;
+	case EFX_BIST_TYPE_PHY_CABLE_LONG:
+		MCDI_IN_SET_DWORD(req, START_BIST_IN_TYPE,
+		    MC_CMD_PHY_BIST_CABLE_LONG);
+		break;
+	case EFX_BIST_TYPE_MC_MEM:
+		MCDI_IN_SET_DWORD(req, START_BIST_IN_TYPE,
+		    MC_CMD_MC_MEM_BIST);
+		break;
+	case EFX_BIST_TYPE_SAT_MEM:
+		MCDI_IN_SET_DWORD(req, START_BIST_IN_TYPE,
+		    MC_CMD_PORT_MEM_BIST);
+		break;
+	case EFX_BIST_TYPE_REG:
+		MCDI_IN_SET_DWORD(req, START_BIST_IN_TYPE,
+		    MC_CMD_REG_BIST);
+		break;
+	default:
+		EFSYS_ASSERT(0);
+	}
 
 	efx_mcdi_execute(enp, &req);
 
-	/* Invert EIO */
-	if (req.emr_rc != EIO) {
-		rc = EIO;
+	if (req.emr_rc != 0) {
+		rc = req.emr_rc;
 		goto fail1;
 	}
 
@@ -679,64 +1269,391 @@ fail1:
 	return (rc);
 }
 
-	__checkReturn	boolean_t
-efx_mcdi_request_abort(
+#endif /* EFSYS_OPT_BIST */
+
+
+/* Enable logging of some events (e.g. link state changes) */
+	__checkReturn	int
+efx_mcdi_log_ctrl(
 	__in		efx_nic_t *enp)
 {
-	efx_mcdi_iface_t *emip = &(enp->en_u.siena.enu_mip);
-	efx_mcdi_req_t *emrp;
-	boolean_t aborted;
-	int state;
+	efx_mcdi_req_t req;
+	uint8_t payload[MAX(MC_CMD_LOG_CTRL_IN_LEN,
+			    MC_CMD_LOG_CTRL_OUT_LEN)];
+	int rc;
 
-	EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
-	EFSYS_ASSERT3U(enp->en_features, &, EFX_FEATURE_MCDI);
+	(void) memset(payload, 0, sizeof (payload));
+	req.emr_cmd = MC_CMD_LOG_CTRL;
+	req.emr_in_buf = payload;
+	req.emr_in_length = MC_CMD_LOG_CTRL_IN_LEN;
+	req.emr_out_buf = payload;
+	req.emr_out_length = MC_CMD_LOG_CTRL_OUT_LEN;
+
+	MCDI_IN_SET_DWORD(req, LOG_CTRL_IN_LOG_DEST,
+		    MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ);
+	MCDI_IN_SET_DWORD(req, LOG_CTRL_IN_LOG_DEST_EVQ, 0);
+
+	efx_mcdi_execute(enp, &req);
+
+	if (req.emr_rc != 0) {
+		rc = req.emr_rc;
+		goto fail1;
+	}
+
+	return (0);
+
+fail1:
+	EFSYS_PROBE1(fail1, int, rc);
+
+	return (rc);
+}
+
+
+#if EFSYS_OPT_MAC_STATS
+
+typedef enum efx_stats_action_e
+{
+	EFX_STATS_CLEAR,
+	EFX_STATS_UPLOAD,
+	EFX_STATS_ENABLE_NOEVENTS,
+	EFX_STATS_ENABLE_EVENTS,
+	EFX_STATS_DISABLE,
+} efx_stats_action_t;
+
+static	__checkReturn	int
+efx_mcdi_mac_stats(
+	__in		efx_nic_t *enp,
+	__in_opt	efsys_mem_t *esmp,
+	__in		efx_stats_action_t action)
+{
+	efx_mcdi_req_t req;
+	uint8_t payload[MAX(MC_CMD_MAC_STATS_IN_LEN,
+			    MC_CMD_MAC_STATS_OUT_DMA_LEN)];
+	int clear = (action == EFX_STATS_CLEAR);
+	int upload = (action == EFX_STATS_UPLOAD);
+	int enable = (action == EFX_STATS_ENABLE_NOEVENTS);
+	int events = (action == EFX_STATS_ENABLE_EVENTS);
+	int disable = (action == EFX_STATS_DISABLE);
+	int rc;
+
+	(void) memset(payload, 0, sizeof (payload));
+	req.emr_cmd = MC_CMD_MAC_STATS;
+	req.emr_in_buf = payload;
+	req.emr_in_length = MC_CMD_MAC_STATS_IN_LEN;
+	req.emr_out_buf = payload;
+	req.emr_out_length = MC_CMD_MAC_STATS_OUT_DMA_LEN;
+
+	MCDI_IN_POPULATE_DWORD_6(req, MAC_STATS_IN_CMD,
+	    MAC_STATS_IN_DMA, upload,
+	    MAC_STATS_IN_CLEAR, clear,
+	    MAC_STATS_IN_PERIODIC_CHANGE, enable | events | disable,
+	    MAC_STATS_IN_PERIODIC_ENABLE, enable | events,
+	    MAC_STATS_IN_PERIODIC_NOEVENT, !events,
+	    MAC_STATS_IN_PERIOD_MS, (enable | events) ? 1000: 0);
+
+	if (esmp != NULL) {
+		int bytes = MC_CMD_MAC_NSTATS * sizeof (uint64_t);
+
+		EFX_STATIC_ASSERT(MC_CMD_MAC_NSTATS * sizeof (uint64_t) <=
+		    EFX_MAC_STATS_SIZE);
+
+		MCDI_IN_SET_DWORD(req, MAC_STATS_IN_DMA_ADDR_LO,
+			    EFSYS_MEM_ADDR(esmp) & 0xffffffff);
+		MCDI_IN_SET_DWORD(req, MAC_STATS_IN_DMA_ADDR_HI,
+			    EFSYS_MEM_ADDR(esmp) >> 32);
+		MCDI_IN_SET_DWORD(req, MAC_STATS_IN_DMA_LEN, bytes);
+	} else {
+		EFSYS_ASSERT(!upload && !enable && !events);
+	}
 
 	/*
-	 * efx_mcdi_ev_* may have already completed this event, and be
-	 * spinning/blocked on the upper layer lock. So it *is* legitimate
-	 * to for emi_pending_req to be NULL. If there is a pending event
-	 * completed request, then provide a "credit" to allow
-	 * efx_mcdi_ev_cpl() to accept a single spurious completion.
+	 * NOTE: Do not use EVB_PORT_ID_ASSIGNED when disabling periodic stats,
+	 *	 as this may fail (and leave periodic DMA enabled) if the
+	 *	 vadapter has already been deleted.
 	 */
-	EFSYS_LOCK(enp->en_eslp, state);
-	emrp = emip->emi_pending_req;
-	aborted = (emrp != NULL);
-	if (aborted) {
-		emip->emi_pending_req = NULL;
+	MCDI_IN_SET_DWORD(req, MAC_STATS_IN_PORT_ID,
+	    (disable ? EVB_PORT_ID_NULL : enp->en_vport_id));
 
-		/* Error the request */
-		emrp->emr_out_length_used = 0;
-		emrp->emr_rc = ETIMEDOUT;
-
-		/* Provide a credit for seqno/emr_pending_req mismatches */
-		if (emip->emi_ev_cpl)
-			++emip->emi_aborted;
+	efx_mcdi_execute(enp, &req);
 
-		/*
-		 * The upper layer has called us, so we don't
-		 * need to complete the request.
-		 */
+	if (req.emr_rc != 0) {
+		/* EF10: Expect ENOENT if no DMA queues are initialised */
+		if ((req.emr_rc != ENOENT) ||
+		    (enp->en_rx_qcount + enp->en_tx_qcount != 0)) {
+			rc = req.emr_rc;
+			goto fail1;
+		}
 	}
-	EFSYS_UNLOCK(enp->en_eslp, state);
 
-	return (aborted);
+	return (0);
+
+fail1:
+	EFSYS_PROBE1(fail1, int, rc);
+
+	return (rc);
 }
 
-			void
-efx_mcdi_fini(
+	__checkReturn	int
+efx_mcdi_mac_stats_clear(
 	__in		efx_nic_t *enp)
 {
-	efx_mcdi_iface_t *emip = &(enp->en_u.siena.enu_mip);
+	int rc;
 
-	EFSYS_ASSERT3U(enp->en_mod_flags, ==, EFX_MOD_MCDI);
-	enp->en_mod_flags &= ~EFX_MOD_MCDI;
+	if ((rc = efx_mcdi_mac_stats(enp, NULL, EFX_STATS_CLEAR)) != 0)
+		goto fail1;
 
-	if (~(enp->en_features) & EFX_FEATURE_MCDI)
-		return;
+	return (0);
 
-	emip->emi_mtp = NULL;
-	emip->emi_port = 0;
-	emip->emi_aborted = 0;
+fail1:
+	EFSYS_PROBE1(fail1, int, rc);
+
+	return (rc);
 }
 
+	__checkReturn	int
+efx_mcdi_mac_stats_upload(
+	__in		efx_nic_t *enp,
+	__in		efsys_mem_t *esmp)
+{
+	int rc;
+
+	/*
+	 * The MC DMAs aggregate statistics for our convenience, so we can
+	 * avoid having to pull the statistics buffer into the cache to
+	 * maintain cumulative statistics.
+	 */
+	if ((rc = efx_mcdi_mac_stats(enp, esmp, EFX_STATS_UPLOAD)) != 0)
+		goto fail1;
+
+	return (0);
+
+fail1:
+	EFSYS_PROBE1(fail1, int, rc);
+
+	return (rc);
+}
+
+	__checkReturn	int
+efx_mcdi_mac_stats_periodic(
+	__in		efx_nic_t *enp,
+	__in		efsys_mem_t *esmp,
+	__in		uint16_t period,
+	__in		boolean_t events)
+{
+	int rc;
+
+	/*
+	 * The MC DMAs aggregate statistics for our convenience, so we can
+	 * avoid having to pull the statistics buffer into the cache to
+	 * maintain cumulative statistics.
+	 * Huntington uses a fixed 1sec period, so use that on Siena too.
+	 */
+	if (period == 0)
+		rc = efx_mcdi_mac_stats(enp, NULL, EFX_STATS_DISABLE);
+	else if (events)
+		rc = efx_mcdi_mac_stats(enp, esmp, EFX_STATS_ENABLE_EVENTS);
+	else
+		rc = efx_mcdi_mac_stats(enp, esmp, EFX_STATS_ENABLE_NOEVENTS);
+
+	if (rc != 0)
+		goto fail1;
+
+	return (0);
+
+fail1:
+	EFSYS_PROBE1(fail1, int, rc);
+
+	return (rc);
+}
+
+#endif	/* EFSYS_OPT_MAC_STATS */
+
+#if EFSYS_OPT_HUNTINGTON
+
+/*
+ * This function returns the pf and vf number of a function.  If it is a pf the
+ * vf number is 0xffff.  The vf number is the index of the vf on that
+ * function. So if you have 3 vfs on pf 0 the 3 vfs will return (pf=0,vf=0),
+ * (pf=0,vf=1), (pf=0,vf=2) aand the pf will return (pf=0, vf=0xffff).
+ */
+	__checkReturn		int
+efx_mcdi_get_function_info(
+	__in			efx_nic_t *enp,
+	__out			uint32_t *pfp,
+	__out_opt		uint32_t *vfp)
+{
+	efx_mcdi_req_t req;
+	uint8_t payload[MAX(MC_CMD_GET_FUNCTION_INFO_IN_LEN,
+			    MC_CMD_GET_FUNCTION_INFO_OUT_LEN)];
+	int rc;
+
+	(void) memset(payload, 0, sizeof (payload));
+	req.emr_cmd = MC_CMD_GET_FUNCTION_INFO;
+	req.emr_in_buf = payload;
+	req.emr_in_length = MC_CMD_GET_FUNCTION_INFO_IN_LEN;
+	req.emr_out_buf = payload;
+	req.emr_out_length = MC_CMD_GET_FUNCTION_INFO_OUT_LEN;
+
+	efx_mcdi_execute(enp, &req);
+
+	if (req.emr_rc != 0) {
+		rc = req.emr_rc;
+		goto fail1;
+	}
+
+	if (req.emr_out_length_used < MC_CMD_GET_FUNCTION_INFO_OUT_LEN) {
+		rc = EMSGSIZE;
+		goto fail2;
+	}
+
+	*pfp = MCDI_OUT_DWORD(req, GET_FUNCTION_INFO_OUT_PF);
+	if (vfp != NULL)
+		*vfp = MCDI_OUT_DWORD(req, GET_FUNCTION_INFO_OUT_VF);
+
+	return (0);
+
+fail2:
+	EFSYS_PROBE(fail2);
+fail1:
+	EFSYS_PROBE1(fail1, int, rc);
+
+	return (rc);
+}
+
+	__checkReturn		int
+efx_mcdi_privilege_mask(
+	__in			efx_nic_t *enp,
+	__in			uint32_t pf,
+	__in			uint32_t vf,
+	__out			uint32_t *maskp)
+{
+	efx_mcdi_req_t req;
+	uint8_t payload[MAX(MC_CMD_PRIVILEGE_MASK_IN_LEN,
+			    MC_CMD_PRIVILEGE_MASK_OUT_LEN)];
+	int rc;
+
+	(void) memset(payload, 0, sizeof (payload));
+	req.emr_cmd = MC_CMD_PRIVILEGE_MASK;
+	req.emr_in_buf = payload;
+	req.emr_in_length = MC_CMD_PRIVILEGE_MASK_IN_LEN;
+	req.emr_out_buf = payload;
+	req.emr_out_length = MC_CMD_PRIVILEGE_MASK_OUT_LEN;
+
+	MCDI_IN_POPULATE_DWORD_2(req, PRIVILEGE_MASK_IN_FUNCTION,
+	    PRIVILEGE_MASK_IN_FUNCTION_PF, pf,
+	    PRIVILEGE_MASK_IN_FUNCTION_VF, vf);
+
+	efx_mcdi_execute(enp, &req);
+
+	if (req.emr_rc != 0) {
+		rc = req.emr_rc;
+		goto fail1;
+	}
+
+	if (req.emr_out_length_used < MC_CMD_PRIVILEGE_MASK_OUT_LEN) {
+		rc = EMSGSIZE;
+		goto fail2;
+	}
+
+	*maskp = MCDI_OUT_DWORD(req, PRIVILEGE_MASK_OUT_OLD_MASK);
+
+	return (0);
+
+fail2:
+	EFSYS_PROBE(fail2);
+fail1:
+	EFSYS_PROBE1(fail1, int, rc);
+
+	return (rc);
+}
+
+#endif /* EFSYS_OPT_HUNTINGTON */
+
+	__checkReturn		int
+efx_mcdi_set_workaround(
+	__in			efx_nic_t *enp,
+	__in			uint32_t type,
+	__in			boolean_t enabled,
+	__out_opt		uint32_t *flagsp)
+{
+	efx_mcdi_req_t req;
+	uint8_t payload[MAX(MC_CMD_WORKAROUND_IN_LEN,
+			    MC_CMD_WORKAROUND_EXT_OUT_LEN)];
+	int rc;
+
+	(void) memset(payload, 0, sizeof (payload));
+	req.emr_cmd = MC_CMD_WORKAROUND;
+	req.emr_in_buf = payload;
+	req.emr_in_length = MC_CMD_WORKAROUND_IN_LEN;
+	req.emr_out_buf = payload;
+	req.emr_out_length = MC_CMD_WORKAROUND_OUT_LEN;
+
+	MCDI_IN_SET_DWORD(req, WORKAROUND_IN_TYPE, type);
+	MCDI_IN_SET_DWORD(req, WORKAROUND_IN_ENABLED, enabled ? 1 : 0);
+
+	efx_mcdi_execute_quiet(enp, &req);
+
+	if (req.emr_rc != 0) {
+		rc = req.emr_rc;
+		goto fail1;
+	}
+
+	if (flagsp != NULL) {
+		if (req.emr_out_length_used >= MC_CMD_WORKAROUND_EXT_OUT_LEN)
+			*flagsp = MCDI_OUT_DWORD(req, WORKAROUND_EXT_OUT_FLAGS);
+		else
+			*flagsp = 0;
+	}
+
+	return (0);
+
+fail1:
+	EFSYS_PROBE1(fail1, int, rc);
+
+	return (rc);
+}
+
+
+	__checkReturn		int
+efx_mcdi_get_workarounds(
+	__in			efx_nic_t *enp,
+	__out_opt		uint32_t *implementedp,
+	__out_opt		uint32_t *enabledp)
+{
+	efx_mcdi_req_t req;
+	uint8_t payload[MC_CMD_GET_WORKAROUNDS_OUT_LEN];
+	int rc;
+
+	(void) memset(payload, 0, sizeof (payload));
+	req.emr_cmd = MC_CMD_GET_WORKAROUNDS;
+	req.emr_in_buf = NULL;
+	req.emr_in_length = 0;
+	req.emr_out_buf = payload;
+	req.emr_out_length = MC_CMD_GET_WORKAROUNDS_OUT_LEN;
+
+	efx_mcdi_execute(enp, &req);
+
+	if (req.emr_rc != 0) {
+		rc = req.emr_rc;
+		goto fail1;
+	}
+
+	if (implementedp != NULL) {
+		*implementedp =
+		    MCDI_OUT_DWORD(req, GET_WORKAROUNDS_OUT_IMPLEMENTED);
+	}
+
+	if (enabledp != NULL) {
+		*enabledp = MCDI_OUT_DWORD(req, GET_WORKAROUNDS_OUT_ENABLED);
+	}
+
+	return (0);
+
+fail1:
+	EFSYS_PROBE1(fail1, int, rc);
+
+	return (rc);
+}
+
+
 #endif	/* EFSYS_OPT_MCDI */
diff --git a/sys/dev/sfxge/common/efx_mcdi.h b/sys/dev/sfxge/common/efx_mcdi.h
index b1157466495b..ea0224878162 100644
--- a/sys/dev/sfxge/common/efx_mcdi.h
+++ b/sys/dev/sfxge/common/efx_mcdi.h
@@ -1,26 +1,31 @@
 /*-
- * Copyright 2009 Solarflare Communications Inc.  All rights reserved.
+ * Copyright (c) 2009-2015 Solarflare Communications Inc.
+ * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
+ * modification, are permitted provided that the following conditions are met:
  *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are
+ * those of the authors and should not be interpreted as representing official
+ * policies, either expressed or implied, of the FreeBSD Project.
  *
  * $FreeBSD$
  */
@@ -36,10 +41,15 @@
 extern "C" {
 #endif
 
-/* Number of retries attempted for init code */
-#define	EFX_MCDI_REQ_RETRY_INIT 2
+/*
+ * A reboot/assertion causes the MCDI status word to be set after the
+ * command word is set or a REBOOT event is sent. If we notice a reboot
+ * via these mechanisms then wait 10ms for the status word to be set.
+ */
+#define	EFX_MCDI_STATUS_SLEEP_US	10000
 
 struct efx_mcdi_req_s {
+	boolean_t	emr_quiet;
 	/* Inputs: Command #, input buffer and length */
 	unsigned int	emr_cmd;
 	uint8_t		*emr_in_buf;
@@ -52,19 +62,25 @@ struct efx_mcdi_req_s {
 };
 
 typedef struct efx_mcdi_iface_s {
-	const efx_mcdi_transport_t *emi_mtp;
 	unsigned int		emi_port;
 	unsigned int		emi_seq;
 	efx_mcdi_req_t		*emi_pending_req;
 	boolean_t		emi_ev_cpl;
+	boolean_t		emi_new_epoch;
 	int			emi_aborted;
 	uint32_t		emi_poll_cnt;
+	uint32_t		emi_mc_reboot_status;
 } efx_mcdi_iface_t;
 
 extern			void
 efx_mcdi_execute(
 	__in		efx_nic_t *enp,
-	__in		efx_mcdi_req_t *emrp);
+	__inout		efx_mcdi_req_t *emrp);
+
+extern			void
+efx_mcdi_execute_quiet(
+	__in		efx_nic_t *enp,
+	__inout		efx_mcdi_req_t *emrp);
 
 extern			void
 efx_mcdi_ev_cpl(
@@ -78,6 +94,16 @@ efx_mcdi_ev_death(
 	__in		efx_nic_t *enp,
 	__in		int rc);
 
+extern	__checkReturn	int
+efx_mcdi_request_errcode(
+	__in		unsigned int err);
+
+extern			void
+efx_mcdi_raise_exception(
+	__in		efx_nic_t *enp,
+	__in_opt	efx_mcdi_req_t *emrp,
+	__in		int rc);
+
 typedef enum efx_mcdi_boot_e {
 	EFX_MCDI_BOOT_PRIMARY,
 	EFX_MCDI_BOOT_SECONDARY,
@@ -91,6 +117,86 @@ efx_mcdi_version(
 	__out_opt		uint32_t *buildp,
 	__out_opt		efx_mcdi_boot_t *statusp);
 
+extern	__checkReturn		int
+efx_mcdi_read_assertion(
+	__in			efx_nic_t *enp);
+
+extern	__checkReturn		int
+efx_mcdi_exit_assertion_handler(
+	__in			efx_nic_t *enp);
+
+extern	__checkReturn		int
+efx_mcdi_drv_attach(
+	__in			efx_nic_t *enp,
+	__in			boolean_t attach);
+
+extern	__checkReturn		int
+efx_mcdi_get_board_cfg(
+	__in			efx_nic_t *enp,
+	__out_opt		uint32_t *board_typep,
+	__out_opt		efx_dword_t *capabilitiesp,
+	__out_ecount_opt(6)	uint8_t mac_addrp[6]);
+
+extern	__checkReturn		int
+efx_mcdi_get_phy_cfg(
+	__in			efx_nic_t *enp);
+
+extern	__checkReturn		int
+efx_mcdi_firmware_update_supported(
+	__in			efx_nic_t *enp,
+	__out			boolean_t *supportedp);
+
+extern	__checkReturn		int
+efx_mcdi_macaddr_change_supported(
+	__in			efx_nic_t *enp,
+	__out			boolean_t *supportedp);
+
+#if EFSYS_OPT_BIST
+#if EFSYS_OPT_HUNTINGTON
+extern	__checkReturn		int
+efx_mcdi_bist_enable_offline(
+	__in			efx_nic_t *enp);
+#endif /* EFSYS_OPT_HUNTINGTON */
+extern	__checkReturn		int
+efx_mcdi_bist_start(
+	__in			efx_nic_t *enp,
+	__in			efx_bist_type_t type);
+#endif /* EFSYS_OPT_BIST */
+
+extern	__checkReturn		int
+efx_mcdi_get_resource_limits(
+	__in			efx_nic_t *enp,
+	__out_opt		uint32_t *nevqp,
+	__out_opt		uint32_t *nrxqp,
+	__out_opt		uint32_t *ntxqp);
+
+extern	__checkReturn	int
+efx_mcdi_log_ctrl(
+	__in		efx_nic_t *enp);
+
+extern	__checkReturn	int
+efx_mcdi_mac_stats_clear(
+	__in		efx_nic_t *enp);
+
+extern	__checkReturn	int
+efx_mcdi_mac_stats_upload(
+	__in		efx_nic_t *enp,
+	__in		efsys_mem_t *esmp);
+
+extern	__checkReturn	int
+efx_mcdi_mac_stats_periodic(
+	__in		efx_nic_t *enp,
+	__in		efsys_mem_t *esmp,
+	__in		uint16_t period,
+	__in		boolean_t events);
+
+
+#if EFSYS_OPT_LOOPBACK
+extern	__checkReturn	int
+efx_mcdi_get_loopback_modes(
+	__in		efx_nic_t *enp);
+#endif /* EFSYS_OPT_LOOPBACK */
+
 #define	MCDI_IN(_emr, _type, _ofst)					\
 	((_type *)((_emr).emr_in_buf + (_ofst)))
 
@@ -101,10 +207,18 @@ efx_mcdi_version(
 	EFX_POPULATE_BYTE_1(*MCDI_IN2(_emr, efx_byte_t, _ofst),		\
 		EFX_BYTE_0, _value)
 
+#define	MCDI_IN_SET_WORD(_emr, _ofst, _value)				\
+	EFX_POPULATE_WORD_1(*MCDI_IN2(_emr, efx_word_t, _ofst),		\
+		EFX_WORD_0, _value)
+
 #define	MCDI_IN_SET_DWORD(_emr, _ofst, _value)				\
 	EFX_POPULATE_DWORD_1(*MCDI_IN2(_emr, efx_dword_t, _ofst),	\
 		EFX_DWORD_0, _value)
 
+#define	MCDI_IN_SET_DWORD_FIELD(_emr, _ofst, _field, _value)		\
+	EFX_SET_DWORD_FIELD(*MCDI_IN2(_emr, efx_dword_t, _ofst),	\
+		MC_CMD_ ## _field, _value)
+
 #define	MCDI_IN_POPULATE_DWORD_1(_emr, _ofst, _field1, _value1)		\
 	EFX_POPULATE_DWORD_1(*MCDI_IN2(_emr, efx_dword_t, _ofst),	\
 		MC_CMD_ ## _field1, _value1)
@@ -154,7 +268,7 @@ efx_mcdi_version(
 #define	MCDI_IN_POPULATE_DWORD_7(_emr, _ofst, _field1, _value1,		\
 		_field2, _value2, _field3, _value3, _field4, _value4,	\
 		_field5, _value5, _field6, _value6, _field7, _value7)	\
-	EFX_POPULATE_DWORD_7(MCDI_IN2(_emr, efx_dword_t, _ofst),	\
+	EFX_POPULATE_DWORD_7(*MCDI_IN2(_emr, efx_dword_t, _ofst),	\
 		MC_CMD_ ## _field1, _value1,				\
 		MC_CMD_ ## _field2, _value2,				\
 		MC_CMD_ ## _field3, _value3,				\
@@ -233,7 +347,7 @@ efx_mcdi_version(
 #define	MCDI_EV_FIELD(_eqp, _field)					\
 	EFX_QWORD_FIELD(*_eqp, MCDI_EVENT_ ## _field)
 
-#define MCDI_CMD_DWORD_FIELD(_edp, _field)				\
+#define	MCDI_CMD_DWORD_FIELD(_edp, _field)				\
 	EFX_DWORD_FIELD(*_edp, MC_CMD_ ## _field)
 
 #ifdef	__cplusplus
diff --git a/sys/dev/sfxge/common/efx_mon.c b/sys/dev/sfxge/common/efx_mon.c
index dc2e25603e7e..c5b356d687a9 100644
--- a/sys/dev/sfxge/common/efx_mon.c
+++ b/sys/dev/sfxge/common/efx_mon.c
@@ -1,26 +1,31 @@
 /*-
- * Copyright 2007-2009 Solarflare Communications Inc.  All rights reserved.
+ * Copyright (c) 2007-2015 Solarflare Communications Inc.
+ * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
+ * modification, are permitted provided that the following conditions are met:
  *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are
+ * those of the authors and should not be interpreted as representing official
+ * policies, either expressed or implied, of the FreeBSD Project.
  */
 
 #include <sys/cdefs.h>
@@ -44,17 +49,22 @@ __FBSDID("$FreeBSD$");
 #include "max6647.h"
 #endif
 
+#if EFSYS_OPT_MON_MCDI
+#include "mcdi_mon.h"
+#endif
+
 #if EFSYS_OPT_NAMES
 
-static const char	__cs * __cs __efx_mon_name[] = {
+static const char	*__efx_mon_name[] = {
 	"",
 	"nullmon",
 	"lm87",
 	"max6647",
-	"sfx90x0"
+	"sfx90x0",
+	"sfx91x0"
 };
 
-		const char __cs *
+		const char *
 efx_mon_name(
 	__in	efx_nic_t *enp)
 {
@@ -70,47 +80,46 @@ efx_mon_name(
 #endif	/* EFSYS_OPT_NAMES */
 
 #if EFSYS_OPT_MON_NULL
-static efx_mon_ops_t	__cs __efx_mon_null_ops = {
+static efx_mon_ops_t	__efx_mon_null_ops = {
 	nullmon_reset,			/* emo_reset */
 	nullmon_reconfigure,		/* emo_reconfigure */
 #if EFSYS_OPT_MON_STATS
-	nullmon_stats_update		/* emo_stat_update */
+	nullmon_stats_update		/* emo_stats_update */
 #endif	/* EFSYS_OPT_MON_STATS */
 };
 #endif
 
 #if EFSYS_OPT_MON_LM87
-static efx_mon_ops_t	__cs __efx_mon_lm87_ops = {
+static efx_mon_ops_t	__efx_mon_lm87_ops = {
 	lm87_reset,			/* emo_reset */
 	lm87_reconfigure,		/* emo_reconfigure */
 #if EFSYS_OPT_MON_STATS
-	lm87_stats_update		/* emo_stat_update */
+	lm87_stats_update		/* emo_stats_update */
 #endif	/* EFSYS_OPT_MON_STATS */
 };
 #endif
 
 #if EFSYS_OPT_MON_MAX6647
-static efx_mon_ops_t	__cs __efx_mon_max6647_ops = {
+static efx_mon_ops_t	__efx_mon_max6647_ops = {
 	max6647_reset,			/* emo_reset */
 	max6647_reconfigure,		/* emo_reconfigure */
 #if EFSYS_OPT_MON_STATS
-	max6647_stats_update		/* emo_stat_update */
+	max6647_stats_update		/* emo_stats_update */
 #endif	/* EFSYS_OPT_MON_STATS */
 };
 #endif
 
-#if EFSYS_OPT_MON_SIENA
-static efx_mon_ops_t	__cs __efx_mon_siena_ops = {
-	siena_mon_reset,		/* emo_reset */
-	siena_mon_reconfigure,		/* emo_reconfigure */
+#if EFSYS_OPT_MON_MCDI
+static efx_mon_ops_t	__efx_mon_mcdi_ops = {
+	NULL,				/* emo_reset */
+	NULL,				/* emo_reconfigure */
 #if EFSYS_OPT_MON_STATS
-	siena_mon_stats_update		/* emo_stat_update */
+	mcdi_mon_stats_update		/* emo_stats_update */
 #endif	/* EFSYS_OPT_MON_STATS */
 };
 #endif
 
-
-static efx_mon_ops_t	__cs * __cs __efx_mon_ops[] = {
+static efx_mon_ops_t	*__efx_mon_ops[] = {
 	NULL,
 #if EFSYS_OPT_MON_NULL
 	&__efx_mon_null_ops,
@@ -127,8 +136,13 @@ static efx_mon_ops_t	__cs * __cs __efx_mon_ops[] = {
 #else
 	NULL,
 #endif
-#if EFSYS_OPT_MON_SIENA
-	&__efx_mon_siena_ops
+#if EFSYS_OPT_MON_MCDI
+	&__efx_mon_mcdi_ops,
+#else
+	NULL,
+#endif
+#if EFSYS_OPT_MON_MCDI
+	&__efx_mon_mcdi_ops
 #else
 	NULL
 #endif
@@ -162,11 +176,15 @@ efx_mon_init(
 		goto fail2;
 	}
 
-	if ((rc = emop->emo_reset(enp)) != 0)
-		goto fail3;
+	if (emop->emo_reset != NULL) {
+		if ((rc = emop->emo_reset(enp)) != 0)
+			goto fail3;
+	}
 
-	if ((rc = emop->emo_reconfigure(enp)) != 0)
-		goto fail4;
+	if (emop->emo_reconfigure != NULL) {
+		if ((rc = emop->emo_reconfigure(enp)) != 0)
+			goto fail4;
+	}
 
 	emp->em_emop = emop;
 	return (0);
@@ -174,7 +192,8 @@ efx_mon_init(
 fail4:
 	EFSYS_PROBE(fail5);
 
-	(void) emop->emo_reset(enp);
+	if (emop->emo_reset != NULL)
+		(void) emop->emo_reset(enp);
 
 fail3:
 	EFSYS_PROBE(fail4);
@@ -195,8 +214,8 @@ fail1:
 
 #if EFSYS_OPT_NAMES
 
-/* START MKCONFIG GENERATED MonitorStatNamesBlock 89ff37f1d74ad8b3 */
-static const char 	__cs * __cs __mon_stat_name[] = {
+/* START MKCONFIG GENERATED MonitorStatNamesBlock b9328f15438c4d01 */
+static const char 	*__mon_stat_name[] = {
 	"value_2_5v",
 	"value_vccp1",
 	"value_vcc",
@@ -227,11 +246,50 @@ static const char 	__cs * __cs __mon_stat_name[] = {
 	"vaoe_in",
 	"iaoe",
 	"iaoe_in",
+	"nic_power",
+	"0_9v",
+	"i0_9v",
+	"i1_2v",
+	"0_9v_adc",
+	"controller_temperature2",
+	"vreg_temperature",
+	"vreg_0_9v_temperature",
+	"vreg_1_2v_temperature",
+	"int_vptat",
+	"controller_internal_adc_temperature",
+	"ext_vptat",
+	"controller_external_adc_temperature",
+	"ambient_temperature",
+	"airflow",
+	"vdd08d_vss08d_csr",
+	"vdd08d_vss08d_csr_extadc",
+	"hotpoint_temperature",
+	"phy_power_switch_port0",
+	"phy_power_switch_port1",
+	"mum_vcc",
+	"0v9_a",
+	"i0v9_a",
+	"0v9_a_temp",
+	"0v9_b",
+	"i0v9_b",
+	"0v9_b_temp",
+	"ccom_avreg_1v2_supply",
+	"ccom_avreg_1v2_supply_ext_adc",
+	"ccom_avreg_1v8_supply",
+	"ccom_avreg_1v8_supply_ext_adc",
+	"controller_master_vptat",
+	"controller_master_internal_temp",
+	"controller_master_vptat_ext_adc",
+	"controller_master_internal_temp_ext_adc",
+	"controller_slave_vptat",
+	"controller_slave_internal_temp",
+	"controller_slave_vptat_ext_adc",
+	"controller_slave_internal_temp_ext_adc",
 };
 
 /* END MKCONFIG GENERATED MonitorStatNamesBlock */
 
-extern					const char __cs *
+extern					const char *
 efx_mon_stat_name(
 	__in				efx_nic_t *enp,
 	__in				efx_mon_stat_t id)
@@ -276,9 +334,11 @@ efx_mon_fini(
 
 	emp->em_emop = NULL;
 
-	rc = emop->emo_reset(enp);
-	if (rc != 0)
-		EFSYS_PROBE1(fail1, int, rc);
+	if (emop->emo_reset != NULL) {
+		rc = emop->emo_reset(enp);
+		if (rc != 0)
+			EFSYS_PROBE1(fail1, int, rc);
+	}
 
 	emp->em_type = EFX_MON_INVALID;
 
diff --git a/sys/dev/sfxge/common/efx_nic.c b/sys/dev/sfxge/common/efx_nic.c
index b0ba58ccfc7a..b5ad65ead44c 100644
--- a/sys/dev/sfxge/common/efx_nic.c
+++ b/sys/dev/sfxge/common/efx_nic.c
@@ -1,26 +1,31 @@
 /*-
- * Copyright 2007-2009 Solarflare Communications Inc.  All rights reserved.
+ * Copyright (c) 2007-2015 Solarflare Communications Inc.
+ * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
+ * modification, are permitted provided that the following conditions are met:
  *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are
+ * those of the authors and should not be interpreted as representing official
+ * policies, either expressed or implied, of the FreeBSD Project.
  */
 
 #include <sys/cdefs.h>
@@ -38,27 +43,55 @@ efx_family(
 	__in		uint16_t devid,
 	__out		efx_family_t *efp)
 {
+	if (venid == EFX_PCI_VENID_SFC) {
+		switch (devid) {
 #if EFSYS_OPT_FALCON
-	if (venid == EFX_PCI_VENID_SFC && devid == EFX_PCI_DEVID_FALCON) {
-		*efp = EFX_FAMILY_FALCON;
-		return (0);
-	}
+		case EFX_PCI_DEVID_FALCON:
+			*efp = EFX_FAMILY_FALCON;
+			return (0);
 #endif
 #if EFSYS_OPT_SIENA
-	if (venid == EFX_PCI_VENID_SFC && devid == EFX_PCI_DEVID_BETHPAGE) {
-		*efp = EFX_FAMILY_SIENA;
-		return (0);
-	}
-	if (venid == EFX_PCI_VENID_SFC && devid == EFX_PCI_DEVID_SIENA) {
-		*efp = EFX_FAMILY_SIENA;
-		return (0);
-	}
-	if (venid == EFX_PCI_VENID_SFC &&
-	    devid == EFX_PCI_DEVID_SIENA_F1_UNINIT) {
-		*efp = EFX_FAMILY_SIENA;
-		return (0);
-	}
+		case EFX_PCI_DEVID_SIENA_F1_UNINIT:
+			/*
+			 * Hardware default for PF0 of uninitialised Siena.
+			 * manftest must be able to cope with this device id.
+			 */
+			*efp = EFX_FAMILY_SIENA;
+			return (0);
+
+		case EFX_PCI_DEVID_BETHPAGE:
+		case EFX_PCI_DEVID_SIENA:
+			*efp = EFX_FAMILY_SIENA;
+			return (0);
+#endif
+
+#if EFSYS_OPT_HUNTINGTON
+		case EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT:
+			/*
+			 * Hardware default for PF0 of uninitialised Huntington.
+			 * manftest must be able to cope with this device id.
+			 */
+			*efp = EFX_FAMILY_HUNTINGTON;
+			return (0);
+
+		case EFX_PCI_DEVID_FARMINGDALE:
+		case EFX_PCI_DEVID_GREENPORT:
+		case EFX_PCI_DEVID_HUNTINGTON:
+			*efp = EFX_FAMILY_HUNTINGTON;
+			return (0);
+
+		case EFX_PCI_DEVID_FARMINGDALE_VF:
+		case EFX_PCI_DEVID_GREENPORT_VF:
+		case EFX_PCI_DEVID_HUNTINGTON_VF:
+			*efp = EFX_FAMILY_HUNTINGTON;
+			return (0);
 #endif
+		default:
+			break;
+		}
+	}
+
+	*efp = EFX_FAMILY_INVALID;
 	return (ENOTSUP);
 }
 
@@ -80,11 +113,28 @@ efx_infer_family(
 	EFSYS_BAR_READO(esbp, FR_AZ_CS_DEBUG_REG_OFST, &oword, B_TRUE);
 	portnum = EFX_OWORD_FIELD(oword, FRF_CZ_CS_PORT_NUM);
 	switch (portnum) {
+	case 0: {
+		efx_dword_t dword;
+		uint32_t hw_rev;
+
+		EFSYS_BAR_READD(esbp, ER_DZ_BIU_HW_REV_ID_REG_OFST, &dword,
+		    B_TRUE);
+		hw_rev = EFX_DWORD_FIELD(dword, ERF_DZ_HW_REV_ID);
+		if (hw_rev == ER_DZ_BIU_HW_REV_ID_REG_RESET) {
+#if EFSYS_OPT_HUNTINGTON
+			family = EFX_FAMILY_HUNTINGTON;
+			break;
+#endif
+		} else {
 #if EFSYS_OPT_FALCON
-	case 0:
-		family = EFX_FAMILY_FALCON;
-		break;
+			family = EFX_FAMILY_FALCON;
+			break;
 #endif
+		}
+		rc = ENOTSUP;
+		goto fail1;
+	}
+
 #if EFSYS_OPT_SIENA
 	case 1:
 	case 2:
@@ -106,15 +156,10 @@ fail1:
 	return (rc);
 }
 
-/*
- * The built-in default value device id for port 1 of Siena is 0x0810.
- * manftest needs to be able to cope with that.
- */
-
 #define	EFX_BIU_MAGIC0	0x01234567
 #define	EFX_BIU_MAGIC1	0xfedcba98
 
-static	__checkReturn	int
+	__checkReturn	int
 efx_nic_biu_test(
 	__in		efx_nic_t *enp)
 {
@@ -128,18 +173,18 @@ efx_nic_biu_test(
 	 * back the cached value that was last written.
 	 */
 	EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC0);
-	EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 0, &oword);
+	EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
 
 	EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC1);
-	EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 1, &oword);
+	EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
 
-	EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 0, &oword);
+	EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
 	if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC0) {
 		rc = EIO;
 		goto fail1;
 	}
 
-	EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 1, &oword);
+	EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
 	if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC1) {
 		rc = EIO;
 		goto fail2;
@@ -151,18 +196,18 @@ efx_nic_biu_test(
 	 * values already written into the scratch registers.
 	 */
 	EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC1);
-	EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 0, &oword);
+	EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
 
 	EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC0);
-	EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 1, &oword);
+	EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
 
-	EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 0, &oword);
+	EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
 	if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC1) {
 		rc = EIO;
 		goto fail3;
 	}
 
-	EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 1, &oword);
+	EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
 	if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC0) {
 		rc = EIO;
 		goto fail4;
@@ -184,10 +229,13 @@ fail1:
 
 #if EFSYS_OPT_FALCON
 
-static efx_nic_ops_t	__cs __efx_nic_falcon_ops = {
+static efx_nic_ops_t	__efx_nic_falcon_ops = {
 	falcon_nic_probe,		/* eno_probe */
+	NULL,				/* eno_set_drv_limits */
 	falcon_nic_reset,		/* eno_reset */
 	falcon_nic_init,		/* eno_init */
+	NULL,				/* eno_get_vi_pool */
+	NULL,				/* eno_get_bar_region */
 #if EFSYS_OPT_DIAG
 	falcon_sram_test,		/* eno_sram_test */
 	falcon_nic_register_test,	/* eno_register_test */
@@ -200,10 +248,13 @@ static efx_nic_ops_t	__cs __efx_nic_falcon_ops = {
 
 #if EFSYS_OPT_SIENA
 
-static efx_nic_ops_t	__cs __efx_nic_siena_ops = {
+static efx_nic_ops_t	__efx_nic_siena_ops = {
 	siena_nic_probe,		/* eno_probe */
+	NULL,				/* eno_set_drv_limits */
 	siena_nic_reset,		/* eno_reset */
 	siena_nic_init,			/* eno_init */
+	NULL,				/* eno_get_vi_pool */
+	NULL,				/* eno_get_bar_region */
 #if EFSYS_OPT_DIAG
 	siena_sram_test,		/* eno_sram_test */
 	siena_nic_register_test,	/* eno_register_test */
@@ -214,6 +265,25 @@ static efx_nic_ops_t	__cs __efx_nic_siena_ops = {
 
 #endif	/* EFSYS_OPT_SIENA */
 
+#if EFSYS_OPT_HUNTINGTON
+
+static efx_nic_ops_t	__efx_nic_hunt_ops = {
+	hunt_nic_probe,			/* eno_probe */
+	hunt_nic_set_drv_limits,	/* eno_set_drv_limits */
+	hunt_nic_reset,			/* eno_reset */
+	hunt_nic_init,			/* eno_init */
+	hunt_nic_get_vi_pool,		/* eno_get_vi_pool */
+	hunt_nic_get_bar_region,	/* eno_get_bar_region */
+#if EFSYS_OPT_DIAG
+	hunt_sram_test,			/* eno_sram_test */
+	hunt_nic_register_test,		/* eno_register_test */
+#endif	/* EFSYS_OPT_DIAG */
+	hunt_nic_fini,			/* eno_fini */
+	hunt_nic_unprobe,		/* eno_unprobe */
+};
+
+#endif	/* EFSYS_OPT_HUNTINGTON */
+
 	__checkReturn	int
 efx_nic_create(
 	__in		efx_family_t family,
@@ -257,10 +327,27 @@ efx_nic_create(
 		    EFX_FEATURE_WOL |
 		    EFX_FEATURE_MCDI |
 		    EFX_FEATURE_LOOKAHEAD_SPLIT |
-		    EFX_FEATURE_MAC_HEADER_FILTERS;
+		    EFX_FEATURE_MAC_HEADER_FILTERS |
+		    EFX_FEATURE_TX_SRC_FILTERS;
 		break;
 #endif	/* EFSYS_OPT_SIENA */
 
+#if EFSYS_OPT_HUNTINGTON
+	case EFX_FAMILY_HUNTINGTON:
+		enp->en_enop = (efx_nic_ops_t *)&__efx_nic_hunt_ops;
+		/* FIXME: Add WOL support */
+		enp->en_features =
+		    EFX_FEATURE_IPV6 |
+		    EFX_FEATURE_LINK_EVENTS |
+		    EFX_FEATURE_PERIODIC_MAC_STATS |
+		    EFX_FEATURE_MCDI |
+		    EFX_FEATURE_MAC_HEADER_FILTERS |
+		    EFX_FEATURE_MCDI_DMA |
+		    EFX_FEATURE_PIO_BUFFERS |
+		    EFX_FEATURE_FW_ASSISTED_TSO;
+		break;
+#endif	/* EFSYS_OPT_HUNTINGTON */
+
 	default:
 		rc = ENOTSUP;
 		goto fail2;
@@ -276,7 +363,7 @@ efx_nic_create(
 	return (0);
 
 fail2:
-	EFSYS_PROBE(fail3);
+	EFSYS_PROBE(fail2);
 
 	enp->en_magic = 0;
 
@@ -294,7 +381,6 @@ efx_nic_probe(
 	__in		efx_nic_t *enp)
 {
 	efx_nic_ops_t *enop;
-	efx_oword_t oword;
 	int rc;
 
 	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
@@ -303,36 +389,22 @@ efx_nic_probe(
 #endif	/* EFSYS_OPT_MCDI */
 	EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_PROBE));
 
-	/* Test BIU */
-	if ((rc = efx_nic_biu_test(enp)) != 0)
-		goto fail1;
-
-	/* Clear the region register */
-	EFX_POPULATE_OWORD_4(oword,
-	    FRF_AZ_ADR_REGION0, 0,
-	    FRF_AZ_ADR_REGION1, (1 << 16),
-	    FRF_AZ_ADR_REGION2, (2 << 16),
-	    FRF_AZ_ADR_REGION3, (3 << 16));
-	EFX_BAR_WRITEO(enp, FR_AZ_ADR_REGION_REG, &oword);
-
 	enop = enp->en_enop;
 	if ((rc = enop->eno_probe(enp)) != 0)
-		goto fail2;
+		goto fail1;
 
 	if ((rc = efx_phy_probe(enp)) != 0)
-		goto fail3;
+		goto fail2;
 
 	enp->en_mod_flags |= EFX_MOD_PROBE;
 
 	return (0);
 
-fail3:
-	EFSYS_PROBE(fail3);
+fail2:
+	EFSYS_PROBE(fail2);
 
 	enop->eno_unprobe(enp);
 
-fail2:
-	EFSYS_PROBE(fail2);
 fail1:
 	EFSYS_PROBE1(fail1, int, rc);
 
@@ -376,6 +448,105 @@ efx_nic_pcie_extended_sync(
 #endif	/* EFSYS_OPT_PCIE_TUNE */
 
 	__checkReturn	int
+efx_nic_set_drv_limits(
+	__inout		efx_nic_t *enp,
+	__in		efx_drv_limits_t *edlp)
+{
+	efx_nic_ops_t *enop = enp->en_enop;
+	int rc;
+
+	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
+	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
+
+	if (enop->eno_set_drv_limits != NULL) {
+		if ((rc = enop->eno_set_drv_limits(enp, edlp)) != 0)
+			goto fail1;
+	}
+
+	return (0);
+
+fail1:
+	EFSYS_PROBE1(fail1, int, rc);
+
+	return (rc);
+}
+
+	__checkReturn	int
+efx_nic_get_bar_region(
+	__in		efx_nic_t *enp,
+	__in		efx_nic_region_t region,
+	__out		uint32_t *offsetp,
+	__out		size_t *sizep)
+{
+	efx_nic_ops_t *enop = enp->en_enop;
+	int rc;
+
+	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
+	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
+	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
+
+	if (enop->eno_get_bar_region == NULL) {
+		rc = ENOTSUP;
+		goto fail1;
+	}
+	if ((rc = (enop->eno_get_bar_region)(enp,
+		    region, offsetp, sizep)) != 0) {
+		goto fail2;
+	}
+
+	return (0);
+
+fail2:
+	EFSYS_PROBE(fail2);
+
+fail1:
+	EFSYS_PROBE1(fail1, int, rc);
+
+	return (rc);
+}
+
+
+	__checkReturn	int
+efx_nic_get_vi_pool(
+	__in		efx_nic_t *enp,
+	__out		uint32_t *evq_countp,
+	__out		uint32_t *rxq_countp,
+	__out		uint32_t *txq_countp)
+{
+	efx_nic_ops_t *enop = enp->en_enop;
+	efx_nic_cfg_t *encp = &enp->en_nic_cfg;
+	int rc;
+
+	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
+	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
+	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
+
+	if (enop->eno_get_vi_pool != NULL) {
+		uint32_t vi_count = 0;
+
+		if ((rc = (enop->eno_get_vi_pool)(enp, &vi_count)) != 0)
+			goto fail1;
+
+		*evq_countp = vi_count;
+		*rxq_countp = vi_count;
+		*txq_countp = vi_count;
+	} else {
+		/* Use NIC limits as default value */
+		*evq_countp = encp->enc_evq_limit;
+		*rxq_countp = encp->enc_rxq_limit;
+		*txq_countp = encp->enc_txq_limit;
+	}
+
+	return (0);
+
+fail1:
+	EFSYS_PROBE1(fail1, int, rc);
+
+	return (rc);
+}
+
+
+	__checkReturn	int
 efx_nic_init(
 	__in		efx_nic_t *enp)
 {
@@ -679,3 +850,191 @@ fail1:
 }
 
 #endif	/* EFSYS_OPT_DIAG */
+
+#if EFSYS_OPT_LOOPBACK
+
+extern			void
+efx_loopback_mask(
+	__in	efx_loopback_kind_t loopback_kind,
+	__out	efx_qword_t *maskp)
+{
+	efx_qword_t mask;
+
+	EFSYS_ASSERT3U(loopback_kind, <, EFX_LOOPBACK_NKINDS);
+	EFSYS_ASSERT(maskp != NULL);
+
+	/* Assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespace agree */
+	EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_NONE == EFX_LOOPBACK_OFF);
+	EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_DATA == EFX_LOOPBACK_DATA);
+	EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMAC == EFX_LOOPBACK_GMAC);
+	EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGMII == EFX_LOOPBACK_XGMII);
+	EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGXS == EFX_LOOPBACK_XGXS);
+	EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI == EFX_LOOPBACK_XAUI);
+	EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMII == EFX_LOOPBACK_GMII);
+	EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SGMII == EFX_LOOPBACK_SGMII);
+	EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGBR == EFX_LOOPBACK_XGBR);
+	EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI == EFX_LOOPBACK_XFI);
+	EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI_FAR == EFX_LOOPBACK_XAUI_FAR);
+	EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMII_FAR == EFX_LOOPBACK_GMII_FAR);
+	EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SGMII_FAR == EFX_LOOPBACK_SGMII_FAR);
+	EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI_FAR == EFX_LOOPBACK_XFI_FAR);
+	EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GPHY == EFX_LOOPBACK_GPHY);
+	EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PHYXS == EFX_LOOPBACK_PHY_XS);
+	EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PCS == EFX_LOOPBACK_PCS);
+	EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PMAPMD == EFX_LOOPBACK_PMA_PMD);
+	EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XPORT == EFX_LOOPBACK_XPORT);
+	EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGMII_WS == EFX_LOOPBACK_XGMII_WS);
+	EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI_WS == EFX_LOOPBACK_XAUI_WS);
+	EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI_WS_FAR ==
+	    EFX_LOOPBACK_XAUI_WS_FAR);
+	EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI_WS_NEAR ==
+	    EFX_LOOPBACK_XAUI_WS_NEAR);
+	EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMII_WS == EFX_LOOPBACK_GMII_WS);
+	EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI_WS == EFX_LOOPBACK_XFI_WS);
+	EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI_WS_FAR ==
+	    EFX_LOOPBACK_XFI_WS_FAR);
+	EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PHYXS_WS == EFX_LOOPBACK_PHYXS_WS);
+	EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PMA_INT == EFX_LOOPBACK_PMA_INT);
+	EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SD_NEAR == EFX_LOOPBACK_SD_NEAR);
+	EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SD_FAR == EFX_LOOPBACK_SD_FAR);
+	EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PMA_INT_WS ==
+	    EFX_LOOPBACK_PMA_INT_WS);
+	EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SD_FEP2_WS ==
+	    EFX_LOOPBACK_SD_FEP2_WS);
+	EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SD_FEP1_5_WS ==
+	    EFX_LOOPBACK_SD_FEP1_5_WS);
+	EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SD_FEP_WS == EFX_LOOPBACK_SD_FEP_WS);
+	EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SD_FES_WS == EFX_LOOPBACK_SD_FES_WS);
+
+	/* Build bitmask of possible loopback types */
+	EFX_ZERO_QWORD(mask);
+
+	if ((loopback_kind == EFX_LOOPBACK_KIND_OFF) ||
+	    (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
+		EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_OFF);
+	}
+
+	if ((loopback_kind == EFX_LOOPBACK_KIND_MAC) ||
+	    (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
+		/*
+		 * The "MAC" grouping has historically been used by drivers to
+		 * mean loopbacks supported by on-chip hardware. Keep that
+		 * meaning here, and include on-chip PHY layer loopbacks.
+		 */
+		EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_DATA);
+		EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMAC);
+		EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGMII);
+		EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGXS);
+		EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XAUI);
+		EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMII);
+		EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SGMII);
+		EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGBR);
+		EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XFI);
+		EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XAUI_FAR);
+		EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMII_FAR);
+		EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SGMII_FAR);
+		EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XFI_FAR);
+		EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PMA_INT);
+		EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SD_NEAR);
+		EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SD_FAR);
+	}
+
+	if ((loopback_kind == EFX_LOOPBACK_KIND_PHY) ||
+	    (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
+		/*
+		 * The "PHY" grouping has historically been used by drivers to
+		 * mean loopbacks supported by off-chip hardware. Keep that
+		 * meaning here.
+		 */
+		EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GPHY);
+		EFX_SET_QWORD_BIT(mask,	EFX_LOOPBACK_PHY_XS);
+		EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PCS);
+		EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PMA_PMD);
+	}
+
+	*maskp = mask;
+}
+
+__checkReturn	int
+efx_mcdi_get_loopback_modes(
+	__in		efx_nic_t *enp)
+{
+	efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
+	efx_mcdi_req_t req;
+	uint8_t payload[MAX(MC_CMD_GET_LOOPBACK_MODES_IN_LEN,
+			    MC_CMD_GET_LOOPBACK_MODES_OUT_LEN)];
+	efx_qword_t mask;
+	efx_qword_t modes;
+	int rc;
+
+	(void) memset(payload, 0, sizeof (payload));
+	req.emr_cmd = MC_CMD_GET_LOOPBACK_MODES;
+	req.emr_in_buf = payload;
+	req.emr_in_length = MC_CMD_GET_LOOPBACK_MODES_IN_LEN;
+	req.emr_out_buf = payload;
+	req.emr_out_length = MC_CMD_GET_LOOPBACK_MODES_OUT_LEN;
+
+	efx_mcdi_execute(enp, &req);
+
+	if (req.emr_rc != 0) {
+		rc = req.emr_rc;
+		goto fail1;
+	}
+
+	if (req.emr_out_length_used <
+	    MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST +
+	    MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN) {
+		rc = EMSGSIZE;
+		goto fail2;
+	}
+
+	/*
+	 * We assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespaces agree
+	 * in efx_loopback_mask() and in siena_phy.c:siena_phy_get_link().
+	 */
+	efx_loopback_mask(EFX_LOOPBACK_KIND_ALL, &mask);
+
+	EFX_AND_QWORD(mask,
+	    *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_SUGGESTED));
+
+	modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_100M);
+	EFX_AND_QWORD(modes, mask);
+	encp->enc_loopback_types[EFX_LINK_100FDX] = modes;
+
+	modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_1G);
+	EFX_AND_QWORD(modes, mask);
+	encp->enc_loopback_types[EFX_LINK_1000FDX] = modes;
+
+	modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_10G);
+	EFX_AND_QWORD(modes, mask);
+	encp->enc_loopback_types[EFX_LINK_10000FDX] = modes;
+
+	if (req.emr_out_length_used >=
+	    MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST +
+	    MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN) {
+		/* Response includes 40G loopback modes */
+		modes =
+		    *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_40G);
+		EFX_AND_QWORD(modes, mask);
+		encp->enc_loopback_types[EFX_LINK_40000FDX] = modes;
+	}
+
+	EFX_ZERO_QWORD(modes);
+	EFX_SET_QWORD_BIT(modes, EFX_LOOPBACK_OFF);
+	EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_100FDX]);
+	EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_1000FDX]);
+	EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_10000FDX]);
+	EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_40000FDX]);
+	encp->enc_loopback_types[EFX_LINK_UNKNOWN] = modes;
+
+	return (0);
+
+fail2:
+	EFSYS_PROBE(fail2);
+fail1:
+	EFSYS_PROBE1(fail1, int, rc);
+
+	return (rc);
+}
+
+#endif /* EFSYS_OPT_LOOPBACK */
diff --git a/sys/dev/sfxge/common/efx_nvram.c b/sys/dev/sfxge/common/efx_nvram.c
index 2df9bb98b3ca..82bb1d9842f5 100644
--- a/sys/dev/sfxge/common/efx_nvram.c
+++ b/sys/dev/sfxge/common/efx_nvram.c
@@ -1,26 +1,31 @@
 /*-
- * Copyright 2009 Solarflare Communications Inc.  All rights reserved.
+ * Copyright (c) 2009-2015 Solarflare Communications Inc.
+ * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
+ * modification, are permitted provided that the following conditions are met:
  *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are
+ * those of the authors and should not be interpreted as representing official
+ * policies, either expressed or implied, of the FreeBSD Project.
  */
 
 #include <sys/cdefs.h>
@@ -36,7 +41,7 @@ __FBSDID("$FreeBSD$");
 
 #if EFSYS_OPT_FALCON
 
-static efx_nvram_ops_t	__cs	__efx_nvram_falcon_ops = {
+static efx_nvram_ops_t	__efx_nvram_falcon_ops = {
 #if EFSYS_OPT_DIAG
 	falcon_nvram_test,		/* envo_test */
 #endif	/* EFSYS_OPT_DIAG */
@@ -54,7 +59,7 @@ static efx_nvram_ops_t	__cs	__efx_nvram_falcon_ops = {
 
 #if EFSYS_OPT_SIENA
 
-static efx_nvram_ops_t	__cs	__efx_nvram_siena_ops = {
+static efx_nvram_ops_t	__efx_nvram_siena_ops = {
 #if EFSYS_OPT_DIAG
 	siena_nvram_test,		/* envo_test */
 #endif	/* EFSYS_OPT_DIAG */
@@ -70,6 +75,24 @@ static efx_nvram_ops_t	__cs	__efx_nvram_siena_ops = {
 
 #endif	/* EFSYS_OPT_SIENA */
 
+#if EFSYS_OPT_HUNTINGTON
+
+static efx_nvram_ops_t	__efx_nvram_hunt_ops = {
+#if EFSYS_OPT_DIAG
+	hunt_nvram_test,		/* envo_test */
+#endif	/* EFSYS_OPT_DIAG */
+	hunt_nvram_size,		/* envo_size */
+	hunt_nvram_get_version,		/* envo_get_version */
+	hunt_nvram_rw_start,		/* envo_rw_start */
+	hunt_nvram_read_chunk,		/* envo_read_chunk */
+	hunt_nvram_erase,		/* envo_erase */
+	hunt_nvram_write_chunk,		/* envo_write_chunk */
+	hunt_nvram_rw_finish,		/* envo_rw_finish */
+	hunt_nvram_set_version,		/* envo_set_version */
+};
+
+#endif	/* EFSYS_OPT_HUNTINGTON */
+
 	__checkReturn	int
 efx_nvram_init(
 	__in		efx_nic_t *enp)
@@ -94,6 +117,12 @@ efx_nvram_init(
 		break;
 #endif	/* EFSYS_OPT_SIENA */
 
+#if EFSYS_OPT_HUNTINGTON
+	case EFX_FAMILY_HUNTINGTON:
+		envop = (efx_nvram_ops_t *)&__efx_nvram_hunt_ops;
+		break;
+#endif	/* EFSYS_OPT_HUNTINGTON */
+
 	default:
 		EFSYS_ASSERT(0);
 		rc = ENOTSUP;
@@ -329,7 +358,7 @@ efx_nvram_rw_finish(
 efx_nvram_set_version(
 	__in			efx_nic_t *enp,
 	__in			efx_nvram_type_t type,
-	__out			uint16_t version[4])
+	__in_ecount(4)		uint16_t version[4])
 {
 	efx_nvram_ops_t *envop = enp->en_envop;
 	int rc;
@@ -373,3 +402,486 @@ efx_nvram_fini(
 }
 
 #endif	/* EFSYS_OPT_NVRAM */
+
+#if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
+
+/*
+ * Internal MCDI request handling
+ */
+
+	__checkReturn		int
+efx_mcdi_nvram_partitions(
+	__in			efx_nic_t *enp,
+	__out_bcount(size)	caddr_t data,
+	__in			size_t size,
+	__out			unsigned int *npartnp)
+{
+	efx_mcdi_req_t req;
+	uint8_t payload[MAX(MC_CMD_NVRAM_PARTITIONS_IN_LEN,
+			    MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX)];
+	unsigned int npartn;
+	int rc;
+
+	(void) memset(payload, 0, sizeof (payload));
+	req.emr_cmd = MC_CMD_NVRAM_PARTITIONS;
+	req.emr_in_buf = payload;
+	req.emr_in_length = MC_CMD_NVRAM_PARTITIONS_IN_LEN;
+	req.emr_out_buf = payload;
+	req.emr_out_length = MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX;
+
+	efx_mcdi_execute(enp, &req);
+
+	if (req.emr_rc != 0) {
+		rc = req.emr_rc;
+		goto fail1;
+	}
+
+	if (req.emr_out_length_used < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN) {
+		rc = EMSGSIZE;
+		goto fail2;
+	}
+	npartn = MCDI_OUT_DWORD(req, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS);
+
+	if (req.emr_out_length_used < MC_CMD_NVRAM_PARTITIONS_OUT_LEN(npartn)) {
+		rc = ENOENT;
+		goto fail3;
+	}
+
+	if (size < npartn * sizeof (uint32_t)) {
+		rc = ENOSPC;
+		goto fail3;
+	}
+
+	*npartnp = npartn;
+
+	memcpy(data,
+	    MCDI_OUT2(req, uint32_t, NVRAM_PARTITIONS_OUT_TYPE_ID),
+	    (npartn * sizeof (uint32_t)));
+
+	return (0);
+
+fail3:
+	EFSYS_PROBE(fail3);
+fail2:
+	EFSYS_PROBE(fail2);
+fail1:
+	EFSYS_PROBE1(fail1, int, rc);
+
+	return (rc);
+}
+
+	__checkReturn		int
+efx_mcdi_nvram_metadata(
+	__in			efx_nic_t *enp,
+	__in			uint32_t partn,
+	__out			uint32_t *subtypep,
+	__out_ecount(4)		uint16_t version[4],
+	__out_bcount_opt(size)	char *descp,
+	__in			size_t size)
+{
+	efx_mcdi_req_t req;
+	uint8_t payload[MAX(MC_CMD_NVRAM_METADATA_IN_LEN,
+			    MC_CMD_NVRAM_METADATA_OUT_LENMAX)];
+	int rc;
+
+	(void) memset(payload, 0, sizeof (payload));
+	req.emr_cmd = MC_CMD_NVRAM_METADATA;
+	req.emr_in_buf = payload;
+	req.emr_in_length = MC_CMD_NVRAM_METADATA_IN_LEN;
+	req.emr_out_buf = payload;
+	req.emr_out_length = MC_CMD_NVRAM_METADATA_OUT_LENMAX;
+
+	MCDI_IN_SET_DWORD(req, NVRAM_METADATA_IN_TYPE, partn);
+
+	efx_mcdi_execute(enp, &req);
+
+	if (req.emr_rc != 0) {
+		rc = req.emr_rc;
+		goto fail1;
+	}
+
+	if (req.emr_out_length_used < MC_CMD_NVRAM_METADATA_OUT_LENMIN) {
+		rc = EMSGSIZE;
+		goto fail2;
+	}
+
+	if (MCDI_OUT_DWORD_FIELD(req, NVRAM_METADATA_OUT_FLAGS,
+		NVRAM_METADATA_OUT_SUBTYPE_VALID)) {
+		*subtypep = MCDI_OUT_DWORD(req, NVRAM_METADATA_OUT_SUBTYPE);
+	} else {
+		*subtypep = 0;
+	}
+
+	if (MCDI_OUT_DWORD_FIELD(req, NVRAM_METADATA_OUT_FLAGS,
+		NVRAM_METADATA_OUT_VERSION_VALID)) {
+		version[0] = MCDI_OUT_WORD(req, NVRAM_METADATA_OUT_VERSION_W);
+		version[1] = MCDI_OUT_WORD(req, NVRAM_METADATA_OUT_VERSION_X);
+		version[2] = MCDI_OUT_WORD(req, NVRAM_METADATA_OUT_VERSION_Y);
+		version[3] = MCDI_OUT_WORD(req, NVRAM_METADATA_OUT_VERSION_Z);
+	} else {
+		version[0] = version[1] = version[2] = version[3] = 0;
+	}
+
+	if (MCDI_OUT_DWORD_FIELD(req, NVRAM_METADATA_OUT_FLAGS,
+		NVRAM_METADATA_OUT_DESCRIPTION_VALID)) {
+		/* Return optional descrition string */
+		if ((descp != NULL) && (size > 0)) {
+			size_t desclen;
+
+			descp[0] = '\0';
+			desclen = (req.emr_out_length_used
+			    - MC_CMD_NVRAM_METADATA_OUT_LEN(0));
+
+			EFSYS_ASSERT3U(desclen, <=,
+			    MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MAXNUM);
+
+			if (size < desclen) {
+				rc = ENOSPC;
+				goto fail3;
+			}
+
+			memcpy(descp, MCDI_OUT2(req, char,
+				NVRAM_METADATA_OUT_DESCRIPTION),
+			    desclen);
+
+			/* Ensure string is NUL terminated */
+			descp[desclen] = '\0';
+		}
+	}
+
+	return (0);
+
+fail3:
+	EFSYS_PROBE(fail3);
+fail2:
+	EFSYS_PROBE(fail2);
+fail1:
+	EFSYS_PROBE1(fail1, int, rc);
+
+	return (rc);
+}
+
+	__checkReturn		int
+efx_mcdi_nvram_info(
+	__in			efx_nic_t *enp,
+	__in			uint32_t partn,
+	__out_opt		size_t *sizep,
+	__out_opt		uint32_t *addressp,
+	__out_opt		uint32_t *erase_sizep)
+{
+	uint8_t payload[MAX(MC_CMD_NVRAM_INFO_IN_LEN,
+			    MC_CMD_NVRAM_INFO_OUT_LEN)];
+	efx_mcdi_req_t req;
+	int rc;
+
+	(void) memset(payload, 0, sizeof (payload));
+	req.emr_cmd = MC_CMD_NVRAM_INFO;
+	req.emr_in_buf = payload;
+	req.emr_in_length = MC_CMD_NVRAM_INFO_IN_LEN;
+	req.emr_out_buf = payload;
+	req.emr_out_length = MC_CMD_NVRAM_INFO_OUT_LEN;
+
+	MCDI_IN_SET_DWORD(req, NVRAM_INFO_IN_TYPE, partn);
+
+	efx_mcdi_execute_quiet(enp, &req);
+
+	if (req.emr_rc != 0) {
+		rc = req.emr_rc;
+		goto fail1;
+	}
+
+	if (req.emr_out_length_used < MC_CMD_NVRAM_INFO_OUT_LEN) {
+		rc = EMSGSIZE;
+		goto fail2;
+	}
+
+	if (sizep)
+		*sizep = MCDI_OUT_DWORD(req, NVRAM_INFO_OUT_SIZE);
+
+	if (addressp)
+		*addressp = MCDI_OUT_DWORD(req, NVRAM_INFO_OUT_PHYSADDR);
+
+	if (erase_sizep)
+		*erase_sizep = MCDI_OUT_DWORD(req, NVRAM_INFO_OUT_ERASESIZE);
+
+	return (0);
+
+fail2:
+	EFSYS_PROBE(fail2);
+fail1:
+	EFSYS_PROBE1(fail1, int, rc);
+
+	return (rc);
+}
+
+	__checkReturn		int
+efx_mcdi_nvram_update_start(
+	__in			efx_nic_t *enp,
+	__in			uint32_t partn)
+{
+	uint8_t payload[MAX(MC_CMD_NVRAM_UPDATE_START_IN_LEN,
+			    MC_CMD_NVRAM_UPDATE_START_OUT_LEN)];
+	efx_mcdi_req_t req;
+	int rc;
+
+	(void) memset(payload, 0, sizeof (payload));
+	req.emr_cmd = MC_CMD_NVRAM_UPDATE_START;
+	req.emr_in_buf = payload;
+	req.emr_in_length = MC_CMD_NVRAM_UPDATE_START_IN_LEN;
+	req.emr_out_buf = payload;
+	req.emr_out_length = MC_CMD_NVRAM_UPDATE_START_OUT_LEN;
+
+	MCDI_IN_SET_DWORD(req, NVRAM_UPDATE_START_IN_TYPE, partn);
+
+	efx_mcdi_execute(enp, &req);
+
+	if (req.emr_rc != 0) {
+		rc = req.emr_rc;
+		goto fail1;
+	}
+
+	return (0);
+
+fail1:
+	EFSYS_PROBE1(fail1, int, rc);
+
+	return (rc);
+}
+
+	__checkReturn		int
+efx_mcdi_nvram_read(
+	__in			efx_nic_t *enp,
+	__in			uint32_t partn,
+	__in			uint32_t offset,
+	__out_bcount(size)	caddr_t data,
+	__in			size_t size)
+{
+	efx_mcdi_req_t req;
+	uint8_t payload[MAX(MC_CMD_NVRAM_READ_IN_LEN,
+			    MC_CMD_NVRAM_READ_OUT_LENMAX)];
+	int rc;
+
+	if (size > MC_CMD_NVRAM_READ_OUT_LENMAX) {
+		rc = EINVAL;
+		goto fail1;
+	}
+
+	(void) memset(payload, 0, sizeof (payload));
+	req.emr_cmd = MC_CMD_NVRAM_READ;
+	req.emr_in_buf = payload;
+	req.emr_in_length = MC_CMD_NVRAM_READ_IN_LEN;
+	req.emr_out_buf = payload;
+	req.emr_out_length = MC_CMD_NVRAM_READ_OUT_LENMAX;
+
+	MCDI_IN_SET_DWORD(req, NVRAM_READ_IN_TYPE, partn);
+	MCDI_IN_SET_DWORD(req, NVRAM_READ_IN_OFFSET, offset);
+	MCDI_IN_SET_DWORD(req, NVRAM_READ_IN_LENGTH, size);
+
+	efx_mcdi_execute(enp, &req);
+
+	if (req.emr_rc != 0) {
+		rc = req.emr_rc;
+		goto fail1;
+	}
+
+	if (req.emr_out_length_used < MC_CMD_NVRAM_READ_OUT_LEN(size)) {
+		rc = EMSGSIZE;
+		goto fail2;
+	}
+
+	memcpy(data,
+	    MCDI_OUT2(req, uint8_t, NVRAM_READ_OUT_READ_BUFFER),
+	    size);
+
+	return (0);
+
+fail2:
+	EFSYS_PROBE(fail2);
+fail1:
+	EFSYS_PROBE1(fail1, int, rc);
+
+	return (rc);
+}
+
+	__checkReturn		int
+efx_mcdi_nvram_erase(
+	__in			efx_nic_t *enp,
+	__in			uint32_t partn,
+	__in			uint32_t offset,
+	__in			size_t size)
+{
+	efx_mcdi_req_t req;
+	uint8_t payload[MAX(MC_CMD_NVRAM_ERASE_IN_LEN,
+			    MC_CMD_NVRAM_ERASE_OUT_LEN)];
+	int rc;
+
+	(void) memset(payload, 0, sizeof (payload));
+	req.emr_cmd = MC_CMD_NVRAM_ERASE;
+	req.emr_in_buf = payload;
+	req.emr_in_length = MC_CMD_NVRAM_ERASE_IN_LEN;
+	req.emr_out_buf = payload;
+	req.emr_out_length = MC_CMD_NVRAM_ERASE_OUT_LEN;
+
+	MCDI_IN_SET_DWORD(req, NVRAM_ERASE_IN_TYPE, partn);
+	MCDI_IN_SET_DWORD(req, NVRAM_ERASE_IN_OFFSET, offset);
+	MCDI_IN_SET_DWORD(req, NVRAM_ERASE_IN_LENGTH, size);
+
+	efx_mcdi_execute(enp, &req);
+
+	if (req.emr_rc != 0) {
+		rc = req.emr_rc;
+		goto fail1;
+	}
+
+	return (0);
+
+fail1:
+	EFSYS_PROBE1(fail1, int, rc);
+
+	return (rc);
+}
+
+	__checkReturn		int
+efx_mcdi_nvram_write(
+	__in			efx_nic_t *enp,
+	__in			uint32_t partn,
+	__in			uint32_t offset,
+	__out_bcount(size)	caddr_t data,
+	__in			size_t size)
+{
+	efx_mcdi_req_t req;
+	uint8_t payload[MAX(MC_CMD_NVRAM_WRITE_IN_LENMAX,
+			    MC_CMD_NVRAM_WRITE_OUT_LEN)];
+	int rc;
+
+	if (size > MC_CMD_NVRAM_WRITE_IN_LENMAX) {
+		rc = EINVAL;
+		goto fail1;
+	}
+
+	(void) memset(payload, 0, sizeof (payload));
+	req.emr_cmd = MC_CMD_NVRAM_WRITE;
+	req.emr_in_buf = payload;
+	req.emr_in_length = MC_CMD_NVRAM_WRITE_IN_LEN(size);
+	req.emr_out_buf = payload;
+	req.emr_out_length = MC_CMD_NVRAM_WRITE_OUT_LEN;
+
+	MCDI_IN_SET_DWORD(req, NVRAM_WRITE_IN_TYPE, partn);
+	MCDI_IN_SET_DWORD(req, NVRAM_WRITE_IN_OFFSET, offset);
+	MCDI_IN_SET_DWORD(req, NVRAM_WRITE_IN_LENGTH, size);
+
+	memcpy(MCDI_IN2(req, uint8_t, NVRAM_WRITE_IN_WRITE_BUFFER),
+	    data, size);
+
+	efx_mcdi_execute(enp, &req);
+
+	if (req.emr_rc != 0) {
+		rc = req.emr_rc;
+		goto fail2;
+	}
+
+	return (0);
+
+fail2:
+	EFSYS_PROBE(fail2);
+fail1:
+	EFSYS_PROBE1(fail1, int, rc);
+
+	return (rc);
+}
+
+	__checkReturn		int
+efx_mcdi_nvram_update_finish(
+	__in			efx_nic_t *enp,
+	__in			uint32_t partn,
+	__in			boolean_t reboot)
+{
+	efx_mcdi_req_t req;
+	uint8_t payload[MAX(MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN,
+			    MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN)];
+	int rc;
+
+	(void) memset(payload, 0, sizeof (payload));
+	req.emr_cmd = MC_CMD_NVRAM_UPDATE_FINISH;
+	req.emr_in_buf = payload;
+	req.emr_in_length = MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN;
+	req.emr_out_buf = payload;
+	req.emr_out_length = MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN;
+
+	MCDI_IN_SET_DWORD(req, NVRAM_UPDATE_FINISH_IN_TYPE, partn);
+	MCDI_IN_SET_DWORD(req, NVRAM_UPDATE_FINISH_IN_REBOOT, reboot);
+
+	efx_mcdi_execute(enp, &req);
+
+	if (req.emr_rc != 0) {
+		rc = req.emr_rc;
+		goto fail1;
+	}
+
+	return (0);
+
+fail1:
+	EFSYS_PROBE1(fail1, int, rc);
+
+	return (rc);
+}
+
+#if EFSYS_OPT_DIAG
+
+	__checkReturn		int
+efx_mcdi_nvram_test(
+	__in			efx_nic_t *enp,
+	__in			uint32_t partn)
+{
+	efx_mcdi_req_t req;
+	uint8_t payload[MAX(MC_CMD_NVRAM_TEST_IN_LEN,
+			    MC_CMD_NVRAM_TEST_OUT_LEN)];
+	int result;
+	int rc;
+
+	(void) memset(payload, 0, sizeof (payload));
+	req.emr_cmd = MC_CMD_NVRAM_TEST;
+	req.emr_in_buf = payload;
+	req.emr_in_length = MC_CMD_NVRAM_TEST_IN_LEN;
+	req.emr_out_buf = payload;
+	req.emr_out_length = MC_CMD_NVRAM_TEST_OUT_LEN;
+
+	MCDI_IN_SET_DWORD(req, NVRAM_TEST_IN_TYPE, partn);
+
+	efx_mcdi_execute(enp, &req);
+
+	if (req.emr_rc != 0) {
+		rc = req.emr_rc;
+		goto fail1;
+	}
+
+	if (req.emr_out_length_used < MC_CMD_NVRAM_TEST_OUT_LEN) {
+		rc = EMSGSIZE;
+		goto fail2;
+	}
+
+	result = MCDI_OUT_DWORD(req, NVRAM_TEST_OUT_RESULT);
+	if (result == MC_CMD_NVRAM_TEST_FAIL) {
+
+		EFSYS_PROBE1(nvram_test_failure, int, partn);
+
+		rc = (EINVAL);
+		goto fail3;
+	}
+
+	return (0);
+
+fail3:
+	EFSYS_PROBE(fail3);
+fail2:
+	EFSYS_PROBE(fail2);
+fail1:
+	EFSYS_PROBE1(fail1, int, rc);
+
+	return (rc);
+}
+
+#endif	/* EFSYS_OPT_DIAG */
+
+
+#endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
diff --git a/sys/dev/sfxge/common/efx_phy.c b/sys/dev/sfxge/common/efx_phy.c
index bb34ea7bd99d..5d18dc70b97b 100644
--- a/sys/dev/sfxge/common/efx_phy.c
+++ b/sys/dev/sfxge/common/efx_phy.c
@@ -1,26 +1,31 @@
 /*-
- * Copyright 2007-2009 Solarflare Communications Inc.  All rights reserved.
+ * Copyright (c) 2007-2015 Solarflare Communications Inc.
+ * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
+ * modification, are permitted provided that the following conditions are met:
  *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are
+ * those of the authors and should not be interpreted as representing official
+ * policies, either expressed or implied, of the FreeBSD Project.
  */
 
 #include <sys/cdefs.h>
@@ -68,7 +73,7 @@ __FBSDID("$FreeBSD$");
 #endif
 
 #if EFSYS_OPT_PHY_NULL
-static efx_phy_ops_t	__cs __efx_phy_null_ops = {
+static efx_phy_ops_t	__efx_phy_null_ops = {
 	NULL,				/* epo_power */
 	nullphy_reset,			/* epo_reset */
 	nullphy_reconfigure,		/* epo_reconfigure */
@@ -86,16 +91,17 @@ static efx_phy_ops_t	__cs __efx_phy_null_ops = {
 	nullphy_prop_get,		/* epo_prop_get */
 	nullphy_prop_set,		/* epo_prop_set */
 #endif	/* EFSYS_OPT_PHY_PROPS */
-#if EFSYS_OPT_PHY_BIST
+#if EFSYS_OPT_BIST
+	NULL,				/* epo_bist_enable_offline */
 	NULL,				/* epo_bist_start */
 	NULL,				/* epo_bist_poll */
 	NULL,				/* epo_bist_stop */
-#endif	/* EFSYS_OPT_PHY_BIST */
+#endif	/* EFSYS_OPT_BIST */
 };
 #endif	/* EFSYS_OPT_PHY_NULL */
 
 #if EFSYS_OPT_PHY_QT2022C2
-static efx_phy_ops_t	__cs __efx_phy_qt2022c2_ops = {
+static efx_phy_ops_t	__efx_phy_qt2022c2_ops = {
 	NULL,				/* epo_power */
 	qt2022c2_reset,			/* epo_reset */
 	qt2022c2_reconfigure,		/* epo_reconfigure */
@@ -113,16 +119,17 @@ static efx_phy_ops_t	__cs __efx_phy_qt2022c2_ops = {
 	qt2022c2_prop_get,		/* epo_prop_get */
 	qt2022c2_prop_set,		/* epo_prop_set */
 #endif	/* EFSYS_OPT_PHY_PROPS */
-#if EFSYS_OPT_PHY_BIST
+#if EFSYS_OPT_BIST
+	NULL,				/* epo_bist_enable_offline */
 	NULL,				/* epo_bist_start */
 	NULL,				/* epo_bist_poll */
 	NULL,				/* epo_bist_stop */
-#endif	/* EFSYS_OPT_PHY_BIST */
+#endif	/* EFSYS_OPT_BIST */
 };
 #endif	/* EFSYS_OPT_PHY_QT2022C2 */
 
 #if EFSYS_OPT_PHY_SFX7101
-static efx_phy_ops_t	__cs __efx_phy_sfx7101_ops = {
+static efx_phy_ops_t	__efx_phy_sfx7101_ops = {
 	sfx7101_power,			/* epo_power */
 	sfx7101_reset,			/* epo_reset */
 	sfx7101_reconfigure,		/* epo_reconfigure */
@@ -140,16 +147,17 @@ static efx_phy_ops_t	__cs __efx_phy_sfx7101_ops = {
 	sfx7101_prop_get,		/* epo_prop_get */
 	sfx7101_prop_set,		/* epo_prop_set */
 #endif	/* EFSYS_OPT_PHY_PROPS */
-#if EFSYS_OPT_PHY_BIST
+#if EFSYS_OPT_BIST
+	NULL,				/* epo_bist_enable_offline */
 	NULL,				/* epo_bist_start */
 	NULL,				/* epo_bist_poll */
 	NULL,				/* epo_bist_stop */
-#endif	/* EFSYS_OPT_PHY_BIST */
+#endif	/* EFSYS_OPT_BIST */
 };
 #endif	/* EFSYS_OPT_PHY_SFX7101 */
 
 #if EFSYS_OPT_PHY_TXC43128
-static efx_phy_ops_t	__cs __efx_phy_txc43128_ops = {
+static efx_phy_ops_t	__efx_phy_txc43128_ops = {
 	NULL,				/* epo_power */
 	txc43128_reset,			/* epo_reset */
 	txc43128_reconfigure,		/* epo_reconfigure */
@@ -167,16 +175,17 @@ static efx_phy_ops_t	__cs __efx_phy_txc43128_ops = {
 	txc43128_prop_get,		/* epo_prop_get */
 	txc43128_prop_set,		/* epo_prop_set */
 #endif	/* EFSYS_OPT_PHY_PROPS */
-#if EFSYS_OPT_PHY_BIST
+#if EFSYS_OPT_BIST
+	NULL,				/* epo_bist_enable_offline */
 	NULL,				/* epo_bist_start */
 	NULL,				/* epo_bist_poll */
 	NULL,				/* epo_bist_stop */
-#endif	/* EFSYS_OPT_PHY_BIST */
+#endif	/* EFSYS_OPT_BIST */
 };
 #endif	/* EFSYS_OPT_PHY_TXC43128 */
 
 #if EFSYS_OPT_PHY_SFT9001
-static efx_phy_ops_t	__cs __efx_phy_sft9001_ops = {
+static efx_phy_ops_t	__efx_phy_sft9001_ops = {
 	NULL,				/* epo_power */
 	sft9001_reset,			/* epo_reset */
 	sft9001_reconfigure,		/* epo_reconfigure */
@@ -194,16 +203,17 @@ static efx_phy_ops_t	__cs __efx_phy_sft9001_ops = {
 	sft9001_prop_get,		/* epo_prop_get */
 	sft9001_prop_set,		/* epo_prop_set */
 #endif	/* EFSYS_OPT_PHY_PROPS */
-#if EFSYS_OPT_PHY_BIST
+#if EFSYS_OPT_BIST
+	NULL,				/* epo_bist_enable_offline */
 	sft9001_bist_start,		/* epo_bist_start */
 	sft9001_bist_poll,		/* epo_bist_poll */
 	sft9001_bist_stop,		/* epo_bist_stop */
-#endif	/* EFSYS_OPT_PHY_BIST */
+#endif	/* EFSYS_OPT_BIST */
 };
 #endif	/* EFSYS_OPT_PHY_SFT9001 */
 
 #if EFSYS_OPT_PHY_QT2025C
-static efx_phy_ops_t	__cs __efx_phy_qt2025c_ops = {
+static efx_phy_ops_t	__efx_phy_qt2025c_ops = {
 	NULL,				/* epo_power */
 	qt2025c_reset,			/* epo_reset */
 	qt2025c_reconfigure,		/* epo_reconfigure */
@@ -221,16 +231,17 @@ static efx_phy_ops_t	__cs __efx_phy_qt2025c_ops = {
 	qt2025c_prop_get,		/* epo_prop_get */
 	qt2025c_prop_set,		/* epo_prop_set */
 #endif	/* EFSYS_OPT_PHY_PROPS */
-#if EFSYS_OPT_PHY_BIST
+#if EFSYS_OPT_BIST
+	NULL,				/* epo_bist_enable_offline */
 	NULL,				/* epo_bist_start */
 	NULL,				/* epo_bist_poll */
 	NULL,				/* epo_bist_stop */
-#endif	/* EFSYS_OPT_PHY_BIST */
+#endif	/* EFSYS_OPT_BIST */
 };
 #endif	/* EFSYS_OPT_PHY_QT2025C */
 
 #if EFSYS_OPT_SIENA
-static efx_phy_ops_t	__cs __efx_phy_siena_ops = {
+static efx_phy_ops_t	__efx_phy_siena_ops = {
 	siena_phy_power,		/* epo_power */
 	NULL,				/* epo_reset */
 	siena_phy_reconfigure,		/* epo_reconfigure */
@@ -248,14 +259,43 @@ static efx_phy_ops_t	__cs __efx_phy_siena_ops = {
 	siena_phy_prop_get,		/* epo_prop_get */
 	siena_phy_prop_set,		/* epo_prop_set */
 #endif	/* EFSYS_OPT_PHY_PROPS */
-#if EFSYS_OPT_PHY_BIST
+#if EFSYS_OPT_BIST
+	NULL,				/* epo_bist_enable_offline */
 	siena_phy_bist_start, 		/* epo_bist_start */
 	siena_phy_bist_poll,		/* epo_bist_poll */
 	siena_phy_bist_stop,		/* epo_bist_stop */
-#endif	/* EFSYS_OPT_PHY_BIST */
+#endif	/* EFSYS_OPT_BIST */
 };
 #endif	/* EFSYS_OPT_SIENA */
 
+#if EFSYS_OPT_HUNTINGTON
+static efx_phy_ops_t	__efx_phy_hunt_ops = {
+	hunt_phy_power,			/* epo_power */
+	NULL,				/* epo_reset */
+	hunt_phy_reconfigure,		/* epo_reconfigure */
+	hunt_phy_verify,		/* epo_verify */
+	NULL,				/* epo_uplink_check */
+	NULL,				/* epo_downlink_check */
+	hunt_phy_oui_get,		/* epo_oui_get */
+#if EFSYS_OPT_PHY_STATS
+	hunt_phy_stats_update,		/* epo_stats_update */
+#endif	/* EFSYS_OPT_PHY_STATS */
+#if EFSYS_OPT_PHY_PROPS
+#if EFSYS_OPT_NAMES
+	hunt_phy_prop_name,		/* epo_prop_name */
+#endif
+	hunt_phy_prop_get,		/* epo_prop_get */
+	hunt_phy_prop_set,		/* epo_prop_set */
+#endif	/* EFSYS_OPT_PHY_PROPS */
+#if EFSYS_OPT_BIST
+	hunt_bist_enable_offline,	/* epo_bist_enable_offline */
+	hunt_bist_start,		/* epo_bist_start */
+	hunt_bist_poll,			/* epo_bist_poll */
+	hunt_bist_stop,			/* epo_bist_stop */
+#endif	/* EFSYS_OPT_BIST */
+};
+#endif	/* EFSYS_OPT_HUNTINGTON */
+
 	__checkReturn	int
 efx_phy_probe(
 	__in		efx_nic_t *enp)
@@ -317,6 +357,11 @@ efx_phy_probe(
 		epop = (efx_phy_ops_t *)&__efx_phy_siena_ops;
 		break;
 #endif	/* EFSYS_OPT_SIENA */
+#if EFSYS_OPT_HUNTINGTON
+	case EFX_FAMILY_HUNTINGTON:
+		epop = (efx_phy_ops_t *)&__efx_phy_hunt_ops;
+		break;
+#endif	/* EFSYS_OPT_HUNTINGTON */
 	default:
 		rc = ENOTSUP;
 		goto fail1;
@@ -516,8 +561,8 @@ efx_phy_media_type_get(
 
 #if EFSYS_OPT_NAMES
 
-/* START MKCONFIG GENERATED PhyStatNamesBlock 271268f3da0e804f */
-static const char 	__cs * __cs __efx_phy_stat_name[] = {
+/* START MKCONFIG GENERATED PhyStatNamesBlock d5f79b4bc2c050fe */
+static const char 	*__efx_phy_stat_name[] = {
 	"oui",
 	"pma_pmd_link_up",
 	"pma_pmd_rx_fault",
@@ -568,7 +613,7 @@ static const char 	__cs * __cs __efx_phy_stat_name[] = {
 
 /* END MKCONFIG GENERATED PhyStatNamesBlock */
 
-					const char __cs *
+					const char *
 efx_phy_stat_name(
 	__in				efx_nic_t *enp,
 	__in				efx_phy_stat_t type)
@@ -602,7 +647,7 @@ efx_phy_stats_update(
 #if EFSYS_OPT_PHY_PROPS
 
 #if EFSYS_OPT_NAMES
-		const char __cs *
+		const char *
 efx_phy_prop_name(
 	__in	efx_nic_t *enp,
 	__in	unsigned int id)
@@ -649,23 +694,51 @@ efx_phy_prop_set(
 }
 #endif	/* EFSYS_OPT_PHY_STATS */
 
-#if EFSYS_OPT_PHY_BIST
+#if EFSYS_OPT_BIST
+
+	__checkReturn		int
+efx_bist_enable_offline(
+	__in			efx_nic_t *enp)
+{
+	efx_port_t *epp = &(enp->en_port);
+	efx_phy_ops_t *epop = epp->ep_epop;
+	int rc;
+
+	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
+
+	if (epop->epo_bist_enable_offline == NULL) {
+		rc = ENOTSUP;
+		goto fail1;
+	}
+
+	if ((rc = epop->epo_bist_enable_offline(enp)) != 0)
+		goto fail2;
+
+	return (0);
+
+fail2:
+	EFSYS_PROBE(fail2);
+fail1:
+	EFSYS_PROBE1(fail1, int, rc);
+
+	return (rc);
+
+}
 
 	__checkReturn		int
-efx_phy_bist_start(
+efx_bist_start(
 	__in			efx_nic_t *enp,
-	__in			efx_phy_bist_type_t type)
+	__in			efx_bist_type_t type)
 {
 	efx_port_t *epp = &(enp->en_port);
 	efx_phy_ops_t *epop = epp->ep_epop;
 	int rc;
 
 	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
-	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
 
-	EFSYS_ASSERT3U(type, !=, EFX_PHY_BIST_TYPE_UNKNOWN);
-	EFSYS_ASSERT3U(type, <, EFX_PHY_BIST_TYPE_NTYPES);
-	EFSYS_ASSERT3U(epp->ep_current_bist, ==, EFX_PHY_BIST_TYPE_UNKNOWN);
+	EFSYS_ASSERT3U(type, !=, EFX_BIST_TYPE_UNKNOWN);
+	EFSYS_ASSERT3U(type, <, EFX_BIST_TYPE_NTYPES);
+	EFSYS_ASSERT3U(epp->ep_current_bist, ==, EFX_BIST_TYPE_UNKNOWN);
 
 	if (epop->epo_bist_start == NULL) {
 		rc = ENOTSUP;
@@ -688,10 +761,10 @@ fail1:
 }
 
 	__checkReturn		int
-efx_phy_bist_poll(
+efx_bist_poll(
 	__in			efx_nic_t *enp,
-	__in			efx_phy_bist_type_t type,
-	__out			efx_phy_bist_result_t *resultp,
+	__in			efx_bist_type_t type,
+	__out			efx_bist_result_t *resultp,
 	__out_opt		uint32_t *value_maskp,
 	__out_ecount_opt(count)	unsigned long *valuesp,
 	__in			size_t count)
@@ -701,10 +774,9 @@ efx_phy_bist_poll(
 	int rc;
 
 	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
-	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
 
-	EFSYS_ASSERT3U(type, !=, EFX_PHY_BIST_TYPE_UNKNOWN);
-	EFSYS_ASSERT3U(type, <, EFX_PHY_BIST_TYPE_NTYPES);
+	EFSYS_ASSERT3U(type, !=, EFX_BIST_TYPE_UNKNOWN);
+	EFSYS_ASSERT3U(type, <, EFX_BIST_TYPE_NTYPES);
 	EFSYS_ASSERT3U(epp->ep_current_bist, ==, type);
 
 	EFSYS_ASSERT(epop->epo_bist_poll != NULL);
@@ -728,18 +800,17 @@ fail1:
 }
 
 			void
-efx_phy_bist_stop(
+efx_bist_stop(
 	__in		efx_nic_t *enp,
-	__in		efx_phy_bist_type_t type)
+	__in		efx_bist_type_t type)
 {
 	efx_port_t *epp = &(enp->en_port);
 	efx_phy_ops_t *epop = epp->ep_epop;
 
 	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
-	EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
 
-	EFSYS_ASSERT3U(type, !=, EFX_PHY_BIST_TYPE_UNKNOWN);
-	EFSYS_ASSERT3U(type, <, EFX_PHY_BIST_TYPE_NTYPES);
+	EFSYS_ASSERT3U(type, !=, EFX_BIST_TYPE_UNKNOWN);
+	EFSYS_ASSERT3U(type, <, EFX_BIST_TYPE_NTYPES);
 	EFSYS_ASSERT3U(epp->ep_current_bist, ==, type);
 
 	EFSYS_ASSERT(epop->epo_bist_stop != NULL);
@@ -747,10 +818,10 @@ efx_phy_bist_stop(
 	if (epop->epo_bist_stop != NULL)
 		epop->epo_bist_stop(enp, type);
 
-	epp->ep_current_bist = EFX_PHY_BIST_TYPE_UNKNOWN;
+	epp->ep_current_bist = EFX_BIST_TYPE_UNKNOWN;
 }
 
-#endif	/* EFSYS_OPT_PHY_BIST */
+#endif	/* EFSYS_OPT_BIST */
 			void
 efx_phy_unprobe(
 	__in	efx_nic_t *enp)
diff --git a/sys/dev/sfxge/common/efx_phy_ids.h b/sys/dev/sfxge/common/efx_phy_ids.h
new file mode 100644
index 000000000000..e06251923938
--- /dev/null
+++ b/sys/dev/sfxge/common/efx_phy_ids.h
@@ -0,0 +1,53 @@
+/*-
+ * Copyright (c) 2013-2015 Solarflare Communications Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are
+ * those of the authors and should not be interpreted as representing official
+ * policies, either expressed or implied, of the FreeBSD Project.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef	_SYS_EFX_PHY_IDS_H
+#define	_SYS_EFX_PHY_IDS_H
+
+#define	EFX_PHY_NULL	0
+
+typedef enum efx_phy_type_e {			/* GENERATED BY scripts/genfwdef */
+	EFX_PHY_TXC43128 = 1,
+	EFX_PHY_SFX7101 = 3,
+	EFX_PHY_QT2022C2 = 4,
+	EFX_PHY_PM8358 = 6,
+	EFX_PHY_SFT9001A = 8,
+	EFX_PHY_QT2025C = 9,
+	EFX_PHY_SFT9001B = 10,
+	EFX_PHY_QLX111V = 12,
+	EFX_PHY_QT2025_KR = 17,
+	EFX_PHY_AEL3020 = 18,
+	EFX_PHY_XFI_FARMI = 19,
+} efx_phy_type_t;
+
+
+#endif	/* _SYS_EFX_PHY_IDS_H */
diff --git a/sys/dev/sfxge/common/efx_port.c b/sys/dev/sfxge/common/efx_port.c
index 0b67d065f2fb..a750c15edb3b 100644
--- a/sys/dev/sfxge/common/efx_port.c
+++ b/sys/dev/sfxge/common/efx_port.c
@@ -1,26 +1,31 @@
 /*-
- * Copyright 2009 Solarflare Communications Inc.  All rights reserved.
+ * Copyright (c) 2009-2015 Solarflare Communications Inc.
+ * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
+ * modification, are permitted provided that the following conditions are met:
  *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are
+ * those of the authors and should not be interpreted as representing official
+ * policies, either expressed or implied, of the FreeBSD Project.
  */
 
 #include <sys/cdefs.h>
@@ -61,6 +66,9 @@ efx_port_init(
 
 	epp->ep_emop->emo_reconfigure(enp);
 
+	/* Pick up current phy capababilities */
+	efx_port_poll(enp, NULL);
+
 	/*
 	 * Turn on the PHY if available, otherwise reset it, and
 	 * reconfigure it with the current configuration.
@@ -96,7 +104,7 @@ fail1:
 	__checkReturn	int
 efx_port_poll(
 	__in		efx_nic_t *enp,
-	__out		efx_link_mode_t	*link_modep)
+	__out_opt	efx_link_mode_t	*link_modep)
 {
 	efx_port_t *epp = &(enp->en_port);
 	efx_mac_ops_t *emop = epp->ep_emop;
@@ -141,7 +149,9 @@ efx_port_loopback_set(
 	EFSYS_ASSERT(emop != NULL);
 
 	EFSYS_ASSERT(link_mode < EFX_LINK_NMODES);
-	if ((1 << loopback_type) & ~encp->enc_loopback_types[link_mode]) {
+
+	if (EFX_TEST_QWORD_BIT(encp->enc_loopback_types[link_mode],
+		loopback_type) == 0) {
 		rc = ENOTSUP;
 		goto fail1;
 	}
@@ -165,7 +175,7 @@ fail1:
 
 #if EFSYS_OPT_NAMES
 
-static const char 	__cs * __cs __efx_loopback_type_name[] = {
+static const char 	*__efx_loopback_type_name[] = {
 	"OFF",
 	"DATA",
 	"GMAC",
@@ -184,13 +194,33 @@ static const char 	__cs * __cs __efx_loopback_type_name[] = {
 	"PHY_XS",
 	"PCS",
 	"PMA_PMD",
+	"XPORT",
+	"XGMII_WS",
+	"XAUI_WS",
+	"XAUI_WS_FAR",
+	"XAUI_WS_NEAR",
+	"GMII_WS",
+	"XFI_WS",
+	"XFI_WS_FAR",
+	"PHYXS_WS",
+	"PMA_INT",
+	"SD_NEAR",
+	"SD_FAR",
+	"PMA_INT_WS",
+	"SD_FEP2_WS",
+	"SD_FEP1_5_WS",
+	"SD_FEP_WS",
+	"SD_FES_WS",
 };
 
-	__checkReturn	const char __cs *
+	__checkReturn	const char *
 efx_loopback_type_name(
 	__in		efx_nic_t *enp,
 	__in		efx_loopback_type_t type)
 {
+	EFX_STATIC_ASSERT(EFX_ARRAY_SIZE(__efx_loopback_type_name) ==
+	    EFX_LOOPBACK_NTYPES);
+
 	_NOTE(ARGUNUSED(enp))
 	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 	EFSYS_ASSERT3U(type, <, EFX_LOOPBACK_NTYPES);
diff --git a/sys/dev/sfxge/common/efx_regs.h b/sys/dev/sfxge/common/efx_regs.h
index 4019663933cb..5ece431fe2ea 100644
--- a/sys/dev/sfxge/common/efx_regs.h
+++ b/sys/dev/sfxge/common/efx_regs.h
@@ -1,26 +1,31 @@
 /*-
- * Copyright 2007-2009 Solarflare Communications Inc.  All rights reserved.
+ * Copyright (c) 2007-2015 Solarflare Communications Inc.
+ * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
+ * modification, are permitted provided that the following conditions are met:
  *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are
+ * those of the authors and should not be interpreted as representing official
+ * policies, either expressed or implied, of the FreeBSD Project.
  *
  * $FreeBSD$
  */
@@ -3854,7 +3859,7 @@ extern "C" {
  */
 
 
-#define FR_AZ_TX_PACE_TBL_OFST FR_BZ_TX_PACE_TBL_OFST
+#define	FR_AZ_TX_PACE_TBL_OFST FR_BZ_TX_PACE_TBL_OFST
 
 
 #ifdef	__cplusplus
diff --git a/sys/dev/sfxge/common/efx_regs_ef10.h b/sys/dev/sfxge/common/efx_regs_ef10.h
index c4a6d0e7c35b..8401726d6935 100644
--- a/sys/dev/sfxge/common/efx_regs_ef10.h
+++ b/sys/dev/sfxge/common/efx_regs_ef10.h
@@ -1,26 +1,31 @@
 /*-
- * Copyright 2007-2010 Solarflare Communications Inc.  All rights reserved.
+ * Copyright (c) 2007-2015 Solarflare Communications Inc.
+ * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
+ * modification, are permitted provided that the following conditions are met:
  *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are
+ * those of the authors and should not be interpreted as representing official
+ * policies, either expressed or implied, of the FreeBSD Project.
  *
  * $FreeBSD$
  */
@@ -34,11 +39,13 @@ extern "C" {
 
 /*
  * BIU_HW_REV_ID_REG(32bit):
- * 
+ *
  */
 
-#define	ER_DZ_BIU_HW_REV_ID_REG 0x00000000
+#define	ER_DZ_BIU_HW_REV_ID_REG_OFST 0x00000000
 /* hunta0=pcie_pf_bar2 */
+#define	ER_DZ_BIU_HW_REV_ID_REG_RESET 0xeb14face
+
 
 #define	ERF_DZ_HW_REV_ID_LBN 0
 #define	ERF_DZ_HW_REV_ID_WIDTH 32
@@ -46,13 +53,15 @@ extern "C" {
 
 /*
  * BIU_MC_SFT_STATUS_REG(32bit):
- * 
+ *
  */
 
-#define	ER_DZ_BIU_MC_SFT_STATUS_REG 0x00000010
+#define	ER_DZ_BIU_MC_SFT_STATUS_REG_OFST 0x00000010
 /* hunta0=pcie_pf_bar2 */
 #define	ER_DZ_BIU_MC_SFT_STATUS_REG_STEP 4
 #define	ER_DZ_BIU_MC_SFT_STATUS_REG_ROWS 8
+#define	ER_DZ_BIU_MC_SFT_STATUS_REG_RESET 0x1111face
+
 
 #define	ERF_DZ_MC_SFT_STATUS_LBN 0
 #define	ERF_DZ_MC_SFT_STATUS_WIDTH 32
@@ -60,11 +69,13 @@ extern "C" {
 
 /*
  * BIU_INT_ISR_REG(32bit):
- * 
+ *
  */
 
-#define	ER_DZ_BIU_INT_ISR_REG 0x00000090
+#define	ER_DZ_BIU_INT_ISR_REG_OFST 0x00000090
 /* hunta0=pcie_pf_bar2 */
+#define	ER_DZ_BIU_INT_ISR_REG_RESET 0x0
+
 
 #define	ERF_DZ_ISR_REG_LBN 0
 #define	ERF_DZ_ISR_REG_WIDTH 32
@@ -72,11 +83,13 @@ extern "C" {
 
 /*
  * MC_DB_LWRD_REG(32bit):
- * 
+ *
  */
 
-#define	ER_DZ_MC_DB_LWRD_REG 0x00000200
+#define	ER_DZ_MC_DB_LWRD_REG_OFST 0x00000200
 /* hunta0=pcie_pf_bar2 */
+#define	ER_DZ_MC_DB_LWRD_REG_RESET 0x0
+
 
 #define	ERF_DZ_MC_DOORBELL_L_LBN 0
 #define	ERF_DZ_MC_DOORBELL_L_WIDTH 32
@@ -84,11 +97,13 @@ extern "C" {
 
 /*
  * MC_DB_HWRD_REG(32bit):
- * 
+ *
  */
 
-#define	ER_DZ_MC_DB_HWRD_REG 0x00000204
+#define	ER_DZ_MC_DB_HWRD_REG_OFST 0x00000204
 /* hunta0=pcie_pf_bar2 */
+#define	ER_DZ_MC_DB_HWRD_REG_RESET 0x0
+
 
 #define	ERF_DZ_MC_DOORBELL_H_LBN 0
 #define	ERF_DZ_MC_DOORBELL_H_WIDTH 32
@@ -96,13 +111,15 @@ extern "C" {
 
 /*
  * EVQ_RPTR_REG(32bit):
- * 
+ *
  */
 
-#define	ER_DZ_EVQ_RPTR_REG 0x00000400
+#define	ER_DZ_EVQ_RPTR_REG_OFST 0x00000400
 /* hunta0=pcie_pf_bar2 */
-#define	ER_DZ_EVQ_RPTR_REG_STEP 4096
+#define	ER_DZ_EVQ_RPTR_REG_STEP 8192
 #define	ER_DZ_EVQ_RPTR_REG_ROWS 2048
+#define	ER_DZ_EVQ_RPTR_REG_RESET 0x0
+
 
 #define	ERF_DZ_EVQ_RPTR_VLD_LBN 15
 #define	ERF_DZ_EVQ_RPTR_VLD_WIDTH 1
@@ -112,13 +129,15 @@ extern "C" {
 
 /*
  * EVQ_TMR_REG(32bit):
- * 
+ *
  */
 
-#define	ER_DZ_EVQ_TMR_REG 0x00000420
+#define	ER_DZ_EVQ_TMR_REG_OFST 0x00000420
 /* hunta0=pcie_pf_bar2 */
-#define	ER_DZ_EVQ_TMR_REG_STEP 4096
+#define	ER_DZ_EVQ_TMR_REG_STEP 8192
 #define	ER_DZ_EVQ_TMR_REG_ROWS 2048
+#define	ER_DZ_EVQ_TMR_REG_RESET 0x0
+
 
 #define	ERF_DZ_TC_TIMER_MODE_LBN 14
 #define	ERF_DZ_TC_TIMER_MODE_WIDTH 2
@@ -128,28 +147,34 @@ extern "C" {
 
 /*
  * RX_DESC_UPD_REG(32bit):
- * 
+ *
  */
 
-#define	ER_DZ_RX_DESC_UPD_REG 0x00000830
+#define	ER_DZ_RX_DESC_UPD_REG_OFST 0x00000830
 /* hunta0=pcie_pf_bar2 */
-#define	ER_DZ_RX_DESC_UPD_REG_STEP 4096
+#define	ER_DZ_RX_DESC_UPD_REG_STEP 8192
 #define	ER_DZ_RX_DESC_UPD_REG_ROWS 2048
+#define	ER_DZ_RX_DESC_UPD_REG_RESET 0x0
+
 
 #define	ERF_DZ_RX_DESC_WPTR_LBN 0
 #define	ERF_DZ_RX_DESC_WPTR_WIDTH 12
 
 
 /*
- * TX_DESC_UPD_REG(76bit):
- * 
+ * TX_DESC_UPD_REG(96bit):
+ *
  */
 
-#define	ER_DZ_TX_DESC_UPD_REG 0x00000a10
+#define	ER_DZ_TX_DESC_UPD_REG_OFST 0x00000a10
 /* hunta0=pcie_pf_bar2 */
-#define	ER_DZ_TX_DESC_UPD_REG_STEP 4096
+#define	ER_DZ_TX_DESC_UPD_REG_STEP 8192
 #define	ER_DZ_TX_DESC_UPD_REG_ROWS 2048
+#define	ER_DZ_TX_DESC_UPD_REG_RESET 0x0
+
 
+#define	ERF_DZ_RSVD_LBN 76
+#define	ERF_DZ_RSVD_WIDTH 20
 #define	ERF_DZ_TX_DESC_WPTR_LBN 64
 #define	ERF_DZ_TX_DESC_WPTR_WIDTH 12
 #define	ERF_DZ_TX_DESC_HWORD_LBN 32
@@ -157,14 +182,38 @@ extern "C" {
 #define	ERF_DZ_TX_DESC_LWORD_LBN 0
 #define	ERF_DZ_TX_DESC_LWORD_WIDTH 32
 
+/*
+ * The workaround for bug 35388 requires multiplexing writes through
+ * the ERF_DZ_TX_DESC_WPTR address.
+ * TX_DESC_UPD: 0ppppppppppp               (bit 11 lost)
+ * EVQ_RPTR:    1000hhhhhhhh, 1001llllllll (split into high and low bits)
+ * EVQ_TMR:     11mmvvvvvvvv               (bits 8:13 of value lost)
+ */
+#define	ER_DD_EVQ_INDIRECT_OFST (ER_DZ_TX_DESC_UPD_REG_OFST + 2 * 4)
+#define	ER_DD_EVQ_INDIRECT_STEP ER_DZ_TX_DESC_UPD_REG_STEP
+#define	ERF_DD_EVQ_IND_RPTR_FLAGS_LBN 8
+#define	ERF_DD_EVQ_IND_RPTR_FLAGS_WIDTH 4
+#define	EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH 8
+#define	EFE_DD_EVQ_IND_RPTR_FLAGS_LOW 9
+#define	ERF_DD_EVQ_IND_RPTR_LBN 0
+#define	ERF_DD_EVQ_IND_RPTR_WIDTH 8
+#define	ERF_DD_EVQ_IND_TIMER_FLAGS_LBN 10
+#define	ERF_DD_EVQ_IND_TIMER_FLAGS_WIDTH 2
+#define	EFE_DD_EVQ_IND_TIMER_FLAGS 3
+#define	ERF_DD_EVQ_IND_TIMER_MODE_LBN 8
+#define	ERF_DD_EVQ_IND_TIMER_MODE_WIDTH 2
+#define	ERF_DD_EVQ_IND_TIMER_VAL_LBN 0
+#define	ERF_DD_EVQ_IND_TIMER_VAL_WIDTH 8
+
 
 /* ES_DRIVER_EV */
 #define	ESF_DZ_DRV_CODE_LBN 60
 #define	ESF_DZ_DRV_CODE_WIDTH 4
 #define	ESF_DZ_DRV_SUB_CODE_LBN 56
 #define	ESF_DZ_DRV_SUB_CODE_WIDTH 4
-#define	ESE_DZ_DRV_TIMER_EV 10
-#define	ESE_DZ_DRV_WAKE_UP_EV 6
+#define	ESE_DZ_DRV_TIMER_EV 3
+#define	ESE_DZ_DRV_START_UP_EV 2
+#define	ESE_DZ_DRV_WAKE_UP_EV 1
 #define	ESF_DZ_DRV_SUB_DATA_DW0_LBN 0
 #define	ESF_DZ_DRV_SUB_DATA_DW0_WIDTH 32
 #define	ESF_DZ_DRV_SUB_DATA_DW1_LBN 32
@@ -194,9 +243,9 @@ extern "C" {
 
 
 /* ES_FF_UMSG_CPU2DL_DESC_FETCH */
-#define	ESF_DZ_C2DDF_DSCR_CACHE_RPTR_LBN 112
+#define	ESF_DZ_C2DDF_DSCR_CACHE_RPTR_LBN 208
 #define	ESF_DZ_C2DDF_DSCR_CACHE_RPTR_WIDTH 6
-#define	ESF_DZ_C2DDF_QID_LBN 96
+#define	ESF_DZ_C2DDF_QID_LBN 160
 #define	ESF_DZ_C2DDF_QID_WIDTH 11
 #define	ESF_DZ_C2DDF_DSCR_BASE_PAGE_ID_LBN 64
 #define	ESF_DZ_C2DDF_DSCR_BASE_PAGE_ID_WIDTH 18
@@ -217,16 +266,16 @@ extern "C" {
 
 
 /* ES_FF_UMSG_CPU2DL_DESC_PUSH */
+#define	ESF_DZ_C2DDP_DSCR_HW_RPTR_LBN 224
+#define	ESF_DZ_C2DDP_DSCR_HW_RPTR_WIDTH 12
 #define	ESF_DZ_C2DDP_DESC_DW0_LBN 128
 #define	ESF_DZ_C2DDP_DESC_DW0_WIDTH 32
 #define	ESF_DZ_C2DDP_DESC_DW1_LBN 160
 #define	ESF_DZ_C2DDP_DESC_DW1_WIDTH 32
 #define	ESF_DZ_C2DDP_DESC_LBN 128
 #define	ESF_DZ_C2DDP_DESC_WIDTH 64
-#define	ESF_DZ_C2DDP_QID_LBN 96
+#define	ESF_DZ_C2DDP_QID_LBN 64
 #define	ESF_DZ_C2DDP_QID_WIDTH 11
-#define	ESF_DZ_C2DDP_DSCR_HW_RPTR_LBN 48
-#define	ESF_DZ_C2DDP_DSCR_HW_RPTR_WIDTH 12
 #define	ESF_DZ_C2DDP_DSCR_HW_WPTR_LBN 32
 #define	ESF_DZ_C2DDP_DSCR_HW_WPTR_WIDTH 12
 #define	ESF_DZ_C2DDP_OID_LBN 16
@@ -258,8 +307,18 @@ extern "C" {
 
 
 /* ES_FF_UMSG_CPU2EV_TXCMPLT */
-#define	ESF_DZ_C2ET_EV_SOFT0_LBN 32
-#define	ESF_DZ_C2ET_EV_SOFT0_WIDTH 16
+#define	ESF_DZ_C2ET_EV_SOFT2_LBN 48
+#define	ESF_DZ_C2ET_EV_SOFT2_WIDTH 16
+#define	ESF_DZ_C2ET_EV_CODE_LBN 42
+#define	ESF_DZ_C2ET_EV_CODE_WIDTH 4
+#define	ESF_DZ_C2ET_EV_OVERRIDE_HOLDOFF_LBN 41
+#define	ESF_DZ_C2ET_EV_OVERRIDE_HOLDOFF_WIDTH 1
+#define	ESF_DZ_C2ET_EV_DROP_EVENT_LBN 40
+#define	ESF_DZ_C2ET_EV_DROP_EVENT_WIDTH 1
+#define	ESF_DZ_C2ET_EV_CAN_MERGE_LBN 39
+#define	ESF_DZ_C2ET_EV_CAN_MERGE_WIDTH 1
+#define	ESF_DZ_C2ET_EV_SOFT1_LBN 32
+#define	ESF_DZ_C2ET_EV_SOFT1_WIDTH 7
 #define	ESF_DZ_C2ET_DSCR_IDX_LBN 16
 #define	ESF_DZ_C2ET_DSCR_IDX_WIDTH 16
 #define	ESF_DZ_C2ET_EV_QID_LBN 5
@@ -310,7 +369,6 @@ extern "C" {
 #define	ESF_DZ_C2RIP_EV_ARG1_WIDTH 16
 #define	ESF_DZ_C2RIP_UPD_CRC_MODE_LBN 157
 #define	ESF_DZ_C2RIP_UPD_CRC_MODE_WIDTH 3
-#define	ESE_DZ_C2RIP_FCOIP_MPA 5
 #define	ESE_DZ_C2RIP_FCOIP_FCOE 4
 #define	ESE_DZ_C2RIP_ISCSI_HDR_AND_PYLD 3
 #define	ESE_DZ_C2RIP_ISCSI_HDR 2
@@ -379,7 +437,7 @@ extern "C" {
 #define	ESF_DZ_C2SD_ENCODED_HOST_ADDR_DW1_WIDTH 16
 #define	ESF_DZ_C2SD_ENCODED_HOST_ADDR_LBN 64
 #define	ESF_DZ_C2SD_ENCODED_HOST_ADDR_WIDTH 48
-#define	ESF_DZ_C2SD_OFFSET_LBN 48
+#define	ESF_DZ_C2SD_OFFSET_LBN 80
 #define	ESF_DZ_C2SD_OFFSET_WIDTH 8
 #define	ESF_DZ_C2SD_QID_LBN 32
 #define	ESF_DZ_C2SD_QID_WIDTH 11
@@ -419,7 +477,6 @@ extern "C" {
 #define	ESF_DZ_C2TDB_DESC_IDX_WIDTH 16
 #define	ESF_DZ_C2TDB_UPD_CRC_MODE_LBN 93
 #define	ESF_DZ_C2TDB_UPD_CRC_MODE_WIDTH 3
-#define	ESE_DZ_C2RIP_FCOIP_MPA 5
 #define	ESE_DZ_C2RIP_FCOIP_FCOE 4
 #define	ESE_DZ_C2RIP_ISCSI_HDR_AND_PYLD 3
 #define	ESE_DZ_C2RIP_ISCSI_HDR 2
@@ -460,6 +517,14 @@ extern "C" {
 
 
 /* ES_FF_UMSG_CPU2TXDP_EGR */
+#define	ESF_DZ_C2TE_RMON_SOFT_LBN 240
+#define	ESF_DZ_C2TE_RMON_SOFT_WIDTH 1
+#define	ESF_DZ_C2TE_VLAN_PRIO_LBN 224
+#define	ESF_DZ_C2TE_VLAN_PRIO_WIDTH 3
+#define	ESF_DZ_C2TE_VLAN_LBN 208
+#define	ESF_DZ_C2TE_VLAN_WIDTH 1
+#define	ESF_DZ_C2TE_QID_LBN 192
+#define	ESF_DZ_C2TE_QID_WIDTH 11
 #define	ESF_DZ_C2TE_PEDIT_DELTA_LBN 168
 #define	ESF_DZ_C2TE_PEDIT_DELTA_WIDTH 8
 #define	ESF_DZ_C2TE_PYLOAD_OFST_LBN 160
@@ -480,20 +545,19 @@ extern "C" {
 #define	ESF_DZ_C2TE_IS_FCOE_WIDTH 1
 #define	ESF_DZ_C2TE_PARSE_INCOMP_LBN 128
 #define	ESF_DZ_C2TE_PARSE_INCOMP_WIDTH 1
-#define	ESF_DZ_C2TE_PKT_LEN_LBN 112
-#define	ESF_DZ_C2TE_PKT_LEN_WIDTH 16
-#define	ESF_DZ_C2TE_UPD_TCPUDPCSUM_MODE_LBN 97
-#define	ESF_DZ_C2TE_UPD_TCPUDPCSUM_MODE_WIDTH 1
-#define	ESF_DZ_C2TE_UPD_IPCSUM_MODE_LBN 96
-#define	ESF_DZ_C2TE_UPD_IPCSUM_MODE_WIDTH 1
-#define	ESF_DZ_C2TE_UPD_CRC_MODE_LBN 93
+#define	ESF_DZ_C2TE_UPD_CRC_MODE_LBN 98
 #define	ESF_DZ_C2TE_UPD_CRC_MODE_WIDTH 3
-#define	ESE_DZ_C2RIP_FCOIP_MPA 5
 #define	ESE_DZ_C2RIP_FCOIP_FCOE 4
 #define	ESE_DZ_C2RIP_ISCSI_HDR_AND_PYLD 3
 #define	ESE_DZ_C2RIP_ISCSI_HDR 2
 #define	ESE_DZ_C2RIP_FCOE 1
 #define	ESE_DZ_C2RIP_OFF 0
+#define	ESF_DZ_C2TE_UPD_TCPUDPCSUM_MODE_LBN 97
+#define	ESF_DZ_C2TE_UPD_TCPUDPCSUM_MODE_WIDTH 1
+#define	ESF_DZ_C2TE_UPD_IPCSUM_MODE_LBN 96
+#define	ESF_DZ_C2TE_UPD_IPCSUM_MODE_WIDTH 1
+#define	ESF_DZ_C2TE_PKT_LEN_LBN 64
+#define	ESF_DZ_C2TE_PKT_LEN_WIDTH 16
 #define	ESF_DZ_C2TE_FINFO_WRD3_LBN 48
 #define	ESF_DZ_C2TE_FINFO_WRD3_WIDTH 16
 #define	ESF_DZ_C2TE_FINFO_WRD2_LBN 32
@@ -542,7 +606,7 @@ extern "C" {
 
 /* ES_FF_UMSG_PACER_BKT_TBL_RD_REQ */
 #define	ESF_DZ_BKT_ID_LBN 0
-#define	ESF_DZ_BKT_ID_WIDTH 9
+#define	ESF_DZ_BKT_ID_WIDTH 10
 
 
 /* ES_FF_UMSG_PACER_BKT_TBL_RD_RSP */
@@ -563,7 +627,7 @@ extern "C" {
 #define	ESF_DZ_MAX_FILL_REG_LBN 12
 #define	ESF_DZ_MAX_FILL_REG_WIDTH 2
 #define	ESF_DZ_BKT_ID_LBN 0
-#define	ESF_DZ_BKT_ID_WIDTH 9
+#define	ESF_DZ_BKT_ID_WIDTH 10
 
 
 /* ES_FF_UMSG_PACER_BKT_TBL_WR_REQ */
@@ -580,7 +644,7 @@ extern "C" {
 #define	ESF_DZ_MAX_FILL_REG_LBN 12
 #define	ESF_DZ_MAX_FILL_REG_WIDTH 2
 #define	ESF_DZ_BKT_ID_LBN 0
-#define	ESF_DZ_BKT_ID_WIDTH 9
+#define	ESF_DZ_BKT_ID_WIDTH 10
 
 
 /* ES_FF_UMSG_PACER_TXQ_TBL_RD_REQ */
@@ -590,13 +654,13 @@ extern "C" {
 
 /* ES_FF_UMSG_PACER_TXQ_TBL_RD_RSP */
 #define	ESF_DZ_MAX_BKT2_LBN 112
-#define	ESF_DZ_MAX_BKT2_WIDTH 9
+#define	ESF_DZ_MAX_BKT2_WIDTH 10
 #define	ESF_DZ_MAX_BKT1_LBN 96
-#define	ESF_DZ_MAX_BKT1_WIDTH 9
+#define	ESF_DZ_MAX_BKT1_WIDTH 10
 #define	ESF_DZ_MAX_BKT0_LBN 80
-#define	ESF_DZ_MAX_BKT0_WIDTH 9
+#define	ESF_DZ_MAX_BKT0_WIDTH 10
 #define	ESF_DZ_MIN_BKT_LBN 64
-#define	ESF_DZ_MIN_BKT_WIDTH 9
+#define	ESF_DZ_MIN_BKT_WIDTH 10
 #define	ESF_DZ_LABEL_LBN 48
 #define	ESF_DZ_LABEL_WIDTH 4
 #define	ESF_DZ_PQ_FLAGS_LBN 32
@@ -609,13 +673,13 @@ extern "C" {
 
 /* ES_FF_UMSG_PACER_TXQ_TBL_WR_REQ */
 #define	ESF_DZ_MAX_BKT2_LBN 112
-#define	ESF_DZ_MAX_BKT2_WIDTH 9
+#define	ESF_DZ_MAX_BKT2_WIDTH 10
 #define	ESF_DZ_MAX_BKT1_LBN 96
-#define	ESF_DZ_MAX_BKT1_WIDTH 9
+#define	ESF_DZ_MAX_BKT1_WIDTH 10
 #define	ESF_DZ_MAX_BKT0_LBN 80
-#define	ESF_DZ_MAX_BKT0_WIDTH 9
+#define	ESF_DZ_MAX_BKT0_WIDTH 10
 #define	ESF_DZ_MIN_BKT_LBN 64
-#define	ESF_DZ_MIN_BKT_WIDTH 9
+#define	ESF_DZ_MIN_BKT_WIDTH 10
 #define	ESF_DZ_LABEL_LBN 48
 #define	ESF_DZ_LABEL_WIDTH 4
 #define	ESF_DZ_PQ_FLAGS_LBN 32
@@ -663,17 +727,19 @@ extern "C" {
 
 
 /* ES_FF_UMSG_RXDP_INGR2CPU */
+#define	ESF_DZ_RI2C_QUEUE_ID_LBN 224
+#define	ESF_DZ_RI2C_QUEUE_ID_WIDTH 11
 #define	ESF_DZ_RI2C_LEN_LBN 208
 #define	ESF_DZ_RI2C_LEN_WIDTH 16
-#define	ESF_DZ_RI2C_L4_CLASS_LBN 202
+#define	ESF_DZ_RI2C_L4_CLASS_LBN 205
 #define	ESF_DZ_RI2C_L4_CLASS_WIDTH 3
-#define	ESF_DZ_RI2C_L3_CLASS_LBN 199
+#define	ESF_DZ_RI2C_L3_CLASS_LBN 202
 #define	ESF_DZ_RI2C_L3_CLASS_WIDTH 3
-#define	ESF_DZ_RI2C_ETHTAG_CLASS_LBN 196
+#define	ESF_DZ_RI2C_ETHTAG_CLASS_LBN 199
 #define	ESF_DZ_RI2C_ETHTAG_CLASS_WIDTH 3
-#define	ESF_DZ_RI2C_ETHBASE_CLASS_LBN 193
+#define	ESF_DZ_RI2C_ETHBASE_CLASS_LBN 196
 #define	ESF_DZ_RI2C_ETHBASE_CLASS_WIDTH 3
-#define	ESF_DZ_RI2C_MAC_CLASS_LBN 192
+#define	ESF_DZ_RI2C_MAC_CLASS_LBN 195
 #define	ESF_DZ_RI2C_MAC_CLASS_WIDTH 1
 #define	ESF_DZ_RI2C_PKT_OFST_LBN 176
 #define	ESF_DZ_RI2C_PKT_OFST_WIDTH 16
@@ -765,12 +831,12 @@ extern "C" {
 #define	ESF_DZ_TD2CP_ETHBASE_CLASS_WIDTH 3
 #define	ESF_DZ_TD2CP_MAC_CLASS_LBN 240
 #define	ESF_DZ_TD2CP_MAC_CLASS_WIDTH 1
-#define	ESF_DZ_TD2CP_SOFT_LBN 226
-#define	ESF_DZ_TD2CP_SOFT_WIDTH 14
-#define	ESF_DZ_TD2CP_PKT_ABORT_LBN 225
+#define	ESF_DZ_TD2CP_PCIE_ERR_OR_ABORT_LBN 239
+#define	ESF_DZ_TD2CP_PCIE_ERR_OR_ABORT_WIDTH 1
+#define	ESF_DZ_TD2CP_PKT_ABORT_LBN 238
 #define	ESF_DZ_TD2CP_PKT_ABORT_WIDTH 1
-#define	ESF_DZ_TD2CP_PCIE_ERR_LBN 224
-#define	ESF_DZ_TD2CP_PCIE_ERR_WIDTH 1
+#define	ESF_DZ_TD2CP_SOFT_LBN 224
+#define	ESF_DZ_TD2CP_SOFT_WIDTH 14
 #define	ESF_DZ_TD2CP_DESC_IDX_LBN 208
 #define	ESF_DZ_TD2CP_DESC_IDX_WIDTH 16
 #define	ESF_DZ_TD2CP_PKT_LEN_LBN 192
@@ -854,7 +920,7 @@ extern "C" {
 
 /* ES_LUE_DB_MATCH_ENTRY */
 #define	ESF_DZ_LUE_DSCRMNTR_LBN 140
-#define	ESF_DZ_LUE_DSCRMNTR_WIDTH 4
+#define	ESF_DZ_LUE_DSCRMNTR_WIDTH 6
 #define	ESF_DZ_LUE_MATCH_VAL_DW0_LBN 44
 #define	ESF_DZ_LUE_MATCH_VAL_DW0_WIDTH 32
 #define	ESF_DZ_LUE_MATCH_VAL_DW1_LBN 76
@@ -875,13 +941,11 @@ extern "C" {
 #define	ESE_DZ_LUE_SINGLE 0
 #define	ESF_DZ_LUE_RCPNTR_LBN 0
 #define	ESF_DZ_LUE_RCPNTR_WIDTH 24
-#define	ESF_DZ_LUE_RCPNTR_ME_PTR_LBN 0
-#define	ESF_DZ_LUE_RCPNTR_ME_PTR_WIDTH 14
 
 
 /* ES_LUE_DB_NONMATCH_ENTRY */
 #define	ESF_DZ_LUE_DSCRMNTR_LBN 140
-#define	ESF_DZ_LUE_DSCRMNTR_WIDTH 4
+#define	ESF_DZ_LUE_DSCRMNTR_WIDTH 6
 #define	ESF_DZ_LUE_TERMINAL_LBN 139
 #define	ESF_DZ_LUE_TERMINAL_WIDTH 1
 #define	ESF_DZ_LUE_LAST_LBN 138
@@ -914,9 +978,9 @@ extern "C" {
 #define	ESF_DZ_MC2L_DR_PAD_DW3_LBN 118
 #define	ESF_DZ_MC2L_DR_PAD_DW3_WIDTH 32
 #define	ESF_DZ_MC2L_DR_PAD_DW4_LBN 150
-#define	ESF_DZ_MC2L_DR_PAD_DW4_WIDTH 16
+#define	ESF_DZ_MC2L_DR_PAD_DW4_WIDTH 18
 #define	ESF_DZ_MC2L_DR_PAD_LBN 22
-#define	ESF_DZ_MC2L_DR_PAD_WIDTH 144
+#define	ESF_DZ_MC2L_DR_PAD_WIDTH 146
 #define	ESF_DZ_MC2L_DR_ADDR_LBN 8
 #define	ESF_DZ_MC2L_DR_ADDR_WIDTH 14
 #define	ESF_DZ_MC2L_DR_THREAD_ID_LBN 5
@@ -933,7 +997,7 @@ extern "C" {
 
 /* ES_LUE_MC_DIRECT_RESPONSE_MSG */
 #define	ESF_DZ_L2MC_DR_PAD_LBN 146
-#define	ESF_DZ_L2MC_DR_PAD_WIDTH 6
+#define	ESF_DZ_L2MC_DR_PAD_WIDTH 8
 #define	ESF_DZ_L2MC_DR_RCPNT_PTR_LBN 132
 #define	ESF_DZ_L2MC_DR_RCPNT_PTR_WIDTH 14
 #define	ESF_DZ_L2MC_DR_RCPNT4_LBN 108
@@ -972,9 +1036,9 @@ extern "C" {
 #define	ESF_DZ_MC2L_GPR_PAD_DW3_LBN 118
 #define	ESF_DZ_MC2L_GPR_PAD_DW3_WIDTH 32
 #define	ESF_DZ_MC2L_GPR_PAD_DW4_LBN 150
-#define	ESF_DZ_MC2L_GPR_PAD_DW4_WIDTH 16
+#define	ESF_DZ_MC2L_GPR_PAD_DW4_WIDTH 18
 #define	ESF_DZ_MC2L_GPR_PAD_LBN 22
-#define	ESF_DZ_MC2L_GPR_PAD_WIDTH 144
+#define	ESF_DZ_MC2L_GPR_PAD_WIDTH 146
 #define	ESF_DZ_MC2L_GPR_ADDR_LBN 8
 #define	ESF_DZ_MC2L_GPR_ADDR_WIDTH 14
 #define	ESF_DZ_MC2L_GPR_THREAD_ID_LBN 5
@@ -999,9 +1063,9 @@ extern "C" {
 #define	ESF_DZ_L2MC_GPR_DATA_DW3_LBN 104
 #define	ESF_DZ_L2MC_GPR_DATA_DW3_WIDTH 32
 #define	ESF_DZ_L2MC_GPR_DATA_DW4_LBN 136
-#define	ESF_DZ_L2MC_GPR_DATA_DW4_WIDTH 16
+#define	ESF_DZ_L2MC_GPR_DATA_DW4_WIDTH 18
 #define	ESF_DZ_L2MC_GPR_DATA_LBN 8
-#define	ESF_DZ_L2MC_GPR_DATA_WIDTH 144
+#define	ESF_DZ_L2MC_GPR_DATA_WIDTH 146
 #define	ESF_DZ_L2MC_GPR_THREAD_ID_LBN 5
 #define	ESF_DZ_L2MC_GPR_THREAD_ID_WIDTH 3
 #define	ESF_DZ_L2MC_GPR_CLIENT_ID_LBN 2
@@ -1024,9 +1088,9 @@ extern "C" {
 #define	ESF_DZ_MC2L_GPW_DATA_DW3_LBN 118
 #define	ESF_DZ_MC2L_GPW_DATA_DW3_WIDTH 32
 #define	ESF_DZ_MC2L_GPW_DATA_DW4_LBN 150
-#define	ESF_DZ_MC2L_GPW_DATA_DW4_WIDTH 16
+#define	ESF_DZ_MC2L_GPW_DATA_DW4_WIDTH 18
 #define	ESF_DZ_MC2L_GPW_DATA_LBN 22
-#define	ESF_DZ_MC2L_GPW_DATA_WIDTH 144
+#define	ESF_DZ_MC2L_GPW_DATA_WIDTH 146
 #define	ESF_DZ_MC2L_GPW_ADDR_LBN 8
 #define	ESF_DZ_MC2L_GPW_ADDR_WIDTH 14
 #define	ESF_DZ_MC2L_GPW_THREAD_ID_LBN 5
@@ -1042,22 +1106,22 @@ extern "C" {
 
 
 /* ES_LUE_MC_MATCH_REQUEST_MSG */
-#define	ESF_DZ_MC2L_MR_PAD_LBN 135
+#define	ESF_DZ_MC2L_MR_PAD_LBN 137
 #define	ESF_DZ_MC2L_MR_PAD_WIDTH 31
-#define	ESF_DZ_MC2L_MR_HASH2_LBN 122
+#define	ESF_DZ_MC2L_MR_HASH2_LBN 124
 #define	ESF_DZ_MC2L_MR_HASH2_WIDTH 13
-#define	ESF_DZ_MC2L_MR_HASH1_LBN 108
+#define	ESF_DZ_MC2L_MR_HASH1_LBN 110
 #define	ESF_DZ_MC2L_MR_HASH1_WIDTH 14
-#define	ESF_DZ_MC2L_MR_MATCH_BITS_DW0_LBN 12
+#define	ESF_DZ_MC2L_MR_MATCH_BITS_DW0_LBN 14
 #define	ESF_DZ_MC2L_MR_MATCH_BITS_DW0_WIDTH 32
-#define	ESF_DZ_MC2L_MR_MATCH_BITS_DW1_LBN 44
+#define	ESF_DZ_MC2L_MR_MATCH_BITS_DW1_LBN 46
 #define	ESF_DZ_MC2L_MR_MATCH_BITS_DW1_WIDTH 32
-#define	ESF_DZ_MC2L_MR_MATCH_BITS_DW2_LBN 76
+#define	ESF_DZ_MC2L_MR_MATCH_BITS_DW2_LBN 78
 #define	ESF_DZ_MC2L_MR_MATCH_BITS_DW2_WIDTH 32
-#define	ESF_DZ_MC2L_MR_MATCH_BITS_LBN 12
+#define	ESF_DZ_MC2L_MR_MATCH_BITS_LBN 14
 #define	ESF_DZ_MC2L_MR_MATCH_BITS_WIDTH 96
 #define	ESF_DZ_MC2L_MR_DSCRMNTR_LBN 8
-#define	ESF_DZ_MC2L_MR_DSCRMNTR_WIDTH 4
+#define	ESF_DZ_MC2L_MR_DSCRMNTR_WIDTH 6
 #define	ESF_DZ_MC2L_MR_THREAD_ID_LBN 5
 #define	ESF_DZ_MC2L_MR_THREAD_ID_WIDTH 3
 #define	ESF_DZ_MC2L_MR_CLIENT_ID_LBN 2
@@ -1078,9 +1142,9 @@ extern "C" {
 #define	ESF_DZ_L2MC_MR_PAD_DW2_LBN 117
 #define	ESF_DZ_L2MC_MR_PAD_DW2_WIDTH 32
 #define	ESF_DZ_L2MC_MR_PAD_DW3_LBN 149
-#define	ESF_DZ_L2MC_MR_PAD_DW3_WIDTH 3
+#define	ESF_DZ_L2MC_MR_PAD_DW3_WIDTH 5
 #define	ESF_DZ_L2MC_MR_PAD_LBN 53
-#define	ESF_DZ_L2MC_MR_PAD_WIDTH 99
+#define	ESF_DZ_L2MC_MR_PAD_WIDTH 101
 #define	ESF_DZ_L2MC_MR_LUE_RCPNT_LBN 29
 #define	ESF_DZ_L2MC_MR_LUE_RCPNT_WIDTH 24
 #define	ESF_DZ_L2MC_MR_RX_MCAST_LBN 28
@@ -1115,9 +1179,9 @@ extern "C" {
 #define	ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW3_LBN 104
 #define	ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW3_WIDTH 32
 #define	ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW4_LBN 136
-#define	ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW4_WIDTH 30
+#define	ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW4_WIDTH 32
 #define	ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_LBN 8
-#define	ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_WIDTH 158
+#define	ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_WIDTH 160
 #define	ESF_DZ_LUE_HW_REQ_BASE_THREAD_ID_LBN 5
 #define	ESF_DZ_LUE_HW_REQ_BASE_THREAD_ID_WIDTH 3
 #define	ESF_DZ_LUE_HW_REQ_BASE_CLIENT_ID_LBN 2
@@ -1144,9 +1208,9 @@ extern "C" {
 #define	ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW3_LBN 104
 #define	ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW3_WIDTH 32
 #define	ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW4_LBN 136
-#define	ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW4_WIDTH 16
+#define	ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW4_WIDTH 18
 #define	ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_LBN 8
-#define	ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_WIDTH 144
+#define	ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_WIDTH 146
 #define	ESF_DZ_LUE_HW_RSP_BASE_THREAD_ID_LBN 5
 #define	ESF_DZ_LUE_HW_RSP_BASE_THREAD_ID_WIDTH 3
 #define	ESF_DZ_LUE_HW_RSP_BASE_CLIENT_ID_LBN 2
@@ -1244,9 +1308,9 @@ extern "C" {
 #define	ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW3_LBN 104
 #define	ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW3_WIDTH 32
 #define	ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW4_LBN 136
-#define	ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW4_WIDTH 16
+#define	ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW4_WIDTH 18
 #define	ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_LBN 8
-#define	ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_WIDTH 144
+#define	ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_WIDTH 146
 #define	ESF_DZ_LUE_HW_RSP_GPRD_THREAD_ID_LBN 5
 #define	ESF_DZ_LUE_HW_RSP_GPRD_THREAD_ID_WIDTH 3
 #define	ESF_DZ_LUE_HW_RSP_GPRD_CLIENT_ID_LBN 2
@@ -1273,9 +1337,9 @@ extern "C" {
 #define	ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW3_LBN 118
 #define	ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW3_WIDTH 32
 #define	ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW4_LBN 150
-#define	ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW4_WIDTH 16
+#define	ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW4_WIDTH 18
 #define	ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_LBN 22
-#define	ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_WIDTH 144
+#define	ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_WIDTH 146
 #define	ESF_DZ_LUE_HW_REQ_GPWR_ADDR_LBN 8
 #define	ESF_DZ_LUE_HW_REQ_GPWR_ADDR_WIDTH 14
 #define	ESF_DZ_LUE_HW_REQ_GPWR_THREAD_ID_LBN 5
@@ -1295,22 +1359,22 @@ extern "C" {
 
 
 /* ES_LUE_MSG_MATCH_REQ */
-#define	ESF_DZ_LUE_HW_REQ_MATCH_MATCH_REQ_COUNT_LBN 135
-#define	ESF_DZ_LUE_HW_REQ_MATCH_MATCH_REQ_COUNT_WIDTH 6
-#define	ESF_DZ_LUE_HW_REQ_MATCH_HASH2_LBN 122
+#define	ESF_DZ_LUE_HW_REQ_MATCH_MATCH_REQ_COUNT_LBN 137
+#define	ESF_DZ_LUE_HW_REQ_MATCH_MATCH_REQ_COUNT_WIDTH 8
+#define	ESF_DZ_LUE_HW_REQ_MATCH_HASH2_LBN 124
 #define	ESF_DZ_LUE_HW_REQ_MATCH_HASH2_WIDTH 13
-#define	ESF_DZ_LUE_HW_REQ_MATCH_HASH1_LBN 108
+#define	ESF_DZ_LUE_HW_REQ_MATCH_HASH1_LBN 110
 #define	ESF_DZ_LUE_HW_REQ_MATCH_HASH1_WIDTH 14
-#define	ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_DW0_LBN 12
+#define	ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_DW0_LBN 14
 #define	ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_DW0_WIDTH 32
-#define	ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_DW1_LBN 44
+#define	ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_DW1_LBN 46
 #define	ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_DW1_WIDTH 32
-#define	ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_DW2_LBN 76
+#define	ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_DW2_LBN 78
 #define	ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_DW2_WIDTH 32
-#define	ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_LBN 12
+#define	ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_LBN 14
 #define	ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_WIDTH 96
 #define	ESF_DZ_LUE_HW_REQ_MATCH_DSCRMNTR_LBN 8
-#define	ESF_DZ_LUE_HW_REQ_MATCH_DSCRMNTR_WIDTH 4
+#define	ESF_DZ_LUE_HW_REQ_MATCH_DSCRMNTR_WIDTH 6
 #define	ESF_DZ_LUE_HW_REQ_MATCH_THREAD_ID_LBN 5
 #define	ESF_DZ_LUE_HW_REQ_MATCH_THREAD_ID_WIDTH 3
 #define	ESF_DZ_LUE_HW_REQ_MATCH_CLIENT_ID_LBN 2
@@ -1543,10 +1607,10 @@ extern "C" {
 #define	ESF_DZ_RX_OVERRIDE_HOLDOFF_WIDTH 1
 #define	ESF_DZ_RX_DROP_EVENT_LBN 58
 #define	ESF_DZ_RX_DROP_EVENT_WIDTH 1
-#define	ESF_DZ_RX_EV_RSVD2_LBN 55
-#define	ESF_DZ_RX_EV_RSVD2_WIDTH 3
+#define	ESF_DZ_RX_EV_RSVD2_LBN 54
+#define	ESF_DZ_RX_EV_RSVD2_WIDTH 4
 #define	ESF_DZ_RX_EV_SOFT2_LBN 52
-#define	ESF_DZ_RX_EV_SOFT2_WIDTH 3
+#define	ESF_DZ_RX_EV_SOFT2_WIDTH 2
 #define	ESF_DZ_RX_DSC_PTR_LBITS_LBN 48
 #define	ESF_DZ_RX_DSC_PTR_LBITS_WIDTH 4
 #define	ESF_DZ_RX_L4_CLASS_LBN 45
@@ -1590,8 +1654,10 @@ extern "C" {
 #define	ESE_DZ_MAC_CLASS_UCAST 0
 #define	ESF_DZ_RX_EV_SOFT1_LBN 32
 #define	ESF_DZ_RX_EV_SOFT1_WIDTH 3
-#define	ESF_DZ_RX_EV_RSVD1_LBN 30
-#define	ESF_DZ_RX_EV_RSVD1_WIDTH 2
+#define	ESF_DZ_RX_EV_RSVD1_LBN 31
+#define	ESF_DZ_RX_EV_RSVD1_WIDTH 1
+#define	ESF_DZ_RX_ABORT_LBN 30
+#define	ESF_DZ_RX_ABORT_WIDTH 1
 #define	ESF_DZ_RX_ECC_ERR_LBN 29
 #define	ESF_DZ_RX_ECC_ERR_WIDTH 1
 #define	ESF_DZ_RX_CRC1_ERR_LBN 28
@@ -1605,7 +1671,7 @@ extern "C" {
 #define	ESF_DZ_RX_ECRC_ERR_LBN 24
 #define	ESF_DZ_RX_ECRC_ERR_WIDTH 1
 #define	ESF_DZ_RX_QLABEL_LBN 16
-#define	ESF_DZ_RX_QLABEL_WIDTH 8
+#define	ESF_DZ_RX_QLABEL_WIDTH 5
 #define	ESF_DZ_RX_PARSE_INCOMPLETE_LBN 15
 #define	ESF_DZ_RX_PARSE_INCOMPLETE_WIDTH 1
 #define	ESF_DZ_RX_CONT_LBN 14
@@ -1687,16 +1753,16 @@ extern "C" {
 #define	ESF_DZ_RX_U_FAST_PATH_WIDTH 1
 #define	ESF_DZ_RX_U_SOFT1_B1R0_4_LBN 68
 #define	ESF_DZ_RX_U_SOFT1_B1R0_4_WIDTH 1
-#define	ESF_DZ_RX_U_NO_FLUSH_LBN 67
-#define	ESF_DZ_RX_U_NO_FLUSH_WIDTH 1
+#define	ESF_DZ_RX_U_CHAIN_LBN 67
+#define	ESF_DZ_RX_U_CHAIN_WIDTH 1
 #define	ESF_DZ_RX_U_SOFT1_B1R0_3_LBN 67
 #define	ESF_DZ_RX_U_SOFT1_B1R0_3_WIDTH 1
 #define	ESF_DZ_RX_U_DESC_ACTIVE_LBN 66
 #define	ESF_DZ_RX_U_DESC_ACTIVE_WIDTH 1
 #define	ESF_DZ_RX_U_SOFT1_B1R0_2_LBN 66
 #define	ESF_DZ_RX_U_SOFT1_B1R0_2_WIDTH 1
-#define	ESF_DZ_RX_U_HDR_SPLIT_LBN 65
-#define	ESF_DZ_RX_U_HDR_SPLIT_WIDTH 1
+#define	ESF_DZ_RX_U_TIMESTAMP_LBN 65
+#define	ESF_DZ_RX_U_TIMESTAMP_WIDTH 1
 #define	ESF_DZ_RX_U_SOFT1_B1R0_1_LBN 65
 #define	ESF_DZ_RX_U_SOFT1_B1R0_1_WIDTH 1
 #define	ESF_DZ_RX_U_Q_ENABLE_LBN 64
@@ -1728,12 +1794,14 @@ extern "C" {
 #define	ESF_DZ_RX_U_DSCR_BASE_PAGE_ID_WIDTH 18
 #define	ESF_DZ_RX_U_SOFT18_B1R0_0_LBN 64
 #define	ESF_DZ_RX_U_SOFT18_B1R0_0_WIDTH 18
-#define	ESF_DZ_RX_U_QST1_SPARE_LBN 52
-#define	ESF_DZ_RX_U_QST1_SPARE_WIDTH 12
+#define	ESF_DZ_RX_U_QST1_SPARE_LBN 53
+#define	ESF_DZ_RX_U_QST1_SPARE_WIDTH 11
 #define	ESF_DZ_RX_U_SOFT16_B0R3_0_LBN 48
 #define	ESF_DZ_RX_U_SOFT16_B0R3_0_WIDTH 16
-#define	ESF_DZ_RX_U_TIMESTAMP_LBN 51
-#define	ESF_DZ_RX_U_TIMESTAMP_WIDTH 1
+#define	ESF_DZ_RX_U_NO_FLUSH_LBN 52
+#define	ESF_DZ_RX_U_NO_FLUSH_WIDTH 1
+#define	ESF_DZ_RX_U_HDR_SPLIT_LBN 51
+#define	ESF_DZ_RX_U_HDR_SPLIT_WIDTH 1
 #define	ESF_DZ_RX_U_DOORBELL_ENABLED_LBN 50
 #define	ESF_DZ_RX_U_DOORBELL_ENABLED_WIDTH 1
 #define	ESF_DZ_RX_U_WORK_PENDING_LBN 49
@@ -1758,6 +1826,39 @@ extern "C" {
 #define	ESF_DZ_RX_U_SOFT3_B0R0_0_WIDTH 3
 
 
+/* ES_SGMII_DEV_PTNR_ABILITY_1000BX_MD */
+#define	ESF_DZ_SGMII_DPA_NXT_PG_LBN 15
+#define	ESF_DZ_SGMII_DPA_NXT_PG_WIDTH 1
+#define	ESF_DZ_SGMII_DPA_ACK_LBN 14
+#define	ESF_DZ_SGMII_DPA_ACK_WIDTH 1
+#define	ESF_DZ_SGMII_DPA_REMOTE_FLT_LBN 12
+#define	ESF_DZ_SGMII_DPA_REMOTE_FLT_WIDTH 2
+#define	ESE_DZ_SGMII_DPA_RF_AN_ERR 3
+#define	ESE_DZ_SGMII_DPA_RF_OFFLINE 2
+#define	ESE_DZ_SGMII_DPA_RF_LINK_FAIL 1
+#define	ESE_DZ_SGMII_DPA_RF_NONE 0
+#define	ESF_DZ_SGMII_DPA_PS_LBN 7
+#define	ESF_DZ_SGMII_DPA_PS_WIDTH 2
+#define	ESF_DZ_SGMII_DPA_HD_LBN 6
+#define	ESF_DZ_SGMII_DPA_HD_WIDTH 1
+#define	ESF_DZ_SGMII_DPA_FD_LBN 5
+#define	ESF_DZ_SGMII_DPA_FD_WIDTH 1
+
+
+/* ES_SGMII_DEV_PTNR_ABILITY_SGMII_MD */
+#define	ESF_DZ_SGMII_DPA_CPR_LINK_STATE_LBN 15
+#define	ESF_DZ_SGMII_DPA_CPR_LINK_STATE_WIDTH 1
+#define	ESF_DZ_SGMII_DPA_ACK_LBN 14
+#define	ESF_DZ_SGMII_DPA_ACK_WIDTH 1
+#define	ESF_DZ_SGMII_CPR_BPLX_STS_LBN 12
+#define	ESF_DZ_SGMII_CPR_BPLX_STS_WIDTH 1
+#define	ESF_DZ_SGMII_DPA_COPPER_SPEED_LBN 10
+#define	ESF_DZ_SGMII_DPA_COPPER_SPEED_WIDTH 2
+#define	ESE_DZ_SGMII_DPA_CPR_1GBS 2
+#define	ESE_DZ_SGMII_DPA_CPR_100MBS 1
+#define	ESE_DZ_SGMII_DPA_CPR_10MBS 0
+
+
 /* ES_SMC_BUFTBL_CNTRL_ENTRY */
 #define	ESF_DZ_SMC_SW_CNTXT_DW0_LBN 16
 #define	ESF_DZ_SMC_SW_CNTXT_DW0_WIDTH 32
@@ -2187,6 +2288,30 @@ extern "C" {
 #define	ESE_DZ_SMC_REQ_BUFTBL_LOOKUP 0
 
 
+/* ES_TX_CSUM_TSTAMP_DESC */
+#define	ESF_DZ_TX_DESC_IS_OPT_LBN 63
+#define	ESF_DZ_TX_DESC_IS_OPT_WIDTH 1
+#define	ESF_DZ_TX_OPTION_TYPE_LBN 60
+#define	ESF_DZ_TX_OPTION_TYPE_WIDTH 3
+#define	ESE_DZ_TX_OPTION_DESC_TSO 7
+#define	ESE_DZ_TX_OPTION_DESC_VLAN 6
+#define	ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0
+#define	ESF_DZ_TX_TIMESTAMP_LBN 5
+#define	ESF_DZ_TX_TIMESTAMP_WIDTH 1
+#define	ESF_DZ_TX_OPTION_CRC_MODE_LBN 2
+#define	ESF_DZ_TX_OPTION_CRC_MODE_WIDTH 3
+#define	ESE_DZ_TX_OPTION_CRC_FCOIP_MPA 5
+#define	ESE_DZ_TX_OPTION_CRC_FCOIP_FCOE 4
+#define	ESE_DZ_TX_OPTION_CRC_ISCSI_HDR_AND_PYLD 3
+#define	ESE_DZ_TX_OPTION_CRC_ISCSI_HDR 2
+#define	ESE_DZ_TX_OPTION_CRC_FCOE 1
+#define	ESE_DZ_TX_OPTION_CRC_OFF 0
+#define	ESF_DZ_TX_OPTION_UDP_TCP_CSUM_LBN 1
+#define	ESF_DZ_TX_OPTION_UDP_TCP_CSUM_WIDTH 1
+#define	ESF_DZ_TX_OPTION_IP_CSUM_LBN 0
+#define	ESF_DZ_TX_OPTION_IP_CSUM_WIDTH 1
+
+
 /* ES_TX_EVENT */
 #define	ESF_DZ_TX_CODE_LBN 60
 #define	ESF_DZ_TX_CODE_WIDTH 4
@@ -2198,10 +2323,12 @@ extern "C" {
 #define	ESF_DZ_TX_EV_RSVD_WIDTH 10
 #define	ESF_DZ_TX_SOFT2_LBN 32
 #define	ESF_DZ_TX_SOFT2_WIDTH 16
+#define	ESF_DZ_TX_CAN_MERGE_LBN 31
+#define	ESF_DZ_TX_CAN_MERGE_WIDTH 1
 #define	ESF_DZ_TX_SOFT1_LBN 24
-#define	ESF_DZ_TX_SOFT1_WIDTH 8
+#define	ESF_DZ_TX_SOFT1_WIDTH 7
 #define	ESF_DZ_TX_QLABEL_LBN 16
-#define	ESF_DZ_TX_QLABEL_WIDTH 8
+#define	ESF_DZ_TX_QLABEL_WIDTH 5
 #define	ESF_DZ_TX_DESCR_INDX_LBN 0
 #define	ESF_DZ_TX_DESCR_INDX_WIDTH 16
 
@@ -2221,305 +2348,33 @@ extern "C" {
 #define	ESF_DZ_TX_KER_BUF_ADDR_WIDTH 48
 
 
-/* ES_TX_OPTION_DESC */
+/* ES_TX_PIO_DESC */
+#define	ESF_DZ_TX_PIO_TYPE_LBN 63
+#define	ESF_DZ_TX_PIO_TYPE_WIDTH 1
+#define	ESF_DZ_TX_PIO_OPT_LBN 60
+#define	ESF_DZ_TX_PIO_OPT_WIDTH 3
+#define	ESF_DZ_TX_PIO_CONT_LBN 59
+#define	ESF_DZ_TX_PIO_CONT_WIDTH 1
+#define	ESF_DZ_TX_PIO_BYTE_CNT_LBN 32
+#define	ESF_DZ_TX_PIO_BYTE_CNT_WIDTH 12
+#define	ESF_DZ_TX_PIO_BUF_ADDR_LBN 0
+#define	ESF_DZ_TX_PIO_BUF_ADDR_WIDTH 12
+
+
+/* ES_TX_TSO_DESC */
 #define	ESF_DZ_TX_DESC_IS_OPT_LBN 63
 #define	ESF_DZ_TX_DESC_IS_OPT_WIDTH 1
 #define	ESF_DZ_TX_OPTION_TYPE_LBN 60
 #define	ESF_DZ_TX_OPTION_TYPE_WIDTH 3
-#define	ESE_DZ_TX_OPTION_DESC_TSO 4
+#define	ESE_DZ_TX_OPTION_DESC_TSO 7
+#define	ESE_DZ_TX_OPTION_DESC_VLAN 6
 #define	ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0
 #define	ESF_DZ_TX_TSO_TCP_FLAGS_LBN 48
 #define	ESF_DZ_TX_TSO_TCP_FLAGS_WIDTH 8
-#define	ESF_DZ_TX_TSO_TCP_MSS_LBN 32
-#define	ESF_DZ_TX_TSO_TCP_MSS_WIDTH 16
+#define	ESF_DZ_TX_TSO_IP_ID_LBN 32
+#define	ESF_DZ_TX_TSO_IP_ID_WIDTH 16
 #define	ESF_DZ_TX_TSO_TCP_SEQNO_LBN 0
 #define	ESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32
-#define	ESF_DZ_TX_OPTION_CRC_MODE_LBN 2
-#define	ESF_DZ_TX_OPTION_CRC_MODE_WIDTH 3
-#define	ESE_DZ_TX_OPTION_CRC_FCOIP_MPA 5
-#define	ESE_DZ_TX_OPTION_CRC_FCOIP_FCOE 4
-#define	ESE_DZ_TX_OPTION_CRC_ISCSI_HDR_AND_PYLD 3
-#define	ESE_DZ_TX_OPTION_CRC_ISCSI_HDR 2
-#define	ESE_DZ_TX_OPTION_CRC_FCOE 1
-#define	ESE_DZ_TX_OPTION_CRC_OFF 0
-#define	ESF_DZ_TX_OPTION_UDP_TCP_CSUM_LBN 1
-#define	ESF_DZ_TX_OPTION_UDP_TCP_CSUM_WIDTH 1
-#define	ESF_DZ_TX_OPTION_IP_CSUM_LBN 0
-#define	ESF_DZ_TX_OPTION_IP_CSUM_WIDTH 1
-
-
-/* ES_TX_PACER_BASE_MSG */
-#define	ESF_DZ_TXP_BASE_REQ_MSG_DATA_DW0_LBN 11
-#define	ESF_DZ_TXP_BASE_REQ_MSG_DATA_DW0_WIDTH 32
-#define	ESF_DZ_TXP_BASE_REQ_MSG_DATA_DW1_LBN 43
-#define	ESF_DZ_TXP_BASE_REQ_MSG_DATA_DW1_WIDTH 32
-#define	ESF_DZ_TXP_BASE_REQ_MSG_DATA_DW2_LBN 75
-#define	ESF_DZ_TXP_BASE_REQ_MSG_DATA_DW2_WIDTH 23
-#define	ESF_DZ_TXP_BASE_REQ_MSG_DATA_LBN 11
-#define	ESF_DZ_TXP_BASE_REQ_MSG_DATA_WIDTH 87
-#define	ESF_DZ_TXP_BASE_OP_LBN 2
-#define	ESF_DZ_TXP_BASE_OP_WIDTH 3
-#define	ESE_DZ_DPCPU_PACER_BKT_TBL_RD 7
-#define	ESE_DZ_DPCPU_PACER_BKT_TBL_WR 6
-#define	ESE_DZ_DPCPU_PACER_TXQ_TBL_RD 5
-#define	ESE_DZ_DPCPU_PACER_TXQ_TBL_WR 4
-#define	ESE_DZ_DPCPU_PACER_TXQ_D_R_NI 3
-#define	ESE_DZ_DPCPU_PACER_TXQ_D_R_I 2
-#define	ESE_DZ_DPCPU_PACER_BKT_D_R_RD 1
-#define	ESE_DZ_DPCPU_PACER_BKT_D_RD 0
-#define	ESF_DZ_TXP_BASE_CLIENT_ID_LBN 0
-#define	ESF_DZ_TXP_BASE_CLIENT_ID_WIDTH 2
-#define	ESE_DZ_DPCPU_PACER_CPU_CLIENT 2
-#define	ESE_DZ_DPCPU_PACER_CMD_CTL_CLIENT 1
-#define	ESE_DZ_DPCPU_PACER_ALRT_CTL_CLIENT 0
-
-
-/* ES_TX_PACER_BKT_D_R_REQ */
-#define	ESF_DZ_TXP_BKT_D_R_REQ_FRM_LEN_LBN 45
-#define	ESF_DZ_TXP_BKT_D_R_REQ_FRM_LEN_WIDTH 14
-#define	ESF_DZ_TXP_BKT_D_R_REQ_MAX_BKT2_LBN 35
-#define	ESF_DZ_TXP_BKT_D_R_REQ_MAX_BKT2_WIDTH 10
-#define	ESF_DZ_TXP_BKT_D_R_REQ_MAX_BKT1_LBN 25
-#define	ESF_DZ_TXP_BKT_D_R_REQ_MAX_BKT1_WIDTH 10
-#define	ESF_DZ_TXP_BKT_D_R_REQ_MAX_BKT0_LBN 15
-#define	ESF_DZ_TXP_BKT_D_R_REQ_MAX_BKT0_WIDTH 10
-#define	ESF_DZ_TXP_BKT_D_R_REQ_MIN_BKT_LBN 5
-#define	ESF_DZ_TXP_BKT_D_R_REQ_MIN_BKT_WIDTH 10
-#define	ESF_DZ_TXP_BKT_D_R_REQ_OP_LBN 2
-#define	ESF_DZ_TXP_BKT_D_R_REQ_OP_WIDTH 3
-#define	ESE_DZ_DPCPU_PACER_BKT_TBL_RD 7
-#define	ESE_DZ_DPCPU_PACER_BKT_TBL_WR 6
-#define	ESE_DZ_DPCPU_PACER_TXQ_TBL_RD 5
-#define	ESE_DZ_DPCPU_PACER_TXQ_TBL_WR 4
-#define	ESE_DZ_DPCPU_PACER_TXQ_D_R_NI 3
-#define	ESE_DZ_DPCPU_PACER_TXQ_D_R_I 2
-#define	ESE_DZ_DPCPU_PACER_BKT_D_R_RD 1
-#define	ESE_DZ_DPCPU_PACER_BKT_D_RD 0
-#define	ESF_DZ_TXP_BKT_D_R_REQ_CLIENT_ID_LBN 0
-#define	ESF_DZ_TXP_BKT_D_R_REQ_CLIENT_ID_WIDTH 2
-#define	ESE_DZ_DPCPU_PACER_CPU_CLIENT 2
-#define	ESE_DZ_DPCPU_PACER_CMD_CTL_CLIENT 1
-#define	ESE_DZ_DPCPU_PACER_ALRT_CTL_CLIENT 0
-
-
-/* ES_TX_PACER_BKT_TBL_D_R_RSP */
-#define	ESF_DZ_TXP_BKT_TBL_D_R_RSP_DUE_TIME_WITH_MIN_BKT_LBN 21
-#define	ESF_DZ_TXP_BKT_TBL_D_R_RSP_DUE_TIME_WITH_MIN_BKT_WIDTH 26
-#define	ESF_DZ_TXP_BKT_TBL_D_R_RSP_DUE_TIME_LBN 5
-#define	ESF_DZ_TXP_BKT_TBL_D_R_RSP_DUE_TIME_WIDTH 16
-#define	ESF_DZ_TXP_BKT_TBL_D_R_RSP_OP_LBN 2
-#define	ESF_DZ_TXP_BKT_TBL_D_R_RSP_OP_WIDTH 3
-#define	ESE_DZ_DPCPU_PACER_BKT_TBL_RD 7
-#define	ESE_DZ_DPCPU_PACER_BKT_TBL_WR 6
-#define	ESE_DZ_DPCPU_PACER_TXQ_TBL_RD 5
-#define	ESE_DZ_DPCPU_PACER_TXQ_TBL_WR 4
-#define	ESE_DZ_DPCPU_PACER_TXQ_D_R_NI 3
-#define	ESE_DZ_DPCPU_PACER_TXQ_D_R_I 2
-#define	ESE_DZ_DPCPU_PACER_BKT_D_R_RD 1
-#define	ESE_DZ_DPCPU_PACER_BKT_D_RD 0
-#define	ESF_DZ_TXP_BKT_TBL_D_R_RSP_CLIENT_ID_LBN 0
-#define	ESF_DZ_TXP_BKT_TBL_D_R_RSP_CLIENT_ID_WIDTH 2
-#define	ESE_DZ_DPCPU_PACER_CPU_CLIENT 2
-#define	ESE_DZ_DPCPU_PACER_CMD_CTL_CLIENT 1
-#define	ESE_DZ_DPCPU_PACER_ALRT_CTL_CLIENT 0
-
-
-/* ES_TX_PACER_BKT_TBL_RD_REQ */
-#define	ESF_DZ_TXP_BKT_TBL_RD_REQ_BKT_ID_LBN 5
-#define	ESF_DZ_TXP_BKT_TBL_RD_REQ_BKT_ID_WIDTH 10
-#define	ESF_DZ_TXP_BKT_TBL_RD_REQ_OP_LBN 2
-#define	ESF_DZ_TXP_BKT_TBL_RD_REQ_OP_WIDTH 3
-#define	ESE_DZ_DPCPU_PACER_BKT_TBL_RD 7
-#define	ESE_DZ_DPCPU_PACER_BKT_TBL_WR 6
-#define	ESE_DZ_DPCPU_PACER_TXQ_TBL_RD 5
-#define	ESE_DZ_DPCPU_PACER_TXQ_TBL_WR 4
-#define	ESE_DZ_DPCPU_PACER_TXQ_D_R_NI 3
-#define	ESE_DZ_DPCPU_PACER_TXQ_D_R_I 2
-#define	ESE_DZ_DPCPU_PACER_BKT_D_R_RD 1
-#define	ESE_DZ_DPCPU_PACER_BKT_D_RD 0
-#define	ESF_DZ_TXP_BKT_TBL_RD_REQ_CLIENT_ID_LBN 0
-#define	ESF_DZ_TXP_BKT_TBL_RD_REQ_CLIENT_ID_WIDTH 2
-#define	ESE_DZ_DPCPU_PACER_CPU_CLIENT 2
-#define	ESE_DZ_DPCPU_PACER_CMD_CTL_CLIENT 1
-#define	ESE_DZ_DPCPU_PACER_ALRT_CTL_CLIENT 0
-
-
-/* ES_TX_PACER_BKT_TBL_RD_RSP */
-#define	ESF_DZ_TXP_BKT_TBL_RD_RSP_IDLE_LBN 97
-#define	ESF_DZ_TXP_BKT_TBL_RD_RSP_IDLE_WIDTH 1
-#define	ESF_DZ_TXP_BKT_TBL_RD_RSP_USED_LBN 96
-#define	ESF_DZ_TXP_BKT_TBL_RD_RSP_USED_WIDTH 1
-#define	ESF_DZ_TXP_BKT_TBL_RD_RSP_MAX_FILL_REG_LBN 94
-#define	ESF_DZ_TXP_BKT_TBL_RD_RSP_MAX_FILL_REG_WIDTH 2
-#define	ESF_DZ_TXP_BKT_TBL_RD_RSP_RATE_REC_LBN 78
-#define	ESF_DZ_TXP_BKT_TBL_RD_RSP_RATE_REC_WIDTH 16
-#define	ESF_DZ_TXP_BKT_TBL_RD_RSP_RATE_LBN 62
-#define	ESF_DZ_TXP_BKT_TBL_RD_RSP_RATE_WIDTH 16
-#define	ESF_DZ_TXP_BKT_TBL_RD_RSP_FILL_LEVEL_LBN 47
-#define	ESF_DZ_TXP_BKT_TBL_RD_RSP_FILL_LEVEL_WIDTH 15
-#define	ESF_DZ_TXP_BKT_TBL_RD_RSP_DUE_TIME_LBN 31
-#define	ESF_DZ_TXP_BKT_TBL_RD_RSP_DUE_TIME_WIDTH 16
-#define	ESF_DZ_TXP_BKT_TBL_RD_RSP_LAST_FILL_TIME_LBN 15
-#define	ESF_DZ_TXP_BKT_TBL_RD_RSP_LAST_FILL_TIME_WIDTH 16
-#define	ESF_DZ_TXP_BKT_TBL_RD_RSP_BKT_ID_LBN 5
-#define	ESF_DZ_TXP_BKT_TBL_RD_RSP_BKT_ID_WIDTH 10
-#define	ESF_DZ_TXP_BKT_TBL_RD_RSP_OP_LBN 2
-#define	ESF_DZ_TXP_BKT_TBL_RD_RSP_OP_WIDTH 3
-#define	ESE_DZ_DPCPU_PACER_BKT_TBL_RD 7
-#define	ESE_DZ_DPCPU_PACER_BKT_TBL_WR 6
-#define	ESE_DZ_DPCPU_PACER_TXQ_TBL_RD 5
-#define	ESE_DZ_DPCPU_PACER_TXQ_TBL_WR 4
-#define	ESE_DZ_DPCPU_PACER_TXQ_D_R_NI 3
-#define	ESE_DZ_DPCPU_PACER_TXQ_D_R_I 2
-#define	ESE_DZ_DPCPU_PACER_BKT_D_R_RD 1
-#define	ESE_DZ_DPCPU_PACER_BKT_D_RD 0
-#define	ESF_DZ_TXP_BKT_TBL_RD_RSP_CLIENT_ID_LBN 0
-#define	ESF_DZ_TXP_BKT_TBL_RD_RSP_CLIENT_ID_WIDTH 2
-#define	ESE_DZ_DPCPU_PACER_CPU_CLIENT 2
-#define	ESE_DZ_DPCPU_PACER_CMD_CTL_CLIENT 1
-#define	ESE_DZ_DPCPU_PACER_ALRT_CTL_CLIENT 0
-
-
-/* ES_TX_PACER_BKT_TBL_WR_REQ */
-#define	ESF_DZ_TXP_BKT_TBL_WR_REQ_IDLE_LBN 65
-#define	ESF_DZ_TXP_BKT_TBL_WR_REQ_IDLE_WIDTH 1
-#define	ESF_DZ_TXP_BKT_TBL_WR_REQ_USED_LBN 64
-#define	ESF_DZ_TXP_BKT_TBL_WR_REQ_USED_WIDTH 1
-#define	ESF_DZ_TXP_BKT_TBL_WR_REQ_MAX_FILL_REG_LBN 62
-#define	ESF_DZ_TXP_BKT_TBL_WR_REQ_MAX_FILL_REG_WIDTH 2
-#define	ESF_DZ_TXP_BKT_TBL_WR_REQ_RATE_REC_LBN 46
-#define	ESF_DZ_TXP_BKT_TBL_WR_REQ_RATE_REC_WIDTH 16
-#define	ESF_DZ_TXP_BKT_TBL_WR_REQ_RATE_LBN 30
-#define	ESF_DZ_TXP_BKT_TBL_WR_REQ_RATE_WIDTH 16
-#define	ESF_DZ_TXP_BKT_TBL_WR_REQ_FILL_LEVEL_LBN 15
-#define	ESF_DZ_TXP_BKT_TBL_WR_REQ_FILL_LEVEL_WIDTH 15
-#define	ESF_DZ_TXP_BKT_TBL_WR_REQ_BKT_ID_LBN 5
-#define	ESF_DZ_TXP_BKT_TBL_WR_REQ_BKT_ID_WIDTH 10
-#define	ESF_DZ_TXP_BKT_TBL_WR_REQ_OP_LBN 2
-#define	ESF_DZ_TXP_BKT_TBL_WR_REQ_OP_WIDTH 3
-#define	ESE_DZ_DPCPU_PACER_BKT_TBL_RD 7
-#define	ESE_DZ_DPCPU_PACER_BKT_TBL_WR 6
-#define	ESE_DZ_DPCPU_PACER_TXQ_TBL_RD 5
-#define	ESE_DZ_DPCPU_PACER_TXQ_TBL_WR 4
-#define	ESE_DZ_DPCPU_PACER_TXQ_D_R_NI 3
-#define	ESE_DZ_DPCPU_PACER_TXQ_D_R_I 2
-#define	ESE_DZ_DPCPU_PACER_BKT_D_R_RD 1
-#define	ESE_DZ_DPCPU_PACER_BKT_D_RD 0
-#define	ESF_DZ_TXP_BKT_TBL_WR_REQ_CLIENT_ID_LBN 0
-#define	ESF_DZ_TXP_BKT_TBL_WR_REQ_CLIENT_ID_WIDTH 2
-#define	ESE_DZ_DPCPU_PACER_CPU_CLIENT 2
-#define	ESE_DZ_DPCPU_PACER_CMD_CTL_CLIENT 1
-#define	ESE_DZ_DPCPU_PACER_ALRT_CTL_CLIENT 0
-
-
-/* ES_TX_PACER_TXQ_D_R_I_REQ */
-#define	ESF_DZ_TXP_TXQ_D_R_I_REQ_FRM_LEN_LBN 15
-#define	ESF_DZ_TXP_TXQ_D_R_I_REQ_FRM_LEN_WIDTH 14
-#define	ESF_DZ_TXP_TXQ_D_R_I_REQ_TXQ_ID_LBN 5
-#define	ESF_DZ_TXP_TXQ_D_R_I_REQ_TXQ_ID_WIDTH 10
-#define	ESF_DZ_TXP_TXQ_D_R_I_REQ_OP_LBN 2
-#define	ESF_DZ_TXP_TXQ_D_R_I_REQ_OP_WIDTH 3
-#define	ESE_DZ_DPCPU_PACER_BKT_TBL_RD 7
-#define	ESE_DZ_DPCPU_PACER_BKT_TBL_WR 6
-#define	ESE_DZ_DPCPU_PACER_TXQ_TBL_RD 5
-#define	ESE_DZ_DPCPU_PACER_TXQ_TBL_WR 4
-#define	ESE_DZ_DPCPU_PACER_TXQ_D_R_NI 3
-#define	ESE_DZ_DPCPU_PACER_TXQ_D_R_I 2
-#define	ESE_DZ_DPCPU_PACER_BKT_D_R_RD 1
-#define	ESE_DZ_DPCPU_PACER_BKT_D_RD 0
-#define	ESF_DZ_TXP_TXQ_D_R_I_REQ_CLIENT_ID_LBN 0
-#define	ESF_DZ_TXP_TXQ_D_R_I_REQ_CLIENT_ID_WIDTH 2
-#define	ESE_DZ_DPCPU_PACER_CPU_CLIENT 2
-#define	ESE_DZ_DPCPU_PACER_CMD_CTL_CLIENT 1
-#define	ESE_DZ_DPCPU_PACER_ALRT_CTL_CLIENT 0
-
-
-/* ES_TX_PACER_TXQ_TBL_RD_REQ */
-#define	ESF_DZ_TXP_TXQ_TBL_RD_REQ_TXQ_ID_LBN 5
-#define	ESF_DZ_TXP_TXQ_TBL_RD_REQ_TXQ_ID_WIDTH 10
-#define	ESF_DZ_TXP_TXQ_TBL_RD_REQ_OP_LBN 2
-#define	ESF_DZ_TXP_TXQ_TBL_RD_REQ_OP_WIDTH 3
-#define	ESE_DZ_DPCPU_PACER_BKT_TBL_RD 7
-#define	ESE_DZ_DPCPU_PACER_BKT_TBL_WR 6
-#define	ESE_DZ_DPCPU_PACER_TXQ_TBL_RD 5
-#define	ESE_DZ_DPCPU_PACER_TXQ_TBL_WR 4
-#define	ESE_DZ_DPCPU_PACER_TXQ_D_R_NI 3
-#define	ESE_DZ_DPCPU_PACER_TXQ_D_R_I 2
-#define	ESE_DZ_DPCPU_PACER_BKT_D_R_RD 1
-#define	ESE_DZ_DPCPU_PACER_BKT_D_RD 0
-#define	ESF_DZ_TXP_TXQ_TBL_RD_REQ_CLIENT_ID_LBN 0
-#define	ESF_DZ_TXP_TXQ_TBL_RD_REQ_CLIENT_ID_WIDTH 2
-#define	ESE_DZ_DPCPU_PACER_CPU_CLIENT 2
-#define	ESE_DZ_DPCPU_PACER_CMD_CTL_CLIENT 1
-#define	ESE_DZ_DPCPU_PACER_ALRT_CTL_CLIENT 0
-
-
-/* ES_TX_PACER_TXQ_TBL_RD_RSP */
-#define	ESF_DZ_TXP_TXQ_TBL_RD_RSP_MAX_BKT2_LBN 53
-#define	ESF_DZ_TXP_TXQ_TBL_RD_RSP_MAX_BKT2_WIDTH 10
-#define	ESF_DZ_TXP_TXQ_TBL_RD_RSP_MAX_BKT1_LBN 43
-#define	ESF_DZ_TXP_TXQ_TBL_RD_RSP_MAX_BKT1_WIDTH 10
-#define	ESF_DZ_TXP_TXQ_TBL_RD_RSP_MAX_BKT0_LBN 33
-#define	ESF_DZ_TXP_TXQ_TBL_RD_RSP_MAX_BKT0_WIDTH 10
-#define	ESF_DZ_TXP_TXQ_TBL_RD_RSP_MIN_BKT_LBN 23
-#define	ESF_DZ_TXP_TXQ_TBL_RD_RSP_MIN_BKT_WIDTH 10
-#define	ESF_DZ_TXP_TXQ_TBL_RD_RSP_LABEL_LBN 19
-#define	ESF_DZ_TXP_TXQ_TBL_RD_RSP_LABEL_WIDTH 4
-#define	ESF_DZ_TXP_TXQ_TBL_RD_RSP_PQ_FLAGS_LBN 16
-#define	ESF_DZ_TXP_TXQ_TBL_RD_RSP_PQ_FLAGS_WIDTH 3
-#define	ESF_DZ_TXP_TXQ_TBL_RD_RSP_DSBL_LBN 15
-#define	ESF_DZ_TXP_TXQ_TBL_RD_RSP_DSBL_WIDTH 1
-#define	ESF_DZ_TXP_TXQ_TBL_RD_RSP_TXQ_ID_LBN 5
-#define	ESF_DZ_TXP_TXQ_TBL_RD_RSP_TXQ_ID_WIDTH 10
-#define	ESF_DZ_TXP_TXQ_TBL_RD_RSP_OP_LBN 2
-#define	ESF_DZ_TXP_TXQ_TBL_RD_RSP_OP_WIDTH 3
-#define	ESE_DZ_DPCPU_PACER_BKT_TBL_RD 7
-#define	ESE_DZ_DPCPU_PACER_BKT_TBL_WR 6
-#define	ESE_DZ_DPCPU_PACER_TXQ_TBL_RD 5
-#define	ESE_DZ_DPCPU_PACER_TXQ_TBL_WR 4
-#define	ESE_DZ_DPCPU_PACER_TXQ_D_R_NI 3
-#define	ESE_DZ_DPCPU_PACER_TXQ_D_R_I 2
-#define	ESE_DZ_DPCPU_PACER_BKT_D_R_RD 1
-#define	ESE_DZ_DPCPU_PACER_BKT_D_RD 0
-#define	ESF_DZ_TXP_TXQ_TBL_RD_RSP_CLIENT_ID_LBN 0
-#define	ESF_DZ_TXP_TXQ_TBL_RD_RSP_CLIENT_ID_WIDTH 2
-#define	ESE_DZ_DPCPU_PACER_CPU_CLIENT 2
-#define	ESE_DZ_DPCPU_PACER_CMD_CTL_CLIENT 1
-#define	ESE_DZ_DPCPU_PACER_ALRT_CTL_CLIENT 0
-
-
-/* ES_TX_PACER_TXQ_TBL_WR_REQ */
-#define	ESF_DZ_TXP_TXQ_TBL_WR_REQ_MAX_BKT2_LBN 53
-#define	ESF_DZ_TXP_TXQ_TBL_WR_REQ_MAX_BKT2_WIDTH 10
-#define	ESF_DZ_TXP_TXQ_TBL_WR_REQ_MAX_BKT1_LBN 43
-#define	ESF_DZ_TXP_TXQ_TBL_WR_REQ_MAX_BKT1_WIDTH 10
-#define	ESF_DZ_TXP_TXQ_TBL_WR_REQ_MAX_BKT0_LBN 33
-#define	ESF_DZ_TXP_TXQ_TBL_WR_REQ_MAX_BKT0_WIDTH 10
-#define	ESF_DZ_TXP_TXQ_TBL_WR_REQ_MIN_BKT_LBN 23
-#define	ESF_DZ_TXP_TXQ_TBL_WR_REQ_MIN_BKT_WIDTH 10
-#define	ESF_DZ_TXP_TXQ_TBL_WR_REQ_LABEL_LBN 19
-#define	ESF_DZ_TXP_TXQ_TBL_WR_REQ_LABEL_WIDTH 4
-#define	ESF_DZ_TXP_TXQ_TBL_WR_REQ_PQ_FLAGS_LBN 16
-#define	ESF_DZ_TXP_TXQ_TBL_WR_REQ_PQ_FLAGS_WIDTH 3
-#define	ESF_DZ_TXP_TXQ_TBL_WR_REQ_DSBL_LBN 15
-#define	ESF_DZ_TXP_TXQ_TBL_WR_REQ_DSBL_WIDTH 1
-#define	ESF_DZ_TXP_TXQ_TBL_WR_REQ_TXQ_ID_LBN 5
-#define	ESF_DZ_TXP_TXQ_TBL_WR_REQ_TXQ_ID_WIDTH 10
-#define	ESF_DZ_TXP_TXQ_TBL_WR_REQ_OP_LBN 2
-#define	ESF_DZ_TXP_TXQ_TBL_WR_REQ_OP_WIDTH 3
-#define	ESE_DZ_DPCPU_PACER_BKT_TBL_RD 7
-#define	ESE_DZ_DPCPU_PACER_BKT_TBL_WR 6
-#define	ESE_DZ_DPCPU_PACER_TXQ_TBL_RD 5
-#define	ESE_DZ_DPCPU_PACER_TXQ_TBL_WR 4
-#define	ESE_DZ_DPCPU_PACER_TXQ_D_R_NI 3
-#define	ESE_DZ_DPCPU_PACER_TXQ_D_R_I 2
-#define	ESE_DZ_DPCPU_PACER_BKT_D_R_RD 1
-#define	ESE_DZ_DPCPU_PACER_BKT_D_RD 0
-#define	ESF_DZ_TXP_TXQ_TBL_WR_REQ_CLIENT_ID_LBN 0
-#define	ESF_DZ_TXP_TXQ_TBL_WR_REQ_CLIENT_ID_WIDTH 2
-#define	ESE_DZ_DPCPU_PACER_CPU_CLIENT 2
-#define	ESE_DZ_DPCPU_PACER_CMD_CTL_CLIENT 1
-#define	ESE_DZ_DPCPU_PACER_ALRT_CTL_CLIENT 0
 
 
 /* ES_TX_USER_DESC */
@@ -2572,8 +2427,12 @@ extern "C" {
 #define	ESF_DZ_TX_U_DC_RPTR_WIDTH 6
 #define	ESF_DZ_TX_U_SOFT6_B1R1_LBN 80
 #define	ESF_DZ_TX_U_SOFT6_B1R1_WIDTH 6
+#define	ESF_DZ_TX_U_CNTAG_LBN 68
+#define	ESF_DZ_TX_U_CNTAG_WIDTH 1
 #define	ESF_DZ_TX_U_SOFT5_B1R0_LBN 64
 #define	ESF_DZ_TX_U_SOFT5_B1R0_WIDTH 5
+#define	ESF_DZ_TX_U_TIMESTAMP_LBN 67
+#define	ESF_DZ_TX_U_TIMESTAMP_WIDTH 1
 #define	ESF_DZ_TX_U_PREFETCH_ACTIVE_LBN 66
 #define	ESF_DZ_TX_U_PREFETCH_ACTIVE_WIDTH 1
 #define	ESF_DZ_TX_U_PREFETCH_PENDING_LBN 65
@@ -2613,6 +2472,18 @@ extern "C" {
 #define	ESF_DZ_TX_U_SOFT18_B1R0_WIDTH 18
 #define	ESF_DZ_TX_U_SOFT16_B0R3_LBN 48
 #define	ESF_DZ_TX_U_SOFT16_B0R3_WIDTH 16
+#define	ESF_DZ_TX_U_EMERGENCY_FETCH_FAILED_LBN 56
+#define	ESF_DZ_TX_U_EMERGENCY_FETCH_FAILED_WIDTH 1
+#define	ESF_DZ_TX_U_PACER_BYPASS_OK_LBN 55
+#define	ESF_DZ_TX_U_PACER_BYPASS_OK_WIDTH 1
+#define	ESF_DZ_TX_U_STALE_DL_FETCH_LBN 54
+#define	ESF_DZ_TX_U_STALE_DL_FETCH_WIDTH 1
+#define	ESF_DZ_TX_U_ROLLBACK_IDX_REACHED_LBN 52
+#define	ESF_DZ_TX_U_ROLLBACK_IDX_REACHED_WIDTH 1
+#define	ESF_DZ_TX_U_ROLLBACK_ACTIVE_LBN 51
+#define	ESF_DZ_TX_U_ROLLBACK_ACTIVE_WIDTH 1
+#define	ESF_DZ_TX_U_QUEUE_PAUSED_LBN 50
+#define	ESF_DZ_TX_U_QUEUE_PAUSED_WIDTH 1
 #define	ESF_DZ_TX_U_QUEUE_ENABLED_LBN 49
 #define	ESF_DZ_TX_U_QUEUE_ENABLED_WIDTH 1
 #define	ESF_DZ_TX_U_FLUSH_PENDING_LBN 48
@@ -2625,7 +2496,7 @@ extern "C" {
 #define	ESF_DZ_TX_U_OWNER_ID_WIDTH 12
 #define	ESF_DZ_TX_U_SOFT12_B0R1_LBN 16
 #define	ESF_DZ_TX_U_SOFT12_B0R1_WIDTH 12
-#define	ESF_DZ_TX_U_DSCR_SIZE_LBN 0
+#define	ESF_DZ_TX_U_DSCR_SIZE_LBN 13
 #define	ESF_DZ_TX_U_DSCR_SIZE_WIDTH 3
 #define	ESF_DZ_TX_U_SOFT3_B0R0_LBN 0
 #define	ESF_DZ_TX_U_SOFT3_B0R0_WIDTH 3
@@ -2642,9 +2513,27 @@ extern "C" {
 #define	ESF_DZ_TX_FINFO_SRCDST_WIDTH 16
 
 
+/* ES_TX_VLAN_DESC */
+#define	ESF_DZ_TX_DESC_IS_OPT_LBN 63
+#define	ESF_DZ_TX_DESC_IS_OPT_WIDTH 1
+#define	ESF_DZ_TX_OPTION_TYPE_LBN 60
+#define	ESF_DZ_TX_OPTION_TYPE_WIDTH 3
+#define	ESE_DZ_TX_OPTION_DESC_TSO 7
+#define	ESE_DZ_TX_OPTION_DESC_VLAN 6
+#define	ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0
+#define	ESF_DZ_TX_VLAN_OP_LBN 32
+#define	ESF_DZ_TX_VLAN_OP_WIDTH 2
+#define	ESF_DZ_TX_VLAN_TAG2_LBN 16
+#define	ESF_DZ_TX_VLAN_TAG2_WIDTH 16
+#define	ESF_DZ_TX_VLAN_TAG1_LBN 0
+#define	ESF_DZ_TX_VLAN_TAG1_WIDTH 16
+
+
 /* ES_b2t_cpl_rsp */
-#define	ESF_DZ_B2T_CPL_RSP_CPL_ECC_LBN 268
+#define	ESF_DZ_B2T_CPL_RSP_CPL_ECC_LBN 284
 #define	ESF_DZ_B2T_CPL_RSP_CPL_ECC_WIDTH 32
+#define	ESF_DZ_B2T_CPL_RSP_CPL_EOT_LBN 283
+#define	ESF_DZ_B2T_CPL_RSP_CPL_EOT_WIDTH 1
 #define	ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW0_LBN 27
 #define	ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW0_WIDTH 32
 #define	ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW1_LBN 59
@@ -2663,8 +2552,6 @@ extern "C" {
 #define	ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW7_WIDTH 32
 #define	ESF_DZ_B2T_CPL_RSP_CPL_DATA_LBN 27
 #define	ESF_DZ_B2T_CPL_RSP_CPL_DATA_WIDTH 256
-#define	ESF_DZ_B2T_CPL_RSP_CPL_EOT_LBN 283
-#define	ESF_DZ_B2T_CPL_RSP_CPL_EOT_WIDTH -15
 #define	ESF_DZ_B2T_CPL_RSP_CPL_ERROR_LBN 26
 #define	ESF_DZ_B2T_CPL_RSP_CPL_ERROR_WIDTH 1
 #define	ESF_DZ_B2T_CPL_RSP_CPL_LAST_LBN 25
@@ -2677,95 +2564,321 @@ extern "C" {
 #define	ESF_DZ_B2T_CPL_RSP_CPL_ADRS_WIDTH 7
 
 
+/* ES_fltr_info_wrd_mac_to_rx */
+#define	ESF_DZ_FLTR_INFO_MAC_TO_RX_RESERVED2_LBN 112
+#define	ESF_DZ_FLTR_INFO_MAC_TO_RX_RESERVED2_WIDTH 16
+#define	ESF_DZ_FLTR_INFO_MAC_TO_RX_TIMESTAMP2_LBN 96
+#define	ESF_DZ_FLTR_INFO_MAC_TO_RX_TIMESTAMP2_WIDTH 16
+#define	ESF_DZ_FLTR_INFO_MAC_TO_RX_TIMESTAMP1_LBN 80
+#define	ESF_DZ_FLTR_INFO_MAC_TO_RX_TIMESTAMP1_WIDTH 16
+#define	ESF_DZ_FLTR_INFO_MAC_TO_RX_TIMESTAMP0_LBN 64
+#define	ESF_DZ_FLTR_INFO_MAC_TO_RX_TIMESTAMP0_WIDTH 16
+#define	ESF_DZ_FLTR_INFO_MAC_TO_RX_RESERVED1_LBN 48
+#define	ESF_DZ_FLTR_INFO_MAC_TO_RX_RESERVED1_WIDTH 16
+#define	ESF_DZ_FLTR_INFO_MAC_TO_RX_IPSEC_SA_LBN 32
+#define	ESF_DZ_FLTR_INFO_MAC_TO_RX_IPSEC_SA_WIDTH 16
+#define	ESF_DZ_FLTR_INFO_MAC_TO_RX_RESERVED0_LBN 8
+#define	ESF_DZ_FLTR_INFO_MAC_TO_RX_RESERVED0_WIDTH 24
+#define	ESF_DZ_FLTR_INFO_MAC_TO_RX_IPSEC_LBN 7
+#define	ESF_DZ_FLTR_INFO_MAC_TO_RX_IPSEC_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_MAC_TO_RX_PRIORITY_LBN 4
+#define	ESF_DZ_FLTR_INFO_MAC_TO_RX_PRIORITY_WIDTH 3
+#define	ESF_DZ_FLTR_INFO_MAC_TO_RX_SRC_LBN 0
+#define	ESF_DZ_FLTR_INFO_MAC_TO_RX_SRC_WIDTH 4
+
+
+/* ES_fltr_info_wrd_mc_pdma */
+#define	ESF_DZ_FLTR_INFO_MC_PDMA_FLTR_OUT_LBN 64
+#define	ESF_DZ_FLTR_INFO_MC_PDMA_FLTR_OUT_WIDTH 16
+#define	ESE_DZ_FLTR_MULTICAST_VLAN 512
+#define	ESE_DZ_FLTR_MAC_VLAN 256
+#define	ESE_DZ_FLTR_STRUCTURED7 128
+#define	ESE_DZ_FLTR_STRUCTURED6 64
+#define	ESE_DZ_FLTR_STRUCTURED5 32
+#define	ESE_DZ_FLTR_STRUCTURED4 16
+#define	ESE_DZ_FLTR_STRUCTURED3 8
+#define	ESE_DZ_FLTR_STRUCTURED2 4
+#define	ESE_DZ_FLTR_STRUCTURED1 2
+#define	ESE_DZ_FLTR_STRUCTURED0 1
+#define	ESF_DZ_FLTR_INFO_MC_PDMA_TIMESTAMP_DW0_LBN 16
+#define	ESF_DZ_FLTR_INFO_MC_PDMA_TIMESTAMP_DW0_WIDTH 32
+#define	ESF_DZ_FLTR_INFO_MC_PDMA_TIMESTAMP_DW1_LBN 48
+#define	ESF_DZ_FLTR_INFO_MC_PDMA_TIMESTAMP_DW1_WIDTH 16
+#define	ESF_DZ_FLTR_INFO_MC_PDMA_TIMESTAMP_LBN 16
+#define	ESF_DZ_FLTR_INFO_MC_PDMA_TIMESTAMP_WIDTH 48
+#define	ESF_DZ_FLTR_INFO_MC_PDMA_DST_LBN 8
+#define	ESF_DZ_FLTR_INFO_MC_PDMA_DST_WIDTH 8
+#define	ESE_DZ_DST_NCSI 64
+#define	ESE_DZ_DST_PORT0 32
+#define	ESE_DZ_DST_PORT1 16
+#define	ESE_DZ_DST_PORT0_IPSEC 8
+#define	ESE_DZ_DST_PORT1_IPSEC 4
+#define	ESE_DZ_DST_PM 2
+#define	ESE_DZ_DST_TIMESTAMP 1
+#define	ESF_DZ_FLTR_INFO_MC_PDMA_PRIORITY_LBN 4
+#define	ESF_DZ_FLTR_INFO_MC_PDMA_PRIORITY_WIDTH 4
+#define	ESF_DZ_FLTR_INFO_MC_PDMA_SRC_LBN 0
+#define	ESF_DZ_FLTR_INFO_MC_PDMA_SRC_WIDTH 4
+
+
+/* ES_fltr_info_wrd_rxdi_to_rxdp */
+#define	ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_INNER_VLAN_LBN 112
+#define	ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_INNER_VLAN_WIDTH 16
+#define	ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_OUTER_VLAN_LBN 96
+#define	ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_OUTER_VLAN_WIDTH 16
+#define	ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_THASH1_LBN 80
+#define	ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_THASH1_WIDTH 16
+#define	ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_THASH0_LBN 64
+#define	ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_THASH0_WIDTH 16
+#define	ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_TIMESTAMP1_LBN 48
+#define	ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_TIMESTAMP1_WIDTH 16
+#define	ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_TIMESTAMP0_LBN 32
+#define	ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_TIMESTAMP0_WIDTH 16
+#define	ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_CNP_LBN 31
+#define	ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_CNP_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_IVP_LBN 30
+#define	ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_IVP_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_OVP_LBN 29
+#define	ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_OVP_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_ST2_LBN 28
+#define	ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_ST2_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_ST1_LBN 27
+#define	ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_ST1_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_ST0_LBN 26
+#define	ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_ST0_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_RX_QID_LBN 16
+#define	ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_RX_QID_WIDTH 10
+#define	ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_DST_HOST_LBN 15
+#define	ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_DST_HOST_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_DST_MC_LBN 14
+#define	ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_DST_MC_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_DST_P0_LBN 13
+#define	ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_DST_P0_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_DST_P1_LBN 12
+#define	ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_DST_P1_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_RESERVED1_LBN 11
+#define	ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_RESERVED1_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_DST_CRF_LBN 10
+#define	ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_DST_CRF_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_RESERVED0_LBN 9
+#define	ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_RESERVED0_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_REPLAY_LBN 8
+#define	ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_REPLAY_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_IPSEC_LBN 7
+#define	ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_IPSEC_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_PRIORITY_LBN 4
+#define	ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_PRIORITY_WIDTH 3
+#define	ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_SRC_LBN 0
+#define	ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_SRC_WIDTH 4
+
+
+/* ES_fltr_info_wrd_rxdp_to_host */
+#define	ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RESERVED3_LBN 33
+#define	ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RESERVED3_WIDTH 31
+#define	ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RMON_SOFT_LBN 32
+#define	ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RMON_SOFT_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RESERVED2_LBN 27
+#define	ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RESERVED2_WIDTH 5
+#define	ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RX_QID_LBN 16
+#define	ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RX_QID_WIDTH 11
+#define	ESF_DZ_FLTR_INFO_RXDP_TO_HOST_DST_HOST_LBN 15
+#define	ESF_DZ_FLTR_INFO_RXDP_TO_HOST_DST_HOST_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_RXDP_TO_HOST_DST_MC_LBN 14
+#define	ESF_DZ_FLTR_INFO_RXDP_TO_HOST_DST_MC_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_RXDP_TO_HOST_DST_P0_LBN 13
+#define	ESF_DZ_FLTR_INFO_RXDP_TO_HOST_DST_P0_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_RXDP_TO_HOST_DST_P1_LBN 12
+#define	ESF_DZ_FLTR_INFO_RXDP_TO_HOST_DST_P1_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RESERVED1_LBN 11
+#define	ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RESERVED1_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_RXDP_TO_HOST_DST_CRF_LBN 10
+#define	ESF_DZ_FLTR_INFO_RXDP_TO_HOST_DST_CRF_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RESERVED0_LBN 9
+#define	ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RESERVED0_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_RXDP_TO_HOST_REPLAY_LBN 8
+#define	ESF_DZ_FLTR_INFO_RXDP_TO_HOST_REPLAY_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_RXDP_TO_HOST_IPSEC_LBN 7
+#define	ESF_DZ_FLTR_INFO_RXDP_TO_HOST_IPSEC_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_RXDP_TO_HOST_PRIORITY_LBN 4
+#define	ESF_DZ_FLTR_INFO_RXDP_TO_HOST_PRIORITY_WIDTH 3
+#define	ESF_DZ_FLTR_INFO_RXDP_TO_HOST_SRC_LBN 0
+#define	ESF_DZ_FLTR_INFO_RXDP_TO_HOST_SRC_WIDTH 4
+
+
+/* ES_fltr_info_wrd_tx_to_mac */
+#define	ESF_DZ_FLTR_INFO_TX_TO_MAC_PRV_LBN 63
+#define	ESF_DZ_FLTR_INFO_TX_TO_MAC_PRV_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_TX_TO_MAC_LB_LBN 62
+#define	ESF_DZ_FLTR_INFO_TX_TO_MAC_LB_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_TX_TO_MAC_MS0_LBN 61
+#define	ESF_DZ_FLTR_INFO_TX_TO_MAC_MS0_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_TX_TO_MAC_MS1_LBN 60
+#define	ESF_DZ_FLTR_INFO_TX_TO_MAC_MS1_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_TX_TO_MAC_NDI_LBN 59
+#define	ESF_DZ_FLTR_INFO_TX_TO_MAC_NDI_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_TX_TO_MAC_RESERVED2_LBN 48
+#define	ESF_DZ_FLTR_INFO_TX_TO_MAC_RESERVED2_WIDTH 11
+#define	ESF_DZ_FLTR_INFO_TX_TO_MAC_IPSEC_SA_LBN 32
+#define	ESF_DZ_FLTR_INFO_TX_TO_MAC_IPSEC_SA_WIDTH 16
+#define	ESF_DZ_FLTR_INFO_TX_TO_MAC_TX_STACK_ID_LBN 24
+#define	ESF_DZ_FLTR_INFO_TX_TO_MAC_TX_STACK_ID_WIDTH 8
+#define	ESF_DZ_FLTR_INFO_TX_TO_MAC_TX_DOMAIN_LBN 16
+#define	ESF_DZ_FLTR_INFO_TX_TO_MAC_TX_DOMAIN_WIDTH 8
+#define	ESF_DZ_FLTR_INFO_TX_TO_MAC_RESERVED1_LBN 14
+#define	ESF_DZ_FLTR_INFO_TX_TO_MAC_RESERVED1_WIDTH 2
+#define	ESF_DZ_FLTR_INFO_TX_TO_MAC_DST_P0_LBN 13
+#define	ESF_DZ_FLTR_INFO_TX_TO_MAC_DST_P0_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_TX_TO_MAC_DST_P1_LBN 12
+#define	ESF_DZ_FLTR_INFO_TX_TO_MAC_DST_P1_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_TX_TO_MAC_DST_IP0_LBN 11
+#define	ESF_DZ_FLTR_INFO_TX_TO_MAC_DST_IP0_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_TX_TO_MAC_DST_IP1_LBN 10
+#define	ESF_DZ_FLTR_INFO_TX_TO_MAC_DST_IP1_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_TX_TO_MAC_DST_PM_LBN 9
+#define	ESF_DZ_FLTR_INFO_TX_TO_MAC_DST_PM_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_TX_TO_MAC_RESERVED0_LBN 8
+#define	ESF_DZ_FLTR_INFO_TX_TO_MAC_RESERVED0_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_TX_TO_MAC_IPSEC_LBN 7
+#define	ESF_DZ_FLTR_INFO_TX_TO_MAC_IPSEC_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_TX_TO_MAC_PRIORITY_LBN 4
+#define	ESF_DZ_FLTR_INFO_TX_TO_MAC_PRIORITY_WIDTH 3
+#define	ESF_DZ_FLTR_INFO_TX_TO_MAC_SRC_LBN 0
+#define	ESF_DZ_FLTR_INFO_TX_TO_MAC_SRC_WIDTH 4
+
+
+/* ES_fltr_info_wrd_txdi_to_txdp */
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_INNER_VLAN_LBN 112
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_INNER_VLAN_WIDTH 16
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_OUTER_VLAN_LBN 96
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_OUTER_VLAN_WIDTH 16
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_CNP_LBN 95
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_CNP_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_IVP_LBN 94
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_IVP_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_OVP_LBN 93
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_OVP_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_RESERVED4_LBN 90
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_RESERVED4_WIDTH 3
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_QID_LBN 80
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_QID_WIDTH 10
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_VRI_LBN 79
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_VRI_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_RESERVED3_LBN 78
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_RESERVED3_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_MTU_DIV4_LBN 66
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_MTU_DIV4_WIDTH 12
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_VRI_OP_LBN 64
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_VRI_OP_WIDTH 2
+#define	ESE_DZ_VRI_OP_INSERT_REPLACE 3
+#define	ESE_DZ_VRI_OP_INSERT_INSERT 2
+#define	ESE_DZ_VRI_OP_REPLACE 1
+#define	ESE_DZ_VRI_OP_INSERT 0
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_PRV_LBN 63
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_PRV_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_LB_LBN 62
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_LB_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_MS0_LBN 61
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_MS0_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_MS1_LBN 60
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_MS1_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_NDI_LBN 59
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_NDI_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_TXDP_CONTEXT_OUT_LBN 48
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_TXDP_CONTEXT_OUT_WIDTH 11
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_IPSEC_SA_LBN 32
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_IPSEC_SA_WIDTH 16
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_TX_STACK_ID_LBN 24
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_TX_STACK_ID_WIDTH 8
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_TX_DOMAIN_LBN 16
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_TX_DOMAIN_WIDTH 8
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_RESERVED1_LBN 14
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_RESERVED1_WIDTH 2
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_DST_P0_LBN 13
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_DST_P0_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_DST_P1_LBN 12
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_DST_P1_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_DST_IP0_LBN 11
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_DST_IP0_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_DST_IP1_LBN 10
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_DST_IP1_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_DST_PM_LBN 9
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_DST_PM_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_RESERVED0_LBN 8
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_RESERVED0_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_IPSEC_LBN 7
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_IPSEC_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_PRIORITY_LBN 4
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_PRIORITY_WIDTH 3
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_SRC_LBN 0
+#define	ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_SRC_WIDTH 4
+
+
+/* ES_fltr_info_wrd_txdp_to_txdi */
+#define	ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_VLAN_OP_LBN 62
+#define	ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_VLAN_OP_WIDTH 2
+#define	ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_RESERVED1_LBN 58
+#define	ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_RESERVED1_WIDTH 4
+#define	ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_TX_QID_LBN 48
+#define	ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_TX_QID_WIDTH 10
+#define	ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_INNER_VLAN_LBN 32
+#define	ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_INNER_VLAN_WIDTH 16
+#define	ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_OUTER_VLAN_LBN 16
+#define	ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_OUTER_VLAN_WIDTH 16
+#define	ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_TXDP_CONTEXT_IN_LBN 5
+#define	ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_TXDP_CONTEXT_IN_WIDTH 11
+#define	ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_RESERVED0_LBN 4
+#define	ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_RESERVED0_WIDTH 1
+#define	ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_SRC_LBN 0
+#define	ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_SRC_WIDTH 4
+
+
+/* ES_nwk_ev_merge_blk_cmd */
+#define	ESF_DZ_EV_MERGE_BLK_COMMAND_OP_LBN 28
+#define	ESF_DZ_EV_MERGE_BLK_COMMAND_OP_WIDTH 4
+#define	ESE_DZ_EV_MERGE_BLK_COMMAND_OP_FLUSH 2
+#define	ESE_DZ_EV_MERGE_BLK_COMMAND_OP_ENABLE 1
+#define	ESE_DZ_EV_MERGE_BLK_COMMAND_OP_DISABLE 0
+#define	ESF_DZ_EV_MERGE_BLK_COMMAND_BUSY_LBN 31
+#define	ESF_DZ_EV_MERGE_BLK_COMMAND_BUSY_WIDTH 1
+#define	ESF_DZ_EV_MERGE_BLK_COMMAND_EVQ_IDX_LBN 0
+#define	ESF_DZ_EV_MERGE_BLK_COMMAND_EVQ_IDX_WIDTH 11
+
+
+/* ES_txpm2ini_cpl_rsp */
+#define	ESF_DZ_TXPM2INI_CPL_RSP_CPL_ECC_LBN 284
+#define	ESF_DZ_TXPM2INI_CPL_RSP_CPL_ECC_WIDTH 32
+#define	ESF_DZ_TXPM2INI_CPL_RSP_CPL_EOT_LBN 283
+#define	ESF_DZ_TXPM2INI_CPL_RSP_CPL_EOT_WIDTH 1
+#define	ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW0_LBN 27
+#define	ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW0_WIDTH 32
+#define	ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW1_LBN 59
+#define	ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW1_WIDTH 32
+#define	ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW2_LBN 91
+#define	ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW2_WIDTH 32
+#define	ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW3_LBN 123
+#define	ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW3_WIDTH 32
+#define	ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW4_LBN 155
+#define	ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW4_WIDTH 32
+#define	ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW5_LBN 187
+#define	ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW5_WIDTH 32
+#define	ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW6_LBN 219
+#define	ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW6_WIDTH 32
+#define	ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW7_LBN 251
+#define	ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW7_WIDTH 32
+#define	ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_LBN 27
+#define	ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_WIDTH 256
+#define	ESF_DZ_TXPM2INI_CPL_RSP_CPL_ERROR_LBN 26
+#define	ESF_DZ_TXPM2INI_CPL_RSP_CPL_ERROR_WIDTH 1
+#define	ESF_DZ_TXPM2INI_CPL_RSP_CPL_LAST_LBN 25
+#define	ESF_DZ_TXPM2INI_CPL_RSP_CPL_LAST_WIDTH 1
+#define	ESF_DZ_TXPM2INI_CPL_RSP_CPL_TAG_LBN 19
+#define	ESF_DZ_TXPM2INI_CPL_RSP_CPL_TAG_WIDTH 6
+#define	ESF_DZ_TXPM2INI_CPL_RSP_CPL_LEN_LBN 7
+#define	ESF_DZ_TXPM2INI_CPL_RSP_CPL_LEN_WIDTH 12
+#define	ESF_DZ_TXPM2INI_CPL_RSP_CPL_ADRS_LBN 0
+#define	ESF_DZ_TXPM2INI_CPL_RSP_CPL_ADRS_WIDTH 7
+
 
-/* Enum DPCPU_INSTR_BRTYPE */
-#define	ESE_DZ_BNEZAL 19
-#define	ESE_DZ_BEQZAL 18
-#define	ESE_DZ_BGEZAL 17
-#define	ESE_DZ_BLTZAL 16
-#define	ESE_DZ_BNEZ 3
-#define	ESE_DZ_BEQZ 2
-#define	ESE_DZ_BGEZ 1
-#define	ESE_DZ_BLTZ 0
-
-/* Enum DPCPU_INSTR_FUNCT */
-#define	ESE_DZ_MASKMOD 44
-#define	ESE_DZ_SLTU 43
-#define	ESE_DZ_SLT 42
-#define	ESE_DZ_INCMOD 40
-#define	ESE_DZ_NOR 39
-#define	ESE_DZ_XOR 38
-#define	ESE_DZ_OR 37
-#define	ESE_DZ_AND 36
-#define	ESE_DZ_SUBU 35
-#define	ESE_DZ_SUB 34
-#define	ESE_DZ_ADDU 33
-#define	ESE_DZ_ADD 32
-#define	ESE_DZ_MULT 25
-#define	ESE_DZ_MFLO 18
-#define	ESE_DZ_MFHI 16
-#define	ESE_DZ_JALR 9
-#define	ESE_DZ_JR 8
-#define	ESE_DZ_SRAV 7
-#define	ESE_DZ_SRLV 6
-#define	ESE_DZ_SLLV 4
-#define	ESE_DZ_SRA 3
-#define	ESE_DZ_SRL 2
-#define	ESE_DZ_SLL 0
-
-/* Enum DPCPU_INSTR_OP */
-#define	ESE_DZ_LM_MSG 49
-#define	ESE_DZ_MSG 48
-#define	ESE_DZ_SHA 43
-#define	ESE_DZ_SBA 42
-#define	ESE_DZ_SH 41
-#define	ESE_DZ_SB 40
-#define	ESE_DZ_LHUA 39
-#define	ESE_DZ_LBUA 38
-#define	ESE_DZ_LHU 37
-#define	ESE_DZ_LBU 36
-#define	ESE_DZ_LHA 35
-#define	ESE_DZ_LBA 34
-#define	ESE_DZ_LH 33
-#define	ESE_DZ_LB 32
-#define	ESE_DZ_BGTU 31
-#define	ESE_DZ_BLEU 30
-#define	ESE_DZ_MODI 28
-#define	ESE_DZ_NEGU 27
-#define	ESE_DZ_NEG 26
-#define	ESE_DZ_LI 25
-#define	ESE_DZ_INCMODI 24
-#define	ESE_DZ_BGT 23
-#define	ESE_DZ_BLE 22
-#define	ESE_DZ_BBS 21
-#define	ESE_DZ_BBC 20
-#define	ESE_DZ_JAL_EVT 19
-#define	ESE_DZ_J_EVT 18
-#define	ESE_DZ_HALT 16
-#define	ESE_DZ_NORI 15
-#define	ESE_DZ_XORI 14
-#define	ESE_DZ_ORI 13
-#define	ESE_DZ_ANDI 12
-#define	ESE_DZ_SLTIU 11
-#define	ESE_DZ_SLTI 10
-#define	ESE_DZ_ADDIU 9
-#define	ESE_DZ_ADDI 8
-#define	ESE_DZ_BGTZ 7
-#define	ESE_DZ_BLEZ 6
-#define	ESE_DZ_BNE 5
-#define	ESE_DZ_BEQ 4
-#define	ESE_DZ_JAL 3
-#define	ESE_DZ_J 2
-#define	ESE_DZ_BRANCH 1
-#define	ESE_DZ_REG2REG 0
-
-/* Enum DPCPU_MSG_DIR */
-#define	ESE_DPCPU_MSG_DZ_OUTB 0x1
-#define	ESE_DPCPU_MSG_DZ_INB 0x0
-
-/* Enum DPCPU_PDBUS_OP */
-#define	ESE_DPCPU_PDBUS_DZ_RD 0x1
-#define	ESE_DPCPU_PDBUS_DZ_WR 0x0
 
 /* Enum INI_OP */
 #define	ESE_DZ_RD_COMPL 0x3
@@ -2778,6 +2891,19 @@ extern "C" {
 #define	ESE_DZ_MSI 0x1
 #define	ESE_DZ_MSIX 0x0
 
+/* Enum MC_PDMA_BUFFER_ID */
+#define	ESE_DZ_MC_PDMA_BUFFER_ALL 4
+#define	ESE_DZ_MC_PDMA_BUFFER_RXDP 3
+#define	ESE_DZ_MC_PDMA_BUFFER_NCSI 2
+#define	ESE_DZ_MC_PDMA_BUFFER_NWPORT1 1
+#define	ESE_DZ_MC_PDMA_BUFFER_NWPORT0 0
+
+/* Enum MC_PDMA_INTERFACE_ID */
+#define	ESE_DZ_MC_PDMA_INTERFACE_RXDP 3
+#define	ESE_DZ_MC_PDMA_INTERFACE_NCSI 2
+#define	ESE_DZ_MC_PDMA_INTERFACE_NWPORT1 1
+#define	ESE_DZ_MC_PDMA_INTERFACE_NWPORT0 0
+
 /* Enum PKT_STRM_CTL */
 #define	ESE_DZ_EOP_TRUNC 0x3
 #define	ESE_DZ_EOP_CRC_ERR 0x2
diff --git a/sys/dev/sfxge/common/efx_regs_mcdi.h b/sys/dev/sfxge/common/efx_regs_mcdi.h
index 9016ca9a4766..bd35970768ec 100644
--- a/sys/dev/sfxge/common/efx_regs_mcdi.h
+++ b/sys/dev/sfxge/common/efx_regs_mcdi.h
@@ -1,5 +1,5 @@
 /*-
- * Copyright 2008-2011 Solarflare Communications Inc.  All rights reserved.
+ * Copyright 2008-2013 Solarflare Communications Inc.  All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -39,6 +39,17 @@
 #define MC_FW_STATE_BOOTING (4)
 /* The Scheduler has started. */
 #define MC_FW_STATE_SCHED (8)
+/* If this is set in MC_RESET_STATE_REG then it should be
+ * possible to jump into IMEM without loading code from flash.
+ * Unlike a warm boot, assume DMEM has been reloaded, so that
+ * the MC persistent data must be reinitialised. */
+#define MC_FW_TEPID_BOOT_OK (16)
+/* We have entered the main firmware via recovery mode.  This
+ * means that MC persistent data must be reinitialised, but that
+ * we shouldn't touch PCIe config. */
+#define MC_FW_RECOVERY_MODE_PCIE_INIT_OK (32)
+/* BIST state has been initialized */
+#define MC_FW_BIST_INIT_OK (128)
 
 /* Siena MC shared memmory offsets */
 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
@@ -57,6 +68,9 @@
 #define MC_STATUS_DWORD_REBOOT (0xb007b007)
 #define MC_STATUS_DWORD_ASSERT (0xdeaddead)
 
+/* Check whether an mcfw version (in host order) belongs to a bootloader */
+#define MC_FW_VERSION_IS_BOOTLOADER(_v) (((_v) >> 16) == 0xb007)
+
 /* The current version of the MCDI protocol.
  *
  * Note that the ROM burnt into the card only talks V0, so at the very
@@ -72,7 +86,7 @@
 
 /* MCDI version 1
  *
- * Each MCDI request starts with an MCDI_HEADER, which is a 32byte
+ * Each MCDI request starts with an MCDI_HEADER, which is a 32bit
  * structure, filled in by the client.
  *
  *       0       7  8     16    20     22  23  24    31
@@ -109,9 +123,11 @@
 #define MCDI_HEADER_DATALEN_LBN 8
 #define MCDI_HEADER_DATALEN_WIDTH 8
 #define MCDI_HEADER_SEQ_LBN 16
-#define MCDI_HEADER_RSVD_LBN 20
-#define MCDI_HEADER_RSVD_WIDTH 2
 #define MCDI_HEADER_SEQ_WIDTH 4
+#define MCDI_HEADER_RSVD_LBN 20
+#define MCDI_HEADER_RSVD_WIDTH 1
+#define MCDI_HEADER_NOT_EPOCH_LBN 21
+#define MCDI_HEADER_NOT_EPOCH_WIDTH 1
 #define MCDI_HEADER_ERROR_LBN 22
 #define MCDI_HEADER_ERROR_WIDTH 1
 #define MCDI_HEADER_RESPONSE_LBN 23
@@ -122,12 +138,16 @@
 #define MCDI_HEADER_XFLAGS_EVREQ 0x01
 
 /* Maximum number of payload bytes */
+#define MCDI_CTL_SDU_LEN_MAX_V1 0xfc
+#define MCDI_CTL_SDU_LEN_MAX_V2 0x400
+
 #ifdef WITH_MCDI_V2
-#define MCDI_CTL_SDU_LEN_MAX 0x400
+#define MCDI_CTL_SDU_LEN_MAX MCDI_CTL_SDU_LEN_MAX_V2
 #else
-#define MCDI_CTL_SDU_LEN_MAX 0xfc
+#define MCDI_CTL_SDU_LEN_MAX MCDI_CTL_SDU_LEN_MAX_V1
 #endif
 
+
 /* The MC can generate events for two reasons:
  *   - To complete a shared memory request if XFLAGS_EVREQ was set
  *   - As a notification (link state, i2c event), controlled
@@ -171,22 +191,114 @@
 #define FSE_AZ_EV_CODE_MCDI_EVRESPONSE 0xc
 
 
+/* Operation not permitted. */
+#define MC_CMD_ERR_EPERM 1
 /* Non-existent command target */
 #define MC_CMD_ERR_ENOENT 2
 /* assert() has killed the MC */
 #define MC_CMD_ERR_EINTR 4
+/* I/O failure */
+#define MC_CMD_ERR_EIO 5
+/* Already exists */
+#define MC_CMD_ERR_EEXIST 6
+/* Try again */
+#define MC_CMD_ERR_EAGAIN 11
+/* Out of memory */
+#define MC_CMD_ERR_ENOMEM 12
 /* Caller does not hold required locks */
 #define MC_CMD_ERR_EACCES 13
 /* Resource is currently unavailable (e.g. lock contention) */
 #define MC_CMD_ERR_EBUSY 16
+/* No such device */
+#define MC_CMD_ERR_ENODEV 19
 /* Invalid argument to target */
 #define MC_CMD_ERR_EINVAL 22
+/* Broken pipe */
+#define MC_CMD_ERR_EPIPE 32
+/* Read-only */
+#define MC_CMD_ERR_EROFS 30
+/* Out of range */
+#define MC_CMD_ERR_ERANGE 34
 /* Non-recursive resource is already acquired */
 #define MC_CMD_ERR_EDEADLK 35
 /* Operation not implemented */
 #define MC_CMD_ERR_ENOSYS 38
 /* Operation timed out */
 #define MC_CMD_ERR_ETIME 62
+/* Link has been severed */
+#define MC_CMD_ERR_ENOLINK 67
+/* Protocol error */
+#define MC_CMD_ERR_EPROTO 71
+/* Operation not supported */
+#define MC_CMD_ERR_ENOTSUP 95
+/* Address not available */
+#define MC_CMD_ERR_EADDRNOTAVAIL 99
+/* Not connected */
+#define MC_CMD_ERR_ENOTCONN 107
+/* Operation already in progress */
+#define MC_CMD_ERR_EALREADY 114
+
+/* Resource allocation failed. */
+#define MC_CMD_ERR_ALLOC_FAIL  0x1000
+/* V-adaptor not found. */
+#define MC_CMD_ERR_NO_VADAPTOR 0x1001
+/* EVB port not found. */
+#define MC_CMD_ERR_NO_EVB_PORT 0x1002
+/* V-switch not found. */
+#define MC_CMD_ERR_NO_VSWITCH  0x1003
+/* Too many VLAN tags. */
+#define MC_CMD_ERR_VLAN_LIMIT  0x1004
+/* Bad PCI function number. */
+#define MC_CMD_ERR_BAD_PCI_FUNC 0x1005
+/* Invalid VLAN mode. */
+#define MC_CMD_ERR_BAD_VLAN_MODE 0x1006
+/* Invalid v-switch type. */
+#define MC_CMD_ERR_BAD_VSWITCH_TYPE 0x1007
+/* Invalid v-port type. */
+#define MC_CMD_ERR_BAD_VPORT_TYPE 0x1008
+/* MAC address exists. */
+#define MC_CMD_ERR_MAC_EXIST 0x1009
+/* Slave core not present */
+#define MC_CMD_ERR_SLAVE_NOT_PRESENT 0x100a
+/* The datapath is disabled. */
+#define MC_CMD_ERR_DATAPATH_DISABLED 0x100b
+/* The requesting client is not a function */
+#define MC_CMD_ERR_CLIENT_NOT_FN  0x100c
+/* The requested operation might require the
+   command to be passed between MCs, and the
+   transport doesn't support that.  Should
+   only ever been seen over the UART. */
+#define MC_CMD_ERR_TRANSPORT_NOPROXY 0x100d
+/* VLAN tag(s) exists */
+#define MC_CMD_ERR_VLAN_EXIST 0x100e
+/* No MAC address assigned to an EVB port */
+#define MC_CMD_ERR_NO_MAC_ADDR 0x100f
+/* Notifies the driver that the request has been relayed
+ * to an admin function for authorization. The driver should
+ * wait for a PROXY_RESPONSE event and then resend its request.
+ * This error code is followed by a 32-bit handle that
+ * helps matching it with the respective PROXY_RESPONSE event. */
+#define MC_CMD_ERR_PROXY_PENDING 0x1010
+#define MC_CMD_ERR_PROXY_PENDING_HANDLE_OFST 4
+/* The request cannot be passed for authorization because
+ * another request from the same function is currently being
+ * authorized. The drvier should try again later. */
+#define MC_CMD_ERR_PROXY_INPROGRESS 0x1011
+/* Returned by MC_CMD_PROXY_COMPLETE if the caller is not the function
+ * that has enabled proxying or BLOCK_INDEX points to a function that
+ * doesn't await an authorization. */
+#define MC_CMD_ERR_PROXY_UNEXPECTED 0x1012
+/* This code is currently only used internally in FW. Its meaning is that
+ * an operation failed due to lack of SR-IOV privilege.
+ * Normally it is translated to EPERM by send_cmd_err(),
+ * but it may also be used to trigger some special mechanism
+ * for handling such case, e.g. to relay the failed request
+ * to a designated admin function for authorization. */
+#define MC_CMD_ERR_NO_PRIVILEGE 0x1013
+/* Workaround 26807 could not be turned on/off because some functions
+ * have already installed filters. See the comment at
+ * MC_CMD_WORKAROUND_BUG26807. */
+#define MC_CMD_ERR_FILTERS_PRESENT 0x1014
 
 #define MC_CMD_ERR_CODE_OFST 0
 
@@ -204,9 +316,11 @@
 
 /* Vectors in the boot ROM */
 /* Point to the copycode entry point. */
-#define MC_BOOTROM_COPYCODE_VEC (0x7f4)
+#define SIENA_MC_BOOTROM_COPYCODE_VEC (0x800 - 3 * 0x4)
+#define HUNT_MC_BOOTROM_COPYCODE_VEC (0x8000 - 3 * 0x4)
 /* Points to the recovery mode entry point. */
-#define MC_BOOTROM_NOFLASH_VEC (0x7f8)
+#define SIENA_MC_BOOTROM_NOFLASH_VEC (0x800 - 2 * 0x4)
+#define HUNT_MC_BOOTROM_NOFLASH_VEC (0x8000 - 2 * 0x4)
 
 /* The command set exported by the boot ROM (MCDI v0) */
 #define MC_CMD_GET_VERSION_V0_SUPPORTED_FUNCS {		\
@@ -216,23 +330,28 @@
 	(1 << MC_CMD_GET_VERSION),			\
 	0, 0, 0 }
 
-#define MC_CMD_SENSOR_INFO_OUT_OFFSET_OFST(_x) \
+#define MC_CMD_SENSOR_INFO_OUT_OFFSET_OFST(_x)		\
 	(MC_CMD_SENSOR_ENTRY_OFST + (_x))
 
-#define MC_CMD_DBI_WRITE_IN_ADDRESS_OFST(n) (  \
-        (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST+     \
-         MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST)+ \
-         ((n)*MC_CMD_DBIWROP_TYPEDEF_LEN))
+#define MC_CMD_DBI_WRITE_IN_ADDRESS_OFST(n)		\
+	(MC_CMD_DBI_WRITE_IN_DBIWROP_OFST +		\
+	 MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST +		\
+	 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN)
 
-#define MC_CMD_DBI_WRITE_IN_BYTE_MASK_OFST(n) (  \
-        (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST+     \
-         MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_OFST)+ \
-         ((n)*MC_CMD_DBIWROP_TYPEDEF_LEN))
+#define MC_CMD_DBI_WRITE_IN_BYTE_MASK_OFST(n)		\
+	(MC_CMD_DBI_WRITE_IN_DBIWROP_OFST +		\
+	 MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_OFST +	\
+	 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN)
 
-#define MC_CMD_DBI_WRITE_IN_VALUE_OFST(n) (  \
-        (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST+     \
-         MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST)+ \
-         ((n)*MC_CMD_DBIWROP_TYPEDEF_LEN))
+#define MC_CMD_DBI_WRITE_IN_VALUE_OFST(n)		\
+	(MC_CMD_DBI_WRITE_IN_DBIWROP_OFST +		\
+	 MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST +		\
+	 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN)
+
+/* This may be ORed with an EVB_PORT_ID_xxx constant to pass a non-default
+ * stack ID (which must be in the range 1-255) along with an EVB port ID.
+ */
+#define EVB_STACK_ID(n)  (((n) & 0xff) << 16)
 
 
 #ifdef WITH_MCDI_V2
@@ -243,8 +362,6 @@
  */
 #define MC_CMD_ERR_ARG_OFST 4
 
-/* Try again */
-#define MC_CMD_ERR_EAGAIN 11
 /* No space */
 #define MC_CMD_ERR_ENOSPC 28
 
@@ -256,10 +373,14 @@
 #define	MCDI_EVENT_CONT_WIDTH 1
 #define	MCDI_EVENT_LEVEL_LBN 33
 #define	MCDI_EVENT_LEVEL_WIDTH 3
-#define	MCDI_EVENT_LEVEL_INFO  0x0 /* enum */
-#define	MCDI_EVENT_LEVEL_WARN 0x1 /* enum */
-#define	MCDI_EVENT_LEVEL_ERR 0x2 /* enum */
-#define	MCDI_EVENT_LEVEL_FATAL 0x3 /* enum */
+/* enum: Info. */
+#define	MCDI_EVENT_LEVEL_INFO  0x0
+/* enum: Warning. */
+#define	MCDI_EVENT_LEVEL_WARN 0x1
+/* enum: Error. */
+#define	MCDI_EVENT_LEVEL_ERR 0x2
+/* enum: Fatal. */
+#define	MCDI_EVENT_LEVEL_FATAL 0x3
 #define	MCDI_EVENT_DATA_OFST 0
 #define	MCDI_EVENT_CMDDONE_SEQ_LBN 0
 #define	MCDI_EVENT_CMDDONE_SEQ_WIDTH 8
@@ -271,9 +392,14 @@
 #define	MCDI_EVENT_LINKCHANGE_LP_CAP_WIDTH 16
 #define	MCDI_EVENT_LINKCHANGE_SPEED_LBN 16
 #define	MCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4
-#define	MCDI_EVENT_LINKCHANGE_SPEED_100M  0x1 /* enum */
-#define	MCDI_EVENT_LINKCHANGE_SPEED_1G  0x2 /* enum */
-#define	MCDI_EVENT_LINKCHANGE_SPEED_10G  0x3 /* enum */
+/* enum: 100Mbs */
+#define	MCDI_EVENT_LINKCHANGE_SPEED_100M  0x1
+/* enum: 1Gbs */
+#define	MCDI_EVENT_LINKCHANGE_SPEED_1G  0x2
+/* enum: 10Gbs */
+#define	MCDI_EVENT_LINKCHANGE_SPEED_10G  0x3
+/* enum: 40Gbs */
+#define	MCDI_EVENT_LINKCHANGE_SPEED_40G  0x4
 #define	MCDI_EVENT_LINKCHANGE_FCNTL_LBN 20
 #define	MCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4
 #define	MCDI_EVENT_LINKCHANGE_LINK_FLAGS_LBN 24
@@ -288,41 +414,94 @@
 #define	MCDI_EVENT_FWALERT_DATA_WIDTH 24
 #define	MCDI_EVENT_FWALERT_REASON_LBN 0
 #define	MCDI_EVENT_FWALERT_REASON_WIDTH 8
-#define	MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS 0x1 /* enum */
+/* enum: SRAM Access. */
+#define	MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS 0x1
 #define	MCDI_EVENT_FLR_VF_LBN 0
 #define	MCDI_EVENT_FLR_VF_WIDTH 8
 #define	MCDI_EVENT_TX_ERR_TXQ_LBN 0
 #define	MCDI_EVENT_TX_ERR_TXQ_WIDTH 12
 #define	MCDI_EVENT_TX_ERR_TYPE_LBN 12
 #define	MCDI_EVENT_TX_ERR_TYPE_WIDTH 4
-#define	MCDI_EVENT_TX_ERR_DL_FAIL 0x1 /* enum */
-#define	MCDI_EVENT_TX_ERR_NO_EOP 0x2 /* enum */
-#define	MCDI_EVENT_TX_ERR_2BIG 0x3 /* enum */
+/* enum: Descriptor loader reported failure */
+#define	MCDI_EVENT_TX_ERR_DL_FAIL 0x1
+/* enum: Descriptor ring empty and no EOP seen for packet */
+#define	MCDI_EVENT_TX_ERR_NO_EOP 0x2
+/* enum: Overlength packet */
+#define	MCDI_EVENT_TX_ERR_2BIG 0x3
+/* enum: Malformed option descriptor */
+#define	MCDI_EVENT_TX_BAD_OPTDESC 0x5
+/* enum: Option descriptor part way through a packet */
+#define	MCDI_EVENT_TX_OPT_IN_PKT 0x8
+/* enum: DMA or PIO data access error */
+#define	MCDI_EVENT_TX_ERR_BAD_DMA_OR_PIO 0x9
 #define	MCDI_EVENT_TX_ERR_INFO_LBN 16
 #define	MCDI_EVENT_TX_ERR_INFO_WIDTH 16
+#define	MCDI_EVENT_TX_FLUSH_TO_DRIVER_LBN 12
+#define	MCDI_EVENT_TX_FLUSH_TO_DRIVER_WIDTH 1
 #define	MCDI_EVENT_TX_FLUSH_TXQ_LBN 0
 #define	MCDI_EVENT_TX_FLUSH_TXQ_WIDTH 12
 #define	MCDI_EVENT_PTP_ERR_TYPE_LBN 0
 #define	MCDI_EVENT_PTP_ERR_TYPE_WIDTH 8
-#define	MCDI_EVENT_PTP_ERR_PLL_LOST 0x1 /* enum */
-#define	MCDI_EVENT_PTP_ERR_FILTER 0x2 /* enum */
-#define	MCDI_EVENT_PTP_ERR_FIFO 0x3 /* enum */
-#define	MCDI_EVENT_PTP_ERR_QUEUE 0x4 /* enum */
+/* enum: PLL lost lock */
+#define	MCDI_EVENT_PTP_ERR_PLL_LOST 0x1
+/* enum: Filter overflow (PDMA) */
+#define	MCDI_EVENT_PTP_ERR_FILTER 0x2
+/* enum: FIFO overflow (FPGA) */
+#define	MCDI_EVENT_PTP_ERR_FIFO 0x3
+/* enum: Merge queue overflow */
+#define	MCDI_EVENT_PTP_ERR_QUEUE 0x4
 #define	MCDI_EVENT_AOE_ERR_TYPE_LBN 0
 #define	MCDI_EVENT_AOE_ERR_TYPE_WIDTH 8
-#define	MCDI_EVENT_AOE_NO_LOAD 0x1 /* enum */
-#define	MCDI_EVENT_AOE_FC_ASSERT 0x2 /* enum */
-#define	MCDI_EVENT_AOE_FC_WATCHDOG 0x3 /* enum */
-#define	MCDI_EVENT_AOE_FC_NO_START 0x4 /* enum */
-#define	MCDI_EVENT_AOE_FAULT 0x5 /* enum */
-#define	MCDI_EVENT_AOE_CPLD_REPROGRAMMED 0x6 /* enum */
-#define	MCDI_EVENT_AOE_LOAD 0x7 /* enum */
-#define	MCDI_EVENT_AOE_DMA 0x8 /* enum */
-#define	MCDI_EVENT_AOE_BYTEBLASTER 0x9 /* enum */
-#define	MCDI_EVENT_AOE_DDR_ECC_STATUS 0xa /* enum */
-#define	MCDI_EVENT_AOE_PTP_STATUS 0xb /* enum */
+/* enum: AOE failed to load - no valid image? */
+#define	MCDI_EVENT_AOE_NO_LOAD 0x1
+/* enum: AOE FC reported an exception */
+#define	MCDI_EVENT_AOE_FC_ASSERT 0x2
+/* enum: AOE FC watchdogged */
+#define	MCDI_EVENT_AOE_FC_WATCHDOG 0x3
+/* enum: AOE FC failed to start */
+#define	MCDI_EVENT_AOE_FC_NO_START 0x4
+/* enum: Generic AOE fault - likely to have been reported via other means too
+ * but intended for use by aoex driver.
+ */
+#define	MCDI_EVENT_AOE_FAULT 0x5
+/* enum: Results of reprogramming the CPLD (status in AOE_ERR_DATA) */
+#define	MCDI_EVENT_AOE_CPLD_REPROGRAMMED 0x6
+/* enum: AOE loaded successfully */
+#define	MCDI_EVENT_AOE_LOAD 0x7
+/* enum: AOE DMA operation completed (LSB of HOST_HANDLE in AOE_ERR_DATA) */
+#define	MCDI_EVENT_AOE_DMA 0x8
+/* enum: AOE byteblaster connected/disconnected (Connection status in
+ * AOE_ERR_DATA)
+ */
+#define	MCDI_EVENT_AOE_BYTEBLASTER 0x9
+/* enum: DDR ECC status update */
+#define	MCDI_EVENT_AOE_DDR_ECC_STATUS 0xa
+/* enum: PTP status update */
+#define	MCDI_EVENT_AOE_PTP_STATUS 0xb
 #define	MCDI_EVENT_AOE_ERR_DATA_LBN 8
 #define	MCDI_EVENT_AOE_ERR_DATA_WIDTH 8
+#define	MCDI_EVENT_RX_ERR_RXQ_LBN 0
+#define	MCDI_EVENT_RX_ERR_RXQ_WIDTH 12
+#define	MCDI_EVENT_RX_ERR_TYPE_LBN 12
+#define	MCDI_EVENT_RX_ERR_TYPE_WIDTH 4
+#define	MCDI_EVENT_RX_ERR_INFO_LBN 16
+#define	MCDI_EVENT_RX_ERR_INFO_WIDTH 16
+#define	MCDI_EVENT_RX_FLUSH_TO_DRIVER_LBN 12
+#define	MCDI_EVENT_RX_FLUSH_TO_DRIVER_WIDTH 1
+#define	MCDI_EVENT_RX_FLUSH_RXQ_LBN 0
+#define	MCDI_EVENT_RX_FLUSH_RXQ_WIDTH 12
+#define	MCDI_EVENT_MC_REBOOT_COUNT_LBN 0
+#define	MCDI_EVENT_MC_REBOOT_COUNT_WIDTH 16
+#define	MCDI_EVENT_MUM_ERR_TYPE_LBN 0
+#define	MCDI_EVENT_MUM_ERR_TYPE_WIDTH 8
+/* enum: MUM failed to load - no valid image? */
+#define	MCDI_EVENT_MUM_NO_LOAD 0x1
+/* enum: MUM f/w reported an exception */
+#define	MCDI_EVENT_MUM_ASSERT 0x2
+/* enum: MUM not kicking watchdog */
+#define	MCDI_EVENT_MUM_WATCHDOG 0x3
+#define	MCDI_EVENT_MUM_ERR_DATA_LBN 8
+#define	MCDI_EVENT_MUM_ERR_DATA_WIDTH 8
 #define	MCDI_EVENT_DATA_LBN 0
 #define	MCDI_EVENT_DATA_WIDTH 32
 #define	MCDI_EVENT_SRC_LBN 36
@@ -331,24 +510,74 @@
 #define	MCDI_EVENT_EV_CODE_WIDTH 4
 #define	MCDI_EVENT_CODE_LBN 44
 #define	MCDI_EVENT_CODE_WIDTH 8
-#define	MCDI_EVENT_CODE_BADSSERT 0x1 /* enum */
-#define	MCDI_EVENT_CODE_PMNOTICE 0x2 /* enum */
-#define	MCDI_EVENT_CODE_CMDDONE 0x3 /* enum */
-#define	MCDI_EVENT_CODE_LINKCHANGE 0x4 /* enum */
-#define	MCDI_EVENT_CODE_SENSOREVT 0x5 /* enum */
-#define	MCDI_EVENT_CODE_SCHEDERR 0x6 /* enum */
-#define	MCDI_EVENT_CODE_REBOOT 0x7 /* enum */
-#define	MCDI_EVENT_CODE_MAC_STATS_DMA 0x8 /* enum */
-#define	MCDI_EVENT_CODE_FWALERT 0x9 /* enum */
-#define	MCDI_EVENT_CODE_FLR 0xa /* enum */
-#define	MCDI_EVENT_CODE_TX_ERR 0xb /* enum */
-#define	MCDI_EVENT_CODE_TX_FLUSH  0xc /* enum */
-#define	MCDI_EVENT_CODE_PTP_RX  0xd /* enum */
-#define	MCDI_EVENT_CODE_PTP_FAULT  0xe /* enum */
-#define	MCDI_EVENT_CODE_PTP_PPS  0xf /* enum */
-#define	MCDI_EVENT_CODE_AOE  0x12 /* enum */
-#define	MCDI_EVENT_CODE_VCAL_FAIL  0x13 /* enum */
-#define	MCDI_EVENT_CODE_HW_PPS  0x14 /* enum */
+/* enum: Event generated by host software */
+#define	MCDI_EVENT_SW_EVENT 0x0
+/* enum: Bad assert. */
+#define	MCDI_EVENT_CODE_BADSSERT 0x1
+/* enum: PM Notice. */
+#define	MCDI_EVENT_CODE_PMNOTICE 0x2
+/* enum: Command done. */
+#define	MCDI_EVENT_CODE_CMDDONE 0x3
+/* enum: Link change. */
+#define	MCDI_EVENT_CODE_LINKCHANGE 0x4
+/* enum: Sensor Event. */
+#define	MCDI_EVENT_CODE_SENSOREVT 0x5
+/* enum: Schedule error. */
+#define	MCDI_EVENT_CODE_SCHEDERR 0x6
+/* enum: Reboot. */
+#define	MCDI_EVENT_CODE_REBOOT 0x7
+/* enum: Mac stats DMA. */
+#define	MCDI_EVENT_CODE_MAC_STATS_DMA 0x8
+/* enum: Firmware alert. */
+#define	MCDI_EVENT_CODE_FWALERT 0x9
+/* enum: Function level reset. */
+#define	MCDI_EVENT_CODE_FLR 0xa
+/* enum: Transmit error */
+#define	MCDI_EVENT_CODE_TX_ERR 0xb
+/* enum: Tx flush has completed */
+#define	MCDI_EVENT_CODE_TX_FLUSH  0xc
+/* enum: PTP packet received timestamp */
+#define	MCDI_EVENT_CODE_PTP_RX  0xd
+/* enum: PTP NIC failure */
+#define	MCDI_EVENT_CODE_PTP_FAULT  0xe
+/* enum: PTP PPS event */
+#define	MCDI_EVENT_CODE_PTP_PPS  0xf
+/* enum: Rx flush has completed */
+#define	MCDI_EVENT_CODE_RX_FLUSH  0x10
+/* enum: Receive error */
+#define	MCDI_EVENT_CODE_RX_ERR 0x11
+/* enum: AOE fault */
+#define	MCDI_EVENT_CODE_AOE  0x12
+/* enum: Network port calibration failed (VCAL). */
+#define	MCDI_EVENT_CODE_VCAL_FAIL  0x13
+/* enum: HW PPS event */
+#define	MCDI_EVENT_CODE_HW_PPS  0x14
+/* enum: The MC has rebooted (huntington and later, siena uses CODE_REBOOT and
+ * a different format)
+ */
+#define	MCDI_EVENT_CODE_MC_REBOOT 0x15
+/* enum: the MC has detected a parity error */
+#define	MCDI_EVENT_CODE_PAR_ERR 0x16
+/* enum: the MC has detected a correctable error */
+#define	MCDI_EVENT_CODE_ECC_CORR_ERR 0x17
+/* enum: the MC has detected an uncorrectable error */
+#define	MCDI_EVENT_CODE_ECC_FATAL_ERR 0x18
+/* enum: The MC has entered offline BIST mode */
+#define	MCDI_EVENT_CODE_MC_BIST 0x19
+/* enum: PTP tick event providing current NIC time */
+#define	MCDI_EVENT_CODE_PTP_TIME 0x1a
+/* enum: MUM fault */
+#define	MCDI_EVENT_CODE_MUM 0x1b
+/* enum: notify the designated PF of a new authorization request */
+#define	MCDI_EVENT_CODE_PROXY_REQUEST 0x1c
+/* enum: notify a function that awaits an authorization that its request has
+ * been processed and it may now resend the command
+ */
+#define	MCDI_EVENT_CODE_PROXY_RESPONSE 0x1d
+/* enum: Artificial event generated by host and posted via MC for test
+ * purposes.
+ */
+#define	MCDI_EVENT_CODE_TESTGEN  0xfa
 #define	MCDI_EVENT_CMDDONE_DATA_OFST 0
 #define	MCDI_EVENT_CMDDONE_DATA_LBN 0
 #define	MCDI_EVENT_CMDDONE_DATA_WIDTH 32
@@ -364,15 +593,81 @@
 #define	MCDI_EVENT_TX_ERR_DATA_OFST 0
 #define	MCDI_EVENT_TX_ERR_DATA_LBN 0
 #define	MCDI_EVENT_TX_ERR_DATA_WIDTH 32
+/* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the seconds field of
+ * timestamp
+ */
 #define	MCDI_EVENT_PTP_SECONDS_OFST 0
 #define	MCDI_EVENT_PTP_SECONDS_LBN 0
 #define	MCDI_EVENT_PTP_SECONDS_WIDTH 32
+/* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the major field of
+ * timestamp
+ */
+#define	MCDI_EVENT_PTP_MAJOR_OFST 0
+#define	MCDI_EVENT_PTP_MAJOR_LBN 0
+#define	MCDI_EVENT_PTP_MAJOR_WIDTH 32
+/* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the nanoseconds field
+ * of timestamp
+ */
 #define	MCDI_EVENT_PTP_NANOSECONDS_OFST 0
 #define	MCDI_EVENT_PTP_NANOSECONDS_LBN 0
 #define	MCDI_EVENT_PTP_NANOSECONDS_WIDTH 32
+/* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the minor field of
+ * timestamp
+ */
+#define	MCDI_EVENT_PTP_MINOR_OFST 0
+#define	MCDI_EVENT_PTP_MINOR_LBN 0
+#define	MCDI_EVENT_PTP_MINOR_WIDTH 32
+/* For CODE_PTP_RX events, the lowest four bytes of sourceUUID from PTP packet
+ */
 #define	MCDI_EVENT_PTP_UUID_OFST 0
 #define	MCDI_EVENT_PTP_UUID_LBN 0
 #define	MCDI_EVENT_PTP_UUID_WIDTH 32
+#define	MCDI_EVENT_RX_ERR_DATA_OFST 0
+#define	MCDI_EVENT_RX_ERR_DATA_LBN 0
+#define	MCDI_EVENT_RX_ERR_DATA_WIDTH 32
+#define	MCDI_EVENT_PAR_ERR_DATA_OFST 0
+#define	MCDI_EVENT_PAR_ERR_DATA_LBN 0
+#define	MCDI_EVENT_PAR_ERR_DATA_WIDTH 32
+#define	MCDI_EVENT_ECC_CORR_ERR_DATA_OFST 0
+#define	MCDI_EVENT_ECC_CORR_ERR_DATA_LBN 0
+#define	MCDI_EVENT_ECC_CORR_ERR_DATA_WIDTH 32
+#define	MCDI_EVENT_ECC_FATAL_ERR_DATA_OFST 0
+#define	MCDI_EVENT_ECC_FATAL_ERR_DATA_LBN 0
+#define	MCDI_EVENT_ECC_FATAL_ERR_DATA_WIDTH 32
+/* For CODE_PTP_TIME events, the major value of the PTP clock */
+#define	MCDI_EVENT_PTP_TIME_MAJOR_OFST 0
+#define	MCDI_EVENT_PTP_TIME_MAJOR_LBN 0
+#define	MCDI_EVENT_PTP_TIME_MAJOR_WIDTH 32
+/* For CODE_PTP_TIME events, bits 19-26 of the minor value of the PTP clock */
+#define	MCDI_EVENT_PTP_TIME_MINOR_26_19_LBN 36
+#define	MCDI_EVENT_PTP_TIME_MINOR_26_19_WIDTH 8
+/* For CODE_PTP_TIME events where report sync status is enabled, indicates
+ * whether the NIC clock has ever been set
+ */
+#define	MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_LBN 36
+#define	MCDI_EVENT_PTP_TIME_NIC_CLOCK_VALID_WIDTH 1
+/* For CODE_PTP_TIME events where report sync status is enabled, indicates
+ * whether the NIC and System clocks are in sync
+ */
+#define	MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_LBN 37
+#define	MCDI_EVENT_PTP_TIME_HOST_NIC_IN_SYNC_WIDTH 1
+/* For CODE_PTP_TIME events where report sync status is enabled, bits 21-26 of
+ * the minor value of the PTP clock
+ */
+#define	MCDI_EVENT_PTP_TIME_MINOR_26_21_LBN 38
+#define	MCDI_EVENT_PTP_TIME_MINOR_26_21_WIDTH 6
+#define	MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_OFST 0
+#define	MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LBN 0
+#define	MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_WIDTH 32
+#define	MCDI_EVENT_PROXY_RESPONSE_HANDLE_OFST 0
+#define	MCDI_EVENT_PROXY_RESPONSE_HANDLE_LBN 0
+#define	MCDI_EVENT_PROXY_RESPONSE_HANDLE_WIDTH 32
+/* Zero means that the request has been completed or authorized, and the driver
+ * should resend it. A non-zero value means that the authorization has been
+ * denied, and gives the reason. Typically it will be EPERM.
+ */
+#define	MCDI_EVENT_PROXY_RESPONSE_RC_LBN 36
+#define	MCDI_EVENT_PROXY_RESPONSE_RC_WIDTH 8
 
 /* FCDI_EVENT structuredef */
 #define	FCDI_EVENT_LEN 8
@@ -380,10 +675,14 @@
 #define	FCDI_EVENT_CONT_WIDTH 1
 #define	FCDI_EVENT_LEVEL_LBN 33
 #define	FCDI_EVENT_LEVEL_WIDTH 3
-#define	FCDI_EVENT_LEVEL_INFO  0x0 /* enum */
-#define	FCDI_EVENT_LEVEL_WARN 0x1 /* enum */
-#define	FCDI_EVENT_LEVEL_ERR 0x2 /* enum */
-#define	FCDI_EVENT_LEVEL_FATAL 0x3 /* enum */
+/* enum: Info. */
+#define	FCDI_EVENT_LEVEL_INFO  0x0
+/* enum: Warning. */
+#define	FCDI_EVENT_LEVEL_WARN 0x1
+/* enum: Error. */
+#define	FCDI_EVENT_LEVEL_ERR 0x2
+/* enum: Fatal. */
+#define	FCDI_EVENT_LEVEL_FATAL 0x3
 #define	FCDI_EVENT_DATA_OFST 0
 #define	FCDI_EVENT_LINK_STATE_STATUS_LBN 0
 #define	FCDI_EVENT_LINK_STATE_STATUS_WIDTH 1
@@ -397,15 +696,26 @@
 #define	FCDI_EVENT_EV_CODE_WIDTH 4
 #define	FCDI_EVENT_CODE_LBN 44
 #define	FCDI_EVENT_CODE_WIDTH 8
-#define	FCDI_EVENT_CODE_REBOOT 0x1 /* enum */
-#define	FCDI_EVENT_CODE_ASSERT 0x2 /* enum */
-#define	FCDI_EVENT_CODE_DDR_TEST_RESULT 0x3 /* enum */
-#define	FCDI_EVENT_CODE_LINK_STATE 0x4 /* enum */
-#define	FCDI_EVENT_CODE_TIMED_READ 0x5 /* enum */
-#define	FCDI_EVENT_CODE_PPS_IN 0x6 /* enum */
-#define	FCDI_EVENT_CODE_PTP_TICK 0x7 /* enum */
-#define	FCDI_EVENT_CODE_DDR_ECC_STATUS 0x8 /* enum */
-#define	FCDI_EVENT_CODE_PTP_STATUS 0x9 /* enum */
+/* enum: The FC was rebooted. */
+#define	FCDI_EVENT_CODE_REBOOT 0x1
+/* enum: Bad assert. */
+#define	FCDI_EVENT_CODE_ASSERT 0x2
+/* enum: DDR3 test result. */
+#define	FCDI_EVENT_CODE_DDR_TEST_RESULT 0x3
+/* enum: Link status. */
+#define	FCDI_EVENT_CODE_LINK_STATE 0x4
+/* enum: A timed read is ready to be serviced. */
+#define	FCDI_EVENT_CODE_TIMED_READ 0x5
+/* enum: One or more PPS IN events */
+#define	FCDI_EVENT_CODE_PPS_IN 0x6
+/* enum: Tick event from PTP clock */
+#define	FCDI_EVENT_CODE_PTP_TICK 0x7
+/* enum: ECC error counters */
+#define	FCDI_EVENT_CODE_DDR_ECC_STATUS 0x8
+/* enum: Current status of PTP */
+#define	FCDI_EVENT_CODE_PTP_STATUS 0x9
+/* enum: Port id config to map MC-FC port idx */
+#define	FCDI_EVENT_CODE_PORT_CONFIG 0xa
 #define	FCDI_EVENT_ASSERT_INSTR_ADDRESS_OFST 0
 #define	FCDI_EVENT_ASSERT_INSTR_ADDRESS_LBN 0
 #define	FCDI_EVENT_ASSERT_INSTR_ADDRESS_WIDTH 32
@@ -430,20 +740,36 @@
 #define	FCDI_EVENT_DDR_ECC_STATUS_STATUS_OFST 0
 #define	FCDI_EVENT_DDR_ECC_STATUS_STATUS_LBN 0
 #define	FCDI_EVENT_DDR_ECC_STATUS_STATUS_WIDTH 32
-
-/* FCDI_EXTENDED_EVENT_PPS structuredef */
+/* Index of MC port being referred to */
+#define	FCDI_EVENT_PORT_CONFIG_SRC_LBN 36
+#define	FCDI_EVENT_PORT_CONFIG_SRC_WIDTH 8
+/* FC Port index that matches the MC port index in SRC */
+#define	FCDI_EVENT_PORT_CONFIG_DATA_OFST 0
+#define	FCDI_EVENT_PORT_CONFIG_DATA_LBN 0
+#define	FCDI_EVENT_PORT_CONFIG_DATA_WIDTH 32
+
+/* FCDI_EXTENDED_EVENT_PPS structuredef: Extended FCDI event to send PPS events
+ * to the MC. Note that this structure | is overlayed over a normal FCDI event
+ * such that bits 32-63 containing | event code, level, source etc remain the
+ * same. In this case the data | field of the header is defined to be the
+ * number of timestamps
+ */
 #define	FCDI_EXTENDED_EVENT_PPS_LENMIN 16
 #define	FCDI_EXTENDED_EVENT_PPS_LENMAX 248
 #define	FCDI_EXTENDED_EVENT_PPS_LEN(num) (8+8*(num))
+/* Number of timestamps following */
 #define	FCDI_EXTENDED_EVENT_PPS_COUNT_OFST 0
 #define	FCDI_EXTENDED_EVENT_PPS_COUNT_LBN 0
 #define	FCDI_EXTENDED_EVENT_PPS_COUNT_WIDTH 32
+/* Seconds field of a timestamp record */
 #define	FCDI_EXTENDED_EVENT_PPS_SECONDS_OFST 8
 #define	FCDI_EXTENDED_EVENT_PPS_SECONDS_LBN 64
 #define	FCDI_EXTENDED_EVENT_PPS_SECONDS_WIDTH 32
+/* Nanoseconds field of a timestamp record */
 #define	FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_OFST 12
 #define	FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LBN 96
 #define	FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_WIDTH 32
+/* Timestamp records comprising the event */
 #define	FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_OFST 8
 #define	FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LEN 8
 #define	FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_OFST 8
@@ -453,12 +779,99 @@
 #define	FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LBN 64
 #define	FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_WIDTH 64
 
+/* MUM_EVENT structuredef */
+#define	MUM_EVENT_LEN 8
+#define	MUM_EVENT_CONT_LBN 32
+#define	MUM_EVENT_CONT_WIDTH 1
+#define	MUM_EVENT_LEVEL_LBN 33
+#define	MUM_EVENT_LEVEL_WIDTH 3
+/* enum: Info. */
+#define	MUM_EVENT_LEVEL_INFO  0x0
+/* enum: Warning. */
+#define	MUM_EVENT_LEVEL_WARN 0x1
+/* enum: Error. */
+#define	MUM_EVENT_LEVEL_ERR 0x2
+/* enum: Fatal. */
+#define	MUM_EVENT_LEVEL_FATAL 0x3
+#define	MUM_EVENT_DATA_OFST 0
+#define	MUM_EVENT_SENSOR_ID_LBN 0
+#define	MUM_EVENT_SENSOR_ID_WIDTH 8
+/*             Enum values, see field(s): */
+/*                MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */
+#define	MUM_EVENT_SENSOR_STATE_LBN 8
+#define	MUM_EVENT_SENSOR_STATE_WIDTH 8
+#define	MUM_EVENT_PORT_PHY_READY_LBN 0
+#define	MUM_EVENT_PORT_PHY_READY_WIDTH 1
+#define	MUM_EVENT_PORT_PHY_LINK_UP_LBN 1
+#define	MUM_EVENT_PORT_PHY_LINK_UP_WIDTH 1
+#define	MUM_EVENT_PORT_PHY_TX_LOL_LBN 2
+#define	MUM_EVENT_PORT_PHY_TX_LOL_WIDTH 1
+#define	MUM_EVENT_PORT_PHY_RX_LOL_LBN 3
+#define	MUM_EVENT_PORT_PHY_RX_LOL_WIDTH 1
+#define	MUM_EVENT_PORT_PHY_TX_LOS_LBN 4
+#define	MUM_EVENT_PORT_PHY_TX_LOS_WIDTH 1
+#define	MUM_EVENT_PORT_PHY_RX_LOS_LBN 5
+#define	MUM_EVENT_PORT_PHY_RX_LOS_WIDTH 1
+#define	MUM_EVENT_PORT_PHY_TX_FAULT_LBN 6
+#define	MUM_EVENT_PORT_PHY_TX_FAULT_WIDTH 1
+#define	MUM_EVENT_DATA_LBN 0
+#define	MUM_EVENT_DATA_WIDTH 32
+#define	MUM_EVENT_SRC_LBN 36
+#define	MUM_EVENT_SRC_WIDTH 8
+#define	MUM_EVENT_EV_CODE_LBN 60
+#define	MUM_EVENT_EV_CODE_WIDTH 4
+#define	MUM_EVENT_CODE_LBN 44
+#define	MUM_EVENT_CODE_WIDTH 8
+/* enum: The MUM was rebooted. */
+#define	MUM_EVENT_CODE_REBOOT 0x1
+/* enum: Bad assert. */
+#define	MUM_EVENT_CODE_ASSERT 0x2
+/* enum: Sensor failure. */
+#define	MUM_EVENT_CODE_SENSOR 0x3
+/* enum: Link fault has been asserted, or has cleared. */
+#define	MUM_EVENT_CODE_QSFP_LASI_INTERRUPT 0x4
+#define	MUM_EVENT_SENSOR_DATA_OFST 0
+#define	MUM_EVENT_SENSOR_DATA_LBN 0
+#define	MUM_EVENT_SENSOR_DATA_WIDTH 32
+#define	MUM_EVENT_PORT_PHY_FLAGS_OFST 0
+#define	MUM_EVENT_PORT_PHY_FLAGS_LBN 0
+#define	MUM_EVENT_PORT_PHY_FLAGS_WIDTH 32
+#define	MUM_EVENT_PORT_PHY_COPPER_LEN_OFST 0
+#define	MUM_EVENT_PORT_PHY_COPPER_LEN_LBN 0
+#define	MUM_EVENT_PORT_PHY_COPPER_LEN_WIDTH 32
+#define	MUM_EVENT_PORT_PHY_CAPS_OFST 0
+#define	MUM_EVENT_PORT_PHY_CAPS_LBN 0
+#define	MUM_EVENT_PORT_PHY_CAPS_WIDTH 32
+#define	MUM_EVENT_PORT_PHY_TECH_OFST 0
+#define	MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_UNKNOWN 0x0 /* enum */
+#define	MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_OPTICAL 0x1 /* enum */
+#define	MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE 0x2 /* enum */
+#define	MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE_EQUALIZED 0x3 /* enum */
+#define	MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LIMITING 0x4 /* enum */
+#define	MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LINEAR 0x5 /* enum */
+#define	MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_BASE_T 0x6 /* enum */
+#define	MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_LOOPBACK_PASSIVE 0x7 /* enum */
+#define	MUM_EVENT_PORT_PHY_TECH_LBN 0
+#define	MUM_EVENT_PORT_PHY_TECH_WIDTH 32
+#define	MUM_EVENT_PORT_PHY_SRC_DATA_ID_LBN 36
+#define	MUM_EVENT_PORT_PHY_SRC_DATA_ID_WIDTH 4
+#define	MUM_EVENT_PORT_PHY_SRC_DATA_ID_FLAGS 0x0 /* enum */
+#define	MUM_EVENT_PORT_PHY_SRC_DATA_ID_COPPER_LEN 0x1 /* enum */
+#define	MUM_EVENT_PORT_PHY_SRC_DATA_ID_CAPS 0x2 /* enum */
+#define	MUM_EVENT_PORT_PHY_SRC_DATA_ID_TECH 0x3 /* enum */
+#define	MUM_EVENT_PORT_PHY_SRC_DATA_ID_MAX 0x4 /* enum */
+#define	MUM_EVENT_PORT_PHY_SRC_PORT_NO_LBN 40
+#define	MUM_EVENT_PORT_PHY_SRC_PORT_NO_WIDTH 4
+
 
 /***********************************/
 /* MC_CMD_READ32
  * Read multiple 32byte words from MC memory.
  */
 #define	MC_CMD_READ32 0x1
+#undef	MC_CMD_0x1_PRIVILEGE_CTG
+
+#define	MC_CMD_0x1_PRIVILEGE_CTG SRIOV_CTG_ADMIN
 
 /* MC_CMD_READ32_IN msgrequest */
 #define	MC_CMD_READ32_IN_LEN 8
@@ -480,6 +893,9 @@
  * Write multiple 32byte words to MC memory.
  */
 #define	MC_CMD_WRITE32 0x2
+#undef	MC_CMD_0x2_PRIVILEGE_CTG
+
+#define	MC_CMD_0x2_PRIVILEGE_CTG SRIOV_CTG_ADMIN
 
 /* MC_CMD_WRITE32_IN msgrequest */
 #define	MC_CMD_WRITE32_IN_LENMIN 8
@@ -500,26 +916,64 @@
  * Copy MC code between two locations and jump.
  */
 #define	MC_CMD_COPYCODE 0x3
+#undef	MC_CMD_0x3_PRIVILEGE_CTG
+
+#define	MC_CMD_0x3_PRIVILEGE_CTG SRIOV_CTG_ADMIN
 
 /* MC_CMD_COPYCODE_IN msgrequest */
 #define	MC_CMD_COPYCODE_IN_LEN 16
+/* Source address
+ *
+ * The main image should be entered via a copy of a single word from and to a
+ * magic address, which controls various aspects of the boot. The magic address
+ * is a bitfield, with each bit as documented below.
+ */
 #define	MC_CMD_COPYCODE_IN_SRC_ADDR_OFST 0
+/* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT (see below) */
+#define	MC_CMD_COPYCODE_HUNT_NO_MAGIC_ADDR 0x10000
+/* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT and
+ * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED (see below)
+ */
+#define	MC_CMD_COPYCODE_HUNT_NO_DATAPATH_MAGIC_ADDR 0x1d0d0
+/* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT,
+ * BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED and BOOT_MAGIC_IGNORE_CONFIG (see
+ * below)
+ */
+#define	MC_CMD_COPYCODE_HUNT_IGNORE_CONFIG_MAGIC_ADDR 0x1badc
+#define	MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_LBN 17
+#define	MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_WIDTH 1
+#define	MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_LBN 2
+#define	MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_WIDTH 1
+#define	MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_LBN 3
+#define	MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_WIDTH 1
+#define	MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_LBN 4
+#define	MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_WIDTH 1
+#define	MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_LBN 5
+#define	MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_WIDTH 1
+/* Destination address */
 #define	MC_CMD_COPYCODE_IN_DEST_ADDR_OFST 4
 #define	MC_CMD_COPYCODE_IN_NUMWORDS_OFST 8
+/* Address of where to jump after copy. */
 #define	MC_CMD_COPYCODE_IN_JUMP_OFST 12
-#define	MC_CMD_COPYCODE_JUMP_NONE 0x1 /* enum */
+/* enum: Control should return to the caller rather than jumping */
+#define	MC_CMD_COPYCODE_JUMP_NONE 0x1
 
 /* MC_CMD_COPYCODE_OUT msgresponse */
 #define	MC_CMD_COPYCODE_OUT_LEN 0
 
 
 /***********************************/
-/* MC_CMD_SET_FUNC 
+/* MC_CMD_SET_FUNC
+ * Select function for function-specific commands.
  */
-#define	MC_CMD_SET_FUNC  0x4
+#define	MC_CMD_SET_FUNC 0x4
+#undef	MC_CMD_0x4_PRIVILEGE_CTG
+
+#define	MC_CMD_0x4_PRIVILEGE_CTG SRIOV_CTG_ADMIN
 
 /* MC_CMD_SET_FUNC_IN msgrequest */
 #define	MC_CMD_SET_FUNC_IN_LEN 4
+/* Set function */
 #define	MC_CMD_SET_FUNC_IN_FUNC_OFST 0
 
 /* MC_CMD_SET_FUNC_OUT msgresponse */
@@ -528,15 +982,22 @@
 
 /***********************************/
 /* MC_CMD_GET_BOOT_STATUS
+ * Get the instruction address from which the MC booted.
  */
 #define	MC_CMD_GET_BOOT_STATUS 0x5
+#undef	MC_CMD_0x5_PRIVILEGE_CTG
+
+#define	MC_CMD_0x5_PRIVILEGE_CTG SRIOV_CTG_ADMIN
 
 /* MC_CMD_GET_BOOT_STATUS_IN msgrequest */
 #define	MC_CMD_GET_BOOT_STATUS_IN_LEN 0
 
 /* MC_CMD_GET_BOOT_STATUS_OUT msgresponse */
 #define	MC_CMD_GET_BOOT_STATUS_OUT_LEN 8
+/* ?? */
 #define	MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_OFST 0
+/* enum: indicates that the MC wasn't flash booted */
+#define	MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_NULL  0xdeadbeef
 #define	MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_OFST 4
 #define	MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_LBN 0
 #define	MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_WIDTH 1
@@ -547,41 +1008,69 @@
 
 
 /***********************************/
-/* MC_CMD_GET_ASSERTS 
- * Get and clear any assertion status.
+/* MC_CMD_GET_ASSERTS
+ * Get (and optionally clear) the current assertion status. Only
+ * OUT.GLOBAL_FLAGS is guaranteed to exist in the completion payload. The other
+ * fields will only be present if OUT.GLOBAL_FLAGS != NO_FAILS
  */
-#define	MC_CMD_GET_ASSERTS  0x6
+#define	MC_CMD_GET_ASSERTS 0x6
+#undef	MC_CMD_0x6_PRIVILEGE_CTG
+
+#define	MC_CMD_0x6_PRIVILEGE_CTG SRIOV_CTG_ADMIN
 
 /* MC_CMD_GET_ASSERTS_IN msgrequest */
 #define	MC_CMD_GET_ASSERTS_IN_LEN 4
+/* Set to clear assertion */
 #define	MC_CMD_GET_ASSERTS_IN_CLEAR_OFST 0
 
 /* MC_CMD_GET_ASSERTS_OUT msgresponse */
 #define	MC_CMD_GET_ASSERTS_OUT_LEN 140
+/* Assertion status flag. */
 #define	MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_OFST 0
-#define	MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 /* enum */
-#define	MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 /* enum */
-#define	MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 /* enum */
-#define	MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 /* enum */
+/* enum: No assertions have failed. */
+#define	MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1
+/* enum: A system-level assertion has failed. */
+#define	MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2
+/* enum: A thread-level assertion has failed. */
+#define	MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3
+/* enum: The system was reset by the watchdog. */
+#define	MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4
+/* enum: An illegal address trap stopped the system (huntington and later) */
+#define	MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5
+/* Failing PC value */
 #define	MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_OFST 4
+/* Saved GP regs */
 #define	MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST 8
 #define	MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_LEN 4
 #define	MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_NUM 31
+/* enum: A magic value hinting that the value in this register at the time of
+ * the failure has likely been lost.
+ */
+#define	MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057
+/* Failing thread address */
 #define	MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_OFST 132
 #define	MC_CMD_GET_ASSERTS_OUT_RESERVED_OFST 136
 
 
 /***********************************/
-/* MC_CMD_LOG_CTRL 
- * Configure the output stream for various events and messages.
+/* MC_CMD_LOG_CTRL
+ * Configure the output stream for log events such as link state changes,
+ * sensor notifications and MCDI completions
  */
-#define	MC_CMD_LOG_CTRL  0x7
+#define	MC_CMD_LOG_CTRL 0x7
+#undef	MC_CMD_0x7_PRIVILEGE_CTG
+
+#define	MC_CMD_0x7_PRIVILEGE_CTG SRIOV_CTG_GENERAL
 
 /* MC_CMD_LOG_CTRL_IN msgrequest */
 #define	MC_CMD_LOG_CTRL_IN_LEN 8
+/* Log destination */
 #define	MC_CMD_LOG_CTRL_IN_LOG_DEST_OFST 0
-#define	MC_CMD_LOG_CTRL_IN_LOG_DEST_UART 0x1 /* enum */
-#define	MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ 0x2 /* enum */
+/* enum: UART. */
+#define	MC_CMD_LOG_CTRL_IN_LOG_DEST_UART 0x1
+/* enum: Event queue. */
+#define	MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ 0x2
+/* Legacy argument. Must be zero. */
 #define	MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_OFST 4
 
 /* MC_CMD_LOG_CTRL_OUT msgresponse */
@@ -589,21 +1078,31 @@
 
 
 /***********************************/
-/* MC_CMD_GET_VERSION 
+/* MC_CMD_GET_VERSION
  * Get version information about the MC firmware.
  */
-#define	MC_CMD_GET_VERSION  0x8
+#define	MC_CMD_GET_VERSION 0x8
+#undef	MC_CMD_0x8_PRIVILEGE_CTG
+
+#define	MC_CMD_0x8_PRIVILEGE_CTG SRIOV_CTG_GENERAL
 
 /* MC_CMD_GET_VERSION_IN msgrequest */
 #define	MC_CMD_GET_VERSION_IN_LEN 0
 
-/* MC_CMD_GET_VERSION_V0_OUT msgresponse */
+/* MC_CMD_GET_VERSION_EXT_IN msgrequest: Asks for the extended version */
+#define	MC_CMD_GET_VERSION_EXT_IN_LEN 4
+/* placeholder, set to 0 */
+#define	MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_OFST 0
+
+/* MC_CMD_GET_VERSION_V0_OUT msgresponse: deprecated version format */
 #define	MC_CMD_GET_VERSION_V0_OUT_LEN 4
 #define	MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0
-#define	MC_CMD_GET_VERSION_OUT_FIRMWARE_ANY 0xffffffff /* enum */
-#define	MC_CMD_GET_VERSION_OUT_FIRMWARE_BOOTROM 0xb0070000 /* enum */
-#define	MC_CMD_GET_VERSION_OUT_FIRMWARE_SIENA_BOOTROM 0xb0070000 /* enum */
-#define	MC_CMD_GET_VERSION_OUT_FIRMWARE_HUNT_BOOTROM 0xb0070001 /* enum */
+/* enum: Reserved version number to indicate "any" version. */
+#define	MC_CMD_GET_VERSION_OUT_FIRMWARE_ANY 0xffffffff
+/* enum: Bootrom version value for Siena. */
+#define	MC_CMD_GET_VERSION_OUT_FIRMWARE_SIENA_BOOTROM 0xb0070000
+/* enum: Bootrom version value for Huntington. */
+#define	MC_CMD_GET_VERSION_OUT_FIRMWARE_HUNT_BOOTROM 0xb0070001
 
 /* MC_CMD_GET_VERSION_OUT msgresponse */
 #define	MC_CMD_GET_VERSION_OUT_LEN 32
@@ -611,6 +1110,7 @@
 /*            Enum values, see field(s): */
 /*               MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */
 #define	MC_CMD_GET_VERSION_OUT_PCOL_OFST 4
+/* 128bit mask of functions supported by the current firmware */
 #define	MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_OFST 8
 #define	MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_LEN 16
 #define	MC_CMD_GET_VERSION_OUT_VERSION_OFST 24
@@ -618,77 +1118,187 @@
 #define	MC_CMD_GET_VERSION_OUT_VERSION_LO_OFST 24
 #define	MC_CMD_GET_VERSION_OUT_VERSION_HI_OFST 28
 
+/* MC_CMD_GET_VERSION_EXT_OUT msgresponse */
+#define	MC_CMD_GET_VERSION_EXT_OUT_LEN 48
+/*            MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
+/*            Enum values, see field(s): */
+/*               MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */
+#define	MC_CMD_GET_VERSION_EXT_OUT_PCOL_OFST 4
+/* 128bit mask of functions supported by the current firmware */
+#define	MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_OFST 8
+#define	MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_LEN 16
+#define	MC_CMD_GET_VERSION_EXT_OUT_VERSION_OFST 24
+#define	MC_CMD_GET_VERSION_EXT_OUT_VERSION_LEN 8
+#define	MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_OFST 24
+#define	MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_OFST 28
+/* extra info */
+#define	MC_CMD_GET_VERSION_EXT_OUT_EXTRA_OFST 32
+#define	MC_CMD_GET_VERSION_EXT_OUT_EXTRA_LEN 16
+
 
 /***********************************/
-/* MC_CMD_FC 
+/* MC_CMD_FC
  * Perform an FC operation
  */
-#define	MC_CMD_FC  0x9
+#define	MC_CMD_FC 0x9
 
 /* MC_CMD_FC_IN msgrequest */
 #define	MC_CMD_FC_IN_LEN 4
 #define	MC_CMD_FC_IN_OP_HDR_OFST 0
 #define	MC_CMD_FC_IN_OP_LBN 0
 #define	MC_CMD_FC_IN_OP_WIDTH 8
-#define	MC_CMD_FC_OP_NULL 0x1 /* enum */
-#define	MC_CMD_FC_OP_UNUSED 0x2 /* enum */
-#define	MC_CMD_FC_OP_MAC 0x3 /* enum */
-#define	MC_CMD_FC_OP_READ32 0x4 /* enum */
-#define	MC_CMD_FC_OP_WRITE32 0x5 /* enum */
-#define	MC_CMD_FC_OP_TRC_READ 0x6 /* enum */
-#define	MC_CMD_FC_OP_TRC_WRITE 0x7 /* enum */
-#define	MC_CMD_FC_OP_GET_VERSION 0x8 /* enum */
-#define	MC_CMD_FC_OP_TRC_RX_READ 0x9 /* enum */
-#define	MC_CMD_FC_OP_TRC_RX_WRITE 0xa /* enum */
-#define	MC_CMD_FC_OP_SFP 0xb /* enum */
-#define	MC_CMD_FC_OP_DDR_TEST 0xc /* enum */
-#define	MC_CMD_FC_OP_GET_ASSERT 0xd /* enum */
-#define	MC_CMD_FC_OP_FPGA_BUILD 0xe /* enum */
-#define	MC_CMD_FC_OP_READ_MAP 0xf /* enum */
-#define	MC_CMD_FC_OP_CAPABILITIES 0x10 /* enum */
-#define	MC_CMD_FC_OP_GLOBAL_FLAGS 0x11 /* enum */
-#define	MC_CMD_FC_OP_IO_REL 0x12 /* enum */
-#define	MC_CMD_FC_OP_UHLINK 0x13 /* enum */
-#define	MC_CMD_FC_OP_SET_LINK 0x14 /* enum */
-#define	MC_CMD_FC_OP_LICENSE 0x15 /* enum */
-#define	MC_CMD_FC_OP_STARTUP 0x16 /* enum */
-#define	MC_CMD_FC_OP_DMA 0x17 /* enum */
-#define	MC_CMD_FC_OP_TIMED_READ 0x18 /* enum */
-#define	MC_CMD_FC_OP_LOG 0x19 /* enum */
-#define	MC_CMD_FC_OP_CLOCK 0x1a /* enum */
-#define	MC_CMD_FC_OP_DDR 0x1b /* enum */
-#define	MC_CMD_FC_OP_TIMESTAMP 0x1c /* enum */
-#define	MC_CMD_FC_OP_SPI 0x1d /* enum */
-#define	MC_CMD_FC_OP_DIAG 0x1e /* enum */
-#define	MC_CMD_FC_IN_PORT_EXT_OFST 0x0 /* enum */
-#define	MC_CMD_FC_IN_PORT_INT_OFST 0x40 /* enum */
+/* enum: NULL MCDI command to FC. */
+#define	MC_CMD_FC_OP_NULL 0x1
+/* enum: Unused opcode */
+#define	MC_CMD_FC_OP_UNUSED 0x2
+/* enum: MAC driver commands */
+#define	MC_CMD_FC_OP_MAC 0x3
+/* enum: Read FC memory */
+#define	MC_CMD_FC_OP_READ32 0x4
+/* enum: Write to FC memory */
+#define	MC_CMD_FC_OP_WRITE32 0x5
+/* enum: Read FC memory */
+#define	MC_CMD_FC_OP_TRC_READ 0x6
+/* enum: Write to FC memory */
+#define	MC_CMD_FC_OP_TRC_WRITE 0x7
+/* enum: FC firmware Version */
+#define	MC_CMD_FC_OP_GET_VERSION 0x8
+/* enum: Read FC memory */
+#define	MC_CMD_FC_OP_TRC_RX_READ 0x9
+/* enum: Write to FC memory */
+#define	MC_CMD_FC_OP_TRC_RX_WRITE 0xa
+/* enum: SFP parameters */
+#define	MC_CMD_FC_OP_SFP 0xb
+/* enum: DDR3 test */
+#define	MC_CMD_FC_OP_DDR_TEST 0xc
+/* enum: Get Crash context from FC */
+#define	MC_CMD_FC_OP_GET_ASSERT 0xd
+/* enum: Get FPGA Build registers */
+#define	MC_CMD_FC_OP_FPGA_BUILD 0xe
+/* enum: Read map support commands */
+#define	MC_CMD_FC_OP_READ_MAP 0xf
+/* enum: FC Capabilities */
+#define	MC_CMD_FC_OP_CAPABILITIES 0x10
+/* enum: FC Global flags */
+#define	MC_CMD_FC_OP_GLOBAL_FLAGS 0x11
+/* enum: FC IO using relative addressing modes */
+#define	MC_CMD_FC_OP_IO_REL 0x12
+/* enum: FPGA link information */
+#define	MC_CMD_FC_OP_UHLINK 0x13
+/* enum: Configure loopbacks and link on FPGA ports */
+#define	MC_CMD_FC_OP_SET_LINK 0x14
+/* enum: Licensing operations relating to AOE */
+#define	MC_CMD_FC_OP_LICENSE 0x15
+/* enum: Startup information to the FC */
+#define	MC_CMD_FC_OP_STARTUP 0x16
+/* enum: Configure a DMA read */
+#define	MC_CMD_FC_OP_DMA 0x17
+/* enum: Configure a timed read */
+#define	MC_CMD_FC_OP_TIMED_READ 0x18
+/* enum: Control UART logging */
+#define	MC_CMD_FC_OP_LOG 0x19
+/* enum: Get the value of a given clock_id */
+#define	MC_CMD_FC_OP_CLOCK 0x1a
+/* enum: DDR3/QDR3 parameters */
+#define	MC_CMD_FC_OP_DDR 0x1b
+/* enum: PTP and timestamp control */
+#define	MC_CMD_FC_OP_TIMESTAMP 0x1c
+/* enum: Commands for SPI Flash interface */
+#define	MC_CMD_FC_OP_SPI 0x1d
+/* enum: Commands for diagnostic components */
+#define	MC_CMD_FC_OP_DIAG 0x1e
+/* enum: External AOE port. */
+#define	MC_CMD_FC_IN_PORT_EXT_OFST 0x0
+/* enum: Internal AOE port. */
+#define	MC_CMD_FC_IN_PORT_INT_OFST 0x40
 
 /* MC_CMD_FC_IN_NULL msgrequest */
 #define	MC_CMD_FC_IN_NULL_LEN 4
 #define	MC_CMD_FC_IN_CMD_OFST 0
 
+/* MC_CMD_FC_IN_PHY msgrequest */
+#define	MC_CMD_FC_IN_PHY_LEN 5
+/*            MC_CMD_FC_IN_CMD_OFST 0 */
+/* FC PHY driver operation code */
+#define	MC_CMD_FC_IN_PHY_OP_OFST 4
+#define	MC_CMD_FC_IN_PHY_OP_LEN 1
+/* enum: PHY init handler */
+#define	MC_CMD_FC_OP_PHY_OP_INIT 0x1
+/* enum: PHY reconfigure handler */
+#define	MC_CMD_FC_OP_PHY_OP_RECONFIGURE 0x2
+/* enum: PHY reboot handler */
+#define	MC_CMD_FC_OP_PHY_OP_REBOOT 0x3
+/* enum: PHY get_supported_cap handler */
+#define	MC_CMD_FC_OP_PHY_OP_GET_SUPPORTED_CAP 0x4
+/* enum: PHY get_config handler */
+#define	MC_CMD_FC_OP_PHY_OP_GET_CONFIG 0x5
+/* enum: PHY get_media_info handler */
+#define	MC_CMD_FC_OP_PHY_OP_GET_MEDIA_INFO 0x6
+/* enum: PHY set_led handler */
+#define	MC_CMD_FC_OP_PHY_OP_SET_LED 0x7
+/* enum: PHY lasi_interrupt handler */
+#define	MC_CMD_FC_OP_PHY_OP_LASI_INTERRUPT 0x8
+/* enum: PHY check_link handler */
+#define	MC_CMD_FC_OP_PHY_OP_CHECK_LINK 0x9
+/* enum: PHY fill_stats handler */
+#define	MC_CMD_FC_OP_PHY_OP_FILL_STATS 0xa
+/* enum: PHY bpx_link_state_changed handler */
+#define	MC_CMD_FC_OP_PHY_OP_BPX_LINK_STATE_CHANGED 0xb
+/* enum: PHY get_state handler */
+#define	MC_CMD_FC_OP_PHY_OP_GET_STATE 0xc
+/* enum: PHY start_bist handler */
+#define	MC_CMD_FC_OP_PHY_OP_START_BIST 0xd
+/* enum: PHY poll_bist handler */
+#define	MC_CMD_FC_OP_PHY_OP_POLL_BIST 0xe
+/* enum: PHY nvram_test handler */
+#define	MC_CMD_FC_OP_PHY_OP_NVRAM_TEST 0xf
+/* enum: PHY relinquish handler */
+#define	MC_CMD_FC_OP_PHY_OP_RELINQUISH_SPI 0x10
+/* enum: PHY read connection from FC - may be not required */
+#define	MC_CMD_FC_OP_PHY_OP_GET_CONNECTION 0x11
+/* enum: PHY read flags from FC - may be not required */
+#define	MC_CMD_FC_OP_PHY_OP_GET_FLAGS 0x12
+
+/* MC_CMD_FC_IN_PHY_INIT msgrequest */
+#define	MC_CMD_FC_IN_PHY_INIT_LEN 4
+#define	MC_CMD_FC_IN_PHY_CMD_OFST 0
+
 /* MC_CMD_FC_IN_MAC msgrequest */
 #define	MC_CMD_FC_IN_MAC_LEN 8
 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 #define	MC_CMD_FC_IN_MAC_HEADER_OFST 4
 #define	MC_CMD_FC_IN_MAC_OP_LBN 0
 #define	MC_CMD_FC_IN_MAC_OP_WIDTH 8
-#define	MC_CMD_FC_OP_MAC_OP_RECONFIGURE 0x1 /* enum */
-#define	MC_CMD_FC_OP_MAC_OP_SET_LINK 0x2 /* enum */
-#define	MC_CMD_FC_OP_MAC_OP_GET_STATS 0x3 /* enum */
-#define	MC_CMD_FC_OP_MAC_OP_GET_RX_STATS 0x6 /* enum */
-#define	MC_CMD_FC_OP_MAC_OP_GET_TX_STATS 0x7 /* enum */
-#define	MC_CMD_FC_OP_MAC_OP_READ_STATUS 0x8 /* enum */
+/* enum: MAC reconfigure handler */
+#define	MC_CMD_FC_OP_MAC_OP_RECONFIGURE 0x1
+/* enum: MAC Set command - same as MC_CMD_SET_MAC */
+#define	MC_CMD_FC_OP_MAC_OP_SET_LINK 0x2
+/* enum: MAC statistics */
+#define	MC_CMD_FC_OP_MAC_OP_GET_STATS 0x3
+/* enum: MAC RX statistics */
+#define	MC_CMD_FC_OP_MAC_OP_GET_RX_STATS 0x6
+/* enum: MAC TX statistics */
+#define	MC_CMD_FC_OP_MAC_OP_GET_TX_STATS 0x7
+/* enum: MAC Read status */
+#define	MC_CMD_FC_OP_MAC_OP_READ_STATUS 0x8
 #define	MC_CMD_FC_IN_MAC_PORT_TYPE_LBN 8
 #define	MC_CMD_FC_IN_MAC_PORT_TYPE_WIDTH 8
-#define	MC_CMD_FC_PORT_EXT 0x0 /* enum */
-#define	MC_CMD_FC_PORT_INT 0x1 /* enum */
+/* enum: External FPGA port. */
+#define	MC_CMD_FC_PORT_EXT 0x0
+/* enum: Internal Siena-facing FPGA ports. */
+#define	MC_CMD_FC_PORT_INT 0x1
 #define	MC_CMD_FC_IN_MAC_PORT_IDX_LBN 16
 #define	MC_CMD_FC_IN_MAC_PORT_IDX_WIDTH 8
 #define	MC_CMD_FC_IN_MAC_CMD_FORMAT_LBN 24
 #define	MC_CMD_FC_IN_MAC_CMD_FORMAT_WIDTH 8
-#define	MC_CMD_FC_OP_MAC_CMD_FORMAT_DEFAULT 0x0 /* enum */
-#define	MC_CMD_FC_OP_MAC_CMD_FORMAT_PORT_OVERRIDE 0x1 /* enum */
+/* enum: Default FC command format; the fields PORT_TYPE and PORT_IDX are
+ * irrelevant. Port number is derived from pci_fn; passed in FC header.
+ */
+#define	MC_CMD_FC_OP_MAC_CMD_FORMAT_DEFAULT 0x0
+/* enum: Override default port number. Port number determined by fields
+ * PORT_TYPE and PORT_IDX.
+ */
+#define	MC_CMD_FC_OP_MAC_CMD_FORMAT_PORT_OVERRIDE 0x1
 
 /* MC_CMD_FC_IN_MAC_RECONFIGURE msgrequest */
 #define	MC_CMD_FC_IN_MAC_RECONFIGURE_LEN 8
@@ -699,7 +1309,9 @@
 #define	MC_CMD_FC_IN_MAC_SET_LINK_LEN 32
 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 /*            MC_CMD_FC_IN_MAC_HEADER_OFST 4 */
+/* MTU size */
 #define	MC_CMD_FC_IN_MAC_SET_LINK_MTU_OFST 8
+/* Drain Tx FIFO */
 #define	MC_CMD_FC_IN_MAC_SET_LINK_DRAIN_OFST 12
 #define	MC_CMD_FC_IN_MAC_SET_LINK_ADDR_OFST 16
 #define	MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LEN 8
@@ -731,6 +1343,7 @@
 #define	MC_CMD_FC_IN_MAC_GET_STATS_LEN 20
 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 /*            MC_CMD_FC_IN_MAC_HEADER_OFST 4 */
+/* MC Statistics index */
 #define	MC_CMD_FC_IN_MAC_GET_STATS_STATS_INDEX_OFST 8
 #define	MC_CMD_FC_IN_MAC_GET_STATS_FLAGS_OFST 12
 #define	MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_ALL_LBN 0
@@ -739,6 +1352,7 @@
 #define	MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_WIDTH 1
 #define	MC_CMD_FC_IN_MAC_GET_STATS_UPDATE_LBN 2
 #define	MC_CMD_FC_IN_MAC_GET_STATS_UPDATE_WIDTH 1
+/* Number of statistics to read */
 #define	MC_CMD_FC_IN_MAC_GET_STATS_NUM_OFST 16
 #define	MC_CMD_FC_MAC_NSTATS_PER_BLOCK 0x1e /* enum */
 #define	MC_CMD_FC_MAC_NBYTES_PER_STAT 0x8 /* enum */
@@ -797,13 +1411,24 @@
 #define	MC_CMD_FC_IN_TRC_RX_WRITE_DATA_NUM 2
 
 /* MC_CMD_FC_IN_SFP msgrequest */
-#define	MC_CMD_FC_IN_SFP_LEN 24
+#define	MC_CMD_FC_IN_SFP_LEN 28
 /*            MC_CMD_FC_IN_CMD_OFST 0 */
+/* Link speed is 100, 1000, 10000, 40000 */
 #define	MC_CMD_FC_IN_SFP_SPEED_OFST 4
+/* Length of copper cable - zero when not relevant (e.g. if cable is fibre) */
 #define	MC_CMD_FC_IN_SFP_COPPER_LEN_OFST 8
+/* Not relevant for cards with QSFP modules. For older cards, true if module is
+ * a dual speed SFP+ module.
+ */
 #define	MC_CMD_FC_IN_SFP_DUAL_SPEED_OFST 12
+/* True if an SFP Module is present (other fields valid when true) */
 #define	MC_CMD_FC_IN_SFP_PRESENT_OFST 16
+/* The type of the SFP+ Module. For later cards with QSFP modules, this field
+ * is unused and the type is communicated by other means.
+ */
 #define	MC_CMD_FC_IN_SFP_TYPE_OFST 20
+/* Capabilities corresponding to 1 bits. */
+#define	MC_CMD_FC_IN_SFP_CAPS_OFST 24
 
 /* MC_CMD_FC_IN_DDR_TEST msgrequest */
 #define	MC_CMD_FC_IN_DDR_TEST_LEN 8
@@ -811,8 +1436,10 @@
 #define	MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4
 #define	MC_CMD_FC_IN_DDR_TEST_OP_LBN 0
 #define	MC_CMD_FC_IN_DDR_TEST_OP_WIDTH 8
-#define	MC_CMD_FC_OP_DDR_TEST_START 0x1 /* enum */
-#define	MC_CMD_FC_OP_DDR_TEST_POLL 0x2 /* enum */
+/* enum: DRAM Test Start */
+#define	MC_CMD_FC_OP_DDR_TEST_START 0x1
+/* enum: DRAM Test Poll */
+#define	MC_CMD_FC_OP_DDR_TEST_POLL 0x2
 
 /* MC_CMD_FC_IN_DDR_TEST_START msgrequest */
 #define	MC_CMD_FC_IN_DDR_TEST_START_LEN 12
@@ -840,10 +1467,14 @@
 /* MC_CMD_FC_IN_FPGA_BUILD msgrequest */
 #define	MC_CMD_FC_IN_FPGA_BUILD_LEN 8
 /*            MC_CMD_FC_IN_CMD_OFST 0 */
+/* FPGA build info operation code */
 #define	MC_CMD_FC_IN_FPGA_BUILD_OP_OFST 4
-#define	MC_CMD_FC_IN_FPGA_BUILD_BUILD 0x1 /* enum */
-#define	MC_CMD_FC_IN_FPGA_BUILD_SERVICES 0x2 /* enum */
-#define	MC_CMD_FC_IN_FPGA_BUILD_BSP_VERSION 0x3 /* enum */
+/* enum: Get the build registers */
+#define	MC_CMD_FC_IN_FPGA_BUILD_BUILD 0x1
+/* enum: Get the services registers */
+#define	MC_CMD_FC_IN_FPGA_BUILD_SERVICES 0x2
+/* enum: Get the BSP version */
+#define	MC_CMD_FC_IN_FPGA_BUILD_BSP_VERSION 0x3
 
 /* MC_CMD_FC_IN_READ_MAP msgrequest */
 #define	MC_CMD_FC_IN_READ_MAP_LEN 8
@@ -851,8 +1482,10 @@
 #define	MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4
 #define	MC_CMD_FC_IN_READ_MAP_OP_LBN 0
 #define	MC_CMD_FC_IN_READ_MAP_OP_WIDTH 8
-#define	MC_CMD_FC_OP_READ_MAP_COUNT 0x1 /* enum */
-#define	MC_CMD_FC_OP_READ_MAP_INDEX 0x2 /* enum */
+/* enum: Get the number of map regions */
+#define	MC_CMD_FC_OP_READ_MAP_COUNT 0x1
+/* enum: Get the specified map */
+#define	MC_CMD_FC_OP_READ_MAP_INDEX 0x2
 
 /* MC_CMD_FC_IN_READ_MAP_COUNT msgrequest */
 #define	MC_CMD_FC_IN_READ_MAP_COUNT_LEN 8
@@ -892,13 +1525,18 @@
 #define	MC_CMD_FC_IN_IO_REL_HEADER_OFST 4
 #define	MC_CMD_FC_IN_IO_REL_OP_LBN 0
 #define	MC_CMD_FC_IN_IO_REL_OP_WIDTH 8
-#define	MC_CMD_FC_IN_IO_REL_GET_ADDR 0x1 /* enum */
-#define	MC_CMD_FC_IN_IO_REL_READ32 0x2 /* enum */
-#define	MC_CMD_FC_IN_IO_REL_WRITE32 0x3 /* enum */
+/* enum: Get the base address that the FC applies to relative commands */
+#define	MC_CMD_FC_IN_IO_REL_GET_ADDR 0x1
+/* enum: Read data */
+#define	MC_CMD_FC_IN_IO_REL_READ32 0x2
+/* enum: Write data */
+#define	MC_CMD_FC_IN_IO_REL_WRITE32 0x3
 #define	MC_CMD_FC_IN_IO_REL_COMP_TYPE_LBN 8
 #define	MC_CMD_FC_IN_IO_REL_COMP_TYPE_WIDTH 8
-#define	MC_CMD_FC_COMP_TYPE_APP_ADDR_SPACE 0x1 /* enum */
-#define	MC_CMD_FC_COMP_TYPE_FLASH 0x2 /* enum */
+/* enum: Application address space */
+#define	MC_CMD_FC_COMP_TYPE_APP_ADDR_SPACE 0x1
+/* enum: Flash address space */
+#define	MC_CMD_FC_COMP_TYPE_FLASH 0x2
 
 /* MC_CMD_FC_IN_IO_REL_GET_ADDR msgrequest */
 #define	MC_CMD_FC_IN_IO_REL_GET_ADDR_LEN 8
@@ -932,22 +1570,36 @@
 #define	MC_CMD_FC_IN_UHLINK_HEADER_OFST 4
 #define	MC_CMD_FC_IN_UHLINK_OP_LBN 0
 #define	MC_CMD_FC_IN_UHLINK_OP_WIDTH 8
-#define	MC_CMD_FC_OP_UHLINK_PHY 0x1 /* enum */
-#define	MC_CMD_FC_OP_UHLINK_MAC 0x2 /* enum */
-#define	MC_CMD_FC_OP_UHLINK_RX_EYE 0x3 /* enum */
-#define	MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT 0x4 /* enum */
-#define	MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT 0x5 /* enum */
-#define	MC_CMD_FC_OP_UHLINK_RX_TUNE 0x6 /* enum */
-#define	MC_CMD_FC_OP_UHLINK_LOOPBACK_SET 0x7 /* enum */
-#define	MC_CMD_FC_OP_UHLINK_LOOPBACK_GET 0x8 /* enum */
+/* enum: Get PHY configuration info */
+#define	MC_CMD_FC_OP_UHLINK_PHY 0x1
+/* enum: Get MAC configuration info */
+#define	MC_CMD_FC_OP_UHLINK_MAC 0x2
+/* enum: Get Rx eye table */
+#define	MC_CMD_FC_OP_UHLINK_RX_EYE 0x3
+/* enum: Get Rx eye plot */
+#define	MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT 0x4
+/* enum: Get Rx eye plot */
+#define	MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT 0x5
+/* enum: Retune Rx settings */
+#define	MC_CMD_FC_OP_UHLINK_RX_TUNE 0x6
+/* enum: Set loopback mode on fpga port */
+#define	MC_CMD_FC_OP_UHLINK_LOOPBACK_SET 0x7
+/* enum: Get loopback mode config state on fpga port */
+#define	MC_CMD_FC_OP_UHLINK_LOOPBACK_GET 0x8
 #define	MC_CMD_FC_IN_UHLINK_PORT_TYPE_LBN 8
 #define	MC_CMD_FC_IN_UHLINK_PORT_TYPE_WIDTH 8
 #define	MC_CMD_FC_IN_UHLINK_PORT_IDX_LBN 16
 #define	MC_CMD_FC_IN_UHLINK_PORT_IDX_WIDTH 8
 #define	MC_CMD_FC_IN_UHLINK_CMD_FORMAT_LBN 24
 #define	MC_CMD_FC_IN_UHLINK_CMD_FORMAT_WIDTH 8
-#define	MC_CMD_FC_OP_UHLINK_CMD_FORMAT_DEFAULT 0x0 /* enum */
-#define	MC_CMD_FC_OP_UHLINK_CMD_FORMAT_PORT_OVERRIDE 0x1 /* enum */
+/* enum: Default FC command format; the fields PORT_TYPE and PORT_IDX are
+ * irrelevant. Port number is derived from pci_fn; passed in FC header.
+ */
+#define	MC_CMD_FC_OP_UHLINK_CMD_FORMAT_DEFAULT 0x0
+/* enum: Override default port number. Port number determined by fields
+ * PORT_TYPE and PORT_IDX.
+ */
+#define	MC_CMD_FC_OP_UHLINK_CMD_FORMAT_PORT_OVERRIDE 0x1
 
 /* MC_CMD_FC_OP_UHLINK_PHY msgrequest */
 #define	MC_CMD_FC_OP_UHLINK_PHY_LEN 8
@@ -1006,6 +1658,7 @@
 /* MC_CMD_FC_IN_SET_LINK msgrequest */
 #define	MC_CMD_FC_IN_SET_LINK_LEN 16
 /*            MC_CMD_FC_IN_CMD_OFST 0 */
+/* See MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */
 #define	MC_CMD_FC_IN_SET_LINK_MODE_OFST 4
 #define	MC_CMD_FC_IN_SET_LINK_SPEED_OFST 8
 #define	MC_CMD_FC_IN_SET_LINK_FLAGS_OFST 12
@@ -1028,7 +1681,9 @@
 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 #define	MC_CMD_FC_IN_STARTUP_BASE_OFST 4
 #define	MC_CMD_FC_IN_STARTUP_LENGTH_OFST 8
+/* Length of identifier */
 #define	MC_CMD_FC_IN_STARTUP_IDLENGTH_OFST 12
+/* Identifier for AOE FPGA */
 #define	MC_CMD_FC_IN_STARTUP_ID_OFST 16
 #define	MC_CMD_FC_IN_STARTUP_ID_LEN 1
 #define	MC_CMD_FC_IN_STARTUP_ID_NUM 24
@@ -1044,6 +1699,7 @@
 #define	MC_CMD_FC_IN_DMA_STOP_LEN 12
 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 /*            MC_CMD_FC_IN_DMA_OP_OFST 4 */
+/* FC supplied handle */
 #define	MC_CMD_FC_IN_DMA_STOP_FC_HANDLE_OFST 8
 
 /* MC_CMD_FC_IN_DMA_READ msgrequest */
@@ -1065,18 +1721,25 @@
 #define	MC_CMD_FC_IN_TIMED_READ_SET_LEN 52
 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 /*            MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */
+/* Host supplied handle (unique) */
 #define	MC_CMD_FC_IN_TIMED_READ_SET_HOST_HANDLE_OFST 8
+/* Address into which to transfer data in host */
 #define	MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_OFST 12
 #define	MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LEN 8
 #define	MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LO_OFST 12
 #define	MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_HI_OFST 16
+/* AOE address from which to transfer data */
 #define	MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_OFST 20
 #define	MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LEN 8
 #define	MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LO_OFST 20
 #define	MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_HI_OFST 24
+/* Length of AOE transfer (total) */
 #define	MC_CMD_FC_IN_TIMED_READ_SET_AOE_LENGTH_OFST 28
+/* Length of host transfer (total) */
 #define	MC_CMD_FC_IN_TIMED_READ_SET_HOST_LENGTH_OFST 32
+/* Offset back from aoe_address to apply operation to */
 #define	MC_CMD_FC_IN_TIMED_READ_SET_OFFSET_OFST 36
+/* Data to apply at offset */
 #define	MC_CMD_FC_IN_TIMED_READ_SET_DATA_OFST 40
 #define	MC_CMD_FC_IN_TIMED_READ_SET_FLAGS_OFST 44
 #define	MC_CMD_FC_IN_TIMED_READ_SET_INDIRECT_LBN 0
@@ -1091,18 +1754,21 @@
 #define	MC_CMD_FC_IN_TIMED_READ_SET_READ  0x1 /* enum */
 #define	MC_CMD_FC_IN_TIMED_READ_SET_WRITE  0x2 /* enum */
 #define	MC_CMD_FC_IN_TIMED_READ_SET_READWRITE  0x3 /* enum */
+/* Period at which reads are performed (100ms units) */
 #define	MC_CMD_FC_IN_TIMED_READ_SET_PERIOD_OFST 48
 
 /* MC_CMD_FC_IN_TIMED_READ_GET msgrequest */
 #define	MC_CMD_FC_IN_TIMED_READ_GET_LEN 12
 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 /*            MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */
+/* FC supplied handle */
 #define	MC_CMD_FC_IN_TIMED_READ_GET_FC_HANDLE_OFST 8
 
 /* MC_CMD_FC_IN_TIMED_READ_CLEAR msgrequest */
 #define	MC_CMD_FC_IN_TIMED_READ_CLEAR_LEN 12
 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 /*            MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */
+/* FC supplied handle */
 #define	MC_CMD_FC_IN_TIMED_READ_CLEAR_FC_HANDLE_OFST 8
 
 /* MC_CMD_FC_IN_LOG msgrequest */
@@ -1116,14 +1782,18 @@
 #define	MC_CMD_FC_IN_LOG_ADDR_RANGE_LEN 20
 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 /*            MC_CMD_FC_IN_LOG_OP_OFST 4 */
+/* Partition offset into flash */
 #define	MC_CMD_FC_IN_LOG_ADDR_RANGE_OFFSET_OFST 8
+/* Partition length */
 #define	MC_CMD_FC_IN_LOG_ADDR_RANGE_LENGTH_OFST 12
+/* Partition erase size */
 #define	MC_CMD_FC_IN_LOG_ADDR_RANGE_ERASE_SIZE_OFST 16
 
 /* MC_CMD_FC_IN_LOG_JTAG_UART msgrequest */
 #define	MC_CMD_FC_IN_LOG_JTAG_UART_LEN 12
 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 /*            MC_CMD_FC_IN_LOG_OP_OFST 4 */
+/* Enable/disable printing to JTAG UART */
 #define	MC_CMD_FC_IN_LOG_JTAG_UART_ENABLE_OFST 8
 
 /* MC_CMD_FC_IN_CLOCK msgrequest */
@@ -1132,6 +1802,7 @@
 #define	MC_CMD_FC_IN_CLOCK_OP_OFST 4
 #define	MC_CMD_FC_IN_CLOCK_GET_TIME  0x0 /* enum */
 #define	MC_CMD_FC_IN_CLOCK_SET_TIME  0x1 /* enum */
+/* Perform a clock operation */
 #define	MC_CMD_FC_IN_CLOCK_ID_OFST 8
 #define	MC_CMD_FC_IN_CLOCK_STATS  0x0 /* enum */
 #define	MC_CMD_FC_IN_CLOCK_MAC  0x1 /* enum */
@@ -1140,6 +1811,7 @@
 #define	MC_CMD_FC_IN_CLOCK_GET_TIME_LEN 12
 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 /*            MC_CMD_FC_IN_CLOCK_OP_OFST 4 */
+/* Retrieve the clock value of the specified clock */
 /*            MC_CMD_FC_IN_CLOCK_ID_OFST 8 */
 
 /* MC_CMD_FC_IN_CLOCK_SET_TIME msgrequest */
@@ -1151,6 +1823,7 @@
 #define	MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LEN 8
 #define	MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LO_OFST 12
 #define	MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_HI_OFST 16
+/* Set the clock value of the specified clock */
 #define	MC_CMD_FC_IN_CLOCK_SET_TIME_NANOSECONDS_OFST 20
 
 /* MC_CMD_FC_IN_DDR msgrequest */
@@ -1170,40 +1843,59 @@
 #define	MC_CMD_FC_IN_DDR_SET_SPD_LEN 148
 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 /*            MC_CMD_FC_IN_DDR_OP_OFST 4 */
+/* Affected bank */
 /*            MC_CMD_FC_IN_DDR_BANK_OFST 8 */
+/* Flags */
 #define	MC_CMD_FC_IN_DDR_FLAGS_OFST 12
 #define	MC_CMD_FC_IN_DDR_SET_SPD_ACTIVE  0x1 /* enum */
+/* 128-byte page of serial presence detect data read from module's EEPROM */
 #define	MC_CMD_FC_IN_DDR_SPD_OFST 16
 #define	MC_CMD_FC_IN_DDR_SPD_LEN 1
 #define	MC_CMD_FC_IN_DDR_SPD_NUM 128
+/* Page index of the spd data copied into MC_CMD_FC_IN_DDR_SPD */
 #define	MC_CMD_FC_IN_DDR_SPD_PAGE_ID_OFST 144
 
 /* MC_CMD_FC_IN_DDR_GET_STATUS msgrequest */
 #define	MC_CMD_FC_IN_DDR_GET_STATUS_LEN 12
 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 /*            MC_CMD_FC_IN_DDR_OP_OFST 4 */
+/* Affected bank */
 /*            MC_CMD_FC_IN_DDR_BANK_OFST 8 */
 
 /* MC_CMD_FC_IN_TIMESTAMP msgrequest */
 #define	MC_CMD_FC_IN_TIMESTAMP_LEN 8
 /*            MC_CMD_FC_IN_CMD_OFST 0 */
+/* FC timestamp operation code */
 #define	MC_CMD_FC_IN_TIMESTAMP_OP_OFST 4
-#define	MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT 0x0 /* enum */
-#define	MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT 0x1 /* enum */
-#define	MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT 0x2 /* enum */
+/* enum: Read transmit timestamp(s) */
+#define	MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT 0x0
+/* enum: Read snapshot timestamps */
+#define	MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT 0x1
+/* enum: Clear all transmit timestamps */
+#define	MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT 0x2
 
 /* MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT msgrequest */
 #define	MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_LEN 28
 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 #define	MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_OP_OFST 4
+/* Control filtering of the returned timestamp and sequence number specified
+ * here
+ */
 #define	MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_FILTER_OFST 8
-#define	MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_LATEST 0x0 /* enum */
-#define	MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_MATCH 0x1 /* enum */
+/* enum: Return most recent timestamp. No filtering */
+#define	MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_LATEST 0x0
+/* enum: Match timestamp against the PTP clock ID, port number and sequence
+ * number specified
+ */
+#define	MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_MATCH 0x1
+/* Clock identity of PTP packet for which timestamp required */
 #define	MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_OFST 12
 #define	MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LEN 8
 #define	MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LO_OFST 12
 #define	MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_HI_OFST 16
+/* Port number of PTP packet for which timestamp required */
 #define	MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_PORT_NUM_OFST 20
+/* Sequence number of PTP packet for which timestamp required */
 #define	MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_SEQ_NUM_OFST 24
 
 /* MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT msgrequest */
@@ -1219,10 +1911,14 @@
 /* MC_CMD_FC_IN_SPI msgrequest */
 #define	MC_CMD_FC_IN_SPI_LEN 8
 /*            MC_CMD_FC_IN_CMD_OFST 0 */
+/* Basic commands for SPI Flash. */
 #define	MC_CMD_FC_IN_SPI_OP_OFST 4
-#define	MC_CMD_FC_IN_SPI_READ 0x0 /* enum */
-#define	MC_CMD_FC_IN_SPI_WRITE 0x1 /* enum */
-#define	MC_CMD_FC_IN_SPI_ERASE 0x2 /* enum */
+/* enum: SPI Flash read */
+#define	MC_CMD_FC_IN_SPI_READ 0x0
+/* enum: SPI Flash write */
+#define	MC_CMD_FC_IN_SPI_WRITE 0x1
+/* enum: SPI Flash erase */
+#define	MC_CMD_FC_IN_SPI_ERASE 0x2
 
 /* MC_CMD_FC_IN_SPI_READ msgrequest */
 #define	MC_CMD_FC_IN_SPI_READ_LEN 16
@@ -1253,18 +1949,29 @@
 /* MC_CMD_FC_IN_DIAG msgrequest */
 #define	MC_CMD_FC_IN_DIAG_LEN 8
 /*            MC_CMD_FC_IN_CMD_OFST 0 */
+/* Operation code indicating component type */
 #define	MC_CMD_FC_IN_DIAG_OP_OFST 4
-#define	MC_CMD_FC_IN_DIAG_POWER_NOISE 0x0 /* enum */
-#define	MC_CMD_FC_IN_DIAG_DDR_SOAK 0x1 /* enum */
-#define	MC_CMD_FC_IN_DIAG_DATAPATH_CTRL 0x2 /* enum */
+/* enum: Power noise generator. */
+#define	MC_CMD_FC_IN_DIAG_POWER_NOISE 0x0
+/* enum: DDR soak test component. */
+#define	MC_CMD_FC_IN_DIAG_DDR_SOAK 0x1
+/* enum: Diagnostics datapath control component. */
+#define	MC_CMD_FC_IN_DIAG_DATAPATH_CTRL 0x2
 
 /* MC_CMD_FC_IN_DIAG_POWER_NOISE msgrequest */
 #define	MC_CMD_FC_IN_DIAG_POWER_NOISE_LEN 12
 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 #define	MC_CMD_FC_IN_DIAG_POWER_NOISE_OP_OFST 4
+/* Sub-opcode describing the operation to be carried out */
 #define	MC_CMD_FC_IN_DIAG_POWER_NOISE_SUB_OP_OFST 8
-#define	MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG 0x0 /* enum */
-#define	MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG 0x1 /* enum */
+/* enum: Read the configuration (the 32-bit values in each of the clock enable
+ * count and toggle count registers)
+ */
+#define	MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG 0x0
+/* enum: Write a new configuration to the clock enable count and toggle count
+ * registers
+ */
+#define	MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG 0x1
 
 /* MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG msgrequest */
 #define	MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_LEN 12
@@ -1277,28 +1984,42 @@
 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 #define	MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_OP_OFST 4
 #define	MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_SUB_OP_OFST 8
+/* The 32-bit value to be written to the toggle count register */
 #define	MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_TOGGLE_COUNT_OFST 12
+/* The 32-bit value to be written to the clock enable count register */
 #define	MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_CLKEN_COUNT_OFST 16
 
 /* MC_CMD_FC_IN_DIAG_DDR_SOAK msgrequest */
 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_LEN 12
 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_OP_OFST 4
+/* Sub-opcode describing the operation to be carried out */
 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_SUB_OP_OFST 8
-#define	MC_CMD_FC_IN_DIAG_DDR_SOAK_START 0x0 /* enum */
-#define	MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT 0x1 /* enum */
-#define	MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP 0x2 /* enum */
-#define	MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR 0x3 /* enum */
+/* enum: Starts DDR soak test on selected banks */
+#define	MC_CMD_FC_IN_DIAG_DDR_SOAK_START 0x0
+/* enum: Read status of DDR soak test */
+#define	MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT 0x1
+/* enum: Stop test */
+#define	MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP 0x2
+/* enum: Set or clear bit that triggers fake errors. These cause subsequent
+ * tests to fail until the bit is cleared.
+ */
+#define	MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR 0x3
 
 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_START msgrequest */
 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_START_LEN 24
 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_START_OP_OFST 4
 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_START_SUB_OP_OFST 8
+/* Mask of DDR banks to be tested */
 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_START_BANK_MASK_OFST 12
+/* Pattern to use in the soak test */
 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_PATTERN_OFST 16
 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ZEROS 0x0 /* enum */
 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ONES 0x1 /* enum */
+/* Either multiple automatic tests until a STOP command is issued, or one
+ * single test
+ */
 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_TYPE_OFST 20
 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ONGOING_TEST 0x0 /* enum */
 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_START_SINGLE_TEST 0x1 /* enum */
@@ -1308,6 +2029,7 @@
 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_OP_OFST 4
 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_SUB_OP_OFST 8
+/* DDR bank to read status from */
 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_BANK_ID_OFST 12
 #define	MC_CMD_FC_DDR_BANK0 0x0 /* enum */
 #define	MC_CMD_FC_DDR_BANK1 0x1 /* enum */
@@ -1320,6 +2042,7 @@
 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_OP_OFST 4
 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_SUB_OP_OFST 8
+/* Mask of DDR banks to be tested */
 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_BANK_MASK_OFST 12
 
 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR msgrequest */
@@ -1327,6 +2050,7 @@
 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_OP_OFST 4
 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_SUB_OP_OFST 8
+/* Mask of DDR banks to set/clear error flag on */
 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_BANK_MASK_OFST 12
 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_FLAG_ACTION_OFST 16
 #define	MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_CLEAR 0x0 /* enum */
@@ -1336,15 +2060,19 @@
 #define	MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_LEN 12
 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 #define	MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_OP_OFST 4
+/* Sub-opcode describing the operation to be carried out */
 #define	MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SUB_OP_OFST 8
-#define	MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE 0x0 /* enum */
-#define	MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG 0x1 /* enum */
+/* enum: Set a known datapath configuration */
+#define	MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE 0x0
+/* enum: Apply raw config to datapath control registers */
+#define	MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG 0x1
 
 /* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE msgrequest */
 #define	MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_LEN 16
 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 #define	MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_OP_OFST 4
 #define	MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_SUB_OP_OFST 8
+/* Datapath configuration identifier */
 #define	MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_MODE_OFST 12
 #define	MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_PASSTHROUGH 0x0 /* enum */
 #define	MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_SNAKE 0x1 /* enum */
@@ -1354,8 +2082,11 @@
 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 #define	MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_OP_OFST 4
 #define	MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_SUB_OP_OFST 8
+/* Value to write into control register 1 */
 #define	MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL1_OFST 12
+/* Value to write into control register 2 */
 #define	MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL2_OFST 16
+/* Value to write into control register 3 */
 #define	MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL3_OFST 20
 
 /* MC_CMD_FC_OUT msgresponse */
@@ -1444,7 +2175,8 @@
 #define	MC_CMD_FC_MAC_RX_STATS_JABBERS  0x16 /* enum */
 #define	MC_CMD_FC_MAC_RX_STATS_FRAGMENTS  0x17 /* enum */
 #define	MC_CMD_FC_MAC_RX_MAC_CONTROL_FRAMES  0x18 /* enum */
-#define	MC_CMD_FC_MAC_RX_NSTATS  0x19 /* enum */
+/* enum: (Last entry) */
+#define	MC_CMD_FC_MAC_RX_NSTATS  0x19
 
 /* MC_CMD_FC_OUT_MAC_GET_TX_STATS msgresponse */
 #define	MC_CMD_FC_OUT_MAC_GET_TX_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_TX_NSTATS))+1))>>3)
@@ -1475,10 +2207,12 @@
 #define	MC_CMD_FC_MAC_TX_STATS_PKTS_1024_1518  0x13 /* enum */
 #define	MC_CMD_FC_MAC_TX_STATS_PKTS_1519_TX_MTU  0x14 /* enum */
 #define	MC_CMD_FC_MAC_TX_MAC_CONTROL_FRAMES  0x15 /* enum */
-#define	MC_CMD_FC_MAC_TX_NSTATS  0x16 /* enum */
+/* enum: (Last entry) */
+#define	MC_CMD_FC_MAC_TX_NSTATS  0x16
 
 /* MC_CMD_FC_OUT_MAC_GET_STATS msgresponse */
 #define	MC_CMD_FC_OUT_MAC_GET_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_NSTATS_PER_BLOCK))+1))>>3)
+/* MAC Statistics */
 #define	MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_OFST 0
 #define	MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LEN 8
 #define	MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LO_OFST 0
@@ -1499,10 +2233,14 @@
 #define	MC_CMD_FC_OUT_DDR_TEST_POLL_STATUS_OFST 0
 #define	MC_CMD_FC_OUT_DDR_TEST_POLL_CODE_LBN 0
 #define	MC_CMD_FC_OUT_DDR_TEST_POLL_CODE_WIDTH 8
-#define	MC_CMD_FC_OP_DDR_TEST_NONE 0x0 /* enum */
-#define	MC_CMD_FC_OP_DDR_TEST_INPROGRESS 0x1 /* enum */
-#define	MC_CMD_FC_OP_DDR_TEST_SUCCESS 0x2 /* enum */
-#define	MC_CMD_FC_OP_DDR_TEST_TIMER_EXPIRED 0x3 /* enum */
+/* enum: Test not yet initiated */
+#define	MC_CMD_FC_OP_DDR_TEST_NONE 0x0
+/* enum: Test is in progress */
+#define	MC_CMD_FC_OP_DDR_TEST_INPROGRESS 0x1
+/* enum: Timed completed */
+#define	MC_CMD_FC_OP_DDR_TEST_SUCCESS 0x2
+/* enum: Test did not complete in specified time */
+#define	MC_CMD_FC_OP_DDR_TEST_TIMER_EXPIRED 0x3
 #define	MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T0_LBN 11
 #define	MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T0_WIDTH 1
 #define	MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T1_LBN 10
@@ -1511,6 +2249,7 @@
 #define	MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B0_WIDTH 1
 #define	MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B1_LBN 8
 #define	MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B1_WIDTH 1
+/* Test result from FPGA */
 #define	MC_CMD_FC_OUT_DDR_TEST_POLL_RESULT_OFST 4
 #define	MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T0_LBN 31
 #define	MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T0_WIDTH 1
@@ -1539,23 +2278,35 @@
 
 /* MC_CMD_FC_OUT_GET_ASSERT msgresponse */
 #define	MC_CMD_FC_OUT_GET_ASSERT_LEN 144
+/* Assertion status flag. */
 #define	MC_CMD_FC_OUT_GET_ASSERT_GLOBAL_FLAGS_OFST 0
 #define	MC_CMD_FC_OUT_GET_ASSERT_STATE_LBN 8
 #define	MC_CMD_FC_OUT_GET_ASSERT_STATE_WIDTH 8
-#define	MC_CMD_FC_GET_ASSERT_FLAGS_STATE_CLEAR 0x0 /* enum */
-#define	MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NEW 0x1 /* enum */
-#define	MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NOTIFIED 0x2 /* enum */
+/* enum: No crash data available */
+#define	MC_CMD_FC_GET_ASSERT_FLAGS_STATE_CLEAR 0x0
+/* enum: New crash data available */
+#define	MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NEW 0x1
+/* enum: Crash data has been sent */
+#define	MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NOTIFIED 0x2
 #define	MC_CMD_FC_OUT_GET_ASSERT_TYPE_LBN 0
 #define	MC_CMD_FC_OUT_GET_ASSERT_TYPE_WIDTH 8
-#define	MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_NONE 0x0 /* enum */
-#define	MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_EXCEPTION 0x1 /* enum */
-#define	MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_ASSERTION 0x2 /* enum */
+/* enum: No crash has been recorded. */
+#define	MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_NONE 0x0
+/* enum: Crash due to exception. */
+#define	MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_EXCEPTION 0x1
+/* enum: Crash due to assertion. */
+#define	MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_ASSERTION 0x2
+/* Failing PC value */
 #define	MC_CMD_FC_OUT_GET_ASSERT_SAVED_PC_OFFS_OFST 4
+/* Saved GP regs */
 #define	MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_OFST 8
 #define	MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_LEN 4
 #define	MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_NUM 31
+/* Exception Type */
 #define	MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_TYPE_OFFS_OFST 132
+/* Instruction at which exception occurred */
 #define	MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_PC_ADDR_OFFS_OFST 136
+/* BAD Address that triggered address-based exception */
 #define	MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_BAD_ADDR_OFFS_OFST 140
 
 /* MC_CMD_FC_OUT_FPGA_BUILD msgresponse */
@@ -1573,6 +2324,7 @@
 #define	MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MINOR_WIDTH 8
 #define	MC_CMD_FC_OUT_FPGA_BUILD_BUILD_NUM_LBN 0
 #define	MC_CMD_FC_OUT_FPGA_BUILD_BUILD_NUM_WIDTH 4
+/* Build timestamp (seconds since epoch) */
 #define	MC_CMD_FC_OUT_FPGA_BUILD_TIMESTAMP_OFST 4
 #define	MC_CMD_FC_OUT_FPGA_BUILD_PARAMETERS_OFST 8
 #define	MC_CMD_FC_OUT_FPGA_BUILD_FPGA_TYPE_LBN 0
@@ -1650,6 +2402,7 @@
 #define	MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MINOR_WIDTH 8
 #define	MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_NUM_LBN 0
 #define	MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_NUM_WIDTH 4
+/* Build timestamp (seconds since epoch) */
 #define	MC_CMD_FC_OUT_FPGA_SERVICES_TIMESTAMP_OFST 4
 #define	MC_CMD_FC_OUT_FPGA_SERVICES_PARAMETERS_OFST 8
 #define	MC_CMD_FC_OUT_FPGA_SERVICES_FC_FLASH_BOOTED_LBN 8
@@ -1686,6 +2439,7 @@
 
 /* MC_CMD_FC_OUT_BSP_VERSION msgresponse */
 #define	MC_CMD_FC_OUT_BSP_VERSION_LEN 4
+/* Qsys system ID */
 #define	MC_CMD_FC_OUT_BSP_VERSION_SYSID_OFST 0
 #define	MC_CMD_FC_OUT_BSP_VERSION_VERSION_MAJOR_LBN 12
 #define	MC_CMD_FC_OUT_BSP_VERSION_VERSION_MAJOR_WIDTH 4
@@ -1696,11 +2450,14 @@
 
 /* MC_CMD_FC_OUT_READ_MAP_COUNT msgresponse */
 #define	MC_CMD_FC_OUT_READ_MAP_COUNT_LEN 4
+/* Number of maps */
 #define	MC_CMD_FC_OUT_READ_MAP_COUNT_NUM_MAPS_OFST 0
 
 /* MC_CMD_FC_OUT_READ_MAP_INDEX msgresponse */
 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_LEN 164
+/* Index of the map */
 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_INDEX_OFST 0
+/* Options for the map */
 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_OPTIONS_OFST 4
 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_8  0x0 /* enum */
 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_16  0x1 /* enum */
@@ -1713,19 +2470,24 @@
 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_PERM_WRITE  0x20 /* enum */
 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_FREE  0x0 /* enum */
 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_LICENSED  0x40 /* enum */
+/* Address of start of map */
 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_OFST 8
 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LEN 8
 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LO_OFST 8
 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_HI_OFST 12
+/* Length of address map */
 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_OFST 16
 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LEN 8
 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LO_OFST 16
 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_HI_OFST 20
+/* Component information field */
 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_COMP_INFO_OFST 24
+/* License expiry data for map */
 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_OFST 28
 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LEN 8
 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LO_OFST 28
 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_HI_OFST 32
+/* Name of the component */
 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_OFST 36
 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_LEN 1
 #define	MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_NUM 128
@@ -1735,7 +2497,9 @@
 
 /* MC_CMD_FC_OUT_CAPABILITIES msgresponse */
 #define	MC_CMD_FC_OUT_CAPABILITIES_LEN 8
+/* Number of internal ports */
 #define	MC_CMD_FC_OUT_CAPABILITIES_INTERNAL_OFST 0
+/* Number of external ports */
 #define	MC_CMD_FC_OUT_CAPABILITIES_EXTERNAL_OFST 4
 
 /* MC_CMD_FC_OUT_GLOBAL_FLAGS msgresponse */
@@ -1769,34 +2533,46 @@
 #define	MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_VOD_WIDTH 16
 #define	MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_1STPOSTTAP_LBN 16
 #define	MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_1STPOSTTAP_WIDTH 16
+/* Transceiver Transmit settings */
 #define	MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_1_OFST 4
 #define	MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_PRETAP_LBN 0
 #define	MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_PRETAP_WIDTH 16
 #define	MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_2NDPOSTTAP_LBN 16
 #define	MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_2NDPOSTTAP_WIDTH 16
+/* Transceiver Receive settings */
 #define	MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_SETTINGS_OFST 8
 #define	MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_DC_GAIN_LBN 0
 #define	MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_DC_GAIN_WIDTH 16
 #define	MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_EQ_CONTROL_LBN 16
 #define	MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_EQ_CONTROL_WIDTH 16
+/* Rx eye opening */
 #define	MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_OFST 12
 #define	MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_WIDTH_LBN 0
 #define	MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_WIDTH_WIDTH 16
 #define	MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_HEIGHT_LBN 16
 #define	MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_HEIGHT_WIDTH 16
+/* PCS status word */
 #define	MC_CMD_FC_OUT_UHLINK_PHY_PCS_STATUS_OFST 16
+/* Link status word */
 #define	MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WORD_OFST 20
 #define	MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_LBN 0
 #define	MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WIDTH 1
 #define	MC_CMD_FC_OUT_UHLINK_PHY_LINK_CONFIGURED_LBN 1
 #define	MC_CMD_FC_OUT_UHLINK_PHY_LINK_CONFIGURED_WIDTH 1
+/* Current SFp parameters applied */
 #define	MC_CMD_FC_OUT_UHLINK_PHY_SFP_PARAMS_OFST 24
 #define	MC_CMD_FC_OUT_UHLINK_PHY_SFP_PARAMS_LEN 20
+/* Link speed is 100, 1000, 10000 */
 #define	MC_CMD_FC_OUT_UHLINK_PHY_SFP_SPEED_OFST 24
+/* Length of copper cable - zero when not relevant */
 #define	MC_CMD_FC_OUT_UHLINK_PHY_SFP_COPPER_LEN_OFST 28
+/* True if a dual speed SFP+ module */
 #define	MC_CMD_FC_OUT_UHLINK_PHY_SFP_DUAL_SPEED_OFST 32
+/* True if an SFP Module is present (other fields valid when true) */
 #define	MC_CMD_FC_OUT_UHLINK_PHY_SFP_PRESENT_OFST 36
+/* The type of the SFP+ Module */
 #define	MC_CMD_FC_OUT_UHLINK_PHY_SFP_TYPE_OFST 40
+/* PHY config flags */
 #define	MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_OFST 44
 #define	MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_DFE_LBN 0
 #define	MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_DFE_WIDTH 1
@@ -1807,9 +2583,13 @@
 
 /* MC_CMD_FC_OUT_UHLINK_MAC msgresponse */
 #define	MC_CMD_FC_OUT_UHLINK_MAC_LEN 20
+/* MAC configuration applied */
 #define	MC_CMD_FC_OUT_UHLINK_MAC_CONFIG_OFST 0
+/* MTU size */
 #define	MC_CMD_FC_OUT_UHLINK_MAC_MTU_OFST 4
+/* IF Mode status */
 #define	MC_CMD_FC_OUT_UHLINK_MAC_IF_STATUS_OFST 8
+/* MAC address configured */
 #define	MC_CMD_FC_OUT_UHLINK_MAC_ADDR_OFST 12
 #define	MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LEN 8
 #define	MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LO_OFST 12
@@ -1817,6 +2597,7 @@
 
 /* MC_CMD_FC_OUT_UHLINK_RX_EYE msgresponse */
 #define	MC_CMD_FC_OUT_UHLINK_RX_EYE_LEN ((((0-1+(32*MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK))+1))>>3)
+/* Rx Eye measurements */
 #define	MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_OFST 0
 #define	MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_LEN 4
 #define	MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_NUM MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK
@@ -1826,7 +2607,9 @@
 
 /* MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT msgresponse */
 #define	MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_LEN ((((32-1+(64*MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK))+1))>>3)
+/* Has the eye plot dump completed and data returned is valid? */
 #define	MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_VALID_OFST 0
+/* Rx Eye binary plot */
 #define	MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_OFST 4
 #define	MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LEN 8
 #define	MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LO_OFST 4
@@ -1851,12 +2634,16 @@
 
 /* MC_CMD_FC_OUT_LICENSE msgresponse */
 #define	MC_CMD_FC_OUT_LICENSE_LEN 12
+/* Count of valid keys */
 #define	MC_CMD_FC_OUT_LICENSE_VALID_KEYS_OFST 0
+/* Count of invalid keys */
 #define	MC_CMD_FC_OUT_LICENSE_INVALID_KEYS_OFST 4
+/* Count of blacklisted keys */
 #define	MC_CMD_FC_OUT_LICENSE_BLACKLISTED_KEYS_OFST 8
 
 /* MC_CMD_FC_OUT_STARTUP msgresponse */
 #define	MC_CMD_FC_OUT_STARTUP_LEN 4
+/* Capabilities of the FPGA/FC */
 #define	MC_CMD_FC_OUT_STARTUP_CAPABILITIES_OFST 0
 #define	MC_CMD_FC_OUT_STARTUP_CAN_ACCESS_FLASH_LBN 0
 #define	MC_CMD_FC_OUT_STARTUP_CAN_ACCESS_FLASH_WIDTH 1
@@ -1865,6 +2652,7 @@
 #define	MC_CMD_FC_OUT_DMA_READ_LENMIN 1
 #define	MC_CMD_FC_OUT_DMA_READ_LENMAX 252
 #define	MC_CMD_FC_OUT_DMA_READ_LEN(num) (0+1*(num))
+/* The data read */
 #define	MC_CMD_FC_OUT_DMA_READ_DATA_OFST 0
 #define	MC_CMD_FC_OUT_DMA_READ_DATA_LEN 1
 #define	MC_CMD_FC_OUT_DMA_READ_DATA_MINNUM 1
@@ -1872,27 +2660,36 @@
 
 /* MC_CMD_FC_OUT_TIMED_READ_SET msgresponse */
 #define	MC_CMD_FC_OUT_TIMED_READ_SET_LEN 4
+/* Timer handle */
 #define	MC_CMD_FC_OUT_TIMED_READ_SET_FC_HANDLE_OFST 0
 
 /* MC_CMD_FC_OUT_TIMED_READ_GET msgresponse */
 #define	MC_CMD_FC_OUT_TIMED_READ_GET_LEN 52
+/* Host supplied handle (unique) */
 #define	MC_CMD_FC_OUT_TIMED_READ_GET_HOST_HANDLE_OFST 0
+/* Address into which to transfer data in host */
 #define	MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_OFST 4
 #define	MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LEN 8
 #define	MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LO_OFST 4
 #define	MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_HI_OFST 8
+/* AOE address from which to transfer data */
 #define	MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_OFST 12
 #define	MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LEN 8
 #define	MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LO_OFST 12
 #define	MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_HI_OFST 16
+/* Length of AOE transfer (total) */
 #define	MC_CMD_FC_OUT_TIMED_READ_GET_AOE_LENGTH_OFST 20
+/* Length of host transfer (total) */
 #define	MC_CMD_FC_OUT_TIMED_READ_GET_HOST_LENGTH_OFST 24
+/* See FLAGS entry for MC_CMD_FC_IN_TIMED_READ_SET */
 #define	MC_CMD_FC_OUT_TIMED_READ_GET_FLAGS_OFST 28
 #define	MC_CMD_FC_OUT_TIMED_READ_GET_PERIOD_OFST 32
+/* When active, start read time */
 #define	MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_OFST 36
 #define	MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LEN 8
 #define	MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LO_OFST 36
 #define	MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_HI_OFST 40
+/* When active, end read time */
 #define	MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_OFST 44
 #define	MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LEN 8
 #define	MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LO_OFST 44
@@ -1964,7 +2761,9 @@
 
 /* MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG msgresponse */
 #define	MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_LEN 8
+/* The 32-bit value read from the toggle count register */
 #define	MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_TOGGLE_COUNT_OFST 0
+/* The 32-bit value read from the clock enable count register */
 #define	MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_CLKEN_COUNT_OFST 4
 
 /* MC_CMD_FC_OUT_DIAG_POWER_NOISE_WRITE_CONFIG msgresponse */
@@ -1975,6 +2774,7 @@
 
 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT msgresponse */
 #define	MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_LEN 8
+/* DDR soak test status word; bits [4:0] are relevant. */
 #define	MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_STATUS_OFST 0
 #define	MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PASSED_LBN 0
 #define	MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PASSED_WIDTH 1
@@ -1986,6 +2786,7 @@
 #define	MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_TIMEOUT_WIDTH 1
 #define	MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PNF_LBN 4
 #define	MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PNF_WIDTH 1
+/* DDR soak test error count */
 #define	MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_ERR_COUNT_OFST 4
 
 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_STOP msgresponse */
@@ -2002,39 +2803,70 @@
 
 
 /***********************************/
-/* MC_CMD_AOE 
- * AOE operations (on MC rather than FC)
+/* MC_CMD_AOE
+ * AOE operations on MC
  */
-#define	MC_CMD_AOE  0xa
+#define	MC_CMD_AOE 0xa
 
 /* MC_CMD_AOE_IN msgrequest */
 #define	MC_CMD_AOE_IN_LEN 4
 #define	MC_CMD_AOE_IN_OP_HDR_OFST 0
 #define	MC_CMD_AOE_IN_OP_LBN 0
 #define	MC_CMD_AOE_IN_OP_WIDTH 8
-#define	MC_CMD_AOE_OP_INFO 0x1 /* enum */
-#define	MC_CMD_AOE_OP_CURRENTS 0x2 /* enum */
-#define	MC_CMD_AOE_OP_TEMPERATURES 0x3 /* enum */
-#define	MC_CMD_AOE_OP_CPLD_IDLE 0x4 /* enum */
-#define	MC_CMD_AOE_OP_CPLD_READ 0x5 /* enum */
-#define	MC_CMD_AOE_OP_CPLD_WRITE 0x6 /* enum */
-#define	MC_CMD_AOE_OP_CPLD_INSTRUCTION 0x7 /* enum */
-#define	MC_CMD_AOE_OP_CPLD_REPROGRAM 0x8 /* enum */
-#define	MC_CMD_AOE_OP_POWER 0x9 /* enum */
-#define	MC_CMD_AOE_OP_LOAD 0xa /* enum */
-#define	MC_CMD_AOE_OP_FAN_CONTROL 0xb /* enum */
-#define	MC_CMD_AOE_OP_FAN_FAILURES 0xc /* enum */
-#define	MC_CMD_AOE_OP_MAC_STATS 0xd /* enum */
-#define	MC_CMD_AOE_OP_GET_PHY_MEDIA_INFO 0xe /* enum */
-#define	MC_CMD_AOE_OP_JTAG_WRITE 0xf /* enum */
-#define	MC_CMD_AOE_OP_FPGA_ACCESS 0x10 /* enum */
-#define	MC_CMD_AOE_OP_SET_MTU_OFFSET 0x11 /* enum */
-#define	MC_CMD_AOE_OP_LINK_STATE 0x12 /* enum */
-#define	MC_CMD_AOE_OP_SIENA_STATS 0x13 /* enum */
-#define	MC_CMD_AOE_OP_DDR 0x14 /* enum */
-#define	MC_CMD_AOE_OP_FC 0x15 /* enum */
-#define	MC_CMD_AOE_OP_DDR_ECC_STATUS 0x16 /* enum */
-#define	MC_CMD_AOE_OP_MC_SPI_MASTER 0x17 /* enum */
+/* enum: FPGA and CPLD information */
+#define	MC_CMD_AOE_OP_INFO 0x1
+/* enum: Currents and voltages read from MCP3424s; DEBUG */
+#define	MC_CMD_AOE_OP_CURRENTS 0x2
+/* enum: Temperatures at locations around the PCB; DEBUG */
+#define	MC_CMD_AOE_OP_TEMPERATURES 0x3
+/* enum: Set CPLD to idle */
+#define	MC_CMD_AOE_OP_CPLD_IDLE 0x4
+/* enum: Read from CPLD register */
+#define	MC_CMD_AOE_OP_CPLD_READ 0x5
+/* enum: Write to CPLD register */
+#define	MC_CMD_AOE_OP_CPLD_WRITE 0x6
+/* enum: Execute CPLD instruction */
+#define	MC_CMD_AOE_OP_CPLD_INSTRUCTION 0x7
+/* enum: Reprogram the CPLD on the AOE device */
+#define	MC_CMD_AOE_OP_CPLD_REPROGRAM 0x8
+/* enum: AOE power control */
+#define	MC_CMD_AOE_OP_POWER 0x9
+/* enum: AOE image loading */
+#define	MC_CMD_AOE_OP_LOAD 0xa
+/* enum: Fan monitoring */
+#define	MC_CMD_AOE_OP_FAN_CONTROL 0xb
+/* enum: Fan failures since last reset */
+#define	MC_CMD_AOE_OP_FAN_FAILURES 0xc
+/* enum: Get generic AOE MAC statistics */
+#define	MC_CMD_AOE_OP_MAC_STATS 0xd
+/* enum: Retrieve PHY specific information */
+#define	MC_CMD_AOE_OP_GET_PHY_MEDIA_INFO 0xe
+/* enum: Write a number of JTAG primitive commands, return will give data */
+#define	MC_CMD_AOE_OP_JTAG_WRITE 0xf
+/* enum: Control access to the FPGA via the Siena JTAG Chain */
+#define	MC_CMD_AOE_OP_FPGA_ACCESS 0x10
+/* enum: Set the MTU offset between Siena and AOE MACs */
+#define	MC_CMD_AOE_OP_SET_MTU_OFFSET 0x11
+/* enum: How link state is handled */
+#define	MC_CMD_AOE_OP_LINK_STATE 0x12
+/* enum: How Siena MAC statistics are reported (deprecated - use
+ * MC_CMD_AOE_OP_ASIC_STATS)
+ */
+#define	MC_CMD_AOE_OP_SIENA_STATS 0x13
+/* enum: How native ASIC MAC statistics are reported - replaces the deprecated
+ * command MC_CMD_AOE_OP_SIENA_STATS
+ */
+#define	MC_CMD_AOE_OP_ASIC_STATS 0x13
+/* enum: DDR memory information */
+#define	MC_CMD_AOE_OP_DDR 0x14
+/* enum: FC control */
+#define	MC_CMD_AOE_OP_FC 0x15
+/* enum: DDR ECC status reads */
+#define	MC_CMD_AOE_OP_DDR_ECC_STATUS 0x16
+/* enum: Commands for MC-SPI Master emulation */
+#define	MC_CMD_AOE_OP_MC_SPI_MASTER 0x17
+/* enum: Commands for FC boot control */
+#define	MC_CMD_AOE_OP_FC_BOOT 0x18
 
 /* MC_CMD_AOE_OUT msgresponse */
 #define	MC_CMD_AOE_OUT_LEN 0
@@ -2077,31 +2909,46 @@
 #define	MC_CMD_AOE_IN_CPLD_REPROGRAM_LEN 8
 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
 #define	MC_CMD_AOE_IN_CPLD_REPROGRAM_OP_OFST 4
-#define	MC_CMD_AOE_IN_CPLD_REPROGRAM_REPROGRAM 0x1 /* enum */
-#define	MC_CMD_AOE_IN_CPLD_REPROGRAM_REPROGRAM_EVENT 0x3 /* enum */
-#define	MC_CMD_AOE_IN_CPLD_REPROGRAM_STATUS 0x4 /* enum */
+/* enum: Reprogram CPLD, poll for completion */
+#define	MC_CMD_AOE_IN_CPLD_REPROGRAM_REPROGRAM 0x1
+/* enum: Reprogram CPLD, send event on completion */
+#define	MC_CMD_AOE_IN_CPLD_REPROGRAM_REPROGRAM_EVENT 0x3
+/* enum: Get status of reprogramming operation */
+#define	MC_CMD_AOE_IN_CPLD_REPROGRAM_STATUS 0x4
 
 /* MC_CMD_AOE_IN_POWER msgrequest */
 #define	MC_CMD_AOE_IN_POWER_LEN 8
 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
+/* Turn on or off AOE power */
 #define	MC_CMD_AOE_IN_POWER_OP_OFST 4
-#define	MC_CMD_AOE_IN_POWER_OFF  0x0 /* enum */
-#define	MC_CMD_AOE_IN_POWER_ON  0x1 /* enum */
-#define	MC_CMD_AOE_IN_POWER_CLEAR  0x2 /* enum */
-#define	MC_CMD_AOE_IN_POWER_SHOW_CURRENT  0x3 /* enum */
-#define	MC_CMD_AOE_IN_POWER_SHOW_PEAK  0x4 /* enum */
-#define	MC_CMD_AOE_IN_POWER_DDR_LAST  0x5 /* enum */
-#define	MC_CMD_AOE_IN_POWER_DDR_PEAK  0x6 /* enum */
-#define	MC_CMD_AOE_IN_POWER_DDR_CLEAR  0x7 /* enum */
+/* enum: Turn off FPGA power */
+#define	MC_CMD_AOE_IN_POWER_OFF  0x0
+/* enum: Turn on FPGA power */
+#define	MC_CMD_AOE_IN_POWER_ON  0x1
+/* enum: Clear peak power measurement */
+#define	MC_CMD_AOE_IN_POWER_CLEAR  0x2
+/* enum: Show current power in sensors output */
+#define	MC_CMD_AOE_IN_POWER_SHOW_CURRENT  0x3
+/* enum: Show peak power in sensors output */
+#define	MC_CMD_AOE_IN_POWER_SHOW_PEAK  0x4
+/* enum: Show current DDR current */
+#define	MC_CMD_AOE_IN_POWER_DDR_LAST  0x5
+/* enum: Show peak DDR current */
+#define	MC_CMD_AOE_IN_POWER_DDR_PEAK  0x6
+/* enum: Clear peak DDR current */
+#define	MC_CMD_AOE_IN_POWER_DDR_CLEAR  0x7
 
 /* MC_CMD_AOE_IN_LOAD msgrequest */
 #define	MC_CMD_AOE_IN_LOAD_LEN 8
 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
+/* Image to be loaded (0 - main or 1 - diagnostic) to load in normal sequence
+ */
 #define	MC_CMD_AOE_IN_LOAD_IMAGE_OFST 4
 
 /* MC_CMD_AOE_IN_FAN_CONTROL msgrequest */
 #define	MC_CMD_AOE_IN_FAN_CONTROL_LEN 8
 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
+/* If non zero report measured fan RPM rather than nominal */
 #define	MC_CMD_AOE_IN_FAN_CONTROL_REAL_RPM_OFST 4
 
 /* MC_CMD_AOE_IN_FAN_FAILURES msgrequest */
@@ -2111,7 +2958,9 @@
 /* MC_CMD_AOE_IN_MAC_STATS msgrequest */
 #define	MC_CMD_AOE_IN_MAC_STATS_LEN 24
 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
+/* AOE port */
 #define	MC_CMD_AOE_IN_MAC_STATS_PORT_OFST 4
+/* Host memory address for statistics */
 #define	MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_OFST 8
 #define	MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LEN 8
 #define	MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LO_OFST 8
@@ -2131,11 +2980,13 @@
 #define	MC_CMD_AOE_IN_MAC_STATS_PERIODIC_NOEVENT_WIDTH 1
 #define	MC_CMD_AOE_IN_MAC_STATS_PERIOD_MS_LBN 16
 #define	MC_CMD_AOE_IN_MAC_STATS_PERIOD_MS_WIDTH 16
+/* Length of DMA data (optional) */
 #define	MC_CMD_AOE_IN_MAC_STATS_DMA_LEN_OFST 20
 
 /* MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO msgrequest */
 #define	MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_LEN 12
 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
+/* AOE port */
 #define	MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PORT_OFST 4
 #define	MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PAGE_OFST 8
 
@@ -2153,16 +3004,23 @@
 /* MC_CMD_AOE_IN_FPGA_ACCESS msgrequest */
 #define	MC_CMD_AOE_IN_FPGA_ACCESS_LEN 8
 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
+/* Enable or disable access */
 #define	MC_CMD_AOE_IN_FPGA_ACCESS_OP_OFST 4
-#define	MC_CMD_AOE_IN_FPGA_ACCESS_ENABLE 0x1 /* enum */
-#define	MC_CMD_AOE_IN_FPGA_ACCESS_DISABLE 0x2 /* enum */
+/* enum: Enable access */
+#define	MC_CMD_AOE_IN_FPGA_ACCESS_ENABLE 0x1
+/* enum: Disable access */
+#define	MC_CMD_AOE_IN_FPGA_ACCESS_DISABLE 0x2
 
 /* MC_CMD_AOE_IN_SET_MTU_OFFSET msgrequest */
 #define	MC_CMD_AOE_IN_SET_MTU_OFFSET_LEN 12
 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
+/* AOE port - when not ALL_EXTERNAL or ALL_INTERNAL specifies port number */
 #define	MC_CMD_AOE_IN_SET_MTU_OFFSET_PORT_OFST 4
-#define	MC_CMD_AOE_IN_SET_MTU_OFFSET_ALL_EXTERNAL 0x8000 /* enum */
-#define	MC_CMD_AOE_IN_SET_MTU_OFFSET_ALL_INTERNAL 0x4000 /* enum */
+/* enum: Apply to all external ports */
+#define	MC_CMD_AOE_IN_SET_MTU_OFFSET_ALL_EXTERNAL 0x8000
+/* enum: Apply to all internal ports */
+#define	MC_CMD_AOE_IN_SET_MTU_OFFSET_ALL_INTERNAL 0x4000
+/* The MTU offset to be applied to the external ports */
 #define	MC_CMD_AOE_IN_SET_MTU_OFFSET_OFFSET_OFST 8
 
 /* MC_CMD_AOE_IN_LINK_STATE msgrequest */
@@ -2171,31 +3029,52 @@
 #define	MC_CMD_AOE_IN_LINK_STATE_MODE_OFST 4
 #define	MC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_LBN 0
 #define	MC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_WIDTH 8
-#define	MC_CMD_AOE_IN_LINK_STATE_SIMPLE_SEPARATE  0x0 /* enum */
-#define	MC_CMD_AOE_IN_LINK_STATE_SIMPLE_COMBINED  0x1 /* enum */
-#define	MC_CMD_AOE_IN_LINK_STATE_DIAGNOSTIC  0x2 /* enum */
-#define	MC_CMD_AOE_IN_LINK_STATE_CUSTOM  0x3 /* enum */
+/* enum: AOE and associated external port */
+#define	MC_CMD_AOE_IN_LINK_STATE_SIMPLE_SEPARATE  0x0
+/* enum: AOE and OR of all external ports */
+#define	MC_CMD_AOE_IN_LINK_STATE_SIMPLE_COMBINED  0x1
+/* enum: Individual ports */
+#define	MC_CMD_AOE_IN_LINK_STATE_DIAGNOSTIC  0x2
+/* enum: Configure link state mode on given AOE port */
+#define	MC_CMD_AOE_IN_LINK_STATE_CUSTOM  0x3
 #define	MC_CMD_AOE_IN_LINK_STATE_OPERATION_LBN 8
 #define	MC_CMD_AOE_IN_LINK_STATE_OPERATION_WIDTH 8
-#define	MC_CMD_AOE_IN_LINK_STATE_OP_NONE  0x0 /* enum */
-#define	MC_CMD_AOE_IN_LINK_STATE_OP_OR  0x1 /* enum */
-#define	MC_CMD_AOE_IN_LINK_STATE_OP_AND  0x2 /* enum */
+/* enum: No-op */
+#define	MC_CMD_AOE_IN_LINK_STATE_OP_NONE  0x0
+/* enum: logical OR of all SFP ports link status */
+#define	MC_CMD_AOE_IN_LINK_STATE_OP_OR  0x1
+/* enum: logical AND of all SFP ports link status */
+#define	MC_CMD_AOE_IN_LINK_STATE_OP_AND  0x2
 #define	MC_CMD_AOE_IN_LINK_STATE_SFP_MASK_LBN 16
 #define	MC_CMD_AOE_IN_LINK_STATE_SFP_MASK_WIDTH 16
 
 /* MC_CMD_AOE_IN_SIENA_STATS msgrequest */
 #define	MC_CMD_AOE_IN_SIENA_STATS_LEN 8
 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
+/* How MAC statistics are reported */
 #define	MC_CMD_AOE_IN_SIENA_STATS_MODE_OFST 4
-#define	MC_CMD_AOE_IN_SIENA_STATS_STATS_SIENA  0x0 /* enum */
-#define	MC_CMD_AOE_IN_SIENA_STATS_STATS_AOE  0x1 /* enum */
+/* enum: Statistics from Siena (default) */
+#define	MC_CMD_AOE_IN_SIENA_STATS_STATS_SIENA  0x0
+/* enum: Statistics from AOE external ports */
+#define	MC_CMD_AOE_IN_SIENA_STATS_STATS_AOE  0x1
+
+/* MC_CMD_AOE_IN_ASIC_STATS msgrequest */
+#define	MC_CMD_AOE_IN_ASIC_STATS_LEN 8
+/*            MC_CMD_AOE_IN_CMD_OFST 0 */
+/* How MAC statistics are reported */
+#define	MC_CMD_AOE_IN_ASIC_STATS_MODE_OFST 4
+/* enum: Statistics from the ASIC (default) */
+#define	MC_CMD_AOE_IN_ASIC_STATS_STATS_ASIC  0x0
+/* enum: Statistics from AOE external ports */
+#define	MC_CMD_AOE_IN_ASIC_STATS_STATS_AOE  0x1
 
 /* MC_CMD_AOE_IN_DDR msgrequest */
 #define	MC_CMD_AOE_IN_DDR_LEN 12
 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
 #define	MC_CMD_AOE_IN_DDR_BANK_OFST 4
 /*            Enum values, see field(s): */
-/*               MC_CMD_FC_IN_DDR_BANK */
+/*               MC_CMD_FC/MC_CMD_FC_IN_DDR/MC_CMD_FC_IN_DDR_BANK */
+/* Page index of SPD data */
 #define	MC_CMD_AOE_IN_DDR_SPD_PAGE_ID_OFST 8
 
 /* MC_CMD_AOE_IN_FC msgrequest */
@@ -2207,14 +3086,17 @@
 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
 #define	MC_CMD_AOE_IN_DDR_ECC_STATUS_BANK_OFST 4
 /*            Enum values, see field(s): */
-/*               MC_CMD_FC_IN_DDR_BANK */
+/*               MC_CMD_FC/MC_CMD_FC_IN_DDR/MC_CMD_FC_IN_DDR_BANK */
 
 /* MC_CMD_AOE_IN_MC_SPI_MASTER msgrequest */
 #define	MC_CMD_AOE_IN_MC_SPI_MASTER_LEN 8
 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
+/* Basic commands for MC SPI Master emulation. */
 #define	MC_CMD_AOE_IN_MC_SPI_MASTER_OP_OFST 4
-#define	MC_CMD_AOE_IN_MC_SPI_MASTER_READ 0x0 /* enum */
-#define	MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE 0x1 /* enum */
+/* enum: MC SPI read */
+#define	MC_CMD_AOE_IN_MC_SPI_MASTER_READ 0x0
+/* enum: MC SPI write */
+#define	MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE 0x1
 
 /* MC_CMD_AOE_IN_MC_SPI_MASTER_READ msgrequest */
 #define	MC_CMD_AOE_IN_MC_SPI_MASTER_READ_LEN 12
@@ -2229,42 +3111,80 @@
 #define	MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OFFSET_OFST 8
 #define	MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_DATA_OFST 12
 
+/* MC_CMD_AOE_IN_FC_BOOT msgrequest */
+#define	MC_CMD_AOE_IN_FC_BOOT_LEN 8
+/*            MC_CMD_AOE_IN_CMD_OFST 0 */
+/* FC boot control flags */
+#define	MC_CMD_AOE_IN_FC_BOOT_CONTROL_OFST 4
+#define	MC_CMD_AOE_IN_FC_BOOT_CONTROL_BOOT_ENABLE_LBN 0
+#define	MC_CMD_AOE_IN_FC_BOOT_CONTROL_BOOT_ENABLE_WIDTH 1
+
 /* MC_CMD_AOE_OUT_INFO msgresponse */
 #define	MC_CMD_AOE_OUT_INFO_LEN 44
+/* JTAG IDCODE of CPLD */
 #define	MC_CMD_AOE_OUT_INFO_CPLD_IDCODE_OFST 0
+/* Version of CPLD */
 #define	MC_CMD_AOE_OUT_INFO_CPLD_VERSION_OFST 4
+/* JTAG IDCODE of FPGA */
 #define	MC_CMD_AOE_OUT_INFO_FPGA_IDCODE_OFST 8
+/* JTAG USERCODE of FPGA */
 #define	MC_CMD_AOE_OUT_INFO_FPGA_VERSION_OFST 12
+/* FPGA type - read from CPLD straps */
 #define	MC_CMD_AOE_OUT_INFO_FPGA_TYPE_OFST 16
+/* FPGA state (debug) */
 #define	MC_CMD_AOE_OUT_INFO_FPGA_STATE_OFST 20
+/* FPGA image - partition from which loaded */
 #define	MC_CMD_AOE_OUT_INFO_FPGA_IMAGE_OFST 24
+/* FC state */
 #define	MC_CMD_AOE_OUT_INFO_FC_STATE_OFST 28
-#define	MC_CMD_AOE_OUT_INFO_WATCHDOG 0x1 /* enum */
-#define	MC_CMD_AOE_OUT_INFO_COMMS 0x2 /* enum */
+/* enum: Set if watchdog working */
+#define	MC_CMD_AOE_OUT_INFO_WATCHDOG 0x1
+/* enum: Set if MC-FC communications working */
+#define	MC_CMD_AOE_OUT_INFO_COMMS 0x2
+/* Random pieces of information */
 #define	MC_CMD_AOE_OUT_INFO_FLAGS_OFST 32
-#define	MC_CMD_AOE_OUT_INFO_PEG_POWER 0x1 /* enum */
-#define	MC_CMD_AOE_OUT_INFO_CPLD_GOOD 0x2 /* enum */
-#define	MC_CMD_AOE_OUT_INFO_FPGA_GOOD 0x4 /* enum */
-#define	MC_CMD_AOE_OUT_INFO_FPGA_POWER 0x8 /* enum */
-#define	MC_CMD_AOE_OUT_INFO_BAD_SODIMM 0x10 /* enum */
-#define	MC_CMD_AOE_OUT_INFO_HAS_BYTEBLASTER 0x20 /* enum */
+/* enum: Power to FPGA supplied by PEG connector, not PCIe bus */
+#define	MC_CMD_AOE_OUT_INFO_PEG_POWER 0x1
+/* enum: CPLD apparently good */
+#define	MC_CMD_AOE_OUT_INFO_CPLD_GOOD 0x2
+/* enum: FPGA working normally */
+#define	MC_CMD_AOE_OUT_INFO_FPGA_GOOD 0x4
+/* enum: FPGA is powered */
+#define	MC_CMD_AOE_OUT_INFO_FPGA_POWER 0x8
+/* enum: Board has incompatible SODIMMs fitted */
+#define	MC_CMD_AOE_OUT_INFO_BAD_SODIMM 0x10
+/* enum: Board has ByteBlaster connected */
+#define	MC_CMD_AOE_OUT_INFO_HAS_BYTEBLASTER 0x20
+/* Revision of Modena board */
 #define	MC_CMD_AOE_OUT_INFO_BOARD_REVISION_OFST 36
 #define	MC_CMD_AOE_OUT_INFO_UNKNOWN  0x0 /* enum */
 #define	MC_CMD_AOE_OUT_INFO_R1_0  0x10 /* enum */
 #define	MC_CMD_AOE_OUT_INFO_R1_1  0x11 /* enum */
 #define	MC_CMD_AOE_OUT_INFO_R1_2  0x12 /* enum */
+/* Result of FC booting - not valid while a ByteBlaster is connected. */
 #define	MC_CMD_AOE_OUT_INFO_FC_BOOT_RESULT_OFST 40
-#define	MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_NO_ERROR 0x0 /* enum */
-#define	MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_ADDRESS 0x1 /* enum */
-#define	MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_MAGIC 0x2 /* enum */
-#define	MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_TEXT 0x3 /* enum */
-#define	MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_CHECKSUM 0x4 /* enum */
-#define	MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_BSP 0x5 /* enum */
-#define	MC_CMD_AOE_OUT_INFO_FC_BOOT_APP_EXECUTE 0x80 /* enum */
-#define	MC_CMD_AOE_OUT_INFO_FC_BOOT_NO_BOOTROM 0xff /* enum */
+/* enum: No error */
+#define	MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_NO_ERROR 0x0
+/* enum: Bad address set in CPLD */
+#define	MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_ADDRESS 0x1
+/* enum: Bad header */
+#define	MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_MAGIC 0x2
+/* enum: Bad text section details */
+#define	MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_TEXT 0x3
+/* enum: Bad checksum */
+#define	MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_CHECKSUM 0x4
+/* enum: Bad BSP */
+#define	MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_BSP 0x5
+/* enum: FC application loaded and execution attempted */
+#define	MC_CMD_AOE_OUT_INFO_FC_BOOT_APP_EXECUTE 0x80
+/* enum: FC application Started */
+#define	MC_CMD_AOE_OUT_INFO_FC_BOOT_APP_STARTED 0x81
+/* enum: No bootrom in FPGA */
+#define	MC_CMD_AOE_OUT_INFO_FC_BOOT_NO_BOOTROM 0xff
 
 /* MC_CMD_AOE_OUT_CURRENTS msgresponse */
 #define	MC_CMD_AOE_OUT_CURRENTS_LEN 68
+/* Set of currents and voltages (mA or mV as appropriate) */
 #define	MC_CMD_AOE_OUT_CURRENTS_VALUES_OFST 0
 #define	MC_CMD_AOE_OUT_CURRENTS_VALUES_LEN 4
 #define	MC_CMD_AOE_OUT_CURRENTS_VALUES_NUM 17
@@ -2288,10 +3208,12 @@
 
 /* MC_CMD_AOE_OUT_TEMPERATURES msgresponse */
 #define	MC_CMD_AOE_OUT_TEMPERATURES_LEN 40
+/* Set of temperatures */
 #define	MC_CMD_AOE_OUT_TEMPERATURES_VALUES_OFST 0
 #define	MC_CMD_AOE_OUT_TEMPERATURES_VALUES_LEN 4
 #define	MC_CMD_AOE_OUT_TEMPERATURES_VALUES_NUM 10
-#define	MC_CMD_AOE_OUT_TEMPERATURES_MAIN_0 0x0 /* enum */
+/* enum: The first set of enum values are for Modena code. */
+#define	MC_CMD_AOE_OUT_TEMPERATURES_MAIN_0 0x0
 #define	MC_CMD_AOE_OUT_TEMPERATURES_MAIN_1 0x1 /* enum */
 #define	MC_CMD_AOE_OUT_TEMPERATURES_IND_0 0x2 /* enum */
 #define	MC_CMD_AOE_OUT_TEMPERATURES_IND_1 0x3 /* enum */
@@ -2301,15 +3223,27 @@
 #define	MC_CMD_AOE_OUT_TEMPERATURES_PSU 0x7 /* enum */
 #define	MC_CMD_AOE_OUT_TEMPERATURES_FPGA 0x8 /* enum */
 #define	MC_CMD_AOE_OUT_TEMPERATURES_SIENA 0x9 /* enum */
+/* enum: The second set of enum values are for Sorrento code. */
+#define	MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_MAIN_0 0x0
+#define	MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_MAIN_1 0x1 /* enum */
+#define	MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_IND_0 0x2 /* enum */
+#define	MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_IND_1 0x3 /* enum */
+#define	MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_SODIMM_0 0x4 /* enum */
+#define	MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_SODIMM_1 0x5 /* enum */
+#define	MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_FPGA 0x6 /* enum */
+#define	MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_PHY0 0x7 /* enum */
+#define	MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_PHY1 0x8 /* enum */
 
 /* MC_CMD_AOE_OUT_CPLD_READ msgresponse */
 #define	MC_CMD_AOE_OUT_CPLD_READ_LEN 4
+/* The value read from the CPLD */
 #define	MC_CMD_AOE_OUT_CPLD_READ_VALUE_OFST 0
 
 /* MC_CMD_AOE_OUT_FAN_FAILURES msgresponse */
 #define	MC_CMD_AOE_OUT_FAN_FAILURES_LENMIN 4
 #define	MC_CMD_AOE_OUT_FAN_FAILURES_LENMAX 252
 #define	MC_CMD_AOE_OUT_FAN_FAILURES_LEN(num) (0+4*(num))
+/* Failure counts for each fan */
 #define	MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_OFST 0
 #define	MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_LEN 4
 #define	MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_MINNUM 1
@@ -2317,12 +3251,24 @@
 
 /* MC_CMD_AOE_OUT_CPLD_REPROGRAM msgresponse */
 #define	MC_CMD_AOE_OUT_CPLD_REPROGRAM_LEN 4
+/* Results of status command (only) */
 #define	MC_CMD_AOE_OUT_CPLD_REPROGRAM_STATUS_OFST 0
 
+/* MC_CMD_AOE_OUT_POWER_OFF msgresponse */
+#define	MC_CMD_AOE_OUT_POWER_OFF_LEN 0
+
+/* MC_CMD_AOE_OUT_POWER_ON msgresponse */
+#define	MC_CMD_AOE_OUT_POWER_ON_LEN 0
+
+/* MC_CMD_AOE_OUT_LOAD msgresponse */
+#define	MC_CMD_AOE_OUT_LOAD_LEN 0
+
 /* MC_CMD_AOE_OUT_MAC_STATS_DMA msgresponse */
 #define	MC_CMD_AOE_OUT_MAC_STATS_DMA_LEN 0
 
-/* MC_CMD_AOE_OUT_MAC_STATS_NO_DMA msgresponse */
+/* MC_CMD_AOE_OUT_MAC_STATS_NO_DMA msgresponse: See MC_CMD_MAC_STATS_OUT_NO_DMA
+ * for details
+ */
 #define	MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3)
 #define	MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_OFST 0
 #define	MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LEN 8
@@ -2334,6 +3280,7 @@
 #define	MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMIN 5
 #define	MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMAX 252
 #define	MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LEN(num) (4+1*(num))
+/* in bytes */
 #define	MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATALEN_OFST 0
 #define	MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_OFST 4
 #define	MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_LEN 1
@@ -2344,7 +3291,9 @@
 #define	MC_CMD_AOE_OUT_JTAG_WRITE_LENMIN 12
 #define	MC_CMD_AOE_OUT_JTAG_WRITE_LENMAX 252
 #define	MC_CMD_AOE_OUT_JTAG_WRITE_LEN(num) (8+4*(num))
+/* Used to align the in and out data blocks so the MC can re-use the cmd */
 #define	MC_CMD_AOE_OUT_JTAG_WRITE_DATALEN_OFST 0
+/* out bytes */
 #define	MC_CMD_AOE_OUT_JTAG_WRITE_PAD_OFST 4
 #define	MC_CMD_AOE_OUT_JTAG_WRITE_DATA_OFST 8
 #define	MC_CMD_AOE_OUT_JTAG_WRITE_DATA_LEN 4
@@ -2358,6 +3307,7 @@
 #define	MC_CMD_AOE_OUT_DDR_LENMIN 17
 #define	MC_CMD_AOE_OUT_DDR_LENMAX 252
 #define	MC_CMD_AOE_OUT_DDR_LEN(num) (16+1*(num))
+/* Information on the module. */
 #define	MC_CMD_AOE_OUT_DDR_FLAGS_OFST 0
 #define	MC_CMD_AOE_OUT_DDR_PRESENT_LBN 0
 #define	MC_CMD_AOE_OUT_DDR_PRESENT_WIDTH 1
@@ -2365,25 +3315,42 @@
 #define	MC_CMD_AOE_OUT_DDR_POWERED_WIDTH 1
 #define	MC_CMD_AOE_OUT_DDR_OPERATIONAL_LBN 2
 #define	MC_CMD_AOE_OUT_DDR_OPERATIONAL_WIDTH 1
+#define	MC_CMD_AOE_OUT_DDR_NOT_REACHABLE_LBN 3
+#define	MC_CMD_AOE_OUT_DDR_NOT_REACHABLE_WIDTH 1
+/* Memory size, in MB. */
 #define	MC_CMD_AOE_OUT_DDR_CAPACITY_OFST 4
+/* The memory type, as reported from SPD information */
 #define	MC_CMD_AOE_OUT_DDR_TYPE_OFST 8
+/* Nominal voltage of the module (as applied) */
 #define	MC_CMD_AOE_OUT_DDR_VOLTAGE_OFST 12
+/* SPD data read from the module */
 #define	MC_CMD_AOE_OUT_DDR_SPD_OFST 16
 #define	MC_CMD_AOE_OUT_DDR_SPD_LEN 1
 #define	MC_CMD_AOE_OUT_DDR_SPD_MINNUM 1
 #define	MC_CMD_AOE_OUT_DDR_SPD_MAXNUM 236
 
+/* MC_CMD_AOE_OUT_SET_MTU_OFFSET msgresponse */
+#define	MC_CMD_AOE_OUT_SET_MTU_OFFSET_LEN 0
+
 /* MC_CMD_AOE_OUT_LINK_STATE msgresponse */
 #define	MC_CMD_AOE_OUT_LINK_STATE_LEN 0
 
+/* MC_CMD_AOE_OUT_SIENA_STATS msgresponse */
+#define	MC_CMD_AOE_OUT_SIENA_STATS_LEN 0
+
+/* MC_CMD_AOE_OUT_ASIC_STATS msgresponse */
+#define	MC_CMD_AOE_OUT_ASIC_STATS_LEN 0
+
 /* MC_CMD_AOE_OUT_FC msgresponse */
 #define	MC_CMD_AOE_OUT_FC_LEN 0
 
 /* MC_CMD_AOE_OUT_DDR_ECC_STATUS msgresponse */
 #define	MC_CMD_AOE_OUT_DDR_ECC_STATUS_LEN 8
+/* Flags describing status info on the module. */
 #define	MC_CMD_AOE_OUT_DDR_ECC_STATUS_FLAGS_OFST 0
 #define	MC_CMD_AOE_OUT_DDR_ECC_STATUS_VALID_LBN 0
 #define	MC_CMD_AOE_OUT_DDR_ECC_STATUS_VALID_WIDTH 1
+/* DDR ECC status on the module. */
 #define	MC_CMD_AOE_OUT_DDR_ECC_STATUS_STATUS_OFST 4
 #define	MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_LBN 0
 #define	MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_WIDTH 1
@@ -2408,51 +3375,113 @@
 /* MC_CMD_AOE_OUT_MC_SPI_MASTER msgresponse */
 #define	MC_CMD_AOE_OUT_MC_SPI_MASTER_LEN 0
 
+/* MC_CMD_AOE_OUT_FC_BOOT msgresponse */
+#define	MC_CMD_AOE_OUT_FC_BOOT_LEN 0
+
 
 /***********************************/
-/* MC_CMD_PTP 
+/* MC_CMD_PTP
  * Perform PTP operation
  */
-#define	MC_CMD_PTP  0xb
+#define	MC_CMD_PTP 0xb
+#undef	MC_CMD_0xb_PRIVILEGE_CTG
+
+#define	MC_CMD_0xb_PRIVILEGE_CTG SRIOV_CTG_GENERAL
 
 /* MC_CMD_PTP_IN msgrequest */
 #define	MC_CMD_PTP_IN_LEN 1
+/* PTP operation code */
 #define	MC_CMD_PTP_IN_OP_OFST 0
 #define	MC_CMD_PTP_IN_OP_LEN 1
-#define	MC_CMD_PTP_OP_ENABLE 0x1 /* enum */
-#define	MC_CMD_PTP_OP_DISABLE 0x2 /* enum */
-#define	MC_CMD_PTP_OP_TRANSMIT 0x3 /* enum */
-#define	MC_CMD_PTP_OP_READ_NIC_TIME 0x4 /* enum */
-#define	MC_CMD_PTP_OP_STATUS 0x5 /* enum */
-#define	MC_CMD_PTP_OP_ADJUST 0x6 /* enum */
-#define	MC_CMD_PTP_OP_SYNCHRONIZE 0x7 /* enum */
-#define	MC_CMD_PTP_OP_MANFTEST_BASIC 0x8 /* enum */
-#define	MC_CMD_PTP_OP_MANFTEST_PACKET 0x9 /* enum */
-#define	MC_CMD_PTP_OP_RESET_STATS 0xa /* enum */
-#define	MC_CMD_PTP_OP_DEBUG 0xb /* enum */
-#define	MC_CMD_PTP_OP_FPGAREAD 0xc /* enum */
-#define	MC_CMD_PTP_OP_FPGAWRITE 0xd /* enum */
-#define	MC_CMD_PTP_OP_CLOCK_OFFSET_ADJUST 0xe /* enum */
-#define	MC_CMD_PTP_OP_CLOCK_FREQ_ADJUST 0xf /* enum */
-#define	MC_CMD_PTP_OP_RX_SET_VLAN_FILTER 0x10 /* enum */
-#define	MC_CMD_PTP_OP_RX_SET_UUID_FILTER 0x11 /* enum */
-#define	MC_CMD_PTP_OP_RX_SET_DOMAIN_FILTER 0x12 /* enum */
-#define	MC_CMD_PTP_OP_SET_CLK_SRC 0x13 /* enum */
-#define	MC_CMD_PTP_OP_RST_CLK 0x14 /* enum */
-#define	MC_CMD_PTP_OP_PPS_ENABLE 0x15 /* enum */
-#define	MC_CMD_PTP_OP_MAX 0x16 /* enum */
+/* enum: Enable PTP packet timestamping operation. */
+#define	MC_CMD_PTP_OP_ENABLE 0x1
+/* enum: Disable PTP packet timestamping operation. */
+#define	MC_CMD_PTP_OP_DISABLE 0x2
+/* enum: Send a PTP packet. */
+#define	MC_CMD_PTP_OP_TRANSMIT 0x3
+/* enum: Read the current NIC time. */
+#define	MC_CMD_PTP_OP_READ_NIC_TIME 0x4
+/* enum: Get the current PTP status. */
+#define	MC_CMD_PTP_OP_STATUS 0x5
+/* enum: Adjust the PTP NIC's time. */
+#define	MC_CMD_PTP_OP_ADJUST 0x6
+/* enum: Synchronize host and NIC time. */
+#define	MC_CMD_PTP_OP_SYNCHRONIZE 0x7
+/* enum: Basic manufacturing tests. */
+#define	MC_CMD_PTP_OP_MANFTEST_BASIC 0x8
+/* enum: Packet based manufacturing tests. */
+#define	MC_CMD_PTP_OP_MANFTEST_PACKET 0x9
+/* enum: Reset some of the PTP related statistics */
+#define	MC_CMD_PTP_OP_RESET_STATS 0xa
+/* enum: Debug operations to MC. */
+#define	MC_CMD_PTP_OP_DEBUG 0xb
+/* enum: Read an FPGA register */
+#define	MC_CMD_PTP_OP_FPGAREAD 0xc
+/* enum: Write an FPGA register */
+#define	MC_CMD_PTP_OP_FPGAWRITE 0xd
+/* enum: Apply an offset to the NIC clock */
+#define	MC_CMD_PTP_OP_CLOCK_OFFSET_ADJUST 0xe
+/* enum: Change Apply an offset to the NIC clock */
+#define	MC_CMD_PTP_OP_CLOCK_FREQ_ADJUST 0xf
+/* enum: Set the MC packet filter VLAN tags for received PTP packets */
+#define	MC_CMD_PTP_OP_RX_SET_VLAN_FILTER 0x10
+/* enum: Set the MC packet filter UUID for received PTP packets */
+#define	MC_CMD_PTP_OP_RX_SET_UUID_FILTER 0x11
+/* enum: Set the MC packet filter Domain for received PTP packets */
+#define	MC_CMD_PTP_OP_RX_SET_DOMAIN_FILTER 0x12
+/* enum: Set the clock source */
+#define	MC_CMD_PTP_OP_SET_CLK_SRC 0x13
+/* enum: Reset value of Timer Reg. */
+#define	MC_CMD_PTP_OP_RST_CLK 0x14
+/* enum: Enable the forwarding of PPS events to the host */
+#define	MC_CMD_PTP_OP_PPS_ENABLE 0x15
+/* enum: Get the time format used by this NIC for PTP operations */
+#define	MC_CMD_PTP_OP_GET_TIME_FORMAT 0x16
+/* enum: Get the clock attributes. NOTE- extended version of
+ * MC_CMD_PTP_OP_GET_TIME_FORMAT
+ */
+#define	MC_CMD_PTP_OP_GET_ATTRIBUTES 0x16
+/* enum: Get corrections that should be applied to the various different
+ * timestamps
+ */
+#define	MC_CMD_PTP_OP_GET_TIMESTAMP_CORRECTIONS 0x17
+/* enum: Subscribe to receive periodic time events indicating the current NIC
+ * time
+ */
+#define	MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE 0x18
+/* enum: Unsubscribe to stop receiving time events */
+#define	MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE 0x19
+/* enum: PPS based manfacturing tests. Requires PPS output to be looped to PPS
+ * input on the same NIC.
+ */
+#define	MC_CMD_PTP_OP_MANFTEST_PPS 0x1a
+/* enum: Set the PTP sync status. Status is used by firmware to report to event
+ * subscribers.
+ */
+#define	MC_CMD_PTP_OP_SET_SYNC_STATUS 0x1b
+/* enum: Above this for future use. */
+#define	MC_CMD_PTP_OP_MAX 0x1c
 
 /* MC_CMD_PTP_IN_ENABLE msgrequest */
 #define	MC_CMD_PTP_IN_ENABLE_LEN 16
 #define	MC_CMD_PTP_IN_CMD_OFST 0
 #define	MC_CMD_PTP_IN_PERIPH_ID_OFST 4
+/* Event queue for PTP events */
 #define	MC_CMD_PTP_IN_ENABLE_QUEUE_OFST 8
+/* PTP timestamping mode */
 #define	MC_CMD_PTP_IN_ENABLE_MODE_OFST 12
-#define	MC_CMD_PTP_MODE_V1 0x0 /* enum */
-#define	MC_CMD_PTP_MODE_V1_VLAN 0x1 /* enum */
-#define	MC_CMD_PTP_MODE_V2 0x2 /* enum */
-#define	MC_CMD_PTP_MODE_V2_VLAN 0x3 /* enum */
-#define	MC_CMD_PTP_MODE_V2_ENHANCED 0x4 /* enum */
+/* enum: PTP, version 1 */
+#define	MC_CMD_PTP_MODE_V1 0x0
+/* enum: PTP, version 1, with VLAN headers - deprecated */
+#define	MC_CMD_PTP_MODE_V1_VLAN 0x1
+/* enum: PTP, version 2 */
+#define	MC_CMD_PTP_MODE_V2 0x2
+/* enum: PTP, version 2, with VLAN headers - deprecated */
+#define	MC_CMD_PTP_MODE_V2_VLAN 0x3
+/* enum: PTP, version 2, with improved UUID filtering */
+#define	MC_CMD_PTP_MODE_V2_ENHANCED 0x4
+/* enum: FCoE (seconds and microseconds) */
+#define	MC_CMD_PTP_MODE_FCOE 0x5
 
 /* MC_CMD_PTP_IN_DISABLE msgrequest */
 #define	MC_CMD_PTP_IN_DISABLE_LEN 8
@@ -2465,7 +3494,9 @@
 #define	MC_CMD_PTP_IN_TRANSMIT_LEN(num) (12+1*(num))
 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
+/* Transmit packet length */
 #define	MC_CMD_PTP_IN_TRANSMIT_LENGTH_OFST 8
+/* Transmit packet data */
 #define	MC_CMD_PTP_IN_TRANSMIT_PACKET_OFST 12
 #define	MC_CMD_PTP_IN_TRANSMIT_PACKET_LEN 1
 #define	MC_CMD_PTP_IN_TRANSMIT_PACKET_MINNUM 1
@@ -2485,19 +3516,31 @@
 #define	MC_CMD_PTP_IN_ADJUST_LEN 24
 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
+/* Frequency adjustment 40 bit fixed point ns */
 #define	MC_CMD_PTP_IN_ADJUST_FREQ_OFST 8
 #define	MC_CMD_PTP_IN_ADJUST_FREQ_LEN 8
 #define	MC_CMD_PTP_IN_ADJUST_FREQ_LO_OFST 8
 #define	MC_CMD_PTP_IN_ADJUST_FREQ_HI_OFST 12
-#define	MC_CMD_PTP_IN_ADJUST_BITS 0x28 /* enum */
+/* enum: Number of fractional bits in frequency adjustment */
+#define	MC_CMD_PTP_IN_ADJUST_BITS 0x28
+/* Time adjustment in seconds */
 #define	MC_CMD_PTP_IN_ADJUST_SECONDS_OFST 16
+/* Time adjustment major value */
+#define	MC_CMD_PTP_IN_ADJUST_MAJOR_OFST 16
+/* Time adjustment in nanoseconds */
 #define	MC_CMD_PTP_IN_ADJUST_NANOSECONDS_OFST 20
+/* Time adjustment minor value */
+#define	MC_CMD_PTP_IN_ADJUST_MINOR_OFST 20
 
 /* MC_CMD_PTP_IN_SYNCHRONIZE msgrequest */
 #define	MC_CMD_PTP_IN_SYNCHRONIZE_LEN 20
 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
+/* Number of time readings to capture */
 #define	MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_OFST 8
+/* Host address in which to write "synchronization started" indication (64
+ * bits)
+ */
 #define	MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_OFST 12
 #define	MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LEN 8
 #define	MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_OFST 12
@@ -2512,17 +3555,20 @@
 #define	MC_CMD_PTP_IN_MANFTEST_PACKET_LEN 12
 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
+/* Enable or disable packet testing */
 #define	MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_OFST 8
 
 /* MC_CMD_PTP_IN_RESET_STATS msgrequest */
 #define	MC_CMD_PTP_IN_RESET_STATS_LEN 8
 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
+/* Reset PTP statistics */
 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
 
 /* MC_CMD_PTP_IN_DEBUG msgrequest */
 #define	MC_CMD_PTP_IN_DEBUG_LEN 12
 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
+/* Debug operations */
 #define	MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_OFST 8
 
 /* MC_CMD_PTP_IN_FPGAREAD msgrequest */
@@ -2548,24 +3594,34 @@
 #define	MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_LEN 16
 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
+/* Time adjustment in seconds */
 #define	MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_OFST 8
+/* Time adjustment major value */
+#define	MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MAJOR_OFST 8
+/* Time adjustment in nanoseconds */
 #define	MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_OFST 12
+/* Time adjustment minor value */
+#define	MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MINOR_OFST 12
 
 /* MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST msgrequest */
 #define	MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_LEN 16
 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
+/* Frequency adjustment 40 bit fixed point ns */
 #define	MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_OFST 8
 #define	MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LEN 8
 #define	MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_OFST 8
 #define	MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_OFST 12
+/* enum: Number of fractional bits in frequency adjustment */
 /*               MC_CMD_PTP_IN_ADJUST_BITS 0x28 */
 
 /* MC_CMD_PTP_IN_RX_SET_VLAN_FILTER msgrequest */
 #define	MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_LEN 24
 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
+/* Number of VLAN tags, 0 if not VLAN */
 #define	MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_OFST 8
+/* Set of VLAN tags to filter against */
 #define	MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_OFST 12
 #define	MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_LEN 4
 #define	MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_NUM 3
@@ -2574,7 +3630,9 @@
 #define	MC_CMD_PTP_IN_RX_SET_UUID_FILTER_LEN 20
 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
+/* 1 to enable UUID filtering, 0 to disable */
 #define	MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_OFST 8
+/* UUID to filter against */
 #define	MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_OFST 12
 #define	MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LEN 8
 #define	MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_OFST 12
@@ -2584,82 +3642,237 @@
 #define	MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_LEN 16
 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
 /*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
+/* 1 to enable Domain filtering, 0 to disable */
 #define	MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_OFST 8
+/* Domain number to filter against */
 #define	MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_OFST 12
 
+/* MC_CMD_PTP_IN_SET_CLK_SRC msgrequest */
+#define	MC_CMD_PTP_IN_SET_CLK_SRC_LEN 12
+/*            MC_CMD_PTP_IN_CMD_OFST 0 */
+/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
+/* Set the clock source. */
+#define	MC_CMD_PTP_IN_SET_CLK_SRC_CLK_OFST 8
+/* enum: Internal. */
+#define	MC_CMD_PTP_CLK_SRC_INTERNAL 0x0
+/* enum: External. */
+#define	MC_CMD_PTP_CLK_SRC_EXTERNAL 0x1
+
+/* MC_CMD_PTP_IN_RST_CLK msgrequest */
+#define	MC_CMD_PTP_IN_RST_CLK_LEN 8
+/*            MC_CMD_PTP_IN_CMD_OFST 0 */
+/* Reset value of Timer Reg. */
+/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
+
 /* MC_CMD_PTP_IN_PPS_ENABLE msgrequest */
 #define	MC_CMD_PTP_IN_PPS_ENABLE_LEN 12
 /*            MC_CMD_PTP_IN_CMD_OFST 0 */
+/* Enable or disable */
 #define	MC_CMD_PTP_IN_PPS_ENABLE_OP_OFST 4
-#define	MC_CMD_PTP_ENABLE_PPS 0x0 /* enum */
-#define	MC_CMD_PTP_DISABLE_PPS 0x1 /* enum */
+/* enum: Enable */
+#define	MC_CMD_PTP_ENABLE_PPS 0x0
+/* enum: Disable */
+#define	MC_CMD_PTP_DISABLE_PPS 0x1
+/* Queue id to send events back */
 #define	MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_OFST 8
 
+/* MC_CMD_PTP_IN_GET_TIME_FORMAT msgrequest */
+#define	MC_CMD_PTP_IN_GET_TIME_FORMAT_LEN 8
+/*            MC_CMD_PTP_IN_CMD_OFST 0 */
+/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
+
+/* MC_CMD_PTP_IN_GET_ATTRIBUTES msgrequest */
+#define	MC_CMD_PTP_IN_GET_ATTRIBUTES_LEN 8
+/*            MC_CMD_PTP_IN_CMD_OFST 0 */
+/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
+
+/* MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS msgrequest */
+#define	MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS_LEN 8
+/*            MC_CMD_PTP_IN_CMD_OFST 0 */
+/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
+
+/* MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE msgrequest */
+#define	MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN 12
+/*            MC_CMD_PTP_IN_CMD_OFST 0 */
+/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
+/* Original field containing queue ID. Now extended to include flags. */
+#define	MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_OFST 8
+#define	MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_LBN 0
+#define	MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_WIDTH 16
+#define	MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_LBN 31
+#define	MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_REPORT_SYNC_STATUS_WIDTH 1
+
+/* MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE msgrequest */
+#define	MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN 16
+/*            MC_CMD_PTP_IN_CMD_OFST 0 */
+/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
+/* Unsubscribe options */
+#define	MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL_OFST 8
+/* enum: Unsubscribe a single queue */
+#define	MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE 0x0
+/* enum: Unsubscribe all queues */
+#define	MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_ALL 0x1
+/* Event queue ID */
+#define	MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_OFST 12
+
+/* MC_CMD_PTP_IN_MANFTEST_PPS msgrequest */
+#define	MC_CMD_PTP_IN_MANFTEST_PPS_LEN 12
+/*            MC_CMD_PTP_IN_CMD_OFST 0 */
+/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
+/* 1 to enable PPS test mode, 0 to disable and return result. */
+#define	MC_CMD_PTP_IN_MANFTEST_PPS_TEST_ENABLE_OFST 8
+
+/* MC_CMD_PTP_IN_SET_SYNC_STATUS msgrequest */
+#define	MC_CMD_PTP_IN_SET_SYNC_STATUS_LEN 24
+/*            MC_CMD_PTP_IN_CMD_OFST 0 */
+/*            MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
+/* NIC - Host System Clock Synchronization status */
+#define	MC_CMD_PTP_IN_SET_SYNC_STATUS_STATUS_OFST 8
+/* enum: Host System clock and NIC clock are not in sync */
+#define	MC_CMD_PTP_IN_SET_SYNC_STATUS_NOT_IN_SYNC 0x0
+/* enum: Host System clock and NIC clock are synchronized */
+#define	MC_CMD_PTP_IN_SET_SYNC_STATUS_IN_SYNC 0x1
+/* If synchronized, number of seconds until clocks should be considered to be
+ * no longer in sync.
+ */
+#define	MC_CMD_PTP_IN_SET_SYNC_STATUS_TIMEOUT_OFST 12
+#define	MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED0_OFST 16
+#define	MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED1_OFST 20
+
 /* MC_CMD_PTP_OUT msgresponse */
 #define	MC_CMD_PTP_OUT_LEN 0
 
 /* MC_CMD_PTP_OUT_TRANSMIT msgresponse */
 #define	MC_CMD_PTP_OUT_TRANSMIT_LEN 8
+/* Value of seconds timestamp */
 #define	MC_CMD_PTP_OUT_TRANSMIT_SECONDS_OFST 0
+/* Timestamp major value */
+#define	MC_CMD_PTP_OUT_TRANSMIT_MAJOR_OFST 0
+/* Value of nanoseconds timestamp */
 #define	MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_OFST 4
+/* Timestamp minor value */
+#define	MC_CMD_PTP_OUT_TRANSMIT_MINOR_OFST 4
+
+/* MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE msgresponse */
+#define	MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE_LEN 0
+
+/* MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE msgresponse */
+#define	MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE_LEN 0
 
 /* MC_CMD_PTP_OUT_READ_NIC_TIME msgresponse */
 #define	MC_CMD_PTP_OUT_READ_NIC_TIME_LEN 8
+/* Value of seconds timestamp */
 #define	MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_OFST 0
+/* Timestamp major value */
+#define	MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_OFST 0
+/* Value of nanoseconds timestamp */
 #define	MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_OFST 4
+/* Timestamp minor value */
+#define	MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_OFST 4
 
 /* MC_CMD_PTP_OUT_STATUS msgresponse */
 #define	MC_CMD_PTP_OUT_STATUS_LEN 64
+/* Frequency of NIC's hardware clock */
 #define	MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_OFST 0
+/* Number of packets transmitted and timestamped */
 #define	MC_CMD_PTP_OUT_STATUS_STATS_TX_OFST 4
+/* Number of packets received and timestamped */
 #define	MC_CMD_PTP_OUT_STATUS_STATS_RX_OFST 8
+/* Number of packets timestamped by the FPGA */
 #define	MC_CMD_PTP_OUT_STATUS_STATS_TS_OFST 12
+/* Number of packets filter matched */
 #define	MC_CMD_PTP_OUT_STATUS_STATS_FM_OFST 16
+/* Number of packets not filter matched */
 #define	MC_CMD_PTP_OUT_STATUS_STATS_NFM_OFST 20
+/* Number of PPS overflows (noise on input?) */
 #define	MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_OFST 24
+/* Number of PPS bad periods */
 #define	MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_OFST 28
+/* Minimum period of PPS pulse in nanoseconds */
 #define	MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_OFST 32
+/* Maximum period of PPS pulse in nanoseconds */
 #define	MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_OFST 36
+/* Last period of PPS pulse in nanoseconds */
 #define	MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_OFST 40
+/* Mean period of PPS pulse in nanoseconds */
 #define	MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_OFST 44
+/* Minimum offset of PPS pulse in nanoseconds (signed) */
 #define	MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_OFST 48
+/* Maximum offset of PPS pulse in nanoseconds (signed) */
 #define	MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_OFST 52
+/* Last offset of PPS pulse in nanoseconds (signed) */
 #define	MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_OFST 56
+/* Mean offset of PPS pulse in nanoseconds (signed) */
 #define	MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_OFST 60
 
 /* MC_CMD_PTP_OUT_SYNCHRONIZE msgresponse */
 #define	MC_CMD_PTP_OUT_SYNCHRONIZE_LENMIN 20
 #define	MC_CMD_PTP_OUT_SYNCHRONIZE_LENMAX 240
 #define	MC_CMD_PTP_OUT_SYNCHRONIZE_LEN(num) (0+20*(num))
+/* A set of host and NIC times */
 #define	MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_OFST 0
 #define	MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_LEN 20
 #define	MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MINNUM 1
 #define	MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MAXNUM 12
+/* Host time immediately before NIC's hardware clock read */
 #define	MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_OFST 0
+/* Value of seconds timestamp */
 #define	MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_OFST 4
+/* Timestamp major value */
+#define	MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_OFST 4
+/* Value of nanoseconds timestamp */
 #define	MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_OFST 8
+/* Timestamp minor value */
+#define	MC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_OFST 8
+/* Host time immediately after NIC's hardware clock read */
 #define	MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_OFST 12
+/* Number of nanoseconds waited after reading NIC's hardware clock */
 #define	MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_OFST 16
 
 /* MC_CMD_PTP_OUT_MANFTEST_BASIC msgresponse */
 #define	MC_CMD_PTP_OUT_MANFTEST_BASIC_LEN 8
+/* Results of testing */
 #define	MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_OFST 0
-#define	MC_CMD_PTP_MANF_SUCCESS 0x0 /* enum */
-#define	MC_CMD_PTP_MANF_FPGA_LOAD 0x1 /* enum */
-#define	MC_CMD_PTP_MANF_FPGA_VERSION 0x2 /* enum */
-#define	MC_CMD_PTP_MANF_FPGA_REGISTERS 0x3 /* enum */
-#define	MC_CMD_PTP_MANF_OSCILLATOR 0x4 /* enum */
-#define	MC_CMD_PTP_MANF_TIMESTAMPS 0x5 /* enum */
-#define	MC_CMD_PTP_MANF_PACKET_COUNT 0x6 /* enum */
-#define	MC_CMD_PTP_MANF_FILTER_COUNT 0x7 /* enum */
-#define	MC_CMD_PTP_MANF_PACKET_ENOUGH 0x8 /* enum */
-#define	MC_CMD_PTP_MANF_GPIO_TRIGGER 0x9 /* enum */
+/* enum: Successful test */
+#define	MC_CMD_PTP_MANF_SUCCESS 0x0
+/* enum: FPGA load failed */
+#define	MC_CMD_PTP_MANF_FPGA_LOAD 0x1
+/* enum: FPGA version invalid */
+#define	MC_CMD_PTP_MANF_FPGA_VERSION 0x2
+/* enum: FPGA registers incorrect */
+#define	MC_CMD_PTP_MANF_FPGA_REGISTERS 0x3
+/* enum: Oscillator possibly not working? */
+#define	MC_CMD_PTP_MANF_OSCILLATOR 0x4
+/* enum: Timestamps not increasing */
+#define	MC_CMD_PTP_MANF_TIMESTAMPS 0x5
+/* enum: Mismatched packet count */
+#define	MC_CMD_PTP_MANF_PACKET_COUNT 0x6
+/* enum: Mismatched packet count (Siena filter and FPGA) */
+#define	MC_CMD_PTP_MANF_FILTER_COUNT 0x7
+/* enum: Not enough packets to perform timestamp check */
+#define	MC_CMD_PTP_MANF_PACKET_ENOUGH 0x8
+/* enum: Timestamp trigger GPIO not working */
+#define	MC_CMD_PTP_MANF_GPIO_TRIGGER 0x9
+/* enum: Insufficient PPS events to perform checks */
+#define	MC_CMD_PTP_MANF_PPS_ENOUGH 0xa
+/* enum: PPS time event period not sufficiently close to 1s. */
+#define	MC_CMD_PTP_MANF_PPS_PERIOD 0xb
+/* enum: PPS time event nS reading not sufficiently close to zero. */
+#define	MC_CMD_PTP_MANF_PPS_NS 0xc
+/* enum: PTP peripheral registers incorrect */
+#define	MC_CMD_PTP_MANF_REGISTERS 0xd
+/* enum: Failed to read time from PTP peripheral */
+#define	MC_CMD_PTP_MANF_CLOCK_READ 0xe
+/* Presence of external oscillator */
 #define	MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_OFST 4
 
 /* MC_CMD_PTP_OUT_MANFTEST_PACKET msgresponse */
 #define	MC_CMD_PTP_OUT_MANFTEST_PACKET_LEN 12
+/* Results of testing */
 #define	MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_OFST 0
+/* Number of packets received by FPGA */
 #define	MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_OFST 4
+/* Number of packets received by Siena filters */
 #define	MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_OFST 8
 
 /* MC_CMD_PTP_OUT_FPGAREAD msgresponse */
@@ -2671,15 +3884,85 @@
 #define	MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MINNUM 1
 #define	MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MAXNUM 252
 
+/* MC_CMD_PTP_OUT_GET_TIME_FORMAT msgresponse */
+#define	MC_CMD_PTP_OUT_GET_TIME_FORMAT_LEN 4
+/* Time format required/used by for this NIC. Applies to all PTP MCDI
+ * operations that pass times between the host and firmware. If this operation
+ * is not supported (older firmware) a format of seconds and nanoseconds should
+ * be assumed.
+ */
+#define	MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_OFST 0
+/* enum: Times are in seconds and nanoseconds */
+#define	MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_NANOSECONDS 0x0
+/* enum: Major register has units of 16 second per tick, minor 8 ns per tick */
+#define	MC_CMD_PTP_OUT_GET_TIME_FORMAT_16SECONDS_8NANOSECONDS 0x1
+/* enum: Major register has units of seconds, minor 2^-27s per tick */
+#define	MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_27FRACTION 0x2
+
+/* MC_CMD_PTP_OUT_GET_ATTRIBUTES msgresponse */
+#define	MC_CMD_PTP_OUT_GET_ATTRIBUTES_LEN 24
+/* Time format required/used by for this NIC. Applies to all PTP MCDI
+ * operations that pass times between the host and firmware. If this operation
+ * is not supported (older firmware) a format of seconds and nanoseconds should
+ * be assumed.
+ */
+#define	MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_OFST 0
+/* enum: Times are in seconds and nanoseconds */
+#define	MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_NANOSECONDS 0x0
+/* enum: Major register has units of 16 second per tick, minor 8 ns per tick */
+#define	MC_CMD_PTP_OUT_GET_ATTRIBUTES_16SECONDS_8NANOSECONDS 0x1
+/* enum: Major register has units of seconds, minor 2^-27s per tick */
+#define	MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_27FRACTION 0x2
+/* Minimum acceptable value for a corrected synchronization timeset. When
+ * comparing host and NIC clock times, the MC returns a set of samples that
+ * contain the host start and end time, the MC time when the host start was
+ * detected and the time the MC waited between reading the time and detecting
+ * the host end. The corrected sync window is the difference between the host
+ * end and start times minus the time that the MC waited for host end.
+ */
+#define	MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_OFST 4
+/* Various PTP capabilities */
+#define	MC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_OFST 8
+#define	MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_LBN 0
+#define	MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_WIDTH 1
+#define	MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED0_OFST 12
+#define	MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED1_OFST 16
+#define	MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED2_OFST 20
+
+/* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS msgresponse */
+#define	MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_LEN 16
+/* Uncorrected error on transmit timestamps in NIC clock format */
+#define	MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_OFST 0
+/* Uncorrected error on receive timestamps in NIC clock format */
+#define	MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_OFST 4
+/* Uncorrected error on PPS output in NIC clock format */
+#define	MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_OFST 8
+/* Uncorrected error on PPS input in NIC clock format */
+#define	MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_OFST 12
+
+/* MC_CMD_PTP_OUT_MANFTEST_PPS msgresponse */
+#define	MC_CMD_PTP_OUT_MANFTEST_PPS_LEN 4
+/* Results of testing */
+#define	MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_OFST 0
+/*            Enum values, see field(s): */
+/*               MC_CMD_PTP_OUT_MANFTEST_BASIC/TEST_RESULT */
+
+/* MC_CMD_PTP_OUT_SET_SYNC_STATUS msgresponse */
+#define	MC_CMD_PTP_OUT_SET_SYNC_STATUS_LEN 0
+
 
 /***********************************/
-/* MC_CMD_CSR_READ32 
+/* MC_CMD_CSR_READ32
  * Read 32bit words from the indirect memory map.
  */
-#define	MC_CMD_CSR_READ32  0xc
+#define	MC_CMD_CSR_READ32 0xc
+#undef	MC_CMD_0xc_PRIVILEGE_CTG
+
+#define	MC_CMD_0xc_PRIVILEGE_CTG SRIOV_CTG_ADMIN
 
 /* MC_CMD_CSR_READ32_IN msgrequest */
 #define	MC_CMD_CSR_READ32_IN_LEN 12
+/* Address */
 #define	MC_CMD_CSR_READ32_IN_ADDR_OFST 0
 #define	MC_CMD_CSR_READ32_IN_STEP_OFST 4
 #define	MC_CMD_CSR_READ32_IN_NUMWORDS_OFST 8
@@ -2688,6 +3971,7 @@
 #define	MC_CMD_CSR_READ32_OUT_LENMIN 4
 #define	MC_CMD_CSR_READ32_OUT_LENMAX 252
 #define	MC_CMD_CSR_READ32_OUT_LEN(num) (0+4*(num))
+/* The last dword is the status, not a value read */
 #define	MC_CMD_CSR_READ32_OUT_BUFFER_OFST 0
 #define	MC_CMD_CSR_READ32_OUT_BUFFER_LEN 4
 #define	MC_CMD_CSR_READ32_OUT_BUFFER_MINNUM 1
@@ -2695,15 +3979,19 @@
 
 
 /***********************************/
-/* MC_CMD_CSR_WRITE32 
+/* MC_CMD_CSR_WRITE32
  * Write 32bit dwords to the indirect memory map.
  */
-#define	MC_CMD_CSR_WRITE32  0xd
+#define	MC_CMD_CSR_WRITE32 0xd
+#undef	MC_CMD_0xd_PRIVILEGE_CTG
+
+#define	MC_CMD_0xd_PRIVILEGE_CTG SRIOV_CTG_ADMIN
 
 /* MC_CMD_CSR_WRITE32_IN msgrequest */
 #define	MC_CMD_CSR_WRITE32_IN_LENMIN 12
 #define	MC_CMD_CSR_WRITE32_IN_LENMAX 252
 #define	MC_CMD_CSR_WRITE32_IN_LEN(num) (8+4*(num))
+/* Address */
 #define	MC_CMD_CSR_WRITE32_IN_ADDR_OFST 0
 #define	MC_CMD_CSR_WRITE32_IN_STEP_OFST 4
 #define	MC_CMD_CSR_WRITE32_IN_BUFFER_OFST 8
@@ -2717,35 +4005,58 @@
 
 
 /***********************************/
-/* MC_CMD_HP 
- * HP specific commands.
+/* MC_CMD_HP
+ * These commands are used for HP related features. They are grouped under one
+ * MCDI command to avoid creating too many MCDI commands.
  */
-#define	MC_CMD_HP  0x54
+#define	MC_CMD_HP 0x54
+#undef	MC_CMD_0x54_PRIVILEGE_CTG
+
+#define	MC_CMD_0x54_PRIVILEGE_CTG SRIOV_CTG_ADMIN
 
 /* MC_CMD_HP_IN msgrequest */
 #define	MC_CMD_HP_IN_LEN 16
+/* HP OCSD sub-command. When address is not NULL, request activation of OCSD at
+ * the specified address with the specified interval.When address is NULL,
+ * INTERVAL is interpreted as a command: 0: stop OCSD / 1: Report OCSD current
+ * state / 2: (debug) Show temperature reported by one of the supported
+ * sensors.
+ */
 #define	MC_CMD_HP_IN_SUBCMD_OFST 0
-#define	MC_CMD_HP_IN_OCSD_SUBCMD 0x0 /* enum */
-#define	MC_CMD_HP_IN_LAST_SUBCMD 0x0 /* enum */
+/* enum: OCSD (Option Card Sensor Data) sub-command. */
+#define	MC_CMD_HP_IN_OCSD_SUBCMD 0x0
+/* enum: Last known valid HP sub-command. */
+#define	MC_CMD_HP_IN_LAST_SUBCMD 0x0
+/* The address to the array of sensor fields. (Or NULL to use a sub-command.)