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authorAdrian Chadd <adrian@FreeBSD.org>2025-01-11 14:55:28 +0000
committerAdrian Chadd <adrian@FreeBSD.org>2025-01-22 21:46:57 +0000
commit40fc36ff2c1d14f8ea7237e8f9487ab2f25de86b (patch)
tree7b6a27e74848446c6c966a362408aa2e0b3d9900
parent1e734f15c7099408f45d3b1ea433868d0468916f (diff)
rtwn: fix RTL8192EU power-down / power-up hanging
The RTL8192EU NIC (on older USB 2/USB 3 ports, not on newer USB 3 ports, that still needs to be fixed!) will attach, scan, associate fine. However, restarting wpa_supplicant results in the NIC hanging until you disconnect it. It turns out early in the power_on sequence - BUT only after a power_off - the NIC would suddenly stop responding to any USB transfers. It doesn't require the MCU to be available for USB transfers - the hardware itself does that - so something had to be going very sideways. I traced it down to these steps during the power_off sequence. They don't exist in the Linux rtl8xxxu driver, and there are commits earlier in their RTL8192EU bring-up that suggest the author was facing similar power sequencing / re-sequencing issues. This likely won't fix the actual channel programming / power sequencing / deafness issues on later USB-3 ports. There are other commits / fixes in the rtl8xxxu driver related to RTL8192EU bring-up that we don't have. Differential Revision: https://reviews.freebsd.org/D48428 Obtained from: Linux rtl8xxxu driver
-rw-r--r--sys/dev/rtwn/rtl8192e/r92e_init.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/sys/dev/rtwn/rtl8192e/r92e_init.c b/sys/dev/rtwn/rtl8192e/r92e_init.c
index 925221bdabb1..077c64626f8c 100644
--- a/sys/dev/rtwn/rtl8192e/r92e_init.c
+++ b/sys/dev/rtwn/rtl8192e/r92e_init.c
@@ -368,6 +368,7 @@ r92e_power_off(struct rtwn_softc *sc)
return;
}
+#if 0
/* SOP option to disable BG/MB. */
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0xff,
R92C_APS_FSMCO_SOP_RCK, 3);
@@ -377,12 +378,15 @@ r92e_power_off(struct rtwn_softc *sc)
/* Disable small LDO. */
rtwn_setbits_1(sc, R92C_SPS0_CTRL, 0x1, 0);
+#endif
/* Enable WL suspend. */
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, R92C_APS_FSMCO_AFSM_PCIE,
R92C_APS_FSMCO_AFSM_HSUS, 1);
+#if 0
/* Enable SW LPS. */
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
R92C_APS_FSMCO_APFM_RSM, 1);
+#endif
}