libpmc: Update some x86 event definitions.

MFC after:	1 month

90 files changed, 32387 insertions, 26682 deletions

diff --git a/lib/libpmc/pmu-events/arch/x86/amdzen1/branch.json b/lib/libpmc/pmu-events/arch/x86/amdzen1/branch.json
index a9943eeb8d6b..4ceb67a0db21 100644
--- a/lib/libpmc/pmu-events/arch/x86/amdzen1/branch.json
+++ b/lib/libpmc/pmu-events/arch/x86/amdzen1/branch.json
@@ -19,5 +19,10 @@
     "EventName": "bp_de_redirect",
     "EventCode": "0x91",
     "BriefDescription": "Decoder Overrides Existing Branch Prediction (speculative)."
+  },
+  {
+    "EventName": "bp_l1_tlb_fetch_hit",
+    "EventCode": "0x94",
+    "BriefDescription": "The number of instruction fetches that hit in the L1 ITLB."
   }
 ]
diff --git a/lib/libpmc/pmu-events/arch/x86/amdzen1/cache.json b/lib/libpmc/pmu-events/arch/x86/amdzen1/cache.json
index 404d4c569c01..0d46cb82bd52 100644
--- a/lib/libpmc/pmu-events/arch/x86/amdzen1/cache.json
+++ b/lib/libpmc/pmu-events/arch/x86/amdzen1/cache.json
@@ -38,31 +38,31 @@
     "EventName": "ic_fetch_stall.ic_stall_any",
     "EventCode": "0x87",
     "BriefDescription": "Instruction Pipe Stall. IC pipe was stalled during this clock cycle for any reason (nothing valid in pipe ICM1).",
-    "UMask": "0x4"
+    "UMask": "0x04"
   },
   {
     "EventName": "ic_fetch_stall.ic_stall_dq_empty",
     "EventCode": "0x87",
     "BriefDescription": "Instruction Pipe Stall. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to DQ empty.",
-    "UMask": "0x2"
+    "UMask": "0x02"
   },
   {
     "EventName": "ic_fetch_stall.ic_stall_back_pressure",
     "EventCode": "0x87",
     "BriefDescription": "Instruction Pipe Stall. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to back-pressure.",
-    "UMask": "0x1"
+    "UMask": "0x01"
   },
   {
     "EventName": "ic_cache_inval.l2_invalidating_probe",
     "EventCode": "0x8c",
     "BriefDescription": "IC line invalidated due to L2 invalidating probe (external or LS). The number of instruction cache lines invalidated. A non-SMC event is CMC (cross modifying code), either from the other thread of the core or another core.",
-    "UMask": "0x2"
+    "UMask": "0x02"
   },
   {
     "EventName": "ic_cache_inval.fill_invalidated",
     "EventCode": "0x8c",
     "BriefDescription": "IC line invalidated due to overwriting fill response. The number of instruction cache lines invalidated. A non-SMC event is CMC (cross modifying code), either from the other thread of the core or another core.",
-    "UMask": "0x1"
+    "UMask": "0x01"
   },
   {
     "EventName": "bp_tlb_rel",
@@ -97,25 +97,30 @@
     "EventName": "l2_request_g1.change_to_x",
     "EventCode": "0x60",
     "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Request change to writable, check L2 for current state.",
-    "UMask": "0x8"
+    "UMask": "0x08"
   },
   {
     "EventName": "l2_request_g1.prefetch_l2_cmd",
     "EventCode": "0x60",
     "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
-    "UMask": "0x4"
+    "UMask": "0x04"
   },
   {
     "EventName": "l2_request_g1.l2_hw_pf",
     "EventCode": "0x60",
     "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2 pipeline, hit or miss. Types of PF and L2 hit/miss broken out in a separate perfmon event.",
-    "UMask": "0x2"
+    "UMask": "0x02"
   },
   {
     "EventName": "l2_request_g1.group2",
     "EventCode": "0x60",
     "BriefDescription": "Miscellaneous events covered in more detail by l2_request_g2 (PMCx061).",
-    "UMask": "0x1"
+    "UMask": "0x01"
+  },
+  {
+    "EventName": "l2_request_g1.all_no_prefetch",
+    "EventCode": "0x60",
+    "UMask": "0xf9"
   },
   {
     "EventName": "l2_request_g2.group1",
@@ -145,31 +150,31 @@
     "EventName": "l2_request_g2.ic_rd_sized_nc",
     "EventCode": "0x61",
     "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized non-cacheable.",
-    "UMask": "0x8"
+    "UMask": "0x08"
   },
   {
     "EventName": "l2_request_g2.smc_inval",
     "EventCode": "0x61",
     "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Self-modifying code invalidates.",
-    "UMask": "0x4"
+    "UMask": "0x04"
   },
   {
     "EventName": "l2_request_g2.bus_locks_originator",
     "EventCode": "0x61",
     "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Bus locks.",
-    "UMask": "0x2"
+    "UMask": "0x02"
   },
   {
     "EventName": "l2_request_g2.bus_locks_responses",
     "EventCode": "0x61",
     "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Bus lock response.",
-    "UMask": "0x1"
+    "UMask": "0x01"
   },
   {
     "EventName": "l2_latency.l2_cycles_waiting_on_fills",
     "EventCode": "0x62",
     "BriefDescription": "Total cycles spent waiting for L2 fills to complete from L3 or memory, divided by four. Event counts are for both threads. To calculate average latency, the number of fills from both threads must be used.",
-    "UMask": "0x1"
+    "UMask": "0x01"
   },
   {
     "EventName": "l2_wcb_req.wcb_write",
@@ -187,13 +192,13 @@
     "EventName": "l2_wcb_req.zero_byte_store",
     "EventCode": "0x63",
     "BriefDescription": "LS to L2 WCB zero byte store requests. LS (Load/Store unit) to L2 WCB (Write Combining Buffer) zero byte store requests.",
-    "UMask": "0x4"
+    "UMask": "0x04"
   },
   {
     "EventName": "l2_wcb_req.cl_zero",
     "EventCode": "0x63",
     "BriefDescription": "LS to L2 WCB cache line zeroing requests. LS (Load/Store unit) to L2 WCB (Write Combining Buffer) cache line zeroing requests.",
-    "UMask": "0x1"
+    "UMask": "0x01"
   },
   {
     "EventName": "l2_cache_req_stat.ls_rd_blk_cs",
@@ -223,31 +228,67 @@
     "EventName": "l2_cache_req_stat.ls_rd_blk_c",
     "EventCode": "0x64",
     "BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data cache request miss in L2 (all types).",
-    "UMask": "0x8"
+    "UMask": "0x08"
   },
   {
     "EventName": "l2_cache_req_stat.ic_fill_hit_x",
     "EventCode": "0x64",
     "BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache hit modifiable line in L2.",
-    "UMask": "0x4"
+    "UMask": "0x04"
   },
   {
     "EventName": "l2_cache_req_stat.ic_fill_hit_s",
     "EventCode": "0x64",
     "BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache hit clean line in L2.",
-    "UMask": "0x2"
+    "UMask": "0x02"
   },
   {
     "EventName": "l2_cache_req_stat.ic_fill_miss",
     "EventCode": "0x64",
     "BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request miss in L2.",
-    "UMask": "0x1"
+    "UMask": "0x01"
+  },
+  {
+    "EventName": "l2_cache_req_stat.ic_access_in_l2",
+    "EventCode": "0x64",
+    "BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache requests in L2.",
+    "UMask": "0x07"
+  },
+  {
+    "EventName": "l2_cache_req_stat.ic_dc_miss_in_l2",
+    "EventCode": "0x64",
+    "BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request miss in L2 and Data cache request miss in L2 (all types).",
+    "UMask": "0x09"
+  },
+  {
+    "EventName": "l2_cache_req_stat.ic_dc_hit_in_l2",
+    "EventCode": "0x64",
+    "BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request hit in L2 and Data cache request hit in L2 (all types).",
+    "UMask": "0xf6"
   },
   {
     "EventName": "l2_fill_pending.l2_fill_busy",
     "EventCode": "0x6d",
     "BriefDescription": "Cycles with fill pending from L2. Total cycles spent with one or more fill requests in flight from L2.",
-    "UMask": "0x1"
+    "UMask": "0x01"
+  },
+  {
+    "EventName": "l2_pf_hit_l2",
+    "EventCode": "0x70",
+    "BriefDescription": "L2 prefetch hit in L2. Use l2_cache_hits_from_l2_hwpf instead.",
+    "UMask": "0xff"
+  },
+  {
+    "EventName": "l2_pf_miss_l2_hit_l3",
+    "EventCode": "0x71",
+    "BriefDescription": "L2 prefetcher hits in L3. Counts all L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit the L3.",
+    "UMask": "0xff"
+  },
+  {
+    "EventName": "l2_pf_miss_l2_l3",
+    "EventCode": "0x72",
+    "BriefDescription": "L2 prefetcher misses in L3. All L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches.",
+    "UMask": "0xff"
   },
   {
     "EventName": "l3_request_g1.caching_l3_cache_accesses",
diff --git a/lib/libpmc/pmu-events/arch/x86/amdzen1/core.json b/lib/libpmc/pmu-events/arch/x86/amdzen1/core.json
index 7e1aa8273935..4dceeabc4a9f 100644
--- a/lib/libpmc/pmu-events/arch/x86/amdzen1/core.json
+++ b/lib/libpmc/pmu-events/arch/x86/amdzen1/core.json
@@ -61,28 +61,28 @@
   {
     "EventName": "ex_ret_brn_ind_misp",
     "EventCode": "0xca",
-    "BriefDescription": "Retired Indirect Branch Instructions Mispredicted.",
+    "BriefDescription": "Retired Indirect Branch Instructions Mispredicted."
   },
   {
     "EventName": "ex_ret_mmx_fp_instr.sse_instr",
     "EventCode": "0xcb",
     "BriefDescription": "SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX).",
     "PublicDescription": "The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX).",
-    "UMask": "0x4"
+    "UMask": "0x04"
   },
   {
     "EventName": "ex_ret_mmx_fp_instr.mmx_instr",
     "EventCode": "0xcb",
     "BriefDescription": "MMX instructions.",
     "PublicDescription": "The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. MMX instructions.",
-    "UMask": "0x2"
+    "UMask": "0x02"
   },
   {
     "EventName": "ex_ret_mmx_fp_instr.x87_instr",
     "EventCode": "0xcb",
     "BriefDescription": "x87 instructions.",
     "PublicDescription": "The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. x87 instructions.",
-    "UMask": "0x1"
+    "UMask": "0x01"
   },
   {
     "EventName": "ex_ret_cond",
@@ -103,19 +103,19 @@
     "EventName": "ex_tagged_ibs_ops.ibs_count_rollover",
     "EventCode": "0x1cf",
     "BriefDescription": "Tagged IBS Ops. Number of times an op could not be tagged by IBS because of a previous tagged op that has not retired.",
-    "UMask": "0x4"
+    "UMask": "0x04"
   },
   {
     "EventName": "ex_tagged_ibs_ops.ibs_tagged_ops_ret",
     "EventCode": "0x1cf",
     "BriefDescription": "Tagged IBS Ops. Number of Ops tagged by IBS that retired.",
-    "UMask": "0x2"
+    "UMask": "0x02"
   },
   {
     "EventName": "ex_tagged_ibs_ops.ibs_tagged_ops",
     "EventCode": "0x1cf",
     "BriefDescription": "Tagged IBS Ops. Number of Ops tagged by IBS.",
-    "UMask": "0x1"
+    "UMask": "0x01"
   },
   {
     "EventName": "ex_ret_fus_brnch_inst",
diff --git a/lib/libpmc/pmu-events/arch/x86/amdzen1/data-fabric.json b/lib/libpmc/pmu-events/arch/x86/amdzen1/data-fabric.json
index 6f138730df4f..40271df40015 100644
--- a/lib/libpmc/pmu-events/arch/x86/amdzen1/data-fabric.json
+++ b/lib/libpmc/pmu-events/arch/x86/amdzen1/data-fabric.json
@@ -1,2668 +1,98 @@
-[

- {

-  "EventName": "df_ccm_reqa.Node0.anydram",

-  "EventCode": "0x8B",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Any DRAM transaction",

-  "UMask": "0x0F"

- },

- {

-  "EventName": "df_ccm_reqa.Node1.anydram",

-  "EventCode": "0x8B",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Any DRAM transaction",

-  "UMask": "0x2F"

- },

- {

-  "EventName": "df_ccm_reqa.Node2.anydram",

-  "EventCode": "0x8B",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Any DRAM transaction",

-  "UMask": "0x4F"

- },

- {

-  "EventName": "df_ccm_reqa.Node3.anydram",

-  "EventCode": "0x8B",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Any DRAM transaction",

-  "UMask": "0x6F"

- },

- {

-  "EventName": "df_ccm_reqa.Node4.anydram",

-  "EventCode": "0x8B",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Any DRAM transaction",

-  "UMask": "0x8F"

- },

- {

-  "EventName": "df_ccm_reqa.Node5.anydram",

-  "EventCode": "0x8B",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Any DRAM transaction",

-  "UMask": "0xAF"

- },

- {

-  "EventName": "df_ccm_reqa.Node6.anydram",

-  "EventCode": "0x8B",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Any DRAM transaction",

-  "UMask": "0xCF"

- },

- {

-  "EventName": "df_ccm_reqa.Node7.anydram",

-  "EventCode": "0x8B",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Any DRAM transaction",

-  "UMask": "0xEF"

- },

- {

-  "EventName": "df_ccm_reqa.Node0.wrsizedfullzero",

-  "EventCode": "0x8B",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered WrSizedFullZero",

-  "UMask": "0x0E"

- },

- {

-  "EventName": "df_ccm_reqa.Node1.wrsizedfullzero",

-  "EventCode": "0x8B",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered WrSizedFullZero",

-  "UMask": "0x2E"

- },

- {

-  "EventName": "df_ccm_reqa.Node2.wrsizedfullzero",

-  "EventCode": "0x8B",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered WrSizedFullZero",

-  "UMask": "0x4E"

- },

- {

-  "EventName": "df_ccm_reqa.Node3.wrsizedfullzero",

-  "EventCode": "0x8E",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered WrSizedFullZero",

-  "UMask": "0x6E"

- },

- {

-  "EventName": "df_ccm_reqa.Node4.wrsizedfullzero",

-  "EventCode": "0x8B",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered WrSizedFullZero",

-  "UMask": "0x8E"

- },

- {

-  "EventName": "df_ccm_reqa.Node5.wrsizedfullzero",

-  "EventCode": "0x8B",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered WrSizedFullZero",

-  "UMask": "0xAE"

- },

- {

-  "EventName": "df_ccm_reqa.Node6.wrsizedfullzero",

-  "EventCode": "0x8B",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered WrSizedFullZero",

-  "UMask": "0xCE"

- },

- {

-  "EventName": "df_ccm_reqa.Node7.wrsizedfullzero",

-  "EventCode": "0x8B",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered WrSizedFullZero",

-  "UMask": "0xEE"

- },

- {

-  "EventName": "df_ccm_reqa.Node0.wrsizedfullnc",

-  "EventCode": "0x8B",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullnc",

-  "UMask": "0x0D"

- },

- {

-  "EventName": "df_ccm_reqa.Node1.wrsizedfullnc",

-  "EventCode": "0x8A",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullnc",

-  "UMask": "0x2D"

- },

- {

-  "EventName": "df_ccm_reqa.Node2.wrsizedfullnc",

-  "EventCode": "0x8B",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullnc",

-  "UMask": "0x4D"

- },

- {

-  "EventName": "df_ccm_reqa.Node3.wrsizedfullnc",

-  "EventCode": "0x8B",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullnc",

-  "UMask": "0x6D"

- },

- {

-  "EventName": "df_ccm_reqa.Node4.wrsizedfullnc",

-  "EventCode": "0x8B",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullnc",

-  "UMask": "0x8D"

- },

- {

-  "EventName": "df_ccm_reqa.Node5.wrsizedfullnc",

-  "EventCode": "0x8B",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullnc",

-  "UMask": "0xAD"

- },

- {

-  "EventName": "df_ccm_reqa.Node6.wrsizedfullnc",

-  "EventCode": "0x8B",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullnc",

-  "UMask": "0xCD"

- },

- {

-  "EventName": "df_ccm_reqa.Node7.wrsizedfullnc",

-  "EventCode": "0x8B",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullnc",

-  "UMask": "0xED"

- },

- {

-  "EventName": "df_ccm_reqa.Node0.wrsized",

-  "EventCode": "0x8B",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsized",

-  "UMask": "0x0C"

- },

- {

-  "EventName": "df_ccm_reqa.Node1.wrsized",

-  "EventCode": "0x8B",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsized",

-  "UMask": "0x2C"

- },

- {

-  "EventName": "df_ccm_reqa.Node2.wrsized",

-  "EventCode": "0x8B",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsized",

-  "UMask": "0x4C"

- },

- {

-  "EventName": "df_ccm_reqa.Node3.wrsized",

-  "EventCode": "0x8B",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsized",

-  "UMask": "0x6C"

- },

- {

-  "EventName": "df_ccm_reqa.Node4.wrsized",

-  "EventCode": "0x8B",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsized",

-  "UMask": "0x8C"

- },

- {

-  "EventName": "df_ccm_reqa.Node5.wrsized",

-  "EventCode": "0x8B",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsized",

-  "UMask": "0xAC"

- },

- {

-  "EventName": "df_ccm_reqa.Node6.wrsized",

-  "EventCode": "0x8B",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsized",

-  "UMask": "0xCC"

- },

- {

-  "EventName": "df_ccm_reqa.Node7.wrsized",

-  "EventCode": "0x8B",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsized",

-  "UMask": "0xEC"

- },

- {

-  "EventName": "df_ccm_reqa.Node0.wrsizedfullzero",

-  "EventCode": "0x8B",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullzero",

-  "UMask": "0x0B"

- },

- {

-  "EventName": "df_ccm_reqa.Node1.wrsizedfullzero",

-  "EventCode": "0x8B",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullzero",

-  "UMask": "0x2B"

- },

- {

-  "EventName": "df_ccm_reqa.Node2.wrsizedfullzero",

-  "EventCode": "0x8B",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullzero",

-  "UMask": "0x4B"

- },

- {

-  "EventName": "df_ccm_reqa.Node3.wrsizedfullzero",

-  "EventCode": "0x8B",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullzero",

-  "UMask": "0x6B"

- },

- {

-  "EventName": "df_ccm_reqa.Node4.wrsizedfullzero",

-  "EventCode": "0x8B",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullzero",

-  "UMask": "0x8B"

- },

- {

-  "EventName": "df_ccm_reqa.Node5.wrsizedfullzero",

-  "EventCode": "0x8B",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullzero",

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-  "EventName": "df_ccm_reqb.Node5.rdsized",

-  "EventCode": "0x8c",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdsized",

-  "UMask": "0xA1"

- },

- {

-  "EventName": "df_ccm_reqb.Node6.rdsized",

-  "EventCode": "0x8c",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdsized",

-  "UMask": "0xC1"

- },

- {

-  "EventName": "df_ccm_reqb.Node7.rdsized",

-  "EventCode": "0x8c",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdsized",

-  "UMask": "0xE1"

- }, 

- {

-  "EventName": "df_ccm_reqc.apicaccess",

-  "EventCode": "0x08D",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Type C (PIE Requests)APIC access",

-  "UMask": "0x01"

- },

- {

-  "EventName": "df_ccm_reqc.apicucodeaccess",

-  "EventCode": "0x08D",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Type C (PIE Requests)APIC ucode access",

-  "UMask": "0x02"

- },

- {

-  "EventName": "df_ccm_reqc.fasttprwrite",

-  "EventCode": "0x08D",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Type C (PIE Requests)Fast TPR write",

-  "UMask": "0x03"

- },

- {

-  "EventName": "df_ccm_reqc.anybuslockrequest",

-  "EventCode": "0x08D",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Type C (PIE Requests)APIC access Any Bus Lock request",

-  "UMask": "0x04"

- },

- {

-  "EventName": "df_ioms_reqa.Node0.masterabort",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) masterabort",

-  "UMask": "0x0C"

- },

- {

-  "EventName": "df_ioms_reqa.Node1.masterabort",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) masterabort",

-  "UMask": "0x2C"

- },

- {

-  "EventName": "df_ioms_reqa.Node2.masterabort",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) masterabort",

-  "UMask": "0x4C"

- },

- {

-  "EventName": "df_ioms_reqa.Node3.masterabort",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) masterabort",

-  "UMask": "0x6C"

- },

- {

-  "EventName": "df_ioms_reqa.Node4.masterabort",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) masterabort",

-  "UMask": "0x8C"

- },

- {

-  "EventName": "df_ioms_reqa.Node5.masterabort",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) masterabort",

-  "UMask": "0xAC"

- },

- {

-  "EventName": "df_ioms_reqa.Node6.masterabort",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) masterabort",

-  "UMask": "0xCC"

- },

- {

-  "EventName": "df_ioms_reqa.Node7.masterabort",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) masterabort",

-  "UMask": "0xEC"

- },

- {

-  "EventName": "df_ioms_reqa.Node0.ios_resp",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) ios_resp",

-  "UMask": "0x0B"

- },

- {

-  "EventName": "df_ioms_reqa.Node1.ios_resp",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) ios_resp",

-  "UMask": "0x2B"

- },

- {

-  "EventName": "df_ioms_reqa.Node2.ios_resp",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) ios_resp",

-  "UMask": "0x4B"

- },

- {

-  "EventName": "df_ioms_reqa.Node3.ios_resp",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) ios_resp",

-  "UMask": "0x6B"

- },

- {

-  "EventName": "df_ioms_reqa.Node4.ios_resp",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) ios_resp",

-  "UMask": "0x8B"

- },

- {

-  "EventName": "df_ioms_reqa.Node5.ios_resp",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) ios_resp",

-  "UMask": "0xAB"

- },

- {

-  "EventName": "df_ioms_reqa.Node6.ios_resp",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) ios_resp",

-  "UMask": "0xCB"

- },

- {

-  "EventName": "df_ioms_reqa.Node7.ios_resp",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) ios_resp",

-  "UMask": "0xEB"

- },

- {

-  "EventName": "df_ioms_reqa.Node0.flush",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) flush",

-  "UMask": "0x0A"

- },

- {

-  "EventName": "df_ioms_reqa.Node1.flush",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) flush",

-  "UMask": "0x2A"

- },

- {

-  "EventName": "df_ioms_reqa.Node2.flush",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) flush",

-  "UMask": "0x4A"

- },

- {

-  "EventName": "df_ioms_reqa.Node3.flush",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) flush",

-  "UMask": "0x6A"

- },

- {

-  "EventName": "df_ioms_reqa.Node4.flush",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) flush",

-  "UMask": "0x8A"

- },

- {

-  "EventName": "df_ioms_reqa.Node5.flush",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) flush",

-  "UMask": "0xAA"

- },

- {

-  "EventName": "df_ioms_reqa.Node6.flush",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) flush",

-  "UMask": "0xCA"

- },

- {

-  "EventName": "df_ioms_reqa.Node7.flush",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) flush",

-  "UMask": "0xEA"

- },

- {

-  "EventName": "df_ioms_reqa.Node0.fence",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) fence",

-  "UMask": "0x09"

- },

- {

-  "EventName": "df_ioms_reqa.Node1.fence",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) fence",

-  "UMask": "0x29"

- },

- {

-  "EventName": "df_ioms_reqa.Node2.fence",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) fence",

-  "UMask": "0x49"

- },

- {

-  "EventName": "df_ioms_reqa.Node3.fence",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) fence",

-  "UMask": "0x69"

- },

- {

-  "EventName": "df_ioms_reqa.Node4.fence",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) fence",

-  "UMask": "0x89"

- },

- {

-  "EventName": "df_ioms_reqa.Node5.fence",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) fence",

-  "UMask": "0xA9"

- },

- {

-  "EventName": "df_ioms_reqa.Node6.fence",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) fence",

-  "UMask": "0xC9"

- },

- {

-  "EventName": "df_ioms_reqa.Node7.fence",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) fence",

-  "UMask": "0xE9"

- },

- {

-  "EventName": "df_ioms_reqa.Node0.anydramtransaction",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anydramtransaction",

-  "UMask": "0x08"

- },

- {

-  "EventName": "df_ioms_reqa.Node1.anydramtransaction",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anydramtransaction",

-  "UMask": "0x28"

- },

- {

-  "EventName": "df_ioms_reqa.Node2.anydramtransaction",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anydramtransaction",

-  "UMask": "0x48"

- },

- {

-  "EventName": "df_ioms_reqa.Node3.anydramtransaction",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anydramtransaction",

-  "UMask": "0x68"

- },

- {

-  "EventName": "df_ioms_reqa.Node4.anydramtransaction",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anydramtransaction",

-  "UMask": "0x88"

- },

- {

-  "EventName": "df_ioms_reqa.Node5.anydramtransaction",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anydramtransaction",

-  "UMask": "0xA8"

- },

- {

-  "EventName": "df_ioms_reqa.Node6.anydramtransaction",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anydramtransaction",

-  "UMask": "0xC8"

- },

- {

-  "EventName": "df_ioms_reqa.Node7.anydramtransaction",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anydramtransaction",

-  "UMask": "0xE8"

- },

- {

-  "EventName": "df_ioms_reqa.Node0.anyatomic",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anyatomic",

-  "UMask": "0x07"

- },

- {

-  "EventName": "df_ioms_reqa.Node1.anyatomic",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anyatomic",

-  "UMask": "0x27"

- },

- {

-  "EventName": "df_ioms_reqa.Node2.anyatomic",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anyatomic",

-  "UMask": "0x47"

- },

- {

-  "EventName": "df_ioms_reqa.Node3.anyatomic",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anyatomic",

-  "UMask": "0x67"

- },

- {

-  "EventName": "df_ioms_reqa.Node4.anyatomic",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anyatomic",

-  "UMask": "0x87"

- },

- {

-  "EventName": "df_ioms_reqa.Node5.anyatomic",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anyatomic",

-  "UMask": "0xA7"

- },

- {

-  "EventName": "df_ioms_reqa.Node6.anyatomic",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anyatomic",

-  "UMask": "0xC7"

- },

- {

-  "EventName": "df_ioms_reqa.Node7.anyatomic",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anyatomic",

-  "UMask": "0xE7"

- },

- {

-  "EventName": "df_ioms_reqa.Node0.anywrsized=64b",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized=64b",

-  "UMask": "0x06"

- },

- {

-  "EventName": "df_ioms_reqa.Node1.anywrsized=64b",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized=64b",

-  "UMask": "0x26"

- },

- {

-  "EventName": "df_ioms_reqa.Node2.anywrsized=64b",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized=64b",

-  "UMask": "0x46"

- },

- {

-  "EventName": "df_ioms_reqa.Node3.anywrsized=64b",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized=64b",

-  "UMask": "0x66"

- },

- {

-  "EventName": "df_ioms_reqa.Node4.anywrsized=64b",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized=64b",

-  "UMask": "0x86"

- },

- {

-  "EventName": "df_ioms_reqa.Node5.anywrsized=64b",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized=64b",

-  "UMask": "0xA6"

- },

- {

-  "EventName": "df_ioms_reqa.Node6.anywrsized=64b",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized=64b",

-  "UMask": "0xC6"

- },

- {

-  "EventName": "df_ioms_reqa.Node7.anywrsized=64b",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized=64b",

-  "UMask": "0xE6"

- },

- {

-  "EventName": "df_ioms_reqa.Node0.anywrsized>32band<64b",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized>32band<64b",

-  "UMask": "0x05"

- },

- {

-  "EventName": "df_ioms_reqa.Node1.anywrsized>32band<64b",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized>32band<64b",

-  "UMask": "0x25"

- },

- {

-  "EventName": "df_ioms_reqa.Node2.anywrsized>32band<64b",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized>32band<64b",

-  "UMask": "0x45"

- },

- {

-  "EventName": "df_ioms_reqa.Node3.anywrsized>32band<64b",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized>32band<64b",

-  "UMask": "0x65"

- },

- {

-  "EventName": "df_ioms_reqa.Node4.anywrsized>32band<64b",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized>32band<64b",

-  "UMask": "0x85"

- },

- {

-  "EventName": "df_ioms_reqa.Node5.anywrsized>32band<64b",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized>32band<64b",

-  "UMask": "0xA5"

- },

- {

-  "EventName": "df_ioms_reqa.Node6.anywrsized>32band<64b",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized>32band<64b",

-  "UMask": "0xC5"

- },

- {

-  "EventName": "df_ioms_reqa.Node7.anywrsized>32band<64b",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized>32band<64b",

-  "UMask": "0xE5"

- }, 

- {

-  "EventName": "df_ioms_reqa.Node0.anywrsized=32b",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized=32b",

-  "UMask": "0x04"

- },

- {

-  "EventName": "df_ioms_reqa.Node1.anywrsized=32b",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized=32b",

-  "UMask": "0x24"

- },

- {

-  "EventName": "df_ioms_reqa.Node2.anywrsized=32b",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized=32b",

-  "UMask": "0x44"

- },

- {

-  "EventName": "df_ioms_reqa.Node3.anywrsized=32b",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized=32b",

-  "UMask": "0x64"

- },

- {

-  "EventName": "df_ioms_reqa.Node4.anywrsized=32b",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized=32b",

-  "UMask": "0x84"

- },

- {

-  "EventName": "df_ioms_reqa.Node5.anywrsized=32b",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized=32b",

-  "UMask": "0xA4"

- },

- {

-  "EventName": "df_ioms_reqa.Node6.anywrsized=32b",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized=32b",

-  "UMask": "0xC4"

- },

- {

-  "EventName": "df_ioms_reqa.Node7.anywrsized=32b",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized=32b",

-  "UMask": "0xE4"

- }, 

- {

-  "EventName": "df_ioms_reqa.Node0.anywrsized<32b",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized<32b",

-  "UMask": "0x03"

- },

- {

-  "EventName": "df_ioms_reqa.Node1.anywrsized<32b",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized<32b",

-  "UMask": "0x23"

- },

- {

-  "EventName": "df_ioms_reqa.Node2.anywrsized<32b",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized<32b",

-  "UMask": "0x43"

- },

- {

-  "EventName": "df_ioms_reqa.Node3.anywrsized<32b",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized<32b",

-  "UMask": "0x63"

- },

- {

-  "EventName": "df_ioms_reqa.Node4.anywrsized<32b",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized<32b",

-  "UMask": "0x83"

- },

- {

-  "EventName": "df_ioms_reqa.Node5.anywrsized<32b",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized<32b",

-  "UMask": "0xA3"

- },

- {

-  "EventName": "df_ioms_reqa.Node6.anywrsized<32b",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized<32b",

-  "UMask": "0xC3"

- },

- {

-  "EventName": "df_ioms_reqa.Node7.anywrsized<32b",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized<32b",

-  "UMask": "0xE3"

- }, 

- {

-  "EventName": "df_ioms_reqa.Node0.anyrdsized",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anyrdsized",

-  "UMask": "0x02"

- },

- {

-  "EventName": "df_ioms_reqa.Node1.anyrdsized",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anyrdsized",

-  "UMask": "0x22"

- },

- {

-  "EventName": "df_ioms_reqa.Node2.anyrdsized",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anyrdsized",

-  "UMask": "0x42"

- },

- {

-  "EventName": "df_ioms_reqa.Node3.anyrdsized",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anyrdsized",

-  "UMask": "0x62"

- },

- {

-  "EventName": "df_ioms_reqa.Node4.anyrdsized",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anyrdsized",

-  "UMask": "0x82"

- },

- {

-  "EventName": "df_ioms_reqa.Node5.anyrdsized",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anyrdsized",

-  "UMask": "0xA2"

- },

- {

-  "EventName": "df_ioms_reqa.Node6.anyrdsized",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anyrdsized",

-  "UMask": "0xC2"

- },

- {

-  "EventName": "df_ioms_reqa.Node7.anyrdsized",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anyrdsized",

-  "UMask": "0xE2"

- }, 

- {

-  "EventName": "df_ioms_reqa.Node0.largeread",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) largeread",

-  "UMask": "0x01"

- },

- {

-  "EventName": "df_ioms_reqa.Node1.largeread",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) largeread",

-  "UMask": "0x21"

- },

- {

-  "EventName": "df_ioms_reqa.Node2.largeread",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) largeread",

-  "UMask": "0x41"

- },

- {

-  "EventName": "df_ioms_reqa.Node3.largeread",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) largeread",

-  "UMask": "0x61"

- },

- {

-  "EventName": "df_ioms_reqa.Node4.largeread",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) largeread",

-  "UMask": "0x81"

- },

- {

-  "EventName": "df_ioms_reqa.Node5.largeread",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) largeread",

-  "UMask": "0xA1"

- },

- {

-  "EventName": "df_ioms_reqa.Node6.largeread",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) largeread",

-  "UMask": "0xC1"

- },

- {

-  "EventName": "df_ioms_reqa.Node7.largeread",

-  "EventCode": "0x108",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) largeread",

-  "UMask": "0xE1"

- },

- {

-  "EventName": "df_ioms_reqb.Node0.pieiorequest",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Any DRAM transaction",

-  "UMask": "0x0F"

- },

- {

-  "EventName": "df_ioms_reqb.Node1.pieiorequest",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Any DRAM transaction",

-  "UMask": "0x2F"

- },

- {

-  "EventName": "df_ioms_reqb.Node2.pieiorequest",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Any DRAM transaction",

-  "UMask": "0x4F"

- },

- {

-  "EventName": "df_ioms_reqb.Node3.pieiorequest",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Any DRAM transaction",

-  "UMask": "0x6F"

- },

- {

-  "EventName": "df_ioms_reqb.Node4.pieiorequest",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Any DRAM transaction",

-  "UMask": "0x8F"

- },

- {

-  "EventName": "df_ioms_reqb.Node5.pieiorequest",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Any DRAM transaction",

-  "UMask": "0xAF"

- },

- {

-  "EventName": "df_ioms_reqb.Node6.pieiorequest",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Any DRAM transaction",

-  "UMask": "0xCF"

- },

- {

-  "EventName": "df_ioms_reqb.Node7.pieiorequest",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Any DRAM transaction",

-  "UMask": "0xEF"

- },

- {

-  "EventName": "df_ioms_reqb.Node0.piesystemmanagement",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered piesystemmanagement",

-  "UMask": "0x0E"

- },

- {

-  "EventName": "df_ioms_reqb.Node1.piesystemmanagement",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered piesystemmanagement",

-  "UMask": "0x2E"

- },

- {

-  "EventName": "df_ioms_reqb.Node2.piesystemmanagement",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered piesystemmanagement",

-  "UMask": "0x4E"

- },

- {

-  "EventName": "df_ioms_reqb.Node3.piesystemmanagement",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered piesystemmanagement",

-  "UMask": "0x6E"

- },

- {

-  "EventName": "df_ioms_reqb.Node4.piesystemmanagement",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered piesystemmanagement",

-  "UMask": "0x8E"

- },

- {

-  "EventName": "df_ioms_reqb.Node5.piesystemmanagement",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered piesystemmanagement",

-  "UMask": "0xAE"

- },

- {

-  "EventName": "df_ioms_reqb.Node6.piesystemmanagement",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered piesystemmanagement",

-  "UMask": "0xCE"

- },

- {

-  "EventName": "df_ioms_reqb.Node7.piesystemmanagement",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered piesystemmanagement",

-  "UMask": "0xEE"

- },

- {

-  "EventName": "df_ioms_reqb.Node0.pieinterrupt",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered pieinterrupt",

-  "UMask": "0x0D"

- },

- {

-  "EventName": "df_ioms_reqb.Node1.pieinterrupt",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered pieinterrupt",

-  "UMask": "0x2D"

- },

- {

-  "EventName": "df_ioms_reqb.Node2.pieinterrupt",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered pieinterrupt",

-  "UMask": "0x4D"

- },

- {

-  "EventName": "df_ioms_reqb.Node3.pieinterrupt",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered pieinterrupt",

-  "UMask": "0x6D"

- },

- {

-  "EventName": "df_ioms_reqb.Node4.pieinterrupt",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered pieinterrupt",

-  "UMask": "0x8D"

- },

- {

-  "EventName": "df_ioms_reqb.Node5.pieinterrupt",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered pieinterrupt",

-  "UMask": "0xAD"

- },

- {

-  "EventName": "df_ioms_reqb.Node6.pieinterrupt",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered pieinterrupt",

-  "UMask": "0xCD"

- },

- {

-  "EventName": "df_ioms_reqb.Node7.pieinterrupt",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered pieinterrupt",

-  "UMask": "0xED"

- },

- {

-  "EventName": "df_ioms_reqb.Node0.anyiotransaction",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered anyiotransaction",

-  "UMask": "0x0C"

- },

- {

-  "EventName": "df_ioms_reqb.Node1.anyiotransaction",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered anyiotransaction",

-  "UMask": "0x2C"

- },

- {

-  "EventName": "df_ioms_reqb.Node2.anyiotransaction",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered anyiotransaction",

-  "UMask": "0x4C"

- },

- {

-  "EventName": "df_ioms_reqb.Node3.anyiotransaction",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered anyiotransaction",

-  "UMask": "0x6C"

- },

- {

-  "EventName": "df_ioms_reqb.Node4.anyiotransaction",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered anyiotransaction",

-  "UMask": "0x8C"

- },

- {

-  "EventName": "df_ioms_reqb.Node5.anyiotransaction",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered anyiotransaction",

-  "UMask": "0xAC"

- },

- {

-  "EventName": "df_ioms_reqb.Node6.anyiotransaction",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered anyiotransaction",

-  "UMask": "0xCC"

- },

- {

-  "EventName": "df_ioms_reqb.Node7.anyiotransaction",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered anyiotransaction",

-  "UMask": "0xEC"

- },

- {

-  "EventName": "df_ioms_reqb.Node0.ioanyatomic",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanyatomic",

-  "UMask": "0x0B"

- },

- {

-  "EventName": "df_ioms_reqb.Node1.ioanyatomic",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanyatomic",

-  "UMask": "0x2B"

- },

- {

-  "EventName": "df_ioms_reqb.Node2.ioanyatomic",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanyatomic",

-  "UMask": "0x4B"

- },

- {

-  "EventName": "df_ioms_reqb.Node3.ioanyatomic",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanyatomic",

-  "UMask": "0x6B"

- },

- {

-  "EventName": "df_ioms_reqb.Node4.ioanyatomic",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanyatomic",

-  "UMask": "0x8B"

- },

- {

-  "EventName": "df_ioms_reqb.Node5.ioanyatomic",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanyatomic",

-  "UMask": "0xAB"

- },

- {

-  "EventName": "df_ioms_reqb.Node6.ioanyatomic",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanyatomic",

-  "UMask": "0xCB"

- },

- {

-  "EventName": "df_ioms_reqb.Node7.ioanyatomic",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanyatomic",

-  "UMask": "0xEB"

- },

- {

-  "EventName": "df_ioms_reqb.Node0.ioanynon-postedwrsized=64b",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized=64b",

-  "UMask": "0x0A"

- },

- {

-  "EventName": "df_ioms_reqb.Node1.ioanynon-postedwrsized=64b",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized=64b",

-  "UMask": "0x2A"

- },

- {

-  "EventName": "df_ioms_reqb.Node2.ioanynon-postedwrsized=64b",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized=64b",

-  "UMask": "0x4A"

- },

- {

-  "EventName": "df_ioms_reqb.Node3.ioanynon-postedwrsized=64b",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized=64b",

-  "UMask": "0x6A"

- },

- {

-  "EventName": "df_ioms_reqb.Node4.ioanynon-postedwrsized=64b",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized=64b",

-  "UMask": "0x8A"

- },

- {

-  "EventName": "df_ioms_reqb.Node5.ioanynon-postedwrsized=64b",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized=64b",

-  "UMask": "0xAA"

- },

- {

-  "EventName": "df_ioms_reqb.Node6.ioanynon-postedwrsized=64b",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized=64b",

-  "UMask": "0xCA"

- },

- {

-  "EventName": "df_ioms_reqb.Node7.ioanynon-postedwrsized=64b",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized=64b",

-  "UMask": "0xEA"

- },

- {

-  "EventName": "df_ioms_reqb.Node0.ioanynon-postedwrsized>32band<64b",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized>32band<64b",

-  "UMask": "0x09"

- },

- {

-  "EventName": "df_ioms_reqb.Node1.ioanynon-postedwrsized>32band<64b",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized>32band<64b",

-  "UMask": "0x29"

- },

- {

-  "EventName": "df_ioms_reqb.Node2.ioanynon-postedwrsized>32band<64b",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized>32band<64b",

-  "UMask": "0x49"

- },

- {

-  "EventName": "df_ioms_reqb.Node3.ioanynon-postedwrsized>32band<64b",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized>32band<64b",

-  "UMask": "0x69"

- },

- {

-  "EventName": "df_ioms_reqb.Node4.ioanynon-postedwrsized>32band<64b",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized>32band<64b",

-  "UMask": "0x89"

- },

- {

-  "EventName": "df_ioms_reqb.Node5.ioanynon-postedwrsized>32band<64b",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized>32band<64b",

-  "UMask": "0xA9"

- },

- {

-  "EventName": "df_ioms_reqb.Node6.ioanynon-postedwrsized>32band<64b",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized>32band<64b",

-  "UMask": "0xC9"

- },

- {

-  "EventName": "df_ioms_reqb.Node7.ioanynon-postedwrsized>32band<64b",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized>32band<64b",

-  "UMask": "0xE9"

- },

- {

-  "EventName": "df_ioms_reqb.Node0.ioanynon-postedwrsized=32b",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized=32b",

-  "UMask": "0x08"

- },

- {

-  "EventName": "df_ioms_reqb.Node1.ioanynon-postedwrsized=32b",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized=32b",

-  "UMask": "0x28"

- },

- {

-  "EventName": "df_ioms_reqb.Node2.ioanynon-postedwrsized=32b",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized=32b",

-  "UMask": "0x48"

- },

- {

-  "EventName": "df_ioms_reqb.Node3.ioanynon-postedwrsized=32b",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized=32b",

-  "UMask": "0x68"

- },

- {

-  "EventName": "df_ioms_reqb.Node4.ioanynon-postedwrsized=32b",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized=32b",

-  "UMask": "0x88"

- },

- {

-  "EventName": "df_ioms_reqb.Node5.ioanynon-postedwrsized=32b",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized=32b",

-  "UMask": "0xA8"

- },

- {

-  "EventName": "df_ioms_reqb.Node6.ioanynon-postedwrsized=32b",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized=32b",

-  "UMask": "0xC8"

- },

- {

-  "EventName": "df_ioms_reqb.Node7.ioanynon-postedwrsized=32b",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized=32b",

-  "UMask": "0xE8"

- },

- {

-  "EventName": "df_ioms_reqb.Node0.ioanynon-postedwrsized<32b",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized<32b",

-  "UMask": "0x07"

- },

- {

-  "EventName": "df_ioms_reqb.Node1.ioanynon-postedwrsized<32b",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized<32b",

-  "UMask": "0x27"

- },

- {

-  "EventName": "df_ioms_reqb.Node2.ioanynon-postedwrsized<32b",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized<32b",

-  "UMask": "0x47"

- },

- {

-  "EventName": "df_ioms_reqb.Node3.ioanynon-postedwrsized<32b",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized<32b",

-  "UMask": "0x67"

- },

- {

-  "EventName": "df_ioms_reqb.Node4.ioanynon-postedwrsized<32b",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized<32b",

-  "UMask": "0x87"

- },

- {

-  "EventName": "df_ioms_reqb.Node5.ioanynon-postedwrsized<32b",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized<32b",

-  "UMask": "0xA7"

- },

- {

-  "EventName": "df_ioms_reqb.Node6.ioanynon-postedwrsized<32b",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized<32b",

-  "UMask": "0xC7"

- },

- {

-  "EventName": "df_ioms_reqb.Node7.ioanynon-postedwrsized<32b",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized<32b",

-  "UMask": "0xE7"

- },

- {

-  "EventName": "df_ioms_reqb.Node0.ioanypostedwrsized=64b",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized=64b",

-  "UMask": "0x06"

- },

- {

-  "EventName": "df_ioms_reqb.Node1.ioanypostedwrsized=64b",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized=64b",

-  "UMask": "0x26"

- },

- {

-  "EventName": "df_ioms_reqb.Node2.ioanypostedwrsized=64b",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized=64b",

-  "UMask": "0x46"

- },

- {

-  "EventName": "df_ioms_reqb.Node3.ioanypostedwrsized=64b",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized=64b",

-  "UMask": "0x66"

- },

- {

-  "EventName": "df_ioms_reqb.Node4.ioanypostedwrsized=64b",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized=64b",

-  "UMask": "0x86"

- },

- {

-  "EventName": "df_ioms_reqb.Node5.ioanypostedwrsized=64b",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized=64b",

-  "UMask": "0xA6"

- },

- {

-  "EventName": "df_ioms_reqb.Node6.ioanypostedwrsized=64b",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized=64b",

-  "UMask": "0xC6"

- },

- {

-  "EventName": "df_ioms_reqb.Node7.ioanypostedwrsized=64b",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized=64b",

-  "UMask": "0xE6"

- },

- {

-  "EventName": "df_ioms_reqb.Node0.ioanypostedwrsized>32band<64b",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized>32band<64b",

-  "UMask": "0x05"

- },

- {

-  "EventName": "df_ioms_reqb.Node1.ioanypostedwrsized>32band<64b",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized>32band<64b",

-  "UMask": "0x25"

- },

- {

-  "EventName": "df_ioms_reqb.Node2.ioanypostedwrsized>32band<64b",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized>32band<64b",

-  "UMask": "0x45"

- },

- {

-  "EventName": "df_ioms_reqb.Node3.ioanypostedwrsized>32band<64b",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized>32band<64b",

-  "UMask": "0x65"

- },

- {

-  "EventName": "df_ioms_reqb.Node4.ioanypostedwrsized>32band<64b",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized>32band<64b",

-  "UMask": "0x85"

- },

- {

-  "EventName": "df_ioms_reqb.Node5.ioanypostedwrsized>32band<64b",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized>32band<64b",

-  "UMask": "0xA5"

- },

- {

-  "EventName": "df_ioms_reqb.Node6.ioanypostedwrsized>32band<64b",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized>32band<64b",

-  "UMask": "0xC5"

- },

- {

-  "EventName": "df_ioms_reqb.Node7.ioanypostedwrsized>32band<64b",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized>32band<64b",

-  "UMask": "0xE5"

- }, 

- {

-  "EventName": "df_ioms_reqb.Node0.ioanypostedwrsized=32",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized=32",

-  "UMask": "0x04"

- },

- {

-  "EventName": "df_ioms_reqb.Node1.ioanypostedwrsized=32",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized=32",

-  "UMask": "0x24"

- },

- {

-  "EventName": "df_ioms_reqb.Node2.ioanypostedwrsized=32",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized=32",

-  "UMask": "0x44"

- },

- {

-  "EventName": "df_ioms_reqb.Node3.ioanypostedwrsized=32",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized=32",

-  "UMask": "0x64"

- },

- {

-  "EventName": "df_ioms_reqb.Node4.ioanypostedwrsized=32",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized=32",

-  "UMask": "0x84"

- },

- {

-  "EventName": "df_ioms_reqb.Node5.ioanypostedwrsized=32",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized=32",

-  "UMask": "0xA4"

- },

- {

-  "EventName": "df_ioms_reqb.Node6.ioanypostedwrsized=32",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized=32",

-  "UMask": "0xC4"

- },

- {

-  "EventName": "df_ioms_reqb.Node7.ioanypostedwrsized=32",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized=32",

-  "UMask": "0xE4"

- }, 

- {

-  "EventName": "df_ioms_reqb.Node0.ioanypostedwrsized<32",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized<32",

-  "UMask": "0x03"

- },

- {

-  "EventName": "df_ioms_reqb.Node1.ioanypostedwrsized<32",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized<32",

-  "UMask": "0x23"

- },

- {

-  "EventName": "df_ioms_reqb.Node2.ioanypostedwrsized<32",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized<32",

-  "UMask": "0x43"

- },

- {

-  "EventName": "df_ioms_reqb.Node3.ioanypostedwrsized<32",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized<32",

-  "UMask": "0x63"

- },

- {

-  "EventName": "df_ioms_reqb.Node4.ioanypostedwrsized<32",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized<32",

-  "UMask": "0x83"

- },

- {

-  "EventName": "df_ioms_reqb.Node5.ioanypostedwrsized<32",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized<32",

-  "UMask": "0xA3"

- },

- {

-  "EventName": "df_ioms_reqb.Node6.ioanypostedwrsized<32",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized<32",

-  "UMask": "0xC3"

- },

- {

-  "EventName": "df_ioms_reqb.Node7.ioanypostedwrsized<32",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized<32",

-  "UMask": "0xE3"

- }, 

- {

-  "EventName": "df_ioms_reqb.Node0.ioanyrdsized",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanyrdsized",

-  "UMask": "0x02"

- },

- {

-  "EventName": "df_ioms_reqb.Node1.ioanyrdsized",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanyrdsized",

-  "UMask": "0x22"

- },

- {

-  "EventName": "df_ioms_reqb.Node2.ioanyrdsized",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanyrdsized",

-  "UMask": "0x42"

- },

- {

-  "EventName": "df_ioms_reqb.Node3.ioanyrdsized",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanyrdsized",

-  "UMask": "0x62"

- },

- {

-  "EventName": "df_ioms_reqb.Node4.ioanyrdsized",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanyrdsized",

-  "UMask": "0x82"

- },

- {

-  "EventName": "df_ioms_reqb.Node5.ioanyrdsized",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanyrdsized",

-  "UMask": "0xA2"

- },

- {

-  "EventName": "df_ioms_reqb.Node6.ioanyrdsized",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanyrdsized",

-  "UMask": "0xC2"

- },

- {

-  "EventName": "df_ioms_reqb.Node7.ioanyrdsized",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanyrdsized",

-  "UMask": "0xE2"

- }, 

- {

-  "EventName": "df_ioms_reqb.Node0.iolargeread",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered iolargeread",

-  "UMask": "0x01"

- },

- {

-  "EventName": "df_ioms_reqb.Node1.iolargeread",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered iolargeread",

-  "UMask": "0x21"

- },

- {

-  "EventName": "df_ioms_reqb.Node2.iolargeread",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered iolargeread",

-  "UMask": "0x41"

- },

- {

-  "EventName": "df_ioms_reqb.Node3.iolargeread",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered iolargeread",

-  "UMask": "0x61"

- },

- {

-  "EventName": "df_ioms_reqb.Node4.iolargeread",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered iolargeread",

-  "UMask": "0x81"

- },

- {

-  "EventName": "df_ioms_reqb.Node5.iolargeread",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered iolargeread",

-  "UMask": "0xA1"

- },

- {

-  "EventName": "df_ioms_reqb.Node6.iolargeread",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered iolargeread",

-  "UMask": "0xC1"

- },

- {

-  "EventName": "df_ioms_reqb.Node7.iolargeread",

-  "EventCode": "0x109",

-  "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered iolargeread",

-  "UMask": "0xE1"

- } 

-]

-

-

+[
+  {
+    "EventName": "remote_outbound_data_controller_0",
+    "PublicDescription": "Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Controller 0",
+    "EventCode": "0x7c7",
+    "UMask": "0x02",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_outbound_data_controller_1",
+    "PublicDescription": "Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Controller 1",
+    "EventCode": "0x807",
+    "UMask": "0x02",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_outbound_data_controller_2",
+    "PublicDescription": "Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Controller 2",
+    "EventCode": "0x847",
+    "UMask": "0x02",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_outbound_data_controller_3",
+    "PublicDescription": "Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Controller 3",
+    "EventCode": "0x887",
+    "UMask": "0x02",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "dram_channel_data_controller_0",
+    "PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0",
+    "EventCode": "0x07",
+    "UMask": "0x38",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "dram_channel_data_controller_1",
+    "PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0",
+    "EventCode": "0x47",
+    "UMask": "0x38",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "dram_channel_data_controller_2",
+    "PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0",
+    "EventCode": "0x87",
+    "UMask": "0x38",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "dram_channel_data_controller_3",
+    "PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0",
+    "EventCode": "0xc7",
+    "UMask": "0x38",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "dram_channel_data_controller_4",
+    "PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0",
+    "EventCode": "0x107",
+    "UMask": "0x38",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "dram_channel_data_controller_5",
+    "PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0",
+    "EventCode": "0x147",
+    "UMask": "0x38",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "dram_channel_data_controller_6",
+    "PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0",
+    "EventCode": "0x187",
+    "UMask": "0x38",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "dram_channel_data_controller_7",
+    "PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0",
+    "EventCode": "0x1c7",
+    "UMask": "0x38",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  }
+]
diff --git a/lib/libpmc/pmu-events/arch/x86/amdzen1/floating-point.json b/lib/libpmc/pmu-events/arch/x86/amdzen1/floating-point.json
index a35542bd3b36..3995b528ebd6 100644
--- a/lib/libpmc/pmu-events/arch/x86/amdzen1/floating-point.json
+++ b/lib/libpmc/pmu-events/arch/x86/amdzen1/floating-point.json
@@ -39,35 +39,35 @@
     "EventCode": "0x00",
     "BriefDescription": "Total number uOps assigned to all fpu pipes.",
     "PublicDescription": "The number of operations (uOps) and dual-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to all pipes.",
-    "UMask": "0xf"
+    "UMask": "0x0f"
   },
   {
     "EventName": "fpu_pipe_assignment.total3",
     "EventCode": "0x00",
     "BriefDescription": "Total number of fp uOps on pipe 3.",
     "PublicDescription": "The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one-cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 3.",
-    "UMask": "0x8"
+    "UMask": "0x08"
   },
   {
     "EventName": "fpu_pipe_assignment.total2",
     "EventCode": "0x00",
     "BriefDescription": "Total number of fp uOps on pipe 2.",
     "PublicDescription": "The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 2.",
-    "UMask": "0x4"
+    "UMask": "0x04"
   },
   {
     "EventName": "fpu_pipe_assignment.total1",
     "EventCode": "0x00",
     "BriefDescription": "Total number of fp uOps on pipe 1.",
     "PublicDescription": "The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 1.",
-    "UMask": "0x2"
+    "UMask": "0x02"
   },
   {
     "EventName": "fpu_pipe_assignment.total0",
     "EventCode": "0x00",
     "BriefDescription": "Total number of fp uOps  on pipe 0.",
     "PublicDescription": "The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 0.",
-    "UMask": "0x1"
+    "UMask": "0x01"
   },
   {
     "EventName": "fp_sched_empty",
@@ -79,28 +79,28 @@
     "EventCode": "0x02",
     "BriefDescription": "All Ops.",
     "PublicDescription": "The number of x87 floating-point Ops that have retired. The number of events logged per cycle can vary from 0 to 8.",
-    "UMask": "0x7"
+    "UMask": "0x07"
   },
   {
     "EventName": "fp_retx87_fp_ops.div_sqr_r_ops",
     "EventCode": "0x02",
     "BriefDescription": "Divide and square root Ops.",
     "PublicDescription": "The number of x87 floating-point Ops that have retired. The number of events logged per cycle can vary from 0 to 8. Divide and square root Ops.",
-    "UMask": "0x4"
+    "UMask": "0x04"
   },
   {
     "EventName": "fp_retx87_fp_ops.mul_ops",
     "EventCode": "0x02",
     "BriefDescription": "Multiply Ops.",
     "PublicDescription": "The number of x87 floating-point Ops that have retired. The number of events logged per cycle can vary from 0 to 8. Multiply Ops.",
-    "UMask": "0x2"
+    "UMask": "0x02"
   },
   {
     "EventName": "fp_retx87_fp_ops.add_sub_ops",
     "EventCode": "0x02",
     "BriefDescription": "Add/subtract Ops.",
     "PublicDescription": "The number of x87 floating-point Ops that have retired. The number of events logged per cycle can vary from 0 to 8. Add/subtract Ops.",
-    "UMask": "0x1"
+    "UMask": "0x01"
   },
   {
     "EventName": "fp_ret_sse_avx_ops.all",
@@ -142,83 +142,83 @@
     "EventCode": "0x03",
     "BriefDescription": "Single precision multiply-add FLOPS. Multiply-add counts as 2 FLOPS.",
     "PublicDescription": "This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Single precision multiply-add FLOPS. Multiply-add counts as 2 FLOPS.",
-    "UMask": "0x8"
+    "UMask": "0x08"
   },
   {
     "EventName": "fp_ret_sse_avx_ops.sp_div_flops",
     "EventCode": "0x03",
     "BriefDescription": "Single-precision divide/square root FLOPS.",
     "PublicDescription": "This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Single-precision divide/square root FLOPS.",
-    "UMask": "0x4"
+    "UMask": "0x04"
   },
   {
     "EventName": "fp_ret_sse_avx_ops.sp_mult_flops",
     "EventCode": "0x03",
     "BriefDescription": "Single-precision multiply FLOPS.",
     "PublicDescription": "This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Single-precision multiply FLOPS.",
-    "UMask": "0x2"
+    "UMask": "0x02"
   },
   {
     "EventName": "fp_ret_sse_avx_ops.sp_add_sub_flops",
     "EventCode": "0x03",
     "BriefDescription": "Single-precision add/subtract FLOPS.",
     "PublicDescription": "This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15. Single-precision add/subtract FLOPS.",
-    "UMask": "0x1"
+    "UMask": "0x01"
   },
   {
     "EventName": "fp_num_mov_elim_scal_op.optimized",
     "EventCode": "0x04",
     "BriefDescription": "Number of Scalar Ops optimized.",
     "PublicDescription": "This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes. Number of Scalar Ops optimized.",
-    "UMask": "0x8"
+    "UMask": "0x08"
   },
   {
     "EventName": "fp_num_mov_elim_scal_op.opt_potential",
     "EventCode": "0x04",
     "BriefDescription": "Number of Ops that are candidates for optimization (have Z-bit either set or pass).",
     "PublicDescription": "This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes. Number of Ops that are candidates for optimization (have Z-bit either set or pass).",
-    "UMask": "0x4"
+    "UMask": "0x04"
   },
   {
     "EventName": "fp_num_mov_elim_scal_op.sse_mov_ops_elim",
     "EventCode": "0x04",
     "BriefDescription": "Number of SSE Move Ops eliminated.",
     "PublicDescription": "This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes. Number of SSE Move Ops eliminated.",
-    "UMask": "0x2"
+    "UMask": "0x02"
   },
   {
     "EventName": "fp_num_mov_elim_scal_op.sse_mov_ops",
     "EventCode": "0x04",
     "BriefDescription": "Number of SSE Move Ops.",
     "PublicDescription": "This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes. Number of SSE Move Ops.",
-    "UMask": "0x1"
+    "UMask": "0x01"
   },
   {
     "EventName": "fp_retired_ser_ops.x87_ctrl_ret",
     "EventCode": "0x05",
     "BriefDescription": "x87 control word mispredict traps due to mispredictions in RC or PC, or changes in mask bits.",
     "PublicDescription": "The number of serializing Ops retired. x87 control word mispredict traps due to mispredictions in RC or PC, or changes in mask bits.",
-    "UMask": "0x8"
+    "UMask": "0x08"
   },
   {
     "EventName": "fp_retired_ser_ops.x87_bot_ret",
     "EventCode": "0x05",
     "BriefDescription": "x87 bottom-executing uOps retired.",
     "PublicDescription": "The number of serializing Ops retired. x87 bottom-executing uOps retired.",
-    "UMask": "0x4"
+    "UMask": "0x04"
   },
   {
     "EventName": "fp_retired_ser_ops.sse_ctrl_ret",
     "EventCode": "0x05",
     "BriefDescription": "SSE control word mispredict traps due to mispredictions in RC, FTZ or DAZ, or changes in mask bits.",
     "PublicDescription": "The number of serializing Ops retired. SSE control word mispredict traps due to mispredictions in RC, FTZ or DAZ, or changes in mask bits.",
-    "UMask": "0x2"
+    "UMask": "0x02"
   },
   {
     "EventName": "fp_retired_ser_ops.sse_bot_ret",
     "EventCode": "0x05",
     "BriefDescription": "SSE bottom-executing uOps retired.",
     "PublicDescription": "The number of serializing Ops retired. SSE bottom-executing uOps retired.",
-    "UMask": "0x1"
+    "UMask": "0x01"
   }
 ]
diff --git a/lib/libpmc/pmu-events/arch/x86/amdzen1/l3cache.json b/lib/libpmc/pmu-events/arch/x86/amdzen1/l3cache.json
deleted file mode 100644
index f7e2dcd2194f..000000000000
--- a/lib/libpmc/pmu-events/arch/x86/amdzen1/l3cache.json
+++ /dev/null
@@ -1,5411 +0,0 @@
-[

- {

-  "EventName": "l3_request_g1.t0.s0.wrsizednc",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses ",

-  "L3ThreadMask": "0x01",

-  "L3SliceMask": "0x01",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3_request_g1.t1.s0.wrsizednc",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x02",

-  "L3SliceMask": "0x01",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3_request_g1.t2.s0.wrsizednc",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x04",

-  "L3SliceMask": "0x01",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3_request_g1.t3.s0.wrsizednc",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x08",

-  "L3SliceMask": "0x01",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3_request_g1.t4.s0.wrsizednc",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x10",

-  "L3SliceMask": "0x01",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3_request_g1.t5.s0.wrsizednc",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x20",

-  "L3SliceMask": "0x01",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3_request_g1.t6.s0.wrsizednc",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x40",

-  "L3SliceMask": "0x01",

-  "UMask": "0x02"

- },

-

- {

-  "EventName": "l3_request_g1.t7.s0.wrsizednc",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x80",

-  "L3SliceMask": "0x01",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3_request_g1.t0.s1.wrsizednc",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x01",

-  "L3SliceMask": "0x02",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3_request_g1.t1.s1.wrsizednc",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x02",

-  "L3SliceMask": "0x02",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3_request_g1.t2.s1.wrsizednc",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x04",

-  "L3SliceMask": "0x02",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3_request_g1.t3.s1.wrsizednc",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x08",

-  "L3SliceMask": "0x02",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3_request_g1.t4.s1.wrsizednc",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x10",

-  "L3SliceMask": "0x02",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3_request_g1.t5.s1.wrsizednc",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x20",

-  "L3SliceMask": "0x02",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3_request_g1.t6.s1.wrsizednc",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x40",

-  "L3SliceMask": "0x02",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3_request_g1.t7.s1.wrsizednc",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x80",

-  "L3SliceMask": "0x02",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3_request_g1.t0.s2.wrsizednc",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x01",

-  "L3SliceMask": "0x04",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3_request_g1.t1.s2.wrsizednc",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x02",

-  "L3SliceMask": "0x04",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3_request_g1.t2.s2.wrsizednc",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x04",

-  "L3SliceMask": "0x04",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3_request_g1.t3.s2.wrsizednc",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x08",

-  "L3SliceMask": "0x04",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3_request_g1.t4.s2.wrsizednc",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x10",

-  "L3SliceMask": "0x04",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3_request_g1.t5.s2.wrsizednc",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x20",

-  "L3SliceMask": "0x04",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3_request_g1.t6.s2.wrsizednc",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x40",

-  "L3SliceMask": "0x04",

-  "UMask": "0x02"

- },

-

- {

-  "EventName": "l3_request_g1.t7.s2.wrsizednc",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x80",

-  "L3SliceMask": "0x04",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3_request_g1.t0.s3.wrsizednc",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x01",

-  "L3SliceMask": "0x08",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3_request_g1.t1.s3.wrsizednc",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x02",

-  "L3SliceMask": "0x08",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3_request_g1.t2.s3.wrsizednc",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x04",

-  "L3SliceMask": "0x08",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3_request_g1.t3.s3.wrsizednc",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x08",

-  "L3SliceMask": "0x08",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3_request_g1.t4.s3.wrsizednc",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x10",

-  "L3SliceMask": "0x08",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3_request_g1.t5.s3.wrsizednc",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x20",

-  "L3SliceMask": "0x08",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3_request_g1.t6.s3.wrsizednc",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x40",

-  "L3SliceMask": "0x08",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3_request_g1.t7.s3.wrsizednc",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x80",

-  "L3SliceMask": "0x08",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3_request_g1.t0.s0.wrsized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x01",

-  "L3SliceMask": "0x01",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3_request_g1.t1.s0.wrsized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x02",

-  "L3SliceMask": "0x01",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3_request_g1.t2.s0.wrsized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x04",

-  "L3SliceMask": "0x01",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3_request_g1.t3.s0.wrsized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x08",

-  "L3SliceMask": "0x01",

-  "UMask": "0x04"

- },

-   {

-  "EventName": "l3_request_g1.t4.s0.wrsized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x10",

-  "L3SliceMask": "0x01",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3_request_g1.t5.s0.wrsized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x20",

-  "L3SliceMask": "0x01",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3_request_g1.t6.s0.wrsized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x40",

-  "L3SliceMask": "0x01",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3_request_g1.t7.s0.wrsized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x80",

-  "L3SliceMask": "0x01",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3_request_g1.t0.s1.wrsized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x01",

-  "L3SliceMask": "0x02",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3_request_g1.t1.s1.wrsized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x02",

-  "L3SliceMask": "0x02",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3_request_g1.t2.s1.wrsized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x04",

-  "L3SliceMask": "0x02",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3_request_g1.t3.s1.wrsized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x08",

-  "L3SliceMask": "0x02",

-  "UMask": "0x04"

- },

-   {

-  "EventName": "l3_request_g1.t4.s1.wrsized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x10",

-  "L3SliceMask": "0x02",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3_request_g1.t5.s1.wrsized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x20",

-  "L3SliceMask": "0x02",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3_request_g1.t6.s1.wrsized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x40",

-  "L3SliceMask": "0x02",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3_request_g1.t7.s1.wrsized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x80",

-  "L3SliceMask": "0x02",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3_request_g1.t0.s2.wrsized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x01",

-  "L3SliceMask": "0x04",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3_request_g1.t1.s2.wrsized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x02",

-  "L3SliceMask": "0x04",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3_request_g1.t2.s2.wrsized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x04",

-  "L3SliceMask": "0x04",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3_request_g1.t3.s2.wrsized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x08",

-  "L3SliceMask": "0x04",

-  "UMask": "0x04"

- },

-   {

-  "EventName": "l3_request_g1.t4.s2.wrsized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x10",

-  "L3SliceMask": "0x04",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3_request_g1.t5.s2.wrsized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x20",

-  "L3SliceMask": "0x04",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3_request_g1.t6.s2.wrsized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x40",

-  "L3SliceMask": "0x04",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3_request_g1.t7.s2.wrsized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x80",

-  "L3SliceMask": "0x04",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3_request_g1.t0.s3.wrsized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x01",

-  "L3SliceMask": "0x08",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3_request_g1.t1.s3.wrsized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x02",

-  "L3SliceMask": "0x08",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3_request_g1.t2.s3.wrsized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x04",

-  "L3SliceMask": "0x08",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3_request_g1.t3.s3.wrsized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x08",

-  "L3SliceMask": "0x08",

-  "UMask": "0x04"

- },

-   {

-  "EventName": "l3_request_g1.t4.s3.wrsized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x10",

-  "L3SliceMask": "0x08",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3_request_g1.t5.s3.wrsized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x20",

-  "L3SliceMask": "0x08",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3_request_g1.t6.s3.wrsized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x40",

-  "L3SliceMask": "0x08",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3_request_g1.t7.s3.wrsized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x80",

-  "L3SliceMask": "0x08",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3_request_g1.t0.s0.RdSizedNC",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x01",

-  "L3SliceMask": "0x01",

-  "UMask": "0x20"

- },

- {

-  "EventName": "l3_request_g1.t1.s0.RdSizedNC",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x02",

-  "L3SliceMask": "0x01",

-  "UMask": "0x20"

- },

- {

-  "EventName": "l3_request_g1.t2.s0.RdSizedNC",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x04",

-  "L3SliceMask": "0x01",

-  "UMask": "0x20"

- },

- {

-  "EventName": "l3_request_g1.t3.s0.RdSizedNC",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x08",

-  "L3SliceMask": "0x01",

-  "UMask": "0x20"

- },

- {

-  "EventName": "l3_request_g1.t4.s0.RdSizedNC",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x10",

-  "L3SliceMask": "0x01",

-  "UMask": "0x20"

- },

- {

-  "EventName": "l3_request_g1.t5.s0.RdSizedNC",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x20",

-  "L3SliceMask": "0x01",

-  "UMask": "0x20"

- },

- {

-  "EventName": "l3_request_g1.t6.s0.RdSizedNC",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x40",

-  "L3SliceMask": "0x01",

-  "UMask": "0x20"

- },

- {

-  "EventName": "l3_request_g1.t7.s0.RdSizedNC",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x80",

-  "L3SliceMask": "0x01",

-  "UMask": "0x20"

- },

- {

-  "EventName": "l3_request_g1.t0.s1.RdSizedNC",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x01",

-  "L3SliceMask": "0x02",

-  "UMask": "0x20"

- },

- {

-  "EventName": "l3_request_g1.t1.s1.RdSizedNC",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x02",

-  "L3SliceMask": "0x02",

-  "UMask": "0x20"

- },

- {

-  "EventName": "l3_request_g1.t2.s1.RdSizedNC",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x04",

-  "L3SliceMask": "0x02",

-  "UMask": "0x20"

- },

- {

-  "EventName": "l3_request_g1.t3.s1.RdSizedNC",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x08",

-  "L3SliceMask": "0x02",

-  "UMask": "0x20"

- },

- {

-  "EventName": "l3_request_g1.t4.s1.RdSizedNC",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x10",

-  "L3SliceMask": "0x02",

-  "UMask": "0x20"

- },

- {

-  "EventName": "l3_request_g1.t5.s1.RdSizedNC",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x20",

-  "L3SliceMask": "0x02",

-  "UMask": "0x20"

- },

- {

-  "EventName": "l3_request_g1.t6.s1.RdSizedNC",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x40",

-  "L3SliceMask": "0x02",

-  "UMask": "0x20"

- },

- {

-  "EventName": "l3_request_g1.t7.s1.RdSizedNC",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x80",

-  "L3SliceMask": "0x02",

-  "UMask": "0x20"

- },

-

-{

-  "EventName": "l3_request_g1.t0.s2.RdSizedNC",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x01",

-  "L3SliceMask": "0x04",

-  "UMask": "0x20"

- },

- {

-  "EventName": "l3_request_g1.t1.s2.RdSizedNC",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x02",

-  "L3SliceMask": "0x04",

-  "UMask": "0x20"

- },

- {

-  "EventName": "l3_request_g1.t2.s2.RdSizedNC",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x04",

-  "L3SliceMask": "0x04",

-  "UMask": "0x20"

- },

- {

-  "EventName": "l3_request_g1.t3.s2.RdSizedNC",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x08",

-  "L3SliceMask": "0x04",

-  "UMask": "0x20"

- },

- {

-  "EventName": "l3_request_g1.t4.s2.RdSizedNC",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x10",

-  "L3SliceMask": "0x04",

-  "UMask": "0x20"

- },

- {

-  "EventName": "l3_request_g1.t5.s2.RdSizedNC",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x20",

-  "L3SliceMask": "0x04",

-  "UMask": "0x20"

- },

- {

-  "EventName": "l3_request_g1.t6.s2.RdSizedNC",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x40",

-  "L3SliceMask": "0x04",

-  "UMask": "0x20"

- },

- {

-  "EventName": "l3_request_g1.t7.s2.RdSizedNC",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x80",

-  "L3SliceMask": "0x04",

-  "UMask": "0x20"

- },

-

-{

-  "EventName": "l3_request_g1.t0.s3.RdSizedNC",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x01",

-  "L3SliceMask": "0x08",

-  "UMask": "0x20"

- },

- {

-  "EventName": "l3_request_g1.t1.s3.RdSizedNC",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x02",

-  "L3SliceMask": "0x08",

-  "UMask": "0x20"

- },

- {

-  "EventName": "l3_request_g1.t2.s3.RdSizedNC",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x04",

-  "L3SliceMask": "0x08",

-  "UMask": "0x20"

- },

- {

-  "EventName": "l3_request_g1.t3.s3.RdSizedNC",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x08",

-  "L3SliceMask": "0x08",

-  "UMask": "0x20"

- },

- {

-  "EventName": "l3_request_g1.t4.s3.RdSizedNC",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x10",

-  "L3SliceMask": "0x08",

-  "UMask": "0x20"

- },

- {

-  "EventName": "l3_request_g1.t5.s3.RdSizedNC",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x20",

-  "L3SliceMask": "0x08",

-  "UMask": "0x20"

- },

- {

-  "EventName": "l3_request_g1.t6.s3.RdSizedNC",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x40",

-  "L3SliceMask": "0x08",

-  "UMask": "0x20"

- },

- {

-  "EventName": "l3_request_g1.t7.s3.RdSizedNC",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x80",

-  "L3SliceMask": "0x08",

-  "UMask": "0x20"

- },

- {

-  "EventName": "l3_request_g1.t0.s0.RdSized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x01",

-  "L3SliceMask": "0x01",

-  "UMask": "0x40"

- },

- {

-  "EventName": "l3_request_g1.t1.s0.RdSized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x01",

-  "L3SliceMask": "0x02",

-  "UMask": "0x40"

- },

- {

-  "EventName": "l3_request_g1.t2.s0.RdSized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x04",

-  "L3SliceMask": "0x01",

-  "UMask": "0x40"

- },

- {

-  "EventName": "l3_request_g1.t3.s0.RdSized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x08",

-  "L3SliceMask": "0x01",

-  "UMask": "0x40"

- },

- {

-  "EventName": "l3_request_g1.t4.s0.RdSized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x10",

-  "L3SliceMask": "0x01",

-  "UMask": "0x40"

- },

- {  

-  "EventName": "l3_request_g1.t5.s0.RdSized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x20",

-  "L3SliceMask": "0x01",

-  "UMask": "0x40"

- },

- {

-  "EventName": "l3_request_g1.t6.s0.RdSized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x40",

-  "L3SliceMask": "0x01",

-  "UMask": "0x40"

- },

- {

-  "EventName": "l3_request_g1.t7.s0.RdSized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x80",

-  "L3SliceMask": "0x01",

-  "UMask": "0x40"

- },

- {

-  "EventName": "l3_request_g1.t0.s1.RdSized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x01",

-  "L3SliceMask": "0x02",

-  "UMask": "0x40"

- },

- {

-  "EventName": "l3_request_g1.t1.s1.RdSized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x01",

-  "L3SliceMask": "0x02",

-  "UMask": "0x40"

- },

- {

-  "EventName": "l3_request_g1.t2.s1.RdSized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x04",

-  "L3SliceMask": "0x02",

-  "UMask": "0x40"

- },

- {

-  "EventName": "l3_request_g1.t3.s1.RdSized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x08",

-  "L3SliceMask": "0x02",

-  "UMask": "0x40"

- },

- {

-  "EventName": "l3_request_g1.t4.s1.RdSized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x10",

-  "L3SliceMask": "0x02",

-  "UMask": "0x40"

- },

- {  

-  "EventName": "l3_request_g1.t5.s1.RdSized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x20",

-  "L3SliceMask": "0x02",

-  "UMask": "0x40"

- },

- {

-  "EventName": "l3_request_g1.t6.s1.RdSized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x40",

-  "L3SliceMask": "0x02",

-  "UMask": "0x40"

- },

- {

-  "EventName": "l3_request_g1.t7.s1.RdSized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x80",

-  "L3SliceMask": "0x02",

-  "UMask": "0x40"

- },

-

-{

-  "EventName": "l3_request_g1.t0.s2.RdSized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x01",

-  "L3SliceMask": "0x04",

-  "UMask": "0x40"

- },

- {

-  "EventName": "l3_request_g1.t1.s2.RdSized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x01",

-  "L3SliceMask": "0x04",

-  "UMask": "0x40"

- },

- {

-  "EventName": "l3_request_g1.t2.s2.RdSized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x04",

-  "L3SliceMask": "0x04",

-  "UMask": "0x40"

- },

- {

-  "EventName": "l3_request_g1.t3.s2.RdSized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x08",

-  "L3SliceMask": "0x04",

-  "UMask": "0x40"

- },

- {

-  "EventName": "l3_request_g1.t4.s2.RdSized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x10",

-  "L3SliceMask": "0x04",

-  "UMask": "0x40"

- },

- {  

-  "EventName": "l3_request_g1.t5.s2.RdSized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x20",

-  "L3SliceMask": "0x04",

-  "UMask": "0x40"

- },

- {

-  "EventName": "l3_request_g1.t6.s2.RdSized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x40",

-  "L3SliceMask": "0x04",

-  "UMask": "0x40"

- },

- {

-  "EventName": "l3_request_g1.t7.s2.RdSized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x80",

-  "L3SliceMask": "0x04",

-  "UMask": "0x40"

- },

-

-{

-  "EventName": "l3_request_g1.t0.s3.RdSized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x01",

-  "L3SliceMask": "0x08",

-  "UMask": "0x40"

- },

- {

-  "EventName": "l3_request_g1.t1.s3.RdSized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x02",

-  "L3SliceMask": "0x08",

-  "UMask": "0x40"

- },

- {

-  "EventName": "l3_request_g1.t2.s3.RdSized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x04",

-  "L3SliceMask": "0x08",

-  "UMask": "0x40"

- },

- {

-  "EventName": "l3_request_g1.t3.s3.RdSized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x08",

-  "L3SliceMask": "0x08",

-  "UMask": "0x40"

- },

- {

-  "EventName": "l3_request_g1.t4.s3.RdSized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x10",

-  "L3SliceMask": "0x08",

-  "UMask": "0x40"

- },

- {  

-  "EventName": "l3_request_g1.t5.s3.RdSized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x20",

-  "L3SliceMask": "0x08",

-  "UMask": "0x40"

- },

- {

-  "EventName": "l3_request_g1.t6.s3.RdSized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x40",

-  "L3SliceMask": "0x08",

-  "UMask": "0x40"

- },

- {

-  "EventName": "l3_request_g1.t7.s3.RdSized",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x80",

-  "L3SliceMask": "0x08",

-  "UMask": "0x40"

- },

- {

-  "EventName": "l3_request_g1.t0.s0.caching",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x01",

-  "L3SliceMask": "0x01",

-  "UMask": "0x80"

- },

- {

-  "EventName": "l3_request_g1.t1.s0.caching",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x02",

-  "L3SliceMask": "0x01",

-  "UMask": "0x80"

- },

-{

-  "EventName": "l3_request_g1.t2.s0.caching",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x04",

-  "L3SliceMask": "0x01",

-  "UMask": "0x80"

- },

-{

-  "EventName": "l3_request_g1.t3.s0.caching",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x08",

-  "L3SliceMask": "0x01",

-  "UMask": "0x80"

- },

-{

-  "EventName": "l3_request_g1.t4.s0.caching",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x10",

-  "L3SliceMask": "0x01",

-  "UMask": "0x80"

- },

-{

-  "EventName": "l3_request_g1.t5.s0.caching",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x20",

-  "L3SliceMask": "0x01",

-  "UMask": "0x80"

- },

-{

-  "EventName": "l3_request_g1.t6.s0.caching",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x40",

-  "L3SliceMask": "0x01",

-  "UMask": "0x80"

- },

-{

-  "EventName": "l3_request_g1.t7.s0.caching",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x80",

-  "L3SliceMask": "0x01",

-  "UMask": "0x80"

- },

- {

-  "EventName": "l3_request_g1.t0.s1.caching",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x01",

-  "L3SliceMask": "0x02",

-  "UMask": "0x80"

- },

- {

-  "EventName": "l3_request_g1.t1.s1.caching",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x02",

-  "L3SliceMask": "0x02",

-  "UMask": "0x80"

- },

-{

-  "EventName": "l3_request_g1.t2.s1.caching",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x04",

-  "L3SliceMask": "0x02",

-  "UMask": "0x80"

- },

-{

-  "EventName": "l3_request_g1.t3.s1.caching",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x08",

-  "L3SliceMask": "0x02",

-  "UMask": "0x80"

- },

-{

-  "EventName": "l3_request_g1.t4.s1.caching",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x10",

-  "L3SliceMask": "0x02",

-  "UMask": "0x80"

- },

-{

-  "EventName": "l3_request_g1.t5.s1.caching",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x20",

-  "L3SliceMask": "0x02",

-  "UMask": "0x80"

- },

-{

-  "EventName": "l3_request_g1.t6.s1.caching",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x40",

-  "L3SliceMask": "0x02",

-  "UMask": "0x80"

- },

-{

-  "EventName": "l3_request_g1.t7.s1.caching",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x80",

-  "L3SliceMask": "0x02",

-  "UMask": "0x80"

- },

-

-{

-  "EventName": "l3_request_g1.t0.s2.caching",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x01",

-  "L3SliceMask": "0x04",

-  "UMask": "0x80"

- },

- {

-  "EventName": "l3_request_g1.t1.s2.caching",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x02",

-  "L3SliceMask": "0x04",

-  "UMask": "0x80"

- },

-{

-  "EventName": "l3_request_g1.t2.s2.caching",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x04",

-  "L3SliceMask": "0x04",

-  "UMask": "0x80"

- },

-{

-  "EventName": "l3_request_g1.t3.s2.caching",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x08",

-  "L3SliceMask": "0x04",

-  "UMask": "0x80"

- },

-{

-  "EventName": "l3_request_g1.t4.s2.caching",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x10",

-  "L3SliceMask": "0x04",

-  "UMask": "0x80"

- },

-{

-  "EventName": "l3_request_g1.t5.s2.caching",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x20",

-  "L3SliceMask": "0x04",

-  "UMask": "0x80"

- },

-{

-  "EventName": "l3_request_g1.t6.s2.caching",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x40",

-  "L3SliceMask": "0x04",

-  "UMask": "0x80"

- },

-{

-  "EventName": "l3_request_g1.t7.s2.caching",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x80",

-  "L3SliceMask": "0x04",

-  "UMask": "0x80"

- },

-

-{

-  "EventName": "l3_request_g1.t0.s3.caching",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x01",

-  "L3SliceMask": "0x08",

-  "UMask": "0x80"

- },

- {

-  "EventName": "l3_request_g1.t1.s3.caching",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x02",

-  "L3SliceMask": "0x08",

-  "UMask": "0x80"

- },

-{

-  "EventName": "l3_request_g1.t2.s3.caching",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x04",

-  "L3SliceMask": "0x08",

-  "UMask": "0x80"

- },

-{

-  "EventName": "l3_request_g1.t3.s3.caching",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x08",

-  "L3SliceMask": "0x08",

-  "UMask": "0x80"

- },

-{

-  "EventName": "l3_request_g1.t4.s3.caching",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x10",

-  "L3SliceMask": "0x08",

-  "UMask": "0x80"

- },

-{

-  "EventName": "l3_request_g1.t5.s3.caching",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x20",

-  "L3SliceMask": "0x08",

-  "UMask": "0x80"

- },

-{

-  "EventName": "l3_request_g1.t6.s3.caching",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x40",

-  "L3SliceMask": "0x08",

-  "UMask": "0x80"

- },

-{

-  "EventName": "l3_request_g1.t7.s3.caching",

-  "EventCode": "0x01",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses",

-  "L3ThreadMask": "0x80",

-  "L3SliceMask": "0x08",

-  "UMask": "0x80"

- },

- {

-  "EventName": "l3fillvicreq.t0.s0.vicblk",

-  "EventCode": "0x03",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",

-  "L3ThreadMask": "0x01",

-  "L3SliceMask": "0x01",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3fillvicreq.t1.s0.vicblk",

-  "EventCode": "0x03",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",

-  "L3ThreadMask": "0x02",

-  "L3SliceMask": "0x01",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3fillvicreq.t2.s0.vicblk",

-  "EventCode": "0x03",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",

-  "L3ThreadMask": "0x04",

-  "L3SliceMask": "0x01",

-  "UMask": "0x01"

- },

- { 

-  "EventName": "l3fillvicreq.t3.s0.vicblk",

-  "EventCode": "0x03",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",

-  "L3ThreadMask": "0x08",

-  "L3SliceMask": "0x01",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3fillvicreq.t4.s0.vicblk",

-  "EventCode": "0x03",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",

-  "L3ThreadMask": "0x10",

-  "L3SliceMask": "0x01",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3fillvicreq.t5.s0.vicblk",

-  "EventCode": "0x03",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",

-  "L3ThreadMask": "0x20",

-  "L3SliceMask": "0x01",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3fillvicreq.t6.s0.vicblk",

-  "EventCode": "0x03",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",

-  "L3ThreadMask": "0x40",

-  "L3SliceMask": "0x01",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3fillvicreq.t7.s0.vicblk",

-  "EventCode": "0x03",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",

-  "L3ThreadMask": "0x80",

-  "L3SliceMask": "0x01",

-  "UMask": "0x01"

- },

- 

- {

-  "EventName": "l3fillvicreq.t0.s1.vicblk",

-  "EventCode": "0x03",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",

-  "L3ThreadMask": "0x01",

-  "L3SliceMask": "0x02",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3fillvicreq.t1.s1.vicblk",

-  "EventCode": "0x03",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",

-  "L3ThreadMask": "0x02",

-  "L3SliceMask": "0x02",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3fillvicreq.t2.s1.vicblk",

-  "EventCode": "0x03",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",

-  "L3ThreadMask": "0x04",

-  "L3SliceMask": "0x02",

-  "UMask": "0x01"

- },

- { 

-  "EventName": "l3fillvicreq.t3.s1.vicblk",

-  "EventCode": "0x03",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",

-  "L3ThreadMask": "0x08",

-  "L3SliceMask": "0x02",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3fillvicreq.t4.s1.vicblk",

-  "EventCode": "0x03",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",

-  "L3ThreadMask": "0x10",

-  "L3SliceMask": "0x02",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3fillvicreq.t5.s1.vicblk",

-  "EventCode": "0x03",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",

-  "L3ThreadMask": "0x20",

-  "L3SliceMask": "0x02",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3fillvicreq.t6.s1.vicblk",

-  "EventCode": "0x03",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",

-  "L3ThreadMask": "0x40",

-  "L3SliceMask": "0x02",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3fillvicreq.t7.s1.vicblk",

-  "EventCode": "0x03",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",

-  "L3ThreadMask": "0x80",

-  "L3SliceMask": "0x02",

-  "UMask": "0x01"

- },

-

-

- {

-  "EventName": "l3fillvicreq.t0.s2.vicblk",

-  "EventCode": "0x03",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",

-  "L3ThreadMask": "0x01",

-  "L3SliceMask": "0x04",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3fillvicreq.t1.s2.vicblk",

-  "EventCode": "0x03",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",

-  "L3ThreadMask": "0x04",

-  "L3SliceMask": "0x01",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3fillvicreq.t2.s2.vicblk",

-  "EventCode": "0x03",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",

-  "L3ThreadMask": "0x04",

-  "L3SliceMask": "0x04",

-  "UMask": "0x01"

- },

- { 

-  "EventName": "l3fillvicreq.t3.s2.vicblk",

-  "EventCode": "0x03",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",

-  "L3ThreadMask": "0x08",

-  "L3SliceMask": "0x04",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3fillvicreq.t4.s2.vicblk",

-  "EventCode": "0x03",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",

-  "L3ThreadMask": "0x10",

-  "L3SliceMask": "0x04",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3fillvicreq.t5.s2.vicblk",

-  "EventCode": "0x03",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",

-  "L3ThreadMask": "0x20",

-  "L3SliceMask": "0x04",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3fillvicreq.t6.s2.vicblk",

-  "EventCode": "0x03",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",

-  "L3ThreadMask": "0x40",

-  "L3SliceMask": "0x04",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3fillvicreq.t7.s2.vicblk",

-  "EventCode": "0x03",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",

-  "L3ThreadMask": "0x80",

-  "L3SliceMask": "0x04",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3fillvicreq.t0.s3.vicblk",

-  "EventCode": "0x03",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",

-  "L3ThreadMask": "0x01",

-  "L3SliceMask": "0x08",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3fillvicreq.t1.s3.vicblk",

-  "EventCode": "0x03",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",

-  "L3ThreadMask": "0x02",

-  "L3SliceMask": "0x08",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3fillvicreq.t2.s3.vicblk",

-  "EventCode": "0x03",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",

-  "L3ThreadMask": "0x04",

-  "L3SliceMask": "0x08",

-  "UMask": "0x01"

- },

- { 

-  "EventName": "l3fillvicreq.t3.s3.vicblk",

-  "EventCode": "0x03",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",

-  "L3ThreadMask": "0x08",

-  "L3SliceMask": "0x08",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3fillvicreq.t4.s3.vicblk",

-  "EventCode": "0x03",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",

-  "L3ThreadMask": "0x10",

-  "L3SliceMask": "0x08",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3fillvicreq.t5.s3.vicblk",

-  "EventCode": "0x03",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",

-  "L3ThreadMask": "0x20",

-  "L3SliceMask": "0x08",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3fillvicreq.t6.s3.vicblk",

-  "EventCode": "0x03",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",

-  "L3ThreadMask": "0x40",

-  "L3SliceMask": "0x08",

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- {

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- {

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- {

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- {

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- {

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- {

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- {

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- {

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- {

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- {

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- {

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- {

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- {

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- {

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- {

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- {

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- {

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- {

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- {

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- {

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- {

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- {

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- {

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- {

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- {

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- {

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- {

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- {

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- {

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- {

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- {

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- {

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- {

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- {

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-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",

-  "L3ThreadMask": "0x40",

-  "L3SliceMask": "0x04",

-  "UMask": "0x80"

- },

- {

-  "EventName": "l3fillvicreq.t7.s2.rdblkl",

-  "EventCode": "0x03",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",

-  "L3ThreadMask": "0x80",

-  "L3SliceMask": "0x04",

-  "UMask": "0x80"

- },

- {

-  "EventName": "l3fillvicreq.t0.s3.rdblkl",

-  "EventCode": "0x03",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",

-  "L3ThreadMask": "0x01",

-  "L3SliceMask": "0x08",

-  "UMask": "0x80"

- },

- {

-  "EventName": "l3fillvicreq.t1.s3.rdblkl",

-  "EventCode": "0x03",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",

-  "L3ThreadMask": "0x02",

-  "L3SliceMask": "0x08",

-  "UMask": "0x80"

- },

- {

-  "EventName": "l3fillvicreq.t2.s3.rdblkl",

-  "EventCode": "0x03",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",

-  "L3ThreadMask": "0x04",

-  "L3SliceMask": "0x08",

-  "UMask": "0x80"

- },

- {

-  "EventName": "l3fillvicreq.t3.s3.rdblkl",

-  "EventCode": "0x03",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",

-  "L3ThreadMask": "0x08",

-  "L3SliceMask": "0x08",

-  "UMask": "0x80"

- },

- {

-  "EventName": "l3fillvicreq.t4.s3.rdblkl",

-  "EventCode": "0x03",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",

-  "L3ThreadMask": "0x10",

-  "L3SliceMask": "0x08",

-  "UMask": "0x80"

- },

- {

-  "EventName": "l3fillvicreq.t5.s3.rdblkl",

-  "EventCode": "0x03",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",

-  "L3ThreadMask": "0x20",

-  "L3SliceMask": "0x08",

-  "UMask": "0x80"

- },

- {

-  "EventName": "l3fillvicreq.t6.s3.rdblkl",

-  "EventCode": "0x03",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",

-  "L3ThreadMask": "0x40",

-  "L3SliceMask": "0x08",

-  "UMask": "0x80"

- },

- {

-  "EventName": "l3fillvicreq.t7.s3.rdblkl",

-  "EventCode": "0x03",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",

-  "L3ThreadMask": "0x80",

-  "L3SliceMask": "0x08",

-  "UMask": "0x80"

- },

- {

-  "EventName": "l3combclstrstate",

-  "EventCode": "0x06",

-  "BriefDescription": "L3 Cache Performance Monitor Counters RequestMiss: L3 miss",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3victimstate.t0.s0.nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x01",

-  "L3SliceMask": "0x01",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3victimstate.t1.s0.nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x02",

-  "L3SliceMask": "0x01",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3victimstate.t2.s0.nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x04",

-  "L3SliceMask": "0x01",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3victimstate.t3.s0.nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x08",

-  "L3SliceMask": "0x01",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3victimstate.t4.s0.nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x10",

-  "L3SliceMask": "0x01",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3victimstate.t5.s0.nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x20",

-  "L3SliceMask": "0x01",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3victimstate.t6.s0.nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x40",

-  "L3SliceMask": "0x01",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3victimstate.t7.s0.nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x80",

-  "L3SliceMask": "0x01",

-  "UMask": "0x01"

- },

- 

- {

-  "EventName": "l3victimstate.t0.s1.nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x01",

-  "L3SliceMask": "0x02",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3victimstate.t1.s1.nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x02",

-  "L3SliceMask": "0x02",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3victimstate.t2.s1.nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x04",

-  "L3SliceMask": "0x02",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3victimstate.t3.s1.nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x08",

-  "L3SliceMask": "0x02",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3victimstate.t4.s1.nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x10",

-  "L3SliceMask": "0x02",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3victimstate.t5.s1.nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x20",

-  "L3SliceMask": "0x02",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3victimstate.t6.s1.nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x40",

-  "L3SliceMask": "0x02",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3victimstate.t7.s1.nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x80",

-  "L3SliceMask": "0x02",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3victimstate.t0.s2.nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x01",

-  "L3SliceMask": "0x04",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3victimstate.t1.s2.nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x02",

-  "L3SliceMask": "0x04",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3victimstate.t2.s2.nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x04",

-  "L3SliceMask": "0x04",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3victimstate.t3.s2.nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x08",

-  "L3SliceMask": "0x04",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3victimstate.t4.s2.nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x10",

-  "L3SliceMask": "0x04",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3victimstate.t5.s2.nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x20",

-  "L3SliceMask": "0x04",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3victimstate.t6.s2.nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x40",

-  "L3SliceMask": "0x04",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3victimstate.t7.s2.nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x80",

-  "L3SliceMask": "0x04",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3victimstate.t0.s3.nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x01",

-  "L3SliceMask": "0x08",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3victimstate.t1.s3.nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x02",

-  "L3SliceMask": "0x08",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3victimstate.t2.s3.nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x04",

-  "L3SliceMask": "0x08",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3victimstate.t3.s3.nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x08",

-  "L3SliceMask": "0x08",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3victimstate.t4.s3.nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x10",

-  "L3SliceMask": "0x08",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3victimstate.t5.s3.nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x20",

-  "L3SliceMask": "0x08",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3victimstate.t6.s3.nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x40",

-  "L3SliceMask": "0x08",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3victimstate.t7.s3.nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x80",

-  "L3SliceMask": "0x08",

-  "UMask": "0x01"

- },

- {

-  "EventName": "l3victimstate.t0.s0.none_nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x01",

-  "L3SliceMask": "0x01",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3victimstate.t1.s0.none_nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x02",

-  "L3SliceMask": "0x01",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3victimstate.t2.s0.none_nol3victimline",

-  "EventCode": "0x09",

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-  "L3ThreadMask": "0x04",

-  "L3SliceMask": "0x01",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3victimstate.t3.s0.none_nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x08",

-  "L3SliceMask": "0x01",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3victimstate.t4.s0.none_nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x10",

-  "L3SliceMask": "0x01",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3victimstate.t5.s0.none_nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x20",

-  "L3SliceMask": "0x01",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3victimstate.t6.s0.none_nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x40",

-  "L3SliceMask": "0x01",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3victimstate.t7.s0.none_nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x80",

-  "L3SliceMask": "0x01",

-  "UMask": "0x02"

- },

- 

- {

-  "EventName": "l3victimstate.t0.s1.none_nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x01",

-  "L3SliceMask": "0x02",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3victimstate.t1.s1.none_nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x02",

-  "L3SliceMask": "0x02",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3victimstate.t2.s1.none_nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x04",

-  "L3SliceMask": "0x02",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3victimstate.t3.s1.none_nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x08",

-  "L3SliceMask": "0x02",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3victimstate.t4.s1.none_nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x10",

-  "L3SliceMask": "0x02",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3victimstate.t5.s1.none_nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x20",

-  "L3SliceMask": "0x02",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3victimstate.t6.s1.none_nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x40",

-  "L3SliceMask": "0x02",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3victimstate.t7.s1.none_nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x80",

-  "L3SliceMask": "0x02",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3victimstate.t0.s2.none_nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x01",

-  "L3SliceMask": "0x04",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3victimstate.t1.s2.none_nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x02",

-  "L3SliceMask": "0x04",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3victimstate.t2.s2.none_nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x04",

-  "L3SliceMask": "0x04",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3victimstate.t3.s2.none_nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x08",

-  "L3SliceMask": "0x04",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3victimstate.t4.s2.none_nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x10",

-  "L3SliceMask": "0x04",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3victimstate.t5.s2.none_nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x20",

-  "L3SliceMask": "0x04",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3victimstate.t6.s2.none_nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x40",

-  "L3SliceMask": "0x04",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3victimstate.t7.s2.none_nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x80",

-  "L3SliceMask": "0x04",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3victimstate.t0.s3.none_nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x01",

-  "L3SliceMask": "0x08",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3victimstate.t1.s3.none_nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x02",

-  "L3SliceMask": "0x08",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3victimstate.t2.s3.none_nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x04",

-  "L3SliceMask": "0x08",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3victimstate.t3.s3.none_nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x08",

-  "L3SliceMask": "0x08",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3victimstate.t4.s3.none_nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x10",

-  "L3SliceMask": "0x08",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3victimstate.t5.s3.none_nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x20",

-  "L3SliceMask": "0x08",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3victimstate.t6.s3.none_nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x40",

-  "L3SliceMask": "0x08",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3victimstate.t7.s3.none_nol3victimline",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x80",

-  "L3SliceMask": "0x08",

-  "UMask": "0x02"

- },

- {

-  "EventName": "l3victimstate.t0.s0.F_S",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x01",

-  "L3SliceMask": "0x01",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3victimstate.t1.s0.F_S",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x02",

-  "L3SliceMask": "0x01",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3victimstate.t2.s0.F_S",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x04",

-  "L3SliceMask": "0x01",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3victimstate.t3.s0.F_S",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x08",

-  "L3SliceMask": "0x01",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3victimstate.t4.s0.F_S",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x10",

-  "L3SliceMask": "0x01",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3victimstate.t5.s0.F_S",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x20",

-  "L3SliceMask": "0x01",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3victimstate.t6.s0.F_S",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x40",

-  "L3SliceMask": "0x01",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3victimstate.t7.s0.F_S",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x80",

-  "L3SliceMask": "0x01",

-  "UMask": "0x04"

- },

- 

- {

-  "EventName": "l3victimstate.t0.s1.F_S",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x01",

-  "L3SliceMask": "0x02",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3victimstate.t1.s1.F_S",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x02",

-  "L3SliceMask": "0x02",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3victimstate.t2.s1.F_S",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x04",

-  "L3SliceMask": "0x02",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3victimstate.t3.s1.F_S",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x08",

-  "L3SliceMask": "0x02",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3victimstate.t4.s1.F_S",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x10",

-  "L3SliceMask": "0x02",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3victimstate.t5.s1.F_S",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x20",

-  "L3SliceMask": "0x02",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3victimstate.t6.s1.F_S",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x40",

-  "L3SliceMask": "0x02",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3victimstate.t7.s1.F_S",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x80",

-  "L3SliceMask": "0x02",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3victimstate.t0.s2.F_S",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x01",

-  "L3SliceMask": "0x04",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3victimstate.t1.s2.F_S",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x02",

-  "L3SliceMask": "0x04",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3victimstate.t2.s2.F_S",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x04",

-  "L3SliceMask": "0x04",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3victimstate.t3.s2.F_S",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x08",

-  "L3SliceMask": "0x04",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3victimstate.t4.s2.F_S",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x10",

-  "L3SliceMask": "0x04",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3victimstate.t5.s2.F_S",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x20",

-  "L3SliceMask": "0x04",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3victimstate.t6.s2.F_S",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x40",

-  "L3SliceMask": "0x04",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3victimstate.t7.s2.F_S",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x80",

-  "L3SliceMask": "0x04",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3victimstate.t0.s3.F_S",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x01",

-  "L3SliceMask": "0x08",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3victimstate.t1.s3.F_S",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x02",

-  "L3SliceMask": "0x08",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3victimstate.t2.s3.F_S",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x04",

-  "L3SliceMask": "0x08",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3victimstate.t3.s3.F_S",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x08",

-  "L3SliceMask": "0x08",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3victimstate.t4.s3.F_S",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x10",

-  "L3SliceMask": "0x08",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3victimstate.t5.s3.F_S",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x20",

-  "L3SliceMask": "0x08",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3victimstate.t6.s3.F_S",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x40",

-  "L3SliceMask": "0x08",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3victimstate.t7.s3.F_S",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x80",

-  "L3SliceMask": "0x08",

-  "UMask": "0x04"

- },

- {

-  "EventName": "l3victimstate.t0.s0.o",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x01",

-  "L3SliceMask": "0x01",

-  "UMask": "0x08"

- },

- {

-  "EventName": "l3victimstate.t1.s0.o",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x02",

-  "L3SliceMask": "0x01",

-  "UMask": "0x08"

- },

- {

-  "EventName": "l3victimstate.t2.s0.o",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x04",

-  "L3SliceMask": "0x01",

-  "UMask": "0x08"

- },

- {

-  "EventName": "l3victimstate.t3.s0.o",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x08",

-  "L3SliceMask": "0x01",

-  "UMask": "0x08"

- },

- {

-  "EventName": "l3victimstate.t4.s0.o",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x10",

-  "L3SliceMask": "0x01",

-  "UMask": "0x08"

- },

- {

-  "EventName": "l3victimstate.t5.s0.o",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x20",

-  "L3SliceMask": "0x01",

-  "UMask": "0x08"

- },

- {

-  "EventName": "l3victimstate.t6.s0.o",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x40",

-  "L3SliceMask": "0x01",

-  "UMask": "0x08"

- },

- {

-  "EventName": "l3victimstate.t7.s0.o",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x80",

-  "L3SliceMask": "0x01",

-  "UMask": "0x08"

- },

- 

- {

-  "EventName": "l3victimstate.t0.s1.o",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x01",

-  "L3SliceMask": "0x02",

-  "UMask": "0x08"

- },

- {

-  "EventName": "l3victimstate.t1.s1.o",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x02",

-  "L3SliceMask": "0x02",

-  "UMask": "0x08"

- },

- {

-  "EventName": "l3victimstate.t2.s1.o",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x04",

-  "L3SliceMask": "0x02",

-  "UMask": "0x08"

- },

- {

-  "EventName": "l3victimstate.t3.s1.o",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x08",

-  "L3SliceMask": "0x02",

-  "UMask": "0x08"

- },

- {

-  "EventName": "l3victimstate.t4.s1.o",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x10",

-  "L3SliceMask": "0x02",

-  "UMask": "0x08"

- },

- {

-  "EventName": "l3victimstate.t5.s1.o",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x20",

-  "L3SliceMask": "0x02",

-  "UMask": "0x08"

- },

- {

-  "EventName": "l3victimstate.t6.s1.o",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x40",

-  "L3SliceMask": "0x02",

-  "UMask": "0x08"

- },

- {

-  "EventName": "l3victimstate.t7.s1.o",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x80",

-  "L3SliceMask": "0x02",

-  "UMask": "0x08"

- },

- {

-  "EventName": "l3victimstate.t0.s2.o",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x01",

-  "L3SliceMask": "0x04",

-  "UMask": "0x08"

- },

- {

-  "EventName": "l3victimstate.t1.s2.o",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x02",

-  "L3SliceMask": "0x04",

-  "UMask": "0x08"

- },

- {

-  "EventName": "l3victimstate.t2.s2.o",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x04",

-  "L3SliceMask": "0x04",

-  "UMask": "0x08"

- },

- {

-  "EventName": "l3victimstate.t3.s2.o",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x08",

-  "L3SliceMask": "0x04",

-  "UMask": "0x08"

- },

- {

-  "EventName": "l3victimstate.t4.s2.o",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x10",

-  "L3SliceMask": "0x04",

-  "UMask": "0x08"

- },

- {

-  "EventName": "l3victimstate.t5.s2.o",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x20",

-  "L3SliceMask": "0x04",

-  "UMask": "0x08"

- },

- {

-  "EventName": "l3victimstate.t6.s2.o",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x40",

-  "L3SliceMask": "0x04",

-  "UMask": "0x08"

- },

- {

-  "EventName": "l3victimstate.t7.s2.o",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x80",

-  "L3SliceMask": "0x04",

-  "UMask": "0x08"

- },

- {

-  "EventName": "l3victimstate.t0.s3.o",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x01",

-  "L3SliceMask": "0x08",

-  "UMask": "0x08"

- },

- {

-  "EventName": "l3victimstate.t1.s3.o",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x02",

-  "L3SliceMask": "0x08",

-  "UMask": "0x08"

- },

- {

-  "EventName": "l3victimstate.t2.s3.o",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x04",

-  "L3SliceMask": "0x08",

-  "UMask": "0x08"

- },

- {

-  "EventName": "l3victimstate.t3.s3.o",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x08",

-  "L3SliceMask": "0x08",

-  "UMask": "0x08"

- },

- {

-  "EventName": "l3victimstate.t4.s3.o",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x10",

-  "L3SliceMask": "0x08",

-  "UMask": "0x08"

- },

- {

-  "EventName": "l3victimstate.t5.s3.o",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x20",

-  "L3SliceMask": "0x08",

-  "UMask": "0x08"

- },

- {

-  "EventName": "l3victimstate.t6.s3.o",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x40",

-  "L3SliceMask": "0x08",

-  "UMask": "0x08"

- },

- {

-  "EventName": "l3victimstate.t7.s3.o",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x80",

-  "L3SliceMask": "0x08",

-  "UMask": "0x08"

- },

- {

-  "EventName": "l3victimstate.t0.s0.e_fe",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x01",

-  "L3SliceMask": "0x01",

-  "UMask": "0x10"

- },

- {

-  "EventName": "l3victimstate.t1.s0.e_fe",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x02",

-  "L3SliceMask": "0x01",

-  "UMask": "0x10"

- },

- {

-  "EventName": "l3victimstate.t2.s0.e_fe",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x04",

-  "L3SliceMask": "0x01",

-  "UMask": "0x10"

- },

- {

-  "EventName": "l3victimstate.t3.s0.e_fe",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x08",

-  "L3SliceMask": "0x01",

-  "UMask": "0x10"

- },

- {

-  "EventName": "l3victimstate.t4.s0.e_fe",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x10",

-  "L3SliceMask": "0x01",

-  "UMask": "0x10"

- },

- {

-  "EventName": "l3victimstate.t5.s0.e_fe",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

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-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x80",

-  "L3SliceMask": "0x02",

-  "UMask": "0x40"

- },

- {

-  "EventName": "l3victimstate.t0.s2.d",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x01",

-  "L3SliceMask": "0x04",

-  "UMask": "0x40"

- },

- {

-  "EventName": "l3victimstate.t1.s2.d",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x02",

-  "L3SliceMask": "0x04",

-  "UMask": "0x40"

- },

- {

-  "EventName": "l3victimstate.t2.s2.d",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x04",

-  "L3SliceMask": "0x04",

-  "UMask": "0x40"

- },

- {

-  "EventName": "l3victimstate.t3.s2.d",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x08",

-  "L3SliceMask": "0x04",

-  "UMask": "0x40"

- },

- {

-  "EventName": "l3victimstate.t4.s2.d",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x10",

-  "L3SliceMask": "0x04",

-  "UMask": "0x40"

- },

- {

-  "EventName": "l3victimstate.t5.s2.d",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x20",

-  "L3SliceMask": "0x04",

-  "UMask": "0x40"

- },

- {

-  "EventName": "l3victimstate.t6.s2.d",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x40",

-  "L3SliceMask": "0x04",

-  "UMask": "0x40"

- },

- {

-  "EventName": "l3victimstate.t7.s2.d",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x80",

-  "L3SliceMask": "0x04",

-  "UMask": "0x40"

- },

- {

-  "EventName": "l3victimstate.t0.s3.d",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x01",

-  "L3SliceMask": "0x08",

-  "UMask": "0x40"

- },

- {

-  "EventName": "l3victimstate.t1.s3.d",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x02",

-  "L3SliceMask": "0x08",

-  "UMask": "0x40"

- },

- {

-  "EventName": "l3victimstate.t2.s3.d",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x04",

-  "L3SliceMask": "0x08",

-  "UMask": "0x40"

- },

- {

-  "EventName": "l3victimstate.t3.s3.d",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x08",

-  "L3SliceMask": "0x08",

-  "UMask": "0x40"

- },

- {

-  "EventName": "l3victimstate.t4.s3.d",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x10",

-  "L3SliceMask": "0x08",

-  "UMask": "0x40"

- },

- {

-  "EventName": "l3victimstate.t5.s3.d",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x20",

-  "L3SliceMask": "0x08",

-  "UMask": "0x40"

- },

- {

-  "EventName": "l3victimstate.t6.s3.d",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x40",

-  "L3SliceMask": "0x08",

-  "UMask": "0x40"

- },

- {

-  "EventName": "l3victimstate.t7.s3.d",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x80",

-  "L3SliceMask": "0x08",

-  "UMask": "0x40"

- },

- {

-  "EventName": "l3victimstate.t0.s0.od",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x01",

-  "L3SliceMask": "0x01",

-  "UMask": "0x80"

- },

- {

-  "EventName": "l3victimstate.t1.s0.od",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x02",

-  "L3SliceMask": "0x01",

-  "UMask": "0x80"

- },

- {

-  "EventName": "l3victimstate.t2.s0.od",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x04",

-  "L3SliceMask": "0x01",

-  "UMask": "0x80"

- },

- {

-  "EventName": "l3victimstate.t3.s0.od",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x08",

-  "L3SliceMask": "0x01",

-  "UMask": "0x80"

- },

- {

-  "EventName": "l3victimstate.t4.s0.od",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x10",

-  "L3SliceMask": "0x01",

-  "UMask": "0x80"

- },

- {

-  "EventName": "l3victimstate.t5.s0.od",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x20",

-  "L3SliceMask": "0x01",

-  "UMask": "0x80"

- },

- {

-  "EventName": "l3victimstate.t6.s0.od",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x40",

-  "L3SliceMask": "0x01",

-  "UMask": "0x80"

- },

- {

-  "EventName": "l3victimstate.t7.s0.od",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x80",

-  "L3SliceMask": "0x01",

-  "UMask": "0x80"

- },

- 

- {

-  "EventName": "l3victimstate.t0.s1.od",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x01",

-  "L3SliceMask": "0x02",

-  "UMask": "0x80"

- },

- {

-  "EventName": "l3victimstate.t1.s1.od",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x02",

-  "L3SliceMask": "0x02",

-  "UMask": "0x80"

- },

- {

-  "EventName": "l3victimstate.t2.s1.od",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x04",

-  "L3SliceMask": "0x02",

-  "UMask": "0x80"

- },

- {

-  "EventName": "l3victimstate.t3.s1.od",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x08",

-  "L3SliceMask": "0x02",

-  "UMask": "0x80"

- },

- {

-  "EventName": "l3victimstate.t4.s1.od",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x10",

-  "L3SliceMask": "0x02",

-  "UMask": "0x80"

- },

- {

-  "EventName": "l3victimstate.t5.s1.od",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x20",

-  "L3SliceMask": "0x02",

-  "UMask": "0x80"

- },

- {

-  "EventName": "l3victimstate.t6.s1.od",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x40",

-  "L3SliceMask": "0x02",

-  "UMask": "0x80"

- },

- {

-  "EventName": "l3victimstate.t7.s1.od",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x80",

-  "L3SliceMask": "0x02",

-  "UMask": "0x80"

- },

- {

-  "EventName": "l3victimstate.t0.s2.od",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x01",

-  "L3SliceMask": "0x04",

-  "UMask": "0x80"

- },

- {

-  "EventName": "l3victimstate.t1.s2.od",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x02",

-  "L3SliceMask": "0x04",

-  "UMask": "0x80"

- },

- {

-  "EventName": "l3victimstate.t2.s2.od",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x04",

-  "L3SliceMask": "0x04",

-  "UMask": "0x80"

- },

- {

-  "EventName": "l3victimstate.t3.s2.od",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x08",

-  "L3SliceMask": "0x04",

-  "UMask": "0x80"

- },

- {

-  "EventName": "l3victimstate.t4.s2.od",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x10",

-  "L3SliceMask": "0x04",

-  "UMask": "0x80"

- },

- {

-  "EventName": "l3victimstate.t5.s2.od",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x20",

-  "L3SliceMask": "0x04",

-  "UMask": "0x80"

- },

- {

-  "EventName": "l3victimstate.t6.s2.od",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x40",

-  "L3SliceMask": "0x04",

-  "UMask": "0x80"

- },

- {

-  "EventName": "l3victimstate.t7.s2.od",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x80",

-  "L3SliceMask": "0x04",

-  "UMask": "0x80"

- },

- {

-  "EventName": "l3victimstate.t0.s3.od",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x01",

-  "L3SliceMask": "0x08",

-  "UMask": "0x80"

- },

- {

-  "EventName": "l3victimstate.t1.s3.od",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x02",

-  "L3SliceMask": "0x08",

-  "UMask": "0x80"

- },

- {

-  "EventName": "l3victimstate.t2.s3.od",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x04",

-  "L3SliceMask": "0x08",

-  "UMask": "0x80"

- },

- {

-  "EventName": "l3victimstate.t3.s3.od",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x08",

-  "L3SliceMask": "0x08",

-  "UMask": "0x80"

- },

- {

-  "EventName": "l3victimstate.t4.s3.od",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x10",

-  "L3SliceMask": "0x08",

-  "UMask": "0x80"

- },

- {

-  "EventName": "l3victimstate.t5.s3.od",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x20",

-  "L3SliceMask": "0x08",

-  "UMask": "0x80"

- },

- {

-  "EventName": "l3victimstate.t6.s3.od",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x40",

-  "L3SliceMask": "0x08",

-  "UMask": "0x80"

- },

- {

-  "EventName": "l3victimstate.t7.s3.od",

-  "EventCode": "0x09",

-  "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",

-  "L3ThreadMask": "0x80",

-  "L3SliceMask": "0x08",

-  "UMask": "0x80"

- }

- 

-]

-

diff --git a/lib/libpmc/pmu-events/arch/x86/amdzen1/memory.json b/lib/libpmc/pmu-events/arch/x86/amdzen1/memory.json
index b33a3c308019..385022fb026e 100644
--- a/lib/libpmc/pmu-events/arch/x86/amdzen1/memory.json
+++ b/lib/libpmc/pmu-events/arch/x86/amdzen1/memory.json
@@ -3,25 +3,25 @@
     "EventName": "ls_locks.bus_lock",
     "EventCode": "0x25",
     "BriefDescription": "Bus lock when a locked operations crosses a cache boundary or is done on an uncacheable memory type.",
-    "UMask": "0x1"
+    "UMask": "0x01"
   },
   {
     "EventName": "ls_dispatch.ld_st_dispatch",
     "EventCode": "0x29",
     "BriefDescription": "Counts the number of operations dispatched to the LS unit. Unit Masks ADDed. Load-op-Stores.",
-    "UMask": "0x4"
+    "UMask": "0x04"
   },
   {
     "EventName": "ls_dispatch.store_dispatch",
     "EventCode": "0x29",
     "BriefDescription": "Counts the number of stores dispatched to the LS unit. Unit Masks ADDed.",
-    "UMask": "0x2"
+    "UMask": "0x02"
   },
   {
     "EventName": "ls_dispatch.ld_dispatch",
     "EventCode": "0x29",
     "BriefDescription": "Counts the number of loads dispatched to the LS unit. Unit Masks ADDed.",
-    "UMask": "0x1"
+    "UMask": "0x01"
   },
   {
     "EventName": "ls_stlf",
@@ -37,13 +37,13 @@
     "EventName": "ls_mab_alloc.dc_prefetcher",
     "EventCode": "0x41",
     "BriefDescription": "LS MAB allocates by type - DC prefetcher.",
-    "UMask": "0x8"
+    "UMask": "0x08"
   },
   {
     "EventName": "ls_mab_alloc.stores",
     "EventCode": "0x41",
     "BriefDescription": "LS MAB allocates by type - stores.",
-    "UMask": "0x2"
+    "UMask": "0x02"
   },
   {
     "EventName": "ls_mab_alloc.loads",
@@ -85,61 +85,61 @@
     "EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit",
     "EventCode": "0x45",
     "BriefDescription": "L1 DTLB Reload of a page of 1G size.",
-    "UMask": "0x8"
+    "UMask": "0x08"
   },
   {
     "EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit",
     "EventCode": "0x45",
     "BriefDescription": "L1 DTLB Reload of a page of 2M size.",
-    "UMask": "0x4"
+    "UMask": "0x04"
   },
   {
     "EventName": "ls_l1_d_tlb_miss.tlb_reload_32k_l2_hit",
     "EventCode": "0x45",
     "BriefDescription": "L1 DTLB Reload of a page of 32K size.",
-    "UMask": "0x2"
+    "UMask": "0x02"
   },
   {
     "EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit",
     "EventCode": "0x45",
     "BriefDescription": "L1 DTLB Reload of a page of 4K size.",
-    "UMask": "0x1"
+    "UMask": "0x01"
   },
   {
     "EventName": "ls_tablewalker.iside",
     "EventCode": "0x46",
     "BriefDescription": "Total Page Table Walks on I-side.",
-    "UMask": "0xc"
+    "UMask": "0x0c"
   },
   {
     "EventName": "ls_tablewalker.ic_type1",
     "EventCode": "0x46",
     "BriefDescription": "Total Page Table Walks IC Type 1.",
-    "UMask": "0x8"
+    "UMask": "0x08"
   },
   {
     "EventName": "ls_tablewalker.ic_type0",
     "EventCode": "0x46",
     "BriefDescription": "Total Page Table Walks IC Type 0.",
-    "UMask": "0x4"
+    "UMask": "0x04"
   },
   {
     "EventName": "ls_tablewalker.dside",
     "EventCode": "0x46",
     "BriefDescription": "Total Page Table Walks on D-side.",
-    "UMask": "0x3"
+    "UMask": "0x03"
   },
   {
     "EventName": "ls_tablewalker.dc_type1",
     "EventCode": "0x46",
     "BriefDescription": "Total Page Table Walks DC Type 1.",
-    "UMask": "0x2"
+    "UMask": "0x02"
   },
   {
     "EventName": "ls_tablewalker.dc_type0",
     "EventCode": "0x46",
     "BriefDescription": "Total Page Table Walks DC Type 0.",
-    "UMask": "0x1"
+    "UMask": "0x01"
   },
   {
     "EventName": "ls_misal_accesses",
@@ -150,31 +150,31 @@
     "EventName": "ls_pref_instr_disp.prefetch_nta",
     "EventCode": "0x4b",
     "BriefDescription": "Software Prefetch Instructions (PREFETCHNTA instruction) Dispatched.",
-    "UMask": "0x4"
+    "UMask": "0x04"
   },
   {
     "EventName": "ls_pref_instr_disp.store_prefetch_w",
     "EventCode": "0x4b",
     "BriefDescription": "Software Prefetch Instructions (3DNow PREFETCHW instruction) Dispatched.",
-    "UMask": "0x2"
+    "UMask": "0x02"
   },
   {
     "EventName": "ls_pref_instr_disp.load_prefetch_w",
     "EventCode": "0x4b",
     "BriefDescription": "Software Prefetch Instructions Dispatched. Prefetch, Prefetch_T0_T1_T2.",
-    "UMask": "0x1"
+    "UMask": "0x01"
   },
   {
     "EventName": "ls_inef_sw_pref.mab_mch_cnt",
     "EventCode": "0x52",
     "BriefDescription": "The number of software prefetches that did not fetch data outside of the processor core. Software PREFETCH instruction saw a match on an already-allocated miss request buffer.",
-    "UMask": "0x2"
+    "UMask": "0x02"
   },
   {
     "EventName": "ls_inef_sw_pref.data_pipe_sw_pf_dc_hit",
     "EventCode": "0x52",
     "BriefDescription": "The number of software prefetches that did not fetch data outside of the processor core. Software PREFETCH instruction saw a DC hit.",
-    "UMask": "0x1"
+    "UMask": "0x01"
   },
   {
     "EventName": "ls_not_halted_cyc",
diff --git a/lib/libpmc/pmu-events/arch/x86/amdzen1/other.json b/lib/libpmc/pmu-events/arch/x86/amdzen1/other.json
index ff780098d36e..7626986ce1fb 100644
--- a/lib/libpmc/pmu-events/arch/x86/amdzen1/other.json
+++ b/lib/libpmc/pmu-events/arch/x86/amdzen1/other.json
@@ -3,13 +3,13 @@
     "EventName": "ic_oc_mode_switch.oc_ic_mode_switch",
     "EventCode": "0x28a",
     "BriefDescription": "OC Mode Switch. OC to IC mode switch.",
-    "UMask": "0x2"
+    "UMask": "0x02"
   },
   {
     "EventName": "ic_oc_mode_switch.ic_oc_mode_switch",
     "EventCode": "0x28a",
     "BriefDescription": "OC Mode Switch. IC to OC mode switch.",
-    "UMask": "0x1"
+    "UMask": "0x01"
   },
   {
     "EventName": "de_dis_dispatch_token_stalls0.retire_token_stall",
@@ -33,24 +33,24 @@
     "EventName": "de_dis_dispatch_token_stalls0.alsq3_0_token_stall",
     "EventCode": "0xaf",
     "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 3_0 Tokens unavailable.",
-    "UMask": "0x8"
+    "UMask": "0x08"
   },
   {
     "EventName": "de_dis_dispatch_token_stalls0.alsq3_token_stall",
     "EventCode": "0xaf",
     "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 3 Tokens unavailable.",
-    "UMask": "0x4"
+    "UMask": "0x04"
   },
   {
     "EventName": "de_dis_dispatch_token_stalls0.alsq2_token_stall",
     "EventCode": "0xaf",
     "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 2 Tokens unavailable.",
-    "UMask": "0x2"
+    "UMask": "0x02"
   },
   {
     "EventName": "de_dis_dispatch_token_stalls0.alsq1_token_stall",
     "EventCode": "0xaf",
     "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 1 Tokens unavailable.",
-    "UMask": "0x1"
+    "UMask": "0x01"
   }
 ]
diff --git a/lib/libpmc/pmu-events/arch/x86/amdzen1/recommended.json b/lib/libpmc/pmu-events/arch/x86/amdzen1/recommended.json
new file mode 100644
index 000000000000..bf5083c1c260
--- /dev/null
+++ b/lib/libpmc/pmu-events/arch/x86/amdzen1/recommended.json
@@ -0,0 +1,178 @@
+[
+  {
+    "MetricName": "branch_misprediction_ratio",
+    "BriefDescription": "Execution-Time Branch Misprediction Ratio (Non-Speculative)",
+    "MetricExpr": "d_ratio(ex_ret_brn_misp, ex_ret_brn)",
+    "MetricGroup": "branch_prediction",
+    "ScaleUnit": "100%"
+  },
+  {
+    "EventName": "all_dc_accesses",
+    "EventCode": "0x29",
+    "BriefDescription": "All L1 Data Cache Accesses",
+    "UMask": "0x07"
+  },
+  {
+    "MetricName": "all_l2_cache_accesses",
+    "BriefDescription": "All L2 Cache Accesses",
+    "MetricExpr": "l2_request_g1.all_no_prefetch + l2_pf_hit_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3",
+    "MetricGroup": "l2_cache"
+  },
+  {
+    "EventName": "l2_cache_accesses_from_ic_misses",
+    "EventCode": "0x60",
+    "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)",
+    "UMask": "0x10"
+  },
+  {
+    "EventName": "l2_cache_accesses_from_dc_misses",
+    "EventCode": "0x60",
+    "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)",
+    "UMask": "0xc8"
+  },
+  {
+    "MetricName": "l2_cache_accesses_from_l2_hwpf",
+    "BriefDescription": "L2 Cache Accesses from L2 HWPF",
+    "MetricExpr": "l2_pf_hit_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3",
+    "MetricGroup": "l2_cache"
+  },
+  {
+    "MetricName": "all_l2_cache_misses",
+    "BriefDescription": "All L2 Cache Misses",
+    "MetricExpr": "l2_cache_req_stat.ic_dc_miss_in_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3",
+    "MetricGroup": "l2_cache"
+  },
+  {
+    "EventName": "l2_cache_misses_from_ic_miss",
+    "EventCode": "0x64",
+    "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses",
+    "UMask": "0x01"
+  },
+  {
+    "EventName": "l2_cache_misses_from_dc_misses",
+    "EventCode": "0x64",
+    "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses",
+    "UMask": "0x08"
+  },
+  {
+    "MetricName": "l2_cache_misses_from_l2_hwpf",
+    "BriefDescription": "L2 Cache Misses from L2 HWPF",
+    "MetricExpr": "l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3",
+    "MetricGroup": "l2_cache"
+  },
+  {
+    "MetricName": "all_l2_cache_hits",
+    "BriefDescription": "All L2 Cache Hits",
+    "MetricExpr": "l2_cache_req_stat.ic_dc_hit_in_l2 + l2_pf_hit_l2",
+    "MetricGroup": "l2_cache"
+  },
+  {
+    "EventName": "l2_cache_hits_from_ic_misses",
+    "EventCode": "0x64",
+    "BriefDescription": "L2 Cache Hits from L1 Instruction Cache Misses",
+    "UMask": "0x06"
+  },
+  {
+    "EventName": "l2_cache_hits_from_dc_misses",
+    "EventCode": "0x64",
+    "BriefDescription": "L2 Cache Hits from L1 Data Cache Misses",
+    "UMask": "0x70"
+  },
+  {
+    "EventName": "l2_cache_hits_from_l2_hwpf",
+    "EventCode": "0x70",
+    "BriefDescription": "L2 Cache Hits from L2 HWPF",
+    "UMask": "0xff"
+  },
+  {
+    "EventName": "l3_accesses",
+    "EventCode": "0x04",
+    "BriefDescription": "L3 Accesses",
+    "UMask": "0xff",
+    "Unit": "L3PMC"
+  },
+  {
+    "EventName": "l3_misses",
+    "EventCode": "0x04",
+    "BriefDescription": "L3 Misses (includes Chg2X)",
+    "UMask": "0x01",
+    "Unit": "L3PMC"
+  },
+  {
+    "MetricName": "l3_read_miss_latency",
+    "BriefDescription": "Average L3 Read Miss Latency (in core clocks)",
+    "MetricExpr": "(xi_sys_fill_latency * 16) / xi_ccx_sdp_req1.all_l3_miss_req_typs",
+    "MetricGroup": "l3_cache",
+    "ScaleUnit": "1core clocks"
+  },
+  {
+    "MetricName": "ic_fetch_miss_ratio",
+    "BriefDescription": "L1 Instruction Cache (32B) Fetch Miss Ratio",
+    "MetricExpr": "d_ratio(l2_cache_req_stat.ic_access_in_l2, bp_l1_tlb_fetch_hit + bp_l1_tlb_miss_l2_hit + bp_l1_tlb_miss_l2_miss)",
+    "MetricGroup": "l2_cache",
+    "ScaleUnit": "100%"
+  },
+  {
+    "MetricName": "l1_itlb_misses",
+    "BriefDescription": "L1 ITLB Misses",
+    "MetricExpr": "bp_l1_tlb_miss_l2_hit + bp_l1_tlb_miss_l2_miss",
+    "MetricGroup": "tlb"
+  },
+  {
+    "EventName": "l2_itlb_misses",
+    "EventCode": "0x85",
+    "BriefDescription": "L2 ITLB Misses & Instruction page walks",
+    "UMask": "0x07"
+  },
+  {
+    "EventName": "l1_dtlb_misses",
+    "EventCode": "0x45",
+    "BriefDescription": "L1 DTLB Misses",
+    "UMask": "0xff"
+  },
+  {
+    "EventName": "l2_dtlb_misses",
+    "EventCode": "0x45",
+    "BriefDescription": "L2 DTLB Misses & Data page walks",
+    "UMask": "0xf0"
+  },
+  {
+    "EventName": "all_tlbs_flushed",
+    "EventCode": "0x78",
+    "BriefDescription": "All TLBs Flushed",
+    "UMask": "0xdf"
+  },
+  {
+    "EventName": "uops_dispatched",
+    "EventCode": "0xaa",
+    "BriefDescription": "Micro-ops Dispatched",
+    "UMask": "0x03"
+  },
+  {
+    "EventName": "sse_avx_stalls",
+    "EventCode": "0x0e",
+    "BriefDescription": "Mixed SSE/AVX Stalls",
+    "UMask": "0x0e"
+  },
+  {
+    "EventName": "uops_retired",
+    "EventCode": "0xc1",
+    "BriefDescription": "Micro-ops Retired"
+  },
+  {
+    "MetricName": "all_remote_links_outbound",
+    "BriefDescription": "Approximate: Outbound data bytes for all Remote Links for a node (die)",
+    "MetricExpr": "remote_outbound_data_controller_0 + remote_outbound_data_controller_1 + remote_outbound_data_controller_2 + remote_outbound_data_controller_3",
+    "MetricGroup": "data_fabric",
+    "PerPkg": "1",
+    "ScaleUnit": "3e-5MiB"
+  },
+  {
+    "MetricName": "nps1_die_to_dram",
+    "BriefDescription": "Approximate: Combined DRAM B/bytes of all channels on a NPS1 node (die) (may need --metric-no-group)",
+    "MetricExpr": "dram_channel_data_controller_0 + dram_channel_data_controller_1 + dram_channel_data_controller_2 + dram_channel_data_controller_3 + dram_channel_data_controller_4 + dram_channel_data_controller_5 + dram_channel_data_controller_6 + dram_channel_data_controller_7",
+    "MetricGroup": "data_fabric",
+    "PerPkg": "1",
+    "ScaleUnit": "6.1e-5MiB"
+  }
+]
diff --git a/lib/libpmc/pmu-events/arch/x86/amdzen2/branch.json b/lib/libpmc/pmu-events/arch/x86/amdzen2/branch.json
index ef4166a66288..84fb43fa59ad 100644
--- a/lib/libpmc/pmu-events/arch/x86/amdzen2/branch.json
+++ b/lib/libpmc/pmu-events/arch/x86/amdzen2/branch.json
@@ -24,25 +24,25 @@
     "EventName": "bp_l1_tlb_fetch_hit",
     "EventCode": "0x94",
     "BriefDescription": "The number of instruction fetches that hit in the L1 ITLB.",
-    "UMask": "0xFF"
+    "UMask": "0xff"
   },
   {
     "EventName": "bp_l1_tlb_fetch_hit.if1g",
     "EventCode": "0x94",
     "BriefDescription": "The number of instruction fetches that hit in the L1 ITLB. Instruction fetches to a 1GB page.",
-    "UMask": "0x4"
+    "UMask": "0x04"
   },
   {
     "EventName": "bp_l1_tlb_fetch_hit.if2m",
     "EventCode": "0x94",
     "BriefDescription": "The number of instruction fetches that hit in the L1 ITLB. Instruction fetches to a 2MB page.",
-    "UMask": "0x2"
+    "UMask": "0x02"
   },
   {
     "EventName": "bp_l1_tlb_fetch_hit.if4k",
     "EventCode": "0x94",
     "BriefDescription": "The number of instruction fetches that hit in the L1 ITLB. Instruction fetches to a 4KB page.",
-    "UMask": "0x1"
+    "UMask": "0x01"
   },
   {
     "EventName": "bp_tlb_rel",
diff --git a/lib/libpmc/pmu-events/arch/x86/amdzen2/cache.json b/lib/libpmc/pmu-events/arch/x86/amdzen2/cache.json
index 1c60bfa0f00b..c858fb9477e3 100644
--- a/lib/libpmc/pmu-events/arch/x86/amdzen2/cache.json
+++ b/lib/libpmc/pmu-events/arch/x86/amdzen2/cache.json
@@ -27,25 +27,30 @@
     "EventName": "l2_request_g1.change_to_x",
     "EventCode": "0x60",
     "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change requests. Request change to writable, check L2 for current state.",
-    "UMask": "0x8"
+    "UMask": "0x08"
   },
   {
     "EventName": "l2_request_g1.prefetch_l2_cmd",
     "EventCode": "0x60",
     "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
-    "UMask": "0x4"
+    "UMask": "0x04"
   },
   {
     "EventName": "l2_request_g1.l2_hw_pf",
     "EventCode": "0x60",
     "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches accepted by L2 pipeline, hit or miss. Types of PF and L2 hit/miss broken out in a separate perfmon event.",
-    "UMask": "0x2"
+    "UMask": "0x02"
   },
   {
     "EventName": "l2_request_g1.group2",
     "EventCode": "0x60",
     "BriefDescription": "Miscellaneous events covered in more detail by l2_request_g2 (PMCx061).",
-    "UMask": "0x1"
+    "UMask": "0x01"
+  },
+  {
+    "EventName": "l2_request_g1.all_no_prefetch",
+    "EventCode": "0x60",
+    "UMask": "0xf9"
   },
   {
     "EventName": "l2_request_g2.group1",
@@ -75,31 +80,31 @@
     "EventName": "l2_request_g2.ic_rd_sized_nc",
     "EventCode": "0x61",
     "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized non-cacheable.",
-    "UMask": "0x8"
+    "UMask": "0x08"
   },
   {
     "EventName": "l2_request_g2.smc_inval",
     "EventCode": "0x61",
     "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Self-modifying code invalidates.",
-    "UMask": "0x4"
+    "UMask": "0x04"
   },
   {
     "EventName": "l2_request_g2.bus_locks_originator",
     "EventCode": "0x61",
     "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Bus locks.",
-    "UMask": "0x2"
+    "UMask": "0x02"
   },
   {
     "EventName": "l2_request_g2.bus_locks_responses",
     "EventCode": "0x61",
     "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Bus lock response.",
-    "UMask": "0x1"
+    "UMask": "0x01"
   },
   {
     "EventName": "l2_latency.l2_cycles_waiting_on_fills",
     "EventCode": "0x62",
     "BriefDescription": "Total cycles spent waiting for L2 fills to complete from L3 or memory, divided by four. Event counts are for both threads. To calculate average latency, the number of fills from both threads must be used.",
-    "UMask": "0x1"
+    "UMask": "0x01"
   },
   {
     "EventName": "l2_wcb_req.wcb_write",
@@ -117,13 +122,13 @@
     "EventName": "l2_wcb_req.zero_byte_store",
     "EventCode": "0x63",
     "BriefDescription": "LS to L2 WCB zero byte store requests. LS (Load/Store unit) to L2 WCB (Write Combining Buffer) zero byte store requests.",
-    "UMask": "0x4"
+    "UMask": "0x04"
   },
   {
     "EventName": "l2_wcb_req.cl_zero",
     "EventCode": "0x63",
     "BriefDescription": "LS to L2 WCB cache line zeroing requests. LS (Load/Store unit) to L2 WCB (Write Combining Buffer) cache line zeroing requests.",
-    "UMask": "0x1"
+    "UMask": "0x01"
   },
   {
     "EventName": "l2_cache_req_stat.ls_rd_blk_cs",
@@ -153,36 +158,54 @@
     "EventName": "l2_cache_req_stat.ls_rd_blk_c",
     "EventCode": "0x64",
     "BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Data cache request miss in L2 (all types).",
-    "UMask": "0x8"
+    "UMask": "0x08"
   },
   {
     "EventName": "l2_cache_req_stat.ic_fill_hit_x",
     "EventCode": "0x64",
     "BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache hit modifiable line in L2.",
-    "UMask": "0x4"
+    "UMask": "0x04"
   },
   {
     "EventName": "l2_cache_req_stat.ic_fill_hit_s",
     "EventCode": "0x64",
     "BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache hit clean line in L2.",
-    "UMask": "0x2"
+    "UMask": "0x02"
   },
   {
     "EventName": "l2_cache_req_stat.ic_fill_miss",
     "EventCode": "0x64",
     "BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request miss in L2.",
-    "UMask": "0x1"
+    "UMask": "0x01"
+  },
+  {
+    "EventName": "l2_cache_req_stat.ic_access_in_l2",
+    "EventCode": "0x64",
+    "BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache requests in L2.",
+    "UMask": "0x07"
+  },
+  {
+    "EventName": "l2_cache_req_stat.ic_dc_miss_in_l2",
+    "EventCode": "0x64",
+    "BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request miss in L2 and Data cache request miss in L2 (all types).",
+    "UMask": "0x09"
+  },
+  {
+    "EventName": "l2_cache_req_stat.ic_dc_hit_in_l2",
+    "EventCode": "0x64",
+    "BriefDescription": "Core to L2 cacheable request access status (not including L2 Prefetch). Instruction cache request hit in L2 and Data cache request hit in L2 (all types).",
+    "UMask": "0xf6"
   },
   {
     "EventName": "l2_fill_pending.l2_fill_busy",
     "EventCode": "0x6d",
     "BriefDescription": "Cycles with fill pending from L2. Total cycles spent with one or more fill requests in flight from L2.",
-    "UMask": "0x1"
+    "UMask": "0x01"
   },
   {
     "EventName": "l2_pf_hit_l2",
     "EventCode": "0x70",
-    "BriefDescription": "L2 prefetch hit in L2.",
+    "BriefDescription": "L2 prefetch hit in L2. Use l2_cache_hits_from_l2_hwpf instead.",
     "UMask": "0xff"
   },
   {
@@ -232,19 +255,19 @@
     "EventName": "bp_l1_tlb_miss_l2_tlb_miss.if1g",
     "EventCode": "0x85",
     "BriefDescription": "The number of instruction fetches that miss in both the L1 and L2 TLBs. Instruction fetches to a 1GB page.",
-    "UMask": "0x4"
+    "UMask": "0x04"
   },
   {
     "EventName": "bp_l1_tlb_miss_l2_tlb_miss.if2m",
     "EventCode": "0x85",
     "BriefDescription": "The number of instruction fetches that miss in both the L1 and L2 TLBs. Instruction fetches to a 2MB page.",
-    "UMask": "0x2"
+    "UMask": "0x02"
   },
   {
     "EventName": "bp_l1_tlb_miss_l2_tlb_miss.if4k",
     "EventCode": "0x85",
     "BriefDescription": "The number of instruction fetches that miss in both the L1 and L2 TLBs. Instruction fetches to a 4KB page.",
-    "UMask": "0x1"
+    "UMask": "0x01"
   },
   {
     "EventName": "bp_snp_re_sync",
@@ -255,43 +278,43 @@
     "EventName": "ic_fetch_stall.ic_stall_any",
     "EventCode": "0x87",
     "BriefDescription": "Instruction Pipe Stall. IC pipe was stalled during this clock cycle for any reason (nothing valid in pipe ICM1).",
-    "UMask": "0x4"
+    "UMask": "0x04"
   },
   {
     "EventName": "ic_fetch_stall.ic_stall_dq_empty",
     "EventCode": "0x87",
     "BriefDescription": "Instruction Pipe Stall. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to DQ empty.",
-    "UMask": "0x2"
+    "UMask": "0x02"
   },
   {
     "EventName": "ic_fetch_stall.ic_stall_back_pressure",
     "EventCode": "0x87",
     "BriefDescription": "Instruction Pipe Stall. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to back-pressure.",
-    "UMask": "0x1"
+    "UMask": "0x01"
   },
   {
     "EventName": "ic_cache_inval.l2_invalidating_probe",
     "EventCode": "0x8c",
     "BriefDescription": "IC line invalidated due to L2 invalidating probe (external or LS). The number of instruction cache lines invalidated. A non-SMC event is CMC (cross modifying code), either from the other thread of the core or another core.",
-    "UMask": "0x2"
+    "UMask": "0x02"
   },
   {
     "EventName": "ic_cache_inval.fill_invalidated",
     "EventCode": "0x8c",
     "BriefDescription": "IC line invalidated due to overwriting fill response. The number of instruction cache lines invalidated. A non-SMC event is CMC (cross modifying code), either from the other thread of the core or another core.",
-    "UMask": "0x1"
+    "UMask": "0x01"
   },
   {
     "EventName": "ic_oc_mode_switch.oc_ic_mode_switch",
     "EventCode": "0x28a",
     "BriefDescription": "OC Mode Switch. OC to IC mode switch.",
-    "UMask": "0x2"
+    "UMask": "0x02"
   },
   {
     "EventName": "ic_oc_mode_switch.ic_oc_mode_switch",
     "EventCode": "0x28a",
     "BriefDescription": "OC Mode Switch. IC to OC mode switch.",
-    "UMask": "0x1"
+    "UMask": "0x01"
   },
   {
     "EventName": "l3_request_g1.caching_l3_cache_accesses",
@@ -330,7 +353,7 @@
   },
   {
     "EventName": "xi_ccx_sdp_req1.all_l3_miss_req_typs",
-    "EventCode": "0x9A",
+    "EventCode": "0x9a",
     "BriefDescription": "All L3 Miss Request Types. Ignores SliceMask and ThreadMask.",
     "UMask": "0x3f",
     "Unit": "L3PMC"
diff --git a/lib/libpmc/pmu-events/arch/x86/amdzen2/core.json b/lib/libpmc/pmu-events/arch/x86/amdzen2/core.json
index de89e5a44ff1..bed14829f0bc 100644
--- a/lib/libpmc/pmu-events/arch/x86/amdzen2/core.json
+++ b/lib/libpmc/pmu-events/arch/x86/amdzen2/core.json
@@ -68,21 +68,21 @@
     "EventCode": "0xcb",
     "BriefDescription": "SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX).",
     "PublicDescription": "The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX).",
-    "UMask": "0x4"
+    "UMask": "0x04"
   },
   {
     "EventName": "ex_ret_mmx_fp_instr.mmx_instr",
     "EventCode": "0xcb",
     "BriefDescription": "MMX instructions.",
     "PublicDescription": "The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. MMX instructions.",
-    "UMask": "0x2"
+    "UMask": "0x02"
   },
   {
     "EventName": "ex_ret_mmx_fp_instr.x87_instr",
     "EventCode": "0xcb",
     "BriefDescription": "x87 instructions.",
     "PublicDescription": "The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. x87 instructions.",
-    "UMask": "0x1"
+    "UMask": "0x01"
   },
   {
     "EventName": "ex_ret_cond",
@@ -108,23 +108,23 @@
     "EventName": "ex_tagged_ibs_ops.ibs_count_rollover",
     "EventCode": "0x1cf",
     "BriefDescription": "Tagged IBS Ops. Number of times an op could not be tagged by IBS because of a previous tagged op that has not retired.",
-    "UMask": "0x4"
+    "UMask": "0x04"
   },
   {
     "EventName": "ex_tagged_ibs_ops.ibs_tagged_ops_ret",
     "EventCode": "0x1cf",
     "BriefDescription": "Tagged IBS Ops. Number of Ops tagged by IBS that retired.",
-    "UMask": "0x2"
+    "UMask": "0x02"
   },
   {
     "EventName": "ex_tagged_ibs_ops.ibs_tagged_ops",
     "EventCode": "0x1cf",
     "BriefDescription": "Tagged IBS Ops. Number of Ops tagged by IBS.",
-    "UMask": "0x1"
+    "UMask": "0x01"
   },
   {
     "EventName": "ex_ret_fus_brnch_inst",
     "EventCode": "0x1d0",
-    "BriefDescription": "Retired Fused Instructions. The number of fuse-branch instructions retired per cycle. The number of events logged per cycle can vary from 0-8.",
+    "BriefDescription": "Retired Fused Instructions. The number of fuse-branch instructions retired per cycle. The number of events logged per cycle can vary from 0-8."
   }
 ]
diff --git a/lib/libpmc/pmu-events/arch/x86/amdzen2/data-fabric.json b/lib/libpmc/pmu-events/arch/x86/amdzen2/data-fabric.json
new file mode 100644
index 000000000000..40271df40015
--- /dev/null
+++ b/lib/libpmc/pmu-events/arch/x86/amdzen2/data-fabric.json
@@ -0,0 +1,98 @@
+[
+  {
+    "EventName": "remote_outbound_data_controller_0",
+    "PublicDescription": "Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Controller 0",
+    "EventCode": "0x7c7",
+    "UMask": "0x02",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_outbound_data_controller_1",
+    "PublicDescription": "Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Controller 1",
+    "EventCode": "0x807",
+    "UMask": "0x02",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_outbound_data_controller_2",
+    "PublicDescription": "Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Controller 2",
+    "EventCode": "0x847",
+    "UMask": "0x02",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "remote_outbound_data_controller_3",
+    "PublicDescription": "Remote Link Controller Outbound Packet Types: Data (32B): Remote Link Controller 3",
+    "EventCode": "0x887",
+    "UMask": "0x02",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "dram_channel_data_controller_0",
+    "PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0",
+    "EventCode": "0x07",
+    "UMask": "0x38",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "dram_channel_data_controller_1",
+    "PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0",
+    "EventCode": "0x47",
+    "UMask": "0x38",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "dram_channel_data_controller_2",
+    "PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0",
+    "EventCode": "0x87",
+    "UMask": "0x38",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "dram_channel_data_controller_3",
+    "PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0",
+    "EventCode": "0xc7",
+    "UMask": "0x38",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "dram_channel_data_controller_4",
+    "PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0",
+    "EventCode": "0x107",
+    "UMask": "0x38",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "dram_channel_data_controller_5",
+    "PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0",
+    "EventCode": "0x147",
+    "UMask": "0x38",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "dram_channel_data_controller_6",
+    "PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0",
+    "EventCode": "0x187",
+    "UMask": "0x38",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  },
+  {
+    "EventName": "dram_channel_data_controller_7",
+    "PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channel Controller 0",
+    "EventCode": "0x1c7",
+    "UMask": "0x38",
+    "PerPkg": "1",
+    "Unit": "DFPMC"
+  }
+]
diff --git a/lib/libpmc/pmu-events/arch/x86/amdzen2/floating-point.json b/lib/libpmc/pmu-events/arch/x86/amdzen2/floating-point.json
index 622a0c420e46..91ed96f2580b 100644
--- a/lib/libpmc/pmu-events/arch/x86/amdzen2/floating-point.json
+++ b/lib/libpmc/pmu-events/arch/x86/amdzen2/floating-point.json
@@ -4,35 +4,35 @@
     "EventCode": "0x00",
     "BriefDescription": "Total number of fp uOps.",
     "PublicDescription": "Total number of fp uOps. The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS.",
-    "UMask": "0xf"
+    "UMask": "0x0f"
   },
   {
     "EventName": "fpu_pipe_assignment.total3",
     "EventCode": "0x00",
     "BriefDescription": "Total number uOps assigned to pipe 3.",
     "PublicDescription": "The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one-cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 3.",
-    "UMask": "0x8"
+    "UMask": "0x08"
   },
   {
     "EventName": "fpu_pipe_assignment.total2",
     "EventCode": "0x00",
     "BriefDescription": "Total number uOps assigned to pipe 2.",
     "PublicDescription": "The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 2.",
-    "UMask": "0x4"
+    "UMask": "0x04"
   },
   {
     "EventName": "fpu_pipe_assignment.total1",
     "EventCode": "0x00",
     "BriefDescription": "Total number uOps assigned to pipe 1.",
     "PublicDescription": "The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 1.",
-    "UMask": "0x2"
+    "UMask": "0x02"
   },
   {
     "EventName": "fpu_pipe_assignment.total0",
     "EventCode": "0x00",
     "BriefDescription": "Total number of fp uOps  on pipe 0.",
     "PublicDescription": "The number of operations (uOps) dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the FPU pipelines are and may be used for workload characterization. This includes all operations performed by x87, MMX, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. This event is a speculative event. Since this event includes non-numeric operations it is not suitable for measuring MFLOPS. Total number uOps assigned to pipe 0.",
-    "UMask": "0x1"
+    "UMask": "0x01"
   },
   {
     "EventName": "fp_ret_sse_avx_ops.all",
@@ -45,96 +45,96 @@
     "EventCode": "0x03",
     "BriefDescription": "Multiply-add FLOPS. Multiply-add counts as 2 FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15.",
     "PublicDescription": "",
-    "UMask": "0x8"
+    "UMask": "0x08"
   },
   {
     "EventName": "fp_ret_sse_avx_ops.div_flops",
     "EventCode": "0x03",
     "BriefDescription": "Divide/square root FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15.",
-    "UMask": "0x4"
+    "UMask": "0x04"
   },
   {
     "EventName": "fp_ret_sse_avx_ops.mult_flops",
     "EventCode": "0x03",
     "BriefDescription": "Multiply FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15.",
-    "UMask": "0x2"
+    "UMask": "0x02"
   },
   {
     "EventName": "fp_ret_sse_avx_ops.add_sub_flops",
     "EventCode": "0x03",
     "BriefDescription": "Add/subtract FLOPS. This is a retire-based event. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to 64. This event can count above 15.",
-    "UMask": "0x1"
+    "UMask": "0x01"
   },
   {
     "EventName": "fp_num_mov_elim_scal_op.optimized",
     "EventCode": "0x04",
     "BriefDescription": "Number of Scalar Ops optimized. This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes.",
-    "UMask": "0x8"
+    "UMask": "0x08"
   },
   {
     "EventName": "fp_num_mov_elim_scal_op.opt_potential",
     "EventCode": "0x04",
     "BriefDescription": "Number of Ops that are candidates for optimization (have Z-bit either set or pass). This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes.",
-    "UMask": "0x4"
+    "UMask": "0x04"
   },
   {
     "EventName": "fp_num_mov_elim_scal_op.sse_mov_ops_elim",
     "EventCode": "0x04",
     "BriefDescription": "Number of SSE Move Ops eliminated. This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes.",
-    "UMask": "0x2"
+    "UMask": "0x02"
   },
   {
     "EventName": "fp_num_mov_elim_scal_op.sse_mov_ops",
     "EventCode": "0x04",
     "BriefDescription": "Number of SSE Move Ops. This is a dispatch based speculative event, and is useful for measuring the effectiveness of the Move elimination and Scalar code optimization schemes.",
-    "UMask": "0x1"
+    "UMask": "0x01"
   },
   {
     "EventName": "fp_retired_ser_ops.sse_bot_ret",
     "EventCode": "0x05",
     "BriefDescription": "SSE bottom-executing uOps retired. The number of serializing Ops retired.",
-    "UMask": "0x8"
+    "UMask": "0x08"
   },
   {
     "EventName": "fp_retired_ser_ops.sse_ctrl_ret",
     "EventCode": "0x05",
     "BriefDescription": "The number of serializing Ops retired. SSE control word mispredict traps due to mispredictions in RC, FTZ or DAZ, or changes in mask bits.",
-    "UMask": "0x4"
+    "UMask": "0x04"
   },
   {
     "EventName": "fp_retired_ser_ops.x87_bot_ret",
     "EventCode": "0x05",
     "BriefDescription": "x87 bottom-executing uOps retired. The number of serializing Ops retired.",
-    "UMask": "0x2"
+    "UMask": "0x02"
   },
   {
     "EventName": "fp_retired_ser_ops.x87_ctrl_ret",
     "EventCode": "0x05",
     "BriefDescription": "x87 control word mispredict traps due to mispredictions in RC or PC, or changes in mask bits. The number of serializing Ops retired.",
-    "UMask": "0x1"
+    "UMask": "0x01"
   },
   {
     "EventName": "fp_disp_faults.ymm_spill_fault",
     "EventCode": "0x0e",
     "BriefDescription": "Floating Point Dispatch Faults. YMM spill fault.",
-    "UMask": "0x8"
+    "UMask": "0x08"
   },
   {
     "EventName": "fp_disp_faults.ymm_fill_fault",
     "EventCode": "0x0e",
     "BriefDescription": "Floating Point Dispatch Faults. YMM fill fault.",
-    "UMask": "0x4"
+    "UMask": "0x04"
   },
   {
     "EventName": "fp_disp_faults.xmm_fill_fault",
     "EventCode": "0x0e",
     "BriefDescription": "Floating Point Dispatch Faults. XMM fill fault.",
-    "UMask": "0x2"
+    "UMask": "0x02"
   },
   {
     "EventName": "fp_disp_faults.x87_fill_fault",
     "EventCode": "0x0e",
     "BriefDescription": "Floating Point Dispatch Faults. x87 fill fault.",
-    "UMask": "0x1"
+    "UMask": "0x01"
   }
 ]
diff --git a/lib/libpmc/pmu-events/arch/x86/amdzen2/memory.json b/lib/libpmc/pmu-events/arch/x86/amdzen2/memory.json
index 715046b339cb..89822b9ddb79 100644
--- a/lib/libpmc/pmu-events/arch/x86/amdzen2/memory.json
+++ b/lib/libpmc/pmu-events/arch/x86/amdzen2/memory.json
@@ -4,31 +4,31 @@
     "EventCode": "0x24",
     "BriefDescription": "Non-forwardable conflict; used to reduce STLI's via software. All reasons. Store To Load Interlock (STLI) are loads that were unable to complete because of a possible match with an older store, and the older store could not do STLF for some reason.",
     "PublicDescription" : "Store-to-load conflicts: A load was unable to complete due to a non-forwardable conflict with an older store. Most commonly, a load's address range partially but not completely overlaps with an uncompleted older store. Software can avoid this problem by using same-size and same-alignment loads and stores when accessing the same data. Vector/SIMD code is particularly susceptible to this problem; software should construct wide vector stores by manipulating vector elements in registers using shuffle/blend/swap instructions prior to storing to memory, instead of using narrow element-by-element stores.",
-    "UMask": "0x2"
+    "UMask": "0x02"
   },
   {
     "EventName": "ls_locks.spec_lock_hi_spec",
     "EventCode": "0x25",
     "BriefDescription": "Retired lock instructions. High speculative cacheable lock speculation succeeded.",
-    "UMask": "0x8"
+    "UMask": "0x08"
   },
   {
     "EventName": "ls_locks.spec_lock_lo_spec",
     "EventCode": "0x25",
     "BriefDescription": "Retired lock instructions. Low speculative cacheable lock speculation succeeded.",
-    "UMask": "0x4"
+    "UMask": "0x04"
   },
   {
     "EventName": "ls_locks.non_spec_lock",
     "EventCode": "0x25",
     "BriefDescription": "Retired lock instructions. Non-speculative lock succeeded.",
-    "UMask": "0x2"
+    "UMask": "0x02"
   },
   {
     "EventName": "ls_locks.bus_lock",
     "EventCode": "0x25",
     "BriefDescription": "Retired lock instructions. Bus lock when a locked operations crosses a cache boundary or is done on an uncacheable memory type. Comparable to legacy bus lock.",
-    "UMask": "0x1"
+    "UMask": "0x01"
   },
   {
     "EventName": "ls_ret_cl_flush",
@@ -44,33 +44,33 @@
     "EventName": "ls_dispatch.ld_st_dispatch",
     "EventCode": "0x29",
     "BriefDescription": "Dispatch of a single op that performs a load from and store to the same memory address. Number of single ops that do load/store to an address.",
-    "UMask": "0x4"
+    "UMask": "0x04"
   },
   {
     "EventName": "ls_dispatch.store_dispatch",
     "EventCode": "0x29",
     "BriefDescription": "Number of stores dispatched. Counts the number of operations dispatched to the LS unit. Unit Masks ADDed.",
-    "UMask": "0x2"
+    "UMask": "0x02"
   },
   {
     "EventName": "ls_dispatch.ld_dispatch",
     "EventCode": "0x29",
     "BriefDescription": "Number of loads dispatched. Counts the number of operations dispatched to the LS unit. Unit Masks ADDed.",
-    "UMask": "0x1"
+    "UMask": "0x01"
   },
   {
     "EventName": "ls_smi_rx",
-    "EventCode": "0x2B",
+    "EventCode": "0x2b",
     "BriefDescription": "Number of SMIs received."
   },
   {
     "EventName": "ls_int_taken",
-    "EventCode": "0x2C",
+    "EventCode": "0x2c",
     "BriefDescription": "Number of interrupts taken."
   },
   {
     "EventName": "ls_rdtsc",
-    "EventCode": "0x2D",
+    "EventCode": "0x2d",
     "BriefDescription": "Number of reads of the TSC (RDTSC instructions). The count is speculative."
   },
   {
@@ -93,19 +93,19 @@
     "EventName": "ls_mab_alloc.dc_prefetcher",
     "EventCode": "0x41",
     "BriefDescription": "LS MAB Allocates by Type. DC prefetcher.",
-    "UMask": "0x8"
+    "UMask": "0x08"
   },
   {
     "EventName": "ls_mab_alloc.stores",
     "EventCode": "0x41",
     "BriefDescription": "LS MAB Allocates by Type. Stores.",
-    "UMask": "0x2"
+    "UMask": "0x02"
   },
   {
     "EventName": "ls_mab_alloc.loads",
     "EventCode": "0x41",
     "BriefDescription": "LS MAB Allocates by Type. Loads.",
-    "UMask": "0x1"
+    "UMask": "0x01"
   },
   {
     "EventName": "ls_refills_from_sys.ls_mabresp_rmt_dram",
@@ -123,19 +123,19 @@
     "EventName": "ls_refills_from_sys.ls_mabresp_lcl_dram",
     "EventCode": "0x43",
     "BriefDescription": "Demand Data Cache Fills by Data Source. DRAM or IO from this thread's die.",
-    "UMask": "0x8"
+    "UMask": "0x08"
   },
   {
     "EventName": "ls_refills_from_sys.ls_mabresp_lcl_cache",
     "EventCode": "0x43",
     "BriefDescription": "Demand Data Cache Fills by Data Source. Hit in cache; local CCX (not Local L2), or Remote CCX and the address's Home Node is on this thread's die.",
-    "UMask": "0x2"
+    "UMask": "0x02"
   },
   {
     "EventName": "ls_refills_from_sys.ls_mabresp_lcl_l2",
     "EventCode": "0x43",
     "BriefDescription": "Demand Data Cache Fills by Data Source. Local L2 hit.",
-    "UMask": "0x1"
+    "UMask": "0x01"
   },
   {
     "EventName": "ls_l1_d_tlb_miss.all",
@@ -171,61 +171,61 @@
     "EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit",
     "EventCode": "0x45",
     "BriefDescription": "L1 DTLB Miss. DTLB reload to a 1G page that hit in the L2 TLB.",
-    "UMask": "0x8"
+    "UMask": "0x08"
   },
   {
     "EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit",
     "EventCode": "0x45",
     "BriefDescription": "L1 DTLB Miss. DTLB reload to a 2M page that hit in the L2 TLB.",
-    "UMask": "0x4"
+    "UMask": "0x04"
   },
   {
     "EventName": "ls_l1_d_tlb_miss.tlb_reload_coalesced_page_hit",
     "EventCode": "0x45",
     "BriefDescription": "L1 DTLB Miss. DTLB reload hit a coalesced page.",
-    "UMask": "0x2"
+    "UMask": "0x02"
   },
   {
     "EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit",
     "EventCode": "0x45",
     "BriefDescription": "L1 DTLB Miss. DTLB reload to a 4K page that hit in the L2 TLB.",
-    "UMask": "0x1"
+    "UMask": "0x01"
   },
   {
     "EventName": "ls_tablewalker.iside",
     "EventCode": "0x46",
     "BriefDescription": "Total Page Table Walks on I-side.",
-    "UMask": "0xc"
+    "UMask": "0x0c"
   },
   {
     "EventName": "ls_tablewalker.ic_type1",
     "EventCode": "0x46",
     "BriefDescription": "Total Page Table Walks IC Type 1.",
-    "UMask": "0x8"
+    "UMask": "0x08"
   },
   {
     "EventName": "ls_tablewalker.ic_type0",
     "EventCode": "0x46",
     "BriefDescription": "Total Page Table Walks IC Type 0.",
-    "UMask": "0x4"
+    "UMask": "0x04"
   },
   {
     "EventName": "ls_tablewalker.dside",
     "EventCode": "0x46",
     "BriefDescription": "Total Page Table Walks on D-side.",
-    "UMask": "0x3"
+    "UMask": "0x03"
   },
   {
     "EventName": "ls_tablewalker.dc_type1",
     "EventCode": "0x46",
     "BriefDescription": "Total Page Table Walks DC Type 1.",
-    "UMask": "0x2"
+    "UMask": "0x02"
   },
   {
     "EventName": "ls_tablewalker.dc_type0",
     "EventCode": "0x46",
     "BriefDescription": "Total Page Table Walks DC Type 0.",
-    "UMask": "0x1"
+    "UMask": "0x01"
   },
   {
     "EventName": "ls_misal_accesses",
@@ -242,31 +242,31 @@
     "EventName": "ls_pref_instr_disp.prefetch_nta",
     "EventCode": "0x4b",
     "BriefDescription": "Software Prefetch Instructions Dispatched (Speculative). PrefetchNTA instruction. See docAPM3 PREFETCHlevel.",
-    "UMask": "0x4"
+    "UMask": "0x04"
   },
   {
     "EventName": "ls_pref_instr_disp.prefetch_w",
     "EventCode": "0x4b",
     "BriefDescription": "Software Prefetch Instructions Dispatched (Speculative). See docAPM3 PREFETCHW.",
-    "UMask": "0x2"
+    "UMask": "0x02"
   },
   {
     "EventName": "ls_pref_instr_disp.prefetch",
     "EventCode": "0x4b",
     "BriefDescription": "Software Prefetch Instructions Dispatched (Speculative). Prefetch_T0_T1_T2. PrefetchT0, T1 and T2 instructions. See docAPM3 PREFETCHlevel.",
-    "UMask": "0x1"
+    "UMask": "0x01"
   },
   {
     "EventName": "ls_inef_sw_pref.mab_mch_cnt",
     "EventCode": "0x52",
     "BriefDescription": "The number of software prefetches that did not fetch data outside of the processor core. Software PREFETCH instruction saw a match on an already-allocated miss request buffer.",
-    "UMask": "0x2"
+    "UMask": "0x02"
   },
   {
     "EventName": "ls_inef_sw_pref.data_pipe_sw_pf_dc_hit",
     "EventCode": "0x52",
     "BriefDescription": "The number of software prefetches that did not fetch data outside of the processor core. Software PREFETCH instruction saw a DC hit.",
-    "UMask": "0x1"
+    "UMask": "0x01"
   },
   {
     "EventName": "ls_sw_pf_dc_fill.ls_mabresp_rmt_dram",
@@ -284,49 +284,49 @@
     "EventName": "ls_sw_pf_dc_fill.ls_mabresp_lcl_dram",
     "EventCode": "0x59",
     "BriefDescription": "Software Prefetch Data Cache Fills by Data Source. DRAM or IO from this thread's die.  From DRAM (home node local).",
-    "UMask": "0x8"
+    "UMask": "0x08"
   },
   {
     "EventName": "ls_sw_pf_dc_fill.ls_mabresp_lcl_cache",
     "EventCode": "0x59",
     "BriefDescription": "Software Prefetch Data Cache Fills by Data Source. From another cache (home node local).",
-    "UMask": "0x2"
+    "UMask": "0x02"
   },
   {
     "EventName": "ls_sw_pf_dc_fill.ls_mabresp_lcl_l2",
     "EventCode": "0x59",
     "BriefDescription": "Software Prefetch Data Cache Fills by Data Source. Local L2 hit.",
-    "UMask": "0x1"
+    "UMask": "0x01"
   },
   {
     "EventName": "ls_hw_pf_dc_fill.ls_mabresp_rmt_dram",
-    "EventCode": "0x5A",
+    "EventCode": "0x5a",
     "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From DRAM (home node remote).",
     "UMask": "0x40"
   },
   {
     "EventName": "ls_hw_pf_dc_fill.ls_mabresp_rmt_cache",
-    "EventCode": "0x5A",
+    "EventCode": "0x5a",
     "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From another cache (home node remote).",
     "UMask": "0x10"
   },
   {
     "EventName": "ls_hw_pf_dc_fill.ls_mabresp_lcl_dram",
-    "EventCode": "0x5A",
+    "EventCode": "0x5a",
     "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From DRAM (home node local).",
-    "UMask": "0x8"
+    "UMask": "0x08"
   },
   {
     "EventName": "ls_hw_pf_dc_fill.ls_mabresp_lcl_cache",
-    "EventCode": "0x5A",
+    "EventCode": "0x5a",
     "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From another cache (home node local).",
-    "UMask": "0x2"
+    "UMask": "0x02"
   },
   {
     "EventName": "ls_hw_pf_dc_fill.ls_mabresp_lcl_l2",
-    "EventCode": "0x5A",
+    "EventCode": "0x5a",
     "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. Local L2 hit.",
-    "UMask": "0x1"
+    "UMask": "0x01"
   },
   {
     "EventName": "ls_not_halted_cyc",
diff --git a/lib/libpmc/pmu-events/arch/x86/amdzen2/other.json b/lib/libpmc/pmu-events/arch/x86/amdzen2/other.json
index e94994d4a60e..1bdf106ca785 100644
--- a/lib/libpmc/pmu-events/arch/x86/amdzen2/other.json
+++ b/lib/libpmc/pmu-events/arch/x86/amdzen2/other.json
@@ -14,13 +14,13 @@
     "EventName": "de_dis_uops_from_decoder.opcache_dispatched",
     "EventCode": "0xaa",
     "BriefDescription": "Count of dispatched Ops from OpCache.",
-    "UMask": "0x2"
+    "UMask": "0x02"
   },
   {
     "EventName": "de_dis_uops_from_decoder.decoder_dispatched",
     "EventCode": "0xaa",
     "BriefDescription": "Count of dispatched Ops from Decoder.",
-    "UMask": "0x1"
+    "UMask": "0x01"
   },
   {
     "EventName": "de_dis_dispatch_token_stalls1.fp_misc_rsrc_stall",
@@ -50,25 +50,25 @@
     "EventName": "de_dis_dispatch_token_stalls1.int_sched_misc_token_stall",
     "EventCode": "0xae",
     "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Integer Scheduler miscellaneous resource stall.",
-    "UMask": "0x8"
+    "UMask": "0x08"
   },
   {
     "EventName": "de_dis_dispatch_token_stalls1.store_queue_token_stall",
     "EventCode": "0xae",
     "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Store queue resource stall. Applies to all ops with store semantics.",
-    "UMask": "0x4"
+    "UMask": "0x04"
   },
   {
     "EventName": "de_dis_dispatch_token_stalls1.load_queue_token_stall",
     "EventCode": "0xae",
     "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Load queue resource stall. Applies to all ops with load semantics.",
-    "UMask": "0x2"
+    "UMask": "0x02"
   },
   {
     "EventName": "de_dis_dispatch_token_stalls1.int_phy_reg_file_token_stall",
     "EventCode": "0xae",
     "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. Integer Physical Register File resource stall. Applies to all ops that have an integer destination register.",
-    "UMask": "0x1"
+    "UMask": "0x01"
   },
   {
     "EventName": "de_dis_dispatch_token_stalls0.sc_agu_dispatch_stall",
@@ -92,24 +92,24 @@
     "EventName": "de_dis_dispatch_token_stalls0.alu_token_stall",
     "EventCode": "0xaf",
     "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALU tokens total unavailable.",
-    "UMask": "0x8"
+    "UMask": "0x08"
   },
   {
     "EventName": "de_dis_dispatch_token_stalls0.alsq3_0_token_stall",
     "EventCode": "0xaf",
     "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ3_0_TokenStall.",
-    "UMask": "0x4"
+    "UMask": "0x04"
   },
   {
     "EventName": "de_dis_dispatch_token_stalls0.alsq2_token_stall",
     "EventCode": "0xaf",
     "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 2 Tokens unavailable.",
-    "UMask": "0x2"
+    "UMask": "0x02"
   },
   {
     "EventName": "de_dis_dispatch_token_stalls0.alsq1_token_stall",
     "EventCode": "0xaf",
     "BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a token stall. ALSQ 1 Tokens unavailable.",
-    "UMask": "0x1"
+    "UMask": "0x01"
   }
 ]
diff --git a/lib/libpmc/pmu-events/arch/x86/amdzen2/recommended.json b/lib/libpmc/pmu-events/arch/x86/amdzen2/recommended.json
new file mode 100644
index 000000000000..a71694a043ba
--- /dev/null
+++ b/lib/libpmc/pmu-events/arch/x86/amdzen2/recommended.json
@@ -0,0 +1,178 @@
+[
+  {
+    "MetricName": "branch_misprediction_ratio",
+    "BriefDescription": "Execution-Time Branch Misprediction Ratio (Non-Speculative)",
+    "MetricExpr": "d_ratio(ex_ret_brn_misp, ex_ret_brn)",
+    "MetricGroup": "branch_prediction",
+    "ScaleUnit": "100%"
+  },
+  {
+    "EventName": "all_dc_accesses",
+    "EventCode": "0x29",
+    "BriefDescription": "All L1 Data Cache Accesses",
+    "UMask": "0x07"
+  },
+  {
+    "MetricName": "all_l2_cache_accesses",
+    "BriefDescription": "All L2 Cache Accesses",
+    "MetricExpr": "l2_request_g1.all_no_prefetch + l2_pf_hit_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3",
+    "MetricGroup": "l2_cache"
+  },
+  {
+    "EventName": "l2_cache_accesses_from_ic_misses",
+    "EventCode": "0x60",
+    "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)",
+    "UMask": "0x10"
+  },
+  {
+    "EventName": "l2_cache_accesses_from_dc_misses",
+    "EventCode": "0x60",
+    "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)",
+    "UMask": "0xc8"
+  },
+  {
+    "MetricName": "l2_cache_accesses_from_l2_hwpf",
+    "BriefDescription": "L2 Cache Accesses from L2 HWPF",
+    "MetricExpr": "l2_pf_hit_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3",
+    "MetricGroup": "l2_cache"
+  },
+  {
+    "MetricName": "all_l2_cache_misses",
+    "BriefDescription": "All L2 Cache Misses",
+    "MetricExpr": "l2_cache_req_stat.ic_dc_miss_in_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3",
+    "MetricGroup": "l2_cache"
+  },
+  {
+    "EventName": "l2_cache_misses_from_ic_miss",
+    "EventCode": "0x64",
+    "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses",
+    "UMask": "0x01"
+  },
+  {
+    "EventName": "l2_cache_misses_from_dc_misses",
+    "EventCode": "0x64",
+    "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses",
+    "UMask": "0x08"
+  },
+  {
+    "MetricName": "l2_cache_misses_from_l2_hwpf",
+    "BriefDescription": "L2 Cache Misses from L2 HWPF",
+    "MetricExpr": "l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3",
+    "MetricGroup": "l2_cache"
+  },
+  {
+    "MetricName": "all_l2_cache_hits",
+    "BriefDescription": "All L2 Cache Hits",
+    "MetricExpr": "l2_cache_req_stat.ic_dc_hit_in_l2 + l2_pf_hit_l2",
+    "MetricGroup": "l2_cache"
+  },
+  {
+    "EventName": "l2_cache_hits_from_ic_misses",
+    "EventCode": "0x64",
+    "BriefDescription": "L2 Cache Hits from L1 Instruction Cache Misses",
+    "UMask": "0x06"
+  },
+  {
+    "EventName": "l2_cache_hits_from_dc_misses",
+    "EventCode": "0x64",
+    "BriefDescription": "L2 Cache Hits from L1 Data Cache Misses",
+    "UMask": "0x70"
+  },
+  {
+    "EventName": "l2_cache_hits_from_l2_hwpf",
+    "EventCode": "0x70",
+    "BriefDescription": "L2 Cache Hits from L2 HWPF",
+    "UMask": "0xff"
+  },
+  {
+    "EventName": "l3_accesses",
+    "EventCode": "0x04",
+    "BriefDescription": "L3 Accesses",
+    "UMask": "0xff",
+    "Unit": "L3PMC"
+  },
+  {
+    "EventName": "l3_misses",
+    "EventCode": "0x04",
+    "BriefDescription": "L3 Misses (includes Chg2X)",
+    "UMask": "0x01",
+    "Unit": "L3PMC"
+  },
+  {
+    "MetricName": "l3_read_miss_latency",
+    "BriefDescription": "Average L3 Read Miss Latency (in core clocks)",
+    "MetricExpr": "(xi_sys_fill_latency * 16) / xi_ccx_sdp_req1.all_l3_miss_req_typs",
+    "MetricGroup": "l3_cache",
+    "ScaleUnit": "1core clocks"
+  },
+  {
+    "MetricName": "ic_fetch_miss_ratio",
+    "BriefDescription": "L1 Instruction Cache (32B) Fetch Miss Ratio",
+    "MetricExpr": "d_ratio(l2_cache_req_stat.ic_access_in_l2, bp_l1_tlb_fetch_hit + bp_l1_tlb_miss_l2_hit + bp_l1_tlb_miss_l2_tlb_miss)",
+    "MetricGroup": "l2_cache",
+    "ScaleUnit": "100%"
+  },
+  {
+    "MetricName": "l1_itlb_misses",
+    "BriefDescription": "L1 ITLB Misses",
+    "MetricExpr": "bp_l1_tlb_miss_l2_hit + bp_l1_tlb_miss_l2_tlb_miss",
+    "MetricGroup": "tlb"
+  },
+  {
+    "EventName": "l2_itlb_misses",
+    "EventCode": "0x85",
+    "BriefDescription": "L2 ITLB Misses & Instruction page walks",
+    "UMask": "0x07"
+  },
+  {
+    "EventName": "l1_dtlb_misses",
+    "EventCode": "0x45",
+    "BriefDescription": "L1 DTLB Misses",
+    "UMask": "0xff"
+  },
+  {
+    "EventName": "l2_dtlb_misses",
+    "EventCode": "0x45",
+    "BriefDescription": "L2 DTLB Misses & Data page walks",
+    "UMask": "0xf0"
+  },
+  {
+    "EventName": "all_tlbs_flushed",
+    "EventCode": "0x78",
+    "BriefDescription": "All TLBs Flushed",
+    "UMask": "0xdf"
+  },
+  {
+    "EventName": "uops_dispatched",
+    "EventCode": "0xaa",
+    "BriefDescription": "Micro-ops Dispatched",
+    "UMask": "0x03"
+  },
+  {
+    "EventName": "sse_avx_stalls",
+    "EventCode": "0x0e",
+    "BriefDescription": "Mixed SSE/AVX Stalls",
+    "UMask": "0x0e"
+  },
+  {
+    "EventName": "uops_retired",
+    "EventCode": "0xc1",
+    "BriefDescription": "Micro-ops Retired"
+  },
+  {
+    "MetricName": "all_remote_links_outbound",
+    "BriefDescription": "Approximate: Outbound data bytes for all Remote Links for a node (die)",
+    "MetricExpr": "remote_outbound_data_controller_0 + remote_outbound_data_controller_1 + remote_outbound_data_controller_2 + remote_outbound_data_controller_3",
+    "MetricGroup": "data_fabric",
+    "PerPkg": "1",
+    "ScaleUnit": "3e-5MiB"
+  },
+  {
+    "MetricName": "nps1_die_to_dram",
+    "BriefDescription": "Approximate: Combined DRAM B/bytes of all channels on a NPS1 node (die) (may need --metric-no-group)",
+    "MetricExpr": "dram_channel_data_controller_0 + dram_channel_data_controller_1 + dram_channel_data_controller_2 + dram_channel_data_controller_3 + dram_channel_data_controller_4 + dram_channel_data_controller_5 + dram_channel_data_controller_6 + dram_channel_data_controller_7",
+    "MetricGroup": "data_fabric",
+    "PerPkg": "1",
+    "ScaleUnit": "6.1e-5MiB"
+  }
+]
diff --git a/lib/libpmc/pmu-events/arch/x86/broadwell/bdw-metrics.json b/lib/libpmc/pmu-events/arch/x86/broadwell/bdw-metrics.json
index 45a34ce4fe89..8cdc7c13dc2a 100644
--- a/lib/libpmc/pmu-events/arch/x86/broadwell/bdw-metrics.json
+++ b/lib/libpmc/pmu-events/arch/x86/broadwell/bdw-metrics.json
@@ -297,7 +297,7 @@
     },
     {
         "BriefDescription": "Fraction of cycles spent in Kernel mode",
-        "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC:k / CPU_CLK_UNHALTED.REF_TSC",
+        "MetricExpr": "CPU_CLK_UNHALTED.THREAD:k / CPU_CLK_UNHALTED.THREAD",
         "MetricGroup": "Summary",
         "MetricName": "Kernel_Utilization"
     },
diff --git a/lib/libpmc/pmu-events/arch/x86/broadwellde/bdwde-metrics.json b/lib/libpmc/pmu-events/arch/x86/broadwellde/bdwde-metrics.json
index 961fe4395758..16fd8a7490fc 100644
--- a/lib/libpmc/pmu-events/arch/x86/broadwellde/bdwde-metrics.json
+++ b/lib/libpmc/pmu-events/arch/x86/broadwellde/bdwde-metrics.json
@@ -115,7 +115,7 @@
     },
     {
         "BriefDescription": "Fraction of cycles spent in Kernel mode",
-        "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC:k / CPU_CLK_UNHALTED.REF_TSC",
+        "MetricExpr": "CPU_CLK_UNHALTED.THREAD:k / CPU_CLK_UNHALTED.THREAD",
         "MetricGroup": "Summary",
         "MetricName": "Kernel_Utilization"
     },
diff --git a/lib/libpmc/pmu-events/arch/x86/broadwellx/bdx-metrics.json b/lib/libpmc/pmu-events/arch/x86/broadwellx/bdx-metrics.json
index 746734ce09be..1eb0415fa11a 100644
--- a/lib/libpmc/pmu-events/arch/x86/broadwellx/bdx-metrics.json
+++ b/lib/libpmc/pmu-events/arch/x86/broadwellx/bdx-metrics.json
@@ -297,7 +297,7 @@
     },
     {
         "BriefDescription": "Fraction of cycles spent in Kernel mode",
-        "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC:k / CPU_CLK_UNHALTED.REF_TSC",
+        "MetricExpr": "CPU_CLK_UNHALTED.THREAD:k / CPU_CLK_UNHALTED.THREAD",
         "MetricGroup": "Summary",
         "MetricName": "Kernel_Utilization"
     },
diff --git a/lib/libpmc/pmu-events/arch/x86/cascadelakex/cache.json b/lib/libpmc/pmu-events/arch/x86/cascadelakex/cache.json
index 3fba310a5012..ffafb9f284d2 100644
--- a/lib/libpmc/pmu-events/arch/x86/cascadelakex/cache.json
+++ b/lib/libpmc/pmu-events/arch/x86/cascadelakex/cache.json
@@ -1,61 +1,125 @@
 [
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
+        "BriefDescription": "L1D data line replacements",
         "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
-        "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0400028000",
-        "Offcore": "1",
-        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
-        "SampleAfterValue": "100003",
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
+        "EventCode": "0x51",
+        "EventName": "L1D.REPLACEMENT",
+        "PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
+        "SampleAfterValue": "2000003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
+        "BriefDescription": "Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch.",
         "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
-        "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0100400002",
-        "Offcore": "1",
-        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
-        "SampleAfterValue": "100003",
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
+        "EventCode": "0x48",
+        "EventName": "L1D_PEND_MISS.FB_FULL",
+        "PublicDescription": "Number of times a request needed a FB (Fill Buffer) entry but there was no entry available for it. A request includes cacheable/uncacheable demands that are load, store or SW prefetch instructions.",
+        "SampleAfterValue": "2000003",
+        "UMask": "0x2"
+    },
+    {
+        "BriefDescription": "L1D miss outstandings duration in cycles",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
+        "EventCode": "0x48",
+        "EventName": "L1D_PEND_MISS.PENDING",
+        "PublicDescription": "Counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch.Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",
+        "SampleAfterValue": "2000003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE",
+        "BriefDescription": "Cycles with L1D load Misses outstanding.",
         "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE",
-        "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x00803C0004",
-        "Offcore": "1",
-        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
-        "SampleAfterValue": "100003",
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
+        "CounterMask": "1",
+        "EventCode": "0x48",
+        "EventName": "L1D_PEND_MISS.PENDING_CYCLES",
+        "PublicDescription": "Counts duration of L1D miss outstanding in cycles.",
+        "SampleAfterValue": "2000003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP",
+        "AnyThread": "1",
+        "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
         "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP",
-        "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x3F80200491",
-        "Offcore": "1",
-        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
+        "CounterMask": "1",
+        "EventCode": "0x48",
+        "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
+        "SampleAfterValue": "2000003",
+        "UMask": "0x1"
+    },
+    {
+        "BriefDescription": "L2 cache lines filling L2",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
+        "EventCode": "0xF1",
+        "EventName": "L2_LINES_IN.ALL",
+        "PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover rejects.",
         "SampleAfterValue": "100003",
+        "UMask": "0x1f"
+    },
+    {
+        "BriefDescription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines can be either in modified state or clean state. Modified lines may either be written back to L3 or directly written to memory and not allocated in L3.  Clean lines may either be allocated in L3 or dropped",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
+        "EventCode": "0xF2",
+        "EventName": "L2_LINES_OUT.NON_SILENT",
+        "PublicDescription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines can be either in modified state or clean state. Modified lines may either be written back to L3 or directly written to memory and not allocated in L3.  Clean lines may either be allocated in L3 or dropped.",
+        "SampleAfterValue": "200003",
+        "UMask": "0x2"
+    },
+    {
+        "BriefDescription": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared state. A non-threaded event.",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
+        "EventCode": "0xF2",
+        "EventName": "L2_LINES_OUT.SILENT",
+        "SampleAfterValue": "200003",
         "UMask": "0x1"
     },
     {
+        "BriefDescription": "Counts the number of lines that have been hardware prefetched but not used and now evicted by L2 cache",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
+        "EventCode": "0xF2",
+        "EventName": "L2_LINES_OUT.USELESS_HWPF",
+        "SampleAfterValue": "200003",
+        "UMask": "0x4"
+    },
+    {
+        "BriefDescription": "This event is deprecated. Refer to new event L2_LINES_OUT.USELESS_HWPF",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
+        "Deprecated": "1",
+        "EventCode": "0xF2",
+        "EventName": "L2_LINES_OUT.USELESS_PREF",
+        "SampleAfterValue": "200003",
+        "UMask": "0x4"
+    },
+    {
+        "BriefDescription": "L2 code requests",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
+        "EventCode": "0x24",
+        "EventName": "L2_RQSTS.ALL_CODE_RD",
+        "PublicDescription": "Counts the total number of L2 code requests.",
+        "SampleAfterValue": "200003",
+        "UMask": "0xe4"
+    },
+    {
+        "BriefDescription": "Demand Data Read requests",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
+        "EventCode": "0x24",
+        "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
+        "PublicDescription": "Counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.",
+        "SampleAfterValue": "200003",
+        "UMask": "0xe1"
+    },
+    {
         "BriefDescription": "Demand requests that miss L2 cache",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3,4,5,6,7",
@@ -66,34 +130,427 @@
         "UMask": "0x27"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP",
+        "BriefDescription": "Demand requests to L2 cache",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
+        "EventCode": "0x24",
+        "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES",
+        "PublicDescription": "Demand requests to L2 cache.",
+        "SampleAfterValue": "200003",
+        "UMask": "0xe7"
+    },
+    {
+        "BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
+        "EventCode": "0x24",
+        "EventName": "L2_RQSTS.ALL_PF",
+        "PublicDescription": "Counts the total number of requests from the L2 hardware prefetchers.",
+        "SampleAfterValue": "200003",
+        "UMask": "0xf8"
+    },
+    {
+        "BriefDescription": "RFO requests to L2 cache",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
+        "EventCode": "0x24",
+        "EventName": "L2_RQSTS.ALL_RFO",
+        "PublicDescription": "Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.",
+        "SampleAfterValue": "200003",
+        "UMask": "0xe2"
+    },
+    {
+        "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
+        "EventCode": "0x24",
+        "EventName": "L2_RQSTS.CODE_RD_HIT",
+        "PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.",
+        "SampleAfterValue": "200003",
+        "UMask": "0xc4"
+    },
+    {
+        "BriefDescription": "L2 cache misses when fetching instructions",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
+        "EventCode": "0x24",
+        "EventName": "L2_RQSTS.CODE_RD_MISS",
+        "PublicDescription": "Counts L2 cache misses when fetching instructions.",
+        "SampleAfterValue": "200003",
+        "UMask": "0x24"
+    },
+    {
+        "BriefDescription": "Demand Data Read requests that hit L2 cache",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
+        "EventCode": "0x24",
+        "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
+        "PublicDescription": "Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache",
+        "SampleAfterValue": "200003",
+        "UMask": "0xc1"
+    },
+    {
+        "BriefDescription": "Demand Data Read miss L2, no rejects",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
+        "EventCode": "0x24",
+        "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
+        "PublicDescription": "Counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.",
+        "SampleAfterValue": "200003",
+        "UMask": "0x21"
+    },
+    {
+        "BriefDescription": "All requests that miss L2 cache",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
+        "EventCode": "0x24",
+        "EventName": "L2_RQSTS.MISS",
+        "PublicDescription": "All requests that miss L2 cache.",
+        "SampleAfterValue": "200003",
+        "UMask": "0x3f"
+    },
+    {
+        "BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
+        "EventCode": "0x24",
+        "EventName": "L2_RQSTS.PF_HIT",
+        "PublicDescription": "Counts requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache.",
+        "SampleAfterValue": "200003",
+        "UMask": "0xd8"
+    },
+    {
+        "BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cache",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
+        "EventCode": "0x24",
+        "EventName": "L2_RQSTS.PF_MISS",
+        "PublicDescription": "Counts requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cache.",
+        "SampleAfterValue": "200003",
+        "UMask": "0x38"
+    },
+    {
+        "BriefDescription": "All L2 requests",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
+        "EventCode": "0x24",
+        "EventName": "L2_RQSTS.REFERENCES",
+        "PublicDescription": "All L2 requests.",
+        "SampleAfterValue": "200003",
+        "UMask": "0xff"
+    },
+    {
+        "BriefDescription": "RFO requests that hit L2 cache",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
+        "EventCode": "0x24",
+        "EventName": "L2_RQSTS.RFO_HIT",
+        "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.",
+        "SampleAfterValue": "200003",
+        "UMask": "0xc2"
+    },
+    {
+        "BriefDescription": "RFO requests that miss L2 cache",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
+        "EventCode": "0x24",
+        "EventName": "L2_RQSTS.RFO_MISS",
+        "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.",
+        "SampleAfterValue": "200003",
+        "UMask": "0x22"
+    },
+    {
+        "BriefDescription": "L2 writebacks that access L2 cache",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
+        "EventCode": "0xF0",
+        "EventName": "L2_TRANS.L2_WB",
+        "PublicDescription": "Counts L2 writebacks that access L2 cache.",
+        "SampleAfterValue": "200003",
+        "UMask": "0x40"
+    },
+    {
+        "BriefDescription": "Core-originated cacheable demand requests missed L3",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
+        "Errata": "SKL057",
+        "EventCode": "0x2E",
+        "EventName": "LONGEST_LAT_CACHE.MISS",
+        "PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches from L1 and L2. It does not include all misses to the L3.",
+        "SampleAfterValue": "100003",
+        "UMask": "0x41"
+    },
+    {
+        "BriefDescription": "Core-originated cacheable demand requests that refer to L3",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
+        "Errata": "SKL057",
+        "EventCode": "0x2E",
+        "EventName": "LONGEST_LAT_CACHE.REFERENCE",
+        "PublicDescription": "Counts core-originated cacheable requests to the  L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches from L1 and L2.  It does not include all accesses to the L3.",
+        "SampleAfterValue": "100003",
+        "UMask": "0x4f"
+    },
+    {
+        "BriefDescription": "All retired load instructions.",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP",
-        "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x3F80040491",
-        "Offcore": "1",
-        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+        "Data_LA": "1",
+        "EventCode": "0xD0",
+        "EventName": "MEM_INST_RETIRED.ALL_LOADS",
+        "PEBS": "1",
+        "SampleAfterValue": "2000003",
+        "UMask": "0x81"
+    },
+    {
+        "BriefDescription": "All retired store instructions.",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3",
+        "Data_LA": "1",
+        "EventCode": "0xD0",
+        "EventName": "MEM_INST_RETIRED.ALL_STORES",
+        "L1_Hit_Indication": "1",
+        "PEBS": "1",
+        "SampleAfterValue": "2000003",
+        "UMask": "0x82"
+    },
+    {
+        "BriefDescription": "Retired load instructions with locked access.",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3",
+        "Data_LA": "1",
+        "EventCode": "0xD0",
+        "EventName": "MEM_INST_RETIRED.LOCK_LOADS",
+        "PEBS": "1",
+        "SampleAfterValue": "100007",
+        "UMask": "0x21"
+    },
+    {
+        "BriefDescription": "Retired load instructions that split across a cacheline boundary.",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3",
+        "Data_LA": "1",
+        "EventCode": "0xD0",
+        "EventName": "MEM_INST_RETIRED.SPLIT_LOADS",
+        "PEBS": "1",
+        "PublicDescription": "Counts retired load instructions that split across a cacheline boundary.",
         "SampleAfterValue": "100003",
+        "UMask": "0x41"
+    },
+    {
+        "BriefDescription": "Retired store instructions that split across a cacheline boundary.",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3",
+        "Data_LA": "1",
+        "EventCode": "0xD0",
+        "EventName": "MEM_INST_RETIRED.SPLIT_STORES",
+        "L1_Hit_Indication": "1",
+        "PEBS": "1",
+        "PublicDescription": "Counts retired store instructions that split across a cacheline boundary.",
+        "SampleAfterValue": "100003",
+        "UMask": "0x42"
+    },
+    {
+        "BriefDescription": "Retired load instructions that miss the STLB.",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3",
+        "Data_LA": "1",
+        "EventCode": "0xD0",
+        "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS",
+        "PEBS": "1",
+        "SampleAfterValue": "100003",
+        "UMask": "0x11"
+    },
+    {
+        "BriefDescription": "Retired store instructions that miss the STLB.",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3",
+        "Data_LA": "1",
+        "EventCode": "0xD0",
+        "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES",
+        "L1_Hit_Indication": "1",
+        "PEBS": "1",
+        "SampleAfterValue": "100003",
+        "UMask": "0x12"
+    },
+    {
+        "BriefDescription": "Retired load instructions which data sources were L3 and cross-core snoop hits in on-pkg core cache",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3",
+        "Data_LA": "1",
+        "EventCode": "0xD2",
+        "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT",
+        "PEBS": "1",
+        "PublicDescription": "Retired load instructions which data sources were L3 and cross-core snoop hits in on-pkg core cache.",
+        "SampleAfterValue": "20011",
+        "UMask": "0x2"
+    },
+    {
+        "BriefDescription": "Retired load instructions which data sources were HitM responses from shared L3",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3",
+        "Data_LA": "1",
+        "EventCode": "0xD2",
+        "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM",
+        "PEBS": "1",
+        "PublicDescription": "Retired load instructions which data sources were HitM responses from shared L3.",
+        "SampleAfterValue": "20011",
+        "UMask": "0x4"
+    },
+    {
+        "BriefDescription": "Retired load instructions which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3",
+        "Data_LA": "1",
+        "EventCode": "0xD2",
+        "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS",
+        "PEBS": "1",
+        "SampleAfterValue": "20011",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_MISS",
+        "BriefDescription": "Retired load instructions which data sources were hits in L3 without snoops required",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_M.SNOOP_MISS",
-        "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0200040010",
-        "Offcore": "1",
-        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+        "Data_LA": "1",
+        "EventCode": "0xD2",
+        "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE",
+        "PEBS": "1",
+        "PublicDescription": "Retired load instructions which data sources were hits in L3 without snoops required.",
         "SampleAfterValue": "100003",
+        "UMask": "0x8"
+    },
+    {
+        "BriefDescription": "Retired load instructions which data sources missed L3 but serviced from local dram",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3",
+        "Data_LA": "1",
+        "EventCode": "0xD3",
+        "EventName": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM",
+        "PEBS": "1",
+        "PublicDescription": "Retired load instructions which data sources missed L3 but serviced from local DRAM.",
+        "SampleAfterValue": "100007",
         "UMask": "0x1"
     },
     {
+        "BriefDescription": "Retired load instructions which data sources missed L3 but serviced from remote dram",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3",
+        "Data_LA": "1",
+        "EventCode": "0xD3",
+        "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM",
+        "PEBS": "1",
+        "SampleAfterValue": "100007",
+        "UMask": "0x2"
+    },
+    {
+        "BriefDescription": "Retired load instructions whose data sources was forwarded from a remote cache",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3",
+        "Data_LA": "1",
+        "EventCode": "0xD3",
+        "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD",
+        "PublicDescription": "Retired load instructions whose data sources was forwarded from a remote cache.",
+        "SampleAfterValue": "100007",
+        "UMask": "0x8"
+    },
+    {
+        "BriefDescription": "Retired load instructions whose data sources was remote HITM",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3",
+        "Data_LA": "1",
+        "EventCode": "0xD3",
+        "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM",
+        "PEBS": "1",
+        "PublicDescription": "Retired load instructions whose data sources was remote HITM.",
+        "SampleAfterValue": "100007",
+        "UMask": "0x4"
+    },
+    {
+        "BriefDescription": "Retired load instructions with remote Intel Optane DC persistent memory as the data source where the data request missed all caches. Precise event.",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3",
+        "Data_LA": "1",
+        "ELLC": "1",
+        "EventCode": "0xD3",
+        "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM",
+        "PEBS": "1",
+        "PublicDescription": "Counts retired load instructions with remote Intel Optane DC persistent memory as the data source and the data request missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode). Precise event",
+        "SampleAfterValue": "100007",
+        "UMask": "0x10"
+    },
+    {
+        "BriefDescription": "Retired instructions with at least 1 uncacheable load or lock.",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3",
+        "Data_LA": "1",
+        "EventCode": "0xD4",
+        "EventName": "MEM_LOAD_MISC_RETIRED.UC",
+        "PEBS": "1",
+        "SampleAfterValue": "100007",
+        "UMask": "0x4"
+    },
+    {
+        "BriefDescription": "Retired load instructions which data sources were load missed L1 but hit FB due to preceding miss to the same cache line with data not ready",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3",
+        "Data_LA": "1",
+        "EventCode": "0xD1",
+        "EventName": "MEM_LOAD_RETIRED.FB_HIT",
+        "PEBS": "1",
+        "PublicDescription": "Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready.",
+        "SampleAfterValue": "100007",
+        "UMask": "0x40"
+    },
+    {
+        "BriefDescription": "Retired load instructions with L1 cache hits as data sources",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3",
+        "Data_LA": "1",
+        "EventCode": "0xD1",
+        "EventName": "MEM_LOAD_RETIRED.L1_HIT",
+        "PEBS": "1",
+        "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source.",
+        "SampleAfterValue": "2000003",
+        "UMask": "0x1"
+    },
+    {
+        "BriefDescription": "Retired load instructions missed L1 cache as data sources",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3",
+        "Data_LA": "1",
+        "EventCode": "0xD1",
+        "EventName": "MEM_LOAD_RETIRED.L1_MISS",
+        "PEBS": "1",
+        "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L1 cache.",
+        "SampleAfterValue": "100003",
+        "UMask": "0x8"
+    },
+    {
+        "BriefDescription": "Retired load instructions with L2 cache hits as data sources",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3",
+        "Data_LA": "1",
+        "EventCode": "0xD1",
+        "EventName": "MEM_LOAD_RETIRED.L2_HIT",
+        "PEBS": "1",
+        "PublicDescription": "Retired load instructions with L2 cache hits as data sources.",
+        "SampleAfterValue": "100003",
+        "UMask": "0x2"
+    },
+    {
+        "BriefDescription": "Retired load instructions missed L2 cache as data sources",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3",
+        "Data_LA": "1",
+        "EventCode": "0xD1",
+        "EventName": "MEM_LOAD_RETIRED.L2_MISS",
+        "PEBS": "1",
+        "PublicDescription": "Retired load instructions missed L2 cache as data sources.",
+        "SampleAfterValue": "50021",
+        "UMask": "0x10"
+    },
+    {
         "BriefDescription": "Retired load instructions with L3 cache hits as data sources",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
@@ -106,2157 +563,2121 @@
         "UMask": "0x4"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
+        "BriefDescription": "Retired load instructions missed L3 cache as data sources",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
-        "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x3F80400001",
-        "Offcore": "1",
-        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+        "Data_LA": "1",
+        "EventCode": "0xD1",
+        "EventName": "MEM_LOAD_RETIRED.L3_MISS",
+        "PEBS": "1",
+        "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L3 cache.",
+        "SampleAfterValue": "100007",
+        "UMask": "0x20"
+    },
+    {
+        "BriefDescription": "Retired load instructions with local Intel Optane DC persistent memory as the data source where the data request missed all caches. Precise event.",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3",
+        "Data_LA": "1",
+        "ELLC": "1",
+        "EventCode": "0xD1",
+        "EventName": "MEM_LOAD_RETIRED.LOCAL_PMM",
+        "PEBS": "1",
+        "PublicDescription": "Counts retired load instructions with local Intel Optane DC persistent memory as the data source and the data request missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode). Precise event",
+        "SampleAfterValue": "100003",
+        "UMask": "0x80"
+    },
+    {
+        "BriefDescription": "Demand and prefetch data reads",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
+        "EventCode": "0xB0",
+        "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
+        "PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.",
+        "SampleAfterValue": "100003",
+        "UMask": "0x8"
+    },
+    {
+        "BriefDescription": "Any memory transaction that reached the SQ.",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
+        "EventCode": "0xB0",
+        "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS",
+        "PublicDescription": "Counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, etc..",
+        "SampleAfterValue": "100003",
+        "UMask": "0x80"
+    },
+    {
+        "BriefDescription": "Cacheable and noncachaeble code read requests",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
+        "EventCode": "0xB0",
+        "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
+        "PublicDescription": "Counts both cacheable and non-cacheable code read requests.",
+        "SampleAfterValue": "100003",
+        "UMask": "0x2"
+    },
+    {
+        "BriefDescription": "Demand Data Read requests sent to uncore",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
+        "EventCode": "0xB0",
+        "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
+        "PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
+        "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
         "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
-        "Deprecated": "1",
-        "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
-        "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x08003C0491",
-        "Offcore": "1",
-        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
+        "EventCode": "0xB0",
+        "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
+        "PublicDescription": "Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.",
         "SampleAfterValue": "100003",
+        "UMask": "0x4"
+    },
+    {
+        "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
+        "EventCode": "0xB2",
+        "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
+        "PublicDescription": "Counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.Note: Writeback pending FIFO has six entries.",
+        "SampleAfterValue": "2000003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "L2 writebacks that access L2 cache",
+        "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3,4,5,6,7",
-        "EventCode": "0xF0",
-        "EventName": "L2_TRANS.L2_WB",
-        "PublicDescription": "Counts L2 writebacks that access L2 cache.",
-        "SampleAfterValue": "200003",
-        "UMask": "0x40"
+        "EventCode": "0x60",
+        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
+        "PublicDescription": "Counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
+        "SampleAfterValue": "2000003",
+        "UMask": "0x8"
     },
     {
-        "BriefDescription": "L2 cache lines filling L2",
+        "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3,4,5,6,7",
-        "EventCode": "0xF1",
-        "EventName": "L2_LINES_IN.ALL",
-        "PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover rejects.",
-        "SampleAfterValue": "100003",
-        "UMask": "0x1f"
+        "CounterMask": "1",
+        "EventCode": "0x60",
+        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
+        "PublicDescription": "Counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
+        "SampleAfterValue": "2000003",
+        "UMask": "0x8"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.SNOOP_NONE",
+        "BriefDescription": "Cycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore.",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
+        "CounterMask": "1",
+        "EventCode": "0x60",
+        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD",
+        "PublicDescription": "Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",
+        "SampleAfterValue": "2000003",
+        "UMask": "0x2"
+    },
+    {
+        "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
+        "CounterMask": "1",
+        "EventCode": "0x60",
+        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
+        "PublicDescription": "Counts cycles when offcore outstanding Demand Data Read transactions are present in the super queue (SQ). A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation).",
+        "SampleAfterValue": "2000003",
+        "UMask": "0x1"
+    },
+    {
+        "BriefDescription": "Cycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore.",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
+        "CounterMask": "1",
+        "EventCode": "0x60",
+        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
+        "PublicDescription": "Counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",
+        "SampleAfterValue": "2000003",
+        "UMask": "0x4"
+    },
+    {
+        "BriefDescription": "Offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle.",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
+        "EventCode": "0x60",
+        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
+        "PublicDescription": "Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",
+        "SampleAfterValue": "2000003",
+        "UMask": "0x2"
+    },
+    {
+        "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
+        "EventCode": "0x60",
+        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
+        "PublicDescription": "Counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS.Note: A prefetch promoted to Demand is counted from the promotion point.",
+        "SampleAfterValue": "2000003",
+        "UMask": "0x1"
+    },
+    {
+        "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
+        "CounterMask": "6",
+        "EventCode": "0x60",
+        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",
+        "SampleAfterValue": "2000003",
+        "UMask": "0x1"
+    },
+    {
+        "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
+        "Counter": "0,1,2,3",
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
+        "EventCode": "0x60",
+        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
+        "PublicDescription": "Counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
+        "SampleAfterValue": "2000003",
+        "UMask": "0x4"
+    },
+    {
+        "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
-        "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_F.SNOOP_NONE",
-        "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0080200002",
-        "Offcore": "1",
+        "EventName": "OFFCORE_RESPONSE",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.ANY_RESPONSE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x08007C0010",
+        "MSRValue": "0x0000010491",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP",
+        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x3F80020004",
+        "MSRValue": "0x3F803C0491",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NONE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NONE",
+        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0080040080",
+        "MSRValue": "0x10003C0491",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x08000807F7",
+        "MSRValue": "0x08003C0491",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared state. A non-threaded event.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
-        "EventCode": "0xF2",
-        "EventName": "L2_LINES_OUT.SILENT",
-        "SampleAfterValue": "200003",
-        "UMask": "0x1"
-    },
-    {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
+        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0100080080",
+        "MSRValue": "0x04003C0491",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.SNOOP_NONE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_S.SNOOP_NONE",
+        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0080100020",
+        "MSRValue": "0x01003C0491",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISS",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISS",
+        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0200080004",
+        "MSRValue": "0x08007C0491",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP",
+        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x3F803C0080",
+        "MSRValue": "0x02003C0491",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOP",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOP",
+        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x3F80200001",
+        "MSRValue": "0x00803C0491",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
+        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x3F80020491",
+        "MSRValue": "0x3F80080491",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0400100001",
+        "MSRValue": "0x1000080491",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED",
+        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0100200004",
+        "MSRValue": "0x0800080491",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x04003C0100",
+        "MSRValue": "0x0400080491",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP",
+        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x3F80100080",
+        "MSRValue": "0x0100080491",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE",
+        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x1000200020",
+        "MSRValue": "0x0200080491",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOP",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_F.ANY_SNOOP",
+        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x3F80200100",
+        "MSRValue": "0x0080080491",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0800040020",
+        "MSRValue": "0x3F80200491",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
+        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x3F80020490",
+        "MSRValue": "0x1000200491",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
+        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0100200490",
+        "MSRValue": "0x0800200491",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.ANY_SNOOP",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.ANY_SNOOP",
+        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x3F80028000",
+        "MSRValue": "0x0400200491",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
+        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x3F804007F7",
+        "MSRValue": "0x0100200491",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_MISS",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_S.SNOOP_MISS",
+        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0200100400",
+        "MSRValue": "0x0200200491",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_MISS",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_MISS",
+        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0200020400",
+        "MSRValue": "0x0080200491",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0800040400",
+        "MSRValue": "0x3F80040491",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "All requests that miss L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
-        "EventCode": "0x24",
-        "EventName": "L2_RQSTS.MISS",
-        "PublicDescription": "All requests that miss L2 cache.",
-        "SampleAfterValue": "200003",
-        "UMask": "0x3f"
-    },
-    {
-        "BriefDescription": "Retired load instructions whose data sources was forwarded from a remote cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
-        "Data_LA": "1",
-        "EventCode": "0xD3",
-        "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD",
-        "PublicDescription": "Retired load instructions whose data sources was forwarded from a remote cache.",
-        "SampleAfterValue": "100007",
-        "UMask": "0x8"
-    },
-    {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
+        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0080400490",
+        "MSRValue": "0x1000040491",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP",
+        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x3F803C0400",
+        "MSRValue": "0x0800040491",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
+        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0100400490",
+        "MSRValue": "0x0400040491",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0400020491",
+        "MSRValue": "0x0100040491",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "Retired load instructions which data sources were L3 and cross-core snoop hits in on-pkg core cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
-        "Data_LA": "1",
-        "EventCode": "0xD2",
-        "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT",
-        "PEBS": "1",
-        "PublicDescription": "Retired load instructions which data sources were L3 and cross-core snoop hits in on-pkg core cache.",
-        "SampleAfterValue": "20011",
-        "UMask": "0x2"
-    },
-    {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP",
+        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x3F80040001",
+        "MSRValue": "0x0200040491",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0400100122",
+        "MSRValue": "0x0080040491",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x08007C0080",
+        "MSRValue": "0x3F80100491",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "Retired load instructions missed L1 cache as data sources",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
-        "Data_LA": "1",
-        "EventCode": "0xD1",
-        "EventName": "MEM_LOAD_RETIRED.L1_MISS",
-        "PEBS": "1",
-        "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L1 cache.",
+        "Deprecated": "1",
+        "EventCode": "0xB7, 0xBB",
+        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
+        "MSRIndex": "0x1a6,0x1a7",
+        "MSRValue": "0x1000100491",
+        "Offcore": "1",
+        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
-        "UMask": "0x8"
+        "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0800108000",
+        "MSRValue": "0x0800100491",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
+        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0100020122",
+        "MSRValue": "0x0400100491",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
+        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0200020080",
+        "MSRValue": "0x0100100491",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP",
+        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x3F80200010",
+        "MSRValue": "0x0200100491",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.SNOOP_NONE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_NONE",
+        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0080100002",
+        "MSRValue": "0x0080100491",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE",
+        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x1000100020",
+        "MSRValue": "0x3F80400491",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
+        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0080400002",
+        "MSRValue": "0x0080400491",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.SNOOP_MISS",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_MISS",
+        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0200048000",
+        "MSRValue": "0x0100400491",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0400080400",
+        "MSRValue": "0x3F80020491",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE",
+        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x1000200122",
+        "MSRValue": "0x1000020491",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
+        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0100040001",
+        "MSRValue": "0x0800020491",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.SNOOP_MISS",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_E.SNOOP_MISS",
+        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0200080122",
+        "MSRValue": "0x0400020491",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0400020122",
+        "MSRValue": "0x0100020491",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0800200122",
+        "MSRValue": "0x0200020491",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "AnyThread": "1",
-        "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
-        "CounterMask": "1",
-        "EventCode": "0x48",
-        "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
-        "SampleAfterValue": "2000003",
-        "UMask": "0x1"
-    },
-    {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0400208000",
+        "MSRValue": "0x0080020491",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.ANY_RESPONSE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x1000100010",
+        "MSRValue": "0x0000010490",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x1000020080",
+        "MSRValue": "0x3F803C0490",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0080100491",
+        "MSRValue": "0x10003C0490",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOP",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_F.ANY_SNOOP",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x3F80200020",
+        "MSRValue": "0x08003C0490",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "Any memory transaction that reached the SQ.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
-        "EventCode": "0xB0",
-        "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS",
-        "PublicDescription": "Counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, etc..",
-        "SampleAfterValue": "100003",
-        "UMask": "0x80"
-    },
-    {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0100200010",
+        "MSRValue": "0x04003C0490",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0100200120",
+        "MSRValue": "0x01003C0490",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0200040120",
+        "MSRValue": "0x08007C0490",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDED",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.NO_SNOOP_NEEDED",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0100048000",
+        "MSRValue": "0x02003C0490",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.HITM_OTHER_CORE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.HITM_OTHER_CORE",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x1000028000",
+        "MSRValue": "0x00803C0490",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CORE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CORE",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x1000200400",
+        "MSRValue": "0x3F80080490",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x04003C0010",
+        "MSRValue": "0x1000080490",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "Retired instructions with at least 1 uncacheable load or lock.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
-        "Data_LA": "1",
-        "EventCode": "0xD4",
-        "EventName": "MEM_LOAD_MISC_RETIRED.UC",
-        "PEBS": "1",
-        "SampleAfterValue": "100007",
-        "UMask": "0x4"
-    },
-    {
-        "BriefDescription": "Retired load instructions with remote Intel\u00ae Optane\u2122 DC persistent memory as the data source where the data request missed all caches. Precise event.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
-        "Data_LA": "1",
-        "ELLC": "1",
-        "EventCode": "0xD3",
-        "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM",
-        "PEBS": "1",
-        "PublicDescription": "Counts retired load instructions with remote Intel\u00ae Optane\u2122 DC persistent memory as the data source and the data request missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode). Precise event",
-        "SampleAfterValue": "100007",
-        "UMask": "0x10"
-    },
-    {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0400080122",
+        "MSRValue": "0x0800080490",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x3F80080400",
+        "MSRValue": "0x0400080490",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.SNOOP_MISS",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_E.SNOOP_MISS",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x02000807F7",
+        "MSRValue": "0x0100080490",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x08007C0490",
+        "MSRValue": "0x0200080490",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0100080002",
+        "MSRValue": "0x0080080490",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0800080010",
+        "MSRValue": "0x3F80200490",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0100400001",
+        "MSRValue": "0x1000200490",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.ANY_RESPONSE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.ANY_RESPONSE",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0000010490",
+        "MSRValue": "0x0800200490",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "Retired load instructions which data sources were hits in L3 without snoops required",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
-        "Data_LA": "1",
-        "EventCode": "0xD2",
-        "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE",
-        "PEBS": "1",
-        "PublicDescription": "Retired load instructions which data sources were hits in L3 without snoops required.",
+        "Deprecated": "1",
+        "EventCode": "0xB7, 0xBB",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
+        "MSRIndex": "0x1a6,0x1a7",
+        "MSRValue": "0x0400200490",
+        "Offcore": "1",
+        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
-        "UMask": "0x8"
+        "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0100400122",
+        "MSRValue": "0x0100200490",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "Demand Data Read requests",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
-        "EventCode": "0x24",
-        "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
-        "PublicDescription": "Counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.",
-        "SampleAfterValue": "200003",
-        "UMask": "0xe1"
-    },
-    {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0400200020",
+        "MSRValue": "0x0200200490",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0200040491",
+        "MSRValue": "0x0080200490",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_NONE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_M.SNOOP_NONE",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0080040010",
+        "MSRValue": "0x3F80040490",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x10003C0001",
+        "MSRValue": "0x1000040490",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.SNOOP_MISS",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_MISS",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0200028000",
+        "MSRValue": "0x0800040490",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "Cycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
-        "CounterMask": "1",
-        "EventCode": "0x60",
-        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
-        "PublicDescription": "Counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",
-        "SampleAfterValue": "2000003",
-        "UMask": "0x4"
-    },
-    {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0100100001",
+        "MSRValue": "0x0400040490",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "Number of cache line split locks sent to uncore.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
-        "EventCode": "0xF4",
-        "EventName": "SQ_MISC.SPLIT_LOCK",
-        "PublicDescription": "Counts the number of cache line split locks sent to the uncore.",
-        "SampleAfterValue": "100003",
-        "UMask": "0x10"
-    },
-    {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.SNOOP_MISS",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_F.SNOOP_MISS",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0200200100",
+        "MSRValue": "0x0100040490",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0800100002",
+        "MSRValue": "0x0200040490",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
-        "EventCode": "0x24",
-        "EventName": "L2_RQSTS.CODE_RD_HIT",
-        "PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.",
-        "SampleAfterValue": "200003",
-        "UMask": "0xc4"
-    },
-    {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x1000200120",
+        "MSRValue": "0x0080040490",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0080020010",
+        "MSRValue": "0x3F80100490",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_S.HITM_OTHER_CORE",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x10001007F7",
+        "MSRValue": "0x1000100490",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0400040122",
+        "MSRValue": "0x0800100490",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0400100010",
+        "MSRValue": "0x0400100490",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.SNOOP_MISS",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_S.SNOOP_MISS",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x02001007F7",
+        "MSRValue": "0x0100100490",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0800020120",
+        "MSRValue": "0x0200100490",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0800040120",
+        "MSRValue": "0x0080100490",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0400040020",
+        "MSRValue": "0x3F80400490",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x08001007F7",
+        "MSRValue": "0x0080400490",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x08003C07F7",
+        "MSRValue": "0x0100400490",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x08007C0004",
+        "MSRValue": "0x3F80020490",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "Retired load instructions which data sources were HitM responses from shared L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
-        "Data_LA": "1",
-        "EventCode": "0xD2",
-        "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM",
-        "PEBS": "1",
-        "PublicDescription": "Retired load instructions which data sources were HitM responses from shared L3.",
-        "SampleAfterValue": "20011",
-        "UMask": "0x4"
-    },
-    {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.SNOOP_NONE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_F.SNOOP_NONE",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0080200020",
+        "MSRValue": "0x1000020490",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0100200080",
+        "MSRValue": "0x0800020490",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0400048000",
+        "MSRValue": "0x0400020490",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "Retired store instructions that split across a cacheline boundary.",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
-        "Data_LA": "1",
-        "EventCode": "0xD0",
-        "EventName": "MEM_INST_RETIRED.SPLIT_STORES",
-        "L1_Hit_Indication": "1",
-        "PEBS": "1",
-        "PublicDescription": "Counts retired store instructions that split across a cacheline boundary.",
+        "Deprecated": "1",
+        "EventCode": "0xB7, 0xBB",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
+        "MSRIndex": "0x1a6,0x1a7",
+        "MSRValue": "0x0100020490",
+        "Offcore": "1",
+        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
-        "UMask": "0x42"
+        "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.ANY_RESPONSE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0000010122",
+        "MSRValue": "0x0200020490",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x1000100120",
+        "MSRValue": "0x0080020490",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.ANY_RESPONSE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.ANY_RESPONSE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0000010002",
+        "MSRValue": "0x0000010120",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x1000020491",
+        "MSRValue": "0x3F803C0120",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0200100120",
+        "MSRValue": "0x10003C0120",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.ANY_RESPONSE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0000010001",
+        "MSRValue": "0x08003C0120",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_NONE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_E.SNOOP_NONE",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0080080400",
+        "MSRValue": "0x04003C0120",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0080400080",
+        "MSRValue": "0x01003C0120",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HITM_OTHER_CORE",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x10003C0122",
+        "MSRValue": "0x08007C0120",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0100400080",
+        "MSRValue": "0x02003C0120",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0800080120",
+        "MSRValue": "0x00803C0120",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0800080001",
+        "MSRValue": "0x3F80080120",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0800100491",
+        "MSRValue": "0x1000080120",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0400100002",
+        "MSRValue": "0x0800080120",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x3F80400100",
+        "MSRValue": "0x0400080120",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONE",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0080080001",
+        "MSRValue": "0x0100080120",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.ANY_RESPONSE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0000010004",
+        "MSRValue": "0x0200080120",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0200100490",
+        "MSRValue": "0x0080080120",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONE",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0080040004",
+        "MSRValue": "0x3F80200120",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0080400020",
+        "MSRValue": "0x1000200120",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.SNOOP_MISS",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_MISS",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x02003C8000",
+        "MSRValue": "0x0800200120",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOP",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOP",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x3F80020100",
+        "MSRValue": "0x0400200120",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0100200020",
+        "MSRValue": "0x0100200120",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x3F80200400",
+        "MSRValue": "0x0200200120",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0080040120",
+        "MSRValue": "0x0080200120",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x04003C0400",
+        "MSRValue": "0x3F80040120",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOP",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_M.ANY_SNOOP",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x3F80040020",
+        "MSRValue": "0x1000040120",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x3F80100120",
+        "MSRValue": "0x0800040120",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x3F80400002",
+        "MSRValue": "0x0400040120",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0400040491",
+        "MSRValue": "0x0100040120",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
-        "EventCode": "0x48",
-        "EventName": "L1D_PEND_MISS.FB_FULL",
-        "PublicDescription": "Number of times a request needed a FB (Fill Buffer) entry but there was no entry available for it. A request includes cacheable/uncacheable demands that are load, store or SW prefetch instructions.",
-        "SampleAfterValue": "2000003",
-        "UMask": "0x2"
-    },
-    {
-        "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
+        "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS",
+        "MSRIndex": "0x1a6,0x1a7",
+        "MSRValue": "0x0200040120",
+        "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NONE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NONE",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0080020020",
+        "MSRValue": "0x0080040120",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_NONE",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x00803C0120",
+        "MSRValue": "0x3F80100120",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0400020010",
+        "MSRValue": "0x1000100120",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x3F80200490",
+        "MSRValue": "0x0800100120",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x08003C0100",
+        "MSRValue": "0x0400100120",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0400040001",
+        "MSRValue": "0x0100100120",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
-        "EventCode": "0xB2",
-        "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
-        "PublicDescription": "Counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.Note: Writeback pending FIFO has six entries.",
-        "SampleAfterValue": "2000003",
-        "UMask": "0x1"
-    },
-    {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.SNOOP_MISS",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_F.SNOOP_MISS",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0200200020",
+        "MSRValue": "0x0200100120",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x1000200490",
+        "MSRValue": "0x0080100120",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.ANY_SNOOP",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x3F803C0100",
+        "MSRValue": "0x3F80400120",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0080400491",
+        "MSRValue": "0x0080400120",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x10000207F7",
+        "MSRValue": "0x0100400120",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0400080120",
+        "MSRValue": "0x3F80020120",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "Retired load instructions missed L2 cache as data sources",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
-        "Data_LA": "1",
-        "EventCode": "0xD1",
-        "EventName": "MEM_LOAD_RETIRED.L2_MISS",
-        "PEBS": "1",
-        "PublicDescription": "Retired load instructions missed L2 cache as data sources.",
-        "SampleAfterValue": "50021",
-        "UMask": "0x10"
-    },
-    {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.SNOOP_MISS",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_MISS",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x02003C0122",
+        "MSRValue": "0x1000020120",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_NONE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_F.SNOOP_NONE",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0080200400",
+        "MSRValue": "0x0800020120",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0100400004",
+        "MSRValue": "0x0400020120",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
@@ -2277,3204 +2698,3038 @@
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0100200100",
+        "MSRValue": "0x0200020120",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_MISS",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.SNOOP_MISS",
+        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0200040080",
+        "MSRValue": "0x0080020120",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.SNOOP_MISS",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.ANY_RESPONSE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_MISS",
+        "EventName": "OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0200088000",
+        "MSRValue": "0x00000107F7",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.SNOOP_NONE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.ANY_SNOOP",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NONE",
+        "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x00803C8000",
+        "MSRValue": "0x3F803C07F7",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
+        "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0100200001",
+        "MSRValue": "0x10003C07F7",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOP",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_E.ANY_SNOOP",
+        "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x3F80080020",
+        "MSRValue": "0x08003C07F7",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
+        "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x3F80400490",
+        "MSRValue": "0x04003C07F7",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
+        "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x3F80400400",
+        "MSRValue": "0x01003C07F7",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
+        "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0100400020",
+        "MSRValue": "0x08007C07F7",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
-        "EventCode": "0x24",
-        "EventName": "L2_RQSTS.PF_MISS",
-        "PublicDescription": "Counts requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cache.",
-        "SampleAfterValue": "200003",
-        "UMask": "0x38"
-    },
-    {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.SNOOP_MISS",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x08000407F7",
+        "MSRValue": "0x02003C07F7",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.SNOOP_NONE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0800200100",
+        "MSRValue": "0x00803C07F7",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.ANY_SNOOP",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP",
+        "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_E.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x3F80080004",
+        "MSRValue": "0x3F800807F7",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_MISS",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_M.SNOOP_MISS",
+        "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_E.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0200040400",
+        "MSRValue": "0x10000807F7",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0400100004",
+        "MSRValue": "0x08000807F7",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_MISS",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.SNOOP_MISS",
+        "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0200080080",
+        "MSRValue": "0x04000807F7",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_M.HITM_OTHER_CORE",
+        "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x10000407F7",
+        "MSRValue": "0x01000807F7",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.SNOOP_MISS",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_READS.SUPPLIER_NONE.SNOOP_NONE",
+        "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_E.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x00800207F7",
+        "MSRValue": "0x02000807F7",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.SNOOP_NONE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_NONE",
+        "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_E.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x00803C0491",
+        "MSRValue": "0x00800807F7",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.ANY_RESPONSE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.ANY_SNOOP",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.ANY_RESPONSE",
+        "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_F.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0000010080",
+        "MSRValue": "0x3F802007F7",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS",
+        "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_F.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0200020122",
+        "MSRValue": "0x10002007F7",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x04003C0122",
+        "MSRValue": "0x08002007F7",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP",
+        "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x3F80080001",
+        "MSRValue": "0x04002007F7",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
+        "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0080020491",
+        "MSRValue": "0x01002007F7",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISS",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.SNOOP_MISS",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISS",
+        "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_F.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0200040001",
+        "MSRValue": "0x02002007F7",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.SNOOP_NONE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
+        "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_F.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x3F80400122",
+        "MSRValue": "0x00802007F7",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.ANY_RESPONSE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.ANY_SNOOP",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.ANY_RESPONSE",
+        "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_M.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0000010020",
+        "MSRValue": "0x3F800407F7",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_M.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x08003C0490",
+        "MSRValue": "0x10000407F7",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
+        "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x1000020020",
+        "MSRValue": "0x08000407F7",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.SNOOP_MISS",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_S.SNOOP_MISS",
+        "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0200100122",
+        "MSRValue": "0x04000407F7",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_NONE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_F.SNOOP_NONE",
+        "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0080200001",
+        "MSRValue": "0x01000407F7",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.SNOOP_MISS",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_M.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0400020080",
+        "MSRValue": "0x02000407F7",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.SNOOP_NONE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
+        "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_M.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0100040010",
+        "MSRValue": "0x00800407F7",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.SNOOP_MISS",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.ANY_SNOOP",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.SNOOP_MISS",
+        "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_S.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0200080100",
+        "MSRValue": "0x3F801007F7",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
+        "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_S.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0080020490",
+        "MSRValue": "0x10001007F7",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x08000207F7",
+        "MSRValue": "0x08001007F7",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "Retired load instructions missed L3 cache as data sources",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3",
-        "Data_LA": "1",
-        "EventCode": "0xD1",
-        "EventName": "MEM_LOAD_RETIRED.L3_MISS",
-        "PEBS": "1",
-        "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L3 cache.",
-        "SampleAfterValue": "100007",
-        "UMask": "0x20"
-    },
-    {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE",
+        "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x1000200100",
+        "MSRValue": "0x04001007F7",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
+        "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0100020002",
+        "MSRValue": "0x01001007F7",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.SNOOP_NONE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.SNOOP_MISS",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NONE",
+        "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_S.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0080028000",
+        "MSRValue": "0x02001007F7",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.SNOOP_NONE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
+        "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_S.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0100020491",
+        "MSRValue": "0x00801007F7",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP",
+        "EventName": "OFFCORE_RESPONSE.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x3F80080120",
+        "MSRValue": "0x3F804007F7",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_MISS",
+        "EventName": "OFFCORE_RESPONSE.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x02003C0120",
+        "MSRValue": "0x00804007F7",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
+        "EventName": "OFFCORE_RESPONSE.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x01003C0010",
+        "MSRValue": "0x01004007F7",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP",
+        "EventName": "OFFCORE_RESPONSE.ALL_READS.SUPPLIER_NONE.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x3F80020020",
+        "MSRValue": "0x3F800207F7",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0800020100",
+        "MSRValue": "0x10000207F7",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "Core-originated cacheable demand requests missed L3",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
-        "Errata": "SKL057",
-        "EventCode": "0x2E",
-        "EventName": "LONGEST_LAT_CACHE.MISS",
-        "PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches from L1 and L2. It does not include all misses to the L3.",
-        "SampleAfterValue": "100003",
-        "UMask": "0x41"
-    },
-    {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE",
+        "EventName": "OFFCORE_RESPONSE.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0080200490",
+        "MSRValue": "0x08000207F7",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_MISS",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_F.SNOOP_MISS",
+        "EventName": "OFFCORE_RESPONSE.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0200200080",
+        "MSRValue": "0x04000207F7",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE",
+        "EventName": "OFFCORE_RESPONSE.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0080080120",
+        "MSRValue": "0x01000207F7",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.SNOOP_MISS",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
+        "EventName": "OFFCORE_RESPONSE.ALL_READS.SUPPLIER_NONE.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x1000020010",
+        "MSRValue": "0x02000207F7",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED",
+        "EventName": "OFFCORE_RESPONSE.ALL_READS.SUPPLIER_NONE.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x01003C0120",
+        "MSRValue": "0x00800207F7",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOOP",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.ANY_RESPONSE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOOP",
+        "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x3F80020400",
+        "MSRValue": "0x0000010122",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.ANY_SNOOP",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP",
+        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x3F80100400",
+        "MSRValue": "0x3F803C0122",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.HITM_OTHER_CORE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.HITM_OTHER_CORE",
+        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x10003C8000",
+        "MSRValue": "0x10003C0122",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x08007C0400",
+        "MSRValue": "0x08003C0122",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE",
+        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x1000040120",
+        "MSRValue": "0x04003C0122",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x08007C0100",
+        "MSRValue": "0x01003C0122",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
+        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0100200002",
+        "MSRValue": "0x08007C0122",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.SNOOP_MISS",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS",
+        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x02003C0490",
+        "MSRValue": "0x02003C0122",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.SNOOP_NONE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.SNOOP_NONE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_F.SNOOP_NONE",
+        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0080200100",
+        "MSRValue": "0x00803C0122",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
+        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_E.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x01004007F7",
+        "MSRValue": "0x3F80080122",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
+        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0100080120",
+        "MSRValue": "0x1000080122",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
-        "EventCode": "0x60",
-        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
-        "PublicDescription": "Counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
-        "SampleAfterValue": "2000003",
-        "UMask": "0x4"
-    },
-    {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x08007C0491",
+        "MSRValue": "0x0800080122",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE",
+        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x1000100100",
+        "MSRValue": "0x0400080122",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
+        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x1000020100",
+        "MSRValue": "0x0100080122",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_NONE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.SNOOP_MISS",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_E.SNOOP_NONE",
+        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_E.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0080080010",
+        "MSRValue": "0x0200080122",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.SNOOP_NONE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
+        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_E.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0080400010",
+        "MSRValue": "0x0080080122",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines can be either in modified state or clean state. Modified lines may either be written back to L3 or directly written to memory and not allocated in L3.  Clean lines may either be allocated in L3 or dropped",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
-        "EventCode": "0xF2",
-        "EventName": "L2_LINES_OUT.NON_SILENT",
-        "PublicDescription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines can be either in modified state or clean state. Modified lines may either be written back to L3 or directly written to memory and not allocated in L3.  Clean lines may either be allocated in L3 or dropped.",
-        "SampleAfterValue": "200003",
-        "UMask": "0x2"
-    },
-    {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
+        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_F.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x1000040010",
+        "MSRValue": "0x3F80200122",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
+        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x00804007F7",
+        "MSRValue": "0x1000200122",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x08007C0020",
+        "MSRValue": "0x0800200122",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0800100100",
+        "MSRValue": "0x0400200122",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "RFO requests that hit L2 cache",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
-        "EventCode": "0x24",
-        "EventName": "L2_RQSTS.RFO_HIT",
-        "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.",
-        "SampleAfterValue": "200003",
-        "UMask": "0xc2"
-    },
-    {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0800100080",
+        "MSRValue": "0x0100200122",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.SNOOP_MISS",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_F.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0400200001",
+        "MSRValue": "0x0200200122",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.SNOOP_NONE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_F.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0400020100",
+        "MSRValue": "0x0080200122",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
-        "Counter": "0,1,2,3",
-        "CounterHTOff": "0,1,2,3,4,5,6,7",
-        "EventCode": "0x60",
-        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
-        "PublicDescription": "Counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
-        "SampleAfterValue": "2000003",
-        "UMask": "0x8"
-    },
-    {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_M.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0400108000",
+        "MSRValue": "0x3F80040122",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.ANY_RESPONSE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE",
+        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x00000107F7",
+        "MSRValue": "0x1000040122",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.ANY_SNOOP",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_E.ANY_SNOOP",
+        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x3F800807F7",
+        "MSRValue": "0x0800040122",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP",
+        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x3F80040004",
+        "MSRValue": "0x0400040122",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
+        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0200020001",
+        "MSRValue": "0x0100040122",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.SNOOP_MISS",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
+        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_M.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0100100122",
+        "MSRValue": "0x0200040122",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.SNOOP_NONE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.SNOOP_NONE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_S.SNOOP_NONE",
+        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_M.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0080100122",
+        "MSRValue": "0x0080040122",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP",
+        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_S.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x3F803C0001",
+        "MSRValue": "0x3F80100122",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOP",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.ANY_SNOOP",
+        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x3F80080002",
+        "MSRValue": "0x1000100122",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP",
+        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x3F80040010",
+        "MSRValue": "0x0800100122",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_MISS",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_F.SNOOP_MISS",
+        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0200200010",
+        "MSRValue": "0x0400100122",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOP",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.ANY_SNOOP",
+        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x3F80100100",
+        "MSRValue": "0x0100100122",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.SNOOP_MISS",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_S.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0800200001",
+        "MSRValue": "0x0200100122",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.SNOOP_NONE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
+        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_S.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0080408000",
+        "MSRValue": "0x0080100122",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_NONE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_M.SNOOP_NONE",
+        "EventName": "OFFCORE_RESPONSE.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0080040400",
+        "MSRValue": "0x3F80400122",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED",
+        "EventName": "OFFCORE_RESPONSE.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0100040400",
+        "MSRValue": "0x0080400122",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0400080491",
+        "MSRValue": "0x0100400122",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE",
+        "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x10003C0491",
+        "MSRValue": "0x3F80020122",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP",
+        "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x3F80200080",
+        "MSRValue": "0x1000020122",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
+        "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0100040122",
+        "MSRValue": "0x0800020122",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.SNOOP_NONE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NONE",
+        "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0080088000",
+        "MSRValue": "0x0400020122",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0400040490",
+        "MSRValue": "0x0100020122",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE",
+        "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x00803C0080",
+        "MSRValue": "0x0200020122",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
+        "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0800100122",
+        "MSRValue": "0x0080020122",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.ANY_RESPONSE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
+        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0100020004",
+        "MSRValue": "0x0000010004",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NONE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NONE",
+        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0080100080",
+        "MSRValue": "0x3F803C0004",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
+        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x1000200080",
+        "MSRValue": "0x10003C0004",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED",
+        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x01003C0002",
+        "MSRValue": "0x08003C0004",
         "Offcore": "1",
         "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
         "SampleAfterValue": "100003",
         "UMask": "0x1"
     },
     {
-        "BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
+        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "Counter": "0,1,2,3",
         "CounterHTOff": "0,1,2,3",
         "Deprecated": "1",
         "EventCode": "0xB7, 0xBB",
-        "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
+        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
         "MSRIndex": "0x1a6,0x1a7",
-        "MSRValue": "0x0400080100",
+        "MSRValue": "0x04003C0004",<