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author | Ruslan Bukin <br@FreeBSD.org> | 2016-11-19 16:00:05 +0000 |
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committer | Ruslan Bukin <br@FreeBSD.org> | 2016-11-19 16:00:05 +0000 |
commit | 57b28934e964b15f1fcd91734c6dbef762222079 (patch) | |
tree | 58e0ae03b52fe6961201a84c439a52691492e82a | |
parent | cbfebd9a6eff0bf8d80fba37b207ca79326ff032 (diff) | |
download | src-57b28934e964b15f1fcd91734c6dbef762222079.tar.gz src-57b28934e964b15f1fcd91734c6dbef762222079.zip |
Add receiver timeout interrupt enable bit implemented in some
system on chips.
Submitted by: kan
Sponsored by: DARPA, AFRL
Notes
Notes:
svn path=/head/; revision=308841
-rw-r--r-- | sys/dev/ic/ns16550.h | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/sys/dev/ic/ns16550.h b/sys/dev/ic/ns16550.h index 3a94d634b4a5..29a73a018619 100644 --- a/sys/dev/ic/ns16550.h +++ b/sys/dev/ic/ns16550.h @@ -45,8 +45,13 @@ #define IER_ETXRDY 0x2 #define IER_ERLS 0x4 #define IER_EMSC 0x8 +/* + * Receive timeout interrupt enable. + * Implemented in Intel XScale, Ingenic XBurst. + */ +#define IER_RXTMOUT 0x10 -#define IER_BITS "\20\1ERXRDY\2ETXRDY\3ERLS\4EMSC" +#define IER_BITS "\20\1ERXRDY\2ETXRDY\3ERLS\4EMSC\5RXTMOUT" #define com_iir 2 /* interrupt identification register (R) */ #define REG_IIR com_iir |