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authorAdrian Chadd <adrian@FreeBSD.org>2025-01-19 01:08:32 +0000
committerAdrian Chadd <adrian@FreeBSD.org>2025-01-22 21:46:57 +0000
commit5f9a2eec337c9cfdbfa800aff8875f5424e847e8 (patch)
tree15a4197813dc4ee3496cf1617f225e2177177ba4
parent40fc36ff2c1d14f8ea7237e8f9487ab2f25de86b (diff)
rtwn: bring the RTL8192EU RF read/write routines in line with rtl8xxxu
The Linux rtl8xxxu driver has more delays in the RF read and write path. It looks like for writes it's ensuring the hardware is out of power save and that the transition has properly occured. And it looks for reads that it wants a delay after some bit setting, likely some shifting into the RF register space is occuring with a bit set/clear to trigger a load. See rtl8xxxu_write_rfreg() and rtl8xxxu_read_rfreg() for more information. Differential Revision: https://reviews.freebsd.org/D48512 Obtained from: Linux rtl8xxxu
-rw-r--r--sys/dev/rtwn/rtl8192e/r92e_rf.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/sys/dev/rtwn/rtl8192e/r92e_rf.c b/sys/dev/rtwn/rtl8192e/r92e_rf.c
index 8e05a827262b..478945d13c85 100644
--- a/sys/dev/rtwn/rtl8192e/r92e_rf.c
+++ b/sys/dev/rtwn/rtl8192e/r92e_rf.c
@@ -64,7 +64,9 @@ r92e_rf_read(struct rtwn_softc *sc, int chain, uint8_t addr)
RW(val, R92C_HSSI_PARAM2_READ_ADDR, addr) &
~R92C_HSSI_PARAM2_READ_EDGE);
+ rtwn_delay(sc, 10);
rtwn_bb_setbits(sc, R92C_HSSI_PARAM2(0), R92C_HSSI_PARAM2_READ_EDGE, 0);
+ rtwn_delay(sc, 100);
rtwn_bb_setbits(sc, R92C_HSSI_PARAM2(0), 0, R92C_HSSI_PARAM2_READ_EDGE);
rtwn_delay(sc, 20);
@@ -82,5 +84,6 @@ r92e_rf_write(struct rtwn_softc *sc, int chain, uint8_t addr, uint32_t val)
rtwn_bb_setbits(sc, 0x818, 0x20000, 0);
rtwn_bb_write(sc, R92C_LSSI_PARAM(chain),
SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val));
+ rtwn_delay(sc, 1);
rtwn_bb_setbits(sc, 0x818, 0, 0x20000);
}