diff options
| author | Olivier Certner <olce@FreeBSD.org> | 2026-02-09 17:45:07 +0000 |
|---|---|---|
| committer | Olivier Certner <olce@FreeBSD.org> | 2026-02-20 10:12:53 +0000 |
| commit | 80d32a6b1d73e0c81303417fa280ac74ef1f417a (patch) | |
| tree | 229a538706542615d509c647e3e3724cfa353513 | |
| parent | b69a396de211feb1dcfe6a7e95d1b23ae53f916a (diff) | |
hwpstate_amd(4): CPPC: Switch the default to maximum performance
Set controls to maximum performance to avoid regressions now that CPPC
is activated by default and to match what the P-state support does.
Relnotes: yes
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D55253
| -rw-r--r-- | sys/x86/cpufreq/hwpstate_amd.c | 18 |
1 files changed, 10 insertions, 8 deletions
diff --git a/sys/x86/cpufreq/hwpstate_amd.c b/sys/x86/cpufreq/hwpstate_amd.c index 72fe6dbf6014..a1586f58166a 100644 --- a/sys/x86/cpufreq/hwpstate_amd.c +++ b/sys/x86/cpufreq/hwpstate_amd.c @@ -799,14 +799,6 @@ enable_cppc_cb(void *args) data->request = sc->cppc.request; /* - * In Intel's reference manual, the default value of EPP is 0x80u which - * is the balanced mode. For consistency, we set the same value in AMD's - * CPPC driver. - */ - SET_BITS_VALUE(data->request, AMD_CPPC_REQUEST_EPP_BITS, 0x80); - /* Enable autonomous mode by setting desired performance to 0. */ - SET_BITS_VALUE(data->request, AMD_CPPC_REQUEST_DES_PERF_BITS, 0); - /* * Assuming reading MSR_AMD_CPPC_CAPS_1 succeeded, if it stays at its * reset value (0) before CPPC activation (not supposed to happen, but * happens in the field), we use reasonable default values that are @@ -834,6 +826,16 @@ enable_cppc_cb(void *args) lowest_perf); SET_BITS_VALUE(data->request, AMD_CPPC_REQUEST_MAX_PERF_BITS, highest_perf); + /* + * Set controls to maximum performance to avoid regressions now that + * CPPC is activated by default and to match what the P-state support + * does. + */ + SET_BITS_VALUE(data->request, AMD_CPPC_REQUEST_EPP_BITS, 0); + /* 0 in "Desired Performance" is autonomous mode. */ + MPASS(highest_perf != 0); + SET_BITS_VALUE(data->request, AMD_CPPC_REQUEST_DES_PERF_BITS, + highest_perf); error = wrmsr_safe(MSR_AMD_CPPC_REQUEST, data->request); if (error != 0) |