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authorHans Petter Selasky <hselasky@FreeBSD.org>2020-09-19 22:37:45 +0000
committerHans Petter Selasky <hselasky@FreeBSD.org>2020-09-19 22:37:45 +0000
commita29c0348f0653c25adb65e340e6f5a7edc86b8a2 (patch)
tree348db44f07c1ce6f9eaf45ade78a15680917d7e9
parent68d7185b6495e194e399289edc479ab85e5e4f3f (diff)
downloadsrc-a29c0348f0653c25adb65e340e6f5a7edc86b8a2.tar.gz
src-a29c0348f0653c25adb65e340e6f5a7edc86b8a2.zip
Fix for use of the XHCI driver on Cortex-A72 by adding a missing cache
flush operation before writing to the XHCI_ERSTBA_LO/HI register(s). PR: 237666 Discussed with: Mark Millard <marklmi@yahoo.com> MFC after: 1 week Sponsored by: Mellanox Technologies // Nvidia
Notes
Notes: svn path=/head/; revision=365918
-rw-r--r--sys/dev/usb/controller/xhci.c13
1 files changed, 13 insertions, 0 deletions
diff --git a/sys/dev/usb/controller/xhci.c b/sys/dev/usb/controller/xhci.c
index c37506030599..aba990532627 100644
--- a/sys/dev/usb/controller/xhci.c
+++ b/sys/dev/usb/controller/xhci.c
@@ -432,6 +432,19 @@ xhci_start_controller(struct xhci_softc *sc)
phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr);
phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS);
+ /*
+ * PR 237666:
+ *
+ * According to the XHCI specification, the XWRITE4's to
+ * XHCI_ERSTBA_LO and _HI lead to the XHCI to copy the
+ * qwEvrsTablePtr and dwEvrsTableSize values above at that
+ * time, as the XHCI initializes its event ring support. This
+ * is before the event ring starts to pay attention to the
+ * RUN/STOP bit. Thus, make sure the values are observable to
+ * the XHCI before that point.
+ */
+ usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc);
+
DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr);
XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);