diff options
| author | Ruslan Bukin <br@FreeBSD.org> | 2018-06-12 16:19:27 +0000 |
|---|---|---|
| committer | Ruslan Bukin <br@FreeBSD.org> | 2018-06-12 16:19:27 +0000 |
| commit | a9063ba1d79492a55b80a19409ee8e1dfb33bcc2 (patch) | |
| tree | 435da6c51f270df9a27e769c06a7d1aad93009ce | |
| parent | 0c38b2d37c472a119a050203ebac022ab744ed10 (diff) | |
| download | src-a9063ba1d79492a55b80a19409ee8e1dfb33bcc2.tar.gz src-a9063ba1d79492a55b80a19409ee8e1dfb33bcc2.zip | |
Align virtual addressing entries.
This is required due to C-compressed ISA extension option being turned on.
This fixes SMP operation in QEMU.
Sponsored by: DARPA, AFRL
Notes
Notes:
svn path=/head/; revision=335000
| -rw-r--r-- | sys/riscv/riscv/locore.S | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/sys/riscv/riscv/locore.S b/sys/riscv/riscv/locore.S index 84905084a066..fb39402267e3 100644 --- a/sys/riscv/riscv/locore.S +++ b/sys/riscv/riscv/locore.S @@ -156,6 +156,8 @@ _start: or s2, s2, t0 sfence.vma csrw sptbr, s2 + + .align 2 va: /* Setup supervisor trap vector */ @@ -284,6 +286,8 @@ ENTRY(mpentry) or s2, s2, t0 sfence.vma csrw sptbr, s2 + + .align 2 mpva: /* Setup supervisor trap vector */ la t0, cpu_exception_handler |