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authorKonstantin Belousov <konstantinb@nvidia.com>2021-04-26 22:38:46 +0000
committerKonstantin Belousov <kib@FreeBSD.org>2021-07-12 09:34:39 +0000
commitb1277d42d718cd42d04d39fa2d61873655e909b3 (patch)
treeb18e0b3944b377a28d0de1d12712974acb39addf
parent2f7ce2326f9486e90cda2f0129331e1ab3694252 (diff)
downloadsrc-b1277d42d718cd42d04d39fa2d61873655e909b3.tar.gz
src-b1277d42d718cd42d04d39fa2d61873655e909b3.zip
mlx5en: add ASCII art providing an overview of flow tables organization
Reviewed by: hselasky Sponsored by: Mellanox Technologies/NVidia Networking MFC after: 1 week
-rw-r--r--sys/dev/mlx5/mlx5_en/mlx5_en_flow_table.c29
1 files changed, 29 insertions, 0 deletions
diff --git a/sys/dev/mlx5/mlx5_en/mlx5_en_flow_table.c b/sys/dev/mlx5/mlx5_en/mlx5_en_flow_table.c
index cdfe19d910d1..54fbe8e057cc 100644
--- a/sys/dev/mlx5/mlx5_en/mlx5_en_flow_table.c
+++ b/sys/dev/mlx5/mlx5_en/mlx5_en_flow_table.c
@@ -31,6 +31,35 @@
#include <dev/mlx5/fs.h>
#include <dev/mlx5/mpfs.h>
+/*
+ * The flow tables with rules define the packet processing on receive.
+ * Currently, the following structure is set up to handle different offloads
+ * like VLAN decapsulation, packet classification, RSS hashing, VxLAN checksum
+ * offloading:
+ *
+ *
+ * +=========+ +=========+ +=================+
+ * |VLAN ft: | |VxLAN | |VxLAN Main |
+ * |CTAG/STAG|------>| VNI|----->|Inner Proto Match|=====> Inner TIR n
+ * |VID/noVID|/ |Catch-all|\ | |
+ * +=========+ +=========+| +=================+
+ * |
+ * |
+ * |
+ * v
+ * +=================+
+ * |Main |
+ * |Outer Proto Match|=====> TIR n
+ * | |
+ * +=================+
+ *
+ * The path through flow rules directs each packet into an appropriate TIR,
+ * according to the:
+ * - VLAN encapsulation
+ * - Outer protocol
+ * - Presence of inner protocol
+ */
+
#define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v)
enum {