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| author | Jose Luis Duran <jlduran@gmail.com> | 2021-05-02 21:20:25 +0000 |
|---|---|---|
| committer | Konstantin Belousov <kib@FreeBSD.org> | 2021-05-10 00:50:08 +0000 |
| commit | b316c016e1958a8274133fdefc1251329beb8b42 (patch) | |
| tree | b30c494f685ceb14df975ef562936528ad978c12 | |
| parent | 2fb889b52071868e1da08251cce93a9d42edbb7e (diff) | |
| download | src-b316c016e1958a8274133fdefc1251329beb8b42.tar.gz src-b316c016e1958a8274133fdefc1251329beb8b42.zip | |
Add Apollo Lake SIO/LPSS UARTs PCI IDs
PR: 255556
(cherry picked from commit 8f1562430fbb83f6cedff6450e1aa1b593e3d7e7)
| -rw-r--r-- | sys/dev/uart/uart_bus_pci.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/sys/dev/uart/uart_bus_pci.c b/sys/dev/uart/uart_bus_pci.c index 123ee3e26829..707b82dc078b 100644 --- a/sys/dev/uart/uart_bus_pci.c +++ b/sys/dev/uart/uart_bus_pci.c @@ -147,6 +147,14 @@ static const struct pci_id pci_ns8250_ids[] = { { 0x8086, 0x2e17, 0xffff, 0, "4 Series Chipset Serial KT Controller", 0x10 }, { 0x8086, 0x3b67, 0xffff, 0, "5 Series/3400 Series Chipset KT Controller", 0x10 }, +{ 0x8086, 0x5abc, 0xffff, 0, "Intel Apollo Lake SIO/LPSS UART 0", 0x10, + 24 * DEFAULT_RCLK, 2 }, +{ 0x8086, 0x5abe, 0xffff, 0, "Intel Apollo Lake SIO/LPSS UART 1", 0x10, + 24 * DEFAULT_RCLK, 2 }, +{ 0x8086, 0x5ac0, 0xffff, 0, "Intel Apollo Lake SIO/LPSS UART 2", 0x10, + 24 * DEFAULT_RCLK, 2 }, +{ 0x8086, 0x5aee, 0xffff, 0, "Intel Apollo Lake SIO/LPSS UART 3", 0x10, + 24 * DEFAULT_RCLK, 2 }, { 0x8086, 0x8811, 0xffff, 0, "Intel EG20T Serial Port 0", 0x10 }, { 0x8086, 0x8812, 0xffff, 0, "Intel EG20T Serial Port 1", 0x10 }, { 0x8086, 0x8813, 0xffff, 0, "Intel EG20T Serial Port 2", 0x10 }, |