aq(4): correct Atlantic 2 register access

Four Atlantic 2 register-access corrections found in bring-up.

B0 aggregate octet counters: the B0 firmware statistics interface reports
only aggregate rx/tx good octets, not the per-cast breakdown A0 and
Atlantic 1 provide, so every octet sysctl read a permanent zero while
frame counters advanced.  Populate the aggregate octet fields from the B0
buffer; aq_update_hw_stats() accumulates them directly when the per-cast
octets are absent.

Drop the duplicate attach-time MCP reboot: aq_hw_mpi_create() already
reboots the A2 firmware to read its version and caps, then aq_hw_reset()
immediately rebooted it again -- a full MCP restart plus several
transaction-id-bracketed window reads, adding attach latency and a
duplicate banner.  Give aq_hw_reset() a reboot flag and pass reboot=false
for A2 at attach; the load-bearing down/stop reboot (which resyncs A2 RX
DMA across ifconfig down/up) keeps reboot=true.

Skip Atlantic 1 register accesses on Atlantic 2: gate out the 0x7040
Atlantic 1 TPO write (which A2 lacks; already a no-op via the unset TPO2
feature, but Linux hw_atl2 omits it), and guard the
aq_hw_mpi_read_stats() direct reads of reg_rx_dma_stat_counter7 (dpc) and
the LRO counter (cprc) with !ATLANTIC2 -- those are Atlantic 1 codegen
offsets that on Atlantic 2 land on unrelated registers and can report
bogus input-drop / LRO counts.

HW-validated on AQC107 <-> AQC113C: A1 stats unchanged, A2 IQDROPS stays
0, attach consumes one MCP reboot instead of two, bidirectional iperf3
clean.

Reviewed by:	adrian
Differential Revision:	https://reviews.freebsd.org/D58143

4 files changed, 31 insertions, 18 deletions

diff --git a/sys/dev/aq/aq2_fw.c b/sys/dev/aq/aq2_fw.c
index 76152a9c07bb..d36b9e841624 100644
--- a/sys/dev/aq/aq2_fw.c
+++ b/sys/dev/aq/aq2_fw.c
@@ -422,6 +422,8 @@ aq2_fw_get_stats(struct aq_hw *hw, struct aq_hw_stats *stats)
 		stats->ptc = u.a0.tx_good_frames;
 	} else if (hw->aq2_iface == AQ2_FW_INTERFACE_OUT_VERSION_IFACE_VER_B0) {
 		/* B0 reports aggregate octets only; per-cast stays zero. */
+		stats->brc = u.b0.rx_good_octets;
+		stats->btc = u.b0.tx_good_octets;
 		stats->uprc = u.b0.rx_unicast_frames;
 		stats->mprc = u.b0.rx_multicast_frames;
 		stats->bprc = u.b0.rx_broadcast_frames;
diff --git a/sys/dev/aq/aq_hw.c b/sys/dev/aq/aq_hw.c
index 5dbdec172096..ca733ffa7e3d 100644
--- a/sys/dev/aq/aq_hw.c
+++ b/sys/dev/aq/aq_hw.c
@@ -217,13 +217,17 @@ aq_hw_mpi_read_stats(struct aq_hw *hw, struct aq_hw_stats *stats)
 	int err;
 
 	err = hw->fw_ops->get_stats(hw, stats);
+	if (err != 0)
+		return (err);
+
+	/* No firmware interface reports the RPB drop count; read it directly. */
+	stats->dpc = reg_rx_dma_stat_counter7get(hw);
 
-	if (err == 0) {
-		stats->dpc = reg_rx_dma_stat_counter7get(hw);
+	/* The LRO counter has no A2 counterpart in any reference driver. */
+	if (!IS_CHIP_FEATURE(hw, ATLANTIC2))
 		stats->cprc = stats_rx_lro_coalesced_pkt_count0_get(hw);
-	}
 
-	return (err);
+	return (0);
 }
 
 static int
@@ -364,19 +368,25 @@ aq_hw_set_power(struct aq_hw *hw, unsigned int power_state)
 /* HW NIC functions */
 
 int
-aq_hw_reset(struct aq_hw *hw)
+aq_hw_reset(struct aq_hw *hw, bool reboot)
 {
 	int err = 0;
 
 	AQ_DBG_ENTER();
 
-	/* A2 resets by rebooting the MCP; A1 uses the RBL/FLB reset. */
-	if (IS_CHIP_FEATURE(hw, ATLANTIC2))
-		err = aq2_fw_reboot(hw);
-	else
-		err = aq_fw_reset(hw);
-	if (err != 0)
-		goto err_exit;
+	/*
+	 * A2 resets by rebooting the MCP; A1 uses the RBL/FLB reset.  At attach
+	 * aq_hw_mpi_create() has already done this, so the caller passes
+	 * reboot=false to skip the (costly, on A2) redundant MCP reboot.
+	 */
+	if (reboot) {
+		if (IS_CHIP_FEATURE(hw, ATLANTIC2))
+			err = aq2_fw_reboot(hw);
+		else
+			err = aq_fw_reset(hw);
+		if (err != 0)
+			goto err_exit;
+	}
 
 	itr_irq_reg_res_dis_set(hw, 0);
 	itr_res_irq_set(hw, 1);
@@ -569,9 +579,10 @@ aq_hw_init_tx_path(struct aq_hw *hw)
 	/* Tx interrupts */
 	tdm_tx_desc_wr_wb_irq_en_set(hw, 1U);
 
-	/* misc */
-	AQ_WRITE_REG(hw, 0x00007040U,
-	    IS_CHIP_FEATURE(hw, TPO2) ? 0x00010000U : 0x00000000U);
+	/* misc (Atlantic 1 TPO register; absent on Atlantic 2) */
+	if (!IS_CHIP_FEATURE(hw, ATLANTIC2))
+		AQ_WRITE_REG(hw, 0x00007040U,
+		    IS_CHIP_FEATURE(hw, TPO2) ? 0x00010000U : 0x00000000U);
 	tdm_tx_dca_en_set(hw, 0U);
 	tdm_tx_dca_mode_set(hw, 0U);
 
diff --git a/sys/dev/aq/aq_hw.h b/sys/dev/aq/aq_hw.h
index a19a136ff172..ee824641294f 100644
--- a/sys/dev/aq/aq_hw.h
+++ b/sys/dev/aq/aq_hw.h
@@ -364,7 +364,7 @@ int aq_hw_set_link_speed(struct aq_hw *hw, uint32_t speed);
 
 int aq_hw_fw_downld_dwords(struct aq_hw *hw, uint32_t a, uint32_t *p, uint32_t cnt);
 
-int aq_hw_reset(struct aq_hw *hw);
+int aq_hw_reset(struct aq_hw *hw, bool reboot);
 
 int aq_hw_mpi_create(struct aq_hw *hw);
 
diff --git a/sys/dev/aq/aq_main.c b/sys/dev/aq/aq_main.c
index b78407a56c67..a8b87daa59d4 100644
--- a/sys/dev/aq/aq_main.c
+++ b/sys/dev/aq/aq_main.c
@@ -382,7 +382,7 @@ aq_if_attach_pre(if_ctx_t ctx)
 	if (hw->fast_start_enabled)
 		rc = hw->fw_ops->reset(hw);
 	else
-		rc = aq_hw_reset(&softc->hw);
+		rc = aq_hw_reset(&softc->hw, !IS_CHIP_FEATURE(hw, ATLANTIC2));
 	if (rc != 0) {
 		device_printf(softc->dev, "%s: reset failed, err=%d\n",
 		    __func__, rc);
@@ -813,7 +813,7 @@ aq_if_stop(if_ctx_t ctx)
 		aq_ring_rx_stop(hw, softc->rx_rings[i]);
 	}
 
-	aq_hw_reset(&softc->hw);
+	aq_hw_reset(&softc->hw, true);
 	memset(&softc->last_stats, 0, sizeof(softc->last_stats));
 	softc->linkup = false;
 	aq_if_update_admin_status(ctx);