aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorD Scott Phillips <scottph@FreeBSD.org>2021-02-17 19:06:48 +0000
committerEd Maste <emaste@FreeBSD.org>2021-02-17 19:08:38 +0000
commitc720435062566324459cb5dd1bdfc1d0e108c516 (patch)
treeba32187adaae3fad6b6b73465df4351329bf6c87
parentab4fad4be14462e347ed24ee3663a18eacfb138e (diff)
downloadsrc-c720435062566324459cb5dd1bdfc1d0e108c516.tar.gz
src-c720435062566324459cb5dd1bdfc1d0e108c516.zip
gicv3_its: Leave LPI interrupts enabled during handling
This follows the behavior on x86 where edge triggered interrupts are not disabled when executing the handler. Because the ITS is a shared resource, contention for the command queue lock can be substantial. Suggested by: gallatin Reviewed by: andrew Tested by: gallatin Sponsored by: Ampere Computing LLC Differential Revision: https://reviews.freebsd.org/D28709
-rw-r--r--sys/arm64/arm64/gicv3_its.c2
1 files changed, 0 insertions, 2 deletions
diff --git a/sys/arm64/arm64/gicv3_its.c b/sys/arm64/arm64/gicv3_its.c
index 061d5a1dbdb9..ba7ccdc7d696 100644
--- a/sys/arm64/arm64/gicv3_its.c
+++ b/sys/arm64/arm64/gicv3_its.c
@@ -1013,7 +1013,6 @@ gicv3_its_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
sc = device_get_softc(dev);
girq = (struct gicv3_its_irqsrc *)isrc;
- gicv3_its_disable_intr(dev, isrc);
gic_icc_write(EOIR1, girq->gi_lpi + GIC_FIRST_LPI);
}
@@ -1021,7 +1020,6 @@ static void
gicv3_its_post_ithread(device_t dev, struct intr_irqsrc *isrc)
{
- gicv3_its_enable_intr(dev, isrc);
}
static void