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authorRoman Kurakin <rik@FreeBSD.org>2004-02-23 20:19:00 +0000
committerRoman Kurakin <rik@FreeBSD.org>2004-02-23 20:19:00 +0000
commitcee1270c1af563b8877f3ee833694ca693505177 (patch)
tree437ea38b10203cbe918b27dad6973dcd481e3664
parentb51049906c1fee1e4630b83c64be043f8973d9e5 (diff)
downloadsrc-cee1270c1af563b8877f3ee833694ca693505177.tar.gz
src-cee1270c1af563b8877f3ee833694ca693505177.zip
Add support for Cronyx-Tau. For now I added only Tau-ISA files, system files
would be changed in next patches, after extra verifications. Approved by: imp (mentor)
Notes
Notes: svn path=/head/; revision=126177
-rw-r--r--sys/dev/ctau/am8530.h115
-rw-r--r--sys/dev/ctau/ctau.c1796
-rw-r--r--sys/dev/ctau/ctau2fw.h498
-rw-r--r--sys/dev/ctau/ctaue1fw.h2066
-rw-r--r--sys/dev/ctau/ctaufw.h848
-rw-r--r--sys/dev/ctau/ctaug7fw.h2062
-rw-r--r--sys/dev/ctau/ctaureg.h276
-rw-r--r--sys/dev/ctau/ctddk.c1162
-rw-r--r--sys/dev/ctau/ctddk.h606
-rw-r--r--sys/dev/ctau/ds2153.h290
-rw-r--r--sys/dev/ctau/hdc64570.h492
-rw-r--r--sys/dev/ctau/if_ct.c2737
-rw-r--r--sys/dev/ctau/lxt318.h44
-rw-r--r--sys/dev/ctau/ng_ct.h31
14 files changed, 13023 insertions, 0 deletions
diff --git a/sys/dev/ctau/am8530.h b/sys/dev/ctau/am8530.h
new file mode 100644
index 000000000000..0ab2d4eaeb45
--- /dev/null
+++ b/sys/dev/ctau/am8530.h
@@ -0,0 +1,115 @@
+/*
+ * AMD Am83C30 serial communication controller registers.
+ *
+ * Copyright (C) 1996 Cronyx Engineering.
+ * Author: Serge Vakulenko, <vak@cronyx.ru>
+ *
+ * This software is distributed with NO WARRANTIES, not even the implied
+ * warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Authors grant any other persons or organisations permission to use
+ * or modify this software as long as this message is kept with the software,
+ * all derivative works or modified versions.
+ *
+ * Cronyx Id: am8530.h,v 1.1.2.2 2003/11/12 17:31:21 rik Exp $
+ * $FreeBSD$
+ */
+
+/*
+ * Read/write registers.
+ */
+#define AM_IVR 2 /* rw2 - interrupt vector register */
+#define AM_DAT 8 /* rw8 - data buffer register */
+#define AM_TCL 12 /* rw12 - time constant low */
+#define AM_TCH 13 /* rw13 - time constant high */
+#define AM_SICR 15 /* rw15 - status interrupt control reg */
+
+/*
+ * Write only registers.
+ */
+#define AM_CR 0 /* w0 - command register */
+#define AM_IMR 1 /* w1 - interrupt mode register */
+#define AM_RCR 3 /* w3 - receive control register */
+#define AM_PMR 4 /* w4 - tx/rx parameters and modes reg */
+#define AM_TCR 5 /* w5 - transmit control register */
+#define AM_SAF 6 /* w6 - sync address field */
+#define AM_SFR 7 /* w7 - sync flag register */
+#define AM_MICR 9 /* w9 - master interrupt control reg */
+#define AM_MCR 10 /* w10 - misc control register */
+#define AM_CMR 11 /* w11 - clock mode register */
+#define AM_BCR 14 /* w14 - baud rate control register */
+
+/*
+ * Read only registers.
+ */
+#define AM_SR 0 /* r0 - status register */
+#define AM_RSR 1 /* r1 - receive status register */
+#define AM_IPR 3 /* r3 - interrupt pending register */
+#define AM_MSR 10 /* r10 - misc status register */
+
+/*
+ * Enhanced mode registers.
+ * In enhanced mode registers PMR(w4), TCR(w5) become readable.
+ */
+#define AM_FBCL 6 /* r6 - frame byte count low */
+#define AM_FBCH 7 /* r7 - frame byte count high */
+#define AM_RCR_R 9 /* r9 - read RCR(w3) */
+#define AM_MCR_R 11 /* r11 - read MCR(w10) */
+#define AM_SFR_R 14 /* r14 - read SFR(w7') */
+
+#define AM_A 32 /* channel A offset */
+
+/*
+ * Interrupt vector register
+ */
+#define IVR_A 0x08 /* channel A status */
+#define IVR_REASON 0x06 /* interrupt reason mask */
+#define IVR_TXRDY 0x00 /* transmit buffer empty */
+#define IVR_STATUS 0x02 /* external status interrupt */
+#define IVR_RX 0x04 /* receive character available */
+#define IVR_RXERR 0x06 /* special receive condition */
+
+/*
+ * Interrupt mask register
+ */
+#define IMR_EXT 0x01 /* ext interrupt enable */
+#define IMR_TX 0x02 /* ext interrupt enable */
+#define IMR_PARITY 0x04 /* ext interrupt enable */
+
+#define IMR_RX_FIRST 0x08 /* ext interrupt enable */
+#define IMR_RX_ALL 0x10 /* ext interrupt enable */
+#define IMR_RX_ERR 0x18 /* ext interrupt enable */
+
+#define IMR_WD_RX 0x20 /* wait/request follows receiver fifo */
+#define IMR_WD_REQ 0x40 /* wait/request function as request */
+#define IMR_WD_ENABLE 0x80 /* wait/request pin enable */
+
+/*
+ * Master interrupt control register
+ */
+#define MICR_VIS 0x01 /* vector includes status */
+#define MICR_NV 0x02 /* no interrupt vector */
+#define MICR_DLC 0x04 /* disable lower chain */
+#define MICR_MIE 0x08 /* master interrupt enable */
+#define MICR_HIGH 0x10 /* status high */
+#define MICR_NINTACK 0x20 /* interrupt masking without INTACK */
+
+#define MICR_RESET_A 0x80 /* channel reset A */
+#define MICR_RESET_B 0x40 /* channel reset B */
+#define MICR_RESET_HW 0xc0 /* force hardware reset */
+
+/*
+ * Receive status register
+ */
+#define RSR_FRME 0x10 /* framing error */
+#define RSR_RXOVRN 0x20 /* rx overrun error */
+
+/*
+ * Command register
+ */
+#define CR_RST_EXTINT 0x10 /* reset external/status irq */
+#define CR_TX_ABORT 0x18 /* send abort (SDLC) */
+#define CR_RX_NXTINT 0x20 /* enable irq on next rx character */
+#define CR_RST_TXINT 0x28 /* reset tx irq pending */
+#define CR_RST_ERROR 0x30 /* error reset */
+#define CR_RST_HIUS 0x38 /* reset highest irq under service */
diff --git a/sys/dev/ctau/ctau.c b/sys/dev/ctau/ctau.c
new file mode 100644
index 000000000000..8c3805bdb6d1
--- /dev/null
+++ b/sys/dev/ctau/ctau.c
@@ -0,0 +1,1796 @@
+/*
+ * Low-level subroutines for Cronyx-Tau adapter.
+ *
+ * Copyright (C) 1994-2001 Cronyx Engineering.
+ * Author: Serge Vakulenko, <vak@cronyx.ru>
+ *
+ * Copyright (C) 2003 Cronyx Engineering.
+ * Author: Roman Kurakin, <rik@cronyx.ru>
+ *
+ * This software is distributed with NO WARRANTIES, not even the implied
+ * warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Authors grant any other persons or organisations permission to use
+ * or modify this software as long as this message is kept with the software,
+ * all derivative works or modified versions.
+ *
+ * Cronyx Id: ctau.c,v 1.1.2.4 2003/12/11 17:33:43 rik Exp $
+ */
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <dev/cx/machdep.h>
+#include <dev/ctau/ctddk.h>
+#include <dev/ctau/ctaureg.h>
+#include <dev/ctau/hdc64570.h>
+#include <dev/ctau/ds2153.h>
+#include <dev/ctau/am8530.h>
+#include <dev/ctau/lxt318.h>
+#include <dev/cx/cronyxfw.h>
+
+#define DMA_MASK 0xd4 /* DMA mask register */
+#define DMA_MASK_CLEAR 0x04 /* DMA clear mask */
+#define DMA_MODE 0xd6 /* DMA mode register */
+#define DMA_MODE_MASTER 0xc0 /* DMA master mode */
+
+#define BYTE *(unsigned char*)&
+
+static unsigned char irqmask [] = {
+ BCR0_IRQ_DIS, BCR0_IRQ_DIS, BCR0_IRQ_DIS, BCR0_IRQ_3,
+ BCR0_IRQ_DIS, BCR0_IRQ_5, BCR0_IRQ_DIS, BCR0_IRQ_7,
+ BCR0_IRQ_DIS, BCR0_IRQ_DIS, BCR0_IRQ_10, BCR0_IRQ_11,
+ BCR0_IRQ_12, BCR0_IRQ_DIS, BCR0_IRQ_DIS, BCR0_IRQ_15,
+};
+
+static unsigned char dmamask [] = {
+ BCR0_DMA_DIS, BCR0_DMA_DIS, BCR0_DMA_DIS, BCR0_DMA_DIS,
+ BCR0_DMA_DIS, BCR0_DMA_5, BCR0_DMA_6, BCR0_DMA_7,
+};
+
+static short porttab [] = { /* standard base port set */
+ 0x200, 0x220, 0x240, 0x260, 0x280, 0x2a0, 0x2c0, 0x2e0,
+ 0x300, 0x320, 0x340, 0x360, 0x380, 0x3a0, 0x3c0, 0x3e0, 0
+};
+
+static short irqtab [] = { 3, 5, 7, 10, 11, 12, 15, 0 };
+static short dmatab [] = { 5, 6, 7, 0 };
+
+static int valid (short value, short *list)
+{
+ while (*list)
+ if (value == *list++)
+ return 1;
+ return 0;
+}
+
+long ct_baud = 256000; /* default baud rate */
+unsigned char ct_chan_mode = M_HDLC; /* default mode */
+
+static void ct_init_chan (ct_board_t *b, int num);
+static void ct_enable_loop (ct_chan_t *c);
+static void ct_disable_loop (ct_chan_t *c);
+
+int ct_download (port_t port, const unsigned char *firmware,
+ long bits, const cr_dat_tst_t *tst)
+{
+ unsigned char cr1, sr2;
+ long i, n, maxn = (bits + 7) >> 3;
+ int v, b;
+
+ inb (BSR3(port));
+ for (i=n=0; n<maxn; ++n) {
+ v = ((firmware[n] ^ ' ') << 1) | ((firmware[n] >> 7) & 1);
+ for (b=0; b<7; b+=2, i+=2) {
+ if (i >= bits)
+ break;
+ cr1 = 0;
+ if (v >> b & 1)
+ cr1 |= BCR1_TMS;
+ if (v >> b & 2)
+ cr1 |= BCR1_TDI;
+ outb (BCR1(port), cr1);
+ sr2 = inb (BSR2(port));
+ outb (BCR0(port), BCR0_TCK);
+ outb (BCR0(port), 0);
+ if (i >= tst->end)
+ ++tst;
+ if (i >= tst->start && (sr2 & BSR2_LERR))
+ return (0);
+ }
+ }
+ return (1);
+}
+
+/*
+ * Firmware unpack algorithm.
+ */
+typedef struct {
+ const unsigned char *ptr;
+ unsigned char byte;
+ unsigned char count;
+} unpack_t;
+
+static unsigned short unpack_init (unpack_t *t, const unsigned char *ptr)
+{
+ unsigned short len;
+
+ len = *ptr++;
+ len |= *ptr++ << 8;
+ t->ptr = ptr;
+ t->byte = 0;
+ t->count = 0;
+ return len;
+}
+
+static unsigned char unpack_getchar (unpack_t *t)
+{
+ if (t->count > 0) {
+ --t->count;
+ return t->byte;
+ }
+ t->byte = *t->ptr++;
+ if (t->byte == 0)
+ t->count = *t->ptr++;
+ return t->byte;
+}
+
+/*
+ * Firmware download signals.
+ */
+#define nstatus(b) (inb(BSR3(b)) & BSR3_NSTATUS)
+
+#define confdone(b) (inb(BSR3(b)) & BSR3_CONF_DN)
+
+#define nconfig_set(b) outb (bcr1_port, (bcr1 &= ~BCR1_NCONFIGI))
+#define nconfig_clr(b) outb (bcr1_port, (bcr1 |= BCR1_NCONFIGI))
+
+#define dclk_tick(b) outb (BCR3(b), 0)
+
+#define putbit(b,bit) { if (bit) bcr1 |= BCR1_1KDAT; \
+ else bcr1 &= ~BCR1_1KDAT; \
+ outb (bcr1_port, bcr1); \
+ dclk_tick (b); }
+
+#define DEBUG(x) /*trace_str x*/
+
+int ct_download2 (port_t port, const unsigned char *fwaddr)
+{
+ unsigned short bytes;
+ unsigned char bcr1, val;
+ port_t bcr1_port;
+ unpack_t t;
+
+ /*
+ * Set NCONFIG and wait until NSTATUS is set.
+ */
+ bcr1_port = BCR1(port);
+ bcr1 = 0;
+ nconfig_set(port);
+ for (val=0; val<255; ++val)
+ if (nstatus(port))
+ break;
+
+ /*
+ * Clear NCONFIG, wait 2 usec and check that NSTATUS is cleared.
+ */
+ nconfig_clr(port);
+ for (val=0; val<2*3; ++val)
+ nconfig_clr(port);
+ if (nstatus(port)) {
+ DEBUG (("Bad nstatus, downloading aborted (bsr3=0x%x).\n", inb(BSR3(port))));
+ nconfig_set(port);
+ return 0;
+ }
+
+ /*
+ * Set NCONFIG and wait 5 usec.
+ */
+ nconfig_set(port);
+ for (val=0; val<5*3; ++val) /* Delay 5 msec. */
+ nconfig_set(port);
+
+ /*
+ * С адреса `fwaddr' в памяти должны лежать упакованные данные
+ * для загрузки firmware. Значение должно быть согласовано с параметром
+ * вызова утилиты `megaprog' в скрипте загрузки (и Makefile).
+ */
+ bytes = unpack_init (&t, fwaddr);
+ for (; bytes>0; --bytes) {
+ val = unpack_getchar (&t);
+
+ if (nstatus(port) == 0) {
+ DEBUG (("Bad nstatus, %d bytes remaining.\n", bytes));
+ goto failed;
+ }
+
+ if (confdone(port)) {
+ /* Ten extra clocks. Hope 50 is enough. */
+ for (val=0; val<50; ++val)
+ dclk_tick (port);
+
+ if (nstatus(port) == 0) {
+ DEBUG (("Bad nstatus after confdone, %d bytes remaining (%d).\n",
+ bytes, t.ptr - fwaddr));
+ goto failed;
+ }
+
+ /* Succeeded. */
+ /*DEBUG (("Download succeeded.\n"));*/
+ return 1;
+ }
+
+ putbit (port, val & 0x01);
+ putbit (port, val & 0x02);
+ putbit (port, val & 0x04);
+ putbit (port, val & 0x08);
+ putbit (port, val & 0x10);
+ putbit (port, val & 0x20);
+ putbit (port, val & 0x40);
+ putbit (port, val & 0x80);
+
+ /* if ((bytes & 1023) == 0) putch ('.'); */
+ }
+
+ DEBUG (("Bad confdone.\n"));
+failed:
+ DEBUG (("Downloading aborted.\n"));
+ return 0;
+}
+
+/*
+ * Detect Tau2 adapter.
+ */
+static int ct_probe2_board (port_t port)
+{
+ unsigned char sr3, osr3;
+ int i;
+
+ if (! valid (port, porttab))
+ return 0;
+
+ osr3 = inb (BSR3(port));
+ if ((osr3 & (BSR3_IB | BSR3_IB_NEG)) != BSR3_IB &&
+ (osr3 & (BSR3_IB | BSR3_IB_NEG)) != BSR3_IB_NEG)
+ return (0);
+ for (i=0; i<100; ++i) {
+ /* Do it twice */
+ sr3 = inb (BSR3(port));
+ sr3 = inb (BSR3(port));
+ if (((sr3 ^ osr3) & (BSR3_IB | BSR3_IB_NEG | BSR3_ZERO)) !=
+ (BSR3_IB | BSR3_IB_NEG))
+ return (0);
+ osr3 = sr3;
+ }
+ /* Reset the controller. */
+ outb (BCR0(port), 0);
+ return 1;
+}
+
+/*
+ * Check if the Tau board is present at the given base port.
+ * Read board status register 1 and check identification bits
+ * which should invert every next read.
+ * The "zero" bit should remain stable.
+ */
+int ct_probe_board (port_t port, int irq, int dma)
+{
+ unsigned char sr3, osr3;
+ int i;
+
+ if (! valid (port, porttab))
+ return 0;
+
+ if ((irq > 0) && (!valid (irq, irqtab)))
+ return 0;
+
+ if ((dma > 0) && (!valid (dma, dmatab)))
+ return 0;
+
+ osr3 = inb (BSR3(port));
+ if ((osr3 & (BSR3_IB | BSR3_IB_NEG)) != BSR3_IB &&
+ (osr3 & (BSR3_IB | BSR3_IB_NEG)) != BSR3_IB_NEG)
+ return (0);
+ for (i=0; i<100; ++i) {
+ sr3 = inb (BSR3(port));
+ if (((sr3 ^ osr3) & (BSR3_IB | BSR3_IB_NEG | BSR3_ZERO)) !=
+ (BSR3_IB | BSR3_IB_NEG))
+ return ct_probe2_board (port);
+ osr3 = sr3;
+ }
+ /* Reset the controller. */
+ outb (BCR0(port), 0);
+ return (1);
+}
+
+/*
+ * Check that the irq is functional.
+ * irq>0 - activate the interrupt from the adapter (irq=on)
+ * irq<0 - deactivate the interrupt (irq=off)
+ * irq==0 - free the interrupt line (irq=tri-state)
+ * Return the interrupt mask _before_ activating irq.
+ */
+int ct_probe_irq (ct_board_t *b, int irq)
+{
+ int mask;
+
+ outb (0x20, 0x0a);
+ mask = inb (0x20);
+ outb (0xa0, 0x0a);
+ mask |= inb (0xa0) << 8;
+
+ if (irq > 0) {
+ outb (BCR0(b->port), BCR0_HDRUN | irqmask[irq]);
+ outb (R(b->port,HD_TEPR_0R), 0);
+ outw (R(b->port,HD_TCONR_0R), 1);
+ outw (R(b->port,HD_TCNT_0R), 0);
+ outb (R(b->port,HD_TCSR_0R), TCSR_ENABLE | TCSR_INTR);
+ outb (IER2(b->port), IER2_RX_TME_0);
+ } else if (irq < 0) {
+ outb (BCR0(b->port), BCR0_HDRUN | irqmask[-irq]);
+ outb (IER0(b->port), 0);
+ outb (IER1(b->port), 0);
+ outb (IER2(b->port), 0);
+ outb (R(b->port,HD_TCSR_0R), 0);
+ cte_out (E1CS0 (b->port), DS_IMR2, 0);
+ cte_out (E1CS1 (b->port), DS_IMR2, 0);
+ if (-irq > 7) {
+ outb (0xa0, 0x60 | ((-irq) & 7));
+ outb (0x20, 0x62);
+ } else
+ outb (0x20, 0x60 | (-irq));
+ } else {
+ outb (BCR0(b->port), b->bcr0);
+ cte_out (E1CS0 (b->port), DS_IMR2, SR2_SEC);
+ cte_out (E1CS1 (b->port), DS_IMR2, SR2_SEC);
+ }
+
+ return mask;
+}
+
+void ct_init_board (ct_board_t *b, int num, port_t port, int irq, int dma,
+ int type, long osc)
+{
+ int i;
+
+ /* Initialize board structure. */
+ b->type = type;
+ b->port = port;
+ b->num = num;
+ b->irq = irq;
+ b->dma = dma;
+ b->osc = osc;
+
+ /* Get the board type. */
+ if (b->type == B_TAU) strcpy (b->name, "Tau");
+ else if (b->type == B_TAU_E1) strcpy (b->name, "Tau/E1");
+ else if (b->type == B_TAU_E1C) strcpy (b->name, "Tau/E1c");
+ else if (b->type == B_TAU_E1D) strcpy (b->name, "Tau/E1d");
+ else if (b->type == B_TAU_G703) strcpy (b->name, "Tau/G.703");
+ else if (b->type == B_TAU_G703C) strcpy (b->name, "Tau/G.703c");
+ else if (b->type == B_TAU2) strcpy (b->name, "Tau2");
+ else if (b->type == B_TAU2_E1) strcpy (b->name, "Tau2/E1");
+ else if (b->type == B_TAU2_E1D) strcpy (b->name, "Tau2/E1d");
+ else if (b->type == B_TAU2_G703) strcpy (b->name, "Tau2/G.703");
+ else strcpy (b->name, "Tau/???");
+
+ /* Set DMA and IRQ. */
+ b->bcr0 = BCR0_HDRUN | dmamask[b->dma] | irqmask[b->irq];
+
+ /* Clear DTR[0..1]. */
+ b->bcr1 = 0;
+ b->e1cfg = 0;
+
+ /* Initialize channel structures. */
+ for (i=0; i<NCHAN; ++i)
+ ct_init_chan (b, i);
+ ct_reinit_board (b);
+}
+
+/*
+ * Initialize the board structure.
+ */
+void ct_init (ct_board_t *b, int num, port_t port, int irq, int dma,
+ const unsigned char *firmware, long bits, const cr_dat_tst_t *tst,
+ const unsigned char *firmware2)
+{
+ static long tlen = 182;
+ static cr_dat_tst_t tvec [] = {{ 114, 178 }, { 182, 182 }};
+ static cr_dat_tst_t tvec2 [] = {{ 50, 178 }, { 182, 182 }};
+ static unsigned char tau [] = { 155,153,113,48,64,236,
+ 48,49,49,49,49,49,49,49,49,49,49,49,49,49,49,49,183,};
+ static unsigned char e1 [] = { 155,153,113,48,64,236,
+ 112,37,49,37,33,116,101,100,112,37,49,37,33,116,101,100,230,};
+ static unsigned char e1_2 [] = { 155,153,113,48,64,236,
+ 112,37,49,37,33,116,101,100,96,97,53,49,49,96,97,100,230,};
+ static unsigned char e1_3 [] = { 155,153,113,48,64,236,
+ 96,97,53,49,49,96,97,100,96,97,53,49,49,96,97,100,230,};
+ static unsigned char e1_4 [] = { 155,153,113,48,64,236,
+ 96,97,53,49,49,96,97,100,112,37,49,37,33,116,101,100,230,};
+ static unsigned char g703 [] = { 155,153,113,48,64,236,
+ 112,37,49,37,33,116,101,32,117,37,49,37,33,116,101,100,230,};
+ static unsigned char g703_2 [] = { 155,153,113,48,64,236,
+ 112,37,49,37,33,116,101,32,101,97,53,49,49,96,97,100,230,};
+ static unsigned char g703_3 [] = { 155,153,113,48,64,236,
+ 96,97,53,49,49,96,97,32,101,97,53,49,49,96,97,100,230,};
+ static unsigned char g703_4 [] = { 155,153,113,48,64,236,
+ 96,97,53,49,49,96,97,32,117,37,49,37,33,116,101,100,230,};
+
+ int type = B_TAU;
+ long osc = (inb (BSR3(port)) & BSR3_ZERO) ? 8192000 : 10000000;
+
+ /* Get the board type. */
+ if (ct_probe2_board (port) && ct_download2 (port, firmware2)) {
+ /* Tau2, 1k30-based model */
+ unsigned char sr0 = inb (BSR0(port));
+ if (! (sr0 & BSR0_T703))
+ type = B_TAU2_G703;
+ else if (sr0 & BSR0_TE1)
+ type = B_TAU2;
+ else if (inb(E1SR(port)) & E1SR_REV)
+ type = B_TAU2_E1D;
+ else
+ type = B_TAU2_E1;
+ } else if (ct_download (port, tau, tlen, tvec)) {
+ if (! ct_download (port, firmware, bits, tst))
+ type = B_TAU;
+ else {
+ unsigned char sr0 = inb (BSR0(port));
+ if (! (sr0 & BSR0_T703))
+ type = B_TAU_G703C;
+ else if (sr0 & BSR0_TE1)
+ type = B_TAU;
+ else if (inb(E1SR(port)) & E1SR_REV)
+ type = B_TAU_E1D;
+ else
+ type = B_TAU_E1C;
+ }
+ } else if (ct_download (port, e1, tlen, tvec2) ||
+ ct_download (port, e1_2, tlen, tvec2) ||
+ ct_download (port, e1_3, tlen, tvec2) ||
+ ct_download (port, e1_4, tlen, tvec2))
+ type = B_TAU_E1;
+ else if (ct_download (port, g703, tlen, tvec2) ||
+ ct_download (port, g703_2, tlen, tvec2) ||
+ ct_download (port, g703_3, tlen, tvec2) ||
+ ct_download (port, g703_4, tlen, tvec2))
+ type = B_TAU_G703;
+ ct_init_board (b, num, port, irq, dma, type, osc);
+}
+
+/*
+ * Initialize the channel structure.
+ */
+static void ct_init_chan (ct_board_t *b, int i)
+{
+ ct_chan_t *c = b->chan + i;
+ port_t port = b->port;
+
+ c->num = i;
+ c->board = b;
+ switch (b->type) {
+ case B_TAU:
+ case B_TAU2: c->type = T_SERIAL; break;
+ case B_TAU_E1:
+ case B_TAU_E1C:
+ case B_TAU_E1D:
+ case B_TAU2_E1:
+ case B_TAU2_E1D: c->type = T_E1; break;
+ case B_TAU_G703:
+ case B_TAU_G703C:
+ case B_TAU2_G703: c->type = T_G703; break;
+ }
+ if (c->num)
+ c->type |= T_SERIAL;
+
+#define reg(X,N) HD_##X##_##N
+#define set(X,N) c->X = R(port,reg(X,N))
+#define srx(X,N) c->RX.X = R(port,reg(X,N##R))
+#define stx(X,N) c->TX.X = R(port,reg(X,N##T))
+ if (i == 0) {
+ set(MD0, 0); set(MD1, 0); set(MD2, 0); set(CTL, 0);
+ set(RXS, 0); set(TXS, 0); set(TMC, 0); set(CMD, 0);
+ set(ST0, 0); set(ST1, 0); set(ST2, 0); set(ST3, 0);
+ set(FST, 0); set(IE0, 0); set(IE1, 0); set(IE2, 0);
+ set(FST, 0); set(IE0, 0); set(IE1, 0); set(IE2, 0);
+ set(FIE, 0); set(SA0, 0); set(SA1, 0); set(IDL, 0);
+ set(TRB, 0); set(RRC, 0); set(TRC0,0); set(TRC1,0);
+ set(CST, 0);
+ srx(DAR, 0); srx(DARB,0); srx(SAR, 0); srx(SARB,0);
+ srx(CDA, 0); srx(EDA, 0); srx(BFL, 0); srx(BCR, 0);
+ srx(DSR, 0); srx(DMR, 0); srx(FCT, 0); srx(DIR, 0);
+ srx(DCR, 0);
+ srx(TCNT,0); srx(TCONR,0); srx(TCSR,0); srx(TEPR,0);
+ stx(DAR, 0); stx(DARB,0); stx(SAR, 0); stx(SARB,0);
+ stx(CDA, 0); stx(EDA, 0); stx(BCR, 0);
+ stx(DSR, 0); stx(DMR, 0); stx(FCT, 0); stx(DIR, 0);
+ stx(DCR, 0);
+ stx(TCNT,0); stx(TCONR,0); stx(TCSR,0); stx(TEPR,0);
+ } else {
+ set(MD0, 1); set(MD1, 1); set(MD2, 1); set(CTL, 1);
+ set(RXS, 1); set(TXS, 1); set(TMC, 1); set(CMD, 1);
+ set(ST0, 1); set(ST1, 1); set(ST2, 1); set(ST3, 1);
+ set(FST, 1); set(IE0, 1); set(IE1, 1); set(IE2, 1);
+ set(FST, 1); set(IE0, 1); set(IE1, 1); set(IE2, 1);
+ set(FIE, 1); set(SA0, 1); set(SA1, 1); set(IDL, 1);
+ set(TRB, 1); set(RRC, 1); set(TRC0,1); set(TRC1,1);
+ set(CST, 1);
+ srx(DAR, 1); srx(DARB,1); srx(SAR, 1); srx(SARB,1);
+ srx(CDA, 1); srx(EDA, 1); srx(BFL, 1); srx(BCR, 1);
+ srx(DSR, 1); srx(DMR, 1); srx(FCT, 1); srx(DIR, 1);
+ srx(DCR, 1);
+ srx(TCNT,1); srx(TCONR,1); srx(TCSR,1); srx(TEPR,1);
+ stx(DAR, 1); stx(DARB,1); stx(SAR, 1); stx(SARB,1);
+ stx(CDA, 1); stx(EDA, 1); stx(BCR, 1);
+ stx(DSR, 1); stx(DMR, 1); stx(FCT, 1); stx(DIR, 1);
+ stx(DCR, 1);
+ stx(TCNT,1); stx(TCONR,1); stx(TCSR,1); stx(TEPR,1);
+ }
+#undef set
+#undef srx
+#undef stx
+#undef reg
+}
+
+/*
+ * Reinitialize the channels, using new options.
+ */
+void ct_reinit_chan (ct_chan_t *c)
+{
+ ct_board_t *b = c->board;
+ long s;
+ int i;
+
+ if (c->hopt.txs == CLK_LINE) {
+ /* External clock mode -- set zero baud rate. */
+ if (c->mode != M_ASYNC)
+ c->baud = 0;
+ } else if (c->baud == 0) {
+ /* No baud rate in internal clock mode -- set default values. */
+ if (c->mode == M_ASYNC)
+ c->baud = 9600;
+ else if (c->mode == M_HDLC)
+ c->baud = 64000;
+ }
+ switch (c->type) {
+ case T_E1_SERIAL:
+ if (b->opt.cfg == CFG_B)
+ break;
+ /* Fall through... */
+ case T_E1:
+ c->mode = M_E1;
+ c->hopt.txs = CLK_LINE;
+
+ /* Compute the baud value. */
+ if (c->num) {
+ s = b->opt.s1;
+ if (b->opt.cfg == CFG_C)
+ s &=~ b->opt.s0;
+ } else
+ s = b->opt.s0;
+ /* Skip timeslot 16 in CAS mode. */
+ if (c->gopt.cas)
+ s &=~ (1L << 16);
+
+ c->baud = 0;
+ for (i=0; i<32; ++i)
+ if ((s >> i) & 1)
+ c->baud += 64000;
+ c->gopt.rate = c->baud / 1000;
+
+ /* Set NRZ and clear INVCLK. */
+ c->opt.md2.encod = MD2_ENCOD_NRZ;
+ c->board->opt.bcr2 &= c->num ?
+ ~(BCR2_INVTXC1 | BCR2_INVRXC1) :
+ ~(BCR2_INVTXC0 | BCR2_INVRXC0);
+ break;
+
+ case T_G703_SERIAL:
+ if (b->opt.cfg == CFG_B)
+ break;
+ /* Fall through... */
+ case T_G703:
+ c->mode = M_G703;
+ c->hopt.txs = CLK_LINE;
+ c->baud = c->gopt.rate * 1000L;
+
+ /* Set NRZ/NRZI and clear INVCLK. */
+ if (c->opt.md2.encod != MD2_ENCOD_NRZ &&
+ c->opt.md2.encod != MD2_ENCOD_NRZI)
+ c->opt.md2.encod = MD2_ENCOD_NRZ;
+ c->board->opt.bcr2 &= c->num ?
+ ~(BCR2_INVTXC1 | BCR2_INVRXC1) :
+ ~(BCR2_INVTXC0 | BCR2_INVRXC0);
+ break;
+ }
+}
+
+/*
+ * Reinitialize all channels, using new options and baud rate.
+ */
+void ct_reinit_board (ct_board_t *b)
+{
+ ct_chan_t *c;
+
+ b->opt = ct_board_opt_dflt;
+ for (c=b->chan; c<b->chan+NCHAN; ++c) {
+ c->opt = ct_chan_opt_dflt;
+ c->hopt = ct_opt_hdlc_dflt;
+ c->gopt = ct_opt_g703_dflt;
+ c->mode = ct_chan_mode;
+ c->baud = ct_baud;
+
+ ct_reinit_chan (c);
+ }
+}
+
+/*
+ * Set up the E1 controller of the Tau/E1 board.
+ * Frame sync signals:
+ * Configuration Rsync0 Tsync0 Rsync1 Tsync1
+ * ---------------------------------------------------
+ * A (II) out out out out
+ * B,C,D (HI,K,D) in out in out
+ * ---------------------------------------------------
+ * BI out out in in -- not implemented
+ * old B,C,D (HI,K,D) out in out in -- old
+ */
+static void ct_setup_ctlr (ct_chan_t *c)
+{
+ ct_board_t *b = c->board;
+ port_t p = c->num ? E1CS1 (b->port) : E1CS0 (b->port);
+ unsigned char rcr1, rcr2, tcr1, tcr2, ccr1, licr;
+ unsigned long xcbr, tir;
+ int i;
+
+ rcr2 = RCR2_RSCLKM;
+ tcr1 = TCR1_TSIS | TCR1_TSO;
+ tcr2 = 0;
+ ccr1 = 0;
+ licr = 0;
+
+ if (b->opt.cfg != CFG_D) {
+ /* Enable monitoring channel, when not in telephony mode. */
+ rcr2 |= RCR2_SA_4;
+ tcr2 |= TCR2_SA_4;
+ }
+ if (b->opt.cfg == CFG_A) {
+ rcr1 = RCR1_RSO;
+ } else {
+ rcr1 = RCR1_RSI;
+ rcr2 |= RCR2_RESE;
+ }
+
+ if (c->gopt.cas)
+ tcr1 |= TCR1_T16S;
+ else
+ ccr1 |= CCR1_CCS;
+
+ if (c->gopt.hdb3)
+ ccr1 |= CCR1_THDB3 | CCR1_RHDB3;
+
+ if (c->gopt.crc4) {
+ ccr1 |= CCR1_TCRC4 | CCR1_RCRC4;
+ tcr2 |= TCR2_AEBE;
+ }
+
+ if (c->gopt.higain)
+ licr |= LICR_HIGAIN;
+ if (inb (E1SR (b->port)) & (c->num ? E1SR_TP1 : E1SR_TP0))
+ licr |= LICR_LB120P;
+ else
+ licr |= LICR_LB75P;
+
+ cte_out (p, DS_RCR1, rcr1); /* receive control 1 */
+ cte_out (p, DS_RCR2, rcr2); /* receive control 2 */
+ cte_out (p, DS_TCR1, tcr1); /* transmit control 1 */
+ cte_out (p, DS_TCR2, tcr2); /* transmit control 2 */
+ cte_out (p, DS_CCR1, ccr1); /* common control 1 */
+ cte_out (p, DS_CCR2, CCR2_CNTCV | CCR2_AUTORA | CCR2_LOFA1); /* common control 2 */
+ cte_out (p, DS_CCR3, CCR3_TSCLKM); /* common control 3 */
+ cte_out (p, DS_LICR, licr); /* line interface control */
+ cte_out (p, DS_IMR1, 0); /* interrupt mask 1 */
+ cte_out (p, DS_IMR2, SR2_SEC); /* interrupt mask 2 */
+ cte_out (p, DS_TEST1, 0);
+ cte_out (p, DS_TEST2, 0);
+ cte_out (p, DS_TAF, 0x9b); /* transmit align frame */
+ cte_out (p, DS_TNAF, 0xdf); /* transmit non-align frame */
+ cte_out (p, DS_TIDR, 0xff); /* transmit idle definition */
+
+ cte_out (p, DS_TS, 0x0b); /* transmit signaling 1 */
+ for (i=1; i<16; ++i)
+ /* transmit signaling 2..16 */
+ cte_out (p, (unsigned char) (DS_TS+i), 0xff);
+
+ /*
+ * S0 == list of timeslots for channel 0
+ * S1 == list of timeslots for channel 1
+ * S2 == list of timeslots for E1 subchannel (pass through)
+ *
+ * Each channel uses the same timeslots for receive and transmit,
+ * i.e. RCBRi == TCBRi.
+ */
+ if (b->opt.cfg == CFG_B)
+ b->opt.s1 = 0;
+ else if (b->opt.cfg == CFG_C)
+ b->opt.s1 &=~ b->opt.s0;
+ if (c->gopt.cas) {
+ /* Skip timeslot 16 in CAS mode. */
+ b->opt.s0 &=~ (1L << 16);
+ b->opt.s1 &=~ (1L << 16);
+ }
+ b->opt.s2 &=~ b->opt.s0;
+ b->opt.s2 &=~ b->opt.s1;
+
+ /*
+ * Configuration A:
+ * xCBRi := Si
+ * TIRi := ~Si
+ *
+ * Configuration B:
+ * xCBRi := Si
+ * TIRi := 0
+ *
+ * Configuration C: (S0 & S2 == 0)
+ * xCBR0 := S0
+ * xCBR1 := 0
+ * TIR0 := ~S0 & ~S2
+ * TIR1 := ~S2
+ *
+ * Configuration D: (Si & Sj == 0)
+ * xCBR0 := S0
+ * xCBR1 := S1
+ * TIR0 := ~S0 & ~S1 & ~S2
+ * TIR1 := ~S2
+ */
+ xcbr = c->num ? b->opt.s1 : b->opt.s0;
+ if (b->opt.cfg == CFG_A)
+ tir = ~xcbr;
+ else if (b->opt.cfg == CFG_D)
+ tir = 0;
+ else if (c->num == 0)
+ tir = ~(b->opt.s0 | b->opt.s1 | b->opt.s2);
+ else
+ tir = ~b->opt.s2;
+
+ /* Mark idle channels. */
+ cte_out (p, DS_TIR, (unsigned char) (tir & 0xfe));
+ cte_out (p, DS_TIR+1, (unsigned char) (tir >> 8));
+ cte_out (p, DS_TIR+2, (unsigned char) (tir >> 16));
+ cte_out (p, DS_TIR+3, (unsigned char) (tir >> 24));
+
+ /* Set up rx/tx timeslots. */
+ cte_out (p, DS_RCBR, (unsigned char) (xcbr & 0xfe));
+ cte_out (p, DS_RCBR+1, (unsigned char) (xcbr >> 8));
+ cte_out (p, DS_RCBR+2, (unsigned char) (xcbr >> 16));
+ cte_out (p, DS_RCBR+3, (unsigned char) (xcbr >> 24));
+ cte_out (p, DS_TCBR, (unsigned char) (xcbr & 0xfe));
+ cte_out (p, DS_TCBR+1, (unsigned char) (xcbr >> 8));
+ cte_out (p, DS_TCBR+2, (unsigned char) (xcbr >> 16));
+ cte_out (p, DS_TCBR+3, (unsigned char) (xcbr >> 24));
+
+ /* Reset the line interface. */
+ cte_out (p, DS_CCR3, CCR3_TSCLKM | CCR3_LIRESET);
+ cte_out (p, DS_CCR3, CCR3_TSCLKM);
+
+ /* Reset the elastic store. */
+ cte_out (p, DS_CCR3, CCR3_TSCLKM | CCR3_ESRESET);
+ cte_out (p, DS_CCR3, CCR3_TSCLKM);
+
+ /* Clear status registers. */
+ cte_ins (p, DS_SR1, 0xff);
+ cte_ins (p, DS_SR2, 0xff);
+ cte_ins (p, DS_RIR, 0xff);
+}
+
+/*
+ * Set up the serial controller of the Tau/E1 board.
+ */
+static void ct_setup_scc (port_t port)
+{
+#define SET(r,v) { cte_out2 (port, r, v); cte_out2 (port, AM_A | r, v); }
+
+ /* hardware reset */
+ cte_out2 (port, AM_MICR, MICR_RESET_HW);
+
+ SET (AM_PMR, 0x0c); /* 2 stop bits */
+ SET (AM_IMR, 0); /* no W/REQ signal */
+ cte_out2 (port, AM_IVR, 0); /* interrupt vector */
+ SET (AM_RCR, 0xc0); /* rx 8 bits/char */
+ SET (AM_TCR, 0x60); /* tx 8 bits/char */
+ SET (AM_SAF, 0); /* sync address field */
+ SET (AM_SFR, 0x7e); /* sync flag register */
+ cte_out2 (port, AM_MICR, 0); /* master interrupt control */
+ SET (AM_MCR, 0); /* NRZ mode */
+ SET (AM_CMR, 0x08); /* rxclk=RTxC, txclk=TRxC */
+ SET (AM_TCL, 0); /* time constant low */
+ SET (AM_TCH, 0); /* time constant high */
+ SET (AM_BCR, 0); /* disable baud rate generator */
+
+ SET (AM_RCR, 0xc1); /* enable rx */
+ SET (AM_TCR, 0x68); /* enable tx */
+
+ SET (AM_SICR, 0); /* no status interrupt */
+ SET (AM_CR, CR_RST_EXTINT); /* reset external status */
+ SET (AM_CR, CR_RST_EXTINT); /* reset ext/status twice */
+#undef SET
+}
+
+/*
+ * Set up the Tau/E1 board.
+ */
+void ct_setup_e1 (ct_board_t *b)
+{
+ /*
+ * Control register 0:
+ * 1) board configuration
+ * 2) clock modes
+ */
+ b->e1cfg &= E1CFG_LED;
+ switch (b->opt.cfg){
+ case CFG_C: b->e1cfg |= E1CFG_K; break;
+ case CFG_B: b->e1cfg |= E1CFG_HI; break;
+ case CFG_D: b->e1cfg |= E1CFG_D; break;
+ default: b->e1cfg |= E1CFG_II; break;
+ }
+
+ if (b->opt.clk0 == GCLK_RCV) b->e1cfg |= E1CFG_CLK0_RCV;
+ if (b->opt.clk0 == GCLK_RCLKO) b->e1cfg |= E1CFG_CLK0_RCLK1;
+ else b->e1cfg |= E1CFG_CLK0_INT;
+ if (b->opt.clk1 == GCLK_RCV) b->e1cfg |= E1CFG_CLK1_RCV;
+ if (b->opt.clk1 == GCLK_RCLKO) b->e1cfg |= E1CFG_CLK1_RCLK0;
+ else b->e1cfg |= E1CFG_CLK1_INT;
+
+ outb (E1CFG (b->port), b->e1cfg);
+
+ /*
+ * Set up serial controller.
+ */
+ ct_setup_scc (b->port);
+
+ /*
+ * Set up E1 controllers.
+ */
+ ct_setup_ctlr (b->chan + 0); /* channel 0 */
+ ct_setup_ctlr (b->chan + 1); /* channel 1 */
+
+ /* Start the board (GRUN). */
+ b->e1cfg |= E1CFG_GRUN;
+ outb (E1CFG (b->port), b->e1cfg);
+}
+
+/*
+ * Set up the G.703 controller of the Tau/G.703 board.
+ */
+static void ct_setup_lxt (ct_chan_t *c)
+{
+ ctg_outx (c, LX_CCR1, LX_RESET); /* reset the chip */
+ /* Delay */
+ ctg_inx (c, LX_CCR1);
+ c->lx = LX_LOS; /* disable loss of sync interrupt */
+ if (c->num && c->board->opt.cfg == CFG_B)
+ c->lx |= LX_TAOS; /* idle channel--transmit all ones */
+ if (c->gopt.hdb3)
+ c->lx |= LX_HDB3; /* enable HDB3 encoding */
+ ctg_outx (c, LX_CCR1, c->lx); /* setup the new mode */
+ ctg_outx (c, LX_CCR2, LX_CCR2_LH); /* setup Long Haul mode */
+ ctg_outx (c, LX_CCR3, LX_CCR3_E1_LH); /* setup Long Haul mode */
+}
+
+/*
+ * Set up the Tau/G.703 board.
+ */
+void ct_setup_g703 (ct_board_t *b)
+{
+ b->gmd0 = GMD_2048;
+ if (b->chan[0].gopt.pce) {
+ if (b->chan[0].gopt.pce2) b->gmd0 |= GMD_PCE_PCM2;
+ else b->gmd0 |= GMD_PCE_PCM2D;
+ }
+ if (b->opt.clk0)
+ b->gmd0 |= GMD_RSYNC;
+
+ b->gmd1 = 0;
+ if (b->chan[1].gopt.pce) {
+ if (b->chan[1].gopt.pce2) b->gmd1 |= GMD_PCE_PCM2;
+ else b->gmd1 |= GMD_PCE_PCM2D;
+ }
+ if (b->opt.clk1)
+ b->gmd1 |= GMD_RSYNC;
+
+ switch (b->chan[0].gopt.rate) {
+ case 2048: b->gmd0 |= GMD_2048; break;
+ case 1024: b->gmd0 |= GMD_1024; break;
+ case 512: b->gmd0 |= GMD_512; break;
+ case 256: b->gmd0 |= GMD_256; break;
+ case 128: b->gmd0 |= GMD_128; break;
+ case 64: b->gmd0 |= GMD_64; break;
+ }
+ switch (b->chan[1].gopt.rate) {
+ case 2048: b->gmd1 |= GMD_2048; break;
+ case 1024: b->gmd1 |= GMD_1024; break;
+ case 512: b->gmd1 |= GMD_512; break;
+ case 256: b->gmd1 |= GMD_256; break;
+
+ case 128: b->gmd1 |= GMD_128; break;
+ case 64: b->gmd1 |= GMD_64; break;
+ }
+
+ outb (GMD0(b->port), b->gmd0);
+ outb (GMD1(b->port), b->gmd1 | GMD1_NCS0 | GMD1_NCS1);
+
+ b->gmd2 &= GMD2_LED;
+ if (b->opt.cfg == CFG_B) b->gmd2 |= GMD2_SERIAL;
+ outb (GMD2(b->port), b->gmd2);
+
+ /* Set up G.703 controllers. */
+ if ((b->chan + 0)->lx & LX_LLOOP) {
+ ct_setup_lxt (b->chan + 0); /* channel 0 */
+ ct_enable_loop (b->chan + 0);
+ } else {
+ ct_setup_lxt (b->chan + 0); /* channel 0 */
+ }
+ if ((b->chan + 1)->lx & LX_LLOOP) {
+ ct_setup_lxt (b->chan + 1); /* channel 1 */
+ ct_enable_loop (b->chan + 1);
+ } else {
+ ct_setup_lxt (b->chan + 1); /* channel 1 */
+ }
+
+ /* Clear errors. */
+ outb (GERR(b->port), 0xff);
+ outb (GLDR(b->port), 0xff);
+}
+
+/*
+ * Set up the board.
+ */
+int ct_setup_board (ct_board_t *b, const unsigned char *firmware,
+ long bits, const cr_dat_tst_t *tst)
+{
+ ct_chan_t *c;
+
+ /* Disable DMA channel. */
+ outb (DMA_MASK, (b->dma & 3) | DMA_MASK_CLEAR);
+
+ /* Reset the controller. */
+ outb (BCR0(b->port), 0);
+
+ /* Load the firmware. */
+ if (firmware && (b->type == B_TAU || b->type == B_TAU_E1 ||
+ b->type == B_TAU_G703) &&
+ ! ct_download (b->port, firmware, bits, tst))
+ return (0);
+ if (firmware && (b->type == B_TAU2 || b->type == B_TAU2_E1 ||
+ b->type == B_TAU2_E1D || b->type == B_TAU2_G703) &&
+ ! ct_download2 (b->port, firmware))
+ return (0);
+
+ /* Enable DMA and IRQ. */
+ outb (BCR0(b->port), BCR0_HDRUN);
+ outb (BCR0(b->port), b->bcr0);
+
+ /* Clear DTR[0..1]. */
+ outb (BCR1(b->port), b->bcr1);
+
+ /* Set bus timing. */
+ b->bcr2 = b->opt.bcr2;
+ outb (BCR2(b->port), b->bcr2);
+
+ /*
+ * Initialize the controller.
+ */
+ /* Zero wait state mode. */
+ outb (WCRL(b->port), 0);
+ outb (WCRM(b->port), 0);
+ outb (WCRH(b->port), 0);
+
+ /* Clear interrupt modified vector register. */
+ outb (IMVR(b->port), 0);
+ outb (ITCR(b->port), ITCR_CYCLE_SINGLE | ITCR_VECT_MOD);
+
+ /* Disable all interrupts. */
+ outb (IER0(b->port), 0);
+ outb (IER1(b->port), 0);
+ outb (IER2(b->port), 0);
+
+ /* Set DMA parameters, enable master DMA mode. */
+ outb (PCR(b->port), BYTE b->opt.pcr);
+ outb (DMER(b->port), DME_ENABLE);
+
+ /* Set up DMA channel to master mode. */
+ outb (DMA_MODE, (b->dma & 3) | DMA_MODE_MASTER);
+
+ /* Enable DMA channel. */
+ outb (DMA_MASK, b->dma & 3);
+
+ /* Disable byte-sync mode for Tau/G.703. */
+ if (b->type == B_TAU_G703)
+ outb (GMD2(b->port), 0);
+
+ /* Initialize all channels. */
+ for (c=b->chan; c<b->chan+NCHAN; ++c)
+ ct_setup_chan (c);
+
+ switch (b->type) {
+ case B_TAU_G703:
+ case B_TAU_G703C:
+ case B_TAU2_G703:
+ ct_setup_g703 (b);
+ break;
+ case B_TAU_E1:
+ case B_TAU_E1C:
+ case B_TAU_E1D:
+ case B_TAU2_E1:
+ case B_TAU2_E1D:
+ ct_setup_e1 (b);
+ break;
+ }
+ return (1);
+}
+
+/*
+ * Update the channel mode options.
+ */
+void ct_update_chan (ct_chan_t *c)
+{
+ int txbr, rxbr, tmc, txcout;
+ unsigned char rxs, txs, dmr = 0;
+ ct_md0_async_t amd0;
+ ct_md0_hdlc_t hmd0;
+ ct_md1_async_t amd1;
+
+ switch (c->mode) { /* initialize the channel mode */
+ case M_ASYNC: default:
+ rxs = CLK_INT;
+ txs = CLK_INT;
+
+ amd0.mode = MD0_MODE_ASYNC;
+ amd0.stopb = MD0_STOPB_1;
+ amd0.cts_rts_dcd = 0;
+
+ amd1.clk = MD1_CLK_16;
+ amd1.txclen = amd1.rxclen = MD1_CLEN_8;
+ amd1.parmode = MD1_PAR_NO;
+
+ outb (c->MD0, BYTE amd0);
+ outb (c->MD1, BYTE amd1);
+ outb (c->CTL, c->rts ? 0 : CTL_RTS_INV);
+ break;
+
+ case M_E1:
+ case M_G703:
+ case M_HDLC:
+ rxs = c->hopt.rxs;
+ txs = c->hopt.txs;
+
+ if (c->mode == M_E1 && c->board->opt.cfg == CFG_D) {
+ hmd0 = c->hopt.md0;
+ hmd0.crc = 0;
+
+ outb (c->MD0, BYTE hmd0);
+ outb (c->MD1, BYTE c->hopt.md1);
+ outb (c->CTL, c->hopt.ctl & ~CTL_IDLE_PTRN);
+ outb (c->SA0, c->hopt.sa0);
+ outb (c->SA1, c->hopt.sa1);
+ outb (c->IDL, 0x7e); /* HDLC flag 01111110 */
+ } else {
+ outb (c->MD0, BYTE c->hopt.md0);
+ outb (c->MD1, BYTE c->hopt.md1);
+ outb (c->SA0, c->hopt.sa0);
+ outb (c->SA1, c->hopt.sa1);
+ outb (c->IDL, 0x7e); /* HDLC flag 01111110 */
+
+ if (c->rts)
+ outb (c->CTL, c->hopt.ctl & ~CTL_RTS_INV);
+ else
+ outb (c->CTL, c->hopt.ctl | CTL_RTS_INV);
+ }
+
+ /* Chained-block DMA mode with frame counter. */
+ dmr |= DMR_CHAIN_CNTE | DMR_CHAIN_NF | DMR_TMOD;
+ break;
+
+ }
+ outb (c->RX.DMR, dmr);
+ outb (c->TX.DMR, dmr);
+
+ /* set mode-independent options */
+ c->opt.md2.dpll_clk = MD2_DPLL_CLK_8;
+ outb (c->MD2, BYTE c->opt.md2);
+
+ /* set up receiver and transmitter clocks */
+ if (c->baud > 1024000) {
+ /* turn off DPLL if the baud rate is too high */
+ if (rxs == CLK_RXS_LINE_NS) rxs = CLK_LINE;
+ else if (rxs == CLK_RXS_DPLL_INT) rxs = CLK_INT;
+ }
+ if (rxs == CLK_RXS_LINE_NS || rxs == CLK_RXS_DPLL_INT) {
+ /* Using 1:8 sampling rate. */
+ ct_compute_clock (c->board->osc, c->baud * 8, &rxbr, &tmc);
+ txbr = rxbr + 3;
+ } else if (c->mode == M_ASYNC) {
+ /* Using 1:16 sampling rate. */
+ ct_compute_clock (c->board->osc, c->baud * 8, &rxbr, &tmc);
+ --rxbr;
+ txbr = rxbr;
+ } else {
+ ct_compute_clock (c->board->osc, c->baud, &rxbr, &tmc);
+ txbr = rxbr;
+ }
+ txs |= txbr;
+ rxs |= rxbr;
+ outb (c->TMC, tmc);
+ outb (c->RXS, rxs);
+
+ /* Disable TXCOUT before changing TXS
+ * to avoid two transmitters on the same line.
+ * Enable it after TXS is set, if needed. */
+ txcout = c->num ? BCR1_TXCOUT1 : BCR1_TXCOUT0;
+ c->board->bcr1 &= ~txcout;
+ outb (BCR1(c->board->port), c->board->bcr1);
+ outb (c->TXS, txs);
+ if ((txs & CLK_MASK) != CLK_LINE) {
+ c->board->bcr1 |= txcout;
+ outb (BCR1(c->board->port), c->board->bcr1);
+ }
+ if (c->board->type == B_TAU_E1D ||
+ c->board->type == B_TAU2_E1D)
+ ct_set_phony (c, c->gopt.phony);
+}
+
+/*
+ * Initialize the channel.
+ */
+void ct_setup_chan (ct_chan_t *c)
+{
+ /* reset the channel */
+ outb (c->RX.DSR, DSR_DMA_DISABLE);
+ outb (c->TX.DSR, DSR_DMA_DISABLE);
+ outb (c->CMD, CMD_TX_RESET);
+ outb (c->CMD, CMD_TX_ABORT);
+ outb (c->CMD, CMD_CHAN_RESET);
+
+ /* disable interrupts */
+ outb (c->IE0, 0);
+ outb (c->IE1, 0);
+ outb (c->IE2, 0);
+ outb (c->FIE, 0);
+
+ /* clear DTR, RTS */
+ ct_set_dtr (c, 0);
+ ct_set_rts (c, 0);
+
+ c->lx = LX_LOS;
+ ct_update_chan (c);
+}
+
+unsigned long ct_get_ts (ct_chan_t *c)
+{
+ return c->num ? c->board->opt.s1 : c->board->opt.s0;
+}
+
+/*
+ * Data transfer speed
+ */
+unsigned long ct_get_baud (ct_chan_t *c)
+{
+ unsigned long speed;
+ unsigned long ts;
+
+ if (c->mode == M_G703) {
+ speed = 1000 * c->gopt.rate;
+ } else if (c->mode == M_E1) {
+ ts = ct_get_ts (c);
+ for (speed=0; ts; ts >>= 1) /* Each timeslot is 64 Kbps */
+ if (ts & 1)
+ speed += 64000;
+ } else
+ speed = (c->hopt.txs == CLK_INT) ? c->baud : 0;
+ return speed;
+}
+
+/*
+ * Turn local loopback on
+ */
+static void ct_enable_loop (ct_chan_t *c)
+{
+ if (c->mode == M_E1) {
+ unsigned short p = c->num ? E1CS1 (c->board->port) :
+ E1CS0 (c->board->port);
+
+ /* Local loopback. */
+ cte_out (p, DS_CCR2, cte_in (p, DS_CCR2) | CCR2_LLOOP);
+
+ /* Enable jitter attenuator at the transmit side. */
+ cte_out (p, DS_LICR, cte_in (p, DS_LICR) | LICR_JA_TX);
+ return;
+ } else if (c->mode == M_G703) {
+ c->lx = LX_LOS | LX_HDB3;
+ ctg_outx (c, LX_CCR1, c->lx |= LX_LLOOP);
+ return;
+ } else if (c->mode == M_HDLC && ct_get_baud(c)) {
+ unsigned char rxs = inb (c->RXS) & ~CLK_MASK;
+ unsigned char txs = inb (c->TXS) & ~CLK_MASK;
+ int txcout = c->num ? BCR1_TXCOUT1 : BCR1_TXCOUT0;
+ c->opt.md2.loop = MD2_LLOOP;
+
+ /* Disable TXCOUT before changing TXS */
+ /* to avoid two transmitters on the same line. */
+ /* Enable it after TXS is set. */
+ outb (BCR1(c->board->port), c->board->bcr1 & ~txcout);
+
+ outb (c->RXS, rxs | CLK_INT);
+ outb (c->TXS, txs | CLK_INT);
+
+ c->board->bcr1 |= txcout;
+ outb (BCR1(c->board->port), c->board->bcr1);
+
+ outb (c->MD2, *(unsigned char*)&c->opt.md2);
+ return;
+ }
+}
+
+/*
+ * Turn local loopback off
+ */
+static void ct_disable_loop (ct_chan_t *c)
+{
+ if (c->mode == M_E1) {
+ unsigned short p = c->num ? E1CS1 (c->board->port) :
+ E1CS0 (c->board->port);
+
+ /* Local loopback. */
+ cte_out (p, DS_CCR2, cte_in (p, DS_CCR2) & ~CCR2_LLOOP);
+
+ /* Disable jitter attenuator at the transmit side. */
+ cte_out (p, DS_LICR, cte_in (p, DS_LICR) & ~LICR_JA_TX);
+ return;
+ } else if (c->mode == M_G703) {
+ c->lx = LX_LOS | LX_HDB3;
+ ctg_outx (c, LX_CCR1, c->lx);
+ return;
+ } else if (c->mode == M_HDLC && ct_get_baud(c)) {
+ unsigned char rxs = inb (c->RXS) & ~CLK_MASK;
+ unsigned char txs = inb (c->TXS) & ~CLK_MASK;
+ int txcout = c->num ? BCR1_TXCOUT1 : BCR1_TXCOUT0;
+ c->opt.md2.loop = MD2_FDX;
+
+ outb (BCR1(c->board->port), c->board->bcr1 & ~txcout);
+
+ outb (c->RXS, rxs | CLK_LINE);
+ if (ct_get_baud (c))
+ outb (c->TXS, txs | CLK_INT);
+ else
+ outb (c->TXS, txs | CLK_LINE);
+
+ c->board->bcr1 |= txcout;
+ outb (BCR1(c->board->port), c->board->bcr1);
+
+ outb (c->MD2, *(unsigned char*)&c->opt.md2);
+ return;
+ }
+}
+
+/*
+ * Turn local loopback on/off
+ */
+void ct_set_loop (ct_chan_t *c, int on)
+{
+ if (on)
+ ct_enable_loop (c);
+ else
+ ct_disable_loop (c);
+}
+
+int ct_get_loop (ct_chan_t *c)
+{
+ if (c->mode == M_E1) {
+ unsigned short p = c->num ? E1CS1 (c->board->port) :
+ E1CS0 (c->board->port);
+
+ return cte_in (p, DS_CCR2) & CCR2_LLOOP;
+ }
+ if (c->mode == M_G703)
+ return c->lx & LX_LLOOP;
+
+ /* M_HDLC */
+ return (c->opt.md2.loop & MD2_LLOOP) != 0;
+}
+
+void ct_set_phony (ct_chan_t *c, int on)
+{
+ /* Valid only for TauPCI-E1. */
+ if (c->board->type != B_TAU_E1D &&
+ c->board->type != B_TAU2_E1D)
+ return;
+ c->gopt.phony = (on != 0);
+ if (c->gopt.phony) {
+ c->board->e1syn |= c->num ? E1SYN_ENS1 : E1SYN_ENS0;
+ /* No receive/transmit crc. */
+ c->hopt.md0.crc = 0;
+ } else {
+ c->board->e1syn &= ~(c->num ? E1SYN_ENS1 : E1SYN_ENS0);
+ /* Enable crc. */
+ c->hopt.md0.crc = 1;
+ }
+ outb (c->MD0, BYTE c->hopt.md0);
+ outb (E1SYN(c->board->port), c->board->e1syn);
+}
+
+void ct_start_receiver (ct_chan_t *c, int dma, unsigned long buf,
+ unsigned len, unsigned long desc, unsigned long lim)
+{
+ int ier0 = inb (IER0(c->board->port));
+ int ier1 = inb (IER1(c->board->port));
+ int ier2 = inb (IER2(c->board->port));
+ int ie0 = inb (c->IE0);
+ int ie2 = inb (c->IE2);
+
+ if (dma) {
+ ier1 |= c->num ? (IER1_RX_DMERE_1 | IER1_RX_DME_1) :
+ (IER1_RX_DMERE_0 | IER1_RX_DME_0);
+ if (c->mode == M_ASYNC) {
+ ier0 |= c->num ? IER0_RX_INTE_1 : IER0_RX_INTE_0;
+ ie0 |= IE0_RX_INTE;
+ ie2 |= IE2_OVRNE | IE2_ASYNC_FRMEE | IE2_ASYNC_PEE;
+ }
+ } else {
+ ier0 |= c->num ? (IER0_RX_INTE_1 | IER0_RX_RDYE_1) :
+ (IER0_RX_INTE_0 | IER0_RX_RDYE_0);
+ ie0 |= IE0_RX_INTE | IE0_RX_RDYE;
+ }
+
+ /* Start timer. */
+ if (! dma) {
+ outb (c->RX.TEPR, TEPR_64); /* prescale to 16 kHz */
+ outw (c->RX.TCONR, 160); /* period is 10 msec */
+ outw (c->RX.TCNT, 0);
+ outb (c->RX.TCSR, TCSR_ENABLE | TCSR_INTR);
+ ier2 |= c->num ? IER2_RX_TME_1 : IER2_RX_TME_0;
+ }
+
+ /* Enable interrupts. */
+ outb (IER0(c->board->port), ier0);
+ outb (IER1(c->board->port), ier1);
+ outb (IER2(c->board->port), ier2);
+ outb (c->IE0, ie0);
+ outb (c->IE2, ie2);
+
+ /* RXRDY:=1 when the receive buffer has more than RRC chars */
+ outb (c->RRC, dma ? c->opt.dma_rrc : c->opt.pio_rrc);
+
+ /* Start receiver. */
+ if (dma) {
+ outb (c->RX.DCR, DCR_ABORT);
+ if (c->mode == M_ASYNC) {
+ /* Single-buffer DMA mode. */
+ outb (c->RX.DARB, (unsigned char) (buf >> 16));
+ outw (c->RX.DAR, (unsigned short) buf);
+ outw (c->RX.BCR, len);
+ outb (c->RX.DIR, DIR_EOTE);
+ } else {
+ /* Chained-buffer DMA mode. */
+ outb (c->RX.SARB, (unsigned char) (desc >> 16));
+ outw (c->RX.EDA, (unsigned short) lim);
+ outw (c->RX.CDA, (unsigned short) desc);
+ outw (c->RX.BFL, len);
+ outb (c->RX.DIR, DIR_CHAIN_EOME | DIR_CHAIN_BOFE |
+ DIR_CHAIN_COFE);
+ }
+ outb (c->RX.DSR, DSR_DMA_ENABLE);
+ }
+ outb (c->CMD, CMD_RX_ENABLE);
+}
+
+void ct_start_transmitter (ct_chan_t *c, int dma, unsigned long buf,
+ unsigned len, unsigned long desc, unsigned long lim)
+{
+ int ier0 = inb (IER0(c->board->port));
+ int ier1 = inb (IER1(c->board->port));
+ int ie0 = inb (c->IE0);
+ int ie1 = inb (c->IE1);
+
+ /* Enable underrun interrupt in HDLC and raw modes. */
+ if (c->mode != M_ASYNC) {
+ ier0 |= c->num ? IER0_TX_INTE_1 : IER0_TX_INTE_0;
+ ie0 |= IE0_TX_INTE;
+ ie1 |= IE1_HDLC_UDRNE;
+ }
+ if (dma)
+ ier1 |= c->num ? (IER1_TX_DMERE_1 | IER1_TX_DME_1) :
+ (IER1_TX_DMERE_0 | IER1_TX_DME_0);
+ else {
+ ier0 |= c->num ? IER0_TX_RDYE_1 : IER0_TX_RDYE_0;
+ ie0 |= IE0_TX_RDYE;
+ }
+
+ /* Enable interrupts. */
+ outb (IER0(c->board->port), ier0);
+ outb (IER1(c->board->port), ier1);
+ outb (c->IE0, ie0);
+ outb (c->IE1, ie1);
+
+ /* TXRDY:=1 when the transmit buffer has TRC0 or less chars,
+ * TXRDY:=0 when the transmit buffer has more than TRC1 chars */
+ outb (c->TRC0, dma ? c->opt.dma_trc0 : c->opt.pio_trc0);
+ outb (c->TRC1, dma ? c->opt.dma_trc1 : c->opt.pio_trc1);
+
+ /* Start transmitter. */
+ if (dma) {
+ outb (c->TX.DCR, DCR_ABORT);
+ if (c->mode == M_ASYNC) {
+ /* Single-buffer DMA mode. */
+ outb (c->TX.SARB, (unsigned char) (buf >> 16));
+ outw (c->TX.SAR, (unsigned short) buf);
+ outw (c->TX.BCR, len);
+ outb (c->TX.DIR, DIR_EOTE);
+ } else {
+ /* Chained-buffer DMA mode. */
+ outb (c->TX.SARB, (unsigned char) (desc >> 16));
+ outw (c->TX.EDA, (unsigned short) lim);
+ outw (c->TX.CDA, (unsigned short) desc);
+ outb (c->TX.DIR, /* DIR_CHAIN_EOME | */ DIR_CHAIN_BOFE |
+ DIR_CHAIN_COFE);
+ }
+ /* Set DSR_DMA_ENABLE to begin! */
+ }
+ outb (c->CMD, CMD_TX_ENABLE);
+
+ /* Clear errors. */
+ if (c->board->type == B_TAU_G703) {
+ outb (GERR(c->board->port), 0xff);
+ outb (GLDR(c->board->port), 0xff);
+ }
+}
+
+/*
+ * Control DTR signal for the channel.
+ * Turn it on/off.
+ */
+void ct_set_dtr (ct_chan_t *c, int on)
+{
+ if (on) {
+ c->dtr = 1;
+ c->board->bcr1 |= c->num ? BCR1_DTR1 : BCR1_DTR0;
+ } else {
+ c->dtr = 0;
+ c->board->bcr1 &= ~(c->num ? BCR1_DTR1 : BCR1_DTR0);
+ }
+ outb (BCR1(c->board->port), c->board->bcr1);
+}
+
+/*
+ * Control RTS signal for the channel.
+ * Turn it on/off.
+ */
+void ct_set_rts (ct_chan_t *c, int on)
+{
+ c->rts = (on != 0);
+ if (c->rts)
+ outb (c->CTL, inb (c->CTL) & ~CTL_RTS_INV);
+ else
+ outb (c->CTL, inb (c->CTL) | CTL_RTS_INV);
+}
+
+/*
+ * Control BREAK state in asynchronous mode.
+ * Turn it on/off.
+ */
+void ct_set_brk (ct_chan_t *c, int on)
+{
+ if (c->mode != M_ASYNC)
+ return;
+ if (on)
+ outb (c->CTL, inb (c->CTL) | CTL_BRK);
+ else
+ outb (c->CTL, inb (c->CTL) & ~CTL_BRK);
+}
+
+/*
+ * Get the state of DSR signal of the channel.
+ */
+int ct_get_dsr (ct_chan_t *c)
+{
+ return (inb (BSR1(c->board->port)) &
+ (c->num ? BSR1_DSR1 : BSR1_DSR0)) != 0;
+}
+
+/*
+ * Get the G.703 line signal level.
+ */
+int ct_get_lq (ct_chan_t *c)
+{
+ unsigned char q1, q2, q3;
+ static int lq_to_santibells [] = { 0, 95, 195, 285 };
+ int i;
+
+ if (! (c->type & T_G703))
+ return 0;
+ q1 = inb (GLQ (c->board->port));
+ /* Repeat reading the register to produce a 10-usec delay. */
+ for (i=0; i<20; ++i)
+ q2 = inb (GLQ (c->board->port));
+ for (i=0; i<20; ++i)
+ q3 = inb (GLQ (c->board->port));
+ if (c->num) {
+ q1 >>= GLQ_SHIFT;
+ q2 >>= GLQ_SHIFT;
+ q3 >>= GLQ_SHIFT;
+ }
+ q1 &= GLQ_MASK;
+ q2 &= GLQ_MASK;
+ q3 &= GLQ_MASK;
+ if (q1 <= q2 && q2 <= q3) return lq_to_santibells [q2];
+ if (q2 <= q3 && q3 <= q1) return lq_to_santibells [q3];
+ if (q3 <= q1 && q1 <= q2) return lq_to_santibells [q1];
+ if (q1 <= q3 && q3 <= q2) return lq_to_santibells [q3];
+ if (q3 <= q2 && q2 <= q1) return lq_to_santibells [q2];
+ /* if (q2 <= q1 && q1 <= q3) */ return lq_to_santibells [q1];
+}
+
+/*
+ * Get the state of CARRIER signal of the channel.
+ */
+int ct_get_cd (ct_chan_t *c)
+{
+ return (inb (c->ST3) & ST3_DCD_INV) == 0;
+}
+
+/*
+ * Get the state of CTS signal of the channel.
+ */
+int ct_get_cts (ct_chan_t *c)
+{
+ return (inb (c->ST3) & ST3_CTS_INV) == 0;
+}
+
+/*
+ * Turn LED on/off.
+ */
+void ct_led (ct_board_t *b, int on)
+{
+ switch (b->type) {
+ case B_TAU_G703:
+ case B_TAU_G703C:
+ case B_TAU2_G703:
+ if (on) b->gmd2 |= GMD2_LED;
+ else b->gmd2 &= ~GMD2_LED;
+ outb (GMD2(b->port), b->gmd2);
+ break;
+ default:
+ if (on) b->e1cfg |= E1CFG_LED;
+ else b->e1cfg &= ~E1CFG_LED;
+ outb (E1CFG(b->port), b->e1cfg);
+ break;
+ }
+}
+
+void ct_disable_dma (ct_board_t *b)
+{
+ /* Disable DMA channel. */
+ outb (DMA_MASK, (b->dma & 3) | DMA_MASK_CLEAR);
+}
+
+void ct_compute_clock (long hz, long baud, int *txbr, int *tmc)
+{
+ if (baud < 100)
+ baud = 100;
+ *txbr = 0;
+ if (4*baud > 3*hz)
+ *tmc = 1;
+ else {
+ while (((hz / baud) >> ++*txbr) > 256)
+ continue;
+ *tmc = (((2 * hz / baud) >> *txbr) + 1) / 2;
+ }
+}
+
+/*
+ * Access to DS2153 chips on the Tau/E1 board.
+ * Examples:
+ * val = cte_in (E1CSi (base), DS_RCR1)
+ * cte_out (E1CSi (base), DS_CCR1, val)
+ * val = cte_ins (E1CSi (base), DS_SSR)
+ */
+unsigned char cte_in (port_t base, unsigned char reg)
+{
+ outb (base, reg);
+ return inb (E1DAT (base & 0x3e0));
+}
+
+void cte_out (port_t base, unsigned char reg, unsigned char val)
+{
+ outb (base, reg);
+ outb (E1DAT (base & 0x3e0), val);
+}
+
+/*
+ * Get the DS2153 status register, using write-read-write scheme.
+ */
+unsigned char cte_ins (port_t base, unsigned char reg,
+ unsigned char mask)
+{
+ unsigned char val;
+ port_t rw = E1DAT (base & 0x3e0);
+
+ outb (base, reg); outb (rw, mask); /* lock bits */
+ outb (base, reg); val = inb (rw) & mask; /* get values */
+ outb (base, reg); outb (rw, val); /* unlock bits */
+ return val;
+}
+
+/*
+ * Access to 8530 chip on the Tau/E1 board.
+ * Examples:
+ * val = cte_in2 (base, AM_RSR | AM_A)
+ * cte_out2 (base, AM_IMR, val)
+ */
+unsigned char cte_in2 (port_t base, unsigned char reg)
+{
+ outb (E1CS2(base), E1CS2_SCC | reg >> 4);
+ outb (E1DAT(base), reg & 15);
+ return inb (E1DAT(base));
+}
+
+void cte_out2 (port_t base, unsigned char reg, unsigned char val)
+{
+ outb (E1CS2(base), E1CS2_SCC | reg >> 4);
+ outb (E1DAT(base), reg & 15);
+ outb (E1DAT(base), val);
+}
+
+/*
+ * Read the data from the 8530 receive fifo.
+ */
+unsigned char cte_in2d (ct_chan_t *c)
+{
+ outb (E1CS2(c->board->port), E1CS2_SCC | E1CS2_DC |
+ (c->num ? 0 : E1CS2_AB));
+ return inb (E1DAT(c->board->port));
+}
+
+/*
+ * Send the 8530 command.
+ */
+void cte_out2c (ct_chan_t *c, unsigned char val)
+{
+ outb (E1CS2(c->board->port), E1CS2_SCC | (c->num ? 0 : E1CS2_AB));
+ outb (E1DAT(c->board->port), val);
+}
+
+/*
+ * Write the data to the 8530 transmit fifo.
+ */
+void cte_out2d (ct_chan_t *c, unsigned char val)
+{
+ outb (E1CS2(c->board->port), E1CS2_SCC | E1CS2_DC |
+ (c->num ? 0 : E1CS2_AB));
+ outb (E1DAT(c->board->port), val);
+}
+
+/*
+ * Access to LXT318 chip on the Tau/G.703 board.
+ * Examples:
+ * val = ctg_inx (c)
+ * ctg_outx (c, val)
+ */
+static void ctg_output (port_t port, unsigned char val, unsigned char v0)
+{
+ int i;
+
+ for (i=0; i<8; ++i) {
+ unsigned char v = v0;
+ if ((val >> i) & 1)
+ v |= GMD0_SDI;
+ outb (port, v);
+ outb (port, v);
+ outb (port, v);
+ outb (port, v);
+ outb (port, v | GMD0_SCLK);
+ outb (port, v | GMD0_SCLK);
+ outb (port, v | GMD0_SCLK);
+ outb (port, v | GMD0_SCLK);
+ }
+ outb (port, v0);
+}
+
+void ctg_outx (ct_chan_t *c, unsigned char reg, unsigned char val)
+{
+ port_t port = GMD0(c->board->port);
+
+ outb (GMD1(c->board->port), c->board->gmd1 | GMD1_NCS0 | GMD1_NCS1);
+ outb (GMD1(c->board->port), c->board->gmd1 |
+ (c->num ? GMD1_NCS0 : GMD1_NCS1));
+ ctg_output (port, (reg << 1) | LX_WRITE, c->board->gmd0);
+ ctg_output (port, val, c->board->gmd0);
+ outb (GMD1(c->board->port), c->board->gmd1 | GMD1_NCS0 | GMD1_NCS1);
+}
+
+unsigned char ctg_inx (ct_chan_t *c, unsigned char reg)
+{
+ port_t port = GMD0(c->board->port);
+ port_t data = GLDR(c->board->port);
+ unsigned char val = 0, mask = c->num ? GLDR_C1 : GLDR_C0;
+ int i;
+
+ outb (GMD1(c->board->port), c->board->gmd1 | GMD1_NCS0 | GMD1_NCS1);
+ outb (GMD1(c->board->port), c->board->gmd1 |
+ (c->num ? GMD1_NCS0 : GMD1_NCS1));
+ ctg_output (port, (reg << 1) | LX_READ, c->board->gmd0);
+ for (i=0; i<8; ++i) {
+ outb (port, c->board->gmd0 | GMD0_SCLK);
+ if (inb (data) & mask)
+ val |= 1 << i;
+ outb (port, c->board->gmd0);
+ }
+ outb (GMD1(c->board->port), c->board->gmd1 | GMD1_NCS0 | GMD1_NCS1);
+ return val;
+}
+
+/*
+ * Adapter options
+ */
+ct_board_opt_t ct_board_opt_dflt = {
+ 0, /* board control register 2 */
+ { /* DMA priority control register */
+ PCR_PRIO_ROTATE,
+ 0, /* all channels share the the bus hold */
+ 0, /* hold the bus until all transfers done */
+ },
+ CFG_A, /* E1/G.703 config: two independent channels */
+ GCLK_INT, /* E1/G.703 chan 0 internal tx clock source */
+ GCLK_INT, /* E1/G.703 chan 1 internal tx clock source */
+ ~0UL << 1, /* E1 channel 0 timeslots 1..31 */
+ ~0UL << 1, /* E1 channel 1 timeslots 1..31 */
+ 0, /* no E1 subchannel timeslots */
+};
+
+/*
+ * Mode-independent channel options
+ */
+ct_chan_opt_t ct_chan_opt_dflt = {
+ { /* mode register 2 */
+ MD2_FDX, /* full duplex communication */
+ 0, /* empty ADPLL clock rate */
+ MD2_ENCOD_NRZ, /* NRZ encoding */
+ },
+ /* DMA mode FIFO marks */
+ 15, 24, 30, /* rx ready, tx empty, tx full */
+ /* port i/o mode FIFO marks */
+ 15, 16, 30, /* rx ready, tx empty, tx full */
+};
+
+/*
+ * Default HDLC options
+ */
+ct_opt_hdlc_t ct_opt_hdlc_dflt = {
+ { /* mode register 0 */
+ 1, /* CRC preset to all ones (V.41) */
+ 1, /* CRC-CCITT */
+ 1, /* enable CRC */
+ 0, /* disable automatic CTS/DCD */
+ MD0_MODE_HDLC, /* HDLC mode */
+ },
+ { /* mode register 1 */
+ MD1_ADDR_NOCHK, /* do not check address field */
+ },
+ CTL_IDLE_PTRN | CTL_UDRN_ABORT | CTL_RTS_INV, /* control register */
+ 0, 0, /* empty sync/address registers 0,1 */
+ CLK_LINE, /* receive clock source: RXC line input */
+ CLK_LINE, /* transmit clock source: TXC line input */
+};
+
+/*
+ * Default E1/G.703 options
+ */
+ct_opt_g703_t ct_opt_g703_dflt = {
+ 1, /* HDB3 enable */
+ 0, /* precoder disable */
+ GTEST_DIS, /* test disabled, normal operation */
+ 0, /* CRC4 disable */
+ 0, /* CCS signaling */
+ 0, /* low gain */
+ 0, /* no raw mode */
+ 0, /* no PCM2 precoder compatibility */
+ 2048, /* data rate 2048 kbit/sec */
+};
diff --git a/sys/dev/ctau/ctau2fw.h b/sys/dev/ctau/ctau2fw.h
new file mode 100644
index 000000000000..6d43f9725858
--- /dev/null
+++ b/sys/dev/ctau/ctau2fw.h
@@ -0,0 +1,498 @@
+/*
+ * DO NOT EDIT MANUALLY!
+ * This code was generated by mkfw utility
+ * from the file `ctau2.dat'
+ *
+ * Cronyx Id: ctau2fw.h,v 1.1 2002/06/03 10:19:39 rik Exp $
+ * $FreeBSD$
+ */
+long ctau2_fw_len = 98448;
+
+const char *ctau2_fw_version = "1.0";
+const char *ctau2_fw_date = "22.08.01";
+const char *ctau2_fw_copyright = "Copyright (C) 2001 Cronyx Engineering.";
+
+const unsigned char ctau2_fw_data[] = {
+ 79,231,255,255,98,255,57,0,0,255,255,255,255,255,255,255,255,255,255,
+ 255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,
+ 255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,
+ 255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,
+ 255,255,255,255,255,255,255,255,255,255,160,12,16,1,51,80,6,202,64,
+ 25,0,0,83,96,10,76,129,9,50,65,6,200,0,0,25,32,3,100,128,72,148,1,
+ 0,15,12,144,1,51,0,0,166,202,20,25,32,3,102,128,12,148,41,50,64,6,
+ 192,4,152,48,2,101,160,12,152,1,176,248,0,0,20,192,2,80,0,0,10,64,
+ 1,40,128,2,80,0,0,10,64,1,48,0,0,10,64,1,40,0,0,5,160,0,0,14,128,2,
+ 0,15,18,128,2,80,0,0,5,192,0,0,40,0,0,5,160,0,0,20,128,1,80,0,0,10,
+ 160,0,0,20,128,5,160,0,0,20,128,2,192,255,0,0,4,0,1,16,0,0,2,64,0,
+ 0,8,0,0,2,64,0,0,8,0,60,252,0,15,1,48,0,0,2,64,0,0,8,0,1,32,0,0,8,
+ 128,0,17,128,0,0,16,0,0,4,192,0,3,32,0,1,128,1,16,0,0,2,128,0,0,16,
+ 0,1,16,0,0,2,64,0,0,232,252,0,0,5,8,0,0,20,160,2,84,128,10,0,0,10,
+ 64,1,40,0,0,4,132,160,0,0,16,0,0,2,208,1,10,64,32,32,0,17,32,0,0,4,
+ 0,0,16,16,2,14,192,1,8,0,0,7,32,4,4,128,0,1,2,64,80,0,0,40,0,0,5,168,
+ 0,0,248,255,0,0,5,128,0,0,20,0,4,8,0,0,1,128,8,16,129,4,0,1,16,0,0,
+ 2,0,3,68,32,0,9,64,0,6,32,0,0,4,16,0,0,152,0,0,2,64,0,0,32,1,1,32,
+ 8,4,128,0,0,136,0,0,1,0,0,1,8,0,0,1,0,2,250,0,52,64,0,10,2,0,8,184,
+ 251,0,74,152,255,0,74,152,255,0,74,152,255,0,53,11,0,9,152,32,0,7,
+ 136,253,0,52,192,3,2,0,8,30,0,8,192,251,0,53,3,0,9,24,0,8,40,253,0,
+ 53,3,0,9,24,0,8,40,253,0,1,52,1,0,70,140,249,0,2,16,0,70,136,255,0,
+ 74,152,255,8,0,1,17,0,70,163,253,0,2,10,0,70,229,248,0,1,60,0,71,88,
+ 252,4,0,1,16,0,70,200,251,0,1,32,2,0,70,184,255,16,0,16,208,0,27,4,
+ 0,26,24,255,0,17,192,0,55,88,255,0,17,192,0,55,88,255,12,0,16,192,
+ 0,55,50,249,4,0,17,40,0,26,48,18,0,25,64,248,8,0,16,48,0,27,60,0,26,
+ 96,252,0,46,48,0,26,137,253,8,0,45,48,0,26,144,252,0,65,64,3,0,6,156,
+ 248,0,66,3,0,6,152,252,0,66,3,0,6,152,252,8,0,65,3,0,6,163,255,0,74,
+ 205,250,0,65,192,0,0,2,0,5,120,255,4,0,73,216,251,0,74,152,255,0,4,
+ 208,0,68,84,254,0,4,192,0,68,16,251,0,4,192,0,68,16,251,4,0,3,192,
+ 0,68,99,252,12,0,4,136,0,67,13,254,0,4,48,0,68,152,252,8,0,73,144,
+ 255,0,74,152,255,0,1,180,0,46,16,0,6,32,0,15,52,251,0,1,48,32,0,70,
+ 184,252,0,1,48,0,71,152,252,8,0,0,48,16,0,70,179,255,0,1,128,32,0,
+ 45,192,68,0,5,128,49,0,14,245,249,0,1,60,0,46,240,0,6,224,1,0,14,168,
+ 253,4,0,0,16,32,0,45,192,0,6,128,1,0,14,104,254,0,1,32,0,46,192,0,
+ 6,128,1,0,14,8,249,0,1,132,16,0,7,1,0,4,16,0,35,8,0,18,140,250,0,74,
+ 152,255,0,74,152,255,4,0,1,66,0,70,139,250,12,0,0,48,64,0,7,140,16,
+ 0,4,136,0,34,96,4,0,17,189,254,0,1,60,0,8,15,0,4,48,0,35,120,64,0,
+ 17,232,248,8,0,0,32,8,0,7,12,0,4,192,128,0,34,96,0,18,120,255,0,1,
+ 128,0,8,12,0,4,192,2,0,34,96,0,18,248,255,0,1,4,0,3,90,16,0,0,8,0,
+ 6,16,0,37,13,0,11,1,32,0,2,192,255,0,6,24,0,48,12,0,16,72,250,0,2,
+ 16,0,2,16,0,9,192,0,37,12,0,16,16,250,8,0,0,128,0,3,88,8,0,8,192,0,
+ 37,12,0,16,234,252,0,1,128,8,0,2,24,8,0,0,96,66,0,6,136,0,36,64,4,
+ 0,10,140,129,1,0,1,136,253,0,1,60,0,3,30,0,1,120,0,6,48,0,37,3,0,11,
+ 15,224,129,0,1,168,255,4,0,0,48,0,3,24,16,0,0,96,0,7,128,0,49,12,128,
+ 1,0,1,41,250,0,1,48,66,0,2,152,0,1,96,0,7,2,0,49,12,128,1,0,1,24,254,
+ 16,0,73,204,251,32,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,
+ 128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,0,15,32,0,0,4,128,0,0,16,
+ 0,0,2,64,0,0,8,0,0,1,32,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,
+ 0,4,0,0,152,255,0,74,152,255,44,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,
+ 0,1,32,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,0,15,32,0,0,
+ 4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,128,0,0,16,0,0,2,64,0,0,
+ 8,0,0,1,32,0,0,4,0,0,227,248,4,0,73,141,254,40,0,0,4,128,0,0,16,0,
+ 0,2,64,0,0,8,0,0,1,32,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,
+ 4,0,15,32,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,128,0,0,16,
+ 0,0,2,64,0,0,8,0,0,1,32,0,0,4,0,0,144,255,0,74,152,255,40,0,0,4,128,
+ 0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,
+ 1,32,0,0,4,0,15,32,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,
+ 128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,0,0,144,255,0,74,152,255,
+ 0,74,152,255,0,2,32,0,70,184,255,0,74,152,255,0,74,152,255,8,0,4,2,
+ 0,3,8,0,62,48,253,0,20,16,0,3,4,0,19,16,0,5,128,0,18,128,192,254,0,
+ 16,2,0,29,128,0,10,8,0,13,48,255,0,15,128,0,3,8,0,3,4,0,19,8,128,0,
+ 5,1,0,3,4,0,13,137,251,0,2,8,0,6,8,0,4,16,0,3,1,0,37,4,0,2,34,0,0,
+ 5,0,6,48,252,0,2,8,0,16,64,0,44,1,0,6,208,254,0,10,64,0,48,32,0,11,
+ 128,48,249,0,7,2,0,65,184,255,0,74,152,255,0,6,4,0,66,152,251,0,1,
+ 16,0,71,152,254,0,74,152,255,0,74,152,255,0,74,152,255,0,74,152,255,
+ 0,74,152,255,0,74,152,255,0,69,1,0,3,152,254,0,74,152,255,0,1,64,0,
+ 71,220,255,0,74,152,255,0,74,152,255,0,74,152,255,0,1,32,0,54,32,0,
+ 15,184,255,0,6,16,0,38,8,0,26,8,254,0,1,16,0,52,32,0,17,152,252,0,
+ 2,8,0,61,32,0,7,244,251,0,2,4,0,14,16,0,54,200,250,0,2,64,0,70,216,
+ 255,0,74,152,255,2,0,52,128,0,19,26,255,2,0,3,2,0,50,1,0,2,8,0,13,
+ 252,2,0,4,32,4,0,5,32,0,38,2,0,10,128,0,6,128,146,251,0,1,160,0,1,
+ 2,128,2,0,3,40,0,1,1,0,31,6,0,3,64,0,1,12,2,0,2,16,0,3,64,0,7,88,255,
+ 0,1,40,0,3,10,0,0,130,80,0,0,12,0,0,1,32,0,1,16,0,4,16,0,0,1,0,22,
+ 128,32,0,2,144,0,0,128,8,0,1,1,0,5,144,0,1,128,0,2,176,253,0,6,8,0,
+ 1,2,0,0,8,0,10,64,0,25,32,0,18,128,0,2,240,253,0,1,16,0,4,128,0,0,
+ 16,0,0,2,64,0,0,8,0,9,4,0,22,32,0,23,40,251,0,6,64,0,66,216,251,0,
+ 12,8,0,60,16,255,0,74,152,255,4,0,55,4,0,16,137,254,8,0,73,178,253,
+ 0,49,64,0,20,2,0,1,184,249,0,74,152,255,0,67,1,0,4,128,0,0,255,0,74,
+ 152,255,0,1,192,0,15,2,0,54,16,249,0,74,152,255,0,74,152,255,0,44,
+ 32,0,14,128,0,12,176,255,0,74,152,255,0,45,128,0,14,6,0,11,240,255,
+ 0,44,128,5,0,14,6,0,11,120,250,0,61,6,4,0,10,184,251,0,44,96,128,0,
+ 13,128,7,0,11,136,255,0,61,6,0,11,248,255,0,45,4,1,0,13,70,2,0,10,
+ 200,253,0,25,160,1,0,16,32,0,21,8,0,5,228,248,0,25,128,1,0,47,254,
+ 0,44,128,129,0,27,16,254,8,0,44,4,0,27,163,248,0,67,96,34,0,4,205,
+ 254,0,25,96,0,0,1,0,15,96,128,0,20,120,0,5,112,255,4,0,66,96,0,5,216,
+ 253,0,26,144,0,17,4,1,0,19,96,0,5,24,253,16,0,8,104,68,0,5,208,0,55,
+ 240,253,0,9,96,0,6,192,0,55,56,249,0,9,64,0,6,192,0,55,24,251,12,0,
+ 8,96,33,0,5,192,0,55,66,253,4,0,8,96,4,0,6,72,0,54,48,249,8,0,8,120,
+ 64,0,5,48,0,55,88,252,0,9,96,64,0,62,233,252,8,0,8,96,2,0,62,208,249,
+ 16,0,0,52,0,6,104,68,0,8,64,35,4,0,36,128,194,0,11,224,251,0,1,48,
+ 0,6,96,0,63,248,250,0,1,48,0,6,64,0,50,2,0,11,248,248,12,0,0,48,0,
+ 6,96,33,0,9,32,4,0,37,64,4,0,10,162,252,4,0,1,33,0,5,96,4,0,9,32,0,
+ 38,32,4,0,10,168,248,8,0,0,12,0,6,120,64,0,8,192,3,2,0,36,128,5,0,
+ 11,16,255,0,9,96,64,0,49,6,0,11,137,252,8,0,8,96,2,0,9,10,1,0,37,38,
+ 1,0,10,56,248,16,0,19,64,35,4,0,36,128,0,12,228,250,0,74,152,255,0,
+ 62,4,0,10,216,251,12,0,20,32,4,0,37,22,0,11,227,251,4,0,20,32,0,38,
+ 70,2,0,10,169,254,0,20,192,3,2,0,36,128,7,0,11,102,250,0,61,6,0,11,
+ 248,255,16,0,20,10,1,0,37,6,8,0,10,120,253,16,0,6,64,3,0,1,1,0,34,
+ 128,0,3,64,0,6,128,0,12,32,253,0,8,3,0,64,168,252,0,8,3,0,1,12,0,49,
+ 2,0,10,192,250,12,0,7,3,0,1,128,8,0,34,64,8,0,2,35,4,0,5,16,0,11,26,
+ 248,4,0,7,32,2,0,0,12,0,35,32,2,0,2,16,1,0,5,32,0,11,160,252,8,0,6,
+ 192,0,2,15,4,0,33,128,7,0,2,192,0,6,128,1,4,0,10,48,255,0,8,3,0,1,
+ 12,4,0,60,241,253,8,0,7,83,0,1,12,0,35,32,8,0,2,16,4,0,5,6,8,0,10,
+ 96,254,0,24,1,32,0,25,64,0,3,32,0,0,4,128,34,16,0,10,132,248,0,25,
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+ 16,0,0,64,0,3,32,0,1,64,0,0,4,16,0,16,8,48,0,4,6,0,2,4,0,15,136,249,
+ 128,0,0,164,128,0,0,16,0,2,8,0,0,160,0,2,128,128,8,128,2,0,1,128,144,
+ 0,0,4,0,0,1,4,0,18,4,0,0,128,0,0,4,64,0,0,136,0,1,32,2,0,0,80,0,2,
+ 36,0,8,144,253,32,0,20,128,0,1,1,0,48,176,254,0,1,32,0,14,32,0,6,128,
+ 0,20,8,0,0,128,0,23,176,253,0,74,152,255,0,74,152,255,8,0,73,178,253,
+ 0,74,152,255,0,73,128,16,255,0,16,1,0,47,128,0,7,8,255,0,74,220,251,
+ 0,1,8,0,0,1,0,69,24,254,0,28,8,0,44,24,255,0,1,16,0,18,64,0,2,128,
+ 0,47,80,250,0,74,152,255,0,74,152,255,0,74,152,255,0,74,152,255,0,
+ 74,152,255,0,74,152,255,0,74,152,255,0,74,152,255,0,74,152,255,0,74,
+ 152,255,0,14,4,0,58,216,251,0,74,152,255,0,74,152,255,8,0,73,129,254,
+ 0,14,48,34,0,57,187,252,0,14,60,0,58,224,251,4,0,13,48,0,58,202,249,
+ 0,14,48,0,58,168,255,16,0,71,4,0,0,136,251,0,74,152,255,0,73,32,152,
+ 253,12,0,71,176,0,0,202,250,4,0,71,48,1,248,248,16,0,71,60,8,176,248,
+ 0,72,48,0,0,185,253,0,72,48,18,136,253,0,19,26,0,51,4,0,0,56,250,0,
+ 19,24,0,52,16,24,255,0,74,152,255,8,0,71,128,16,137,255,0,19,64,8,
+ 0,51,17,179,249,0,19,6,0,51,60,0,0,64,248,4,0,19,16,0,50,32,0,0,202,
+ 251,0,20,1,0,50,16,33,136,253,0,24,41,0,46,52,0,1,251,0,25,8,0,45,
+ 32,32,56,255,0,24,8,0,46,48,0,0,32,252,4,0,23,128,4,0,45,32,64,146,
+ 255,12,0,71,16,2,224,250,0,24,7,8,0,45,60,32,160,253,8,0,23,12,4,0,
+ 47,73,250,0,24,140,0,46,16,65,24,254,0,27,4,0,30,4,0,11,4,33,200,249,
+ 0,74,152,255,0,72,32,8,56,253,4,0,71,16,2,202,248,12,0,26,48,0,30,
+ 48,0,12,17,192,249,0,27,60,16,0,29,60,16,0,10,60,0,0,240,251,8,0,26,
+ 48,0,30,48,0,11,32,0,0,161,255,0,27,48,0,30,48,0,11,48,18,136,254,
+ 0,7,64,0,2,1,0,6,2,0,31,64,8,1,0,16,148,8,56,250,0,19,24,0,53,24,254,
+ 0,19,24,0,51,16,32,8,253,4,0,18,152,8,0,31,11,1,0,17,1,225,249,12,
+ 0,7,99,0,1,140,4,0,5,88,8,0,31,17,1,0,16,128,64,251,250,0,7,192,3,
+ 0,1,15,0,6,30,0,31,192,2,0,17,44,0,0,184,254,8,0,7,3,0,1,12,0,6,24,
+ 16,0,31,3,2,0,16,48,0,0,90,249,0,8,3,0,1,12,0,6,24,1,0,31,34,0,17,
+ 48,66,96,253,0,1,4,128,0,0,16,0,0,2,64,0,11,64,0,24,4,128,0,0,16,0,
+ 11,16,0,1,64,0,0,8,0,0,5,8,0,0,20,32,152,251,0,74,152,255,0,69,4,0,
+ 1,16,0,0,136,250,8,0,68,32,8,0,0,128,8,154,255,0,1,48,2,70,200,72,
+ 24,2,19,0,11,19,1,0,22,176,16,38,200,64,0,10,192,0,2,19,96,33,128,
+ 0,2,16,56,255,0,1,60,160,7,240,0,0,30,192,3,1,0,9,192,3,0,23,60,128,
+ 7,240,0,11,240,64,0,0,192,3,122,0,0,11,4,0,0,44,0,0,232,248,4,0,0,
+ 48,0,0,6,192,0,0,24,0,0,3,0,11,3,0,23,48,0,0,6,192,0,11,192,0,2,3,
+ 96,0,0,12,0,1,48,0,0,25,249,0,1,48,0,0,6,192,0,0,24,0,0,3,0,11,3,0,
+ 23,48,0,0,6,192,0,11,192,0,2,3,96,0,0,140,16,0,0,48,66,96,249,0,74,
+ 220,251,32,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,128,0,0,
+ 16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,0,15,32,0,0,4,128,0,0,16,0,0,2,64,
+ 0,0,8,0,0,1,32,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,0,0,
+ 152,255,0,74,152,255,36,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,
+ 0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,0,15,32,0,0,4,128,0,0,
+ 16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,
+ 0,0,4,0,0,235,248,12,0,73,193,250,32,0,0,4,128,0,0,16,0,0,2,64,0,0,
+ 8,0,0,1,32,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,0,15,32,
+ 0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,128,0,0,16,0,0,2,64,
+ 0,0,8,0,0,1,32,0,0,4,0,0,186,253,8,0,73,212,251,32,0,0,4,128,0,0,16,
+ 0,0,2,64,0,0,8,0,0,1,32,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,
+ 0,4,0,15,32,0,0,4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,128,0,0,
+ 16,0,0,2,64,0,0,8,0,0,1,32,0,0,4,0,0,152,255,0,74,152,255,0,24,4,0,
+ 46,48,0,0,168,248,0,74,152,255,0,74,152,255,0,24,8,0,46,32,0,0,48,
+ 253,0,53,1,0,19,136,254,0,2,128,0,41,128,0,0,128,0,25,144,255,0,47,
+ 32,0,25,184,255,0,3,1,0,16,10,0,4,96,0,16,128,0,0,32,1,0,24,88,251,
+ 0,0,1,0,6,2,0,3,32,0,0,8,0,4,8,0,23,32,0,2,16,0,7,32,0,1,64,0,10,200,
+ 252,0,15,8,0,45,16,0,10,85,250,8,1,0,6,2,0,4,1,0,30,4,0,2,128,0,7,
+ 32,0,13,64,253,0,8,2,0,36,16,0,26,184,252,0,14,128,0,58,24,255,0,74,
+ 152,255,0,19,32,0,51,64,16,216,248,0,67,32,0,5,152,253,0,74,152,255,
+ 0,74,152,255,0,74,152,255,0,74,152,255,0,70,16,0,1,64,152,250,8,0,
+ 65,128,0,6,152,255,0,74,152,255,0,73,4,216,255,0,74,152,255,0,74,152,
+ 255,0,53,64,0,19,216,255,0,49,32,0,22,32,152,255,0,20,2,0,27,8,0,2,
+ 2,0,18,164,208,253,0,2,16,0,15,8,0,32,1,0,19,24,254,0,11,2,0,12,2,
+ 0,36,1,0,9,152,252,0,69,16,0,3,136,254,0,74,152,255,0,7,64,0,65,152,
+ 251,0,74,152,255,10,0,45,4,0,5,2,0,0,32,2,0,16,240,255,0,17,32,0,6,
+ 2,0,21,1,0,19,2,64,0,0,8,128,152,248,0,0,3,0,2,128,2,80,0,0,10,32,
+ 0,0,128,1,0,3,16,0,0,80,0,4,8,0,19,8,128,0,0,64,0,1,128,10,0,0,32,
+ 2,0,11,1,32,0,0,164,0,0,208,252,64,2,32,0,0,9,0,0,2,72,64,8,0,0,1,
+ 0,8,64,0,2,8,0,0,144,34,0,17,16,128,8,0,0,2,0,0,2,1,32,0,4,208,8,0,
+ 1,34,0,1,72,8,1,32,2,0,1,176,254,0,6,4,0,38,16,0,4,128,0,0,16,0,19,
+ 251,0,1,8,0,21,2,0,1,8,0,23,2,0,13,16,8,0,4,184,252,0,74,152,255,2,
+ 0,20,1,0,36,64,0,12,128,112,252,0,72,8,80,16,250,2,0,24,4,0,46,128,
+ 112,253,26,0,72,128,10,255,0,4,32,0,68,152,253,0,74,152,255,0,4,4,
+ 0,64,2,0,2,248,255,0,69,32,0,1,128,0,0,176,253,0,74,152,255,0,74,152,
+ 255,0,6,2,0,19,64,0,45,216,249,32,4,16,128,20,64,0,0,8,0,0,1,32,1,
+ 4,0,40,128,0,0,17,36,32,0,0,4,128,0,0,16,0,0,18,0,0,1,96,1,36,128,
+ 4,132,0,0,152,254,0,0,1,32,0,0,128,128,0,0,16,0,0,2,64,0,0,8,0,40,
+ 2,64,0,0,8,0,0,1,32,0,0,4,128,0,0,240,2,10,64,11,40,0,0,5,160,0,0,
+ 48,248,0,0,2,64,0,0,64,0,0,1,32,0,0,4,128,0,0,16,0,61,176,250,0,53,
+ 4,128,0,0,16,0,0,2,64,0,0,8,0,0,1,0,0,1,4,128,4,16,0,0,2,64,0,0,136,
+ 252,0,0,20,128,2,56,0,0,10,64,1,40,0,0,5,160,0,0,45,160,2,84,128,10,
+ 80,1,42,64,5,168,0,0,21,160,2,0,15,21,160,2,84,128,10,208,2,40,0,0,
+ 5,160,0,0,20,128,2,80,0,0,10,192,0,0,40,0,0,3,160,0,0,20,128,2,224,
+ 255,192,12,148,1,34,99,6,204,64,25,40,3,101,160,225,52,129,38,224,
+ 4,154,64,19,112,2,77,160,9,56,1,0,14,192,9,56,1,39,208,4,26,86,25,
+ 40,3,102,192,12,148,1,51,80,6,204,148,25,40,83,102,192,12,152,1,88,
+ 249,255,255,};
diff --git a/sys/dev/ctau/ctaue1fw.h b/sys/dev/ctau/ctaue1fw.h
new file mode 100644
index 000000000000..cb3311cd1d66
--- /dev/null
+++ b/sys/dev/ctau/ctaue1fw.h
@@ -0,0 +1,2066 @@
+/*
+ * DO NOT EDIT MANUALLY!
+ * This code was generated by mkfw utility
+ * from the file `ctaue1.dat'
+ *
+ * Cronyx Id: ctaue1fw.h,v 1.1 2002/06/03 10:19:39 rik Exp $
+ * $FreeBSD$
+ */
+long ctaue1_fw_len = 323982;
+
+const char *ctaue1_fw_version = "1.1";
+const char *ctaue1_fw_date = "10.08.00";
+const char *ctaue1_fw_copyright = "Copyright (C) 2000 Cronyx Engineering.";
+
+const cr_dat_tst_t ctaue1_fw_tvec[] = {
+ {130534,132958}, {134206,136630}, {137878,140302}, {141550,143974},
+ {145222,147646}, {148894,151318}, {152566,154990}, {156238,158662},
+ {159910,162334}, {163582,166006}, {167254,169678}, {170926,173350},
+ {174598,177022}, {178270,180694}, {181942,184366}, {185614,188038},
+ {189286,191710}, {192958,195382}, {196630,199054}, {200302,202726},
+ {203974,206398}, {207646,210070}, {211318,213742}, {214990,217414},
+ {218662,221086}, {222334,224758}, {226006,228430}, {229678,232102},
+ {233350,235774}, {237022,239446}, {240694,243118}, {244366,246790},
+ {248038,250462}, {251710,254134}, {255382,257806}, {259054,261478},
+ {262726,265150}, {266398,268822}, {270070,272494}, {273742,276166},
+ {277414,279838}, {281086,283510}, {284758,287182}, {288430,290854},
+ {292102,294526}, {295774,298198}, {299446,301870}, {303118,305542},
+ {306790,309214}, {310462,312886}, {314134,316558}, {317806,320230},
+ {321478,323902}, {323982,323982},
+};
+
+const unsigned char ctaue1_fw_data[] = {
+ 155,153,97,52,81,185,113,37,97,100,100,36,117,53,32,117,48,101,96,
+ 49,112,48,49,49,113,112,49,48,49,97,117,37,112,112,96,112,53,112,33,
+ 52,100,100,100,116,52,37,100,100,52,112,117,33,52,48,52,36,37,116,
+ 32,49,49,49,117,53,33,49,49,37,37,37,37,49,48,100,100,116,112,96,100,
+ 100,100,100,101,96,100,100,100,100,100,100,100,100,100,100,100,100,
+ 100,100,100,100,36,49,48,49,49,49,113,112,112,96,48,52,52,112,33,100,
+ 100,100,52,112,117,49,49,49,33,52,112,33,48,52,33,116,117,117,100,
+ 100,100,112,53,33,49,49,37,49,49,101,49,36,52,53,49,49,49,49,49,49,
+ 116,36,96,36,100,100,100,52,52,52,52,112,113,48,37,49,37,49,49,49,
+ 36,33,36,49,49,37,53,49,36,37,116,112,96,100,33,53,49,49,49,116,101,
+ 96,100,100,97,97,97,33,53,96,96,112,112,112,48,49,49,100,52,117,48,
+ 49,113,112,112,52,112,112,101,48,52,52,52,100,100,100,52,113,101,100,
+ 100,112,100,48,52,52,112,113,36,37,37,37,49,49,97,52,33,37,49,49,37,
+ 37,37,37,37,36,112,96,97,97,97,100,100,100,117,101,96,100,100,97,97,
+ 97,97,33,53,52,112,112,112,48,49,49,113,113,96,100,100,36,112,112,
+ 112,49,52,53,53,49,113,33,100,100,100,116,101,230,102,36,49,48,49,
+ 113,96,117,37,96,53,100,49,112,36,52,100,100,100,52,112,116,100,100,
+ 112,117,33,52,52,48,52,36,116,32,37,49,49,49,37,53,33,49,49,49,116,
+ 117,32,37,36,37,97,33,53,96,100,100,100,33,113,96,100,100,97,97,97,
+ 97,100,32,49,49,53,52,48,49,49,49,113,49,48,49,49,49,49,49,49,49,49,
+ 49,49,49,49,49,49,49,49,117,117,49,49,100,36,52,52,52,48,36,37,37,
+ 116,32,49,49,49,37,53,33,49,49,37,37,37,116,32,36,101,32,117,117,53,
+ 49,49,49,112,101,100,100,100,97,100,100,113,36,53,101,101,100,100,
+ 100,100,100,36,36,113,33,37,49,49,37,37,37,37,37,116,116,96,97,100,
+ 97,100,100,36,53,100,96,100,100,100,32,96,97,33,53,52,48,113,96,101,
+ 100,100,36,52,112,48,49,113,112,112,112,96,117,37,37,52,52,52,100,
+ 100,36,113,97,36,100,100,52,52,52,37,52,48,52,36,37,37,37,49,49,49,
+ 37,53,33,49,49,101,49,33,37,37,96,52,97,97,97,97,100,100,48,53,100,
+ 96,100,116,96,97,97,97,33,97,97,112,112,112,48,49,49,113,116,32,48,
+ 49,113,112,112,112,112,96,112,48,52,52,52,100,100,100,52,116,36,100,
+ 100,52,52,52,116,36,101,37,49,49,33,37,49,49,49,101,16,177,177,97,
+ 36,100,100,52,112,117,33,112,49,113,48,52,33,37,49,49,49,37,53,33,
+ 49,49,116,117,32,37,37,36,117,33,53,96,97,100,100,100,97,101,96,100,
+ 100,33,117,53,96,33,53,32,112,96,37,48,49,49,113,100,53,49,49,113,
+ 112,112,112,48,33,97,100,100,37,37,100,100,100,100,116,36,100,100,
+ 100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,48,33,
+ 49,113,49,33,37,37,37,116,97,97,33,53,96,100,100,100,97,101,96,100,
+ 100,97,97,33,53,32,53,112,117,117,117,101,100,100,36,52,112,48,49,
+ 113,48,49,113,52,97,101,113,49,49,49,49,49,49,97,96,116,48,100,100,
+ 100,97,97,97,97,33,53,53,112,48,113,48,49,49,97,36,97,100,100,36,112,
+ 49,97,112,96,101,52,100,52,112,49,49,49,33,112,117,49,49,33,52,52,
+ 52,112,117,97,33,37,37,37,49,49,97,36,49,97,100,100,32,37,101,33,37,
+ 36,37,97,97,97,97,100,100,100,117,101,96,100,100,113,100,96,97,33,
+ 48,101,112,112,112,48,49,49,100,37,49,48,49,53,112,112,112,112,96,
+ 32,37,52,52,52,100,100,100,52,37,49,100,100,52,52,52,52,52,48,100,
+ 36,37,37,37,49,49,49,37,53,33,49,49,37,37,37,53,97,113,97,100,100,
+ 96,97,100,100,100,37,76,68,100,53,53,49,49,37,116,117,32,116,97,52,
+ 33,101,96,97,100,100,100,49,49,97,100,36,117,53,96,97,33,97,97,96,
+ 37,112,48,49,49,113,96,113,49,49,113,96,117,37,112,96,112,48,52,112,
+ 33,100,100,100,52,116,36,100,100,52,52,100,52,100,96,48,49,113,97,
+ 33,49,49,49,49,53,33,49,49,49,49,49,49,49,49,49,49,49,49,49,49,49,
+ 49,33,33,48,49,49,49,49,96,97,33,97,112,112,96,37,48,49,49,113,96,
+ 113,49,49,113,112,112,96,37,96,112,36,112,117,117,49,49,49,33,116,
+ 36,100,100,52,100,100,52,101,48,52,117,100,100,100,100,100,100,32,
+ 96,36,49,48,49,49,113,112,112,112,96,101,37,52,100,52,100,100,100,
+ 112,97,36,100,100,100,116,53,52,52,112,97,33,49,37,116,100,100,100,
+ 32,53,33,49,49,49,37,37,37,116,117,112,96,97,97,97,100,100,48,53,100,
+ 96,100,100,97,97,113,96,97,53,97,112,112,112,48,49,49,113,52,112,48,
+ 49,97,49,49,112,112,96,101,49,52,52,52,100,100,36,113,117,33,100,100,
+ 52,52,52,52,52,48,52,36,37,37,37,49,49,49,37,53,33,49,49,37,37,37,
+ 37,37,36,37,97,97,97,97,100,100,100,33,48,49,49,49,49,96,97,101,112,
+ 116,48,49,49,112,48,49,49,113,32,110,108,100,101,96,100,100,33,117,
+ 53,32,53,49,101,96,49,112,48,49,49,113,96,48,100,100,116,117,37,112,
+ 112,96,112,48,112,33,52,100,100,100,52,116,36,100,100,52,112,117,33,
+ 52,48,116,37,37,116,32,49,49,49,117,36,117,100,100,32,37,37,37,49,
+ 48,100,100,100,113,96,100,100,100,100,101,96,100,100,100,100,100,100,
+ 100,100,100,100,100,100,100,100,100,100,36,49,48,49,53,49,112,112,
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+ 100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,
+ 100,100,100,100,100,100,100,100,100,32,37,49,49,49,49,49,96,100,97,
+ 100,117,100,100,100,100,100,100,100,97,100,100,32,96,100,100,97,97,
+ 33,112,53,49,49,49,49,49,49,49,49,49,113,112,112,48,33,100,100,100,
+ 52,100,100,100,33,53,49,49,49,49,96,100,100,100,100,97,100,100,100,
+ 36,53,96,100,100,100,100,100,100,36,112,53,49,49,113,32,100,52,36,
+ 32,36,48,49,49,49,49,49,49,97,117,117,117,101,52,100,100,112,117,33,
+ 112,49,49,49,49,49,49,49,117,37,37,49,49,49,49,49,49,49,96,32,49,49,
+ 49,49,49,49,49,96,100,100,97,100,97,36,112,112,53,32,48,49,49,49,49,
+ 49,49,113,48,49,49,49,113,48,97,37,32,52,52,100,100,100,100,100,100,
+ 100,52,100,100,36,112,32,100,52,52,52,32,117,49,49,49,49,49,49,49,
+ 33,52,52,32,117,49,49,116,117,117,100,32,49,49,33,88,51,116,117,100,
+ 100,100,100,100,112,117,117,117,49,49,116,117,117,100,97,100,100,100,
+ 100,100,100,36,48,49,33,117,117,100,36,117,53,113,53,49,49,49,49,49,
+ 49,49,49,49,49,49,113,53,49,97,101,100,100,100,100,100,100,100,100,
+ 100,100,100,52,52,100,113,101,100,112,117,117,49,49,49,49,49,49,49,
+ 49,49,49,113,116,49,113,48,49,49,49,33,100,100,100,100,100,100,100,
+ 100,100,100,117,117,117,117,100,100,100,36,112,112,48,49,49,49,49,
+ 49,49,113,112,117,53,49,49,49,49,49,49,97,101,100,100,100,100,100,
+ 100,100,100,100,100,32,49,49,49,49,49,49,117,49,49,49,97,85,229,228,
+ 100,100,100,100,100,100,100,100,100,100,100,36,48,49,49,49,49,49,49,
+ 49,49,49,49,113,48,37,49,117,49,49,116,100,97,117,100,100,100,100,
+ 100,100,100,100,117,100,100,100,117,100,100,100,100,36,117,53,49,49,
+ 49,49,49,49,113,117,53,113,101,101,100,112,117,49,49,117,49,49,49,
+ 49,49,49,49,117,117,117,117,117,49,49,116,117,117,117,117,100,100,
+ 100,100,100,100,100,100,100,112,117,117,49,49,96,117,100,117,100,100,
+ 100,100,100,100,100,100,100,117,117,100,100,100,100,100,100,100,100,
+ 100,100,100,100,100,100,100,36,101,117,37,53,49,49,49,117,117,117,
+ 33,100,100,36,117,53,49,49,49,49,49,116,117,117,117,100,36,117,117,
+ 53,113,48,49,49,49,49,49,49,33,100,100,96,117,53,49,97,117,101,116,
+ 101,100,100,100,100,100,100,100,100,100,100,100,116,101,100,112,49,
+ 49,49,49,49,49,49,49,49,49,49,49,37,37,113,116,49,49,116,117,117,100,
+ 100,100,100,100,100,100,100,100,100,52,117,100,52,100,100,100,100,
+ 32,49,49,49,49,49,49,49,49,49,113,117,117,117,53,49,49,49,33,52,52,
+ 100,100,100,100,100,100,100,52,116,117,101,100,100,100,100,100,100,
+ 112,49,49,49,49,49,49,49,49,49,49,49,96,100,100,100,100,100,100,117,
+ 100,100,100,112,93,51,33,117,100,100,100,100,100,52,52,52,52,100,100,
+ 100,32,117,49,33,100,100,100,100,100,100,100,52,100,100,52,100,100,
+ 100,49,32,37,49,37,49,49,49,49,49,49,49,49,49,49,49,49,49,113,48,96,
+ 97,100,97,100,100,100,100,100,100,100,116,117,101,113,101,100,112,
+ 117,36,36,48,49,49,49,49,49,49,49,113,48,49,113,48,49,49,33,52,52,
+ 100,100,100,100,100,100,100,100,100,116,52,97,33,37,49,49,49,113,112,
+ 112,36,49,49,49,49,49,49,113,36,112,101,100,100,100,100,100,100,100,
+ 100,100,100,100,100,100,100,100,100,100,100,100,97,100,100,100,100,
+ 100,112,113,48,49,49,80,229,228,100,100,100,100,100,97,100,100,97,
+ 97,100,100,100,100,100,36,48,49,49,49,49,49,49,49,49,52,48,37,49,49,
+ 96,100,49,97,100,100,100,100,100,100,100,100,100,100,100,52,117,100,
+ 100,100,100,116,32,53,49,49,49,49,49,49,49,113,48,101,112,48,49,33,
+ 52,100,100,52,100,100,100,100,100,100,100,52,52,52,52,52,100,100,32,
+ 37,37,37,37,49,49,49,49,49,49,49,113,112,116,117,117,49,49,36,117,
+ 36,53,49,49,49,49,49,49,49,49,97,116,117,100,52,100,100,100,100,100,
+ 100,32,49,49,49,49,49,49,49,37,49,113,36,49,49,49,49,49,49,117,96,
+ 100,100,96,53,49,49,49,49,49,37,37,37,37,49,49,49,96,117,100,32,49,
+ 49,49,49,49,49,49,37,49,49,37,49,49,113,36,96,97,100,97,100,100,100,
+ 100,100,100,100,100,100,100,100,100,100,52,36,112,48,113,48,49,49,
+ 49,49,49,49,49,117,117,113,116,49,49,116,53,33,33,100,100,100,100,
+ 100,100,100,100,52,100,100,52,100,100,100,32,37,37,49,49,49,49,49,
+ 49,49,49,49,53,101,112,96,97,100,100,100,52,52,52,97,100,100,100,100,
+ 100,100,52,33,116,49,49,49,49,49,49,49,49,49,49,49,49,49,49,49,49,
+ 49,49,49,113,48,49,49,49,49,49,116,52,100,100,36,92,51,48,117,100,
+ 100,100,100,117,96,100,100,100,48,113,53,48,113,32,53,49,49,49,49,
+ 49,49,113,117,117,53,116,97,100,36,96,49,96,117,101,100,100,100,100,
+ 100,100,116,117,117,117,37,53,49,33,112,117,117,117,49,49,49,49,49,
+ 49,49,117,33,52,112,33,100,100,32,37,117,116,117,100,100,100,100,100,
+ 100,100,117,117,32,116,117,100,36,117,117,117,117,53,49,49,49,49,49,
+ 49,113,53,96,97,97,37,100,116,117,37,112,32,97,100,100,100,100,100,
+ 100,52,116,117,117,117,101,100,112,117,117,101,116,49,49,49,49,49,
+ 49,49,117,117,117,117,117,49,49,116,117,117,32,116,100,100,52,81,229,
+ 228,100,100,100,100,112,117,117,117,117,49,49,116,117,117,117,117,
+ 100,100,100,100,100,100,100,117,117,97,117,117,100,36,117,117,100,
+ 117,53,49,49,49,49,49,49,113,101,32,117,53,96,100,116,117,117,37,117,
+ 48,49,49,49,49,49,49,97,49,96,117,101,100,100,100,100,112,117,49,49,
+ 49,49,49,49,49,49,49,49,49,49,49,49,49,49,49,49,49,49,49,49,49,49,
+ 49,49,49,116,117,32,37,37,49,49,96,33,117,117,53,49,49,49,49,49,49,
+ 113,53,116,33,117,53,49,97,117,117,117,117,101,100,100,100,100,100,
+ 100,116,101,100,52,113,101,100,112,49,49,49,37,49,49,113,100,53,49,
+ 49,49,113,53,48,49,49,49,100,116,37,100,52,96,101,100,100,100,100,
+ 100,100,116,117,117,37,117,48,49,33,112,36,112,117,49,49,49,49,49,
+ 49,49,117,117,117,117,97,101,100,32,116,117,117,117,100,100,100,100,
+ 100,100,100,117,32,37,116,32,49,49,96,97,53,117,53,49,49,49,49,49,
+ 49,113,117,53,32,117,53,49,97,117,117,117,117,101,100,100,100,100,
+ 100,100,116,37,112,112,112,33,49,117,117,33,52,96,48,49,49,49,49,49,
+ 49,37,117,117,117,117,49,49,116,117,117,49,117,100,100,100,100,100,
+ 100,100,117,117,117,117,117,100,36,117,117,53,32,53,49,49,101,92,59,
+ 101,113,12,110,48,49,89,27,179,};
diff --git a/sys/dev/ctau/ctaufw.h b/sys/dev/ctau/ctaufw.h
new file mode 100644
index 000000000000..354f2bac974d
--- /dev/null
+++ b/sys/dev/ctau/ctaufw.h
@@ -0,0 +1,848 @@
+/*
+ * DO NOT EDIT MANUALLY!
+ * This code was generated by mkfw utility
+ * from the file `ctau.dat'
+ *
+ * Cronyx Id: ctaufw.h,v 1.1 2002/06/03 10:19:40 rik Exp $
+ * $FreeBSD$
+ */
+long ctau_fw_len = 131234;
+
+const char *ctau_fw_version = "1.1";
+const char *ctau_fw_date = "18.02.97";
+const char *ctau_fw_copyright = "Copyright (C) 1997 Cronyx Engineering.";
+
+const cr_dat_tst_t ctau_fw_tvec[] = {
+ { 65066, 66278}, { 66314, 67526}, { 67562, 68774}, { 68810, 70022},
+ { 70058, 71270}, { 71306, 72518}, { 72554, 73766}, { 73802, 75014},
+ { 75050, 76262}, { 76298, 77510}, { 77546, 78758}, { 78794, 80006},
+ { 80042, 81254}, { 81290, 82502}, { 82538, 83750}, { 83786, 84998},
+ { 85034, 86246}, { 86282, 87494}, { 87530, 88742}, { 88778, 89990},
+ { 90026, 91238}, { 91274, 92486}, { 92522, 93734}, { 93770, 94982},
+ { 95018, 96230}, { 96266, 97478}, { 97514, 98726}, { 98762, 99974},
+ {100010,101222}, {101258,102470}, {102506,103718}, {103754,104966},
+ {105002,106214}, {106250,107462}, {107498,108710}, {108746,109958},
+ {109994,111206}, {111242,112454}, {112490,113702}, {113738,114950},
+ {114986,116198}, {116234,117446}, {117482,118694}, {118730,119942},
+ {119978,121190}, {121226,122438}, {122474,123686}, {123722,124934},
+ {124970,126182}, {126218,127430}, {127466,128678}, {128714,129926},
+ {129962,131174}, {131234,131234},
+};
+
+const unsigned char ctau_fw_data[] = {
+ 155,153,97,92,102,33,49,48,49,49,113,112,112,112,96,101,97,52,100,
+ 52,100,100,100,48,36,48,100,100,52,116,100,48,52,112,97,33,49,37,116,
+ 100,100,100,112,53,33,49,49,37,37,37,37,116,32,33,97,97,97,97,100,
+ 100,48,113,116,97,100,100,97,97,113,96,97,53,97,112,112,112,48,49,
+ 49,113,100,53,49,49,97,49,97,112,112,96,101,49,52,52,52,100,100,36,
+ 113,36,52,100,100,52,52,52,52,52,48,96,33,37,37,37,49,49,49,117,53,
+ 33,49,49,37,37,37,37,37,116,112,96,97,97,97,100,100,100,101,33,49,
+ 49,49,96,97,97,101,112,116,116,100,100,37,48,49,49,113,53,59,57,97,
+ 96,97,100,100,97,97,97,97,33,53,53,112,48,113,48,49,49,97,37,49,48,
+ 49,49,49,32,112,112,96,37,37,100,52,112,49,49,49,33,37,52,100,100,
+ 52,52,52,52,112,117,97,33,37,37,37,49,49,97,116,48,33,49,49,37,37,
+ 101,33,37,36,37,97,97,97,97,100,100,100,97,101,96,100,100,113,100,
+ 96,97,33,48,101,112,112,112,48,49,49,100,37,49,48,49,53,112,112,112,
+ 112,96,112,48,52,52,52,100,100,100,52,53,32,100,100,52,52,52,52,52,
+ 48,52,36,37,37,37,49,49,49,37,53,33,49,49,37,37,37,53,97,113,97,100,
+ 100,96,97,100,100,100,49,76,68,36,97,48,49,49,37,37,37,37,37,116,116,
+ 96,97,100,97,100,100,36,49,36,49,49,49,96,101,36,97,33,53,113,48,113,
+ 96,101,100,100,36,96,117,101,100,36,112,112,112,96,117,37,37,52,52,
+ 52,100,100,36,49,100,36,49,49,33,52,52,37,52,48,52,36,37,37,37,49,
+ 49,49,117,53,33,49,49,101,49,33,37,37,96,52,97,97,97,97,100,100,48,
+ 53,100,96,100,116,96,97,97,97,33,33,52,112,112,112,48,49,49,113,52,
+ 100,48,49,113,112,112,112,112,96,48,49,52,52,52,100,100,100,52,116,
+ 36,100,100,52,52,52,116,36,101,37,49,49,33,37,49,49,49,53,16,177,177,
+ 97,36,100,100,100,52,52,52,52,112,113,33,37,49,37,49,49,49,116,48,
+ 33,49,49,49,117,37,37,37,116,112,96,100,33,53,49,49,49,96,101,96,100,
+ 100,100,97,97,33,117,53,52,112,112,112,48,49,49,100,37,49,48,49,113,
+ 112,112,52,112,112,101,48,52,52,52,100,100,100,52,37,52,100,100,112,
+ 100,36,52,52,112,113,36,37,37,37,49,49,97,116,117,32,49,49,37,37,37,
+ 37,37,36,37,97,97,97,97,100,100,100,97,101,96,100,100,97,97,97,97,
+ 33,97,97,112,112,112,48,49,49,113,32,100,100,100,100,36,112,112,49,
+ 52,53,100,100,36,52,100,100,100,52,32,179,51,32,49,48,49,49,113,112,
+ 112,112,96,101,37,52,100,52,100,100,100,48,49,32,100,100,52,116,100,
+ 48,52,112,97,33,49,37,116,100,100,100,96,33,96,100,100,32,37,37,37,
+ 116,117,112,96,97,97,97,100,100,48,97,112,53,49,49,96,97,113,96,33,
+ 97,97,112,112,112,48,49,49,113,36,49,49,49,33,52,48,112,112,96,101,
+ 49,52,52,52,100,100,36,113,97,36,100,100,52,52,52,52,52,48,52,36,37,
+ 37,37,49,49,49,101,32,32,49,49,37,37,37,37,37,36,37,97,97,97,97,100,
+ 100,100,97,101,96,100,100,97,97,97,101,112,116,48,49,49,112,48,49,
+ 49,113,37,110,108,116,101,100,100,100,97,97,97,97,33,53,117,113,48,
+ 113,48,49,49,97,37,49,48,49,113,112,113,113,112,112,112,37,100,52,
+ 112,49,49,49,33,116,36,100,100,52,100,52,52,112,117,97,33,37,37,37,
+ 49,49,97,116,48,33,49,49,37,37,101,33,37,117,36,97,97,97,97,100,100,
+ 100,97,101,96,100,36,101,100,96,97,33,53,101,112,112,112,48,49,49,
+ 52,100,100,48,49,53,112,112,112,112,96,112,48,52,52,52,100,100,100,
+ 52,116,36,100,100,100,52,52,52,52,48,52,36,37,37,37,49,49,49,37,52,
+ 48,49,49,37,49,37,53,97,113,97,100,100,96,97,100,100,100,113,77,68,
+ 116,113,37,49,49,37,37,37,37,37,37,97,96,97,100,97,100,100,36,97,33,
+ 49,49,49,96,101,36,97,97,97,53,48,113,96,101,100,100,36,100,32,100,
+ 100,36,112,112,112,96,117,37,37,52,52,52,100,100,36,49,96,36,100,100,
+ 100,52,52,37,52,48,52,36,37,37,37,49,49,49,37,52,36,49,49,52,49,33,
+ 49,37,116,52,97,97,97,97,100,100,48,101,101,100,100,36,53,96,97,97,
+ 33,33,52,112,112,112,48,49,49,113,113,96,100,100,36,112,112,112,112,
+ 96,112,53,52,52,52,100,100,100,52,116,36,100,100,52,52,52,116,36,101,
+ 37,49,49,33,37,49,49,49,53,21,177,177,97,36,100,100,52,52,52,52,52,
+ 112,113,33,37,49,37,49,49,49,116,48,33,49,49,37,37,53,36,37,116,112,
+ 96,100,33,53,49,49,49,96,101,96,100,100,97,97,100,33,117,53,52,112,
+ 112,112,48,49,49,100,113,48,100,100,36,112,112,52,112,96,112,48,52,
+ 52,52,100,100,100,52,116,36,100,100,112,100,36,52,52,112,113,36,37,
+ 37,37,49,49,97,116,48,33,49,113,33,37,37,37,37,36,37,97,97,97,97,100,
+ 100,100,97,101,96,100,100,97,100,97,97,33,100,97,112,112,112,48,49,
+ 49,113,100,32,100,100,36,112,48,113,49,52,53,100,100,36,52,100,100,
+ 100,52,52,230,102,49,49,100,100,36,112,112,112,112,112,48,36,52,100,
+ 52,100,100,100,112,36,52,100,100,52,116,100,48,52,112,33,32,49,37,
+ 116,100,100,100,32,52,48,49,49,37,37,37,37,116,117,112,96,97,97,97,
+ 100,100,48,101,96,97,100,100,97,97,113,96,33,53,52,112,112,48,49,49,
+ 49,113,112,49,48,49,97,113,100,37,48,97,101,97,100,52,52,100,100,100,
+ 37,97,100,100,100,49,52,52,52,52,48,52,36,37,37,37,49,49,49,37,53,
+ 33,49,49,37,37,37,37,37,36,37,97,97,97,97,100,100,100,113,96,97,100,
+ 100,97,97,97,100,100,97,32,49,49,113,48,49,49,113,117,58,57,49,100,
+ 96,100,100,97,97,97,97,33,53,53,112,48,113,48,49,49,97,37,49,48,49,
+ 113,112,49,97,112,96,37,37,100,52,112,49,49,49,33,116,36,100,100,52,
+ 52,52,100,112,117,97,33,37,37,37,49,49,97,116,48,33,49,49,37,37,101,
+ 33,37,36,37,97,97,97,97,100,100,100,33,53,96,100,36,53,32,53,96,33,
+ 53,101,112,112,112,48,49,49,112,37,49,48,49,53,112,112,112,112,96,
+ 112,48,52,52,52,100,100,100,52,97,52,100,100,52,52,52,100,52,48,52,
+ 36,37,37,37,49,49,49,37,53,33,49,49,37,37,37,53,97,113,97,100,100,
+ 96,97,100,100,100,49,73,68,52,97,117,100,100,32,37,37,37,37,116,116,
+ 96,97,100,97,100,100,36,53,100,96,100,100,97,101,36,97,33,53,52,48,
+ 113,96,101,100,100,36,101,113,49,49,113,112,112,112,96,117,37,37,52,
+ 52,52,100,100,36,113,97,36,100,100,52,52,52,37,52,112,97,33,37,37,
+ 49,49,49,49,37,53,33,49,49,52,49,33,37,49,116,52,100,100,97,97,100,
+ 100,48,49,101,96,100,116,96,97,97,97,33,97,97,112,112,112,48,49,49,
+ 113,112,49,48,49,113,112,112,112,112,96,112,48,52,52,52,100,100,100,
+ 52,116,36,100,100,52,52,52,52,100,52,36,48,49,49,37,49,49,49,53,4,
+ 177,177,97,36,100,100,52,52,52,52,52,52,36,33,37,49,37,49,49,49,116,
+ 117,32,49,49,37,53,49,36,37,116,32,96,100,33,53,49,49,49,96,101,96,
+ 100,100,97,97,97,33,117,53,52,48,113,112,48,49,49,116,116,37,48,49,
+ 113,112,112,52,112,96,112,48,52,52,52,100,100,100,52,37,100,100,100,
+ 112,52,113,33,52,112,113,36,37,37,37,49,49,113,33,53,33,49,113,53,
+ 37,37,37,37,36,37,97,97,97,97,100,100,100,49,97,100,100,100,97,97,
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+ 52,52,52,48,52,36,37,37,37,49,49,49,37,53,33,49,49,37,37,37,53,97,
+ 113,33,53,97,53,96,100,100,100,97,28,102,97,42,57,37,100,96,100,100,
+ 97,97,97,97,33,53,53,112,48,113,48,49,49,97,32,49,48,49,113,112,49,
+ 97,48,97,37,37,100,52,112,49,49,49,97,32,116,49,49,33,52,52,52,112,
+ 117,97,33,37,37,37,49,49,97,48,33,36,49,49,37,37,101,33,37,36,37,97,
+ 97,97,97,100,100,100,97,101,96,100,36,101,100,96,97,33,53,101,112,
+ 112,112,48,49,49,53,112,49,48,49,53,112,112,112,112,96,32,37,52,52,
+ 52,100,100,100,116,117,36,100,100,52,52,52,52,52,48,52,36,37,37,37,
+ 49,49,49,49,53,33,49,49,37,37,37,53,97,113,97,49,49,53,96,100,100,
+ 100,117,28,102,32,47,57,113,96,101,100,100,97,97,97,97,36,53,101,112,
+ 48,113,48,49,49,97,53,32,49,49,113,112,49,97,112,96,37,37,100,52,112,
+ 49,49,49,33,116,36,100,100,52,52,52,52,112,117,97,33,37,37,37,49,49,
+ 97,33,53,33,49,49,37,37,101,33,37,36,37,97,97,97,97,100,100,100,52,
+ 97,100,100,36,101,49,53,96,36,53,101,112,112,112,48,49,49,100,97,48,
+ 49,49,53,112,112,112,112,96,112,48,52,52,52,100,100,100,52,53,36,49,
+ 49,33,52,52,52,52,48,52,36,37,37,37,49,49,49,37,116,117,100,100,32,
+ 37,37,53,97,113,97,100,100,96,97,100,100,100,49,28,102,117,42,57,37,
+ 100,96,100,100,97,97,97,97,33,53,53,112,48,113,48,49,49,97,100,49,
+ 48,49,113,112,49,97,112,96,37,37,100,52,112,49,49,49,33,116,36,100,
+ 100,52,52,52,52,52,112,97,33,37,37,37,49,49,97,116,48,33,49,49,37,
+ 37,37,116,32,36,37,97,97,97,97,100,100,100,113,101,100,100,36,37,53,
+ 53,96,36,53,101,112,112,112,48,49,49,100,37,49,48,49,53,112,112,112,
+ 112,96,32,37,52,52,52,100,100,100,116,117,36,100,100,52,52,52,52,52,
+ 48,96,33,37,37,37,49,49,49,101,97,53,49,49,37,37,37,53,97,113,97,100,
+ 100,96,97,100,100,100,37,28,102,52,42,57,33,100,100,100,100,97,97,
+ 97,97,33,53,101,112,48,113,48,49,49,97,37,49,48,49,113,112,49,97,112,
+ 96,37,53,49,33,112,49,49,49,33,97,97,100,100,52,52,52,52,112,117,97,
+ 33,37,37,37,49,49,97,116,117,97,100,100,32,37,101,33,37,36,37,97,97,
+ 97,97,100,100,100,97,101,96,100,36,101,100,96,97,33,53,101,112,112,
+ 112,48,49,49,101,52,100,48,49,53,112,112,112,112,96,112,48,52,52,52,
+ 100,100,100,52,53,33,49,49,33,52,52,52,52,48,52,36,37,37,37,49,49,
+ 49,37,53,33,49,49,37,37,37,53,97,113,97,112,100,96,97,100,100,100,
+ 33,8,102,49,42,57,53,100,53,49,49,96,97,97,97,33,53,101,112,48,113,
+ 48,49,49,97,37,49,48,49,113,112,49,97,112,96,37,37,100,52,112,49,49,
+ 49,97,52,48,49,49,33,52,52,52,52,112,97,33,37,37,37,49,49,97,116,48,
+ 33,49,49,37,37,101,36,37,36,37,97,97,97,97,100,100,100,101,112,96,
+ 100,36,101,100,96,97,33,53,101,112,112,112,48,49,49,49,33,97,100,100,
+ 48,112,112,112,112,96,112,48,52,52,52,100,100,100,116,117,36,100,100,
+ 52,52,52,52,52,48,52,36,37,37,37,49,49,49,37,96,32,49,49,37,37,37,
+ 53,97,113,97,100,49,53,96,100,100,100,53,8,102,112,47,57,49,100,96,
+ 100,100,97,97,97,97,33,53,53,112,48,113,48,49,49,97,37,49,48,49,113,
+ 112,49,97,112,96,37,37,100,52,112,49,49,49,33,116,36,100,100,52,52,
+ 52,52,112,117,97,33,37,37,37,49,49,97,52,100,48,49,49,37,37,101,33,
+ 37,36,37,97,97,97,97,100,100,100,97,101,96,100,36,101,36,97,97,33,
+ 53,101,112,112,112,48,49,49,100,37,49,48,49,53,112,112,48,113,96,112,
+ 48,52,52,52,100,100,100,52,32,33,100,100,52,52,100,52,52,48,52,36,
+ 37,37,37,49,49,49,37,53,33,49,49,37,37,37,53,97,113,97,36,101,96,97,
+ 100,100,100,113,29,102,37,42,57,49,100,96,100,100,97,97,97,97,33,53,
+ 53,112,48,113,48,49,49,97,37,49,48,49,113,112,49,97,112,96,37,37,100,
+ 52,112,49,49,49,33,116,36,100,100,52,52,52,52,112,117,97,33,37,37,
+ 37,49,49,97,116,48,33,49,49,37,37,101,53,37,36,37,97,97,97,97,100,
+ 100,100,97,101,96,100,36,101,100,96,97,33,53,101,112,112,112,48,49,
+ 49,100,36,97,100,100,48,112,112,112,112,96,48,49,52,52,52,100,100,
+ 100,52,116,36,100,100,52,52,52,52,52,48,52,36,37,37,37,49,49,49,101,
+ 100,48,49,49,37,37,37,53,97,113,97,36,37,97,97,100,100,100,101,29,
+ 102,36,46,57,49,100,96,100,100,97,97,97,97,33,53,53,112,48,113,48,
+ 49,49,97,37,49,48,49,113,112,49,97,112,96,37,37,100,52,112,49,49,49,
+ 33,116,36,100,100,52,52,52,52,112,117,97,33,37,37,37,49,49,97,52,33,
+ 116,100,100,32,37,101,33,37,36,37,97,97,97,97,100,100,100,113,112,
+ 96,100,36,101,100,96,97,33,53,101,112,112,112,48,49,49,112,37,49,48,
+ 49,53,112,112,112,112,96,112,48,52,52,52,100,100,100,52,116,36,100,
+ 100,52,52,52,52,52,48,52,36,37,37,37,49,49,49,37,53,33,49,49,37,37,
+ 37,53,97,113,97,100,117,101,97,100,100,100,97,25,102,33,46,57,49,100,
+ 96,100,100,97,97,97,97,33,53,53,112,48,113,48,49,49,97,37,49,48,49,
+ 113,112,49,97,112,96,37,37,100,52,112,49,49,49,33,116,36,100,100,52,
+ 52,52,52,112,117,97,33,37,37,37,49,49,97,52,37,32,49,49,37,37,101,
+ 33,37,36,37,97,97,97,97,100,100,100,33,33,96,100,36,101,100,101,97,
+ 33,53,101,112,112,112,48,49,49,100,32,49,48,49,53,112,112,112,112,
+ 96,48,49,52,52,52,100,100,100,52,116,36,100,100,52,52,52,52,52,48,
+ 52,36,37,37,37,49,49,49,37,116,100,100,100,32,37,37,53,97,113,97,100,
+ 100,101,97,100,100,100,117,25,102,96,46,57,49,100,96,100,100,97,97,
+ 97,97,33,53,53,112,48,113,48,49,49,97,37,49,48,49,113,112,49,97,112,
+ 96,37,37,100,52,112,49,49,49,33,116,36,100,100,52,52,52,52,112,117,
+ 97,33,37,37,37,49,49,97,116,48,33,49,49,37,37,101,33,49,36,37,97,97,
+ 100,97,100,100,100,97,101,96,100,36,101,100,96,97,33,48,101,112,112,
+ 112,48,49,49,100,113,36,100,100,48,112,112,112,112,96,112,48,52,52,
+ 52,100,100,100,52,116,36,100,100,52,52,52,52,52,48,52,36,37,37,37,
+ 49,49,49,37,53,33,49,49,37,37,37,53,97,113,97,100,36,97,97,100,100,
+ 100,49,25,102,53,46,57,49,100,96,100,100,97,97,97,97,33,53,53,112,
+ 48,113,48,49,49,97,37,49,48,49,113,112,49,97,112,96,37,37,100,52,112,
+ 49,49,49,33,116,36,100,100,52,52,52,52,112,117,97,33,37,37,37,49,49,
+ 97,116,49,100,100,100,32,37,101,33,37,36,37,97,97,97,97,100,100,100,
+ 53,53,96,100,36,101,100,96,97,33,53,101,112,112,112,48,49,49,100,32,
+ 49,48,49,53,112,112,112,112,96,112,48,52,52,52,100,100,100,52,116,
+ 36,100,100,52,52,52,52,52,48,52,36,37,37,37,49,49,49,37,53,33,49,49,
+ 37,37,37,53,97,113,97,100,100,96,97,100,100,100,112,24,102,116,43,
+ 57,49,100,96,100,100,97,97,97,97,33,53,53,112,48,113,48,49,49,97,37,
+ 49,48,49,113,112,49,97,112,96,37,37,100,52,112,49,49,49,33,116,36,
+ 100,100,52,52,52,52,112,117,97,33,37,37,37,49,49,97,116,48,33,49,49,
+ 37,37,101,33,37,36,37,100,97,97,97,100,100,100,97,101,96,100,36,101,
+ 32,53,96,33,53,101,112,112,112,48,49,49,100,33,97,101,100,48,112,112,
+ 112,48,97,112,48,52,52,52,100,100,100,52,116,36,100,100,52,52,52,52,
+ 52,48,52,36,37,37,37,49,49,49,101,100,36,49,49,37,37,37,53,97,113,
+ 97,100,100,96,97,100,100,100,33,13,102,113,43,57,49,100,96,100,100,
+ 97,97,97,97,33,53,53,112,48,113,48,49,49,97,37,49,48,49,113,112,49,
+ 97,112,96,37,37,100,52,112,49,49,49,33,116,36,100,100,52,52,52,52,
+ 112,117,97,33,37,37,37,49,49,97,52,32,32,49,49,37,37,101,33,37,36,
+ 37,97,97,97,97,100,100,100,53,101,101,100,36,101,100,96,97,33,53,101,
+ 112,112,112,48,49,49,100,32,49,48,49,53,112,112,112,112,96,112,48,
+ 52,52,52,100,100,100,52,116,36,100,100,52,52,52,52,52,48,52,36,37,
+ 37,37,49,49,49,101,53,49,49,49,37,37,37,53,97,33,97,100,100,96,97,
+ 100,100,100,53,13,102,48,46,57,49,100,96,100,100,97,97,97,97,33,53,
+ 53,112,48,113,48,49,49,97,37,49,48,49,113,112,49,97,112,96,37,37,100,
+ 52,112,49,49,49,33,116,36,100,100,52,52,52,52,112,117,97,33,37,37,
+ 37,49,49,97,116,48,33,49,49,37,37,101,33,37,36,37,97,100,97,97,100,
+ 100,100,97,101,96,100,36,101,100,101,97,33,53,101,112,112,112,48,49,
+ 49,100,33,53,48,49,53,112,112,112,48,97,112,48,52,52,52,100,100,100,
+ 52,116,36,100,100,52,52,52,52,52,48,52,36,37,37,37,49,49,49,37,53,
+ 33,49,49,37,37,37,53,97,113,97,100,100,96,97,100,100,100,113,24,102,
+ 101,43,57,49,100,96,100,100,97,97,97,97,33,53,53,112,48,113,48,49,
+ 49,97,37,49,48,49,113,112,49,97,112,96,37,37,100,52,112,49,49,49,33,
+ 116,36,100,100,52,52,52,52,112,117,97,33,37,37,37,49,49,97,52,97,36,
+ 49,49,37,37,101,33,37,36,49,97,97,97,97,100,100,100,97,101,96,100,
+ 36,101,100,96,97,33,53,101,112,112,112,48,49,49,100,32,49,48,49,53,
+ 112,112,112,112,96,112,48,52,52,52,100,100,100,52,116,36,100,100,52,
+ 52,52,52,52,48,52,36,37,37,37,49,49,49,101,32,32,49,49,37,37,37,53,
+ 97,113,97,100,100,96,97,100,100,100,101,24,102,100,127,108,100,101,
+ 96,100,100,97,97,97,97,33,53,53,112,48,113,48,49,49,97,37,49,48,49,
+ 113,112,49,97,112,96,37,37,100,52,112,49,49,49,33,116,36,100,100,52,
+ 52,52,52,112,117,97,33,37,37,37,49,49,97,116,48,33,49,49,37,37,101,
+ 33,37,36,37,97,97,97,97,100,100,100,97,101,96,100,36,101,100,96,97,
+ 33,53,101,112,112,112,48,49,49,100,113,53,48,49,53,112,112,112,48,
+ 97,112,48,52,52,52,100,100,100,52,116,36,100,100,52,52,52,52,52,48,
+ 52,36,37,37,37,49,49,49,37,53,33,49,49,37,37,37,53,97,113,97,100,100,
+ 96,100,100,100,100,97,88,51,96,127,108,100,100,100,100,100,97,97,97,
+ 97,97,100,36,112,48,113,48,96,100,100,100,100,100,100,36,112,100,117,
+ 112,48,49,33,100,52,52,36,48,49,49,49,49,49,49,33,52,52,52,52,100,
+ 100,32,37,37,37,33,100,100,100,100,100,100,100,32,37,101,36,37,49,
+ 49,96,97,97,97,32,49,49,49,49,49,49,49,48,49,97,97,97,100,36,112,112,
+ 112,48,96,100,100,100,100,100,100,36,112,112,112,112,48,49,33,52,52,
+ 52,36,48,49,49,49,49,49,49,33,52,52,52,52,52,100,32,37,37,37,33,100,
+ 100,100,100,100,100,100,32,37,37,101,100,48,49,48,49,97,97,32,49,49,
+ 37,93,51,37,126,108,100,100,100,100,100,97,100,100,100,100,97,100,
+ 100,100,36,53,96,100,100,100,100,100,100,36,112,53,49,49,113,32,100,
+ 52,36,32,36,48,49,49,49,49,49,49,97,117,117,117,101,52,100,100,112,
+ 117,33,112,49,49,49,49,49,49,49,117,37,37,49,49,49,49,49,49,49,96,
+ 32,49,49,49,49,49,49,49,96,100,100,97,100,97,36,112,112,53,32,48,49,
+ 49,49,49,49,49,113,48,49,49,49,113,48,97,37,32,52,52,100,100,100,100,
+ 100,100,100,52,100,100,36,112,32,100,52,52,52,32,117,49,49,49,49,49,
+ 49,49,33,52,52,32,117,49,49,116,117,117,100,32,49,49,33,88,51,116,
+ 127,108,100,100,100,100,100,100,117,117,117,117,100,36,117,117,53,
+ 113,48,49,49,49,49,49,49,33,100,100,96,117,53,49,97,117,101,116,101,
+ 100,100,100,100,100,100,100,100,100,100,100,116,101,100,112,49,49,
+ 49,49,49,49,49,49,49,49,49,49,37,37,113,116,49,49,116,117,117,100,
+ 100,100,100,100,100,100,100,100,100,52,117,100,52,100,100,100,100,
+ 32,49,49,49,49,49,49,49,49,49,113,117,117,117,53,49,49,49,33,52,52,
+ 100,100,100,100,100,100,100,52,116,117,101,100,100,100,100,100,100,
+ 112,49,49,49,49,49,49,49,49,49,49,49,96,100,100,100,100,100,100,117,
+ 100,100,100,112,93,51,33,127,108,100,100,100,100,100,100,32,37,37,
+ 37,49,49,49,96,117,100,32,49,49,49,49,49,49,49,37,49,49,37,49,49,113,
+ 36,96,97,100,97,100,100,100,100,100,100,100,100,100,100,100,100,100,
+ 52,36,112,48,113,48,49,49,49,49,49,49,49,117,117,113,116,49,49,116,
+ 53,33,33,100,100,100,100,100,100,100,100,52,100,100,52,100,100,100,
+ 32,37,37,49,49,49,49,49,49,49,49,49,53,101,112,96,97,100,100,100,52,
+ 52,52,97,100,100,100,100,100,100,52,33,116,49,49,49,49,49,49,49,49,
+ 49,49,49,49,49,49,49,49,49,49,49,113,48,49,49,49,49,49,116,52,100,
+ 100,36,92,51,48,127,108,100,100,100,100,36,53,48,49,49,49,100,116,
+ 37,100,52,96,101,100,100,100,100,100,100,116,117,117,37,117,48,49,
+ 33,112,36,112,117,49,49,49,49,49,49,49,117,117,117,117,97,101,100,
+ 32,116,117,117,117,100,100,100,100,100,100,100,117,32,37,116,32,49,
+ 49,96,97,53,117,53,49,49,49,49,49,49,113,117,53,32,117,53,49,97,117,
+ 117,117,117,101,100,100,100,100,100,100,116,37,112,112,112,33,49,117,
+ 117,33,52,96,48,49,49,49,49,49,49,37,117,117,117,117,49,49,116,117,
+ 117,49,117,100,100,100,100,100,100,100,117,117,117,117,117,100,36,
+ 117,117,53,32,53,49,49,101,92,59,101,43,179,100,194,206,100,};
diff --git a/sys/dev/ctau/ctaug7fw.h b/sys/dev/ctau/ctaug7fw.h
new file mode 100644
index 000000000000..523008932a0f
--- /dev/null
+++ b/sys/dev/ctau/ctaug7fw.h
@@ -0,0 +1,2062 @@
+/*
+ * DO NOT EDIT MANUALLY!
+ * This code was generated by mkfw utility
+ * from the file `ctaug703.dat'
+ *
+ * Cronyx Id: ctaug7fw.h,v 1.1 2002/06/03 10:19:40 rik Exp $
+ * $FreeBSD$
+ */
+long ctaug703_fw_len = 323982;
+
+const char *ctaug703_fw_version = "1.1";
+const char *ctaug703_fw_date = "18.02.97";
+const char *ctaug703_fw_copyright = "Copyright (C) 1997 Cronyx Engineering.";
+
+const cr_dat_tst_t ctaug703_fw_tvec[] = {
+ {130534,132958}, {134206,136630}, {137878,140302}, {141550,143974},
+ {145222,147646}, {148894,151318}, {152566,154990}, {156238,158662},
+ {159910,162334}, {163582,166006}, {167254,169678}, {170926,173350},
+ {174598,177022}, {178270,180694}, {181942,184366}, {185614,188038},
+ {189286,191710}, {192958,195382}, {196630,199054}, {200302,202726},
+ {203974,206398}, {207646,210070}, {211318,213742}, {214990,217414},
+ {218662,221086}, {222334,224758}, {226006,228430}, {229678,232102},
+ {233350,235774}, {237022,239446}, {240694,243118}, {244366,246790},
+ {248038,250462}, {251710,254134}, {255382,257806}, {259054,261478},
+ {262726,265150}, {266398,268822}, {270070,272494}, {273742,276166},
+ {277414,279838}, {281086,283510}, {284758,287182}, {288430,290854},
+ {292102,294526}, {295774,298198}, {299446,301870}, {303118,305542},
+ {306790,309214}, {310462,312886}, {314134,316558}, {317806,320230},
+ {321478,323902}, {323982,323982},
+};
+
+const unsigned char ctaug703_fw_data[] = {
+ 155,153,97,52,81,185,113,32,100,100,101,112,96,101,100,36,96,112,49,
+ 112,96,101,100,116,100,53,32,49,97,100,37,96,100,100,36,97,48,37,116,
+ 100,96,100,101,100,117,36,100,100,52,37,52,52,116,52,112,33,101,33,
+ 37,49,49,113,113,48,97,100,100,48,52,112,97,101,48,100,33,117,53,96,
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+ 112,48,49,49,100,32,49,48,49,53,112,112,112,112,96,112,48,52,52,52,
+ 100,100,100,52,116,36,100,100,52,52,52,52,52,48,52,36,37,37,37,49,
+ 49,49,101,32,32,49,49,37,37,37,53,97,113,97,100,100,96,97,100,100,
+ 100,101,24,102,100,117,48,33,49,49,37,37,37,37,37,116,116,96,97,100,
+ 97,100,100,36,53,100,96,100,100,97,101,36,97,33,53,52,48,113,96,101,
+ 100,100,36,112,49,48,49,113,112,112,112,96,117,37,37,52,52,52,100,
+ 100,36,113,97,36,100,100,52,52,52,37,52,48,52,36,37,37,37,49,49,49,
+ 37,53,33,49,49,52,49,33,37,37,116,52,97,97,97,97,100,100,48,101,117,
+ 96,100,116,96,97,97,97,36,97,97,112,112,112,48,49,49,113,112,49,48,
+ 49,113,112,112,112,112,96,112,48,52,52,52,100,100,100,52,116,36,100,
+ 100,52,52,52,116,36,101,37,49,49,33,49,49,49,49,37,65,229,228,116,
+ 36,100,48,113,36,116,100,100,32,36,53,33,37,116,100,100,101,52,112,
+ 48,49,100,116,32,100,100,100,48,36,113,96,101,36,100,116,100,96,101,
+ 96,100,100,113,96,33,53,100,33,53,112,52,112,48,49,49,53,112,49,48,
+ 49,113,49,97,52,49,113,96,52,37,112,33,100,100,48,113,112,33,49,53,
+ 113,36,112,36,48,117,36,52,33,37,37,49,49,49,101,112,53,49,49,101,
+ 33,37,101,33,36,113,112,96,113,101,100,100,100,100,101,96,48,49,53,
+ 100,36,48,117,100,112,112,96,37,48,49,49,113,112,49,48,49,97,37,96,
+ 37,112,52,37,112,117,36,52,100,100,100,112,113,53,100,96,100,100,97,
+ 97,97,97,33,53,53,112,48,113,48,49,49,97,37,49,48,49,113,112,49,97,
+ 112,96,37,37,100,52,112,49,49,49,33,116,36,100,100,52,52,52,52,112,
+ 117,97,33,37,37,37,49,49,97,116,48,33,49,49,37,37,101,33,37,36,37,
+ 97,97,97,97,100,100,100,97,101,96,100,36,101,100,96,97,33,53,101,112,
+ 112,112,48,49,49,100,113,53,48,49,53,112,112,112,48,97,112,48,52,52,
+ 52,100,100,100,52,116,36,100,100,52,52,52,52,52,48,52,36,37,37,37,
+ 49,49,49,37,53,33,49,49,37,37,37,53,97,113,97,100,100,96,100,100,100,
+ 100,97,88,51,96,117,100,100,100,100,32,37,37,37,37,49,49,96,97,100,
+ 97,32,49,49,49,49,49,49,49,96,49,117,97,97,100,36,48,113,112,48,96,
+ 100,100,100,100,100,100,36,112,112,112,112,48,49,33,52,52,52,36,48,
+ 49,49,49,49,49,49,33,52,52,49,52,100,100,32,37,37,37,33,100,100,100,
+ 100,100,100,100,96,100,36,37,37,49,49,96,97,97,97,32,49,49,49,49,49,
+ 49,49,96,97,97,97,97,100,36,112,112,112,48,96,100,100,100,100,100,
+ 100,36,112,112,112,112,112,48,33,52,52,52,36,48,49,49,49,49,49,49,
+ 33,52,52,52,49,97,100,96,100,36,37,33,100,100,52,84,229,228,100,100,
+ 100,100,52,49,52,113,97,48,49,101,36,37,37,33,100,100,100,100,100,
+ 100,100,32,37,101,116,117,49,113,100,48,48,117,32,49,49,49,49,49,49,
+ 49,48,97,97,97,49,100,36,112,100,112,48,96,100,100,100,100,100,100,
+ 36,100,37,33,37,97,100,52,49,52,52,36,48,49,49,49,49,49,49,33,49,52,
+ 49,52,97,100,96,36,37,37,33,100,100,100,100,100,100,100,96,36,37,101,
+ 36,49,49,48,97,49,97,100,100,100,100,100,100,100,100,97,49,117,52,
+ 97,100,36,112,112,112,48,96,100,100,100,100,100,100,36,112,112,112,
+ 112,36,49,33,52,49,52,36,48,49,113,112,53,49,49,49,49,96,97,97,97,
+ 97,100,36,112,48,113,48,96,100,100,100,100,100,100,36,112,100,117,
+ 112,48,49,33,100,52,52,36,48,49,49,49,49,49,49,33,52,52,52,52,100,
+ 100,32,37,37,37,33,100,100,100,100,100,100,100,32,37,101,36,37,49,
+ 49,96,97,97,97,32,49,49,49,49,49,49,49,48,49,97,97,97,100,36,112,112,
+ 112,48,96,100,100,100,100,100,100,36,112,112,112,112,48,49,33,52,52,
+ 52,36,48,49,49,49,49,49,49,33,52,52,52,52,52,100,32,37,37,37,33,100,
+ 100,100,100,100,100,100,32,37,37,101,100,48,49,48,49,97,97,32,49,49,
+ 37,93,51,37,116,100,100,100,100,32,49,49,49,49,37,49,49,49,49,116,
+ 32,49,49,49,49,49,49,49,96,117,100,100,100,33,48,113,48,32,48,96,100,
+ 100,100,100,100,100,36,117,117,117,53,113,48,49,97,117,37,96,101,100,
+ 100,100,100,100,100,116,53,52,100,100,100,100,100,100,100,32,33,100,
+ 100,100,100,100,100,100,32,49,49,37,49,37,49,96,97,117,32,96,100,100,
+ 100,100,100,100,100,97,100,100,100,100,97,36,53,32,112,112,48,49,49,
+ 49,49,49,49,113,48,49,49,96,33,48,113,112,112,32,116,101,100,100,100,
+ 100,100,100,36,112,112,32,116,101,100,112,117,117,49,33,100,100,36,
+ 64,229,228,100,100,100,100,52,100,100,52,100,52,32,49,49,49,49,49,
+ 49,49,49,49,49,49,49,117,49,49,49,49,37,96,100,100,100,117,100,100,
+ 100,100,100,100,100,100,100,117,97,100,32,113,48,49,113,53,49,49,49,
+ 49,49,49,49,49,49,49,49,113,48,113,48,97,101,100,100,100,100,100,100,
+ 100,100,100,100,52,100,100,100,100,52,32,49,49,37,49,37,49,49,49,49,
+ 49,49,49,49,117,33,32,37,49,49,96,100,100,97,100,100,100,100,100,100,
+ 100,100,97,100,117,100,100,36,48,49,49,49,49,49,49,49,49,49,49,49,
+ 49,49,49,113,48,113,48,97,101,100,100,100,100,100,100,33,53,49,49,
+ 49,49,96,100,100,100,100,97,100,100,100,36,53,96,100,100,100,100,100,
+ 100,36,112,53,49,49,113,32,100,52,36,32,36,48,49,49,49,49,49,49,97,
+ 117,117,117,101,52,100,100,112,117,33,112,49,49,49,49,49,49,49,117,
+ 37,37,49,49,49,49,49,49,49,96,32,49,49,49,49,49,49,49,96,100,100,97,
+ 100,97,36,112,112,53,32,48,49,49,49,49,49,49,113,48,49,49,49,113,48,
+ 97,37,32,52,52,100,100,100,100,100,100,100,52,100,100,36,112,32,100,
+ 52,52,52,32,117,49,49,49,49,49,49,49,33,52,52,32,117,49,49,116,117,
+ 117,100,32,49,49,33,88,51,116,117,100,100,100,100,100,112,117,117,
+ 117,49,49,116,117,117,100,97,100,100,100,100,100,100,36,48,49,33,117,
+ 117,100,36,117,53,113,53,49,49,49,49,49,49,49,49,49,49,49,113,53,49,
+ 97,101,100,100,100,100,100,100,100,100,100,100,100,52,52,100,113,101,
+ 100,112,117,117,49,49,49,49,49,49,49,49,49,49,113,116,49,113,48,49,
+ 49,49,33,100,100,100,100,100,100,100,100,100,100,117,117,117,117,100,
+ 100,100,36,112,112,48,49,49,49,49,49,49,113,112,117,53,49,49,49,49,
+ 49,49,97,101,100,100,100,100,100,100,100,100,100,100,32,49,49,49,49,
+ 49,49,117,49,49,49,97,85,229,228,100,100,100,100,100,116,117,117,117,
+ 101,100,112,117,117,117,117,49,49,49,49,49,49,49,117,117,117,117,117,
+ 49,49,33,117,117,100,117,100,100,100,100,100,100,100,117,100,100,117,
+ 97,100,36,117,53,113,117,53,49,49,49,49,49,49,113,117,117,117,53,37,
+ 49,33,100,113,117,117,101,100,100,100,100,100,100,100,116,117,117,
+ 117,101,100,112,117,49,117,49,49,49,49,49,49,49,49,117,49,49,117,49,
+ 49,49,49,33,117,100,117,100,100,100,100,100,100,100,117,117,100,117,
+ 117,100,36,117,117,117,117,53,49,49,49,49,49,49,49,101,53,101,112,
+ 53,49,49,49,112,117,101,97,100,36,117,53,49,49,49,49,49,116,117,117,
+ 117,100,36,117,117,53,113,48,49,49,49,49,49,49,33,100,100,96,117,53,
+ 49,97,117,101,116,101,100,100,100,100,100,100,100,100,100,100,100,
+ 116,101,100,112,49,49,49,49,49,49,49,49,49,49,49,49,37,37,113,116,
+ 49,49,116,117,117,100,100,100,100,100,100,100,100,100,100,52,117,100,
+ 52,100,100,100,100,32,49,49,49,49,49,49,49,49,49,113,117,117,117,53,
+ 49,49,49,33,52,52,100,100,100,100,100,100,100,52,116,117,101,100,100,
+ 100,100,100,100,112,49,49,49,49,49,49,49,49,49,49,49,96,100,100,100,
+ 100,100,100,117,100,100,100,112,93,51,33,117,100,100,100,100,100,52,
+ 52,52,52,100,100,100,32,117,49,33,100,100,100,100,100,100,100,52,100,
+ 100,52,100,100,100,49,32,37,49,37,49,49,49,49,49,49,49,49,49,49,49,
+ 49,49,113,48,96,97,100,97,100,100,100,100,100,100,100,116,117,101,
+ 113,101,100,112,117,36,36,48,49,49,49,49,49,49,49,113,48,49,113,48,
+ 49,49,33,52,52,100,100,100,100,100,100,100,100,100,116,52,97,33,37,
+ 49,49,49,113,112,112,36,49,49,49,49,49,49,113,36,112,101,100,100,100,
+ 100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,97,
+ 100,100,100,100,100,112,113,48,49,49,80,229,228,100,100,100,100,100,
+ 100,52,52,112,49,49,37,49,37,96,100,100,100,100,100,100,100,100,97,
+ 32,49,96,97,100,100,52,49,97,36,48,49,49,49,49,49,49,113,48,49,97,
+ 37,48,49,33,36,48,33,52,100,100,100,100,100,100,100,100,100,36,48,
+ 49,37,49,49,49,96,100,100,100,100,100,100,100,100,100,100,52,117,112,
+ 96,100,100,100,53,112,117,112,48,49,49,49,49,49,49,116,100,36,116,
+ 49,49,49,49,97,96,36,37,100,100,100,100,100,100,100,97,97,100,113,
+ 101,100,36,112,96,37,112,48,49,49,49,49,49,49,49,101,53,101,33,37,
+ 49,49,49,36,113,101,97,100,100,96,53,49,49,49,49,49,37,37,37,37,49,
+ 49,49,96,117,100,32,49,49,49,49,49,49,49,37,49,49,37,49,49,113,36,
+ 96,97,100,97,100,100,100,100,100,100,100,100,100,100,100,100,100,52,
+ 36,112,48,113,48,49,49,49,49,49,49,49,117,117,113,116,49,49,116,53,
+ 33,33,100,100,100,100,100,100,100,100,52,100,100,52,100,100,100,32,
+ 37,37,49,49,49,49,49,49,49,49,49,53,101,112,96,97,100,100,100,52,52,
+ 52,97,100,100,100,100,100,100,52,33,116,49,49,49,49,49,49,49,49,49,
+ 49,49,49,49,49,49,49,49,49,49,113,48,49,49,49,49,49,116,52,100,100,
+ 36,92,51,48,117,100,100,100,100,117,96,100,100,100,48,113,53,48,113,
+ 32,53,49,49,49,49,49,49,113,117,117,53,116,97,100,36,96,49,96,117,
+ 101,100,100,100,100,100,100,116,117,117,117,37,53,49,33,112,117,117,
+ 117,49,49,49,49,49,49,49,117,33,52,112,33,100,100,32,37,117,116,117,
+ 100,100,100,100,100,100,100,117,117,32,116,117,100,36,117,117,117,
+ 117,53,49,49,49,49,49,49,113,53,96,97,97,37,100,116,117,37,112,32,
+ 97,100,100,100,100,100,100,52,116,117,117,117,101,100,112,117,117,
+ 101,116,49,49,49,49,49,49,49,117,117,117,117,117,49,49,116,117,117,
+ 32,116,100,100,52,81,229,228,100,100,100,100,112,117,36,112,117,49,
+ 49,52,33,52,33,116,100,100,100,100,100,100,100,53,97,97,33,116,100,
+ 36,117,101,112,32,53,49,49,49,49,49,49,113,101,32,117,117,37,100,116,
+ 49,96,117,49,36,49,49,49,49,49,49,97,49,96,117,49,48,49,117,36,112,
+ 117,36,100,100,100,100,100,100,100,112,117,36,37,37,100,100,53,97,
+ 33,52,33,49,49,49,49,49,49,49,52,33,116,49,117,100,36,117,117,101,
+ 32,37,100,100,100,100,100,100,36,117,101,32,101,96,100,116,49,96,117,
+ 49,36,49,49,49,49,49,49,97,37,96,53,113,33,49,117,117,117,48,112,49,
+ 49,113,100,53,49,49,49,113,53,48,49,49,49,100,116,37,100,52,96,101,
+ 100,100,100,100,100,100,116,117,117,37,117,48,49,33,112,36,112,117,
+ 49,49,49,49,49,49,49,117,117,117,117,97,101,100,32,116,117,117,117,
+ 100,100,100,100,100,100,100,117,32,37,116,32,49,49,96,97,53,117,53,
+ 49,49,49,49,49,49,113,117,53,32,117,53,49,97,117,117,117,117,101,100,
+ 100,100,100,100,100,116,37,112,112,112,33,49,117,117,33,52,96,48,49,
+ 49,49,49,49,49,37,117,117,117,117,49,49,116,117,117,49,117,100,100,
+ 100,100,100,100,100,117,117,117,117,117,100,36,117,117,53,32,53,49,
+ 49,101,92,59,101,113,12,110,48,49,89,27,179,};
diff --git a/sys/dev/ctau/ctaureg.h b/sys/dev/ctau/ctaureg.h
new file mode 100644
index 000000000000..9097a5522a1e
--- /dev/null
+++ b/sys/dev/ctau/ctaureg.h
@@ -0,0 +1,276 @@
+/*
+ * Defines for Cronyx-Tau adapter, based on Hitachi HD64570 controller.
+ *
+ * Copyright (C) 1996 Cronyx Engineering.
+ * Author: Serge Vakulenko, <vak@cronyx.ru>
+ *
+ * This software is distributed with NO WARRANTIES, not even the implied
+ * warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Authors grant any other persons or organisations permission to use
+ * or modify this software as long as this message is kept with the software,
+ * all derivative works or modified versions.
+ *
+ * Cronyx Id: ctaureg.h,v 1.1.2.1 2003/11/12 17:16:10 rik Exp $
+ * $FreeBSD$
+ */
+
+/*
+ * Chip register address, B is chip base port, R is chip register number.
+ */
+#define R(b,r) ((b) | 0x8000 | (((r)<<6 & 0x3c00) | ((r) & 0xf)))
+
+/*
+ * Interface board registers, R is register number 0..7.
+ */
+#define GR(p,r) ((p) | 0x0010 | (r)<<1)
+
+/*------------------------------------------------------------
+ * Basic Tau model.
+ */
+#define BSR0(p) (p) /* board status register 0, read only */
+#define BSR1(p) ((p) | 0x2000) /* board status register 1, read only */
+#define BSR2(p) ((p) | 0x4010) /* board status register 2, read only */
+#define BSR3(p) ((p) | 0x4000) /* board status register 3, read only */
+#define BCR0(p) (p) /* board command register 0, write only */
+#define BCR1(p) ((p) | 0x2000) /* board command register 1, write only */
+#define BCR2(p) ((p) | 0x4010) /* board command register 2, write only */
+#define BCR3(p) ((p) | 0x4000) /* board command register 3, write only */
+#define IACK(p) ((p) | 0x6000) /* interrupt acknowledge register, ro */
+
+/*
+ * Board status register 0 bits.
+ */
+#define BSR0_INTR 0x01 /* interrupt pending flag */
+#define BSR0_HDINT 0x02 /* HD64570 interrupt pending */
+#define BSR0_GINT 0x04 /* interface board interrupt pending */
+#define BSR0_RDYERR 0x10 /* HD64570 reg.i/o error - not ready */
+
+#define BSR0_TE1 0x02 /* 0 - E1 daughter board installed */
+#define BSR0_T703 0x04 /* 0 - G.703 daughter board installed */
+
+/*
+ * Board status register 1 bits.
+ */
+#define BSR1_DSR0 0x01 /* DSR from channel 0 */
+#define BSR1_DSR1 0x02 /* DSR from channel 1 */
+
+#define BSR1_CH0_CABLE 0x0c /* channel 0 cable type mask */
+#define BSR1_CH0_V35 0x0c /* channel 0 is V.35 */
+#define BSR1_CH0_RS232 0x08 /* channel 0 is RS-232 or not connected */
+#define BSR1_CH0_X21 0x04 /* channel 0 is X.21 */
+#define BSR1_CH0_RS530 0x00 /* channel 0 is RS-530 */
+
+#define BSR1_CH1_CABLE 0x30 /* channel 1 cable type mask */
+#define BSR1_CH1_SHIFT 2
+#define BSR1_CH1_V35 0x0c /* channel 1 is V.35 */
+#define BSR1_CH1_RS232 0x08 /* channel 1 is RS-232 or not connected */
+#define BSR1_CH1_X21 0x04 /* channel 1 is X.21 */
+#define BSR1_CH1_RS530 0x00 /* channel 1 is RS-530 */
+
+/*
+ * Board status register 2 bits.
+ */
+#define BSR2_GINT0 0x08 /* interface board chan0 interrupt pending */
+#define BSR2_GINT1 0x40 /* interface board chan1 interrupt pending */
+#define BSR2_LERR 0x80 /* firmware download error signal */
+
+/*
+ * Board status register 3 bits.
+ */
+#define BSR3_IB 0x08 /* identification bit */
+#define BSR3_NSTATUS 0x10 /* firmware download status */
+#define BSR3_CONF_DN 0x20 /* firmware download done */
+#define BSR3_IB_NEG 0x40 /* negated identification bit */
+#define BSR3_ZERO 0x80 /* always zero */
+
+/*
+ * Board control register 0 bits.
+ */
+#define BCR0_IRQ_DIS 0x00 /* no interrupt generated */
+#define BCR0_IRQ_3 0x01 /* select IRQ number 3 */
+#define BCR0_IRQ_5 0x02 /* select IRQ number 5 */
+#define BCR0_IRQ_7 0x03 /* select IRQ number 7 */
+#define BCR0_IRQ_10 0x04 /* select IRQ number 10 */
+#define BCR0_IRQ_11 0x05 /* select IRQ number 11 */
+#define BCR0_IRQ_12 0x06 /* select IRQ number 12 */
+#define BCR0_IRQ_15 0x07 /* select IRQ number 15 */
+#define BCR0_IRQ_MASK 0x07 /* IRQ mask */
+
+#define BCR0_HDRUN 0x08 /* inverted board reset flag */
+
+#define BCR0_DMA_DIS 0x00 /* no interrupt generated */
+#define BCR0_DMA_5 0x10 /* select DMA channel 5 */
+#define BCR0_DMA_6 0x20 /* select DMA channel 6 */
+#define BCR0_DMA_7 0x30 /* select DMA channel 7 */
+
+#define BCR0_TCK 0x80 /* firmware download TCK signal */
+
+/*
+ * Board control register 1 bits.
+ */
+#define BCR1_DTR0 0x01 /* channel 0 DTR enable */
+#define BCR1_DTR1 0x02 /* channel 1 DTR enable */
+
+#define BCR1_TXCOUT0 0x10 /* channel 0 TXCOUT enable */
+#define BCR1_TXCOUT1 0x20 /* channel 1 TXCOUT enable */
+
+#define BCR1_TMS 0x08 /* firmware download TMS signal */
+#define BCR1_TDI 0x80 /* firmware download TDI signal */
+
+#define BCR1_NCONFIGI 0x08 /* firmware download start */
+#define BCR1_DCLK 0x40 /* firmware download clock */
+#define BCR1_1KDAT 0x80 /* firmware download data */
+
+/*
+ * Board control register 2 bits -- see ctau.h.
+ */
+
+#define IMVR(b) R(b,HD_IMVR) /* interrupt modified vector reg. */
+#define ITCR(b) R(b,HD_ITCR) /* interrupt control register */
+#define ISR0(b) R(b,HD_ISR0) /* interrupt status register 0, ro */
+#define ISR1(b) R(b,HD_ISR1) /* interrupt status register 1, ro */
+#define ISR2(b) R(b,HD_ISR2) /* interrupt status register 2, ro */
+#define IER0(b) R(b,HD_IER0) /* interrupt enable register 0 */
+#define IER1(b) R(b,HD_IER1) /* interrupt enable register 1 */
+#define IER2(b) R(b,HD_IER2) /* interrupt enable register 2 */
+#define PCR(b) R(b,HD_PCR) /* DMA priority control register */
+#define DMER(b) R(b,HD_DMER) /* DMA master enable register */
+#define WCRL(b) R(b,HD_WCRL) /* wait control register L */
+#define WCRM(b) R(b,HD_WCRM) /* wait control register M */
+#define WCRH(b) R(b,HD_WCRH) /* wait control register H */
+
+/*------------------------------------------------------------
+ * Tau/E1 model.
+ */
+#define E1CFG(p) GR(p,0) /* control register 0, write only */
+#define E1SR(p) GR(p,0) /* status register, read only */
+#define E1CS2(p) GR(p,1) /* chip select 2/IACK, read/write */
+#define E1SYN(p) GR(p,3) /* sync mode enable, write only */
+#define E1CS0(p) GR(p,4) /* chip select 0, write only */
+#define E1CS1(p) GR(p,5) /* chip select 1, write only */
+#define E1DAT(p) GR(p,7) /* selected chip read/write */
+
+/*
+ * Tau/E1 CS2/IACK register bits.
+ */
+#define E1CS2_IACK 0x08 /* serial controller interrupt acknowledge */
+#define E1CS2_SCC 0x04 /* serial controller select */
+#define E1CS2_AB 0x02 /* serial controller A/B signal */
+#define E1CS2_DC 0x01 /* serial controller D/C signal */
+
+/*
+ * Tau/E1 control register bits.
+ */
+#define E1CFG_II 0x00 /* configuration II */
+#define E1CFG_K 0x01 /* configuration K */
+#define E1CFG_HI 0x02 /* configuration HI */
+#define E1CFG_D 0x03 /* configuration D */
+
+#define E1CFG_CLK0_INT 0x00 /* channel E0 transmit clock - internal */
+#define E1CFG_CLK0_RCV 0x04 /* channel E0 transmit clock - RCLK0 */
+#define E1CFG_CLK0_RCLK1 0x08 /* channel E0 transmit clock - RCLK1 */
+
+#define E1CFG_CLK1_INT 0x00 /* channel E1 transmit clock - internal */
+#define E1CFG_CLK1_RCLK0 0x10 /* channel E1 transmit clock - RCLK0 */
+#define E1CFG_CLK1_RCV 0x20 /* channel E1 transmit clock - RCLK1 */
+
+#define E1CFG_LED 0x40 /* LED control */
+#define E1CFG_GRUN 0x80 /* global run flag */
+
+/*
+ * Tau/E1 sync control register bits.
+ */
+#define E1SYN_ENS0 0x01 /* enable channel 0 sync mode */
+#define E1SYN_ENS1 0x02 /* enable channel 1 sync mode */
+
+/*
+ * Tau/E1 status register bits.
+ */
+#define E1SR_E0_IRQ0 0x01 /* E0 controller interrupt 0 */
+#define E1SR_E0_IRQ1 0x02 /* E0 controller interrupt 1 */
+#define E1SR_E1_IRQ0 0x04 /* E1 controller interrupt 0 */
+#define E1SR_E1_IRQ1 0x08 /* E1 controller interrupt 1 */
+#define E1SR_SCC_IRQ 0x10 /* serial controller interrupt */
+#define E1SR_TP0 0x20 /* channel 0 is twisted pair */
+#define E1SR_TP1 0x40 /* channel 1 is twisted pair */
+#define E1SR_REV 0x80 /* Tau/E1 revision */
+
+/*
+ * Tau/E1 serial memory register bits.
+ */
+
+/*------------------------------------------------------------
+ * Tau/G.703 model.
+ */
+#define GLCR0(p) GR(p,3) /* line control register 0, write only */
+#define GMD0(p) GR(p,4) /* mode register 0, write only */
+#define GMD1(p) GR(p,5) /* mode register 1, write only */
+#define GMD2(p) GR(p,6) /* mode register 2, write only */
+#define GLCR1(p) GR(p,7) /* line control register 1, write only */
+#define GERR(p) GR(p,0) /* error register, read/write */
+#define GLQ(p) GR(p,1) /* line quality register, read only */
+#define GLDR(p) GR(p,2) /* loop detect request, read only */
+
+/*
+ * Tau/G.703 mode register 0/1 bits.
+ */
+#define GMD_2048 0x00 /* 2048 kbit/sec */
+#define GMD_1024 0x02 /* 1024 kbit/sec */
+#define GMD_512 0x03 /* 512 kbit/sec */
+#define GMD_256 0x04 /* 256 kbit/sec */
+#define GMD_128 0x05 /* 128 kbit/sec */
+#define GMD_64 0x06 /* 64 kbit/sec */
+
+#define GMD_RSYNC 0x08 /* receive synchronization */
+#define GMD_PCE_PCM2 0x10 /* precoder enable, mode PCM2 */
+#define GMD_PCE_PCM2D 0x20 /* precoder enable, mode PCM2D */
+
+#define GMD0_SDI 0x40 /* serial data input */
+#define GMD0_SCLK 0x80 /* serial data clock */
+
+#define GMD1_NCS0 0x40 /* chip select 0 inverted */
+#define GMD1_NCS1 0x80 /* chip select 1 inverted */
+
+/*
+ * Tau/G.703 mode register 2 bits.
+ */
+#define GMD2_SERIAL 0x01 /* channel 1 serial interface V.35/RS-232/etc */
+#define GMD2_LED 0x02 /* LED control */
+#define GMD2_RAW0 0x04 /* channel 0 raw mode (byte-sync) */
+#define GMD2_RAW1 0x08 /* channel 1 raw mode (byte-sync) */
+
+/*
+ * Tau/G.703 interrupt status register bits.
+ */
+#define GERR_BPV0 0x01 /* channel 0 bipolar violation */
+#define GERR_ERR0 0x02 /* channel 0 test error */
+#define GERR_BPV1 0x04 /* channel 1 bipolar violation */
+#define GERR_ERR1 0x08 /* channel 1 test error */
+
+/*
+ * Tau/G.703 line quality register bits.
+ */
+#define GLQ_MASK 0x03 /* channel 0 mask */
+#define GLQ_SHIFT 2 /* channel 1 shift */
+
+#define GLQ_DB0 0x00 /* channel 0 level 0.0 dB */
+#define GLQ_DB95 0x01 /* channel 0 level -9.5 dB */
+#define GLQ_DB195 0x02 /* channel 0 level -19.5 dB */
+#define GLQ_DB285 0x03 /* channel 0 level -28.5 dB */
+
+/*
+ * Tau/G.703 serial data output register bits.
+ */
+#define GLDR_C0 0x01 /* chip 0 serial data output */
+#define GLDR_LREQ0 0x02 /* channel 0 remote loop request */
+#define GLDR_C1 0x04 /* chip 1 serial data output */
+#define GLDR_LREQ1 0x08 /* channel 1 remote loop request */
+
+/*
+ * Tau/G.703 line control register 0/1 bits.
+ */
+#define GLCR_RENABLE 0x00 /* normal mode, auto remote loop enabled */
+#define GLCR_RDISABLE 0x01 /* normal mode, auto remote loop disabled */
+#define GLCR_RREFUSE 0x02 /* send the remote loop request sequence */
+#define GLCR_RREQUEST 0x03 /* send the remote loop refuse sequence */
diff --git a/sys/dev/ctau/ctddk.c b/sys/dev/ctau/ctddk.c
new file mode 100644
index 000000000000..92f98056697f
--- /dev/null
+++ b/sys/dev/ctau/ctddk.c
@@ -0,0 +1,1162 @@
+/*
+ * DDK library for Cronyx-Tau adapters.
+ *
+ * Copyright (C) 1998-1999 Cronyx Engineering.
+ * Author: Alexander Kvitchenko, <aak@cronyx.ru>
+ *
+ * Copyright (C) 1999-2003 Cronyx Engineering.
+ * Author: Roman Kurakin, <rik@cronyx.ru>
+ *
+ * This source is derived from
+ * Diagnose utility for Cronyx-Tau adapter:
+ * by Serge Vakulenko, <vak@cronyx.ru>
+ *
+ * This software is distributed with NO WARRANTIES, not even the implied
+ * warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Authors grant any other persons or organisations permission to use
+ * or modify this software as long as this message is kept with the software,
+ * all derivative works or modified versions.
+ *
+ * Cronyx Id: ctddk.c,v 1.1.2.3 2003/11/14 16:55:36 rik Exp $
+ */
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <dev/cx/machdep.h>
+#include <dev/ctau/ctddk.h>
+#include <dev/ctau/ctaureg.h>
+#include <dev/ctau/hdc64570.h>
+#include <dev/ctau/ds2153.h>
+#include <dev/ctau/am8530.h>
+#include <dev/ctau/lxt318.h>
+#include <dev/cx/cronyxfw.h>
+#include <dev/ctau/ctaufw.h>
+#include <dev/ctau/ctau2fw.h>
+
+#ifndef CT_DDK_NO_G703
+#include <dev/ctau/ctaug7fw.h>
+#endif
+
+#ifndef CT_DDK_NO_E1
+#include <dev/ctau/ctaue1fw.h>
+#endif
+
+static void ct_hdlc_interrupt (ct_chan_t *c, int imvr);
+static void ct_e1_interrupt (ct_board_t *b);
+static void ct_scc_interrupt (ct_board_t *b);
+static void ct_e1timer_interrupt (ct_chan_t *c);
+
+static short porttab [] = { /* standard base port set */
+ 0x200, 0x220, 0x240, 0x260, 0x280, 0x2a0, 0x2c0, 0x2e0,
+ 0x300, 0x320, 0x340, 0x360, 0x380, 0x3a0, 0x3c0, 0x3e0, 0
+};
+
+int ct_find (port_t *board_ports)
+{
+ int i, n;
+
+ for (i=0, n=0; porttab[i] && n<NBRD; i++)
+ if (ct_probe_board (porttab[i], -1, -1))
+ board_ports[n++] = porttab[i];
+ return n;
+}
+
+int ct_open_board (ct_board_t *b, int num, port_t port, int irq, int dma)
+{
+ ct_chan_t *c;
+ const unsigned char *fw;
+ const cr_dat_tst_t *ft;
+ long flen;
+
+ if (num >= NBRD || ! ct_probe_board (port, irq, dma))
+ return 0;
+
+ /* init callback pointers */
+ for (c=b->chan; c<b->chan+NCHAN; ++c) {
+ c->call_on_tx = 0;
+ c->call_on_rx = 0;
+ c->call_on_msig = 0;
+ c->call_on_scc = 0;
+ c->call_on_err = 0;
+ }
+
+ /* init DDK channel variables */
+ for (c=b->chan; c<b->chan+NCHAN; ++c) {
+ c->sccrx_empty = c->scctx_empty = 1;
+ c->sccrx_b = c->sccrx_e = 0;
+ c->scctx_b = c->scctx_e = 0;
+ c->e1_first_int = 1;
+ }
+
+ /* init board structure */
+ ct_init (b, num, port, irq, dma, ctau_fw_data,
+ ctau_fw_len, ctau_fw_tvec, ctau2_fw_data);
+
+ /* determine which firmware should be loaded */
+ fw = ctau_fw_data;
+ flen = ctau_fw_len;
+ ft = ctau_fw_tvec;
+ switch (b->type) {
+ case B_TAU2:
+ case B_TAU2_G703:
+ case B_TAU2_E1:
+ case B_TAU2_E1D:
+ fw = ctau2_fw_data;
+ flen = 0;
+ ft = 0;
+ break;
+#ifndef CT_DDK_NO_G703
+ case B_TAU_G703:
+ fw = ctaug703_fw_data;
+ flen = ctaug703_fw_len;
+ ft = ctaug703_fw_tvec;
+ break;
+#endif
+#ifndef CT_DDK_NO_E1
+ case B_TAU_E1:
+ fw = ctaue1_fw_data;
+ flen = ctaue1_fw_len;
+ ft = ctaue1_fw_tvec;
+ break;
+#endif
+ }
+ /* Load firmware and set up board */
+ return ct_setup_board (b, fw, flen, ft);
+}
+
+/*
+ * must be called on the exit
+ */
+void ct_close_board (ct_board_t *b)
+{
+ ct_setup_board (b, 0, 0, 0);
+
+ /* Reset the controller. */
+ outb (BCR0(b->port), 0);
+
+ /* Disable DMA channel. */
+ ct_disable_dma (b);
+
+ ct_led (b, 0);
+}
+
+static void ct_g703_rate (ct_chan_t *c, unsigned long rate)
+{
+ c->gopt.rate = rate;
+ ct_setup_g703 (c->board);
+}
+
+/*
+ * Set up baud rate.
+ */
+static void ct_chan_baud (ct_chan_t *c, unsigned long baud)
+{
+ c->baud = baud;
+ if (baud) {
+ c->hopt.txs = CLK_INT;
+ } else {
+ ct_set_dpll (c, 0);
+ c->hopt.txs = CLK_LINE;
+ }
+ ct_update_chan (c);
+}
+
+void ct_set_baud (ct_chan_t *c, unsigned long baud)
+{
+ unsigned long r;
+
+ if (c->mode == M_E1)
+ return;
+ if (c->mode == M_G703) {
+ if (baud >= 2048000) r = 2048;
+ else if (baud >= 1024000) r = 1024;
+ else if (baud >= 512000) r = 512;
+ else if (baud >= 256000) r = 256;
+ else if (baud >= 128000) r = 128;
+ else r = 64;
+ ct_g703_rate (c, r);
+ } else
+ ct_chan_baud (c, baud);
+}
+
+/*
+ * Configure Tau/E1 board.
+ */
+static void ct_e1_config (ct_board_t *b, unsigned char cfg)
+{
+ if (cfg == b->opt.cfg)
+ return;
+
+ if (cfg == CFG_B)
+ b->chan[1].mode = M_HDLC;
+ else
+ b->chan[1].mode = M_E1;
+
+ /* Recovering synchronization */
+ if (b->opt.cfg == CFG_B) {
+ ct_chan_baud (b->chan+1, 0);
+ ct_set_invtxc (b->chan+1, 0);
+ ct_set_invrxc (b->chan+1, 0);
+ ct_set_nrzi (b->chan+1, 0);
+ }
+ b->opt.cfg = cfg;
+ ct_setup_e1 (b);
+}
+
+/*
+ * Config Tau/G.703 board
+ */
+static void ct_g703_config (ct_board_t *b, unsigned char cfg)
+{
+ if (cfg == b->opt.cfg)
+ return;
+
+ if (cfg == CFG_B)
+ b->chan[1].mode = M_HDLC;
+ else
+ b->chan[1].mode = M_G703;
+
+ /* Recovering synchronization */
+ if (b->opt.cfg == CFG_B) {
+ ct_chan_baud (b->chan+1, 0);
+ ct_set_invtxc (b->chan+1, 0);
+ ct_set_invrxc (b->chan+1, 0);
+ ct_set_nrzi (b->chan+1, 0);
+ }
+ b->opt.cfg = cfg;
+ ct_setup_g703 (b);
+}
+
+int ct_set_clk (ct_chan_t *c, int clk)
+{
+ if (c->num)
+ c->board->opt.clk1 = clk;
+ else
+ c->board->opt.clk0 = clk;
+ if (c->mode == M_E1) {
+ ct_setup_e1 (c->board);
+ return 0;
+ } if (c->mode == M_G703) {
+ ct_setup_g703 (c->board);
+ return 0;
+ } else
+ return -1;
+}
+
+int ct_get_clk (ct_chan_t *c)
+{
+ return c->num ? c->board->opt.clk1 : c->board->opt.clk0;
+}
+
+int ct_set_ts (ct_chan_t *c, unsigned long ts)
+{
+ if (! (c->mode == M_E1))
+ return -1;
+ if (c->num)
+ c->board->opt.s1 = ts;
+ else
+ c->board->opt.s0 = ts;
+ ct_setup_e1 (c->board);
+ return 0;
+}
+
+int ct_set_subchan (ct_board_t *b, unsigned long ts)
+{
+ if (b->chan[0].mode != M_E1)
+ return -1;
+ b->opt.s2 = ts;
+ ct_setup_e1 (b);
+ return 0;
+}
+
+int ct_set_higain (ct_chan_t *c, int on)
+{
+ if (! (c->mode == M_E1))
+ return -1;
+ c->gopt.higain = on ? 1 : 0;
+ ct_setup_e1 (c->board);
+ return 0;
+}
+
+/*
+ * Start service channel.
+ */
+void ct_start_scc (ct_chan_t *c, char *rxbuf, char *txbuf)
+{
+ c->sccrx = rxbuf;
+ c->scctx = txbuf;
+
+ /* Enable interrupts from service channel. */
+ if (c->board->type != B_TAU_E1 && c->board->type != B_TAU_E1C &&
+ c->board->type != B_TAU2_E1)
+ return;
+
+ cte_out2 (c->board->port, c->num ? AM_IMR : AM_IMR | AM_A,
+ IMR_TX | IMR_RX_ALL);
+ cte_out2 (c->board->port, AM_MICR, MICR_MIE);
+}
+
+/*
+ * Start HDLC channel.
+ */
+void ct_start_chan (ct_chan_t *c, ct_buf_t *cb, unsigned long phys)
+{
+ int i, ier0;
+ unsigned long bound;
+
+ if (cb) {
+ /* Set up descriptors, align to 64k boundary.
+ * If 64k boundary is inside buffers
+ * buffers will begin on this boundary
+ * (there were allocated additional space for this) */
+ c->tdesc = cb->descbuf;
+ c->tdphys[0] = phys + ((char*)c->tdesc - (char*)cb);
+ bound = ((c->tdphys[0] + 0xffff) & ~(0xffffUL));
+ if (bound < c->tdphys[0] + 2*NBUF*sizeof(ct_desc_t)) {
+ c->tdesc = (ct_desc_t*) ((char*) c->tdesc +
+ (bound - c->tdphys[0]));
+ c->tdphys[0] = bound;
+ }
+ c->rdesc = c->tdesc + NBUF;
+
+ /* Set buffers. */
+ for (i=0; i<NBUF; ++i) {
+ c->rbuf[i] = cb->rbuffer[i];
+ c->tbuf[i] = cb->tbuffer[i];
+ }
+
+ /* Set buffer physical addresses */
+ for (i=0; i<NBUF; ++i) {
+ c->rphys[i] = phys + ((char*)c->rbuf[i] - (char*)cb);
+ c->tphys[i] = phys + ((char*)c->tbuf[i] - (char*)cb);
+ c->rdphys[i] = phys + ((char*)(c->rdesc+i) - (char*)cb);
+ c->tdphys[i] = phys + ((char*)(c->tdesc+i) - (char*)cb);
+ }
+ }
+ /* Set up block chains. */
+ /* receive buffers */
+ for (i=0; i<NBUF; ++i) {
+ B_NEXT (c->rdesc[i]) = c->rdphys[(i+1) % NBUF] & 0xffff;
+ B_PTR (c->rdesc[i]) = c->rphys[i];
+ B_LEN (c->rdesc[i]) = DMABUFSZ;
+ B_STATUS (c->rdesc[i]) = 0;
+ }
+ /* transmit buffers */
+ for (i=0; i<NBUF; ++i) {
+ B_NEXT (c->tdesc[i]) = c->tdphys[(i+1) % NBUF] & 0xffff;
+ B_PTR (c->tdesc[i]) = c->tphys[i];
+ B_LEN (c->tdesc[i]) = DMABUFSZ;
+ B_STATUS (c->tdesc[i]) = FST_EOM;
+ c->attach[i] = 0;
+ }
+
+ if (c->type & T_E1) {
+ c->mode = M_E1;
+ if (c->num && c->board->opt.cfg == CFG_B)
+ c->mode = M_HDLC;
+ }
+ if (c->type & T_G703) {
+ c->mode = M_G703;
+ if (c->num && c->board->opt.cfg == CFG_B)
+ c->mode = M_HDLC;
+ }
+ ct_update_chan (c);
+
+ /* enable receiver */
+ c->rn = 0;
+ ct_start_receiver (c, 1 , c->rphys[0], DMABUFSZ, c->rdphys[0],
+ c->rdphys[NBUF-1]);
+ outb (c->IE1, inb (c->IE1) | IE1_CDCDE);
+ outb (c->IE0, inb (c->IE0) | IE0_RX_INTE);
+ ier0 = inb (IER0(c->board->port));
+ ier0 |= c->num ? IER0_RX_INTE_1 : IER0_RX_INTE_0;
+ outb (IER0(c->board->port), ier0);
+
+ /* Enable transmitter */
+ c->tn = 0;
+ c->te = 0;
+ ct_start_transmitter (c, 1 , c->tphys[0], DMABUFSZ, c->tdphys[0],
+ c->tdphys[0]);
+ outb (c->TX.DIR, DIR_CHAIN_EOME | DIR_CHAIN_BOFE | DIR_CHAIN_COFE);
+
+ /* Clear DTR and RTS */
+ ct_set_dtr (c, 0);
+ ct_set_rts (c, 0);
+}
+
+/*
+ * Turn receiver on/off
+ */
+void ct_enable_receive (ct_chan_t *c, int on)
+{
+ unsigned char st3, ier0, ier1;
+
+ st3 = inb (c->ST3);
+ /* enable or disable receiver */
+ if (on && ! (st3 & ST3_RX_ENABLED)) {
+ c->rn = 0;
+ ct_start_receiver (c, 1 , c->rphys[0], DMABUFSZ, c->rdphys[0],
+ c->rdphys[NBUF-1]);
+ /* enable status interrupt */
+ outb (c->IE1, inb (c->IE1) | IE1_CDCDE);
+ outb (c->IE0, inb (c->IE0) | IE0_RX_INTE);
+ ier0 = inb (IER0(c->board->port));
+ ier0 |= c->num ? IER0_RX_INTE_1 : IER0_RX_INTE_0;
+ outb (IER0(c->board->port), ier0);
+ ct_set_rts (c, 1);
+ } else if (! on && (st3 & ST3_RX_ENABLED)) {
+ ct_set_rts (c, 0);
+ outb (c->CMD, CMD_RX_DISABLE);
+
+ ier0 = inb (IER0(c->board->port));
+ ier0 &= c->num ? ~(IER0_RX_INTE_1 | IER0_RX_RDYE_1) :
+ ~(IER0_RX_INTE_0 | IER0_RX_RDYE_0);
+ outb (IER0(c->board->port), ier0);
+
+ ier1 = inb (IER1(c->board->port));
+ ier1 &= c->num ? ~(IER1_RX_DMERE_1 | IER1_RX_DME_1) :
+ ~(IER1_RX_DMERE_0 | IER1_RX_DME_0);
+ outb (IER1(c->board->port), ier1);
+ }
+
+}
+
+/*
+ * Turn transmitter on/off
+ */
+void ct_enable_transmit (ct_chan_t *c, int on)
+{
+ unsigned char st3, ier0, ier1;
+
+ st3 = inb (c->ST3);
+ /* enable or disable receiver */
+ if (on && ! (st3 & ST3_TX_ENABLED)) {
+ c->tn = 0;
+ c->te = 0;
+ ct_start_transmitter (c, 1 , c->tphys[0], DMABUFSZ,
+ c->tdphys[0], c->tdphys[0]);
+ outb (c->TX.DIR,
+ DIR_CHAIN_EOME | DIR_CHAIN_BOFE | DIR_CHAIN_COFE);
+ } else if (! on && (st3 & ST3_TX_ENABLED)) {
+ outb (c->CMD, CMD_TX_DISABLE);
+
+ ier0 = inb (IER0(c->board->port));
+ ier0 &= c->num ? ~(IER0_TX_INTE_1 | IER0_TX_RDYE_1) :
+ ~(IER0_TX_INTE_0 | IER0_TX_RDYE_0);
+ outb (IER0(c->board->port), ier0);
+
+ ier1 = inb (IER1(c->board->port));
+ ier1 &= c->num ? ~(IER1_TX_DMERE_1 | IER1_TX_DME_1) :
+ ~(IER1_TX_DMERE_0 | IER1_TX_DME_0);
+ outb (IER1(c->board->port), ier1);
+ }
+
+}
+
+int ct_set_config (ct_board_t *b, int cfg)
+{
+ if (b->opt.cfg == cfg)
+ return 0;
+ switch (b->type) {
+ case B_TAU_G703:
+ case B_TAU_G703C:
+ case B_TAU2_G703:
+ if (cfg == CFG_C)
+ return -1;
+ ct_g703_config (b, cfg);
+ return 0;
+ case B_TAU_E1:
+ case B_TAU_E1C:
+ case B_TAU_E1D:
+ case B_TAU2_E1:
+ case B_TAU2_E1D:
+ ct_e1_config (b, cfg);
+ return 0;
+ default:
+ return cfg == CFG_A ? 0 : -1;
+ }
+}
+
+int ct_get_dpll (ct_chan_t *c)
+{
+ return (c->hopt.rxs == CLK_RXS_DPLL_INT);
+}
+
+void ct_set_dpll (ct_chan_t *c, int on)
+{
+ if (on && ct_get_baud (c))
+ c->hopt.rxs = CLK_RXS_DPLL_INT;
+ else
+ c->hopt.rxs = CLK_LINE;
+ ct_update_chan (c);
+}
+
+int ct_get_nrzi (ct_chan_t *c)
+{
+ return (c->opt.md2.encod == MD2_ENCOD_NRZI);
+}
+
+/*
+ * Change line encoding to NRZI, default is NRZ
+ */
+void ct_set_nrzi (ct_chan_t *c, int on)
+{
+ c->opt.md2.encod = on ? MD2_ENCOD_NRZI : MD2_ENCOD_NRZ;
+ outb (c->MD2, *(unsigned char*)&c->opt.md2);
+}
+
+/*
+ * Transmit clock inversion
+ */
+void ct_set_invtxc (ct_chan_t *c, int on)
+{
+ if (on) c->board->bcr2 |= (c->num ? BCR2_INVTXC1 : BCR2_INVTXC0);
+ else c->board->bcr2 &= ~(c->num ? BCR2_INVTXC1 : BCR2_INVTXC0);
+ outb (BCR2(c->board->port), c->board->bcr2);
+}
+
+int ct_get_invtxc (ct_chan_t *c)
+{
+ return (c->board->bcr2 & (c->num ? BCR2_INVTXC1 : BCR2_INVTXC0)) != 0;
+}
+
+/*
+ * Receive clock inversion
+ */
+void ct_set_invrxc (ct_chan_t *c, int on)
+{
+ if (on) c->board->bcr2 |= (c->num ? BCR2_INVRXC1 : BCR2_INVRXC0);
+ else c->board->bcr2 &= ~(c->num ? BCR2_INVRXC1 : BCR2_INVRXC0);
+ outb (BCR2(c->board->port), c->board->bcr2);
+}
+
+int ct_get_invrxc (ct_chan_t *c)
+{
+ return (c->board->bcr2 & (c->num ? BCR2_INVRXC1 : BCR2_INVRXC0)) != 0;
+}
+
+/*
+ * Main interrupt handler
+ */
+void ct_int_handler (ct_board_t *b)
+{
+ unsigned char bsr0, imvr;
+ ct_chan_t *c;
+
+ while ((bsr0 = inb (BSR0(b->port))) & BSR0_INTR) {
+ if (bsr0 & BSR0_RDYERR) {
+ outb (BCR1(b->port), b->bcr1);
+ } else if (bsr0 & BSR0_GINT) {
+ if (b->type == B_TAU_E1 || b->type == B_TAU_E1C ||
+ b->type == B_TAU_E1D || b->type == B_TAU2_E1 ||
+ b->type == B_TAU2_E1D)
+ ct_e1_interrupt (b);
+ } else if (bsr0 & BSR0_HDINT) {
+ /* Read the interrupt modified vector register. */
+ imvr = inb (IACK(b->port));
+ c = b->chan + (imvr & IMVR_CHAN1 ? 1 : 0);
+ ct_hdlc_interrupt (c, imvr);
+ }
+ }
+}
+
+static void ct_e1_interrupt (ct_board_t *b)
+{
+ unsigned char sr;
+
+ sr = inb (E1SR(b->port));
+
+ if (sr & E1SR_SCC_IRQ) ct_scc_interrupt (b);
+ if (sr & E1SR_E0_IRQ1) ct_e1timer_interrupt (b->chan + 0);
+ if (sr & E1SR_E1_IRQ1) ct_e1timer_interrupt (b->chan + 1);
+}
+
+static void ct_scc_interrupt (ct_board_t *b)
+{
+ unsigned char rsr;
+ unsigned char ivr, a = AM_A; /* assume channel A */
+ ct_chan_t *c = b->chan;
+
+ ivr = cte_in2 (b->port, AM_IVR);
+ if (! (ivr & IVR_A))
+ ++c, a = 0; /* really channel B */
+
+ switch (ivr & IVR_REASON) {
+ case IVR_TXRDY: /* transmitter empty */
+ c->scctx_b = (c->scctx_b + 1) % SCCBUFSZ;
+ if (c->scctx_b == c->scctx_e) {
+ c->scctx_empty = 1;
+ cte_out2c (c, AM_CR | CR_RST_TXINT);
+ } else
+ cte_out2d (c, c->scctx[c->scctx_b]);
+ break;
+
+ case IVR_RXERR: /* receive error */
+ case IVR_RX: /* receive character available */
+ rsr = cte_in2 (b->port, a|AM_RSR);
+
+ if (rsr & RSR_RXOVRN) { /* rx overrun */
+ if (c->call_on_err)
+ c->call_on_err (c, CT_SCC_OVERRUN);
+ } else if (rsr & RSR_FRME) { /* frame error */
+ if (c->call_on_err)
+ c->call_on_err (c, CT_SCC_FRAME);
+ } else {
+ c->sccrx[c->sccrx_e] = cte_in2d (c);
+ c->sccrx_e = (c->sccrx_e + 1) % SCCBUFSZ;
+ c->sccrx_empty &= 0;
+ if (c->call_on_scc)
+ c->call_on_scc (c);
+ if (c->sccrx_e == c->sccrx_b && ! c->sccrx_empty)
+ if (c->call_on_err)
+ c->call_on_err (c, CT_SCC_OVERFLOW);
+ }
+ if (rsr)
+ cte_out2c (c, CR_RST_ERROR);
+ break;
+
+ case IVR_STATUS: /* external status interrupt */
+ /* Unexpected SCC status interrupt. */
+ cte_out2c (c, CR_RST_EXTINT);
+ break;
+ }
+}
+
+/*
+ * G.703 mode channel: process 1-second timer interrupts.
+ * Read error and request registers, and fill the status field.
+ */
+void ct_g703_timer (ct_chan_t *c)
+{
+ int bpv, cd, tsterr, tstreq;
+
+ /* Count seconds.
+ * During the first second after the channel startup
+ * the status registers are not stable yet,
+ * we will so skip the first second. */
+ ++c->cursec;
+ if (c->mode != M_G703)
+ return;
+ if (c->totsec + c->cursec <= 1)
+ return;
+ c->status = 0;
+
+ cd = ct_get_cd (c);
+
+ bpv = inb (GERR (c->board->port)) & (c->num ? GERR_BPV1 : GERR_BPV0);
+ outb (GERR (c->board->port), bpv);
+
+ tsterr = inb (GERR (c->board->port)) & (c->num ? GERR_ERR1 : GERR_ERR0);
+ outb (GERR (c->board->port), tsterr);
+
+ tstreq = inb (GLDR (c->board->port)) &
+ (c->num ? GLDR_LREQ1 : GLDR_LREQ0);
+ outb (GLDR (c->board->port), tstreq);
+
+ /* Compute the SNMP-compatible channel status. */
+ if (bpv)
+ ++c->currnt.bpv; /* bipolar violation */
+ if (! cd)
+ c->status |= ESTS_LOS; /* loss of signal */
+ if (tsterr)
+ c->status |= ESTS_TSTERR; /* test error */
+ if (tstreq)
+ c->status |= ESTS_TSTREQ; /* test code detected */
+
+ if (! c->status)
+ c->status = ESTS_NOALARM;
+
+ /* Unavaiable second -- loss of carrier, or receiving test code. */
+ if ((! cd) || tstreq)
+ /* Unavailable second -- no other counters. */
+ ++c->currnt.uas;
+ else {
+ /* Line errored second -- any BPV. */
+ if (bpv)
+ ++c->currnt.les;
+
+ /* Collect data for computing
+ * degraded minutes. */
+ ++c->degsec;
+ if (cd && bpv)
+ ++c->degerr;
+ }
+
+ /* Degraded minutes -- having more than 50% error intervals. */
+ if (c->cursec / 60 == 0) {
+ if (c->degerr*2 > c->degsec)
+ ++c->currnt.dm;
+ c->degsec = 0;
+ c->degerr = 0;
+ }
+
+ /* Rotate statistics every 15 minutes. */
+ if (c->cursec > 15*60) {
+ int i;
+
+ for (i=47; i>0; --i)
+ c->interval[i] = c->interval[i-1];
+ c->interval[0] = c->currnt;
+
+ /* Accumulate total statistics. */
+ c->total.bpv += c->currnt.bpv;
+ c->total.fse += c->currnt.fse;
+ c->total.crce += c->currnt.crce;
+ c->total.rcrce += c->currnt.rcrce;
+ c->total.uas += c->currnt.uas;
+ c->total.les += c->currnt.les;
+ c->total.es += c->currnt.es;
+ c->total.bes += c->currnt.bes;
+ c->total.ses += c->currnt.ses;
+ c->total.oofs += c->currnt.oofs;
+ c->total.css += c->currnt.css;
+ c->total.dm += c->currnt.dm;
+ memset (&c->currnt, 0, sizeof (c->currnt));
+
+ c->totsec += c->cursec;
+ c->cursec = 0;
+ }
+}
+
+static void ct_e1timer_interrupt (ct_chan_t *c)
+{
+ unsigned short port;
+ unsigned char sr1, sr2, ssr;
+ unsigned long bpv, fas, crc4, ebit, pcv, oof;
+
+ port = c->num ? E1CS1(c->board->port) : E1CS0(c->board->port);
+
+ sr2 = cte_ins (port, DS_SR2, 0xff);
+ /* is it timer interrupt ? */
+ if (! (sr2 & SR2_SEC))
+ return;
+
+ /* first interrupts should be ignored */
+ if (c->e1_first_int > 0) {
+ c->e1_first_int --;
+ return;
+ }
+
+ ++c->cursec;
+ c->status = 0;
+
+ /* Compute the SNMP-compatible channel status. */
+ sr1 = cte_ins (port, DS_SR1, 0xff);
+ ssr = cte_in (port, DS_SSR);
+ oof = 0;
+
+ if (sr1 & (SR1_RCL | SR1_RLOS))
+ c->status |= ESTS_LOS; /* loss of signal */
+ if (sr1 & SR1_RUA1)
+ c->status |= ESTS_AIS; /* receiving all ones */
+ if (c->gopt.cas && (sr1 & SR1_RSA1))
+ c->status |= ESTS_AIS16; /* signaling all ones */
+ if (c->gopt.cas && (sr1 & SR1_RDMA))
+ c->status |= ESTS_FARLOMF; /* alarm in timeslot 16 */
+ if (sr1 & SR1_RRA)
+ c->status |= ESTS_FARLOF; /* far loss of framing */
+
+ /* Controlled slip second -- any slip event. */
+ if (sr1 & SR1_RSLIP) {
+ ++c->currnt.css;
+ }
+
+ if (ssr & SSR_SYNC) {
+ c->status |= ESTS_LOF; /* loss of framing */
+ ++oof; /* out of framing */
+ }
+ if ((c->gopt.cas && (ssr & SSR_SYNC_CAS)) ||
+ (c->gopt.crc4 && (ssr & SSR_SYNC_CRC4))) {
+ c->status |= ESTS_LOMF; /* loss of multiframing */
+ ++oof; /* out of framing */
+ }
+
+ if (! c->status)
+ c->status = ESTS_NOALARM;
+
+ /* Get error counters. */
+ bpv = VCR (cte_in (port, DS_VCR1), cte_in (port, DS_VCR2));
+ fas = FASCR (cte_in (port, DS_FASCR1), cte_in (port, DS_FASCR2));
+ crc4 = CRCCR (cte_in (port, DS_CRCCR1), cte_in (port, DS_CRCCR2));
+ ebit = EBCR (cte_in (port, DS_EBCR1), cte_in (port, DS_EBCR2));
+
+ c->currnt.bpv += bpv;
+ c->currnt.fse += fas;
+ if (c->gopt.crc4) {
+ c->currnt.crce += crc4;
+ c->currnt.rcrce += ebit;
+ }
+
+ /* Path code violation is frame sync error if CRC4 disabled,
+ * or CRC error if CRC4 enabled. */
+ pcv = fas;
+ if (c->gopt.crc4)
+ pcv += crc4;
+
+ /* Unavaiable second -- receiving all ones, or
+ * loss of carrier, or loss of signal. */
+ if (sr1 & (SR1_RUA1 | SR1_RCL | SR1_RLOS))
+ /* Unavailable second -- no other counters. */
+ ++c->currnt.uas;
+ else {
+ /* Line errored second -- any BPV. */
+ if (bpv)
+ ++c->currnt.les;
+
+ /* Errored second -- any PCV, or out of frame sync,
+ * or any slip events. */
+ if (pcv || oof || (sr1 & SR1_RSLIP))
+ ++c->currnt.es;
+
+ /* Severely errored framing second -- out of frame sync. */
+ if (oof)
+ ++c->currnt.oofs;
+
+ /* Severely errored seconds --
+ * 832 or more PCVs, or 2048 or more BPVs. */
+ if (bpv >= 2048 || pcv >= 832)
+ ++c->currnt.ses;
+ else {
+ /* Bursty errored seconds --
+ * no SES and more than 1 PCV. */
+ if (pcv > 1)
+ ++c->currnt.bes;
+
+ /* Collect data for computing
+ * degraded minutes. */
+ ++c->degsec;
+ c->degerr += bpv + pcv;
+ }
+ }
+
+ /* Degraded minutes -- having error rate more than 10e-6,
+ * not counting unavailable and severely errored seconds. */
+ if (c->cursec / 60 == 0) {
+ if (c->degerr > c->degsec * 2048 / 1000)
+ ++c->currnt.dm;
+ c->degsec = 0;
+ c->degerr = 0;
+ }
+
+ /* Rotate statistics every 15 minutes. */
+ if (c->cursec > 15*60) {
+ int i;
+
+ for (i=47; i>0; --i)
+ c->interval[i] = c->interval[i-1];
+ c->interval[0] = c->currnt;
+
+ /* Accumulate total statistics. */
+ c->total.bpv += c->currnt.bpv;
+ c->total.fse += c->currnt.fse;
+ c->total.crce += c->currnt.crce;
+ c->total.rcrce += c->currnt.rcrce;
+ c->total.uas += c->currnt.uas;
+ c->total.les += c->currnt.les;
+ c->total.es += c->currnt.es;
+ c->total.bes += c->currnt.bes;
+ c->total.ses += c->currnt.ses;
+ c->total.oofs += c->currnt.oofs;
+ c->total.css += c->currnt.css;
+ c->total.dm += c->currnt.dm;
+ for (i=0; i<sizeof (c->currnt); ++i)
+ *(((char *)(&c->currnt))+i)=0;
+
+ c->totsec += c->cursec;
+ c->cursec = 0;
+ }
+}
+
+static void ct_hdlc_interrupt (ct_chan_t *c, int imvr)
+{
+ int i, dsr, st1, st2, cda;
+
+ switch (imvr & IMVR_VECT_MASK) {
+ case IMVR_RX_DMOK: /* receive DMA normal end */
+ dsr = inb (c->RX.DSR);
+ cda = inw (c->RX.CDA);
+ for (i=0; i<NBUF; ++i)
+ if (cda == (unsigned short) c->rdphys[i])
+ break;
+ if (i >= NBUF)
+ i = c->rn; /* cannot happen */
+ while (c->rn != i) {
+ int cst = B_STATUS (c->rdesc[c->rn]);
+ if (cst == FST_EOM) {
+ /* process data */
+ if (c->call_on_rx)
+ c->call_on_rx (c, c->rbuf[c->rn],
+ B_LEN(c->rdesc[c->rn]));
+ ++c->ipkts;
+ c->ibytes += B_LEN(c->rdesc[c->rn]);
+ } else if (cst & ST2_OVRN) {
+ /* Receive overrun error */
+ if (c->call_on_err)
+ c->call_on_err (c, CT_OVERRUN);
+ ++c->ierrs;
+ } else if (cst & (ST2_HDLC_RBIT |
+ ST2_HDLC_ABT | ST2_HDLC_SHRT)) {
+ /* Receive frame error */
+ if (c->call_on_err)
+ c->call_on_err (c, CT_FRAME);
+ ++c->ierrs;
+ } else if ((cst & ST2_HDLC_EOM)
+ && (cst & ST2_HDLC_CRCE)) {
+ /* Receive CRC error */
+ if (c->call_on_err)
+ c->call_on_err (c, CT_CRC);
+ ++c->ierrs;
+ } else if (! (cst & ST2_HDLC_EOM)) {
+ /* Frame dose not fit in the buffer.*/
+ if (c->call_on_err)
+ c->call_on_err (c, CT_OVERFLOW);
+ ++c->ierrs;
+ }
+
+ B_NEXT (c->rdesc[c->rn]) =
+ c->rdphys[(c->rn+1) % NBUF] & 0xffff;
+ B_PTR (c->rdesc[c->rn]) = c->rphys[c->rn];
+ B_LEN (c->rdesc[c->rn]) = DMABUFSZ;
+ B_STATUS (c->rdesc[c->rn]) = 0;
+ c->rn = (c->rn + 1) % NBUF;
+ }
+ outw (c->RX.EDA, (unsigned short) c->rdphys[(i+NBUF-1)%NBUF]);
+ /* Clear DMA interrupt. */
+ if (inb (c->RX.DSR) & DSR_DMA_ENABLE) {
+ outb (c->RX.DSR, dsr);
+ } else {
+ outb (c->RX.DSR, (dsr & 0xfc) | DSR_DMA_ENABLE);
+ }
+ ++c->rintr;
+ break;
+
+ case IMVR_RX_INT: /* receive status */
+ st1 = inb (c->ST1);
+ st2 = inb (c->ST2);
+ if (st1 & ST1_CDCD){
+ if (c->call_on_msig)
+ c->call_on_msig (c);
+ ++c->mintr;
+ }
+ /* Clear interrupt. */
+ outb (c->ST1, st1);
+ outb (c->ST2, st2);
+ ++c->rintr;
+ break;
+
+ case IMVR_RX_DMERR: /* receive DMA error */
+ dsr = inb (c->RX.DSR);
+ if (dsr & (DSR_CHAIN_BOF | DSR_CHAIN_COF)) {
+ if (c->call_on_err)
+ c->call_on_err (c, CT_OVERFLOW);
+ ++c->ierrs;
+ for (i=0; i<NBUF; ++i) {
+ B_LEN (c->rdesc[i]) = DMABUFSZ;
+ B_STATUS (c->rdesc[i]) = 0;
+ }
+ ct_start_receiver (c, 1, c->rphys[0], DMABUFSZ,
+ c->rdphys[0], c->rdphys[NBUF-1]);
+ c->rn = 0;
+ }
+ /* Clear DMA interrupt. */
+ outb (c->RX.DSR, dsr);
+ ++c->rintr;
+ break;
+
+ case IMVR_TX_DMOK: /* transmit DMA normal end */
+ case IMVR_TX_DMERR: /* transmit DMA error */
+ dsr = inb (c->TX.DSR);
+ cda = inw (c->TX.CDA);
+
+ for (i=0; i<NBUF && cda != (unsigned short)c->tdphys[i]; ++i)
+ continue;
+ if (i >= NBUF)
+ i = 1; /* cannot happen */
+ if (dsr & DSR_CHAIN_COF) {
+ if (c->call_on_err)
+ c->call_on_err (c, CT_UNDERRUN);
+ ++c->oerrs;
+ }
+ while (c->tn != i) {
+ if (c->call_on_tx)
+ c->call_on_tx (c, c->attach[c->tn],
+ B_LEN(c->tdesc[c->tn]));
+ ++c->opkts;
+ c->obytes += B_LEN(c->tdesc[c->tn]);
+
+ c->tn = (c->tn + 1) % NBUF;
+ /* Clear DMA interrupt. */
+ outb (c->TX.DSR, DSR_CHAIN_EOM | DSR_DMA_CONTINUE);
+ }
+ outb (c->TX.DSR, dsr & ~DSR_CHAIN_EOM);
+ ++c->tintr;
+ break;
+
+ case IMVR_TX_INT: /* transmit error, HDLC only */
+ st1 = inb (c->ST1);
+ if (st1 & ST1_HDLC_UDRN) {
+ if (c->call_on_err)
+ c->call_on_err (c, CT_UNDERRUN);
+ ++c->oerrs;
+ }
+ outb (c->ST1, st1);
+ ++c->tintr;
+ break;
+
+ default:
+ /* Unknown interrupt - cannot happen. */
+ break;
+ }
+}
+
+int ct_receive_enabled (ct_chan_t *c)
+{
+ int st3;
+
+ st3 = inb (c->ST3);
+ return (st3 & ST3_RX_ENABLED) ? 1 : 0;
+}
+
+int ct_transmit_enabled (ct_chan_t *c)
+{
+ int st3;
+
+ st3 = inb (c->ST3);
+ return (st3 & ST3_TX_ENABLED) ? 1 : 0;
+}
+
+int ct_buf_free (ct_chan_t *c)
+{
+ return (NBUF + c->tn - c->te - 1) % NBUF;
+}
+
+int ct_send_packet (ct_chan_t *c, unsigned char *data, int len,
+ void *attachment)
+{
+ int dsr, ne;
+
+ if (len > DMABUFSZ)
+ return -2;
+
+ /* Is it really free? */
+ ne = (c->te+1) % NBUF;
+ if (ne == c->tn)
+ return -1;
+
+ /* Set up the tx descriptor. */
+ B_LEN (c->tdesc[c->te]) = len;
+ B_STATUS (c->tdesc[c->te]) = FST_EOM;
+ c->attach[c->te] = attachment;
+ if (c->tbuf[c->te] != data)
+ memcpy (c->tbuf[c->te], data, len);
+
+ /* Start the transmitter. */
+ c->te = ne;
+ outw (c->TX.EDA, (unsigned short) c->tdphys[ne]);
+ dsr = inb (c->TX.DSR);
+ if (! (dsr & DSR_DMA_ENABLE))
+ outb (c->TX.DSR, DSR_DMA_ENABLE);
+ return 0;
+}
+
+int scc_write (ct_chan_t *c, unsigned char *d, int len)
+{
+ int i, free;
+
+ /* determining free place in buffer */
+ if (c->scctx_empty)
+ free = SCCBUFSZ;
+ else
+ free = (SCCBUFSZ + c->scctx_b - c->scctx_e) % SCCBUFSZ;
+
+ if (len > free)
+ return -1;
+
+ for (i=0; i<len; i++){
+ c->scctx[c->scctx_e] = d[i];
+ c->scctx_e = (c->scctx_e+1) % SCCBUFSZ;
+ }
+ if (c->scctx_empty && len) {
+ cte_out2d (c, c->scctx[c->scctx_b]);
+ c->scctx_empty = 0;
+ }
+ return 0;
+}
+
+int scc_read (ct_chan_t *c, unsigned char *d, int len)
+{
+ int i, bytes;
+
+ if (c->sccrx_empty)
+ bytes = 0;
+ else
+ bytes = (SCCBUFSZ + c->sccrx_e - 1 - c->sccrx_b) %
+ SCCBUFSZ + 1;
+ if (len > bytes)
+ return -1;
+
+ for (i=0; i<len; i++){
+ d[i] = c->sccrx[c->sccrx_b];
+ c->sccrx_b = (c->sccrx_b+1) % SCCBUFSZ;
+ }
+ if (c->sccrx_b==c->sccrx_e)
+ c->sccrx_empty = 1;
+ return 0;
+}
+
+int sccrx_check (ct_chan_t *c)
+{
+ int bytes;
+
+ if (c->sccrx_empty)
+ bytes = 0;
+ else
+ bytes = (SCCBUFSZ + c->sccrx_e - 1 - c->sccrx_b) %
+ SCCBUFSZ + 1;
+ return bytes;
+}
+
+int scc_read_byte (ct_chan_t *c)
+{
+ unsigned char a;
+
+ if (scc_read (c, &a, 1) < 0)
+ return -1;
+ return a;
+}
+
+int scc_write_byte (ct_chan_t *c, unsigned char b)
+{
+ if (scc_write (c, &b, 1) < 0)
+ return -1;
+ return b;
+}
+
+/*
+ * Register event processing functions
+ */
+void ct_register_transmit (ct_chan_t *c, void (*func) (ct_chan_t*, void*, int))
+{
+ c->call_on_tx = func;
+}
+
+void ct_register_receive (ct_chan_t *c, void (*func) (ct_chan_t*, char*, int))
+{
+ c->call_on_rx = func;
+}
+
+void ct_register_error (ct_chan_t *c, void (*func) (ct_chan_t*, int))
+{
+ c->call_on_err = func;
+}
+
+void ct_register_scc (ct_chan_t *c, void (*func) (ct_chan_t*))
+{
+ c->call_on_scc = func;
+}
+
+void ct_register_modem (ct_chan_t *c, void (*func) (ct_chan_t*))
+{
+ c->call_on_msig = func;
+}
diff --git a/sys/dev/ctau/ctddk.h b/sys/dev/ctau/ctddk.h
new file mode 100644
index 000000000000..d48e1092319a
--- /dev/null
+++ b/sys/dev/ctau/ctddk.h
@@ -0,0 +1,606 @@
+/*
+ * Defines for Cronyx-Tau adapter driver.
+ *
+ * Copyright (C) 1994-2003 Cronyx Engineering.
+ * Author: Serge Vakulenko, <vak@cronyx.ru>
+ *
+ * This software is distributed with NO WARRANTIES, not even the implied
+ * warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Authors grant any other persons or organisations permission to use
+ * or modify this software as long as this message is kept with the software,
+ * all derivative works or modified versions.
+ *
+ * Cronyx Id: ctddk.h,v 1.1.2.3 2003/12/11 17:33:44 rik Exp $
+ * $FreeBSD$
+ */
+#define NBRD 3 /* the maximum number of installed boards */
+#define NPORT 32 /* the number of i/o ports per board */
+#define NCHAN 2 /* the number of channels on the board */
+#define NBUF 4 /* the number of buffers per direction */
+#define DMABUFSZ 1600 /* buffer size */
+#define SCCBUFSZ 50
+
+#ifndef port_t
+# ifdef _M_ALPHA /* port address on Alpha under */
+# define port_t unsigned long /* Windows NT is 32 bit long */
+# else
+# define port_t unsigned short /* all other architectures */
+# endif /* have 16-bit port addresses */
+#endif
+
+/*
+ * There are tree models of Tau adapters.
+ * Each of two channels of the adapter is assigned a type:
+ *
+ * Channel 0 Channel 1
+ * ------------------------------------------
+ * Tau T_SERIAL T_SERIAL
+ * Tau/E1 T_E1 T_E1_SERIAL
+ * Tau/G703 T_G703 T_G703_SERIAL
+ *
+ * Each channel could work in one of several modes:
+ *
+ * Channel 0 Channel 1
+ * ------------------------------------------
+ * Tau M_ASYNC, M_ASYNC,
+ * M_HDLC M_HDLC
+ * ------------------------------------------
+ * Tau/E1 M_E1, M_E1,
+ * M_E1 & CFG_D, M_E1 & CFG_D,
+ * M_ASYNC,
+ * M_HDLC
+ * ------------------------------------------
+ * Tau/G703 M_G703, M_G703,
+ * M_ASYNC,
+ * M_HDLC
+ * ------------------------------------------
+ */
+#define B_TAU 0 /* Tau - basic model */
+#define B_TAU_E1 1 /* Tau/E1 */
+#define B_TAU_G703 2 /* Tau/G.703 */
+#define B_TAU_E1C 3 /* Tau/E1 revision C */
+#define B_TAU_E1D 4 /* Tau/E1 revision C with phony mode support */
+#define B_TAU_G703C 5 /* Tau/G.703 revision C */
+#define B_TAU2 6 /* Tau2 - basic model */
+#define B_TAU2_E1 7 /* Tau2/E1 */
+#define B_TAU2_E1D 8 /* Tau2/E1 with phony mode support */
+#define B_TAU2_G703 9 /* Tau2/G.703 */
+
+#define T_SERIAL 1
+#define T_E1 2
+#define T_G703 4
+#define T_E1_SERIAL (T_E1 | T_SERIAL)
+#define T_G703_SERIAL (T_G703 | T_SERIAL)
+
+#define M_ASYNC 0 /* asynchronous mode */
+#define M_HDLC 1 /* bit-sync mode (HDLC) */
+#define M_G703 2
+#define M_E1 3
+
+#define CFG_A 0
+#define CFG_B 1
+#define CFG_C 2
+#define CFG_D 3
+
+/* E1/G.703 interfaces - i0, i1
+ * Digital interface - d0
+ *
+ *
+ * Configuration
+ * ---------------------------------------------------
+ * CFG_A | i0<->ct0 i1<->ct1
+ * ---------------------------------------------------
+ * CFG_B | i0<->ct0 d0<->ct1
+ * | ^
+ * | |
+ * | v
+ * | i1
+ * ---------------------------------------------------
+ * CFG_C | ct0<->i0<->ct1
+ * | ^
+ * | |
+ * | v
+ * | i1
+ * ---------------------------------------------------
+ * CFG_D | i0(e1)<->hdlc<->hdlc<->ct0(e1)
+ * ONLY TAU/E1 | i1(e1)<->hdlc<->hdlc<->ct1(e1)
+ * |
+ */
+
+/*
+ * Mode register 0 (MD0) bits.
+ */
+#define MD0_STOPB_1 0 /* 1 stop bit */
+#define MD0_STOPB_15 1 /* 1.5 stop bits */
+#define MD0_STOPB_2 2 /* 2 stop bits */
+
+#define MD0_MODE_ASYNC 0 /* asynchronous mode */
+#define MD0_MODE_EXTSYNC 3 /* external byte-sync mode */
+#define MD0_MODE_HDLC 4 /* HDLC mode */
+
+typedef struct {
+ unsigned stopb : 2; /* stop bit length */
+ unsigned : 2;
+ unsigned cts_rts_dcd : 1; /* auto-enable CTS/DCD/RTS */
+ unsigned mode : 3; /* protocol mode */
+} ct_md0_async_t;
+
+typedef struct {
+ unsigned crcpre : 1; /* CRC preset 1s / 0s */
+ unsigned ccitt : 1; /* CRC-CCITT / CRC-16 */
+ unsigned crc : 1; /* CRC enable */
+ unsigned : 1;
+ unsigned cts_dcd : 1; /* auto-enable CTS/DCD */
+ unsigned mode : 3; /* protocol mode */
+} ct_md0_hdlc_t;
+
+/*
+ * Mode register 1 (MD1) bits.
+ */
+#define MD1_PAR_NO 0 /* no parity */
+#define MD1_PAR_CMD 1 /* parity bit appended by command */
+#define MD1_PAR_EVEN 2 /* even parity */
+#define MD1_PAR_ODD 3 /* odd parity */
+
+#define MD1_CLEN_8 0 /* 8 bits/character */
+#define MD1_CLEN_7 1 /* 7 bits/character */
+#define MD1_CLEN_6 2 /* 6 bits/character */
+#define MD1_CLEN_5 3 /* 5 bits/character */
+
+#define MD1_CLK_1 0 /* 1/1 clock rate */
+#define MD1_CLK_16 1 /* 1/16 clock rate */
+#define MD1_CLK_32 2 /* 1/32 clock rate */
+#define MD1_CLK_64 3 /* 1/64 clock rate */
+
+#define MD1_ADDR_NOCHK 0 /* do not check address field */
+#define MD1_ADDR_SNGLE1 1 /* single address 1 */
+#define MD1_ADDR_SNGLE2 2 /* single address 2 */
+#define MD1_ADDR_DUAL 3 /* dual address */
+
+typedef struct {
+ unsigned parmode : 2; /* parity mode */
+ unsigned rxclen : 2; /* receive character length */
+ unsigned txclen : 2; /* transmit character length */
+ unsigned clk : 2; /* clock rate */
+} ct_md1_async_t;
+
+typedef struct {
+ unsigned : 6;
+ unsigned addr : 2; /* address field check */
+} ct_md1_hdlc_t;
+
+/*
+ * Mode register 2 (MD2) bits.
+ */
+#define MD2_FDX 0 /* full duplex communication */
+#define MD2_RLOOP 1 /* remote loopback (auto echo) */
+#define MD2_LLOOP 3 /* local+remote loopback */
+
+#define MD2_DPLL_CLK_8 0 /* x8 ADPLL clock rate */
+#define MD2_DPLL_CLK_16 1 /* x16 ADPLL clock rate */
+#define MD2_DPLL_CLK_32 2 /* x32 ADPLL clock rate */
+
+#define MD2_ENCOD_NRZ 0 /* NRZ encoding */
+#define MD2_ENCOD_NRZI 1 /* NRZI encoding */
+#define MD2_ENCOD_MANCHESTER 4 /* Manchester encoding */
+#define MD2_ENCOD_FM0 5 /* FM0 encoding */
+#define MD2_ENCOD_FM1 6 /* FM1 encoding */
+
+typedef struct {
+ unsigned loop : 2; /* loopback mode */
+ unsigned : 1;
+ unsigned dpll_clk : 2; /* ADPLL clock rate */
+ unsigned encod : 3; /* signal encoding NRZ/NRZI/etc. */
+} ct_md2_t;
+
+/*
+ * DMA priority control register (PCR) values.
+ */
+#define PCR_PRIO_0_1 0 /* priority c0r > c0t > c1r > c1t */
+#define PCR_PRIO_1_0 1 /* priority c1r > c1t > c0r > c0t */
+#define PCR_PRIO_RX_TX 2 /* priority c0r > c1r > c0t > c1t */
+#define PCR_PRIO_TX_RX 3 /* priority c0t > c1t > c0r > c1r */
+#define PCR_PRIO_ROTATE 4 /* rotation priority -c0r-c0t-c1r-c1t- */
+
+typedef struct {
+ unsigned prio : 3; /* priority of channels */
+ unsigned noshare : 1; /* 1 - chan holds the bus until end of data */
+ /* 0 - all channels share the the bus hold */
+ unsigned release : 1; /* 1 - release the bus between transfers */
+ /* 0 - hold the bus until all transfers done */
+} ct_pcr_t;
+
+typedef struct { /* hdlc channel options */
+ ct_md0_hdlc_t md0; /* mode register 0 */
+ ct_md1_hdlc_t md1; /* mode register 1 */
+ unsigned char ctl; /* control register */
+ unsigned char sa0; /* sync/address register 0 */
+ unsigned char sa1; /* sync/address register 1 */
+ unsigned char rxs; /* receive clock source */
+ unsigned char txs; /* transmit clock source */
+} ct_opt_hdlc_t;
+
+typedef struct {
+ ct_md2_t md2; /* mode register 2 */
+ unsigned char dma_rrc; /* DMA mode receive FIFO ready level */
+ unsigned char dma_trc0; /* DMA mode transmit FIFO empty mark */
+ unsigned char dma_trc1; /* DMA mode transmit FIFO full mark */
+ unsigned char pio_rrc; /* port i/o mode receive FIFO ready level */
+ unsigned char pio_trc0; /* port i/o transmit FIFO empty mark */
+ unsigned char pio_trc1; /* port i/o transmit FIFO full mark */
+} ct_chan_opt_t;
+
+/*
+ * Option CLK is valid for both E1 and G.703 models.
+ * Options RATE, PCE, TEST are for G.703 only.
+ */
+#define GCLK_INT 0 /* internal transmit clock source */
+#define GCLK_RCV 1 /* transmit clock source = receive */
+#define GCLK_RCLKO 2 /* tclk = receive clock of another channel */
+
+#define GTEST_DIS 0 /* test disabled, normal operation */
+#define GTEST_0 1 /* test "all zeros" */
+#define GTEST_1 2 /* test "all ones" */
+#define GTEST_01 3 /* test "0/1" */
+
+typedef struct { /* E1/G.703 channel options */
+ unsigned char hdb3; /* encoding HDB3/AMI */
+ unsigned char pce; /* precoder enable */
+ unsigned char test; /* test mode 0/1/01/disable */
+ unsigned char crc4; /* E1 CRC4 enable */
+ unsigned char cas; /* E1 signalling mode CAS/CCS */
+ unsigned char higain; /* E1 high gain amplifier (30 dB) */
+ unsigned char phony; /* E1 phony mode */
+ unsigned char pce2; /* old PCM2 precoder compatibility */
+ unsigned long rate; /* data rate 2048/1024/512/256/128/64 kbit/s */
+ unsigned short level; /* G.703 input signal level, -cB */
+} ct_opt_g703_t;
+
+typedef struct {
+ unsigned char bcr2; /* board control register 2 */
+ ct_pcr_t pcr; /* DMA priority control register */
+ unsigned char clk0; /* E1/G.703 chan 0 txclk src int/rcv/rclki */
+ unsigned char clk1; /* E1/G.703 chan 1 txclk src int/rcv/rclki */
+ unsigned char cfg; /* E1 configuration II/HI/K */
+ unsigned long s0; /* E1 channel 0 timeslot mask */
+ unsigned long s1; /* E1 channel 1 timeslot mask */
+ unsigned long s2; /* E1 subchannel pass-through timeslot mask */
+} ct_board_opt_t;
+
+/*
+ * Board control register 2 bits.
+ */
+#define BCR2_INVTXC0 0x10 /* channel 0 invert transmit clock */
+#define BCR2_INVTXC1 0x20 /* channel 1 invert transmit clock */
+#define BCR2_INVRXC0 0x40 /* channel 0 invert receive clock */
+#define BCR2_INVRXC1 0x80 /* channel 1 invert receive clock */
+
+#define BCR2_BUS_UNLIM 0x01 /* unlimited DMA master burst length */
+#define BCR2_BUS_RFST 0x02 /* fast read cycle bus timing */
+#define BCR2_BUS_WFST 0x04 /* fast write cycle bus timing */
+
+/*
+ * Receive/transmit clock source register (RXS/TXS) bits - from hdc64570.h.
+ */
+#define CLK_MASK 0x70 /* RXC/TXC clock input mask */
+#define CLK_LINE 0x00 /* RXC/TXC line input */
+#define CLK_INT 0x40 /* internal baud rate generator */
+
+#define CLK_RXS_LINE_NS 0x20 /* RXC line with noise suppression */
+#define CLK_RXS_DPLL_INT 0x60 /* ADPLL based on internal BRG */
+#define CLK_RXS_DPLL_LINE 0x70 /* ADPLL based on RXC line */
+
+#define CLK_TXS_RECV 0x60 /* receive clock */
+
+/*
+ * Control register (CTL) bits - from hdc64570.h.
+ */
+#define CTL_RTS_INV 0x01 /* RTS control bit (inverted) */
+#define CTL_SYNCLD 0x04 /* load SYN characters */
+#define CTL_BRK 0x08 /* async: send break */
+#define CTL_IDLE_MARK 0 /* HDLC: when idle, transmit mark */
+#define CTL_IDLE_PTRN 0x10 /* HDLC: when idle, transmit an idle pattern */
+#define CTL_UDRN_ABORT 0 /* HDLC: on underrun - abort */
+#define CTL_UDRN_FCS 0x20 /* HDLC: on underrun - send FCS/flag */
+
+typedef struct {
+ unsigned long bpv; /* bipolar violations */
+ unsigned long fse; /* frame sync errors */
+ unsigned long crce; /* CRC errors */
+ unsigned long rcrce; /* remote CRC errors (E-bit) */
+ unsigned long uas; /* unavailable seconds */
+ unsigned long les; /* line errored seconds */
+ unsigned long es; /* errored seconds */
+ unsigned long bes; /* bursty errored seconds */
+ unsigned long ses; /* severely errored seconds */
+ unsigned long oofs; /* out of frame seconds */
+ unsigned long css; /* controlled slip seconds */
+ unsigned long dm; /* degraded minutes */
+} ct_gstat_t;
+
+#define ESTS_NOALARM 0x0001 /* no alarm present */
+#define ESTS_FARLOF 0x0002 /* receiving far loss of framing */
+#define ESTS_AIS 0x0008 /* receiving all ones */
+#define ESTS_LOF 0x0020 /* loss of framing */
+#define ESTS_LOS 0x0040 /* loss of signal */
+#define ESTS_AIS16 0x0100 /* receiving all ones in timeslot 16 */
+#define ESTS_FARLOMF 0x0200 /* receiving alarm in timeslot 16 */
+#define ESTS_LOMF 0x0400 /* loss of multiframe sync */
+#define ESTS_TSTREQ 0x0800 /* test code detected */
+#define ESTS_TSTERR 0x1000 /* test error */
+
+typedef struct {
+ unsigned char data[10];
+} ct_desc_t;
+
+typedef struct {
+ unsigned char tbuffer [NBUF] [DMABUFSZ]; /* transmit buffers */
+ unsigned char rbuffer [NBUF] [DMABUFSZ]; /* receive buffers */
+ ct_desc_t descbuf [4*NBUF]; /* descriptors */
+ /* double size for alignment */
+} ct_buf_t;
+
+#define B_NEXT(b) (*(unsigned short*)(b).data) /* next descriptor ptr */
+#define B_PTR(b) (*(unsigned long*) ((b).data+2)) /* ptr to data buffer */
+#define B_LEN(b) (*(unsigned short*)((b).data+6)) /* data buffer length */
+#define B_STATUS(b) (*(unsigned short*)((b).data+8)) /* buf status, see FST */
+
+typedef struct {
+ port_t DAR, DARB, SAR, SARB, CDA, EDA, BFL, BCR, DSR,
+ DMR, FCT, DIR, DCR, TCNT, TCONR, TCSR, TEPR;
+} ct_dmareg_t;
+
+#ifdef NDIS_MINIPORT_DRIVER
+typedef struct _ct_queue_t { /* packet queue */
+ PNDIS_WAN_PACKET head; /* first packet in queue */
+ PNDIS_WAN_PACKET tail; /* last packet in queue */
+} ct_queue_t;
+#endif
+
+typedef struct _ct_chan_t {
+ port_t MD0, MD1, MD2, CTL, RXS, TXS, TMC, CMD, ST0,
+ ST1, ST2, ST3, FST, IE0, IE1, IE2, FIE, SA0,
+ SA1, IDL, TRB, RRC, TRC0, TRC1, CST;
+ ct_dmareg_t RX; /* RX DMA/timer registers */
+ ct_dmareg_t TX; /* TX DMA/timer registers */
+
+ unsigned char num; /* channel number, 0..1 */
+ struct _ct_board_t *board; /* board pointer */
+ unsigned long baud; /* data rate */
+ unsigned char type; /* channel type */
+ unsigned char mode; /* channel mode */
+ ct_chan_opt_t opt; /* common channel options */
+ ct_opt_hdlc_t hopt; /* hdlc mode options */
+ ct_opt_g703_t gopt; /* E1/G.703 options */
+ unsigned char dtr; /* DTR signal value */
+ unsigned char rts; /* RTS signal value */
+ unsigned char lx; /* LXT input bit settings */
+
+ unsigned char *tbuf [NBUF]; /* transmit buffer */
+ ct_desc_t *tdesc; /* transmit buffer descriptors */
+ unsigned long tphys [NBUF]; /* transmit buffer phys address */
+ unsigned long tdphys [NBUF]; /* transmit descr phys addresses */
+ int tn; /* first active transmit buffer */
+ int te; /* first active transmit buffer */
+
+ unsigned char *rbuf [NBUF]; /* receive buffers */
+ ct_desc_t *rdesc; /* receive buffer descriptors */
+ unsigned long rphys [NBUF]; /* receive buffer phys address */
+ unsigned long rdphys [NBUF]; /* receive descr phys addresses */
+ int rn; /* first active receive buffer */
+
+ unsigned long rintr; /* receive interrupts */
+ unsigned long tintr; /* transmit interrupts */
+ unsigned long mintr; /* modem interrupts */
+ unsigned long ibytes; /* input bytes */
+ unsigned long ipkts; /* input packets */
+ unsigned long ierrs; /* input errors */
+ unsigned long obytes; /* output bytes */
+ unsigned long opkts; /* output packets */
+ unsigned long oerrs; /* output errors */
+
+ unsigned short status; /* line status bit mask */
+ unsigned long totsec; /* total seconds elapsed */
+ unsigned long cursec; /* total seconds elapsed */
+ unsigned long degsec; /* degraded seconds */
+ unsigned long degerr; /* errors during degraded seconds */
+ ct_gstat_t currnt; /* current 15-min interval data */
+ ct_gstat_t total; /* total statistics data */
+ ct_gstat_t interval [48]; /* 12 hour period data */
+
+ void *attach [NBUF]; /* system dependent data per buffer */
+ void *sys; /* system dependent data per channel */
+ int debug;
+
+ int e1_first_int;
+ unsigned char *sccrx, *scctx; /* pointers to SCC rx and tx buffers */
+ int sccrx_empty, scctx_empty; /* flags : set when buffer is empty */
+ int sccrx_b, scctx_b; /* first byte in queue */
+ int sccrx_e, scctx_e; /* first free byte in queue */
+
+ /* pointers to callback functions */
+ void (*call_on_tx) (struct _ct_chan_t*, void*, int);
+ void (*call_on_rx) (struct _ct_chan_t*, char*, int);
+ void (*call_on_msig) (struct _ct_chan_t*);
+ void (*call_on_scc) (struct _ct_chan_t*);
+ void (*call_on_err) (struct _ct_chan_t*, int);
+
+#ifdef NDIS_MINIPORT_DRIVER /* NDIS 3 - WinNT/Win95 */
+ HTAPI_LINE htline; /* TAPI line descriptor */
+ HTAPI_CALL htcall; /* TAPI call descriptor */
+ NDIS_HANDLE connect; /* WAN connection context */
+ ct_queue_t sendq; /* packets to transmit queue */
+ ct_queue_t busyq; /* transmit busy queue */
+ UINT state; /* line state mask */
+ int timo; /* state timeout counter */
+#endif
+} ct_chan_t;
+
+typedef struct _ct_board_t {
+ port_t port; /* base board port, 200..3e0 */
+ unsigned short num; /* board number, 0..2 */
+ unsigned char irq; /* intterupt request {3 5 7 10 11 12 15} */
+ unsigned char dma; /* DMA request {5 6 7} */
+ unsigned long osc; /* oscillator frequency: 10MHz or 8.192 */
+ unsigned char type; /* board type Tau/TauE1/TauG703 */
+ char name[16]; /* board version name */
+ unsigned char bcr0; /* BCR0 image */
+ unsigned char bcr1; /* BCR1 image */
+ unsigned char bcr2; /* BCR2 image */
+ unsigned char gmd0; /* G.703 MD0 register image */
+ unsigned char gmd1; /* G.703 MD1 register image */
+ unsigned char gmd2; /* G.703 MD2 register image */
+ unsigned char e1cfg; /* E1 CFG register image */
+ unsigned char e1syn; /* E1 SYN register image */
+ ct_board_opt_t opt; /* board options */
+ ct_chan_t chan[NCHAN]; /* channel structures */
+#ifdef NDIS_MINIPORT_DRIVER /* NDIS 3 - WinNT/Win95 */
+ PVOID ioaddr; /* mapped i/o port address */
+ NDIS_HANDLE mh; /* miniport adapter handler */
+ NDIS_MINIPORT_INTERRUPT irqh; /* interrupt handler */
+ NDIS_HANDLE dmah; /* dma channel handler */
+ ULONG bufsz; /* size of shared memory buffer */
+ PVOID buf; /* shared memory for adapter */
+ NDIS_PHYSICAL_ADDRESS bphys; /* shared memory phys address */
+ NDIS_SPIN_LOCK lock; /* lock descriptor */
+ ULONG debug; /* debug flags */
+ ULONG idbase; /* TAPI device identifier base number */
+ ULONG anum; /* adapter number, from inf setup script */
+ NDIS_MINIPORT_TIMER timer; /* periodic timer structure */
+#endif
+} ct_board_t;
+
+extern long ct_baud;
+extern unsigned char ct_chan_mode;
+
+extern ct_board_opt_t ct_board_opt_dflt; /* default board options */
+extern ct_chan_opt_t ct_chan_opt_dflt; /* default channel options */
+extern ct_opt_hdlc_t ct_opt_hdlc_dflt; /* default hdlc mode options */
+extern ct_opt_g703_t ct_opt_g703_dflt; /* default E1/G.703 options */
+
+struct _cr_dat_tst;
+int ct_probe_board (port_t port, int irq, int dma);
+void ct_init (ct_board_t *b, int num, port_t port, int irq, int dma,
+ const unsigned char *firmware, long bits,
+ const struct _cr_dat_tst *tst, const unsigned char *firmware2);
+void ct_init_board (ct_board_t *b, int num, port_t port, int irq, int dma,
+ int type, long osc);
+int ct_download (port_t port, const unsigned char *firmware, long bits,
+ const struct _cr_dat_tst *tst);
+int ct_download2 (port_t port, const unsigned char *firmware);
+int ct_setup_board (ct_board_t *b, const unsigned char *firmware,
+ long bits, const struct _cr_dat_tst *tst);
+void ct_setup_e1 (ct_board_t *b);
+void ct_setup_g703 (ct_board_t *b);
+void ct_setup_chan (ct_chan_t *c);
+void ct_update_chan (ct_chan_t *c);
+void ct_start_receiver (ct_chan_t *c, int dma, unsigned long buf1,
+ unsigned len, unsigned long buf, unsigned long lim);
+void ct_start_transmitter (ct_chan_t *c, int dma, unsigned long buf1,
+ unsigned len, unsigned long buf, unsigned long lim);
+void ct_set_dtr (ct_chan_t *c, int on);
+void ct_set_rts (ct_chan_t *c, int on);
+void ct_set_brk (ct_chan_t *c, int on);
+void ct_led (ct_board_t *b, int on);
+void ct_cmd (port_t base, int cmd);
+void ct_disable_dma (ct_board_t *b);
+void ct_reinit_board (ct_board_t *b);
+void ct_reinit_chan (ct_chan_t *c);
+int ct_get_dsr (ct_chan_t *c);
+int ct_get_cd (ct_chan_t *c);
+int ct_get_cts (ct_chan_t *c);
+int ct_get_lq (ct_chan_t *c);
+void ct_compute_clock (long hz, long baud, int *txbr, int *tmc);
+unsigned char cte_in (port_t base, unsigned char reg);
+void cte_out (port_t base, unsigned char reg, unsigned char val);
+unsigned char cte_ins (port_t base, unsigned char reg,
+ unsigned char mask);
+unsigned char cte_in2 (port_t base, unsigned char reg);
+void cte_out2 (port_t base, unsigned char reg, unsigned char val);
+void ctg_outx (ct_chan_t *c, unsigned char reg, unsigned char val);
+unsigned char ctg_inx (ct_chan_t *c, unsigned char reg);
+unsigned char cte_in2d (ct_chan_t *c);
+void cte_out2d (ct_chan_t *c, unsigned char val);
+void cte_out2c (ct_chan_t *c, unsigned char val);
+
+/* functions dealing with interrupt vector in DOS */
+#if defined (MSDOS) || defined (__MSDOS__)
+int ddk_int_alloc (int irq, void (*func)(), void *arg);
+int ddk_int_restore (int irq);
+#endif
+
+int ct_probe_irq (ct_board_t *b, int irq);
+void ct_int_handler (ct_board_t *b);
+void ct_g703_timer (ct_chan_t *c);
+
+/* DDK errors */
+#define CT_FRAME 1
+#define CT_CRC 2
+#define CT_OVERRUN 3
+#define CT_OVERFLOW 4
+#define CT_UNDERRUN 5
+#define CT_SCC_OVERRUN 6
+#define CT_SCC_FRAME 7
+#define CT_SCC_OVERFLOW 8
+
+int ct_open_board (ct_board_t *b, int num, port_t port, int irq, int dma);
+void ct_close_board (ct_board_t *b);
+int ct_find (port_t *board_ports);
+
+int ct_set_config (ct_board_t *b, int cfg);
+int ct_set_clk (ct_chan_t *c, int clk);
+int ct_set_ts (ct_chan_t *c, unsigned long ts);
+int ct_set_subchan (ct_board_t *b, unsigned long ts);
+int ct_set_higain (ct_chan_t *c, int on);
+void ct_set_phony (ct_chan_t *c, int on);
+
+#define ct_get_config(b) ((b)->opt.cfg)
+#define ct_get_subchan(b) ((b)->opt.s2)
+#define ct_get_higain(c) ((c)->gopt.higain)
+#define ct_get_phony(c) ((c)->gopt.phony)
+int ct_get_clk (ct_chan_t *c);
+unsigned long ct_get_ts (ct_chan_t *c);
+
+void ct_start_chan (ct_chan_t *c, ct_buf_t *cb, unsigned long phys);
+void ct_enable_receive (ct_chan_t *c, int on);
+void ct_enable_transmit (ct_chan_t *c, int on);
+int ct_receive_enabled (ct_chan_t *c);
+int ct_transmit_enabled (ct_chan_t *c);
+
+void ct_set_baud (ct_chan_t *c, unsigned long baud);
+unsigned long ct_get_baud (ct_chan_t *c);
+
+void ct_set_dpll (ct_chan_t *c, int on);
+int ct_get_dpll (ct_chan_t *c);
+
+void ct_set_nrzi (ct_chan_t *c, int on);
+int ct_get_nrzi (ct_chan_t *c);
+
+void ct_set_loop (ct_chan_t *c, int on);
+int ct_get_loop (ct_chan_t *c);
+
+void ct_set_invtxc (ct_chan_t *c, int on);
+int ct_get_invtxc (ct_chan_t *c);
+void ct_set_invrxc (ct_chan_t *c, int on);
+int ct_get_invrxc (ct_chan_t *c);
+
+int ct_buf_free (ct_chan_t *c);
+int ct_send_packet (ct_chan_t *c, unsigned char *data, int len,
+ void *attachment);
+
+void ct_start_scc (ct_chan_t *c, char *rxbuf, char * txbuf);
+int sccrx_check (ct_chan_t *c);
+int scc_read (ct_chan_t *c, unsigned char *d, int len);
+int scc_write (ct_chan_t *c, unsigned char *d, int len);
+int scc_read_byte (ct_chan_t *c);
+int scc_write_byte (ct_chan_t *c, unsigned char b);
+
+void ct_register_transmit (ct_chan_t *c,
+ void (*func) (ct_chan_t*, void *attachment, int len));
+void ct_register_receive (ct_chan_t *c,
+ void (*func) (ct_chan_t*, char *data, int len));
+void ct_register_error (ct_chan_t *c,
+ void (*func) (ct_chan_t *c, int data));
+void ct_register_modem (ct_chan_t *c, void (*func) (ct_chan_t *c));
+void ct_register_scc (ct_chan_t *c, void (*func) (ct_chan_t *c));
diff --git a/sys/dev/ctau/ds2153.h b/sys/dev/ctau/ds2153.h
new file mode 100644
index 000000000000..bb0241464a55
--- /dev/null
+++ b/sys/dev/ctau/ds2153.h
@@ -0,0 +1,290 @@
+/*
+ * Dallas DS2153, DS21x54 single-chip E1 tranceiver registers.
+ *
+ * Copyright (C) 1996 Cronyx Engineering.
+ * Author: Serge Vakulenko, <vak@cronyx.ru>
+ *
+ * This software is distributed with NO WARRANTIES, not even the implied
+ * warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Authors grant any other persons or organisations permission to use
+ * or modify this software as long as this message is kept with the software,
+ * all derivative works or modified versions.
+ *
+ * Cronyx Id: ds2153.h,v 1.2.4.1 2003/11/12 17:22:33 rik Exp $
+ * $FreeBSD$
+ */
+
+/*
+ * Control and test registers
+ */
+#define DS_RCR1 0x10 /* rw - receive control 1 */
+#define DS_RCR2 0x11 /* rw - receive control 2 */
+#define DS_TCR1 0x12 /* rw - transmit control 1 */
+#define DS_TCR2 0x13 /* rw - transmit control 2 */
+#define DS_CCR1 0x14 /* rw - common control 1 */
+#define DS_CCR2 0x1a /* rw - common control 2 */
+#define DS_CCR3 0x1b /* rw - common control 3 */
+#define DS_LICR 0x18 /* rw - line interface control */
+#define DS_IMR1 0x16 /* rw - interrupt mask 1 */
+#define DS_IMR2 0x17 /* rw - interrupt mask 2 */
+#define DS_TEST1 0x15 /* rw - test 1 */
+#define DS_TEST2 0x19 /* rw - test 2 */
+
+/*
+ * Status and information registers
+ */
+#define DS_RIR 0x08 /* r - receive information */
+#define DS_SSR 0x1e /* r - synchronizer status */
+#define DS_SR1 0x06 /* r - status 1 */
+#define DS_SR2 0x07 /* r - status 2 */
+
+/*
+ * Error count registers
+ */
+#define DS_VCR1 0x00 /* r - BPV or code violation count 1 */
+#define DS_VCR2 0x01 /* r - BPV or code violation count 2 */
+#define DS_CRCCR1 0x02 /* r - CRC4 error count 1 */
+#define DS_CRCCR2 0x03 /* r - CRC4 error count 2 */
+#define DS_EBCR1 0x04 /* r - E-bit count 1 */
+#define DS_EBCR2 0x05 /* r - E-bit count 2 */
+#define DS_FASCR1 0x02 /* r - FAS error count 1 */
+#define DS_FASCR2 0x04 /* r - FAS error count 2 */
+
+/*
+ * Signaling registers
+ */
+#define DS_RS 0x30 /* r - receive signaling 1..16 */
+#define DS_TS 0x40 /* rw - transmit signaling 1..16 */
+
+/*
+ * Transmit idle registers
+ */
+#define DS_TIR 0x26 /* rw - transmit idle 1..4 */
+#define DS_TIDR 0x2a /* rw - transmit idle definition */
+
+/*
+ * Clock blocking registers
+ */
+#define DS_RCBR 0x2b /* rw - receive channel blocking 1..4 */
+#define DS_TCBR 0x22 /* rw - transmit channel blocking 1..4 */
+
+/*
+ * Slot 0 registers
+ */
+#define DS_RAF 0x2f /* r - receive align frame */
+#define DS_RNAF 0x1f /* r - receive non-align frame */
+#define DS_TAF 0x20 /* rw - transmit align frame */
+#define DS_TNAF 0x21 /* rw - transmit non-align frame */
+
+/*----------------------------------------------
+ * Receive control register 1
+ */
+#define RCR1_RSO 0x00 /* RSYNC outputs frame boundaries */
+#define RCR1_RSI 0x20 /* RSYNC is input (elastic store) */
+#define RCR1_RSO_CAS 0x40 /* RSYNC outputs CAS multiframe boundaries */
+#define RCR1_RSO_CRC4 0xc0 /* RSYNC outputs CRC4 multiframe boundaries */
+
+#define RCR1_FRC 0x04 /* frame resync criteria */
+#define RCR1_SYNCD 0x02 /* auto resync disable */
+#define RCR1_RESYNC 0x01 /* force resync */
+
+/*
+ * Receive control register 2
+ */
+#define RCR2_SA_8 0x80 /* output Sa8 bit at RLINK pin */
+#define RCR2_SA_7 0x40 /* output Sa7 bit at RLINK pin */
+#define RCR2_SA_6 0x20 /* output Sa6 bit at RLINK pin */
+#define RCR2_SA_5 0x10 /* output Sa5 bit at RLINK pin */
+#define RCR2_SA_4 0x08 /* output Sa4 bit at RLINK pin */
+#define RCR2_RSCLKM 0x04 /* receive side SYSCLK mode 2048 */
+#define RCR2_RESE 0x02 /* receive side elastic store enable */
+
+/*
+ * Transmit control register 1
+ */
+#define TCR1_TFPT 0x40 /* source timeslot 0 from TSER pin */
+#define TCR1_T16S 0x20 /* source timeslot 16 from TS1..TS16 regs */
+#define TCR1_TUA1 0x10 /* transmit unframed all ones */
+#define TCR1_TSIS 0x08 /* source Si bits from TAF/TNAF registers */
+#define TCR1_TSA1 0x04 /* transmit timeslot 16 all ones */
+
+#define TCR1_TSI 0x00 /* TSYNC is input */
+#define TCR1_TSO 0x01 /* TSYNC outputs frame boundaries */
+#define TCR1_TSO_MF 0x03 /* TSYNC outputs CAS/CRC4 m/f boundaries */
+
+/*
+ * Transmit control register 2
+ */
+#define TCR2_SA_8 0x80 /* source Sa8 bit from TLINK pin */
+#define TCR2_SA_7 0x40 /* source Sa7 bit from TLINK pin */
+#define TCR2_SA_6 0x20 /* source Sa6 bit from TLINK pin */
+#define TCR2_SA_5 0x10 /* source Sa5 bit from TLINK pin */
+#define TCR2_SA_4 0x08 /* source Sa4 bit from TLINK pin */
+#define TCR2_AEBE 0x02 /* automatic E-bit enable */
+#define TCR2_P16F 0x01 /* pin 16 is Loss of Transmit Clock */
+
+/*
+ * Common control register 1
+ */
+#define CCR1_FLOOP 0x80 /* enable framer loopback */
+#define CCR1_THDB3 0x40 /* enable transmit HDB3 */
+#define CCR1_TG802 0x20 /* enable transmit G.802 */
+#define CCR1_TCRC4 0x10 /* enable transmit CRC4 */
+#define CCR1_CCS 0x08 /* common channel signaling mode */
+#define CCR1_RHDB3 0x04 /* enable receive HDB3 */
+#define CCR1_RG802 0x02 /* enable receive G.802 */
+#define CCR1_RCRC4 0x01 /* enable receive CRC4 */
+
+/*
+ * Common control register 2
+ */
+#define CCR2_EC625 0x80 /* update error counters every 62.5 ms */
+#define CCR2_CNTCV 0x40 /* count code violations */
+#define CCR2_AUTOAIS 0x20 /* automatic AIS generation */
+#define CCR2_AUTORA 0x10 /* automatic remote alarm generation */
+#define CCR2_LOFA1 0x08 /* force RSER to 1 under loss of frame align */
+#define CCR2_TRCLK 0x04 /* switch transmitter to RCLK if TCLK stops */
+#define CCR2_RLOOP 0x02 /* enable remote loopback */
+#define CCR2_LLOOP 0x01 /* enable local loopback */
+
+/*
+ * Common control register 3
+ */
+#define CCR3_TESE 0x80 /* enable transmit elastic store */
+#define CCR3_TCBFS 0x40 /* TCBRs define signaling bits to insert */
+#define CCR3_TIRSER 0x20 /* TIRs define data channels from RSER pin */
+#define CCR3_ESRESET 0x10 /* elastic store reset */
+#define CCR3_LIRESET 0x08 /* line interface reset */
+#define CCR3_THSE 0x04 /* insert signaling from TSIG into TSER */
+#define CCR3_TSCLKM 0x02 /* transmit backplane clock 2048 */
+
+/*
+ * Line interface control register
+ */
+#define LICR_DB21 0x80 /* return loss 21 dB */
+
+#define LICR_LB75 0x00 /* 75 Ohm normal */
+#define LICR_LB120 0x20 /* 120 Ohm normal */
+#define LICR_LB75P 0x40 /* 75 Ohm protected */
+#define LICR_LB120P 0x60 /* 120 Ohm protected */
+
+#define LICR_HIGAIN 0x10 /* receive gain 30 dB */
+#define LICR_JA_TX 0x08 /* transmit side jitter attenuator select */
+#define LICR_JA_LOW 0x04 /* low jitter attenuator depth (32 bits) */
+#define LICR_JA_DISABLE 0x02 /* disable jitter attenuator */
+#define LICR_POWERDOWN 0x01 /* transmit power down */
+
+/*----------------------------------------------
+ * Receive information register
+ */
+#define RIR_TES_FULL 0x80 /* transmit elastic store full */
+#define RIR_TES_EMPTY 0x40 /* transmit elastic store empty */
+#define RIR_JALT 0x20 /* jitter attenuation limit trip */
+#define RIR_ES_FULL 0x10 /* elastic store full */
+#define RIR_ES_EMPTY 0x08 /* elastic store empty */
+#define RIR_RESYNC_CRC 0x04 /* CRC4 resync (915/1000 errors) */
+#define RIR_RESYNC 0x02 /* frame resync (three consec errors) */
+#define RIR_RESYNC_CAS 0x01 /* CAS resync (two consec errors) */
+
+/*
+ * Synchronizer status register
+ */
+#define SSR_CSC(v) (((v) >> 2) & 0x3c | ((v) >> 3) & 1)
+ /* CRC4 sync counter (6 bits, bit 1 n/a) */
+#define SSR_SYNC 0x04 /* frame alignment sync active */
+#define SSR_SYNC_CAS 0x02 /* CAS multiframe sync active */
+#define SSR_SYNC_CRC4 0x01 /* CRC4 multiframe sync active */
+
+/*
+ * Status register 1
+ */
+#define SR1_RSA1 0x80 /* receive signaling all ones */
+#define SR1_RDMA 0x40 /* receive distant multiframe alarm */
+#define SR1_RSA0 0x20 /* receive signaling all zeros */
+#define SR1_RSLIP 0x10 /* receive elastic store slip event */
+#define SR1_RUA1 0x08 /* receive unframed all ones */
+#define SR1_RRA 0x04 /* receive remote alarm */
+#define SR1_RCL 0x02 /* receive carrier loss */
+#define SR1_RLOS 0x01 /* receive loss of sync */
+
+/*
+ * Status register 2
+ */
+#define SR2_RMF 0x80 /* receive CAS multiframe (every 2 ms) */
+#define SR2_RAF 0x40 /* receive align frame (every 250 us) */
+#define SR2_TMF 0x20 /* transmit multiframe (every 2 ms) */
+#define SR2_SEC 0x10 /* one second timer (or 62.5 ms) */
+#define SR2_TAF 0x08 /* transmit align frame (every 250 us) */
+#define SR2_LOTC 0x04 /* loss of transmit clock */
+#define SR2_RCMF 0x02 /* receive CRC4 multiframe (every 2 ms) */
+#define SR2_TSLIP 0x01 /* transmit elastic store slip event */
+
+/*
+ * Error count registers
+ */
+#define VCR(h,l) (((short) (h) << 8) | (l)) /* 16-bit code violation */
+#define CRCCR(h,l) (((short) (h) << 8 & 0x300) | (l)) /* 10-bit CRC4 error count */
+#define EBCR(h,l) (((short) (h) << 8 & 0x300) | (l)) /* 10-bit E-bit count */
+#define FASCR(h,l) (((short) (h) << 4 & 0xfc0) | (l) >> 2) /* 12-bit FAS error count */
+
+#define FASCRH(h) ((h) << 4) /* 12-bit FAS error count */
+#define FASCRL(l) ((l) >> 2) /* 12-bit FAS error count */
+
+/*
+ * DS21x54 additional registers
+ */
+#define DS_IDR 0x0f /* r - device id */
+#define DS_TSACR 0x1c /* rw - transmit Sa bit control */
+#define DS_CCR6 0x1d /* rw - common control 6 */
+
+#define DS_TSIAF 0x50 /* rw - transmit Si bits align frame */
+#define DS_TSINAF 0x51 /* rw - transmit Si bits non-align frame */
+#define DS_TRA 0x52 /* rw - transmit remote alarm bits */
+#define DS_TSA4 0x53 /* rw - transmit Sa4 bits */
+#define DS_TSA5 0x54 /* rw - transmit Sa5 bits */
+#define DS_TSA6 0x55 /* rw - transmit Sa6 bits */
+#define DS_TSA7 0x56 /* rw - transmit Sa7 bits */
+#define DS_TSA8 0x57 /* rw - transmit Sa8 bits */
+#define DS_RSIAF 0x58 /* r - receive Si bits align frame */
+#define DS_RSINAF 0x59 /* r - receive Si bits non-align frame */
+#define DS_RRA 0x5a /* r - receive remote alarm bits */
+#define DS_RSA4 0x5b /* r - receive Sa4 bits */
+#define DS_RSA5 0x5c /* r - receive Sa5 bits */
+#define DS_RSA6 0x5d /* r - receive Sa6 bits */
+#define DS_RSA7 0x5e /* r - receive Sa7 bits */
+#define DS_RSA8 0x5f /* r - receive Sa8 bits */
+
+#define DS_TCC1 0xa0 /* rw - transmit channel control 1 */
+#define DS_TCC2 0xa1 /* rw - transmit channel control 2 */
+#define DS_TCC3 0xa2 /* rw - transmit channel control 3 */
+#define DS_TCC4 0xa3 /* rw - transmit channel control 4 */
+#define DS_RCC1 0xa4 /* rw - receive channel control 1 */
+#define DS_RCC2 0xa5 /* rw - receive channel control 2 */
+#define DS_RCC3 0xa6 /* rw - receive channel control 3 */
+#define DS_RCC4 0xa7 /* rw - receive channel control 4 */
+
+#define DS_CCR4 0xa8 /* rw - common control 4 */
+#define DS_TDS0M 0xa9 /* r - transmit ds0 monitor */
+#define DS_CCR5 0xaa /* rw - common control 5 */
+#define DS_RDS0M 0xab /* r - receive ds0 monitor */
+#define DS_TEST3 0xac /* rw - test 3, set to 00h */
+
+#define DS_HCR 0xb0 /* rw - hdlc control */
+#define DS_HSR 0xb1 /* rw - hdlc status */
+#define DS_HIMR 0xb2 /* rw - hdlc interrupt mask */
+#define DS_RHIR 0xb3 /* rw - receive hdlc information */
+#define DS_RHFR 0xb4 /* rw - receive hdlc fifo */
+#define DS_IBO 0xb5 /* rw - interleave bus operation */
+#define DS_THIR 0xb6 /* rw - transmit hdlc information */
+#define DS_THFR 0xb7 /* rw - transmit hdlc fifo */
+#define DS_RDC1 0xb8 /* rw - receive hdlc ds0 control 1 */
+#define DS_RDC2 0xb9 /* rw - receive hdlc ds0 control 2 */
+#define DS_TDC1 0xba /* rw - transmit hdlc ds0 control 1 */
+#define DS_TDC2 0xbb /* rw - transmit hdlc ds0 control 2 */
+
+#define CCR4_RLB 0x80 /* enable remote loopback */
+#define CCR4_LLB 0x40 /* enable local loopback */
+#define CCR5_LIRST 0x80 /* line interface reset */
+#define CCR6_RESR 0x02 /* receive elastic store reset */
+#define CCR6_TESR 0x01 /* transmit elastic store reset */
diff --git a/sys/dev/ctau/hdc64570.h b/sys/dev/ctau/hdc64570.h
new file mode 100644
index 000000000000..978ff6ab20c5
--- /dev/null
+++ b/sys/dev/ctau/hdc64570.h
@@ -0,0 +1,492 @@
+/*
+ * Hitachi HD64570 serial communications adaptor registers.
+ *
+ * Copyright (C) 1996 Cronyx Engineering.
+ * Author: Serge Vakulenko, <vak@cronyx.ru>
+ *
+ * This software is distributed with NO WARRANTIES, not even the implied
+ * warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Authors grant any other persons or organisations permission to use
+ * or modify this software as long as this message is kept with the software,
+ * all derivative works or modified versions.
+ *
+ * Cronyx Id: hdc64570.h,v 1.1.2.2 2003/11/12 17:31:21 rik Exp $
+ * $FreeBSD$
+ */
+
+/*
+ * Low power mode control register.
+ */
+#define HD_LPR 0x00 /* low power register */
+
+/*
+ * Interrupt control registers.
+ */
+#define HD_IVR 0x1a /* interrupt vector register */
+#define HD_IMVR 0x1c /* interrupt modified vector register */
+#define HD_ITCR 0x18 /* interrupt control register */
+#define HD_ISR0 0x10 /* interrupt status register 0, ro */
+#define HD_ISR1 0x11 /* interrupt status register 1, ro */
+#define HD_ISR2 0x12 /* interrupt status register 2, ro */
+#define HD_IER0 0x14 /* interrupt enable register 0 */
+#define HD_IER1 0x15 /* interrupt enable register 1 */
+#define HD_IER2 0x16 /* interrupt enable register 2 */
+
+/*
+ * Multiprotocol serial communication interface registers.
+ */
+#define HD_MD0_0 0x2e /* mode register 0 chan 0 */
+#define HD_MD0_1 0x4e /* mode register 0 chan 1 */
+#define HD_MD1_0 0x2f /* mode register 1 chan 0 */
+#define HD_MD1_1 0x4f /* mode register 1 chan 1 */
+#define HD_MD2_0 0x30 /* mode register 2 chan 0 */
+#define HD_MD2_1 0x50 /* mode register 2 chan 1 */
+#define HD_CTL_0 0x31 /* control register chan 0 */
+#define HD_CTL_1 0x51 /* control register chan 1 */
+#define HD_RXS_0 0x36 /* RX clock source register chan 0 */
+#define HD_RXS_1 0x56 /* RX clock source register chan 1 */
+#define HD_TXS_0 0x37 /* TX clock source register chan 0 */
+#define HD_TXS_1 0x57 /* TX clock source register chan 1 */
+#define HD_TMC_0 0x35 /* time constant register chan 0 */
+#define HD_TMC_1 0x55 /* time constant register chan 1 */
+#define HD_CMD_0 0x2c /* command register chan 0, wo */
+#define HD_CMD_1 0x4c /* command register chan 1, wo */
+#define HD_ST0_0 0x22 /* status register 0 chan 0, ro */
+#define HD_ST0_1 0x42 /* status register 0 chan 1, ro */
+#define HD_ST1_0 0x23 /* status register 1 chan 0 */
+#define HD_ST1_1 0x43 /* status register 1 chan 1 */
+#define HD_ST2_0 0x24 /* status register 2 chan 0 */
+#define HD_ST2_1 0x44 /* status register 2 chan 1 */
+#define HD_ST3_0 0x25 /* status register 3 chan 0, ro */
+#define HD_ST3_1 0x45 /* status register 3 chan 1, ro */
+#define HD_FST_0 0x26 /* frame status register chan 0 */
+#define HD_FST_1 0x46 /* frame status register chan 1 */
+#define HD_IE0_0 0x28 /* interrupt enable register 0 chan 0 */
+#define HD_IE0_1 0x48 /* interrupt enable register 0 chan 1 */
+#define HD_IE1_0 0x29 /* interrupt enable register 1 chan 0 */
+#define HD_IE1_1 0x49 /* interrupt enable register 1 chan 1 */
+#define HD_IE2_0 0x2a /* interrupt enable register 2 chan 0 */
+#define HD_IE2_1 0x4a /* interrupt enable register 2 chan 1 */
+#define HD_FIE_0 0x2b /* frame interrupt enable register chan 0 */
+#define HD_FIE_1 0x4b /* frame interrupt enable register chan 1 */
+#define HD_SA0_0 0x32 /* sync/address register 0 chan 0 */
+#define HD_SA0_1 0x52 /* sync/address register 0 chan 1 */
+#define HD_SA1_0 0x33 /* sync/address register 1 chan 0 */
+#define HD_SA1_1 0x53 /* sync/address register 1 chan 1 */
+#define HD_IDL_0 0x34 /* idle pattern register chan 0 */
+#define HD_IDL_1 0x54 /* idle pattern register chan 1 */
+#define HD_TRB_0 0x20 /* TX/RX buffer register chan 0 */
+#define HD_TRB_1 0x40 /* TX/RX buffer register chan 1 */
+#define HD_RRC_0 0x3a /* RX ready control register chan 0 */
+#define HD_RRC_1 0x5a /* RX ready control register chan 1 */
+#define HD_TRC0_0 0x38 /* TX ready control register 0 chan 0 */
+#define HD_TRC0_1 0x58 /* TX ready control register 0 chan 1 */
+#define HD_TRC1_0 0x39 /* TX ready control register 1 chan 0 */
+#define HD_TRC1_1 0x59 /* TX ready control register 1 chan 1 */
+#define HD_CST_0 0x3c /* current status register chan 0 */
+#define HD_CST_1 0x5c /* current status register chan 1 */
+
+/*
+ * DMA controller registers.
+ */
+#define HD_PCR 0x08 /* DMA priority control register */
+#define HD_DMER 0x09 /* DMA master enable register */
+
+#define HD_DAR_0R 0x80 /* destination address chan 0rx */
+#define HD_DAR_0T 0xa0 /* destination address chan 0tx */
+#define HD_DAR_1R 0xc0 /* destination address chan 1rx */
+#define HD_DAR_1T 0xe0 /* destination address chan 1tx */
+#define HD_DARB_0R 0x82 /* destination address B chan 0rx */
+#define HD_DARB_0T 0xa2 /* destination address B chan 0tx */
+#define HD_DARB_1R 0xc2 /* destination address B chan 1rx */
+#define HD_DARB_1T 0xe2 /* destination address B chan 1tx */
+#define HD_SAR_0R 0x84 /* source address chan 0rx */
+#define HD_SAR_0T 0xa4 /* source address chan 0tx */
+#define HD_SAR_1R 0xc4 /* source address chan 1rx */
+#define HD_SAR_1T 0xe4 /* source address chan 1tx */
+#define HD_SARB_0R 0x86 /* source address B chan 0rx */
+#define HD_SARB_0T 0xa6 /* source address B chan 0tx */
+#define HD_SARB_1R 0xc6 /* source address B chan 1rx */
+#define HD_SARB_1T 0xe6 /* source address B chan 1tx */
+#define HD_CDA_0R 0x88 /* current descriptor address chan 0rx */
+#define HD_CDA_0T 0xa8 /* current descriptor address chan 0tx */
+#define HD_CDA_1R 0xc8 /* current descriptor address chan 1rx */
+#define HD_CDA_1T 0xe8 /* current descriptor address chan 1tx */
+#define HD_EDA_0R 0x8a /* error descriptor address chan 0rx */
+#define HD_EDA_0T 0xaa /* error descriptor address chan 0tx */
+#define HD_EDA_1R 0xca /* error descriptor address chan 1rx */
+#define HD_EDA_1T 0xea /* error descriptor address chan 1tx */
+#define HD_BFL_0R 0x8c /* receive buffer length chan 0rx */
+#define HD_BFL_1R 0xcc /* receive buffer length chan 1rx */
+#define HD_BCR_0R 0x8e /* byte count register chan 0rx */
+#define HD_BCR_0T 0xae /* byte count register chan 0tx */
+#define HD_BCR_1R 0xce /* byte count register chan 1rx */
+#define HD_BCR_1T 0xee /* byte count register chan 1tx */
+#define HD_DSR_0R 0x90 /* DMA status register chan 0rx */
+#define HD_DSR_0T 0xb0 /* DMA status register chan 0tx */
+#define HD_DSR_1R 0xd0 /* DMA status register chan 1rx */
+#define HD_DSR_1T 0xf0 /* DMA status register chan 1tx */
+#define HD_DMR_0R 0x91 /* DMA mode register chan 0rx */
+#define HD_DMR_0T 0xb1 /* DMA mode register chan 0tx */
+#define HD_DMR_1R 0xd1 /* DMA mode register chan 1rx */
+#define HD_DMR_1T 0xf1 /* DMA mode register chan 1tx */
+#define HD_FCT_0R 0x93 /* end-of-frame intr counter chan 0rx, ro */
+#define HD_FCT_0T 0xb3 /* end-of-frame intr counter chan 0tx, ro */
+#define HD_FCT_1R 0xd3 /* end-of-frame intr counter chan 1rx, ro */
+#define HD_FCT_1T 0xf3 /* end-of-frame intr counter chan 1tx, ro */
+#define HD_DIR_0R 0x94 /* DMA interrupt enable register chan 0rx */
+#define HD_DIR_0T 0xb4 /* DMA interrupt enable register chan 0tx */
+#define HD_DIR_1R 0xd4 /* DMA interrupt enable register chan 1rx */
+#define HD_DIR_1T 0xf4 /* DMA interrupt enable register chan 1tx */
+#define HD_DCR_0R 0x95 /* DMA command register chan 0rx, wo */
+#define HD_DCR_0T 0xb5 /* DMA command register chan 0tx, wo */
+#define HD_DCR_1R 0xd5 /* DMA command register chan 1rx, wo */
+#define HD_DCR_1T 0xf5 /* DMA command register chan 1tx, wo */
+
+/*
+ * Timer registers.
+ */
+#define HD_TCNT_0R 0x60 /* timer up counter chan 0rx */
+#define HD_TCNT_0T 0x68 /* timer up counter chan 0tx */
+#define HD_TCNT_1R 0x70 /* timer up counter chan 1rx */
+#define HD_TCNT_1T 0x78 /* timer up counter chan 1tx */
+#define HD_TCONR_0R 0x62 /* timer constant register chan 0rx, wo */
+#define HD_TCONR_0T 0x6a /* timer constant register chan 0tx, wo */
+#define HD_TCONR_1R 0x72 /* timer constant register chan 1rx, wo */
+#define HD_TCONR_1T 0x7a /* timer constant register chan 1tx, wo */
+#define HD_TCSR_0R 0x64 /* timer control/status register chan 0rx */
+#define HD_TCSR_0T 0x6c /* timer control/status register chan 0tx */
+#define HD_TCSR_1R 0x74 /* timer control/status register chan 1rx */
+#define HD_TCSR_1T 0x7c /* timer control/status register chan 1tx */
+#define HD_TEPR_0R 0x65 /* timer expand prescale register chan 0rx */
+#define HD_TEPR_0T 0x6d /* timer expand prescale register chan 0tx */
+#define HD_TEPR_1R 0x75 /* timer expand prescale register chan 1rx */
+#define HD_TEPR_1T 0x7d /* timer expand prescale register chan 1tx */
+
+/*
+ * Wait controller registers.
+ */
+#define HD_PABR0 0x02 /* physical address boundary register 0 */
+#define HD_PABR1 0x03 /* physical address boundary register 1 */
+#define HD_WCRL 0x04 /* wait control register L */
+#define HD_WCRM 0x05 /* wait control register M */
+#define HD_WCRH 0x06 /* wait control register H */
+
+/*
+ * Interrupt modified vector register (IMVR) bits.
+ */
+#define IMVR_CHAN1 040 /* channel 1 vector bit */
+#define IMVR_VECT_MASK 037 /* interrupt reason mask */
+
+#define IMVR_RX_RDY 004 /* receive buffer ready */
+#define IMVR_RX_INT 010 /* receive status */
+#define IMVR_RX_DMERR 024 /* receive DMA error */
+#define IMVR_RX_DMOK 026 /* receive DMA normal end */
+#define IMVR_RX_TIMER 034 /* timer 0/2 count match */
+
+#define IMVR_TX_RDY 006 /* transmit buffer ready */
+#define IMVR_TX_INT 012 /* transmit status */
+#define IMVR_TX_DMERR 030 /* transmit DMA error */
+#define IMVR_TX_DMOK 032 /* transmit DMA normal end */
+#define IMVR_TX_TIMER 036 /* timer 1/3 count match */
+
+/*
+ * Interrupt control register (ITCR) bits.
+ */
+#define ITCR_PRIO_DMAC 0x80 /* DMA priority higher than MSCI */
+#define ITCR_CYCLE_VOID 0x00 /* non-acknowledge cycle */
+#define ITCR_CYCLE_SINGLE 0x20 /* single acknowledge cycle */
+#define ITCR_CYCLE_DOUBLE 0x40 /* double acknowledge cycle */
+#define ITCR_VECT_MOD 0x10 /* interrupt modified vector flag */
+
+/*
+ * Interrupt status register 0 (ISR0) bits.
+ */
+#define ISR0_RX_RDY_0 0x01 /* channel 0 receiver ready */
+#define ISR0_TX_RDY_0 0x02 /* channel 0 transmitter ready */
+#define ISR0_RX_INT_0 0x04 /* channel 0 receiver status */
+#define ISR0_TX_INT_0 0x08 /* channel 0 transmitter status */
+#define ISR0_RX_RDY_1 0x10 /* channel 1 receiver ready */
+#define ISR0_TX_RDY_1 0x20 /* channel 1 transmitter ready */
+#define ISR0_RX_INT_1 0x40 /* channel 1 receiver status */
+#define ISR0_TX_INT_1 0x80 /* channel 1 transmitter status */
+
+/*
+ * Interrupt status register 1 (ISR1) bits.
+ */
+#define ISR1_RX_DMERR_0 0x01 /* channel 0 receive DMA error */
+#define ISR1_RX_DMOK_0 0x02 /* channel 0 receive DMA finished */
+#define ISR1_TX_DMERR_0 0x04 /* channel 0 transmit DMA error */
+#define ISR1_TX_DMOK_0 0x08 /* channel 0 transmit DMA finished */
+#define ISR1_RX_DMERR_1 0x10 /* channel 1 receive DMA error */
+#define ISR1_RX_DMOK_1 0x20 /* channel 1 receive DMA finished */
+#define ISR1_TX_DMERR_1 0x40 /* channel 1 transmit DMA error */
+#define ISR1_TX_DMOK_1 0x80 /* channel 1 transmit DMA finished */
+
+/*
+ * Interrupt status register 2 (ISR2) bits.
+ */
+#define ISR2_RX_TIMER_0 0x10 /* channel 0 receive timer */
+#define ISR2_TX_TIMER_0 0x20 /* channel 0 transmit timer */
+#define ISR2_RX_TIMER_1 0x40 /* channel 1 receive timer */
+#define ISR2_TX_TIMER_1 0x80 /* channel 1 transmit timer */
+
+/*
+ * Interrupt enable register 0 (IER0) bits.
+ */
+#define IER0_RX_RDYE_0 0x01 /* channel 0 receiver ready enable */
+#define IER0_TX_RDYE_0 0x02 /* channel 0 transmitter ready enable */
+#define IER0_RX_INTE_0 0x04 /* channel 0 receiver status enable */
+#define IER0_TX_INTE_0 0x08 /* channel 0 transmitter status enable */
+#define IER0_RX_RDYE_1 0x10 /* channel 1 receiver ready enable */
+#define IER0_TX_RDYE_1 0x20 /* channel 1 transmitter ready enable */
+#define IER0_RX_INTE_1 0x40 /* channel 1 receiver status enable */
+#define IER0_TX_INTE_1 0x80 /* channel 1 transmitter status enable */
+#define IER0_MASK_0 0x0f /* channel 0 bits */
+#define IER0_MASK_1 0xf0 /* channel 1 bits */
+
+/*
+ * Interrupt enable register 1 (IER1) bits.
+ */
+#define IER1_RX_DMERE_0 0x01 /* channel 0 receive DMA error enable */
+#define IER1_RX_DME_0 0x02 /* channel 0 receive DMA finished enable */
+#define IER1_TX_DMERE_0 0x04 /* channel 0 transmit DMA error enable */
+#define IER1_TX_DME_0 0x08 /* channel 0 transmit DMA finished enable */
+#define IER1_RX_DMERE_1 0x10 /* channel 1 receive DMA error enable */
+#define IER1_RX_DME_1 0x20 /* channel 1 receive DMA finished enable */
+#define IER1_TX_DMERE_1 0x40 /* channel 1 transmit DMA error enable */
+#define IER1_TX_DME_1 0x80 /* channel 1 transmit DMA finished enable */
+#define IER1_MASK_0 0x0f /* channel 0 bits */
+#define IER1_MASK_1 0xf0 /* channel 1 bits */
+
+/*
+ * Interrupt enable register 2 (IER2) bits.
+ */
+#define IER2_RX_TME_0 0x10 /* channel 0 receive timer enable */
+#define IER2_TX_TME_0 0x20 /* channel 0 transmit timer enable */
+#define IER2_RX_TME_1 0x40 /* channel 1 receive timer enable */
+#define IER2_TX_TME_1 0x80 /* channel 1 transmit timer enable */
+#define IER2_MASK_0 0x30 /* channel 0 bits */
+#define IER2_MASK_1 0xc0 /* channel 1 bits */
+
+/*
+ * Control register (CTL) bits.
+ */
+#define CTL_RTS_INV 0x01 /* RTS control bit (inverted) */
+#define CTL_SYNCLD 0x04 /* load SYN characters */
+#define CTL_BRK 0x08 /* async: send break */
+#define CTL_IDLE_MARK 0 /* HDLC: when idle, transmit mark */
+#define CTL_IDLE_PTRN 0x10 /* HDLC: when idle, transmit an idle pattern */
+#define CTL_UDRN_ABORT 0 /* HDLC: on underrun - abort */
+#define CTL_UDRN_FCS 0x20 /* HDLC: on underrun - send FCS/flag */
+
+/*
+ * Command register (CMD) values.
+ */
+#define CMD_TX_RESET 001 /* reset: disable, clear buffer/status/BRK */
+#define CMD_TX_ENABLE 002 /* transmitter enable */
+#define CMD_TX_DISABLE 003 /* transmitter disable */
+#define CMD_TX_CRC_INIT 004 /* initialize CRC calculator */
+#define CMD_TX_EOM_CHAR 006 /* set end-of-message char */
+#define CMD_TX_ABORT 007 /* abort transmission (HDLC mode) */
+#define CMD_TX_MPON 010 /* transmit char with MP bit on (async) */
+#define CMD_TX_CLEAR 011 /* clear the transmit buffer */
+
+#define CMD_RX_RESET 021 /* reset: disable, clear buffer/status */
+#define CMD_RX_ENABLE 022 /* receiver enable */
+#define CMD_RX_DISABLE 023 /* receiver disable */
+#define CMD_RX_CRC_INIT 024 /* initialize CRC calculator */
+#define CMD_RX_REJECT 025 /* reject current message (sync mode) */
+#define CMD_RX_SRCH_MP 026 /* skip all until the char witn MP bit on */
+
+#define CMD_NOOP 000 /* continue current operation */
+#define CMD_CHAN_RESET 041 /* init registers, disable/clear RX/TX */
+#define CMD_SEARCH_MODE 061 /* set the ADPLL to search mode */
+
+/*
+ * Status register 0 (ST0) bits.
+ */
+#define ST0_RX_RDY 0x01 /* receiver ready */
+#define ST0_TX_RDY 0x02 /* transmitter ready */
+#define ST0_RX_INT 0x40 /* receiver status interrupt */
+#define ST0_TX_INT 0x80 /* transmitter status interrupt */
+
+/*
+ * Status register 1 (ST1) bits.
+ */
+#define ST1_CDCD 0x04 /* carrier changed */
+#define ST1_CCTS 0x08 /* CTS changed */
+#define ST1_IDL 0x40 /* transmitter idle, ro */
+
+#define ST1_ASYNC_BRKE 0x01 /* break end detected */
+#define ST1_ASYNC_BRKD 0x02 /* break start detected */
+#define ST1_ASYNC_BITS "\20\1brke\2brkd\3cdcd\4ccts\7idl"
+
+#define ST1_HDLC_IDLD 0x01 /* idle sequence start detected */
+#define ST1_HDLC_ABTD 0x02 /* abort sequence start detected */
+#define ST1_HDLC_FLGD 0x10 /* flag detected */
+#define ST1_HDLC_UDRN 0x80 /* underrun detected */
+#define ST1_HDLC_BITS "\20\1idld\2abtd\3cdcd\4ccts\5flgd\7idl\10udrn"
+
+/*
+ * Status register 2 (ST2) bits.
+ */
+#define ST2_OVRN 0x08 /* overrun error detected */
+
+#define ST2_ASYNC_FRME 0x10 /* framing error detected */
+#define ST2_ASYNC_PE 0x20 /* parity error detected */
+#define ST2_ASYNC_PMP 0x40 /* parity/MP bit = 1 */
+#define ST2_ASYNC_BITS "\20\4ovrn\5frme\6pe\7pmp"
+
+#define ST2_HDLC_CRCE 0x04 /* CRC error detected */
+#define ST2_HDLC_RBIT 0x10 /* residual bit frame detected */
+#define ST2_HDLC_ABT 0x20 /* frame with abort end detected */
+#define ST2_HDLC_SHRT 0x40 /* short frame detected */
+#define ST2_HDLC_EOM 0x80 /* receive frame end detected */
+#define ST2_HDLC_BITS "\20\3crce\4ovrn\5rbit\6abt\7shrt\10eom"
+
+/*
+ * Status register 3 (ST3) bits.
+ */
+#define ST3_RX_ENABLED 0x01 /* receiver is enabled */
+#define ST3_TX_ENABLED 0x02 /* transmitter is enabled */
+#define ST3_DCD_INV 0x04 /* DCD input line inverted */
+#define ST3_CTS_INV 0x08 /* CTS input line inverted */
+#define ST3_ASYNC_BITS "\20\1rx\2tx\3nodcd\4nocts"
+
+#define ST3_HDLC_SEARCH 0x10 /* ADPLL search mode */
+#define ST3_HDLC_TX 0x20 /* channel is transmitting data */
+#define ST3_HDLC_BITS "\20\1rx\2tx\3nodcd\4nocts\5search\6txact"
+
+/*
+ * Frame status register (FST) bits, HDLC mode only.
+ */
+#define FST_CRCE 0x04 /* CRC error detected */
+#define FST_OVRN 0x08 /* overrun error detected */
+#define FST_RBIT 0x10 /* residual bit frame detected */
+#define FST_ABT 0x20 /* frame with abort end detected */
+#define FST_SHRT 0x40 /* short frame detected */
+#define FST_EOM 0x80 /* frame end flag */
+
+#define FST_EOT 0x01 /* end of transfer, transmit only */
+
+/*
+ * Interrupt enable register 0 (IE0) bits.
+ */
+#define IE0_RX_RDYE 0x01 /* receiver ready interrupt enable */
+#define IE0_TX_RDYE 0x02 /* transmitter ready interrupt enable */
+#define IE0_RX_INTE 0x40 /* receiver status interrupt enable */
+#define IE0_TX_INTE 0x80 /* transmitter status interrupt enable */
+
+/*
+ * Interrupt enable register 1 (IE1) bits.
+ */
+#define IE1_CDCDE 0x04 /* carrier changed */
+#define IE1_CCTSE 0x08 /* CTS changed */
+#define IE1_IDLE 0x40 /* transmitter idle, ro */
+
+#define IE1_ASYNC_BRKEE 0x01 /* break end detected */
+#define IE1_ASYNC_BRKDE 0x02 /* break start detected */
+
+#define IE1_HDLC_IDLDE 0x01 /* idle sequence start detected */
+#define IE1_HDLC_ABTDE 0x02 /* abort sequence start detected */
+#define IE1_HDLC_FLGDE 0x10 /* flag detected */
+#define IE1_HDLC_UDRNE 0x80 /* underrun detected */
+
+/*
+ * Interrupt enable register 2 (IE2) bits.
+ */
+#define IE2_OVRNE 0x08 /* overrun error detected */
+
+#define IE2_ASYNC_FRMEE 0x10 /* framing error detected */
+#define IE2_ASYNC_PEE 0x20 /* parity error detected */
+#define IE2_ASYNC_PMPE 0x40 /* parity/MP bit = 1 */
+
+#define IE2_HDLC_CRCEE 0x04 /* CRC error detected */
+#define IE2_HDLC_RBITE 0x10 /* residual bit frame detected */
+#define IE2_HDLC_ABTE 0x20 /* frame with abort end detected */
+#define IE2_HDLC_SHRTE 0x40 /* short frame detected */
+#define IE2_HDLC_EOME 0x80 /* receive frame end detected */
+
+/*
+ * Frame interrupt enable register (FIE) bits, HDLC mode only.
+ */
+#define FIE_EOMFE 0x80 /* receive frame end detected */
+
+/*
+ * Current status register (CST0,CST1) bits.
+ * For other bits, see ST2.
+ */
+#define CST0_CDE 0x0001 /* data present on top of FIFO */
+#define CST1_CDE 0x0100 /* data present on second stage of FIFO */
+
+/*
+ * Receive/transmit clock source register (RXS/TXS) bits.
+ */
+#define CLK_MASK 0x70 /* RXC/TXC clock input mask */
+#define CLK_LINE 0x00 /* RXC/TXC line input */
+#define CLK_INT 0x40 /* internal baud rate generator */
+
+#define CLK_RXS_LINE_NS 0x20 /* RXC line with noise suppression */
+#define CLK_RXS_DPLL_INT 0x60 /* ADPLL based on internal BRG */
+#define CLK_RXS_DPLL_LINE 0x70 /* ADPLL based on RXC line */
+
+#define CLK_TXS_RECV 0x60 /* receive clock */
+
+/*
+ * DMA status register (DSR) bits.
+ */
+#define DSR_DMA_DISABLE 0x00 /* disable DMA channel */
+#define DSR_DMA_ENABLE 0x02 /* enable DMA channel */
+#define DSR_DMA_CONTINUE 0x01 /* do not enable/disable DMA channel */
+#define DSR_CHAIN_COF 0x10 /* counter overflow */
+#define DSR_CHAIN_BOF 0x20 /* buffer overflow/underflow */
+#define DSR_CHAIN_EOM 0x40 /* frame transfer completed */
+#define DSR_EOT 0x80 /* transfer completed */
+#define DSR_BITS "\20\1cont\2enab\5cof\6bof\7eom\10eot"
+
+/*
+ * DMA mode register (DMR) bits.
+ */
+#define DMR_CHAIN_CNTE 0x02 /* enable frame interrupt counter (FCT) */
+#define DMR_CHAIN_NF 0x04 /* multi-frame block chain */
+#define DMR_TMOD 0x10 /* chained-block transfer mode */
+
+/*
+ * DMA interrupt enable register (DIR) bits.
+ */
+#define DIR_CHAIN_COFE 0x10 /* counter overflow */
+#define DIR_CHAIN_BOFE 0x20 /* buffer overflow/underflow */
+#define DIR_CHAIN_EOME 0x40 /* frame transfer completed */
+#define DIR_EOTE 0x80 /* transfer completed */
+
+/*
+ * DMA command register (DCR) values.
+ */
+#define DCR_ABORT 1 /* software abort: initialize DMA channel */
+#define DCR_CLEAR 2 /* clear FCT and EOM bit of DSR */
+
+/*
+ * DMA master enable register (DME) bits.
+ */
+#define DME_ENABLE 0x80 /* enable DMA master operation */
+
+/*
+ * Timer control/status register (TCSR) bits.
+ */
+#define TCSR_ENABLE 0x10 /* timer starts incrementing */
+#define TCSR_INTR 0x40 /* timer interrupt enable */
+#define TCSR_MATCH 0x80 /* TCNT and TCONR are equal */
+
+/*
+ * Timer expand prescale register (TEPR) values.
+ */
+#define TEPR_1 0 /* sysclk/8 */
+#define TEPR_2 1 /* sysclk/8/2 */
+#define TEPR_4 2 /* sysclk/8/4 */
+#define TEPR_8 3 /* sysclk/8/8 */
+#define TEPR_16 4 /* sysclk/8/16 */
+#define TEPR_32 5 /* sysclk/8/32 */
+#define TEPR_64 6 /* sysclk/8/64 */
+#define TEPR_128 7 /* sysclk/8/128 */
diff --git a/sys/dev/ctau/if_ct.c b/sys/dev/ctau/if_ct.c
new file mode 100644
index 000000000000..b0c82c820576
--- /dev/null
+++ b/sys/dev/ctau/if_ct.c
@@ -0,0 +1,2737 @@
+/*
+ * Cronyx-Tau adapter driver for FreeBSD.
+ * Supports PPP/HDLC and Cisco/HDLC protocol in synchronous mode,
+ * and asyncronous channels with full modem control.
+ * Keepalive protocol implemented in both Cisco and PPP modes.
+ *
+ * Copyright (C) 1994-2002 Cronyx Engineering.
+ * Author: Serge Vakulenko, <vak@cronyx.ru>
+ *
+ * Copyright (C) 1999-2004 Cronyx Engineering.
+ * Author: Roman Kurakin, <rik@cronyx.ru>
+ *
+ * This software is distributed with NO WARRANTIES, not even the implied
+ * warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Authors grant any other persons or organisations a permission to use,
+ * modify and redistribute this software in source and binary forms,
+ * as long as this message is kept with the software, all derivative
+ * works or modified versions.
+ *
+ * Cronyx Id: if_ct.c,v 1.1.2.20.2.1 2004/02/13 14:48:24 rik Exp $
+ */
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+
+#if __FreeBSD_version >= 500000
+# define NCT 1
+#else
+# include "ct.h"
+#endif
+
+#if NCT > 0
+#include <sys/proc.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/mbuf.h>
+#include <sys/sockio.h>
+#include <sys/malloc.h>
+#include <sys/socket.h>
+#include <sys/conf.h>
+#include <sys/errno.h>
+#include <sys/tty.h>
+#if __FreeBSD_version >= 400000
+# include <sys/bus.h>
+# include <machine/bus.h>
+# include <sys/rman.h>
+# include <isa/isavar.h>
+#endif
+#include <sys/interrupt.h>
+#include <vm/vm.h>
+#include <vm/pmap.h>
+#include <net/if.h>
+#include <machine/cpufunc.h>
+#include <machine/cserial.h>
+#include <machine/clock.h>
+#if __FreeBSD_version < 500000
+#include <i386/isa/isa_device.h>
+#endif
+#if __FreeBSD_version >= 400000
+#include <machine/resource.h>
+# if __FreeBSD_version <= 501000
+# include <i386/isa/intr_machdep.h>
+# endif
+#endif
+#if __FreeBSD_version >= 500000
+#include <dev/cx/machdep.h>
+#include <dev/ctau/ctddk.h>
+#include <dev/cx/cronyxfw.h>
+#else
+#include <i386/isa/cronyx/machdep.h>
+#include <i386/isa/cronyx/ctddk.h>
+#include <i386/isa/cronyx/cronyxfw.h>
+#endif
+#include "opt_ng_cronyx.h"
+#ifdef NETGRAPH_CRONYX
+# include "opt_netgraph.h"
+# include <netgraph/ng_message.h>
+# include <netgraph/netgraph.h>
+#if __FreeBSD_version >= 500000
+# include <dev/ctau/ng_ct.h>
+#else
+# include <netgraph/ng_ct.h>
+#endif
+#else
+# include <net/if_types.h>
+# if __FreeBSD_version < 500000
+# include "sppp.h"
+# if NSPPP <= 0
+# error The device ct requires sppp or netgraph.
+# endif
+# endif
+# include <net/if_sppp.h>
+# define PP_CISCO IFF_LINK2
+#if __FreeBSD_version < 400000
+# include <bpfilter.h>
+# if NBPFILTER > 0
+# include <net/bpf.h>
+# endif
+#else
+# if __FreeBSD_version < 500000
+# include <bpf.h>
+# endif
+# include <net/bpf.h>
+# define NBPFILTER NBPF
+#endif
+#endif
+
+#define CT_DEBUG(d,s) ({if (d->chan->debug) {\
+ printf ("%s: ", d->name); printf s;}})
+#define CT_DEBUG2(d,s) ({if (d->chan->debug>1) {\
+ printf ("%s: ", d->name); printf s;}})
+#define CDEV_MAJOR 99
+
+#if __FreeBSD_version >= 400000
+static void ct_identify __P((driver_t *, device_t));
+static int ct_probe __P((device_t));
+static int ct_attach __P((device_t));
+static int ct_detach __P((device_t));
+
+static device_method_t ct_isa_methods [] = {
+ DEVMETHOD(device_identify, ct_identify),
+ DEVMETHOD(device_probe, ct_probe),
+ DEVMETHOD(device_attach, ct_attach),
+ DEVMETHOD(device_detach, ct_detach),
+ {0, 0}
+};
+
+typedef struct _bdrv_t {
+ ct_board_t *board;
+ struct resource *base_res;
+ struct resource *drq_res;
+ struct resource *irq_res;
+ int base_rid;
+ int drq_rid;
+ int irq_rid;
+ void *intrhand;
+} bdrv_t;
+
+static driver_t ct_isa_driver = {
+ "ct",
+ ct_isa_methods,
+ sizeof (bdrv_t),
+};
+
+static devclass_t ct_devclass;
+#endif
+
+typedef struct _drv_t {
+ char name [8];
+ ct_chan_t *chan;
+ ct_board_t *board;
+ ct_buf_t buf;
+ int running;
+#ifdef NETGRAPH
+ char nodename [NG_NODELEN+1];
+ hook_p hook;
+ hook_p debug_hook;
+ node_p node;
+ struct ifqueue queue;
+ struct ifqueue hi_queue;
+ short timeout;
+ struct callout_handle timeout_handle;
+#else
+ struct sppp pp;
+#endif
+#if __FreeBSD_version >= 400000
+ dev_t devt;
+#endif
+} drv_t;
+
+static void ct_receive (ct_chan_t *c, char *data, int len);
+static void ct_transmit (ct_chan_t *c, void *attachment, int len);
+static void ct_error (ct_chan_t *c, int data);
+static void ct_up (drv_t *d);
+static void ct_start (drv_t *d);
+static void ct_down (drv_t *d);
+static void ct_watchdog (drv_t *d);
+#ifdef NETGRAPH
+extern struct ng_type typestruct;
+#else
+static void ct_ifstart (struct ifnet *ifp);
+static void ct_tlf (struct sppp *sp);
+static void ct_tls (struct sppp *sp);
+static void ct_ifwatchdog (struct ifnet *ifp);
+static int ct_sioctl (struct ifnet *ifp, u_long cmd, caddr_t data);
+static void ct_initialize (void *softc);
+#endif
+
+static ct_board_t *adapter [NCT];
+static drv_t *channel [NCT*NCHAN];
+static struct callout_handle led_timo [NCT];
+static struct callout_handle timeout_handle;
+
+/*
+ * Print the mbuf chain, for debug purposes only.
+ */
+static void printmbuf (struct mbuf *m)
+{
+ printf ("mbuf:");
+ for (; m; m=m->m_next) {
+ if (m->m_flags & M_PKTHDR)
+ printf (" HDR %d:", m->m_pkthdr.len);
+ if (m->m_flags & M_EXT)
+ printf (" EXT:");
+ printf (" %d", m->m_len);
+ }
+ printf ("\n");
+}
+
+/*
+ * Make an mbuf from data.
+ */
+static struct mbuf *makembuf (void *buf, u_int len)
+{
+ struct mbuf *m;
+
+ MGETHDR (m, M_DONTWAIT, MT_DATA);
+ if (! m)
+ return 0;
+ MCLGET (m, M_DONTWAIT);
+ if (! (m->m_flags & M_EXT)) {
+ m_freem (m);
+ return 0;
+ }
+ m->m_pkthdr.len = m->m_len = len;
+ bcopy (buf, mtod (m, caddr_t), len);
+ return m;
+}
+
+static void ct_timeout (void *arg)
+{
+ drv_t *d;
+ int s, i;
+
+ for (i=0; i<NCT*NCHAN; ++i) {
+ d = channel[i];
+ if (! d)
+ continue;
+ if (d->chan->mode != M_G703)
+ continue;
+ s = splimp ();
+ ct_g703_timer (d->chan);
+ splx (s);
+ }
+ timeout_handle = timeout (ct_timeout, 0, hz);
+}
+
+static void ct_led_off (void *arg)
+{
+ ct_board_t *b = arg;
+ int s = splimp ();
+
+ ct_led (b, 0);
+ led_timo[b->num].callout = 0;
+ splx (s);
+}
+
+/*
+ * Activate interupt handler from DDK.
+ */
+#if __FreeBSD_version >= 400000
+static void ct_intr (void *arg)
+{
+ bdrv_t *bd = arg;
+ ct_board_t *b = bd->board;
+#else
+static void ct_intr (int bnum)
+{
+ ct_board_t *b = adapter [bnum];
+#endif
+ int s = splimp ();
+
+ /* Turn LED on. */
+ ct_led (b, 1);
+
+ ct_int_handler (b);
+
+ /* Turn LED off 50 msec later. */
+ if (! led_timo[b->num].callout)
+ led_timo[b->num] = timeout (ct_led_off, b, hz/20);
+ splx (s);
+}
+
+static int probe_irq (ct_board_t *b, int irq)
+{
+ int mask, busy, cnt;
+
+ /* Clear pending irq, if any. */
+ ct_probe_irq (b, -irq);
+ DELAY (100);
+ for (cnt=0; cnt<5; ++cnt) {
+ /* Get the mask of pending irqs, assuming they are busy.
+ * Activate the adapter on given irq. */
+ busy = ct_probe_irq (b, irq);
+ DELAY (1000);
+
+ /* Get the mask of active irqs.
+ * Deactivate our irq. */
+ mask = ct_probe_irq (b, -irq);
+ DELAY (100);
+ if ((mask & ~busy) == 1 << irq) {
+ ct_probe_irq (b, 0);
+ /* printf ("ct%d: irq %d ok, mask=0x%04x, busy=0x%04x\n",
+ b->num, irq, mask, busy); */
+ return 1;
+ }
+ }
+ /* printf ("ctx%d: irq %d not functional, mask=0x%04x, busy=0x%04x\n",
+ b->num, irq, mask, busy); */
+ ct_probe_irq (b, 0);
+ return 0;
+}
+
+static short porttab [] = {
+ 0x200, 0x220, 0x240, 0x260, 0x280, 0x2a0, 0x2c0, 0x2e0,
+ 0x300, 0x320, 0x340, 0x360, 0x380, 0x3a0, 0x3c0, 0x3e0, 0
+ };
+static char dmatab [] = { 7, 6, 5, 0 };
+static char irqtab [] = { 5, 10, 11, 7, 3, 15, 12, 0 };
+
+#if __FreeBSD_version >= 400000
+static int ct_is_free_res (device_t dev, int rid, int type, u_long start,
+ u_long end, u_long count)
+{
+ struct resource *res;
+
+ if (!(res = bus_alloc_resource (dev, type, &rid, start, end, count,
+ RF_ALLOCATED)))
+ return 0;
+
+ bus_release_resource (dev, type, rid, res);
+
+ return 1;
+}
+
+static void ct_identify (driver_t *driver, device_t dev)
+{
+ u_long iobase, rescount;
+ int devcount;
+ device_t *devices;
+ device_t child;
+ devclass_t my_devclass;
+ int i, k;
+
+ if ((my_devclass = devclass_find ("ct")) == NULL)
+ return;
+
+ devclass_get_devices (my_devclass, &devices, &devcount);
+
+ if (devcount == 0) {
+ /* We should find all devices by our self. We could alter other
+ * devices, but we don't have a choise
+ */
+ for (i = 0; (iobase = porttab [i]) != 0; i++) {
+ if (!ct_is_free_res (dev, 1, SYS_RES_IOPORT,
+ iobase, iobase + NPORT, NPORT))
+ continue;
+ if (ct_probe_board (iobase, -1, -1) == 0)
+ continue;
+
+ devcount++;
+ child = BUS_ADD_CHILD (dev, ISA_ORDER_SPECULATIVE, "ct",
+ -1);
+
+ if (child == NULL)
+ return;
+
+ device_set_desc_copy (child, "Cronyx Tau-ISA");
+ device_set_driver (child, driver);
+ bus_set_resource (child, SYS_RES_IOPORT, 0,
+ iobase, NPORT);
+
+ if (devcount >= NCT)
+ break;
+ }
+ } else {
+ static short porttab [] = {
+ 0x200, 0x220, 0x240, 0x260, 0x280, 0x2a0, 0x2c0, 0x2e0,
+ 0x300, 0x320, 0x340, 0x360, 0x380, 0x3a0, 0x3c0, 0x3e0, 0
+ };
+ /* Lets check user choise.
+ */
+ for (k = 0; k < devcount; k++) {
+ if (bus_get_resource (devices[k], SYS_RES_IOPORT, 0,
+ &iobase, &rescount) != 0)
+ continue;
+
+ for (i = 0; porttab [i] != 0; i++) {
+ if (porttab [i] != iobase)
+ continue;
+
+ if (!ct_is_free_res (devices[k], 1, SYS_RES_IOPORT,
+ iobase, iobase + NPORT, NPORT))
+ continue;
+
+ if (ct_probe_board (iobase, -1, -1) == 0)
+ continue;
+ porttab [i] = -1;
+ device_set_desc_copy (devices[k], "Cronyx Tau-ISA");
+ break;
+ }
+ if (porttab [i] == 0) {
+ device_delete_child (
+ device_get_parent (devices[k]),
+ devices [k]);
+ devices[k] = 0;
+ continue;
+ }
+ }
+ for (k = 0; k < devcount; k++) {
+ if (devices[k] == 0)
+ continue;
+ if (bus_get_resource (devices[k], SYS_RES_IOPORT, 0,
+ &iobase, &rescount) == 0)
+ continue;
+ for (i = 0; (iobase = porttab [i]) != 0; i++) {
+ if (porttab [i] == -1)
+ continue;
+ if (!ct_is_free_res (devices[k], 1, SYS_RES_IOPORT,
+ iobase, iobase + NPORT, NPORT))
+ continue;
+ if (ct_probe_board (iobase, -1, -1) == 0)
+ continue;
+
+ bus_set_resource (devices[k], SYS_RES_IOPORT, 0,
+ iobase, NPORT);
+ porttab [i] = -1;
+ device_set_desc_copy (devices[k], "Cronyx Tau-ISA");
+ break;
+ }
+ if (porttab [i] == 0) {
+ device_delete_child (
+ device_get_parent (devices[k]),
+ devices [k]);
+ }
+ }
+ free (devices, M_TEMP);
+ }
+
+ return;
+}
+
+static int ct_probe (device_t dev)
+{
+ int unit = device_get_unit (dev);
+ u_long iobase, rescount;
+
+ if (!device_get_desc (dev) ||
+ strcmp (device_get_desc (dev), "Cronyx Tau-ISA"))
+ return ENXIO;
+
+/* KASSERT ((bd != NULL), ("ct%d: NULL device softc\n", unit));*/
+ if (bus_get_resource (dev, SYS_RES_IOPORT, 0, &iobase, &rescount) != 0) {
+ printf ("ct%d: Couldn't get IOPORT\n", unit);
+ return ENXIO;
+ }
+
+ if (!ct_is_free_res (dev, 1, SYS_RES_IOPORT,
+ iobase, iobase + NPORT, NPORT)) {
+ printf ("ct%d: Resource IOPORT isn't free\n", unit);
+ return ENXIO;
+ }
+
+ if (!ct_probe_board (iobase, -1, -1)) {
+ printf ("ct%d: probing for Tau-ISA at %lx faild\n", unit, iobase);
+ return ENXIO;
+ }
+
+ return 0;
+}
+#else /* __FreeBSD_version < 400000 */
+static int ct_probe (struct isa_device *id)
+{
+ int unit = id->id_unit;
+ int iobase;
+ ct_board_t *b;
+ int i;
+
+ iobase = id->id_iobase;
+ if (iobase < 0) {
+ /* Autodetect the adapter. */
+
+ for (i=0; ; i++) {
+ if (! porttab[i]) {
+ iobase = -1;
+ return 0;
+ }
+ iobase = porttab[i];
+ if (unit > 0 && adapter[0] && adapter[0]->port == iobase)
+ continue;
+ if (unit > 1 && adapter[1] && adapter[1]->port == iobase)
+ continue;
+ if (! haveseen_isadev (id, CC_IOADDR | CC_QUIET) &&
+ ct_probe_board (iobase, -1, -1))
+ break;
+ }
+ } else if (! ct_probe_board (iobase, -1, -1))
+ return 0;
+
+ if (id->id_drq < 0) {
+ /* Find available 16-bit DRQ. */
+
+ for (i=0; ; ++i) {
+ if (! dmatab[i]) {
+ printf ("ct%d: no available drq found\n",
+ unit);
+ id->id_drq = -1;
+ return 0;
+ }
+ id->id_drq = dmatab[i];
+ if (! haveseen_isadev (id, CC_DRQ | CC_QUIET)
+ && !isa_dma_acquire (id->id_drq))
+ break;
+ }
+ }
+
+ b = malloc (sizeof (ct_board_t), M_DEVBUF, M_WAITOK);
+ if (!b) {
+ printf ("ct:%d: Couldn't allocate memory\n", unit);
+ return (ENXIO);
+ }
+ adapter[unit] = b;
+ bzero (b, sizeof(ct_board_t));
+
+ if (! ct_open_board (b, unit, iobase,
+ id->id_irq ? ffs (id->id_irq) - 1 : -1, id->id_drq)) {
+ printf ("ct%d: error loading firmware\n", unit);
+ adapter [unit] = 0;
+ free (b, M_DEVBUF);
+ isa_dma_release (id->id_drq);
+ return 0;
+ }
+
+ if (id->id_irq) {
+ if (! probe_irq (b, ffs (id->id_irq) - 1))
+ printf ("ct%d: irq %d not functional\n",
+ unit, ffs (id->id_irq) - 1);
+ } else {
+ /* Find available IRQ. */
+
+ for (i=0; ; ++i) {
+ if (! irqtab[i]) {
+ printf ("ct%d: no available irq found\n",
+ unit);
+ id->id_irq = -1;
+ isa_dma_release (id->id_drq);
+ adapter [unit] = 0;
+ free (b, M_DEVBUF);
+ return 0;
+ }
+ id->id_irq = 1 << irqtab[i];
+ if (haveseen_isadev (id, CC_IRQ | CC_QUIET))
+ continue;
+#ifdef KLD_MODULE
+ if (register_intr (irqtab[i], 0, 0, (inthand2_t*)
+ ct_intr, &net_imask, unit) != 0)
+ continue;
+ unregister_intr (irqtab[i], (inthand2_t*) ct_intr);
+#endif
+ if (probe_irq (b, irqtab[i]))
+ break;
+ }
+ }
+ ct_init_board (b, b->num, b->port, ffs (id->id_irq) - 1, b->dma,
+ b->type, b->osc);
+ ct_setup_board (b, 0, 0, 0);
+
+ return 1;
+}
+#endif /* __FreeBSD_version < 400000 */
+
+extern struct cdevsw ct_cdevsw;
+/*
+ * The adapter is present, initialize the driver structures.
+ */
+#if __FreeBSD_version < 400000
+static int ct_attach (struct isa_device *id)
+{
+#else
+static int ct_attach (device_t dev)
+{
+ bdrv_t *bd = device_get_softc (dev);
+ u_long iobase, drq, irq, rescount;
+ int unit = device_get_unit (dev);
+ int i;
+ int s;
+#endif
+ ct_board_t *b;
+ ct_chan_t *c;
+ drv_t *d;
+
+#if __FreeBSD_version >= 400000
+ KASSERT ((bd != NULL), ("ct%d: NULL device softc\n", unit));
+
+ bus_get_resource (dev, SYS_RES_IOPORT, 0, &iobase, &rescount);
+ bd->base_rid = 0;
+ bd->base_res = bus_alloc_resource (dev, SYS_RES_IOPORT, &bd->base_rid,
+ iobase, iobase + NPORT, NPORT, RF_ACTIVE);
+ if (! bd->base_res) {
+ printf ("ct%d: cannot alloc base address\n", unit);
+ return ENXIO;
+ }
+
+ if (bus_get_resource (dev, SYS_RES_DRQ, 0, &drq, &rescount) != 0) {
+ for (i = 0; (drq = dmatab [i]) != 0; i++) {
+ if (!ct_is_free_res (dev, 1, SYS_RES_DRQ,
+ drq, drq + 1, 1))
+ continue;
+ bus_set_resource (dev, SYS_RES_DRQ, 0, drq, 1);
+ break;
+ }
+
+ if (dmatab[i] == 0) {
+ bus_release_resource (dev, SYS_RES_IOPORT, bd->base_rid,
+ bd->base_res);
+ printf ("ct%d: Couldn't get DRQ\n", unit);
+ return ENXIO;
+ }
+ }
+
+ bd->drq_rid = 0;
+ bd->drq_res = bus_alloc_resource (dev, SYS_RES_DRQ, &bd->drq_rid,
+ drq, drq + 1, 1, RF_ACTIVE);
+ if (! bd->drq_res) {
+ printf ("ct%d: cannot allocate drq\n", unit);
+ bus_release_resource (dev, SYS_RES_IOPORT, bd->base_rid,
+ bd->base_res);
+ return ENXIO;
+ }
+
+ if (bus_get_resource (dev, SYS_RES_IRQ, 0, &irq, &rescount) != 0) {
+ for (i = 0; (irq = irqtab [i]) != 0; i++) {
+ if (!ct_is_free_res (dev, 1, SYS_RES_IRQ,
+ irq, irq + 1, 1))
+ continue;
+ bus_set_resource (dev, SYS_RES_IRQ, 0, irq, 1);
+ break;
+ }
+
+ if (irqtab[i] == 0) {
+ bus_release_resource (dev, SYS_RES_DRQ, bd->drq_rid,
+ bd->drq_res);
+ bus_release_resource (dev, SYS_RES_IOPORT, bd->base_rid,
+ bd->base_res);
+ printf ("ct%d: Couldn't get IRQ\n", unit);
+ return ENXIO;
+ }
+ }
+
+ bd->irq_rid = 0;
+ bd->irq_res = bus_alloc_resource (dev, SYS_RES_IRQ, &bd->irq_rid,
+ irq, irq + 1, 1, RF_ACTIVE);
+ if (! bd->irq_res) {
+ printf ("ct%d: Couldn't allocate irq\n", unit);
+ bus_release_resource (dev, SYS_RES_DRQ, bd->drq_rid,
+ bd->drq_res);
+ bus_release_resource (dev, SYS_RES_IOPORT, bd->base_rid,
+ bd->base_res);
+ return ENXIO;
+ }
+
+ b = malloc (sizeof (ct_board_t), M_DEVBUF, M_WAITOK);
+ if (!b) {
+ printf ("ct:%d: Couldn't allocate memory\n", unit);
+ return (ENXIO);
+ }
+ adapter[unit] = b;
+ bzero (b, sizeof(ct_board_t));
+
+ if (! ct_open_board (b, unit, iobase, irq, drq)) {
+ printf ("ct%d: error loading firmware\n", unit);
+ free (b, M_DEVBUF);
+ bus_release_resource (dev, SYS_RES_IRQ, bd->irq_rid,
+ bd->irq_res);
+ bus_release_resource (dev, SYS_RES_DRQ, bd->drq_rid,
+ bd->drq_res);
+ bus_release_resource (dev, SYS_RES_IOPORT, bd->base_rid,
+ bd->base_res);
+ return ENXIO;
+ }
+
+ bd->board = b;
+
+ if (! probe_irq (b, irq)) {
+ printf ("ct%d: irq %ld not functional\n", unit, irq);
+ bd->board = 0;
+ adapter [unit] = 0;
+ free (b, M_DEVBUF);
+ bus_release_resource (dev, SYS_RES_IRQ, bd->irq_rid,
+ bd->irq_res);
+ bus_release_resource (dev, SYS_RES_DRQ, bd->drq_rid,
+ bd->drq_res);
+ bus_release_resource (dev, SYS_RES_IOPORT, bd->base_rid,
+ bd->base_res);
+ return ENXIO;
+ }
+
+ s = splimp ();
+ if (bus_setup_intr (dev, bd->irq_res, INTR_TYPE_NET, ct_intr, bd,
+ &bd->intrhand)) {
+ printf ("ct%d: Can't setup irq %ld\n", unit, irq);
+ bd->board = 0;
+ adapter [unit] = 0;
+ free (b, M_DEVBUF);
+ bus_release_resource (dev, SYS_RES_IRQ, bd->irq_rid,
+ bd->irq_res);
+ bus_release_resource (dev, SYS_RES_DRQ, bd->drq_rid,
+ bd->drq_res);
+ bus_release_resource (dev, SYS_RES_IOPORT, bd->base_rid,
+ bd->base_res);
+ splx (s);
+ return ENXIO;
+ }
+
+ ct_init_board (b, b->num, b->port, irq, drq, b->type, b->osc);
+ ct_setup_board (b, 0, 0, 0);
+#else
+ b = adapter [id->id_unit];
+#endif
+
+ printf ("ct%d: <Cronyx-%s>, clock %s MHz\n", b->num, b->name,
+ b->osc == 20000000 ? "20" : "16.384");
+#if __FreeBSD_version < 400000
+ id->id_ointr = ct_intr;
+#endif
+
+ for (c=b->chan; c<b->chan+NCHAN; ++c) {
+ d = contigmalloc (sizeof(drv_t), M_DEVBUF, M_WAITOK,
+ 0x100000, 0x1000000, 16, 0);
+ channel [b->num*NCHAN + c->num] = d;
+ bzero (d, sizeof(drv_t));
+ sprintf (d->name, "ct%d.%d", b->num, c->num);
+ d->board = b;
+ d->chan = c;
+ c->sys = d;
+
+#ifdef NETGRAPH
+ if (ng_make_node_common (&typestruct, &d->node) != 0) {
+ printf ("%s: cannot make common node\n", d->name);
+ channel [b->num*NCHAN + c->num] = 0;
+ c->sys = 0;
+#if __FreeBSD_version < 400000
+ free (d, M_DEVBUF);
+#else
+ contigfree (d, sizeof (*d), M_DEVBUF);
+#endif
+ continue;
+ }
+#if __FreeBSD_version >= 500000
+ NG_NODE_SET_PRIVATE (d->node, d);
+#else
+ d->node->private = d;
+#endif
+ sprintf (d->nodename, "%s%d", NG_CT_NODE_TYPE,
+ c->board->num*NCHAN + c->num);
+ if (ng_name_node (d->node, d->nodename)) {
+ printf ("%s: cannot name node\n", d->nodename);
+#if __FreeBSD_version >= 500000
+ NG_NODE_UNREF (d->node);
+#else
+ ng_rmnode (d->node);
+ ng_unref (d->node);
+#endif
+ channel [b->num*NCHAN + c->num] = 0;
+ c->sys = 0;
+#if __FreeBSD_version < 400000
+ free (d, M_DEVBUF);
+#else
+ contigfree (d, sizeof (*d), M_DEVBUF);
+#endif
+ continue;
+ }
+ d->queue.ifq_maxlen = IFQ_MAXLEN;
+ d->hi_queue.ifq_maxlen = IFQ_MAXLEN;
+#if __FreeBSD_version >= 500000
+ mtx_init (&d->queue.ifq_mtx, "ct_queue", NULL, MTX_DEF);
+ mtx_init (&d->hi_queue.ifq_mtx, "ct_queue_hi", NULL, MTX_DEF);
+#endif
+#else /*NETGRAPH*/
+ d->pp.pp_if.if_softc = d;
+#if __FreeBSD_version > 501000
+ if_initname (&d->pp.pp_if, "ct", b->num * NCHAN + c->num);
+#else
+ d->pp.pp_if.if_unit = b->num * NCHAN + c->num;
+ d->pp.pp_if.if_name = "ct";
+#endif
+ d->pp.pp_if.if_mtu = PP_MTU;
+ d->pp.pp_if.if_flags = IFF_POINTOPOINT | IFF_MULTICAST;
+ d->pp.pp_if.if_ioctl = ct_sioctl;
+ d->pp.pp_if.if_start = ct_ifstart;
+ d->pp.pp_if.if_watchdog = ct_ifwatchdog;
+ d->pp.pp_if.if_init = ct_initialize;
+ sppp_attach (&d->pp.pp_if);
+ if_attach (&d->pp.pp_if);
+ d->pp.pp_tlf = ct_tlf;
+ d->pp.pp_tls = ct_tls;
+#if __FreeBSD_version >= 400000 || NBPFILTER > 0
+ /* If BPF is in the kernel, call the attach for it.
+ * Header size is 4 bytes. */
+ bpfattach (&d->pp.pp_if, DLT_PPP, 4);
+#endif
+#endif /*NETGRAPH*/
+ ct_start_chan (c, &d->buf, vtophys (&d->buf));
+ ct_register_receive (c, &ct_receive);
+ ct_register_transmit (c, &ct_transmit);
+ ct_register_error (c, &ct_error);
+#if __FreeBSD_version >= 400000
+ d->devt = make_dev (&ct_cdevsw, b->num*NCHAN+c->num, UID_ROOT,
+ GID_WHEEL, 0600, "ct%d", b->num*NCHAN+c->num);
+ }
+ splx (s);
+
+ return 0;
+#else /* __FreeBSD_version < 400000 */
+ }
+ return 1;
+#endif /*__FreeBSD_version */
+}
+
+#if __FreeBSD_version >= 400000
+static int ct_detach (device_t dev)
+{
+ bdrv_t *bd = device_get_softc (dev);
+ ct_board_t *b = bd->board;
+ ct_chan_t *c;
+ int s = splimp ();
+
+ /* Check if the device is busy (open). */
+ for (c = b->chan; c < b->chan + NCHAN; ++c) {
+ drv_t *d = (drv_t*) c->sys;
+
+ if (!d || !d->chan->type)
+ continue;
+
+ if (d->running) {
+ splx (s);
+ return EBUSY;
+ }
+ }
+
+ /* Deactivate the timeout routine. */
+ if (led_timo[b->num].callout)
+ untimeout (ct_led_off, b, led_timo[b->num]);
+
+ bus_teardown_intr (dev, bd->irq_res, bd->intrhand);
+ bus_deactivate_resource (dev, SYS_RES_IRQ, bd->irq_rid, bd->irq_res);
+ bus_release_resource (dev, SYS_RES_IRQ, bd->irq_rid, bd->irq_res);
+
+ bus_deactivate_resource (dev, SYS_RES_DRQ, bd->drq_rid, bd->drq_res);
+ bus_release_resource (dev, SYS_RES_DRQ, bd->drq_rid, bd->drq_res);
+
+ bus_deactivate_resource (dev, SYS_RES_IOPORT, bd->base_rid, bd->irq_res);
+ bus_release_resource (dev, SYS_RES_IOPORT, bd->base_rid, bd->base_res);
+
+ ct_close_board (b);
+
+ /* Detach the interfaces, free buffer memory. */
+ for (c = b->chan; c < b->chan + NCHAN; ++c) {
+ drv_t *d = (drv_t*) c->sys;
+
+ if (!d || !d->chan->type)
+ continue;
+
+#ifdef NETGRAPH
+#if __FreeBSD_version >= 500000
+ if (d->node) {
+ ng_rmnode_self (d->node);
+ NG_NODE_UNREF (d->node);
+ d->node = NULL;
+ }
+ mtx_destroy (&d->queue.ifq_mtx);
+ mtx_destroy (&d->hi_queue.ifq_mtx);
+#else
+ ng_rmnode (d->node);
+ d->node = 0;
+#endif
+#else
+#if __FreeBSD_version >= 410000 && NBPFILTER > 0
+ /* Detach from the packet filter list of interfaces. */
+ bpfdetach (&d->pp.pp_if);
+#endif
+ /* Detach from the sync PPP list. */
+ sppp_detach (&d->pp.pp_if);
+
+ if_detach (&d->pp.pp_if);
+#endif
+ destroy_dev (d->devt);
+ }
+
+ ct_led_off (b);
+ if (led_timo[b->num].callout)
+ untimeout (ct_led_off, b, led_timo[b->num]);
+ splx (s);
+
+ s = splimp ();
+ for (c = b->chan; c < b->chan + NCHAN; ++c) {
+ drv_t *d = (drv_t*) c->sys;
+
+ if (!d || !d->chan->type)
+ continue;
+
+ /* Deallocate buffers. */
+#if __FreeBSD_version < 400000
+ free (d, M_DEVBUF);
+#else
+ contigfree (d, sizeof (*d), M_DEVBUF);
+#endif
+ }
+ bd->board = 0;
+ adapter [b->num] = 0;
+ free (b, M_DEVBUF);
+ splx (s);
+
+ return 0;
+}
+#endif
+
+#ifndef NETGRAPH
+static void ct_ifstart (struct ifnet *ifp)
+{
+ drv_t *d = ifp->if_softc;
+
+ ct_start (d);
+}
+
+static void ct_ifwatchdog (struct ifnet *ifp)
+{
+ drv_t *d = ifp->if_softc;
+
+ ct_watchdog (d);
+}
+
+static void ct_tlf (struct sppp *sp)
+{
+ drv_t *d = sp->pp_if.if_softc;
+
+ CT_DEBUG (d, ("ct_tlf\n"));
+/* ct_set_dtr (d->chan, 0);*/
+/* ct_set_rts (d->chan, 0);*/
+ sp->pp_down (sp);
+}
+
+static void ct_tls (struct sppp *sp)
+{
+ drv_t *d = sp->pp_if.if_softc;
+
+ CT_DEBUG (d, ("ct_tls\n"));
+ sp->pp_up (sp);
+}
+
+/*
+ * Initialization of interface.
+ * Ii seems to be never called by upper level.
+ */
+static void ct_initialize (void *softc)
+{
+ drv_t *d = softc;
+
+ CT_DEBUG (d, ("ct_initialize\n"));
+}
+
+/*
+ * Process an ioctl request.
+ */
+static int ct_sioctl (struct ifnet *ifp, u_long cmd, caddr_t data)
+{
+ drv_t *d = ifp->if_softc;
+ int error, s, was_up, should_be_up;
+
+ was_up = (ifp->if_flags & IFF_RUNNING) != 0;
+ error = sppp_ioctl (ifp, cmd, data);
+ if (error)
+ return error;
+
+ if (! (ifp->if_flags & IFF_DEBUG))
+ d->chan->debug = 0;
+ else if (! d->chan->debug)
+ d->chan->debug = 1;
+
+ switch (cmd) {
+ default: CT_DEBUG2 (d, ("ioctl 0x%lx\n", cmd)); return 0;
+ case SIOCADDMULTI: CT_DEBUG2 (d, ("SIOCADDMULTI\n")); return 0;
+ case SIOCDELMULTI: CT_DEBUG2 (d, ("SIOCDELMULTI\n")); return 0;
+ case SIOCSIFFLAGS: CT_DEBUG2 (d, ("SIOCSIFFLAGS\n")); break;
+ case SIOCSIFADDR: CT_DEBUG2 (d, ("SIOCSIFADDR\n")); break;
+ }
+
+ /* We get here only in case of SIFFLAGS or SIFADDR. */
+ s = splimp ();
+ should_be_up = (ifp->if_flags & IFF_RUNNING) != 0;
+ if (! was_up && should_be_up) {
+ /* Interface goes up -- start it. */
+ ct_up (d);
+ ct_start (d);
+ } else if (was_up && ! should_be_up) {
+ /* Interface is going down -- stop it. */
+ /* if ((d->pp.pp_flags & PP_FR) || (ifp->if_flags & PP_CISCO))*/
+ ct_down (d);
+ }
+ splx (s);
+ return 0;
+}
+#endif /*NETGRAPH*/
+
+/*
+ * Stop the interface. Called on splimp().
+ */
+static void ct_down (drv_t *d)
+{
+ int s = splimp ();
+ CT_DEBUG (d, ("ct_down\n"));
+ ct_set_dtr (d->chan, 0);
+ ct_set_rts (d->chan, 0);
+ d->running = 0;
+ splx (s);
+}
+
+/*
+ * Start the interface. Called on splimp().
+ */
+static void ct_up (drv_t *d)
+{
+ int s = splimp ();
+ CT_DEBUG (d, ("ct_up\n"));
+ ct_set_dtr (d->chan, 1);
+ ct_set_rts (d->chan, 1);
+ d->running = 1;
+ splx (s);
+}
+
+/*
+ * Start output on the (slave) interface. Get another datagram to send
+ * off of the interface queue, and copy it to the interface
+ * before starting the output.
+ */
+static void ct_send (drv_t *d)
+{
+ struct mbuf *m;
+ u_short len;
+
+ CT_DEBUG2 (d, ("ct_send, tn=%d\n", d->chan->tn));
+
+ /* No output if the interface is down. */
+ if (! d->running)
+ return;
+
+ /* No output if the modem is off. */
+ if (! ct_get_dsr (d->chan) && !ct_get_loop (d->chan))
+ return;
+
+ while (ct_buf_free (d->chan)) {
+ /* Get the packet to send. */
+#ifdef NETGRAPH
+ IF_DEQUEUE (&d->hi_queue, m);
+ if (! m)
+ IF_DEQUEUE (&d->queue, m);
+#else
+ m = sppp_dequeue (&d->pp.pp_if);
+#endif
+ if (! m)
+ return;
+#if (__FreeBSD_version >= 400000 || NBPFILTER > 0) && !defined (NETGRAPH)
+ if (d->pp.pp_if.if_bpf)
+#if __FreeBSD_version >= 500000
+ BPF_MTAP (&d->pp.pp_if, m);
+#else
+ bpf_mtap (&d->pp.pp_if, m);
+#endif
+#endif
+ len = m->m_pkthdr.len;
+ if (! m->m_next)
+ ct_send_packet (d->chan, (u_char*)mtod (m, caddr_t),
+ len, 0);
+ else {
+ m_copydata (m, 0, len, d->chan->tbuf[d->chan->te]);
+ ct_send_packet (d->chan, d->chan->tbuf[d->chan->te],
+ len, 0);
+ }
+ m_freem (m);
+
+ /* Set up transmit timeout, if the transmit ring is not empty.
+ * Transmit timeout is 10 seconds. */
+#ifdef NETGRAPH
+ d->timeout = 10;
+#else
+ d->pp.pp_if.if_timer = 10;
+#endif
+ }
+#ifndef NETGRAPH
+ d->pp.pp_if.if_flags |= IFF_OACTIVE;
+#endif
+}
+
+/*
+ * Start output on the interface.
+ * Always called on splimp().
+ */
+static void ct_start (drv_t *d)
+{
+ int s = splimp ();
+
+ if (d->running) {
+ if (! d->chan->dtr)
+ ct_set_dtr (d->chan, 1);
+ if (! d->chan->rts)
+ ct_set_rts (d->chan, 1);
+ ct_send (d);
+ }
+
+ splx (s);
+}
+
+/*
+ * Handle transmit timeouts.
+ * Recover after lost transmit interrupts.
+ * Always called on splimp().
+ */
+static void ct_watchdog (drv_t *d)
+{
+ int s = splimp ();
+
+ CT_DEBUG (d, ("device timeout\n"));
+ if (d->running) {
+ ct_setup_chan (d->chan);
+ ct_start_chan (d->chan, 0, 0);
+ ct_set_dtr (d->chan, 1);
+ ct_set_rts (d->chan, 1);
+ ct_start (d);
+ }
+
+ splx (s);
+}
+
+/*
+ * Transmit callback function.
+ */
+static void ct_transmit (ct_chan_t *c, void *attachment, int len)
+{
+ drv_t *d = c->sys;
+
+ if (!d)
+ return;
+#ifdef NETGRAPH
+ d->timeout = 0;
+#else
+ ++d->pp.pp_if.if_opackets;
+ d->pp.pp_if.if_flags &= ~IFF_OACTIVE;
+ d->pp.pp_if.if_timer = 0;
+#endif
+ ct_start (d);
+}
+
+/*
+ * Process the received packet.
+ */
+static void ct_receive (ct_chan_t *c, char *data, int len)
+{
+ drv_t *d = c->sys;
+ struct mbuf *m;
+#if __FreeBSD_version >= 500000 && defined NETGRAPH
+ int error;
+#endif
+
+ if (!d || !d->running)
+ return;
+
+ m = makembuf (data, len);
+ if (! m) {
+ CT_DEBUG (d, ("no memory for packet\n"));
+#ifndef NETGRAPH
+ ++d->pp.pp_if.if_iqdrops;
+#endif
+ return;
+ }
+ if (c->debug > 1)
+ printmbuf (m);
+#ifdef NETGRAPH
+ m->m_pkthdr.rcvif = 0;
+#if __FreeBSD_version >= 500000
+ NG_SEND_DATA_ONLY (error, d->hook, m);
+#else
+ ng_queue_data (d->hook, m, 0);
+#endif
+#else
+ ++d->pp.pp_if.if_ipackets;
+ m->m_pkthdr.rcvif = &d->pp.pp_if;
+#if __FreeBSD_version >= 400000 || NBPFILTER > 0
+ /* Check if there's a BPF listener on this interface.
+ * If so, hand off the raw packet to bpf. */
+ if (d->pp.pp_if.if_bpf)
+#if __FreeBSD_version >= 500000
+ BPF_TAP (&d->pp.pp_if, data, len);
+#else
+ bpf_tap (&d->pp.pp_if, data, len);
+#endif
+#endif
+ sppp_input (&d->pp.pp_if, m);
+#endif
+}
+
+/*
+ * Error callback function.
+ */
+static void ct_error (ct_chan_t *c, int data)
+{
+ drv_t *d = c->sys;
+
+ if (!d)
+ return;
+
+ switch (data) {
+ case CT_FRAME:
+ CT_DEBUG (d, ("frame error\n"));
+#ifndef NETGRAPH
+ ++d->pp.pp_if.if_ierrors;
+#endif
+ break;
+ case CT_CRC:
+ CT_DEBUG (d, ("crc error\n"));
+#ifndef NETGRAPH
+ ++d->pp.pp_if.if_ierrors;
+#endif
+ break;
+ case CT_OVERRUN:
+ CT_DEBUG (d, ("overrun error\n"));
+#ifndef NETGRAPH
+ ++d->pp.pp_if.if_collisions;
+ ++d->pp.pp_if.if_ierrors;
+#endif
+ break;
+ case CT_OVERFLOW:
+ CT_DEBUG (d, ("overflow error\n"));
+#ifndef NETGRAPH
+ ++d->pp.pp_if.if_ierrors;
+#endif
+ break;
+ case CT_UNDERRUN:
+ CT_DEBUG (d, ("underrun error\n"));
+#ifdef NETGRAPH
+ d->timeout = 0;
+#else
+ ++d->pp.pp_if.if_oerrors;
+ d->pp.pp_if.if_flags &= ~IFF_OACTIVE;
+ d->pp.pp_if.if_timer = 0;
+#endif
+ ct_start (d);
+ break;
+ default:
+ CT_DEBUG (d, ("error #%d\n", data));
+ }
+}
+
+#if __FreeBSD_version < 500000
+static int ct_open (dev_t dev, int oflags, int devtype, struct proc *p)
+#else
+static int ct_open (dev_t dev, int oflags, int devtype, struct thread *td)
+#endif
+{
+ drv_t *d;
+
+ if (minor(dev) >= NCT*NCHAN || ! (d = channel[minor(dev)]))
+ return ENXIO;
+
+ CT_DEBUG2 (d, ("ct_open\n"));
+ return 0;
+}
+
+#if __FreeBSD_version < 500000
+static int ct_close (dev_t dev, int fflag, int devtype, struct proc *p)
+#else
+static int ct_close (dev_t dev, int fflag, int devtype, struct thread *td)
+#endif
+{
+ drv_t *d = channel [minor(dev)];
+
+ if (!d)
+ return 0;
+
+ CT_DEBUG2 (d, ("ct_close\n"));
+ return 0;
+}
+
+static int ct_modem_status (ct_chan_t *c)
+{
+ drv_t *d = c->sys;
+ int status, s;
+
+ if (!d)
+ return 0;
+
+ status = d->running ? TIOCM_LE : 0;
+ s = splimp ();
+ if (ct_get_cd (c)) status |= TIOCM_CD;
+ if (ct_get_cts (c)) status |= TIOCM_CTS;
+ if (ct_get_dsr (c)) status |= TIOCM_DSR;
+ if (c->dtr) status |= TIOCM_DTR;
+ if (c->rts) status |= TIOCM_RTS;
+ splx (s);
+ return status;
+}
+
+/*
+ * Process an ioctl request on /dev/cronyx/ctauN.
+ */
+#if __FreeBSD_version < 500000
+static int ct_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p)
+#else
+static int ct_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, struct thread *td)
+#endif
+{
+ drv_t *d = channel [minor (dev)];
+ ct_chan_t *c;
+ struct serial_statistics *st;
+ struct e1_statistics *opte1;
+ int error, s;
+ char mask[16];
+
+ if (!d || !d->chan)
+ return 0;
+
+ c = d->chan;
+
+ switch (cmd) {
+ case SERIAL_GETREGISTERED:
+ bzero (mask, sizeof(mask));
+ for (s=0; s<NCT*NCHAN; ++s)
+ if (channel [s])
+ mask [s/8] |= 1 << (s & 7);
+ bcopy (mask, data, sizeof (mask));
+ return 0;
+
+#ifndef NETGRAPH
+ case SERIAL_GETPROTO:
+ strcpy ((char*)data, /*(d->pp.pp_flags & PP_FR) ? "fr" :*/
+ (d->pp.pp_if.if_flags & PP_CISCO) ? "cisco" : "ppp");
+ return 0;
+
+ case SERIAL_SETPROTO:
+ /* Only for superuser! */
+#if __FreeBSD_version < 400000
+ error = suser (p->p_ucred, &p->p_acflag);
+#elif __FreeBSD_version < 500000
+ error = suser (p);
+#else /* __FreeBSD_version >= 500000 */
+ error = suser (td);
+#endif /* __FreeBSD_version >= 500000 */
+ if (error)
+ return error;
+ if (d->pp.pp_if.if_flags & IFF_RUNNING)
+ return EBUSY;
+ if (! strcmp ("cisco", (char*)data)) {
+/* d->pp.pp_flags &= ~(PP_FR);*/
+ d->pp.pp_flags |= PP_KEEPALIVE;
+ d->pp.pp_if.if_flags |= PP_CISCO;
+/* } else if (! strcmp ("fr", (char*)data)) {
+ d->pp.pp_if.if_flags &= ~(PP_CISCO);
+ d->pp.pp_flags |= PP_FR | PP_KEEPALIVE;*/
+ } else if (! strcmp ("ppp", (char*)data)) {
+ d->pp.pp_flags &= ~(/*PP_FR | */PP_KEEPALIVE);
+ d->pp.pp_if.if_flags &= ~(PP_CISCO);
+ } else
+ return EINVAL;
+ return 0;
+
+ case SERIAL_GETKEEPALIVE:
+ if (/*(d->pp.pp_flags & PP_FR) ||*/
+ (d->pp.pp_if.if_flags & PP_CISCO))
+ return EINVAL;
+ *(int*)data = (d->pp.pp_flags & PP_KEEPALIVE) ? 1 : 0;
+ return 0;
+
+ case SERIAL_SETKEEPALIVE:
+ /* Only for superuser! */
+#if __FreeBSD_version < 400000
+ error = suser (p->p_ucred, &p->p_acflag);
+#elif __FreeBSD_version < 500000
+ error = suser (p);
+#else /* __FreeBSD_version >= 500000 */
+ error = suser (td);
+#endif /* __FreeBSD_version >= 500000 */
+ if (error)
+ return error;
+ if (/*(d->pp.pp_flags & PP_FR) ||*/
+ (d->pp.pp_if.if_flags & PP_CISCO))
+ return EINVAL;
+ if (*(int*)data)
+ d->pp.pp_flags |= PP_KEEPALIVE;
+ else
+ d->pp.pp_flags &= ~PP_KEEPALIVE;
+ return 0;
+#endif /*NETGRAPH*/
+
+ case SERIAL_GETMODE:
+ *(int*)data = SERIAL_HDLC;
+ return 0;
+
+ case SERIAL_GETCFG:
+ if (c->mode == M_HDLC)
+ return EINVAL;
+ switch (ct_get_config (c->board)) {
+ default: *(char*)data = 'a'; break;
+ case CFG_B: *(char*)data = 'b'; break;
+ case CFG_C: *(char*)data = 'c'; break;
+ }
+ return 0;
+
+ case SERIAL_SETCFG:
+ /* Only for superuser! */
+#if __FreeBSD_version < 400000
+ error = suser (p->p_ucred, &p->p_acflag);
+#elif __FreeBSD_version < 500000
+ error = suser (p);
+#else /* __FreeBSD_version >= 500000 */
+ error = suser (td);
+#endif /* __FreeBSD_version >= 500000 */
+ if (error)
+ return error;
+ if (c->mode == M_HDLC)
+ return EINVAL;
+ s = splimp ();
+ switch (*(char*)data) {
+ case 'a': ct_set_config (c->board, CFG_A); break;
+ case 'b': ct_set_config (c->board, CFG_B); break;
+ case 'c': ct_set_config (c->board, CFG_C); break;
+ }
+ splx (s);
+ return 0;
+
+ case SERIAL_GETSTAT:
+ st = (struct serial_statistics*) data;
+ st->rintr = c->rintr;
+ st->tintr = c->tintr;
+ st->mintr = c->mintr;
+ st->ibytes = c->ibytes;
+ st->ipkts = c->ipkts;
+ st->ierrs = c->ierrs;
+ st->obytes = c->obytes;
+ st->opkts = c->opkts;
+ st->oerrs = c->oerrs;
+ return 0;
+
+ case SERIAL_GETESTAT:
+ opte1 = (struct e1_statistics*)data;
+ opte1->status = c->status;
+ opte1->cursec = c->cursec;
+ opte1->totsec = c->totsec + c->cursec;
+
+ opte1->currnt.bpv = c->currnt.bpv;
+ opte1->currnt.fse = c->currnt.fse;
+ opte1->currnt.crce = c->currnt.crce;
+ opte1->currnt.rcrce = c->currnt.rcrce;
+ opte1->currnt.uas = c->currnt.uas;
+ opte1->currnt.les = c->currnt.les;
+ opte1->currnt.es = c->currnt.es;
+ opte1->currnt.bes = c->currnt.bes;
+ opte1->currnt.ses = c->currnt.ses;
+ opte1->currnt.oofs = c->currnt.oofs;
+ opte1->currnt.css = c->currnt.css;
+ opte1->currnt.dm = c->currnt.dm;
+
+ opte1->total.bpv = c->total.bpv + c->currnt.bpv;
+ opte1->total.fse = c->total.fse + c->currnt.fse;
+ opte1->total.crce = c->total.crce + c->currnt.crce;
+ opte1->total.rcrce = c->total.rcrce + c->currnt.rcrce;
+ opte1->total.uas = c->total.uas + c->currnt.uas;
+ opte1->total.les = c->total.les + c->currnt.les;
+ opte1->total.es = c->total.es + c->currnt.es;
+ opte1->total.bes = c->total.bes + c->currnt.bes;
+ opte1->total.ses = c->total.ses + c->currnt.ses;
+ opte1->total.oofs = c->total.oofs + c->currnt.oofs;
+ opte1->total.css = c->total.css + c->currnt.css;
+ opte1->total.dm = c->total.dm + c->currnt.dm;
+ for (s=0; s<48; ++s) {
+ opte1->interval[s].bpv = c->interval[s].bpv;
+ opte1->interval[s].fse = c->interval[s].fse;
+ opte1->interval[s].crce = c->interval[s].crce;
+ opte1->interval[s].rcrce = c->interval[s].rcrce;
+ opte1->interval[s].uas = c->interval[s].uas;
+ opte1->interval[s].les = c->interval[s].les;
+ opte1->interval[s].es = c->interval[s].es;
+ opte1->interval[s].bes = c->interval[s].bes;
+ opte1->interval[s].ses = c->interval[s].ses;
+ opte1->interval[s].oofs = c->interval[s].oofs;
+ opte1->interval[s].css = c->interval[s].css;
+ opte1->interval[s].dm = c->interval[s].dm;
+ }
+ return 0;
+
+ case SERIAL_CLRSTAT:
+ /* Only for superuser! */
+#if __FreeBSD_version < 400000
+ error = suser (p->p_ucred, &p->p_acflag);
+#elif __FreeBSD_version < 500000
+ error = suser (p);
+#else /* __FreeBSD_version >= 500000 */
+ error = suser (td);
+#endif /* __FreeBSD_version >= 500000 */
+ if (error)
+ return error;
+ c->rintr = 0;
+ c->tintr = 0;
+ c->mintr = 0;
+ c->ibytes = 0;
+ c->ipkts = 0;
+ c->ierrs = 0;
+ c->obytes = 0;
+ c->opkts = 0;
+ c->oerrs = 0;
+ bzero (&c->currnt, sizeof (c->currnt));
+ bzero (&c->total, sizeof (c->total));
+ bzero (c->interval, sizeof (c->interval));
+ return 0;
+
+ case SERIAL_GETBAUD:
+ *(long*)data = ct_get_baud(c);
+ return 0;
+
+ case SERIAL_SETBAUD:
+ /* Only for superuser! */
+#if __FreeBSD_version < 400000
+ error = suser (p->p_ucred, &p->p_acflag);
+#elif __FreeBSD_version < 500000
+ error = suser (p);
+#else /* __FreeBSD_version >= 500000 */
+ error = suser (td);
+#endif /* __FreeBSD_version >= 500000 */
+ if (error)
+ return error;
+ s = splimp ();
+ ct_set_baud (c, *(long*)data);
+ splx (s);
+ return 0;
+
+ case SERIAL_GETLOOP:
+ *(int*)data = ct_get_loop (c);
+ return 0;
+
+ case SERIAL_SETLOOP:
+ /* Only for superuser! */
+#if __FreeBSD_version < 400000
+ error = suser (p->p_ucred, &p->p_acflag);
+#elif __FreeBSD_version < 500000
+ error = suser (p);
+#else /* __FreeBSD_version >= 500000 */
+ error = suser (td);
+#endif /* __FreeBSD_version >= 500000 */
+ if (error)
+ return error;
+ s = splimp ();
+ ct_set_loop (c, *(int*)data);
+ splx (s);
+ return 0;
+
+ case SERIAL_GETDPLL:
+ if (c->mode == M_E1 || c->mode == M_G703)
+ return EINVAL;
+ *(int*)data = ct_get_dpll (c);
+ return 0;
+
+ case SERIAL_SETDPLL:
+ /* Only for superuser! */
+#if __FreeBSD_version < 400000
+ error = suser (p->p_ucred, &p->p_acflag);
+#elif __FreeBSD_version < 500000
+ error = suser (p);
+#else /* __FreeBSD_version >= 500000 */
+ error = suser (td);
+#endif /* __FreeBSD_version >= 500000 */
+ if (error)
+ return error;
+ if (c->mode == M_E1 || c->mode == M_G703)
+ return EINVAL;
+ s = splimp ();
+ ct_set_dpll (c, *(int*)data);
+ splx (s);
+ return 0;
+
+ case SERIAL_GETNRZI:
+ if (c->mode == M_E1 || c->mode == M_G703)
+ return EINVAL;
+ *(int*)data = ct_get_nrzi (c);
+ return 0;
+
+ case SERIAL_SETNRZI:
+ /* Only for superuser! */
+#if __FreeBSD_version < 400000
+ error = suser (p->p_ucred, &p->p_acflag);
+#elif __FreeBSD_version < 500000
+ error = suser (p);
+#else /* __FreeBSD_version >= 500000 */
+ error = suser (td);
+#endif /* __FreeBSD_version >= 500000 */
+ if (error)
+ return error;
+ if (c->mode == M_E1 || c->mode == M_G703)
+ return EINVAL;
+ s = splimp ();
+ ct_set_nrzi (c, *(int*)data);
+ splx (s);
+ return 0;
+
+ case SERIAL_GETDEBUG:
+ *(int*)data = c->debug;
+ return 0;
+
+ case SERIAL_SETDEBUG:
+ /* Only for superuser! */
+#if __FreeBSD_version < 400000
+ error = suser (p->p_ucred, &p->p_acflag);
+#elif __FreeBSD_version < 500000
+ error = suser (p);
+#else /* __FreeBSD_version >= 500000 */
+ error = suser (td);
+#endif /* __FreeBSD_version >= 500000 */
+ if (error)
+ return error;
+ c->debug = *(int*)data;
+#ifndef NETGRAPH
+ if (d->chan->debug)
+ d->pp.pp_if.if_flags |= IFF_DEBUG;
+ else
+ d->pp.pp_if.if_flags &= (~IFF_DEBUG);
+#endif
+ return 0;
+
+ case SERIAL_GETHIGAIN:
+ if (c->mode != M_E1)
+ return EINVAL;
+ *(int*)data = ct_get_higain (c);
+ return 0;
+
+ case SERIAL_SETHIGAIN:
+ /* Only for superuser! */
+#if __FreeBSD_version < 400000
+ error = suser (p->p_ucred, &p->p_acflag);
+#elif __FreeBSD_version < 500000
+ error = suser (p);
+#else /* __FreeBSD_version >= 500000 */
+ error = suser (td);
+#endif /* __FreeBSD_version >= 500000 */
+ if (error)
+ return error;
+ s = splimp ();
+ ct_set_higain (c, *(int*)data);
+ splx (s);
+ return 0;
+
+ case SERIAL_GETPHONY:
+ CT_DEBUG2 (d, ("ioctl: getphony\n"));
+ if (c->mode != M_E1)
+ return EINVAL;
+ *(int*)data = c->gopt.phony;
+ return 0;
+
+ case SERIAL_SETPHONY:
+ CT_DEBUG2 (d, ("ioctl: setphony\n"));
+ if (c->mode != M_E1)
+ return EINVAL;
+ /* Only for superuser! */
+#if __FreeBSD_version < 400000
+ error = suser (p->p_ucred, &p->p_acflag);
+#elif __FreeBSD_version < 500000
+ error = suser (p);
+#else /* __FreeBSD_version >= 500000 */
+ error = suser (td);
+#endif /* __FreeBSD_version >= 500000 */
+ if (error)
+ return error;
+ s = splimp ();
+ ct_set_phony (c, *(int*)data);
+ splx (s);
+ return 0;
+
+ case SERIAL_GETCLK:
+ if (c->mode != M_E1 && c->mode != M_G703)
+ return EINVAL;
+ switch (ct_get_clk(c)) {
+ default: *(int*)data = E1CLK_INTERNAL; break;
+ case GCLK_RCV: *(int*)data = E1CLK_RECEIVE; break;
+ case GCLK_RCLKO: *(int*)data = c->num ?
+ E1CLK_RECEIVE_CHAN0 : E1CLK_RECEIVE_CHAN1; break;
+ }
+ return 0;
+
+ case SERIAL_SETCLK:
+ /* Only for superuser! */
+#if __FreeBSD_version < 400000
+ error = suser (p->p_ucred, &p->p_acflag);
+#elif __FreeBSD_version < 500000
+ error = suser (p);
+#else /* __FreeBSD_version >= 500000 */
+ error = suser (td);
+#endif /* __FreeBSD_version >= 500000 */
+ if (error)
+ return error;
+ s = splimp ();
+ switch (*(int*)data) {
+ default: ct_set_clk (c, GCLK_INT); break;
+ case E1CLK_RECEIVE: ct_set_clk (c, GCLK_RCV); break;
+ case E1CLK_RECEIVE_CHAN0:
+ case E1CLK_RECEIVE_CHAN1:
+ ct_set_clk (c, GCLK_RCLKO); break;
+ }
+ splx (s);
+ return 0;
+
+ case SERIAL_GETTIMESLOTS:
+ if (c->mode != M_E1)
+ return EINVAL;
+ *(long*)data = ct_get_ts (c);
+ return 0;
+
+ case SERIAL_SETTIMESLOTS:
+ /* Only for superuser! */
+#if __FreeBSD_version < 400000
+ error = suser (p->p_ucred, &p->p_acflag);
+#elif __FreeBSD_version < 500000
+ error = suser (p);
+#else /* __FreeBSD_version >= 500000 */
+ error = suser (td);
+#endif /* __FreeBSD_version >= 500000 */
+ if (error)
+ return error;
+ s = splimp ();
+ ct_set_ts (c, *(long*)data);
+ splx (s);
+ return 0;
+
+ case SERIAL_GETSUBCHAN:
+ if (c->mode != M_E1)
+ return EINVAL;
+ *(long*)data = ct_get_subchan (c->board);
+ return 0;
+
+ case SERIAL_SETSUBCHAN:
+ /* Only for superuser! */
+#if __FreeBSD_version < 400000
+ error = suser (p->p_ucred, &p->p_acflag);
+#elif __FreeBSD_version < 500000
+ error = suser (p);
+#else /* __FreeBSD_version >= 500000 */
+ error = suser (td);
+#endif /* __FreeBSD_version >= 500000 */
+ if (error)
+ return error;
+ s = splimp ();
+ ct_set_subchan (c->board, *(long*)data);
+ splx (s);
+ return 0;
+
+ case SERIAL_GETINVCLK:
+ case SERIAL_GETINVTCLK:
+ if (c->mode == M_E1 || c->mode == M_G703)
+ return EINVAL;
+ *(int*)data = ct_get_invtxc (c);
+ return 0;
+
+ case SERIAL_GETINVRCLK:
+ if (c->mode == M_E1 || c->mode == M_G703)
+ return EINVAL;
+ *(int*)data = ct_get_invrxc (c);
+ return 0;
+
+ case SERIAL_SETINVCLK:
+ case SERIAL_SETINVTCLK:
+ /* Only for superuser! */
+#if __FreeBSD_version < 400000
+ error = suser (p->p_ucred, &p->p_acflag);
+#elif __FreeBSD_version < 500000
+ error = suser (p);
+#else /* __FreeBSD_version >= 500000 */
+ error = suser (td);
+#endif /* __FreeBSD_version >= 500000 */
+ if (error)
+ return error;
+ if (c->mode == M_E1 || c->mode == M_G703)
+ return EINVAL;
+ s = splimp ();
+ ct_set_invtxc (c, *(int*)data);
+ splx (s);
+ return 0;
+
+ case SERIAL_SETINVRCLK:
+ /* Only for superuser! */
+#if __FreeBSD_version < 400000
+ error = suser (p->p_ucred, &p->p_acflag);
+#elif __FreeBSD_version < 500000
+ error = suser (p);
+#else /* __FreeBSD_version >= 500000 */
+ error = suser (td);
+#endif /* __FreeBSD_version >= 500000 */
+ if (error)
+ return error;
+ if (c->mode == M_E1 || c->mode == M_G703)
+ return EINVAL;
+ s = splimp ();
+ ct_set_invrxc (c, *(int*)data);
+ splx (s);
+ return 0;
+
+ case SERIAL_GETLEVEL:
+ if (c->mode != M_G703)
+ return EINVAL;
+ s = splimp ();
+ *(int*)data = ct_get_lq (c);
+ splx (s);
+ return 0;
+
+ case TIOCSDTR: /* Set DTR */
+ s = splimp ();
+ ct_set_dtr (c, 1);
+ splx (s);
+ return 0;
+
+ case TIOCCDTR: /* Clear DTR */
+ s = splimp ();
+ ct_set_dtr (c, 0);
+ splx (s);
+ return 0;
+
+ case TIOCMSET: /* Set DTR/RTS */
+ s = splimp ();
+ ct_set_dtr (c, (*(int*)data & TIOCM_DTR) ? 1 : 0);
+ ct_set_rts (c, (*(int*)data & TIOCM_RTS) ? 1 : 0);
+ splx (s);
+ return 0;
+
+ case TIOCMBIS: /* Add DTR/RTS */
+ s = splimp ();
+ if (*(int*)data & TIOCM_DTR) ct_set_dtr (c, 1);
+ if (*(int*)data & TIOCM_RTS) ct_set_rts (c, 1);
+ splx (s);
+ return 0;
+
+ case TIOCMBIC: /* Clear DTR/RTS */
+ s = splimp ();
+ if (*(int*)data & TIOCM_DTR) ct_set_dtr (c, 0);
+ if (*(int*)data & TIOCM_RTS) ct_set_rts (c, 0);
+ splx (s);
+ return 0;
+
+ case TIOCMGET: /* Get modem status */
+ *(int*)data = ct_modem_status (c);
+ return 0;
+ }
+ return ENOTTY;
+}
+
+#if __FreeBSD_version < 400000
+struct isa_driver ctdriver = { ct_probe, ct_attach, "ct" };
+static struct cdevsw ct_cdevsw = {
+ ct_open, ct_close, noread, nowrite,
+ ct_ioctl, nostop, noreset, nodevtotty,
+ seltrue, nommap, NULL, "ct",
+ NULL, -1,
+};
+#elif __FreeBSD_version < 500000
+static struct cdevsw ct_cdevsw = {
+ ct_open, ct_close, noread, nowrite,
+ ct_ioctl, nopoll, nommap, nostrategy,
+ "ct", CDEV_MAJOR, nodump, nopsize,
+ D_NAGGED, -1
+};
+#elif __FreeBSD_version == 500000
+static struct cdevsw ct_cdevsw = {
+ ct_open, ct_close, noread, nowrite,
+ ct_ioctl, nopoll, nommap, nostrategy,
+ "ct", CDEV_MAJOR, nodump, nopsize,
+ D_NAGGED,
+ };
+#elif __FreeBSD_version <= 501000
+static struct cdevsw ct_cdevsw = {
+ .d_open = ct_open,
+ .d_close = ct_close,
+ .d_read = noread,
+ .d_write = nowrite,
+ .d_ioctl = ct_ioctl,
+ .d_poll = nopoll,
+ .d_mmap = nommap,
+ .d_strategy = nostrategy,
+ .d_name = "ct",
+ .d_maj = CDEV_MAJOR,
+ .d_dump = nodump,
+ .d_flags = D_NAGGED,
+};
+#else /* __FreeBSD_version > 501000 */
+static struct cdevsw ct_cdevsw = {
+ .d_version = D_VERSION,
+ .d_open = ct_open,
+ .d_close = ct_close,
+ .d_ioctl = ct_ioctl,
+ .d_name = "ct",
+ .d_maj = CDEV_MAJOR,
+ .d_flags = D_NAGGED | D_NEEDGIANT,
+};
+#endif /* __FreeBSD_version > 501000 */
+
+#ifdef NETGRAPH
+#if __FreeBSD_version >= 500000
+static int ng_ct_constructor (node_p node)
+{
+ drv_t *d = NG_NODE_PRIVATE (node);
+#else
+static int ng_ct_constructor (node_p *node)
+{
+ drv_t *d = (*node)->private;
+#endif
+ CT_DEBUG (d, ("Constructor\n"));
+ return EINVAL;
+}
+
+static int ng_ct_newhook (node_p node, hook_p hook, const char *name)
+{
+ int s;
+#if __FreeBSD_version >= 500000
+ drv_t *d = NG_NODE_PRIVATE (node);
+#else
+ drv_t *d = node->private;
+#endif
+
+ if (!d)
+ return EINVAL;
+
+ /* Attach debug hook */
+ if (strcmp (name, NG_CT_HOOK_DEBUG) == 0) {
+#if __FreeBSD_version >= 500000
+ NG_HOOK_SET_PRIVATE (hook, NULL);
+#else
+ hook->private = 0;
+#endif
+ d->debug_hook = hook;
+ return 0;
+ }
+
+ /* Check for raw hook */
+ if (strcmp (name, NG_CT_HOOK_RAW) != 0)
+ return EINVAL;
+
+#if __FreeBSD_version >= 500000
+ NG_HOOK_SET_PRIVATE (hook, d);
+#else
+ hook->private = d;
+#endif
+ d->hook = hook;
+ s = splimp ();
+ ct_up (d);
+ splx (s);
+ return 0;
+}
+
+static char *format_timeslots (u_long s)
+{
+ static char buf [100];
+ char *p = buf;
+ int i;
+
+ for (i=1; i<32; ++i)
+ if ((s >> i) & 1) {
+ int prev = (i > 1) & (s >> (i-1));
+ int next = (i < 31) & (s >> (i+1));
+
+ if (prev) {
+ if (next)
+ continue;
+ *p++ = '-';
+ } else if (p > buf)
+ *p++ = ',';
+
+ if (i >= 10)
+ *p++ = '0' + i / 10;
+ *p++ = '0' + i % 10;
+ }
+ *p = 0;
+ return buf;
+}
+
+static int print_modems (char *s, ct_chan_t *c, int need_header)
+{
+ int status = ct_modem_status (c);
+ int length = 0;
+
+ if (need_header)
+ length += sprintf (s + length, " LE DTR DSR RTS CTS CD\n");
+ length += sprintf (s + length, "%4s %4s %4s %4s %4s %4s\n",
+ status & TIOCM_LE ? "On" : "-",
+ status & TIOCM_DTR ? "On" : "-",
+ status & TIOCM_DSR ? "On" : "-",
+ status & TIOCM_RTS ? "On" : "-",
+ status & TIOCM_CTS ? "On" : "-",
+ status & TIOCM_CD ? "On" : "-");
+ return length;
+}
+
+static int print_stats (char *s, ct_chan_t *c, int need_header)
+{
+ struct serial_statistics st;
+ int length = 0;
+
+ st.rintr = c->rintr;
+ st.tintr = c->tintr;
+ st.mintr = c->mintr;
+ st.ibytes = c->ibytes;
+ st.ipkts = c->ipkts;
+ st.ierrs = c->ierrs;
+ st.obytes = c->obytes;
+ st.opkts = c->opkts;
+ st.oerrs = c->oerrs;
+ if (need_header)
+ length += sprintf (s + length, " Rintr Tintr Mintr Ibytes Ipkts Ierrs Obytes Opkts Oerrs\n");
+ length += sprintf (s + length, "%7ld %7ld %7ld %8ld %7ld %7ld %8ld %7ld %7ld\n",
+ st.rintr, st.tintr, st.mintr, st.ibytes, st.ipkts,
+ st.ierrs, st.obytes, st.opkts, st.oerrs);
+ return length;
+}
+
+static char *format_e1_status (u_char status)
+{
+ static char buf [80];
+
+ if (status & E1_NOALARM)
+ return "Ok";
+ buf[0] = 0;
+ if (status & E1_LOS) strcat (buf, ",LOS");
+ if (status & E1_AIS) strcat (buf, ",AIS");
+ if (status & E1_LOF) strcat (buf, ",LOF");
+ if (status & E1_LOMF) strcat (buf, ",LOMF");
+ if (status & E1_FARLOF) strcat (buf, ",FARLOF");
+ if (status & E1_AIS16) strcat (buf, ",AIS16");
+ if (status & E1_FARLOMF) strcat (buf, ",FARLOMF");
+ if (status & E1_TSTREQ) strcat (buf, ",TSTREQ");
+ if (status & E1_TSTERR) strcat (buf, ",TSTERR");
+ if (buf[0] == ',')
+ return buf+1;
+ return "Unknown";
+}
+
+static int print_frac (char *s, int leftalign, u_long numerator, u_long divider)
+{
+ int n, length = 0;
+
+ if (numerator < 1 || divider < 1) {
+ length += sprintf (s+length, leftalign ? "/- " : " -");
+ return length;
+ }
+ n = (int) (0.5 + 1000.0 * numerator / divider);
+ if (n < 1000) {
+ length += sprintf (s+length, leftalign ? "/.%-3d" : " .%03d", n);
+ return length;
+ }
+ *(s + length) = leftalign ? '/' : ' ';
+ length ++;
+
+ if (n >= 1000000) n = (n+500) / 1000 * 1000;
+ else if (n >= 100000) n = (n+50) / 100 * 100;
+ else if (n >= 10000) n = (n+5) / 10 * 10;
+
+ switch (n) {
+ case 1000: length += printf (s+length, ".999"); return length;
+ case 10000: n = 9990; break;
+ case 100000: n = 99900; break;
+ case 1000000: n = 999000; break;
+ }
+ if (n < 10000) length += sprintf (s+length, "%d.%d", n/1000, n/10%100);
+ else if (n < 100000) length += sprintf (s+length, "%d.%d", n/1000, n/100%10);
+ else if (n < 1000000) length += sprintf (s+length, "%d.", n/1000);
+ else length += sprintf (s+length, "%d", n/1000);
+
+ return length;
+}
+
+static int print_e1_stats (char *s, ct_chan_t *c)
+{
+ struct e1_counters total;
+ u_long totsec;
+ int length = 0;
+
+ totsec = c->totsec + c->cursec;
+ total.bpv = c->total.bpv + c->currnt.bpv;
+ total.fse = c->total.fse + c->currnt.fse;
+ total.crce = c->total.crce + c->currnt.crce;
+ total.rcrce = c->total.rcrce + c->currnt.rcrce;
+ total.uas = c->total.uas + c->currnt.uas;
+ total.les = c->total.les + c->currnt.les;
+ total.es = c->total.es + c->currnt.es;
+ total.bes = c->total.bes + c->currnt.bes;
+ total.ses = c->total.ses + c->currnt.ses;
+ total.oofs = c->total.oofs + c->currnt.oofs;
+ total.css = c->total.css + c->currnt.css;
+ total.dm = c->total.dm + c->currnt.dm;
+
+ length += sprintf (s + length, " Unav/Degr Bpv/Fsyn CRC/RCRC Err/Lerr Sev/Bur Oof/Slp Status\n");
+
+ /* Unavailable seconds, degraded minutes */
+ length += print_frac (s + length, 0, c->currnt.uas, c->cursec);
+ length += print_frac (s + length, 1, 60 * c->currnt.dm, c->cursec);
+
+ /* Bipolar violations, frame sync errors */
+ length += print_frac (s + length, 0, c->currnt.bpv, c->cursec);
+ length += print_frac (s + length, 1, c->currnt.fse, c->cursec);
+
+ /* CRC errors, remote CRC errors (E-bit) */
+ length += print_frac (s + length, 0, c->currnt.crce, c->cursec);
+ length += print_frac (s + length, 1, c->currnt.rcrce, c->cursec);
+
+ /* Errored seconds, line errored seconds */
+ length += print_frac (s + length, 0, c->currnt.es, c->cursec);
+ length += print_frac (s + length, 1, c->currnt.les, c->cursec);
+
+ /* Severely errored seconds, burst errored seconds */
+ length += print_frac (s + length, 0, c->currnt.ses, c->cursec);
+ length += print_frac (s + length, 1, c->currnt.bes, c->cursec);
+
+ /* Out of frame seconds, controlled slip seconds */
+ length += print_frac (s + length, 0, c->currnt.oofs, c->cursec);
+ length += print_frac (s + length, 1, c->currnt.css, c->cursec);
+
+ length += sprintf (s + length, " %s\n", format_e1_status (c->status));
+
+ /* Print total statistics. */
+ length += print_frac (s + length, 0, total.uas, totsec);
+ length += print_frac (s + length, 1, 60 * total.dm, totsec);
+
+ length += print_frac (s + length, 0, total.bpv, totsec);
+ length += print_frac (s + length, 1, total.fse, totsec);
+
+ length += print_frac (s + length, 0, total.crce, totsec);
+ length += print_frac (s + length, 1, total.rcrce, totsec);
+
+ length += print_frac (s + length, 0, total.es, totsec);
+ length += print_frac (s + length, 1, total.les, totsec);
+
+ length += print_frac (s + length, 0, total.ses, totsec);
+ length += print_frac (s + length, 1, total.bes, totsec);
+
+ length += print_frac (s + length, 0, total.oofs, totsec);
+ length += print_frac (s + length, 1, total.css, totsec);
+
+ length += sprintf (s + length, " -- Total\n");
+ return length;
+}
+
+static int print_chan (char *s, ct_chan_t *c)
+{
+ drv_t *d = c->sys;
+ int length = 0;
+
+ length += sprintf (s + length, "ct%d", c->board->num * NCHAN + c->num);
+ if (d->chan->debug)
+ length += sprintf (s + length, " debug=%d", d->chan->debug);
+
+ switch (ct_get_config (c->board)) {
+ case CFG_A: length += sprintf (s + length, " cfg=A"); break;
+ case CFG_B: length += sprintf (s + length, " cfg=B"); break;
+ case CFG_C: length += sprintf (s + length, " cfg=C"); break;
+ default: length += sprintf (s + length, " cfg=unknown"); break;
+ }
+
+ if (ct_get_baud (c))
+ length += sprintf (s + length, " %ld", ct_get_baud (c));
+ else
+ length += sprintf (s + length, " extclock");
+
+ if (c->mode == M_E1 || c->mode == M_G703)
+ switch (ct_get_clk(c)) {
+ case GCLK_INT : length += sprintf (s + length, " syn=int"); break;
+ case GCLK_RCV : length += sprintf (s + length, " syn=rcv"); break;
+ case GCLK_RCLKO : length += sprintf (s + length, " syn=xrcv"); break;
+ }
+ if (c->mode == M_HDLC) {
+ length += sprintf (s + length, " dpll=%s", ct_get_dpll (c) ? "on" : "off");
+ length += sprintf (s + length, " nrzi=%s", ct_get_nrzi (c) ? "on" : "off");
+ length += sprintf (s + length, " invtclk=%s", ct_get_invtxc (c) ? "on" : "off");
+ length += sprintf (s + length, " invrclk=%s", ct_get_invrxc (c) ? "on" : "off");
+ }
+ if (c->mode == M_E1)
+ length += sprintf (s + length, " higain=%s", ct_get_higain (c)? "on" : "off");
+
+ length += sprintf (s + length, " loop=%s", ct_get_loop (c) ? "on" : "off");
+
+ if (c->mode == M_E1)
+ length += sprintf (s + length, " ts=%s", format_timeslots (ct_get_ts(c)));
+ if (c->mode == M_E1 && ct_get_config (c->board) != CFG_A)
+ length += sprintf (s + length, " pass=%s", format_timeslots (ct_get_subchan(c->board)));
+ if (c->mode == M_G703) {
+ int lq, x;
+
+ x = splimp ();
+ lq = ct_get_lq (c);
+ splx (x);
+ length += sprintf (s + length, " (level=-%.1fdB)", lq / 10.0);
+ }
+ length += sprintf (s + length, "\n");
+ return length;
+}
+
+#if __FreeBSD_version >= 500000
+static int ng_ct_rcvmsg (node_p node, item_p item, hook_p lasthook)
+{
+ drv_t *d = NG_NODE_PRIVATE (node);
+ struct ng_mesg *msg;
+#else
+static int ng_ct_rcvmsg (node_p node, struct ng_mesg *msg,
+ const char *retaddr, struct ng_mesg **rptr)
+{
+ drv_t *d = node->private;
+#endif
+ struct ng_mesg *resp = NULL;
+ int error = 0;
+
+ if (!d)
+ return EINVAL;
+
+ CT_DEBUG (d, ("Rcvmsg\n"));
+#if __FreeBSD_version >= 500000
+ NGI_GET_MSG (item, msg);
+#endif
+ switch (msg->header.typecookie) {
+ default:
+ error = EINVAL;
+ break;
+
+ case NGM_CT_COOKIE:
+ printf ("Don't forget to implement\n");
+ error = EINVAL;
+ break;
+
+ case NGM_GENERIC_COOKIE:
+ switch (msg->header.cmd) {
+ default:
+ error = EINVAL;
+ break;
+
+ case NGM_TEXT_STATUS: {
+ char *s;
+ int l = 0;
+ int dl = sizeof (struct ng_mesg) + 730;
+
+#if __FreeBSD_version >= 500000
+ NG_MKRESPONSE (resp, msg, dl, M_NOWAIT);
+ if (! resp) {
+ error = ENOMEM;
+ break;
+ }
+#else
+ MALLOC (resp, struct ng_mesg *, dl,
+ M_NETGRAPH, M_NOWAIT);
+ if (! resp) {
+ error = ENOMEM;
+ break;
+ }
+ bzero (resp, dl);
+#endif
+ s = (resp)->data;
+ l += print_chan (s + l, d->chan);
+ l += print_stats (s + l, d->chan, 1);
+ l += print_modems (s + l, d->chan, 1);
+ l += print_e1_stats (s + l, d->chan);
+#if __FreeBSD_version < 500000
+ (resp)->header.version = NG_VERSION;
+ (resp)->header.arglen = strlen (s) + 1;
+ (resp)->header.token = msg->header.token;
+ (resp)->header.typecookie = NGM_CT_COOKIE;
+ (resp)->header.cmd = msg->header.cmd;
+#endif
+ strncpy ((resp)->header.cmdstr, "status", NG_CMDSTRLEN);
+ }
+ break;
+ }
+ break;
+ }
+#if __FreeBSD_version >= 500000
+ NG_RESPOND_MSG (error, node, item, resp);
+ NG_FREE_MSG (msg);
+#else
+ *rptr = resp;
+ FREE (msg, M_NETGRAPH);
+#endif
+ return error;
+}
+
+#if __FreeBSD_version >= 500000
+static int ng_ct_rcvdata (hook_p hook, item_p item)
+{
+ drv_t *d = NG_NODE_PRIVATE (NG_HOOK_NODE(hook));
+ struct mbuf *m;
+ meta_p meta;
+#else
+static int ng_ct_rcvdata (hook_p hook, struct mbuf *m, meta_p meta)
+{
+ drv_t *d = hook->node->private;
+#endif
+ struct ifqueue *q;
+ int s;
+
+ if (!d)
+ return ENETDOWN;
+
+#if __FreeBSD_version >= 500000
+ NGI_GET_M (item, m);
+ NGI_GET_META (item, meta);
+ NG_FREE_ITEM (item);
+ if (! NG_HOOK_PRIVATE (hook) || ! d) {
+ NG_FREE_M (m);
+ NG_FREE_META (meta);
+#else
+ if (! hook->private || ! d) {
+ NG_FREE_DATA (m,meta);
+#endif
+ return ENETDOWN;
+ }
+ q = (meta && meta->priority > 0) ? &d->hi_queue : &d->queue;
+ s = splimp ();
+#if __FreeBSD_version >= 500000
+ IF_LOCK (q);
+ if (_IF_QFULL (q)) {
+ _IF_DROP (q);
+ IF_UNLOCK (q);
+ splx (s);
+ NG_FREE_M (m);
+ NG_FREE_META (meta);
+ return ENOBUFS;
+ }
+ _IF_ENQUEUE (q, m);
+ IF_UNLOCK (q);
+#else
+ if (IF_QFULL (q)) {
+ IF_DROP (q);
+ splx (s);
+ NG_FREE_DATA (m, meta);
+ return ENOBUFS;
+ }
+ IF_ENQUEUE (q, m);
+#endif
+ ct_start (d);
+ splx (s);
+ return 0;
+}
+
+static int ng_ct_rmnode (node_p node)
+{
+#if __FreeBSD_version >= 500000
+ drv_t *d = NG_NODE_PRIVATE (node);
+
+ CT_DEBUG (d, ("Rmnode\n"));
+ if (d && d->running) {
+ int s = splimp ();
+ ct_down (d);
+ splx (s);
+ }
+#ifdef KLD_MODULE
+ if (node->nd_flags & NG_REALLY_DIE) {
+ NG_NODE_SET_PRIVATE (node, NULL);
+ NG_NODE_UNREF (node);
+ }
+ node->nd_flags &= ~NG_INVALID;
+#endif
+#else /* __FreeBSD_version < 500000 */
+ drv_t *d = node->private;
+ int s;
+
+ if (!d)
+ return 0;
+
+ s = splimp ();
+ ct_down (d);
+ splx (s);
+ node->flags |= NG_INVALID;
+ ng_cutlinks (node);
+#ifdef KLD_MODULE
+ ng_unname (node);
+ ng_unref (node);
+#else
+ node->flags &= ~NG_INVALID;
+#endif
+#endif
+ return 0;
+}
+
+static void ng_ct_watchdog (void *arg)
+{
+ drv_t *d = arg;
+
+ if (!d)
+ return;
+
+ if (d->timeout == 1)
+ ct_watchdog (d);
+ if (d->timeout)
+ d->timeout--;
+ d->timeout_handle = timeout (ng_ct_watchdog, d, hz);
+}
+
+static int ng_ct_connect (hook_p hook)
+{
+#if __FreeBSD_version >= 500000
+ drv_t *d = NG_NODE_PRIVATE (NG_HOOK_NODE (hook));
+#else
+ drv_t *d = hook->node->private;
+#endif
+
+ if (!d)
+ return 0;
+
+ d->timeout_handle = timeout (ng_ct_watchdog, d, hz);
+ return 0;
+}
+
+static int ng_ct_disconnect (hook_p hook)
+{
+#if __FreeBSD_version >= 500000
+ drv_t *d = NG_NODE_PRIVATE (NG_HOOK_NODE (hook));
+#else
+ drv_t *d = hook->node->private;
+#endif
+
+ if (!d)
+ return 0;
+
+#if __FreeBSD_version >= 500000
+ if (NG_HOOK_PRIVATE (hook))
+#else
+ if (hook->private)
+#endif
+ ct_down (d);
+ untimeout (ng_ct_watchdog, d, d->timeout_handle);
+ return 0;
+}
+#endif
+
+#ifdef KLD_MODULE
+#if __FreeBSD_version < 400000
+/*
+ * Function called when loading the driver.
+ */
+static int ct_load (void)
+{
+ int i;
+
+ for (i=0;i<NCT; ++i) {
+ struct isa_device id = {-1, &ctdriver, -1, 0, -1, 0, 0, (inthand2_t *)ct_intr, i, 0, 0, 0, 0 ,0 ,1 ,0 ,0};
+ disable_intr();
+ if (!ct_probe (&id)) {
+ enable_intr();
+ break;
+ }
+ ct_attach (&id);
+ register_intr ((adapter [i])->irq, 0, 0, (inthand2_t*) ct_intr,
+ &net_imask, id.id_unit);
+ enable_intr();
+ }
+ if (!i) {
+ /* Deactivate the timeout routine. */
+ untimeout (ct_timeout, 0, timeout_handle);
+
+ return ENXIO;
+ }
+ return 0;
+}
+
+/*
+ * Function called when unloading the driver.
+ */
+static int ct_unload (void)
+{
+ int i, s;
+
+ /* Check if the device is busy (open). */
+ for (i=0; i<NCT*NCHAN; ++i) {
+ drv_t *d = channel[i];
+
+ if (!d)
+ continue;
+ if (d->running)
+ return EBUSY;
+ }
+
+ /* OK to unload the driver, unregister the interrupt first. */
+ s = splimp ();
+
+ /* Deactivate the timeout routine. */
+ for (i=0; i<NCT; ++i) {
+ if (!adapter [i])
+ continue;
+ untimeout (ct_timeout, 0, timeout_handle);
+ break;
+ }
+
+ for (i=0; i<NCT; ++i) {
+ ct_board_t *b = adapter [i];
+
+ if (!b || ! b->port)
+ continue;
+
+ ct_close_board (b);
+ }
+
+ for (i=0; i<NCT; ++i) {
+ ct_board_t *b = adapter [i];
+
+ if (!b || ! b->port)
+ continue;
+
+ if (led_timo[i].callout)
+ untimeout (ct_led_off, b, led_timo[i]);
+ }
+
+ for (i=0; i<NCT; ++i) {
+ ct_board_t *b = adapter [i];
+
+ if (!b || ! b->port)
+ continue;
+
+ /* Disable the interrupt request. */
+ disable_intr();
+ unregister_intr (b->irq, (inthand2_t *)ct_intr);
+ isa_dma_release (b->dma);
+ enable_intr();
+ }
+
+ /* Detach the interfaces, free buffer memory. */
+ for (i=0; i<NCT*NCHAN; ++i) {
+ drv_t *d = channel[i];
+
+ if (!d)
+ continue;
+
+#ifndef NETGRAPH
+#if NBPFILTER > 0
+ /* Detach from the packet filter list of interfaces. */
+ {
+ struct bpf_if *q, **b = &bpf_iflist;
+
+ while ((q = *b)) {
+ if (q->bif_ifp == d->pp.pp_if) {
+ *b = q->bif_next;
+ free (q, M_DEVBUF);
+ }
+ b = &(q->bif_next);
+ }
+ }
+#endif /* NBPFILTER > 0 */
+ /* Detach from the sync PPP list. */
+ sppp_detach (&d->pp.pp_if);
+
+ /* Detach from the system list of interfaces. */
+ {
+ struct ifaddr *ifa;
+ TAILQ_FOREACH (ifa, &d->pp.pp_if.if_addrhead, ifa_link) {
+ TAILQ_REMOVE (&d->pp.pp_if.if_addrhead, ifa, ifa_link);
+ free (ifa, M_IFADDR);
+ }
+ TAILQ_REMOVE (&ifnet, &d->pp.pp_if, if_link);
+ }
+#endif /* !NETGRAPH */
+ /* Deallocate buffers. */
+/* free (d, M_DEVBUF);*/
+ }
+ for (i=0; i<NCT; ++i) {
+ ct_board_t *b = adapter [i];
+ if (!b)
+ continue;
+ adapter [i] = 0;
+ free (b, M_DEVBUF);
+ }
+ splx(s);
+
+ return 0;
+}
+
+#define devsw(a) cdevsw[major((a))]
+#endif /* __FreeBSD_version < 400000 */
+#endif /* KLD_MODULE */
+
+#if __FreeBSD_version < 400000
+#ifdef KLD_MODULE
+static int ct_modevent (module_t mod, int type, void *unused)
+{
+ dev_t dev;
+ int result;
+ static int load_count = 0;
+
+ dev = makedev (CDEV_MAJOR, 0);
+ switch (type) {
+ case MOD_LOAD:
+ if (devsw(dev))
+ return (ENXIO);
+ load_count ++;
+ cdevsw_add (&dev, &ct_cdevsw, NULL);
+ timeout_handle = timeout (ct_timeout, 0, hz*5);
+ result = ct_load ();
+ return result;
+ case MOD_UNLOAD:
+ result = ct_unload ();
+ if (result)
+ return result;
+ if (devsw(dev)&&!(load_count-1)) {
+ cdevsw_add (&dev, NULL, NULL);
+ }
+ load_count --;
+ return result;
+ case MOD_SHUTDOWN:
+ break;
+ }
+ return 0;
+}
+#endif /* KLD_MODULE */
+#else /* __FreeBSD_version >= 400000 */
+static int ct_modevent (module_t mod, int type, void *unused)
+{
+ dev_t dev;
+ static int load_count = 0;
+ struct cdevsw *cdsw;
+
+ dev = udev2dev (makeudev(CDEV_MAJOR, 0));
+ switch (type) {
+ case MOD_LOAD:
+ if ((cdsw = devsw (dev)) && cdsw->d_maj == CDEV_MAJOR) {
+ printf ("Tau-ISA driver is already in system\n");
+ return (ENXIO);
+ }
+#if __FreeBSD_version >= 500000 && defined NETGRAPH
+ if (ng_newtype (&typestruct))
+ printf ("Failed to register ng_ct\n");
+#endif
+ ++load_count;
+#if __FreeBSD_version <= 500000
+ cdevsw_add (&ct_cdevsw);
+#endif
+ timeout_handle = timeout (ct_timeout, 0, hz*5);
+ break;
+ case MOD_UNLOAD:
+ if (load_count == 1) {
+ printf ("Removing device entry for Tau-ISA\n");
+#if __FreeBSD_version <= 500000
+ cdevsw_remove (&ct_cdevsw);
+#endif
+#if __FreeBSD_version >= 500000 && defined NETGRAPH
+ ng_rmtype (&typestruct);
+#endif
+ }
+ if (timeout_handle.callout)
+ untimeout (ct_timeout, 0, timeout_handle);
+ --load_count;
+ break;
+ case MOD_SHUTDOWN:
+ break;
+ }
+ return 0;
+}
+#endif /* __FreeBSD_version >= 400000 */
+
+#ifdef NETGRAPH
+static struct ng_type typestruct = {
+#if __FreeBSD_version >= 500000
+ NG_ABI_VERSION,
+#else
+ NG_VERSION,
+#endif
+ NG_CT_NODE_TYPE,
+#if __FreeBSD_version < 500000 && (defined KLD_MODULE)
+ ct_modevent,
+#else
+ NULL,
+#endif
+ ng_ct_constructor,
+ ng_ct_rcvmsg,
+ ng_ct_rmnode,
+ ng_ct_newhook,
+ NULL,
+ ng_ct_connect,
+ ng_ct_rcvdata,
+#if __FreeBSD_version < 500000
+ NULL,
+#endif
+ ng_ct_disconnect
+};
+
+#if __FreeBSD_version < 400000
+NETGRAPH_INIT_ORDERED (ct, &typestruct, SI_SUB_DRIVERS,\
+ SI_ORDER_MIDDLE + CDEV_MAJOR);
+#endif
+#endif /*NETGRAPH*/
+
+#if __FreeBSD_version >= 500000
+#ifdef NETGRAPH
+MODULE_DEPEND (ng_ct, netgraph, NG_ABI_VERSION, NG_ABI_VERSION, NG_ABI_VERSION);
+#else
+MODULE_DEPEND (ct, sppp, 1, 1, 1);
+#endif
+#ifdef KLD_MODULE
+DRIVER_MODULE (ctmod, isa, ct_isa_driver, ct_devclass, ct_modevent, NULL);
+#else
+DRIVER_MODULE (ct, isa, ct_isa_driver, ct_devclass, ct_modevent, NULL);
+#endif
+#elif __FreeBSD_version >= 400000
+#ifdef NETGRAPH
+DRIVER_MODULE(ct, isa, ct_isa_driver, ct_devclass, ng_mod_event, &typestruct);
+#else
+DRIVER_MODULE(ct, isa, ct_isa_driver, ct_devclass, ct_modevent, 0);
+#endif
+#else /* __FreeBSD_version < 400000 */
+#ifdef KLD_MODULE
+#ifndef NETGRAPH
+static moduledata_t ctmod = { "ct", ct_modevent, };
+DECLARE_MODULE (ct, ctmod, SI_SUB_DRIVERS, SI_ORDER_MIDDLE + CDEV_MAJOR);
+#endif /* !NETGRAPH */
+#else /* KLD_MODULE */
+
+/*
+ * Now for some driver initialisation.
+ * Occurs ONCE during boot (very early).
+ * This is if we are NOT a loadable module.
+ */
+static void ct_drvinit (void *unused)
+{
+ dev_t dev;
+
+ dev = makedev (CDEV_MAJOR, 0);
+ cdevsw_add (&dev, &ct_cdevsw, NULL);
+
+ /* Activate the timeout routine. */
+ timeout_handle = timeout (ct_timeout, 0, hz);
+#ifdef NETGRAPH
+#if 0
+ /* Register our node type in netgraph */
+ if (ng_newtype (&typestruct))
+ printf ("Failed to register ng_ct\n");
+#endif
+#endif
+}
+
+SYSINIT (ctdev, SI_SUB_DRIVERS, SI_ORDER_MIDDLE+CDEV_MAJOR, ct_drvinit, 0)
+#endif /* KLD_MODULE */
+#endif /* __FreeBSD_version < 400000 */
+#endif /* NCT */
diff --git a/sys/dev/ctau/lxt318.h b/sys/dev/ctau/lxt318.h
new file mode 100644
index 000000000000..f194b7bda03b
--- /dev/null
+++ b/sys/dev/ctau/lxt318.h
@@ -0,0 +1,44 @@
+/*
+ * Level One LXT318 E1 transceiver registers.
+ * Crystal CS61318 E1 Line Interface Unit registers.
+ * Crystal CS61581 T1/E1 Line Interface Unit registers.
+ *
+ * Copyright (C) 1996 Cronyx Engineering.
+ * Author: Serge Vakulenko, <vak@cronyx.ru>
+ *
+ * Copyright (C) 2003 Cronyx Engineering.
+ * Author: Roman Kurakin, <rik@cronyx.ru>
+ *
+ * This software is distributed with NO WARRANTIES, not even the implied
+ * warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Authors grant any other persons or organisations permission to use
+ * or modify this software as long as this message is kept with the software,
+ * all derivative works or modified versions.
+ *
+ * Cronyx Id: lxt318.h,v 1.2.4.4 2003/11/14 19:08:45 rik Exp $
+ * $FreeBSD$
+ */
+
+#define LX_WRITE 0x00
+#define LX_READ 0x01
+
+#define LX_CCR1 0x10
+#define LX_CCR2 0x11 /* CS61318 */
+#define LX_EQGAIN 0x12 /* CS61318 */
+#define LX_RAM 0x13 /* CS61318 */
+#define LX_CCR3 0x14 /* CS61581 */
+#define LX_DPEC 0x15 /* CS61581 */
+
+#define LX_LOS 0x01 /* loss of signal condition */
+#define LX_HDB3 0x04 /* HDB3 encoding enable */
+#define LX_RLOOP 0x20 /* remote loopback */
+#define LX_LLOOP 0x40 /* local loopback */
+#define LX_TAOS 0x80 /* transmit all ones */
+
+#define LX_RESET (LX_RLOOP | LX_LLOOP) /* reset the chip */
+
+#define LX_CCR2_LH 0x00 /* Long Haul mode */
+#define LX_CCR2_SH 0x01 /* Long Haul mode */
+
+#define LX_CCR3_E1_LH 0x60 /* Long Haul mode */
diff --git a/sys/dev/ctau/ng_ct.h b/sys/dev/ctau/ng_ct.h
new file mode 100644
index 000000000000..5fba87812cda
--- /dev/null
+++ b/sys/dev/ctau/ng_ct.h
@@ -0,0 +1,31 @@
+/*
+ * Defines for Cronyx-Tau adapter driver.
+ *
+ * Copyright (C) 1999-2004 Cronyx Engineering.
+ * Author: Kurakin Roman, <rik@cronyx.ru>
+ *
+ * This software is distributed with NO WARRANTIES, not even the implied
+ * warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Authors grant any other persons or organisations a permission to use,
+ * modify and redistribute this software in source and binary forms,
+ * as long as this message is kept with the software, all derivative
+ * works or modified versions.
+ *
+ * Cronyx Id: ng_ct.h,v 1.1.2.3 2004/01/27 14:39:11 rik Exp $
+ * $FreeBSD$
+ */
+
+#ifdef NETGRAPH
+
+#ifndef _CT_NETGRAPH_H_
+#define _CT_NETGRAPH_H_
+
+#define NG_CT_NODE_TYPE "ct"
+#define NGM_CT_COOKIE 942835777
+#define NG_CT_HOOK_RAW "rawdata"
+#define NG_CT_HOOK_DEBUG "debug"
+
+#endif /* _CT_NETGRAPH_H_ */
+
+#endif /* NETGRAPH */