ixgbe(4): Fix enabling/disabling and reconfiguration of queues

- Wrong order of casting and bit shift caused that enabling and disabling
  queues didn't work properly for queues number larger than 32. Use literals
  with right suffix instead.

- TX ring tail address was not updated during reinitiailzation of TX
  structures. It could block sending traffic.

- Also remove unused variables 'eims' and 'active_queues'.

Submitted by:	Krzysztof Galazka <krzysztof.galazka@intel.com>
Reviewed by:	erj@
Sponsored by:	Intel Corporation
Differential Revision:	https://reviews.freebsd.org/D20826

(cherry picked from commit 2dc2d580354e95491a033fa9e21c8ef0cbd9bc42)

3 files changed, 5 insertions, 10 deletions

diff --git a/sys/dev/ixgbe/if_ix.c b/sys/dev/ixgbe/if_ix.c
index d69a8ef80ef6..fa52b58ac1bd 100644
--- a/sys/dev/ixgbe/if_ix.c
+++ b/sys/dev/ixgbe/if_ix.c
@@ -425,7 +425,6 @@ ixgbe_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs,
 		    i);
 
 		txr->sc = que->sc = sc;
-		sc->active_queues |= (u64)1 << txr->me;
 
 		/* Allocate report status array */
 		txr->tx_rsq = (qidx_t *)malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_IXGBE, M_NOWAIT | M_ZERO);
@@ -796,6 +795,8 @@ ixgbe_initialize_transmit_units(if_ctx_t ctx)
 		IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
 
 		/* Cache the tail address */
+		txr->tail = IXGBE_TDT(txr->me);
+
 		txr->tx_rs_cidx = txr->tx_rs_pidx;
 		txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1;
 		for (int k = 0; k < scctx->isc_ntxd[0]; k++)
@@ -2052,7 +2053,6 @@ ixgbe_if_msix_intr_assign(if_ctx_t ctx, int msix)
 		}
 
 		rx_que->msix = vector;
-		sc->active_queues |= (u64)(1 << rx_que->msix);
 		if (sc->feat_en & IXGBE_FEATURE_RSS) {
 			/*
 			 * The queue ID is used as the RSS layer bucket ID.
@@ -3740,7 +3740,7 @@ ixgbe_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid)
 	struct ixgbe_softc     *sc = iflib_get_softc(ctx);
 	struct ix_rx_queue *que = &sc->rx_queues[rxqid];
 
-	ixgbe_enable_queue(sc, que->rxr.me);
+	ixgbe_enable_queue(sc, que->msix);
 
 	return (0);
 } /* ixgbe_if_rx_queue_intr_enable */
@@ -3752,7 +3752,7 @@ static void
 ixgbe_enable_queue(struct ixgbe_softc *sc, u32 vector)
 {
 	struct ixgbe_hw *hw = &sc->hw;
-	u64             queue = (u64)(1 << vector);
+	u64             queue = 1ULL << vector;
 	u32             mask;
 
 	if (hw->mac.type == ixgbe_mac_82598EB) {
@@ -3775,7 +3775,7 @@ static void
 ixgbe_disable_queue(struct ixgbe_softc *sc, u32 vector)
 {
 	struct ixgbe_hw *hw = &sc->hw;
-	u64             queue = (u64)(1 << vector);
+	u64             queue = 1ULL << vector;
 	u32             mask;
 
 	if (hw->mac.type == ixgbe_mac_82598EB) {
diff --git a/sys/dev/ixgbe/if_ixv.c b/sys/dev/ixgbe/if_ixv.c
index 25654ff60950..3eb7a1f5a1b7 100644
--- a/sys/dev/ixgbe/if_ixv.c
+++ b/sys/dev/ixgbe/if_ixv.c
@@ -271,7 +271,6 @@ ixv_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs,
 
 		txr->me = i;
 		txr->sc =  que->sc = sc;
-		sc->active_queues |= (u64)1 << txr->me;
 
 		/* Allocate report status array */
 		if (!(txr->tx_rsq = (qidx_t *)malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) {
@@ -1039,8 +1038,6 @@ ixv_if_msix_intr_assign(if_ctx_t ctx, int msix)
 		}
 
 		rx_que->msix = vector;
-		sc->active_queues |= (u64)(1 << rx_que->msix);
-
 	}
 
 	for (int i = 0; i < sc->num_tx_queues; i++) {
diff --git a/sys/dev/ixgbe/ixgbe.h b/sys/dev/ixgbe/ixgbe.h
index 45f5b88fd1f1..00b01f71c996 100644
--- a/sys/dev/ixgbe/ixgbe.h
+++ b/sys/dev/ixgbe/ixgbe.h
@@ -337,7 +337,6 @@ struct rx_ring {
 struct ix_rx_queue {
 	struct ixgbe_softc	*sc;
 	u32			msix;           /* This queue's MSIX vector */
-	u32			eims;           /* This queue's EIMS bit */
 	u32			eitr_setting;
 	struct resource		*res;
 	void			*tag;
@@ -440,7 +439,6 @@ struct ixgbe_softc {
 	 */
 	struct ix_tx_queue	*tx_queues;
 	struct ix_rx_queue	*rx_queues;
-	u64			active_queues;
 
 	/* Multicast array memory */
 	struct ixgbe_mc_addr    *mta;