5 files changed, 1397 insertions, 454 deletions

diff --git a/sys/dev/cxgbe/common/t4_hw.c b/sys/dev/cxgbe/common/t4_hw.c
index 65292486cbc8..494f83a47135 100644
--- a/sys/dev/cxgbe/common/t4_hw.c
+++ b/sys/dev/cxgbe/common/t4_hw.c
@@ -3282,7 +3282,9 @@ void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size)
 		0x477d4, 0x477fc,
 		0x48000, 0x48004,
 		0x48018, 0x4801c,
-		0x49304, 0x493f0,
+		0x49304, 0x49320,
+		0x4932c, 0x4932c,
+		0x49334, 0x493f0,
 		0x49400, 0x49410,
 		0x49460, 0x494f4,
 		0x50000, 0x50084,
@@ -3305,7 +3307,9 @@ void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size)
 		0x515f0, 0x515f4,
 		0x58000, 0x58004,
 		0x58018, 0x5801c,
-		0x59304, 0x593f0,
+		0x59304, 0x59320,
+		0x5932c, 0x5932c,
+		0x59334, 0x593f0,
 		0x59400, 0x59410,
 		0x59460, 0x594f4,
 	};
@@ -6177,11 +6181,6 @@ static bool mem_intr_handler(struct adapter *adap, int idx, int flags)
 			ii.cause_reg = MC_T7_REG(A_MC_P_DDRCTL_INT_CAUSE, i);
 			ii.enable_reg = MC_T7_REG(A_MC_P_DDRCTL_INT_ENABLE, i);
 			fatal |= t4_handle_intr(adap, &ii, 0, flags);
-
-			snprintf(rname, sizeof(rname), "MC%u_ECC_UE_INT_CAUSE", i);
-			ii.cause_reg = MC_T7_REG(A_MC_P_ECC_UE_INT_CAUSE, i);
-			ii.enable_reg = MC_T7_REG(A_MC_P_ECC_UE_INT_ENABLE, i);
-			fatal |= t4_handle_intr(adap, &ii, 0, flags);
 		}
 		break;
 	}
diff --git a/sys/dev/cxgbe/common/t4_regs.h b/sys/dev/cxgbe/common/t4_regs.h
index 51f150443261..09d0d4aa2c08 100644
--- a/sys/dev/cxgbe/common/t4_regs.h
+++ b/sys/dev/cxgbe/common/t4_regs.h
@@ -27,11 +27,11 @@
  */
 
 /* This file is automatically generated --- changes will be lost */
-/* Generation Date : Tue Oct 28 05:23:45 PM IST 2025 */
+/* Generation Date : Thu Dec 11 08:42:50 PM IST 2025 */
 /* Directory name: t4_reg.txt, Date: Not specified */
-/* Directory name: t5_reg.txt, Changeset: 6945:54ba4ba7ee8b */
+/* Directory name: t5_reg.txt, Changeset: 6946:9d3868c42009 */
 /* Directory name: t6_reg.txt, Changeset: 4277:9c165d0f4899 */
-/* Directory name: t7_sw_reg.txt, Changeset: 5946:0b60ff298e7d */
+/* Directory name: t7_sw_reg.txt, Changeset: 5950:7c934148528c */
 
 #define MYPF_BASE 0x1b000
 #define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr))
@@ -6195,15 +6195,15 @@
 
 #define A_PCIE_PF_INT_CFG 0x3140
 
-#define S_T7_VECNUM    12
-#define M_T7_VECNUM    0x7ffU
-#define V_T7_VECNUM(x) ((x) << S_T7_VECNUM)
-#define G_T7_VECNUM(x) (((x) >> S_T7_VECNUM) & M_T7_VECNUM)
+#define S_T7_PF_INT_VECNUM    12
+#define M_T7_PF_INT_VECNUM    0x7ffU
+#define V_T7_PF_INT_VECNUM(x) ((x) << S_T7_PF_INT_VECNUM)
+#define G_T7_PF_INT_VECNUM(x) (((x) >> S_T7_PF_INT_VECNUM) & M_T7_PF_INT_VECNUM)
 
-#define S_T7_VECBASE    0
-#define M_T7_VECBASE    0xfffU
-#define V_T7_VECBASE(x) ((x) << S_T7_VECBASE)
-#define G_T7_VECBASE(x) (((x) >> S_T7_VECBASE) & M_T7_VECBASE)
+#define S_T7_PF_INT_VECBASE    0
+#define M_T7_PF_INT_VECBASE    0xfffU
+#define V_T7_PF_INT_VECBASE(x) ((x) << S_T7_PF_INT_VECBASE)
+#define G_T7_PF_INT_VECBASE(x) (((x) >> S_T7_PF_INT_VECBASE) & M_T7_PF_INT_VECBASE)
 
 #define A_PCIE_PF_INT_CFG2 0x3144
 #define A_PCIE_VF_INT_CFG 0x3180
@@ -10636,6 +10636,12 @@
 #define G_VFID_PCIE(x) (((x) >> S_VFID_PCIE) & M_VFID_PCIE)
 
 #define A_PCIE_VF_INT_INDIR_DATA 0x5c48
+
+#define S_T7_VECBASE    0
+#define M_T7_VECBASE    0xfffU
+#define V_T7_VECBASE(x) ((x) << S_T7_VECBASE)
+#define G_T7_VECBASE(x) (((x) >> S_T7_VECBASE) & M_T7_VECBASE)
+
 #define A_PCIE_VF_256_INT_CFG2 0x5c4c
 #define A_PCIE_VF_MSI_EN_4 0x5e50
 #define A_PCIE_VF_MSI_EN_5 0x5e54
@@ -17723,6 +17729,22 @@
 #define V_GPIO20_PE_EN(x) ((x) << S_GPIO20_PE_EN)
 #define F_GPIO20_PE_EN    V_GPIO20_PE_EN(1U)
 
+#define S_T7_GPIO19_PE_EN    19
+#define V_T7_GPIO19_PE_EN(x) ((x) << S_T7_GPIO19_PE_EN)
+#define F_T7_GPIO19_PE_EN    V_T7_GPIO19_PE_EN(1U)
+
+#define S_T7_GPIO18_PE_EN    18
+#define V_T7_GPIO18_PE_EN(x) ((x) << S_T7_GPIO18_PE_EN)
+#define F_T7_GPIO18_PE_EN    V_T7_GPIO18_PE_EN(1U)
+
+#define S_T7_GPIO17_PE_EN    17
+#define V_T7_GPIO17_PE_EN(x) ((x) << S_T7_GPIO17_PE_EN)
+#define F_T7_GPIO17_PE_EN    V_T7_GPIO17_PE_EN(1U)
+
+#define S_T7_GPIO16_PE_EN    16
+#define V_T7_GPIO16_PE_EN(x) ((x) << S_T7_GPIO16_PE_EN)
+#define F_T7_GPIO16_PE_EN    V_T7_GPIO16_PE_EN(1U)
+
 #define A_DBG_PVT_REG_THRESHOLD 0x611c
 
 #define S_PVT_CALIBRATION_DONE    8
@@ -17859,6 +17881,22 @@
 #define V_GPIO20_PS_EN(x) ((x) << S_GPIO20_PS_EN)
 #define F_GPIO20_PS_EN    V_GPIO20_PS_EN(1U)
 
+#define S_T7_GPIO19_PS_EN    19
+#define V_T7_GPIO19_PS_EN(x) ((x) << S_T7_GPIO19_PS_EN)
+#define F_T7_GPIO19_PS_EN    V_T7_GPIO19_PS_EN(1U)
+
+#define S_T7_GPIO18_PS_EN    18
+#define V_T7_GPIO18_PS_EN(x) ((x) << S_T7_GPIO18_PS_EN)
+#define F_T7_GPIO18_PS_EN    V_T7_GPIO18_PS_EN(1U)
+
+#define S_T7_GPIO17_PS_EN    17
+#define V_T7_GPIO17_PS_EN(x) ((x) << S_T7_GPIO17_PS_EN)
+#define F_T7_GPIO17_PS_EN    V_T7_GPIO17_PS_EN(1U)
+
+#define S_T7_GPIO16_PS_EN    16
+#define V_T7_GPIO16_PS_EN(x) ((x) << S_T7_GPIO16_PS_EN)
+#define F_T7_GPIO16_PS_EN    V_T7_GPIO16_PS_EN(1U)
+
 #define A_DBG_PVT_REG_IN_TERMP 0x6120
 
 #define S_REG_IN_TERMP_B    4
@@ -21825,10 +21863,6 @@
 #define V_FUTURE_DEXPANSION_WTS(x) ((x) << S_FUTURE_DEXPANSION_WTS)
 #define G_FUTURE_DEXPANSION_WTS(x) (((x) >> S_FUTURE_DEXPANSION_WTS) & M_FUTURE_DEXPANSION_WTS)
 
-#define S_T7_FUTURE_CEXPANSION_WTS    31
-#define V_T7_FUTURE_CEXPANSION_WTS(x) ((x) << S_T7_FUTURE_CEXPANSION_WTS)
-#define F_T7_FUTURE_CEXPANSION_WTS    V_T7_FUTURE_CEXPANSION_WTS(1U)
-
 #define S_CL14_WR_CMD_TO_ERROR    30
 #define V_CL14_WR_CMD_TO_ERROR(x) ((x) << S_CL14_WR_CMD_TO_ERROR)
 #define F_CL14_WR_CMD_TO_ERROR    V_CL14_WR_CMD_TO_ERROR(1U)
@@ -21837,10 +21871,6 @@
 #define V_CL13_WR_CMD_TO_ERROR(x) ((x) << S_CL13_WR_CMD_TO_ERROR)
 #define F_CL13_WR_CMD_TO_ERROR    V_CL13_WR_CMD_TO_ERROR(1U)
 
-#define S_T7_FUTURE_DEXPANSION_WTS    15
-#define V_T7_FUTURE_DEXPANSION_WTS(x) ((x) << S_T7_FUTURE_DEXPANSION_WTS)
-#define F_T7_FUTURE_DEXPANSION_WTS    V_T7_FUTURE_DEXPANSION_WTS(1U)
-
 #define S_CL14_WR_DATA_TO_ERROR    14
 #define V_CL14_WR_DATA_TO_ERROR(x) ((x) << S_CL14_WR_DATA_TO_ERROR)
 #define F_CL14_WR_DATA_TO_ERROR    V_CL14_WR_DATA_TO_ERROR(1U)
@@ -21965,10 +21995,6 @@
 #define V_FUTURE_DEXPANSION_RTE(x) ((x) << S_FUTURE_DEXPANSION_RTE)
 #define G_FUTURE_DEXPANSION_RTE(x) (((x) >> S_FUTURE_DEXPANSION_RTE) & M_FUTURE_DEXPANSION_RTE)
 
-#define S_T7_FUTURE_CEXPANSION_RTE    31
-#define V_T7_FUTURE_CEXPANSION_RTE(x) ((x) << S_T7_FUTURE_CEXPANSION_RTE)
-#define F_T7_FUTURE_CEXPANSION_RTE    V_T7_FUTURE_CEXPANSION_RTE(1U)
-
 #define S_CL14_RD_CMD_TO_EN    30
 #define V_CL14_RD_CMD_TO_EN(x) ((x) << S_CL14_RD_CMD_TO_EN)
 #define F_CL14_RD_CMD_TO_EN    V_CL14_RD_CMD_TO_EN(1U)
@@ -21977,10 +22003,6 @@
 #define V_CL13_RD_CMD_TO_EN(x) ((x) << S_CL13_RD_CMD_TO_EN)
 #define F_CL13_RD_CMD_TO_EN    V_CL13_RD_CMD_TO_EN(1U)
 
-#define S_T7_FUTURE_DEXPANSION_RTE    15
-#define V_T7_FUTURE_DEXPANSION_RTE(x) ((x) << S_T7_FUTURE_DEXPANSION_RTE)
-#define F_T7_FUTURE_DEXPANSION_RTE    V_T7_FUTURE_DEXPANSION_RTE(1U)
-
 #define S_CL14_RD_DATA_TO_EN    14
 #define V_CL14_RD_DATA_TO_EN(x) ((x) << S_CL14_RD_DATA_TO_EN)
 #define F_CL14_RD_DATA_TO_EN    V_CL14_RD_DATA_TO_EN(1U)
@@ -22105,10 +22127,6 @@
 #define V_FUTURE_DEXPANSION_RTS(x) ((x) << S_FUTURE_DEXPANSION_RTS)
 #define G_FUTURE_DEXPANSION_RTS(x) (((x) >> S_FUTURE_DEXPANSION_RTS) & M_FUTURE_DEXPANSION_RTS)
 
-#define S_T7_FUTURE_CEXPANSION_RTS    31
-#define V_T7_FUTURE_CEXPANSION_RTS(x) ((x) << S_T7_FUTURE_CEXPANSION_RTS)
-#define F_T7_FUTURE_CEXPANSION_RTS    V_T7_FUTURE_CEXPANSION_RTS(1U)
-
 #define S_CL14_RD_CMD_TO_ERROR    30
 #define V_CL14_RD_CMD_TO_ERROR(x) ((x) << S_CL14_RD_CMD_TO_ERROR)
 #define F_CL14_RD_CMD_TO_ERROR    V_CL14_RD_CMD_TO_ERROR(1U)
@@ -22117,10 +22135,9 @@
 #define V_CL13_RD_CMD_TO_ERROR(x) ((x) << S_CL13_RD_CMD_TO_ERROR)
 #define F_CL13_RD_CMD_TO_ERROR    V_CL13_RD_CMD_TO_ERROR(1U)
 
-#define S_T7_FUTURE_DEXPANSION_RTS    14
-#define M_T7_FUTURE_DEXPANSION_RTS    0x3U
-#define V_T7_FUTURE_DEXPANSION_RTS(x) ((x) << S_T7_FUTURE_DEXPANSION_RTS)
-#define G_T7_FUTURE_DEXPANSION_RTS(x) (((x) >> S_T7_FUTURE_DEXPANSION_RTS) & M_T7_FUTURE_DEXPANSION_RTS)
+#define S_CL14_RD_DATA_TO_ERROR    14
+#define V_CL14_RD_DATA_TO_ERROR(x) ((x) << S_CL14_RD_DATA_TO_ERROR)
+#define F_CL14_RD_DATA_TO_ERROR    V_CL14_RD_DATA_TO_ERROR(1U)
 
 #define S_CL13_RD_DATA_TO_ERROR    13
 #define V_CL13_RD_DATA_TO_ERROR(x) ((x) << S_CL13_RD_DATA_TO_ERROR)
@@ -22224,10 +22241,9 @@
 #define V_FUTURE_DEXPANSION_IPE(x) ((x) << S_FUTURE_DEXPANSION_IPE)
 #define G_FUTURE_DEXPANSION_IPE(x) (((x) >> S_FUTURE_DEXPANSION_IPE) & M_FUTURE_DEXPANSION_IPE)
 
-#define S_T7_FUTURE_DEXPANSION_IPE    14
-#define M_T7_FUTURE_DEXPANSION_IPE    0x3ffffU
-#define V_T7_FUTURE_DEXPANSION_IPE(x) ((x) << S_T7_FUTURE_DEXPANSION_IPE)
-#define G_T7_FUTURE_DEXPANSION_IPE(x) (((x) >> S_T7_FUTURE_DEXPANSION_IPE) & M_T7_FUTURE_DEXPANSION_IPE)
+#define S_CL14_IF_PAR_EN    14
+#define V_CL14_IF_PAR_EN(x) ((x) << S_CL14_IF_PAR_EN)
+#define F_CL14_IF_PAR_EN    V_CL14_IF_PAR_EN(1U)
 
 #define S_CL13_IF_PAR_EN    13
 #define V_CL13_IF_PAR_EN(x) ((x) << S_CL13_IF_PAR_EN)
@@ -22292,10 +22308,9 @@
 #define V_FUTURE_DEXPANSION_IPS(x) ((x) << S_FUTURE_DEXPANSION_IPS)
 #define G_FUTURE_DEXPANSION_IPS(x) (((x) >> S_FUTURE_DEXPANSION_IPS) & M_FUTURE_DEXPANSION_IPS)
 
-#define S_T7_FUTURE_DEXPANSION_IPS    14
-#define M_T7_FUTURE_DEXPANSION_IPS    0x3ffffU
-#define V_T7_FUTURE_DEXPANSION_IPS(x) ((x) << S_T7_FUTURE_DEXPANSION_IPS)
-#define G_T7_FUTURE_DEXPANSION_IPS(x) (((x) >> S_T7_FUTURE_DEXPANSION_IPS) & M_T7_FUTURE_DEXPANSION_IPS)
+#define S_CL14_IF_PAR_ERROR    14
+#define V_CL14_IF_PAR_ERROR(x) ((x) << S_CL14_IF_PAR_ERROR)
+#define F_CL14_IF_PAR_ERROR    V_CL14_IF_PAR_ERROR(1U)
 
 #define S_CL13_IF_PAR_ERROR    13
 #define V_CL13_IF_PAR_ERROR(x) ((x) << S_CL13_IF_PAR_ERROR)
@@ -39030,21 +39045,21 @@
 #define A_PM_TX_CH1_OSPI_DEFICIT_THRSHLD 0x10028
 #define A_PM_TX_PERR_ENABLE 0x10028
 
-#define S_T7_1_OSPI_OVERFLOW3    23
-#define V_T7_1_OSPI_OVERFLOW3(x) ((x) << S_T7_1_OSPI_OVERFLOW3)
-#define F_T7_1_OSPI_OVERFLOW3    V_T7_1_OSPI_OVERFLOW3(1U)
+#define S_OSPI_OVERFLOW3_TX    23
+#define V_OSPI_OVERFLOW3_TX(x) ((x) << S_OSPI_OVERFLOW3_TX)
+#define F_OSPI_OVERFLOW3_TX    V_OSPI_OVERFLOW3_TX(1U)
 
-#define S_T7_1_OSPI_OVERFLOW2    22
-#define V_T7_1_OSPI_OVERFLOW2(x) ((x) << S_T7_1_OSPI_OVERFLOW2)
-#define F_T7_1_OSPI_OVERFLOW2    V_T7_1_OSPI_OVERFLOW2(1U)
+#define S_OSPI_OVERFLOW2_TX    22
+#define V_OSPI_OVERFLOW2_TX(x) ((x) << S_OSPI_OVERFLOW2_TX)
+#define F_OSPI_OVERFLOW2_TX    V_OSPI_OVERFLOW2_TX(1U)
 
-#define S_T7_1_OSPI_OVERFLOW1    21
-#define V_T7_1_OSPI_OVERFLOW1(x) ((x) << S_T7_1_OSPI_OVERFLOW1)
-#define F_T7_1_OSPI_OVERFLOW1    V_T7_1_OSPI_OVERFLOW1(1U)
+#define S_OSPI_OVERFLOW1_TX    21
+#define V_OSPI_OVERFLOW1_TX(x) ((x) << S_OSPI_OVERFLOW1_TX)
+#define F_OSPI_OVERFLOW1_TX    V_OSPI_OVERFLOW1_TX(1U)
 
-#define S_T7_1_OSPI_OVERFLOW0    20
-#define V_T7_1_OSPI_OVERFLOW0(x) ((x) << S_T7_1_OSPI_OVERFLOW0)
-#define F_T7_1_OSPI_OVERFLOW0    V_T7_1_OSPI_OVERFLOW0(1U)
+#define S_OSPI_OVERFLOW0_TX    20
+#define V_OSPI_OVERFLOW0_TX(x) ((x) << S_OSPI_OVERFLOW0_TX)
+#define F_OSPI_OVERFLOW0_TX    V_OSPI_OVERFLOW0_TX(1U)
 
 #define S_T7_BUNDLE_LEN_OVFL_EN    18
 #define V_T7_BUNDLE_LEN_OVFL_EN(x) ((x) << S_T7_BUNDLE_LEN_OVFL_EN)
@@ -41390,15 +41405,65 @@
 #define V_T7_BUBBLE(x) ((x) << S_T7_BUBBLE)
 #define F_T7_BUBBLE    V_T7_BUBBLE(1U)
 
-#define S_TXTOKENFIFO    15
-#define M_TXTOKENFIFO    0x3ffU
-#define V_TXTOKENFIFO(x) ((x) << S_TXTOKENFIFO)
-#define G_TXTOKENFIFO(x) (((x) >> S_TXTOKENFIFO) & M_TXTOKENFIFO)
+#define S_TX_TF_FIFO_PERR    19
+#define V_TX_TF_FIFO_PERR(x) ((x) << S_TX_TF_FIFO_PERR)
+#define F_TX_TF_FIFO_PERR    V_TX_TF_FIFO_PERR(1U)
 
-#define S_PERR_TP2MPS_TFIFO    13
-#define M_PERR_TP2MPS_TFIFO    0x3U
-#define V_PERR_TP2MPS_TFIFO(x) ((x) << S_PERR_TP2MPS_TFIFO)
-#define G_PERR_TP2MPS_TFIFO(x) (((x) >> S_PERR_TP2MPS_TFIFO) & M_PERR_TP2MPS_TFIFO)
+#define S_TX_FIFO_PERR    18
+#define V_TX_FIFO_PERR(x) ((x) << S_TX_FIFO_PERR)
+#define F_TX_FIFO_PERR    V_TX_FIFO_PERR(1U)
+
+#define S_NON_IPSEC_TX_FIFO3_PERR    17
+#define V_NON_IPSEC_TX_FIFO3_PERR(x) ((x) << S_NON_IPSEC_TX_FIFO3_PERR)
+#define F_NON_IPSEC_TX_FIFO3_PERR    V_NON_IPSEC_TX_FIFO3_PERR(1U)
+
+#define S_NON_IPSEC_TX_FIFO2_PERR    16
+#define V_NON_IPSEC_TX_FIFO2_PERR(x) ((x) << S_NON_IPSEC_TX_FIFO2_PERR)
+#define F_NON_IPSEC_TX_FIFO2_PERR    V_NON_IPSEC_TX_FIFO2_PERR(1U)
+
+#define S_NON_IPSEC_TX_FIFO1_PERR    15
+#define V_NON_IPSEC_TX_FIFO1_PERR(x) ((x) << S_NON_IPSEC_TX_FIFO1_PERR)
+#define F_NON_IPSEC_TX_FIFO1_PERR    V_NON_IPSEC_TX_FIFO1_PERR(1U)
+
+#define S_NON_IPSEC_TX_FIFO0_PERR    14
+#define V_NON_IPSEC_TX_FIFO0_PERR(x) ((x) << S_NON_IPSEC_TX_FIFO0_PERR)
+#define F_NON_IPSEC_TX_FIFO0_PERR    V_NON_IPSEC_TX_FIFO0_PERR(1U)
+
+#define S_TP2MPS_TX0    13
+#define V_TP2MPS_TX0(x) ((x) << S_TP2MPS_TX0)
+#define F_TP2MPS_TX0    V_TP2MPS_TX0(1U)
+
+#define S_CRYPTO2MPS_TX0    12
+#define V_CRYPTO2MPS_TX0(x) ((x) << S_CRYPTO2MPS_TX0)
+#define F_CRYPTO2MPS_TX0    V_CRYPTO2MPS_TX0(1U)
+
+#define S_TP2MPS_TX1    11
+#define V_TP2MPS_TX1(x) ((x) << S_TP2MPS_TX1)
+#define F_TP2MPS_TX1    V_TP2MPS_TX1(1U)
+
+#define S_CRYPTO2MPS_TX1    10
+#define V_CRYPTO2MPS_TX1(x) ((x) << S_CRYPTO2MPS_TX1)
+#define F_CRYPTO2MPS_TX1    V_CRYPTO2MPS_TX1(1U)
+
+#define S_TP2MPS_TX2    9
+#define V_TP2MPS_TX2(x) ((x) << S_TP2MPS_TX2)
+#define F_TP2MPS_TX2    V_TP2MPS_TX2(1U)
+
+#define S_CRYPTO2MPS_TX2    8
+#define V_CRYPTO2MPS_TX2(x) ((x) << S_CRYPTO2MPS_TX2)
+#define F_CRYPTO2MPS_TX2    V_CRYPTO2MPS_TX2(1U)
+
+#define S_TP2MPS_TX3    7
+#define V_TP2MPS_TX3(x) ((x) << S_TP2MPS_TX3)
+#define F_TP2MPS_TX3    V_TP2MPS_TX3(1U)
+
+#define S_CRYPTO2MPS_TX3    6
+#define V_CRYPTO2MPS_TX3(x) ((x) << S_CRYPTO2MPS_TX3)
+#define F_CRYPTO2MPS_TX3    V_CRYPTO2MPS_TX3(1U)
+
+#define S_NCSI2MPS    5
+#define V_NCSI2MPS(x) ((x) << S_NCSI2MPS)
+#define F_NCSI2MPS    V_NCSI2MPS(1U)
 
 #define A_MPS_TX_INT_CAUSE 0x9408
 #define A_MPS_TX_NCSI2MPS_CNT 0x940c
@@ -41420,6 +41485,16 @@
 #define V_BUBBLEERRINT(x) ((x) << S_BUBBLEERRINT)
 #define F_BUBBLEERRINT    V_BUBBLEERRINT(1U)
 
+#define S_TXTOKENFIFO    15
+#define M_TXTOKENFIFO    0x3ffU
+#define V_TXTOKENFIFO(x) ((x) << S_TXTOKENFIFO)
+#define G_TXTOKENFIFO(x) (((x) >> S_TXTOKENFIFO) & M_TXTOKENFIFO)
+
+#define S_PERR_TP2MPS_TFIFO    13
+#define M_PERR_TP2MPS_TFIFO    0x3U
+#define V_PERR_TP2MPS_TFIFO(x) ((x) << S_PERR_TP2MPS_TFIFO)
+#define G_PERR_TP2MPS_TFIFO(x) (((x) >> S_PERR_TP2MPS_TFIFO) & M_PERR_TP2MPS_TFIFO)
+
 #define A_MPS_TX_PERR_INJECT 0x9414
 
 #define S_MPSTXMEMSEL    1
@@ -42174,7 +42249,45 @@
 
 #define A_MPS_TX_DBG_CNT 0x947c
 #define A_MPS_TX_INT2_ENABLE 0x9498
+
+#define S_T7_TX_FIFO_PERR    4
+#define V_T7_TX_FIFO_PERR(x) ((x) << S_T7_TX_FIFO_PERR)
+#define F_T7_TX_FIFO_PERR    V_T7_TX_FIFO_PERR(1U)
+
+#define S_NON_IPSEC_TX_FIFO3    3
+#define V_NON_IPSEC_TX_FIFO3(x) ((x) << S_NON_IPSEC_TX_FIFO3)
+#define F_NON_IPSEC_TX_FIFO3    V_NON_IPSEC_TX_FIFO3(1U)
+
+#define S_NON_IPSEC_TX_FIFO2    2
+#define V_NON_IPSEC_TX_FIFO2(x) ((x) << S_NON_IPSEC_TX_FIFO2)
+#define F_NON_IPSEC_TX_FIFO2    V_NON_IPSEC_TX_FIFO2(1U)
+
+#define S_NON_IPSEC_TX_FIFO1    1
+#define V_NON_IPSEC_TX_FIFO1(x) ((x) << S_NON_IPSEC_TX_FIFO1)
+#define F_NON_IPSEC_TX_FIFO1    V_NON_IPSEC_TX_FIFO1(1U)
+
+#define S_NON_IPSEC_TX_FIFO0    0
+#define V_NON_IPSEC_TX_FIFO0(x) ((x) << S_NON_IPSEC_TX_FIFO0)
+#define F_NON_IPSEC_TX_FIFO0    V_NON_IPSEC_TX_FIFO0(1U)
+
 #define A_MPS_TX_INT2_CAUSE 0x949c
+
+#define S_T7_NON_IPSEC_TX_FIFO3_PERR    3
+#define V_T7_NON_IPSEC_TX_FIFO3_PERR(x) ((x) << S_T7_NON_IPSEC_TX_FIFO3_PERR)
+#define F_T7_NON_IPSEC_TX_FIFO3_PERR    V_T7_NON_IPSEC_TX_FIFO3_PERR(1U)
+
+#define S_T7_NON_IPSEC_TX_FIFO2_PERR    2
+#define V_T7_NON_IPSEC_TX_FIFO2_PERR(x) ((x) << S_T7_NON_IPSEC_TX_FIFO2_PERR)
+#define F_T7_NON_IPSEC_TX_FIFO2_PERR    V_T7_NON_IPSEC_TX_FIFO2_PERR(1U)
+
+#define S_T7_NON_IPSEC_TX_FIFO1_PERR    1
+#define V_T7_NON_IPSEC_TX_FIFO1_PERR(x) ((x) << S_T7_NON_IPSEC_TX_FIFO1_PERR)
+#define F_T7_NON_IPSEC_TX_FIFO1_PERR    V_T7_NON_IPSEC_TX_FIFO1_PERR(1U)
+
+#define S_T7_NON_IPSEC_TX_FIFO0_PERR    0
+#define V_T7_NON_IPSEC_TX_FIFO0_PERR(x) ((x) << S_T7_NON_IPSEC_TX_FIFO0_PERR)
+#define F_T7_NON_IPSEC_TX_FIFO0_PERR    V_T7_NON_IPSEC_TX_FIFO0_PERR(1U)
+
 #define A_MPS_TX_PERR2_ENABLE 0x94a0
 #define A_MPS_TX_INT3_ENABLE 0x94a4
 #define A_MPS_TX_INT3_CAUSE 0x94a8
@@ -42307,6 +42420,12 @@
 #define G_T5_TXPORT(x) (((x) >> S_T5_TXPORT) & M_T5_TXPORT)
 
 #define A_MPS_STAT_PERR_INT_CAUSE_SRAM 0x9614
+
+#define S_T5_RXPP    29
+#define M_T5_RXPP    0x3U
+#define V_T5_RXPP(x) ((x) << S_T5_RXPP)
+#define G_T5_RXPP(x) (((x) >> S_T5_RXPP) & M_T5_RXPP)
+
 #define A_MPS_STAT_PERR_ENABLE_SRAM 0x9618
 #define A_MPS_STAT_PERR_INT_ENABLE_TX_FIFO 0x961c
 
@@ -42429,6 +42548,26 @@
 #define V_T5_TXVF(x) ((x) << S_T5_TXVF)
 #define G_T5_TXVF(x) (((x) >> S_T5_TXVF) & M_T5_TXVF)
 
+#define S_RXVF_CERR    12
+#define M_RXVF_CERR    0xfU
+#define V_RXVF_CERR(x) ((x) << S_RXVF_CERR)
+#define G_RXVF_CERR(x) (((x) >> S_RXVF_CERR) & M_RXVF_CERR)
+
+#define S_TXVF_CERR    8
+#define M_TXVF_CERR    0xfU
+#define V_TXVF_CERR(x) ((x) << S_TXVF_CERR)
+#define G_TXVF_CERR(x) (((x) >> S_TXVF_CERR) & M_TXVF_CERR)
+
+#define S_RXVF_PERR    5
+#define M_RXVF_PERR    0x7U
+#define V_RXVF_PERR(x) ((x) << S_RXVF_PERR)
+#define G_RXVF_PERR(x) (((x) >> S_RXVF_PERR) & M_RXVF_PERR)
+
+#define S_TXVF_PERR    0
+#define M_TXVF_PERR    0x1fU
+#define V_TXVF_PERR(x) ((x) << S_TXVF_PERR)
+#define G_TXVF_PERR(x) (((x) >> S_TXVF_PERR) & M_TXVF_PERR)
+
 #define A_MPS_STAT_PERR_INT_CAUSE_SRAM1 0x96c4
 #define A_MPS_STAT_PERR_ENABLE_SRAM1 0x96c8
 #define A_MPS_STAT_STOP_UPD_BG 0x96cc
@@ -42641,6 +42780,10 @@
 #define V_FILTMEM(x) ((x) << S_FILTMEM)
 #define G_FILTMEM(x) (((x) >> S_FILTMEM) & M_FILTMEM)
 
+#define S_T7_TRCPLERRENB    17
+#define V_T7_TRCPLERRENB(x) ((x) << S_T7_TRCPLERRENB)
+#define F_T7_TRCPLERRENB    V_T7_TRCPLERRENB(1U)
+
 #define S_T7_MISCPERR    16
 #define V_T7_MISCPERR(x) ((x) << S_T7_MISCPERR)
 #define F_T7_MISCPERR    V_T7_MISCPERR(1U)
@@ -42814,11 +42957,6 @@
 #define A_T7_MPS_TRC_FILTER_RUNT_CTL 0xa4a0
 #define A_T7_MPS_TRC_FILTER_DROP 0xa4c0
 #define A_T7_MPS_TRC_INT_ENABLE 0xa4e0
-
-#define S_T7_TRCPLERRENB    17
-#define V_T7_TRCPLERRENB(x) ((x) << S_T7_TRCPLERRENB)
-#define F_T7_TRCPLERRENB    V_T7_TRCPLERRENB(1U)
-
 #define A_T7_MPS_TRC_INT_CAUSE 0xa4e4
 #define A_T7_MPS_TRC_TIMESTAMP_L 0xa4e8
 #define A_T7_MPS_TRC_TIMESTAMP_H 0xa4ec
@@ -42885,13 +43023,72 @@
 #define G_PERR_TF_IN_CTL(x) (((x) >> S_PERR_TF_IN_CTL) & M_PERR_TF_IN_CTL)
 
 #define A_MPS_TRC_INT_ENABLE2 0xa4f4
-#define A_MPS_TRC_INT_CAUSE2 0xa4f8
 
-#define S_T7_TRC_TF_ECC    22
-#define M_T7_TRC_TF_ECC    0xffU
-#define V_T7_TRC_TF_ECC(x) ((x) << S_T7_TRC_TF_ECC)
-#define G_T7_TRC_TF_ECC(x) (((x) >> S_T7_TRC_TF_ECC) & M_T7_TRC_TF_ECC)
+#define S_TX2RX_DWN_CONV_PERR_PT3_CERR    16
+#define V_TX2RX_DWN_CONV_PERR_PT3_CERR(x) ((x) << S_TX2RX_DWN_CONV_PERR_PT3_CERR)
+#define F_TX2RX_DWN_CONV_PERR_PT3_CERR    V_TX2RX_DWN_CONV_PERR_PT3_CERR(1U)
+
+#define S_TX2RX_DWN_CONV_PERR_PT2_CERR    15
+#define V_TX2RX_DWN_CONV_PERR_PT2_CERR(x) ((x) << S_TX2RX_DWN_CONV_PERR_PT2_CERR)
+#define F_TX2RX_DWN_CONV_PERR_PT2_CERR    V_TX2RX_DWN_CONV_PERR_PT2_CERR(1U)
+
+#define S_TX2RX_DWN_CONV_PERR_PT1_CERR    14
+#define V_TX2RX_DWN_CONV_PERR_PT1_CERR(x) ((x) << S_TX2RX_DWN_CONV_PERR_PT1_CERR)
+#define F_TX2RX_DWN_CONV_PERR_PT1_CERR    V_TX2RX_DWN_CONV_PERR_PT1_CERR(1U)
+
+#define S_TX2RX_DWN_CONV_PERR_PT0_CERR    13
+#define V_TX2RX_DWN_CONV_PERR_PT0_CERR(x) ((x) << S_TX2RX_DWN_CONV_PERR_PT0_CERR)
+#define F_TX2RX_DWN_CONV_PERR_PT0_CERR    V_TX2RX_DWN_CONV_PERR_PT0_CERR(1U)
 
+#define S_MPS2MAC_DWN_CONV_PERR_PT1_CERR    12
+#define V_MPS2MAC_DWN_CONV_PERR_PT1_CERR(x) ((x) << S_MPS2MAC_DWN_CONV_PERR_PT1_CERR)
+#define F_MPS2MAC_DWN_CONV_PERR_PT1_CERR    V_MPS2MAC_DWN_CONV_PERR_PT1_CERR(1U)
+
+#define S_MPS2MAC_DWN_CONV_PERR_PT0_CERR    11
+#define V_MPS2MAC_DWN_CONV_PERR_PT0_CERR(x) ((x) << S_MPS2MAC_DWN_CONV_PERR_PT0_CERR)
+#define F_MPS2MAC_DWN_CONV_PERR_PT0_CERR    V_MPS2MAC_DWN_CONV_PERR_PT0_CERR(1U)
+
+#define S_MAC2MPS_DWN_CONV_PERR_PT1_CERR    10
+#define V_MAC2MPS_DWN_CONV_PERR_PT1_CERR(x) ((x) << S_MAC2MPS_DWN_CONV_PERR_PT1_CERR)
+#define F_MAC2MPS_DWN_CONV_PERR_PT1_CERR    V_MAC2MPS_DWN_CONV_PERR_PT1_CERR(1U)
+
+#define S_MAC2MPS_DWN_CONV_PERR_PT0_CERR    9
+#define V_MAC2MPS_DWN_CONV_PERR_PT0_CERR(x) ((x) << S_MAC2MPS_DWN_CONV_PERR_PT0_CERR)
+#define F_MAC2MPS_DWN_CONV_PERR_PT0_CERR    V_MAC2MPS_DWN_CONV_PERR_PT0_CERR(1U)
+
+#define S_TX2RX_DWN_CONV_PERR_PT3_PERR    8
+#define V_TX2RX_DWN_CONV_PERR_PT3_PERR(x) ((x) << S_TX2RX_DWN_CONV_PERR_PT3_PERR)
+#define F_TX2RX_DWN_CONV_PERR_PT3_PERR    V_TX2RX_DWN_CONV_PERR_PT3_PERR(1U)
+
+#define S_TX2RX_DWN_CONV_PERR_PT2_PERR    7
+#define V_TX2RX_DWN_CONV_PERR_PT2_PERR(x) ((x) << S_TX2RX_DWN_CONV_PERR_PT2_PERR)
+#define F_TX2RX_DWN_CONV_PERR_PT2_PERR    V_TX2RX_DWN_CONV_PERR_PT2_PERR(1U)
+
+#define S_TX2RX_DWN_CONV_PERR_PT1_PERR    6
+#define V_TX2RX_DWN_CONV_PERR_PT1_PERR(x) ((x) << S_TX2RX_DWN_CONV_PERR_PT1_PERR)
+#define F_TX2RX_DWN_CONV_PERR_PT1_PERR    V_TX2RX_DWN_CONV_PERR_PT1_PERR(1U)
+
+#define S_TX2RX_DWN_CONV_PERR_PT0_PERR    5
+#define V_TX2RX_DWN_CONV_PERR_PT0_PERR(x) ((x) << S_TX2RX_DWN_CONV_PERR_PT0_PERR)
+#define F_TX2RX_DWN_CONV_PERR_PT0_PERR    V_TX2RX_DWN_CONV_PERR_PT0_PERR(1U)
+
+#define S_MAC2MPS_DWN_CONV_PERR_PT1_PERR    4
+#define V_MAC2MPS_DWN_CONV_PERR_PT1_PERR(x) ((x) << S_MAC2MPS_DWN_CONV_PERR_PT1_PERR)
+#define F_MAC2MPS_DWN_CONV_PERR_PT1_PERR    V_MAC2MPS_DWN_CONV_PERR_PT1_PERR(1U)
+
+#define S_MAC2MPS_DWN_CONV_PERR_PT0_PERR    3
+#define V_MAC2MPS_DWN_CONV_PERR_PT0_PERR(x) ((x) << S_MAC2MPS_DWN_CONV_PERR_PT0_PERR)
+#define F_MAC2MPS_DWN_CONV_PERR_PT0_PERR    V_MAC2MPS_DWN_CONV_PERR_PT0_PERR(1U)
+
+#define S_MPS2MAC_DWN_CONV_PERR_PT1_PERR    2
+#define V_MPS2MAC_DWN_CONV_PERR_PT1_PERR(x) ((x) << S_MPS2MAC_DWN_CONV_PERR_PT1_PERR)
+#define F_MPS2MAC_DWN_CONV_PERR_PT1_PERR    V_MPS2MAC_DWN_CONV_PERR_PT1_PERR(1U)
+
+#define S_MPS2MAC_DWN_CONV_PERR_PT0_PERR    1
+#define V_MPS2MAC_DWN_CONV_PERR_PT0_PERR(x) ((x) << S_MPS2MAC_DWN_CONV_PERR_PT0_PERR)
+#define F_MPS2MAC_DWN_CONV_PERR_PT0_PERR    V_MPS2MAC_DWN_CONV_PERR_PT0_PERR(1U)
+
+#define A_MPS_TRC_INT_CAUSE2 0xa4f8
 #define A_MPS_CLS_CTL 0xd000
 
 #define S_MEMWRITEFAULT    4
@@ -43743,9 +43940,9 @@
 #define A_MPS_RX_CHMN_CNT 0x11070
 #define A_MPS_CTL_STAT 0x11070
 
-#define S_T7_CTL    0
-#define V_T7_CTL(x) ((x) << S_T7_CTL)
-#define F_T7_CTL    V_T7_CTL(1U)
+#define S_T7_MPS_CTL    0
+#define V_T7_MPS_CTL(x) ((x) << S_T7_MPS_CTL)
+#define F_T7_MPS_CTL    V_T7_MPS_CTL(1U)
 
 #define A_MPS_RX_PERR_INT_CAUSE 0x11074
 
@@ -43849,54 +44046,60 @@
 #define V_T6_INT_ERR_INT(x) ((x) << S_T6_INT_ERR_INT)
 #define F_T6_INT_ERR_INT    V_T6_INT_ERR_INT(1U)
 
-#define S_MAC_IN_FIFO_768B    30
-#define V_MAC_IN_FIFO_768B(x) ((x) << S_MAC_IN_FIFO_768B)
-#define F_MAC_IN_FIFO_768B    V_MAC_IN_FIFO_768B(1U)
-
-#define S_T7_1_INT_ERR_INT    29
-#define V_T7_1_INT_ERR_INT(x) ((x) << S_T7_1_INT_ERR_INT)
-#define F_T7_1_INT_ERR_INT    V_T7_1_INT_ERR_INT(1U)
+#define S_T7_INT_ERR_INT    30
+#define V_T7_INT_ERR_INT(x) ((x) << S_T7_INT_ERR_INT)
+#define F_T7_INT_ERR_INT    V_T7_INT_ERR_INT(1U)
 
 #define S_FLOP_PERR    28
 #define V_FLOP_PERR(x) ((x) << S_FLOP_PERR)
 #define F_FLOP_PERR    V_FLOP_PERR(1U)
 
-#define S_RPLC_MAP    13
-#define M_RPLC_MAP    0x1fU
-#define V_RPLC_MAP(x) ((x) << S_RPLC_MAP)
-#define G_RPLC_MAP(x) (((x) >> S_RPLC_MAP) & M_RPLC_MAP)
+#define S_MPS_RX_ATRB_MAP_PERR    23
+#define V_MPS_RX_ATRB_MAP_PERR(x) ((x) << S_MPS_RX_ATRB_MAP_PERR)
+#define F_MPS_RX_ATRB_MAP_PERR    V_MPS_RX_ATRB_MAP_PERR(1U)
 
-#define S_TKN_RUNT_DROP_FIFO    12
-#define V_TKN_RUNT_DROP_FIFO(x) ((x) << S_TKN_RUNT_DROP_FIFO)
-#define F_TKN_RUNT_DROP_FIFO    V_TKN_RUNT_DROP_FIFO(1U)
+#define S_RPLC_MAP_VNI_PERR    18
+#define M_RPLC_MAP_VNI_PERR    0x1fU
+#define V_RPLC_MAP_VNI_PERR(x) ((x) << S_RPLC_MAP_VNI_PERR)
+#define G_RPLC_MAP_VNI_PERR(x) (((x) >> S_RPLC_MAP_VNI_PERR) & M_RPLC_MAP_VNI_PERR)
 
-#define S_T7_PPM3    9
-#define M_T7_PPM3    0x7U
-#define V_T7_PPM3(x) ((x) << S_T7_PPM3)
-#define G_T7_PPM3(x) (((x) >> S_T7_PPM3) & M_T7_PPM3)
+#define S_RPLC_MAP_MCAST_PERR    13
+#define M_RPLC_MAP_MCAST_PERR    0x1fU
+#define V_RPLC_MAP_MCAST_PERR(x) ((x) << S_RPLC_MAP_MCAST_PERR)
+#define G_RPLC_MAP_MCAST_PERR(x) (((x) >> S_RPLC_MAP_MCAST_PERR) & M_RPLC_MAP_MCAST_PERR)
 
-#define S_T7_PPM2    6
-#define M_T7_PPM2    0x7U
-#define V_T7_PPM2(x) ((x) << S_T7_PPM2)
-#define G_T7_PPM2(x) (((x) >> S_T7_PPM2) & M_T7_PPM2)
+#define S_PPM3_PERR    9
+#define M_PPM3_PERR    0x7U
+#define V_PPM3_PERR(x) ((x) << S_PPM3_PERR)
+#define G_PPM3_PERR(x) (((x) >> S_PPM3_PERR) & M_PPM3_PERR)
 
-#define S_T7_PPM1    3
-#define M_T7_PPM1    0x7U
-#define V_T7_PPM1(x) ((x) << S_T7_PPM1)
-#define G_T7_PPM1(x) (((x) >> S_T7_PPM1) & M_T7_PPM1)
+#define S_PPM2_PERR    6
+#define M_PPM2_PERR    0x7U
+#define V_PPM2_PERR(x) ((x) << S_PPM2_PERR)
+#define G_PPM2_PERR(x) (((x) >> S_PPM2_PERR) & M_PPM2_PERR)
 
-#define S_T7_PPM0    0
-#define M_T7_PPM0    0x7U
-#define V_T7_PPM0(x) ((x) << S_T7_PPM0)
-#define G_T7_PPM0(x) (((x) >> S_T7_PPM0) & M_T7_PPM0)
+#define S_PPM1_PERR    3
+#define M_PPM1_PERR    0x7U
+#define V_PPM1_PERR(x) ((x) << S_PPM1_PERR)
+#define G_PPM1_PERR(x) (((x) >> S_PPM1_PERR) & M_PPM1_PERR)
+
+#define S_PPM0_PERR    0
+#define M_PPM0_PERR    0x7U
+#define V_PPM0_PERR(x) ((x) << S_PPM0_PERR)
+#define G_PPM0_PERR(x) (((x) >> S_PPM0_PERR) & M_PPM0_PERR)
 
 #define A_MPS_RX_PERR_INT_ENABLE 0x11078
+#define A_MPS_RX_PERR_ENABLE 0x1107c
 
-#define S_T7_2_INT_ERR_INT    30
-#define V_T7_2_INT_ERR_INT(x) ((x) << S_T7_2_INT_ERR_INT)
-#define F_T7_2_INT_ERR_INT    V_T7_2_INT_ERR_INT(1U)
+#define S_MPS_RX_ATRB_MA_PERRP    23
+#define V_MPS_RX_ATRB_MA_PERRP(x) ((x) << S_MPS_RX_ATRB_MA_PERRP)
+#define F_MPS_RX_ATRB_MA_PERRP    V_MPS_RX_ATRB_MA_PERRP(1U)
+
+#define S_RPLC_MAP_VN_PERRI    18
+#define M_RPLC_MAP_VN_PERRI    0x1fU
+#define V_RPLC_MAP_VN_PERRI(x) ((x) << S_RPLC_MAP_VN_PERRI)
+#define G_RPLC_MAP_VN_PERRI(x) (((x) >> S_RPLC_MAP_VN_PERRI) & M_RPLC_MAP_VN_PERRI)
 
-#define A_MPS_RX_PERR_ENABLE 0x1107c
 #define A_MPS_RX_PERR_INJECT 0x11080
 #define A_MPS_RX_FUNC_INT_CAUSE 0x11084
 
@@ -43965,6 +44168,38 @@
 #define V_LEN_ERR_INT(x) ((x) << S_LEN_ERR_INT)
 #define F_LEN_ERR_INT    V_LEN_ERR_INT(1U)
 
+#define S_MTU_ERR3    19
+#define V_MTU_ERR3(x) ((x) << S_MTU_ERR3)
+#define F_MTU_ERR3    V_MTU_ERR3(1U)
+
+#define S_MTU_ERR2    18
+#define V_MTU_ERR2(x) ((x) << S_MTU_ERR2)
+#define F_MTU_ERR2    V_MTU_ERR2(1U)
+
+#define S_MTU_ERR1    17
+#define V_MTU_ERR1(x) ((x) << S_MTU_ERR1)
+#define F_MTU_ERR1    V_MTU_ERR1(1U)
+
+#define S_MTU_ERR0    16
+#define V_MTU_ERR0(x) ((x) << S_MTU_ERR0)
+#define F_MTU_ERR0    V_MTU_ERR0(1U)
+
+#define S_DBG_LEN_ERR    15
+#define V_DBG_LEN_ERR(x) ((x) << S_DBG_LEN_ERR)
+#define F_DBG_LEN_ERR    V_DBG_LEN_ERR(1U)
+
+#define S_DBG_SPI_ERR    14
+#define V_DBG_SPI_ERR(x) ((x) << S_DBG_SPI_ERR)
+#define F_DBG_SPI_ERR    V_DBG_SPI_ERR(1U)
+
+#define S_DBG_SE_CNT_ERR    13
+#define V_DBG_SE_CNT_ERR(x) ((x) << S_DBG_SE_CNT_ERR)
+#define F_DBG_SE_CNT_ERR    V_DBG_SE_CNT_ERR(1U)
+
+#define S_DBG_SPI_LEN_SE_CNT_ERR    12
+#define V_DBG_SPI_LEN_SE_CNT_ERR(x) ((x) << S_DBG_SPI_LEN_SE_CNT_ERR)
+#define F_DBG_SPI_LEN_SE_CNT_ERR    V_DBG_SPI_LEN_SE_CNT_ERR(1U)
+
 #define A_MPS_RX_FUNC_INT_ENABLE 0x11088
 #define A_MPS_RX_PAUSE_GEN_TH_0 0x1108c
 
@@ -43980,59 +44215,59 @@
 
 #define A_MPS_RX_PERR_INT_CAUSE2 0x1108c
 
-#define S_CRYPT2MPS_RX_INTF_FIFO    28
-#define M_CRYPT2MPS_RX_INTF_FIFO    0xfU
-#define V_CRYPT2MPS_RX_INTF_FIFO(x) ((x) << S_CRYPT2MPS_RX_INTF_FIFO)
-#define G_CRYPT2MPS_RX_INTF_FIFO(x) (((x) >> S_CRYPT2MPS_RX_INTF_FIFO) & M_CRYPT2MPS_RX_INTF_FIFO)
+#define S_CRYPTO2MPS_RX0_PERR    31
+#define V_CRYPTO2MPS_RX0_PERR(x) ((x) << S_CRYPTO2MPS_RX0_PERR)
+#define F_CRYPTO2MPS_RX0_PERR    V_CRYPTO2MPS_RX0_PERR(1U)
 
-#define S_INIC2MPS_TX0_PERR    27
-#define V_INIC2MPS_TX0_PERR(x) ((x) << S_INIC2MPS_TX0_PERR)
-#define F_INIC2MPS_TX0_PERR    V_INIC2MPS_TX0_PERR(1U)
+#define S_CRYPTO2MPS_RX1_PERR    30
+#define V_CRYPTO2MPS_RX1_PERR(x) ((x) << S_CRYPTO2MPS_RX1_PERR)
+#define F_CRYPTO2MPS_RX1_PERR    V_CRYPTO2MPS_RX1_PERR(1U)
+
+#define S_CRYPTO2MPS_RX2_PERR    29
+#define V_CRYPTO2MPS_RX2_PERR(x) ((x) << S_CRYPTO2MPS_RX2_PERR)
+#define F_CRYPTO2MPS_RX2_PERR    V_CRYPTO2MPS_RX2_PERR(1U)
 
-#define S_INIC2MPS_TX1_PERR    26
+#define S_CRYPTO2MPS_RX3_PERR    28
+#define V_CRYPTO2MPS_RX3_PERR(x) ((x) << S_CRYPTO2MPS_RX3_PERR)
+#define F_CRYPTO2MPS_RX3_PERR    V_CRYPTO2MPS_RX3_PERR(1U)
+
+#define S_INIC2MPS_TX1_PERR    27
 #define V_INIC2MPS_TX1_PERR(x) ((x) << S_INIC2MPS_TX1_PERR)
 #define F_INIC2MPS_TX1_PERR    V_INIC2MPS_TX1_PERR(1U)
 
-#define S_XGMAC2MPS_RX0_PERR    25
-#define V_XGMAC2MPS_RX0_PERR(x) ((x) << S_XGMAC2MPS_RX0_PERR)
-#define F_XGMAC2MPS_RX0_PERR    V_XGMAC2MPS_RX0_PERR(1U)
+#define S_INIC2MPS_TX0_PERR    26
+#define V_INIC2MPS_TX0_PERR(x) ((x) << S_INIC2MPS_TX0_PERR)
+#define F_INIC2MPS_TX0_PERR    V_INIC2MPS_TX0_PERR(1U)
 
-#define S_XGMAC2MPS_RX1_PERR    24
+#define S_XGMAC2MPS_RX1_PERR    25
 #define V_XGMAC2MPS_RX1_PERR(x) ((x) << S_XGMAC2MPS_RX1_PERR)
 #define F_XGMAC2MPS_RX1_PERR    V_XGMAC2MPS_RX1_PERR(1U)
 
-#define S_MPS2CRYPTO_RX_INTF_FIFO    20
-#define M_MPS2CRYPTO_RX_INTF_FIFO    0xfU
-#define V_MPS2CRYPTO_RX_INTF_FIFO(x) ((x) << S_MPS2CRYPTO_RX_INTF_FIFO)
-#define G_MPS2CRYPTO_RX_INTF_FIFO(x) (((x) >> S_MPS2CRYPTO_RX_INTF_FIFO) & M_MPS2CRYPTO_RX_INTF_FIFO)
-
-#define S_MAC_RX_PPROC_MPS2TP_TF    19
-#define V_MAC_RX_PPROC_MPS2TP_TF(x) ((x) << S_MAC_RX_PPROC_MPS2TP_TF)
-#define F_MAC_RX_PPROC_MPS2TP_TF    V_MAC_RX_PPROC_MPS2TP_TF(1U)
-
-#define S_MAC_RX_PPROC_LB_CH3    18
-#define V_MAC_RX_PPROC_LB_CH3(x) ((x) << S_MAC_RX_PPROC_LB_CH3)
-#define F_MAC_RX_PPROC_LB_CH3    V_MAC_RX_PPROC_LB_CH3(1U)
+#define S_XGMAC2MPS_RX0_PERR    24
+#define V_XGMAC2MPS_RX0_PERR(x) ((x) << S_XGMAC2MPS_RX0_PERR)
+#define F_XGMAC2MPS_RX0_PERR    V_XGMAC2MPS_RX0_PERR(1U)
 
-#define S_MAC_RX_PPROC_LB_CH2    17
-#define V_MAC_RX_PPROC_LB_CH2(x) ((x) << S_MAC_RX_PPROC_LB_CH2)
-#define F_MAC_RX_PPROC_LB_CH2    V_MAC_RX_PPROC_LB_CH2(1U)
+#define S_MPS2CRYPTO_CH0_INTF_FIFO_PERR    20
+#define M_MPS2CRYPTO_CH0_INTF_FIFO_PERR    0xfU
+#define V_MPS2CRYPTO_CH0_INTF_FIFO_PERR(x) ((x) << S_MPS2CRYPTO_CH0_INTF_FIFO_PERR)
+#define G_MPS2CRYPTO_CH0_INTF_FIFO_PERR(x) (((x) >> S_MPS2CRYPTO_CH0_INTF_FIFO_PERR) & M_MPS2CRYPTO_CH0_INTF_FIFO_PERR)
 
-#define S_MAC_RX_PPROC_LB_CH1    16
-#define V_MAC_RX_PPROC_LB_CH1(x) ((x) << S_MAC_RX_PPROC_LB_CH1)
-#define F_MAC_RX_PPROC_LB_CH1    V_MAC_RX_PPROC_LB_CH1(1U)
+#define S_RX_FINAL_TF_FIFO_PERR    19
+#define V_RX_FINAL_TF_FIFO_PERR(x) ((x) << S_RX_FINAL_TF_FIFO_PERR)
+#define F_RX_FINAL_TF_FIFO_PERR    V_RX_FINAL_TF_FIFO_PERR(1U)
 
-#define S_MAC_RX_PPROC_LB_CH0    15
-#define V_MAC_RX_PPROC_LB_CH0(x) ((x) << S_MAC_RX_PPROC_LB_CH0)
-#define F_MAC_RX_PPROC_LB_CH0    V_MAC_RX_PPROC_LB_CH0(1U)
+#define S_MPS_LB_FIFO_PERR    15
+#define M_MPS_LB_FIFO_PERR    0xfU
+#define V_MPS_LB_FIFO_PERR(x) ((x) << S_MPS_LB_FIFO_PERR)
+#define G_MPS_LB_FIFO_PERR(x) (((x) >> S_MPS_LB_FIFO_PERR) & M_MPS_LB_FIFO_PERR)
 
-#define S_MAC_RX_PPROC_DWRR_CH0_3    14
-#define V_MAC_RX_PPROC_DWRR_CH0_3(x) ((x) << S_MAC_RX_PPROC_DWRR_CH0_3)
-#define F_MAC_RX_PPROC_DWRR_CH0_3    V_MAC_RX_PPROC_DWRR_CH0_3(1U)
+#define S_MPS_DWRR_FIFO_PERR    14
+#define V_MPS_DWRR_FIFO_PERR(x) ((x) << S_MPS_DWRR_FIFO_PERR)
+#define F_MPS_DWRR_FIFO_PERR    V_MPS_DWRR_FIFO_PERR(1U)
 
-#define S_MAC_RX_FIFO_PERR    13
-#define V_MAC_RX_FIFO_PERR(x) ((x) << S_MAC_RX_FIFO_PERR)
-#define F_MAC_RX_FIFO_PERR    V_MAC_RX_FIFO_PERR(1U)
+#define S_MAC_TF_FIFO_PERR    13
+#define V_MAC_TF_FIFO_PERR(x) ((x) << S_MAC_TF_FIFO_PERR)
+#define F_MAC_TF_FIFO_PERR    V_MAC_TF_FIFO_PERR(1U)
 
 #define S_MAC2MPS_PT3_PERR    12
 #define V_MAC2MPS_PT3_PERR(x) ((x) << S_MAC2MPS_PT3_PERR)
@@ -44050,13 +44285,18 @@
 #define V_MAC2MPS_PT0_PERR(x) ((x) << S_MAC2MPS_PT0_PERR)
 #define F_MAC2MPS_PT0_PERR    V_MAC2MPS_PT0_PERR(1U)
 
-#define S_LPBK_FIFO_PERR    8
-#define V_LPBK_FIFO_PERR(x) ((x) << S_LPBK_FIFO_PERR)
-#define F_LPBK_FIFO_PERR    V_LPBK_FIFO_PERR(1U)
+#define S_TP_LPBK_FIFO_PERR    8
+#define V_TP_LPBK_FIFO_PERR(x) ((x) << S_TP_LPBK_FIFO_PERR)
+#define F_TP_LPBK_FIFO_PERR    V_TP_LPBK_FIFO_PERR(1U)
 
-#define S_TP2MPS_TF_FIFO_PERR    7
-#define V_TP2MPS_TF_FIFO_PERR(x) ((x) << S_TP2MPS_TF_FIFO_PERR)
-#define F_TP2MPS_TF_FIFO_PERR    V_TP2MPS_TF_FIFO_PERR(1U)
+#define S_TP_LPBK_TF_PERR    7
+#define V_TP_LPBK_TF_PERR(x) ((x) << S_TP_LPBK_TF_PERR)
+#define F_TP_LPBK_TF_PERR    V_TP_LPBK_TF_PERR(1U)
+
+#define S_RSDV1    0
+#define M_RSDV1    0x7fU
+#define V_RSDV1(x) ((x) << S_RSDV1)
+#define G_RSDV1(x) (((x) >> S_RSDV1) & M_RSDV1)
 
 #define A_MPS_RX_PAUSE_GEN_TH_1 0x11090
 #define A_MPS_RX_PERR_INT_ENABLE2 0x11090
@@ -44978,67 +45218,407 @@
 #define A_MPS_VF_RPLCT_MAP6 0x11308
 #define A_MPS_VF_RPLCT_MAP7 0x1130c
 #define A_MPS_RX_PERR_INT_CAUSE3 0x11310
+
+#define S_FIFO_REPL_CH3_CERR    28
+#define V_FIFO_REPL_CH3_CERR(x) ((x) << S_FIFO_REPL_CH3_CERR)
+#define F_FIFO_REPL_CH3_CERR    V_FIFO_REPL_CH3_CERR(1U)
+
+#define S_FIFO_REPL_CH2_CERR    27
+#define V_FIFO_REPL_CH2_CERR(x) ((x) << S_FIFO_REPL_CH2_CERR)
+#define F_FIFO_REPL_CH2_CERR    V_FIFO_REPL_CH2_CERR(1U)
+
+#define S_FIFO_REPL_CH1_CERR    26
+#define V_FIFO_REPL_CH1_CERR(x) ((x) << S_FIFO_REPL_CH1_CERR)
+#define F_FIFO_REPL_CH1_CERR    V_FIFO_REPL_CH1_CERR(1U)
+
+#define S_FIFO_REPL_CH0_CERR    25
+#define V_FIFO_REPL_CH0_CERR(x) ((x) << S_FIFO_REPL_CH0_CERR)
+#define F_FIFO_REPL_CH0_CERR    V_FIFO_REPL_CH0_CERR(1U)
+
+#define S_VLAN_FILTER_RAM_CERR    24
+#define V_VLAN_FILTER_RAM_CERR(x) ((x) << S_VLAN_FILTER_RAM_CERR)
+#define F_VLAN_FILTER_RAM_CERR    V_VLAN_FILTER_RAM_CERR(1U)
+
+#define S_MPS_RX_TD_STAT_FIFO_PERR_CH3    23
+#define V_MPS_RX_TD_STAT_FIFO_PERR_CH3(x) ((x) << S_MPS_RX_TD_STAT_FIFO_PERR_CH3)
+#define F_MPS_RX_TD_STAT_FIFO_PERR_CH3    V_MPS_RX_TD_STAT_FIFO_PERR_CH3(1U)
+
+#define S_RPLCT_HDR_FIFO_IN_PERR_CH3    22
+#define V_RPLCT_HDR_FIFO_IN_PERR_CH3(x) ((x) << S_RPLCT_HDR_FIFO_IN_PERR_CH3)
+#define F_RPLCT_HDR_FIFO_IN_PERR_CH3    V_RPLCT_HDR_FIFO_IN_PERR_CH3(1U)
+
+#define S_ID_FIFO_IN_PERR_CH3    21
+#define V_ID_FIFO_IN_PERR_CH3(x) ((x) << S_ID_FIFO_IN_PERR_CH3)
+#define F_ID_FIFO_IN_PERR_CH3    V_ID_FIFO_IN_PERR_CH3(1U)
+
+#define S_DESC_HDR2_PERR_CH3    20
+#define V_DESC_HDR2_PERR_CH3(x) ((x) << S_DESC_HDR2_PERR_CH3)
+#define F_DESC_HDR2_PERR_CH3    V_DESC_HDR2_PERR_CH3(1U)
+
+#define S_FIFO_REPL_PERR_CH3    19
+#define V_FIFO_REPL_PERR_CH3(x) ((x) << S_FIFO_REPL_PERR_CH3)
+#define F_FIFO_REPL_PERR_CH3    V_FIFO_REPL_PERR_CH3(1U)
+
+#define S_MPS_RX_TD_PERR_CH3    18
+#define V_MPS_RX_TD_PERR_CH3(x) ((x) << S_MPS_RX_TD_PERR_CH3)
+#define F_MPS_RX_TD_PERR_CH3    V_MPS_RX_TD_PERR_CH3(1U)
+
+#define S_MPS_RX_TD_STAT_FIFO_PERR_CH2    17
+#define V_MPS_RX_TD_STAT_FIFO_PERR_CH2(x) ((x) << S_MPS_RX_TD_STAT_FIFO_PERR_CH2)
+#define F_MPS_RX_TD_STAT_FIFO_PERR_CH2    V_MPS_RX_TD_STAT_FIFO_PERR_CH2(1U)
+
+#define S_RPLCT_HDR_FIFO_IN_PERR_CH2    16
+#define V_RPLCT_HDR_FIFO_IN_PERR_CH2(x) ((x) << S_RPLCT_HDR_FIFO_IN_PERR_CH2)
+#define F_RPLCT_HDR_FIFO_IN_PERR_CH2    V_RPLCT_HDR_FIFO_IN_PERR_CH2(1U)
+
+#define S_ID_FIFO_IN_PERR_CH2    15
+#define V_ID_FIFO_IN_PERR_CH2(x) ((x) << S_ID_FIFO_IN_PERR_CH2)
+#define F_ID_FIFO_IN_PERR_CH2    V_ID_FIFO_IN_PERR_CH2(1U)
+
+#define S_DESC_HDR2_PERR_CH2    14
+#define V_DESC_HDR2_PERR_CH2(x) ((x) << S_DESC_HDR2_PERR_CH2)
+#define F_DESC_HDR2_PERR_CH2    V_DESC_HDR2_PERR_CH2(1U)
+
+#define S_FIFO_REPL_PERR_CH2    13
+#define V_FIFO_REPL_PERR_CH2(x) ((x) << S_FIFO_REPL_PERR_CH2)
+#define F_FIFO_REPL_PERR_CH2    V_FIFO_REPL_PERR_CH2(1U)
+
+#define S_MPS_RX_TD_PERR_CH2    12
+#define V_MPS_RX_TD_PERR_CH2(x) ((x) << S_MPS_RX_TD_PERR_CH2)
+#define F_MPS_RX_TD_PERR_CH2    V_MPS_RX_TD_PERR_CH2(1U)
+
+#define S_MPS_RX_TD_STAT_FIFO_PERR_CH1    11
+#define V_MPS_RX_TD_STAT_FIFO_PERR_CH1(x) ((x) << S_MPS_RX_TD_STAT_FIFO_PERR_CH1)
+#define F_MPS_RX_TD_STAT_FIFO_PERR_CH1    V_MPS_RX_TD_STAT_FIFO_PERR_CH1(1U)
+
+#define S_RPLCT_HDR_FIFO_IN_PERR_CH1    10
+#define V_RPLCT_HDR_FIFO_IN_PERR_CH1(x) ((x) << S_RPLCT_HDR_FIFO_IN_PERR_CH1)
+#define F_RPLCT_HDR_FIFO_IN_PERR_CH1    V_RPLCT_HDR_FIFO_IN_PERR_CH1(1U)
+
+#define S_ID_FIFO_IN_PERR_CH1    9
+#define V_ID_FIFO_IN_PERR_CH1(x) ((x) << S_ID_FIFO_IN_PERR_CH1)
+#define F_ID_FIFO_IN_PERR_CH1    V_ID_FIFO_IN_PERR_CH1(1U)
+
+#define S_DESC_HDR2_PERR_CH1    8
+#define V_DESC_HDR2_PERR_CH1(x) ((x) << S_DESC_HDR2_PERR_CH1)
+#define F_DESC_HDR2_PERR_CH1    V_DESC_HDR2_PERR_CH1(1U)
+
+#define S_FIFO_REPL_PERR_CH1    7
+#define V_FIFO_REPL_PERR_CH1(x) ((x) << S_FIFO_REPL_PERR_CH1)
+#define F_FIFO_REPL_PERR_CH1    V_FIFO_REPL_PERR_CH1(1U)
+
+#define S_MPS_RX_TD_PERR_CH1    6
+#define V_MPS_RX_TD_PERR_CH1(x) ((x) << S_MPS_RX_TD_PERR_CH1)
+#define F_MPS_RX_TD_PERR_CH1    V_MPS_RX_TD_PERR_CH1(1U)
+
+#define S_MPS_RX_TD_STAT_FIFO_PERR_CH0    5
+#define V_MPS_RX_TD_STAT_FIFO_PERR_CH0(x) ((x) << S_MPS_RX_TD_STAT_FIFO_PERR_CH0)
+#define F_MPS_RX_TD_STAT_FIFO_PERR_CH0    V_MPS_RX_TD_STAT_FIFO_PERR_CH0(1U)
+
+#define S_RPLCT_HDR_FIFO_IN_PERR_CH0    4
+#define V_RPLCT_HDR_FIFO_IN_PERR_CH0(x) ((x) << S_RPLCT_HDR_FIFO_IN_PERR_CH0)
+#define F_RPLCT_HDR_FIFO_IN_PERR_CH0    V_RPLCT_HDR_FIFO_IN_PERR_CH0(1U)
+
+#define S_ID_FIFO_IN_PERR_CH0    3
+#define V_ID_FIFO_IN_PERR_CH0(x) ((x) << S_ID_FIFO_IN_PERR_CH0)
+#define F_ID_FIFO_IN_PERR_CH0    V_ID_FIFO_IN_PERR_CH0(1U)
+
+#define S_DESC_HDR2_PERR_CH0    2
+#define V_DESC_HDR2_PERR_CH0(x) ((x) << S_DESC_HDR2_PERR_CH0)
+#define F_DESC_HDR2_PERR_CH0    V_DESC_HDR2_PERR_CH0(1U)
+
+#define S_FIFO_REPL_PERR_CH0    1
+#define V_FIFO_REPL_PERR_CH0(x) ((x) << S_FIFO_REPL_PERR_CH0)
+#define F_FIFO_REPL_PERR_CH0    V_FIFO_REPL_PERR_CH0(1U)
+
+#define S_MPS_RX_TD_PERR_CH0    0
+#define V_MPS_RX_TD_PERR_CH0(x) ((x) << S_MPS_RX_TD_PERR_CH0)
+#define F_MPS_RX_TD_PERR_CH0    V_MPS_RX_TD_PERR_CH0(1U)
+
 #define A_MPS_RX_PERR_INT_ENABLE3 0x11314
 #define A_MPS_RX_PERR_ENABLE3 0x11318
 #define A_MPS_RX_PERR_INT_CAUSE4 0x1131c
 
-#define S_CLS    20
-#define M_CLS    0x3fU
-#define V_CLS(x) ((x) << S_CLS)
-#define G_CLS(x) (((x) >> S_CLS) & M_CLS)
+#define S_VNI_MULTICAST_FIFO_ECC_ERR_CH3    30
+#define V_VNI_MULTICAST_FIFO_ECC_ERR_CH3(x) ((x) << S_VNI_MULTICAST_FIFO_ECC_ERR_CH3)
+#define F_VNI_MULTICAST_FIFO_ECC_ERR_CH3    V_VNI_MULTICAST_FIFO_ECC_ERR_CH3(1U)
+
+#define S_VNI_MULTICAST_FIFO_ECC_ERR_CH2    29
+#define V_VNI_MULTICAST_FIFO_ECC_ERR_CH2(x) ((x) << S_VNI_MULTICAST_FIFO_ECC_ERR_CH2)
+#define F_VNI_MULTICAST_FIFO_ECC_ERR_CH2    V_VNI_MULTICAST_FIFO_ECC_ERR_CH2(1U)
+
+#define S_HASH_SRAM_CLS_ENG1    28
+#define V_HASH_SRAM_CLS_ENG1(x) ((x) << S_HASH_SRAM_CLS_ENG1)
+#define F_HASH_SRAM_CLS_ENG1    V_HASH_SRAM_CLS_ENG1(1U)
+
+#define S_HASH_SRAM_CLS_ENG0    27
+#define V_HASH_SRAM_CLS_ENG0(x) ((x) << S_HASH_SRAM_CLS_ENG0)
+#define F_HASH_SRAM_CLS_ENG0    V_HASH_SRAM_CLS_ENG0(1U)
+
+#define S_CLS_TCAM_SRAM_CLS_ENG1    26
+#define V_CLS_TCAM_SRAM_CLS_ENG1(x) ((x) << S_CLS_TCAM_SRAM_CLS_ENG1)
+#define F_CLS_TCAM_SRAM_CLS_ENG1    V_CLS_TCAM_SRAM_CLS_ENG1(1U)
+
+#define S_CLS_TCAM_CRC_SRAM_CLS_ENG1    25
+#define V_CLS_TCAM_CRC_SRAM_CLS_ENG1(x) ((x) << S_CLS_TCAM_CRC_SRAM_CLS_ENG1)
+#define F_CLS_TCAM_CRC_SRAM_CLS_ENG1    V_CLS_TCAM_CRC_SRAM_CLS_ENG1(1U)
+
+#define S_CLS_TCAM_SRAM_CLS_ENG0    24
+#define V_CLS_TCAM_SRAM_CLS_ENG0(x) ((x) << S_CLS_TCAM_SRAM_CLS_ENG0)
+#define F_CLS_TCAM_SRAM_CLS_ENG0    V_CLS_TCAM_SRAM_CLS_ENG0(1U)
+
+#define S_CLS_TCAM_CRC_SRAM_CLS_ENG0    23
+#define V_CLS_TCAM_CRC_SRAM_CLS_ENG0(x) ((x) << S_CLS_TCAM_CRC_SRAM_CLS_ENG0)
+#define F_CLS_TCAM_CRC_SRAM_CLS_ENG0    V_CLS_TCAM_CRC_SRAM_CLS_ENG0(1U)
+
+#define S_LB_FIFO_ECC_ERR    19
+#define M_LB_FIFO_ECC_ERR    0xfU
+#define V_LB_FIFO_ECC_ERR(x) ((x) << S_LB_FIFO_ECC_ERR)
+#define G_LB_FIFO_ECC_ERR(x) (((x) >> S_LB_FIFO_ECC_ERR) & M_LB_FIFO_ECC_ERR)
+
+#define S_DWRR_CH_FIFO_ECC_ERR    18
+#define V_DWRR_CH_FIFO_ECC_ERR(x) ((x) << S_DWRR_CH_FIFO_ECC_ERR)
+#define F_DWRR_CH_FIFO_ECC_ERR    V_DWRR_CH_FIFO_ECC_ERR(1U)
+
+#define S_MAC_RX_FIFO_ECC_ERR    17
+#define V_MAC_RX_FIFO_ECC_ERR(x) ((x) << S_MAC_RX_FIFO_ECC_ERR)
+#define F_MAC_RX_FIFO_ECC_ERR    V_MAC_RX_FIFO_ECC_ERR(1U)
+
+#define S_LPBK_RX_FIFO_ECC_ERR    16
+#define V_LPBK_RX_FIFO_ECC_ERR(x) ((x) << S_LPBK_RX_FIFO_ECC_ERR)
+#define F_LPBK_RX_FIFO_ECC_ERR    V_LPBK_RX_FIFO_ECC_ERR(1U)
+
+#define S_CRS_DATA_STORE_N_FWD_CH3    15
+#define V_CRS_DATA_STORE_N_FWD_CH3(x) ((x) << S_CRS_DATA_STORE_N_FWD_CH3)
+#define F_CRS_DATA_STORE_N_FWD_CH3    V_CRS_DATA_STORE_N_FWD_CH3(1U)
+
+#define S_TRACE_FWD_FIFO_CERR_CH3    14
+#define V_TRACE_FWD_FIFO_CERR_CH3(x) ((x) << S_TRACE_FWD_FIFO_CERR_CH3)
+#define F_TRACE_FWD_FIFO_CERR_CH3    V_TRACE_FWD_FIFO_CERR_CH3(1U)
 
-#define S_RX_PRE_PROC    16
-#define M_RX_PRE_PROC    0xfU
-#define V_RX_PRE_PROC(x) ((x) << S_RX_PRE_PROC)
-#define G_RX_PRE_PROC(x) (((x) >> S_RX_PRE_PROC) & M_RX_PRE_PROC)
+#define S_TRANSPARENT_ENCAP_FWD_FIFO_CERR_CH3    13
+#define V_TRANSPARENT_ENCAP_FWD_FIFO_CERR_CH3(x) ((x) << S_TRANSPARENT_ENCAP_FWD_FIFO_CERR_CH3)
+#define F_TRANSPARENT_ENCAP_FWD_FIFO_CERR_CH3    V_TRANSPARENT_ENCAP_FWD_FIFO_CERR_CH3(1U)
 
-#define S_PPROC3    12
-#define M_PPROC3    0xfU
-#define V_PPROC3(x) ((x) << S_PPROC3)
-#define G_PPROC3(x) (((x) >> S_PPROC3) & M_PPROC3)
+#define S_PTP_TRACE_FWD_FIFO_CERR_CH3    12
+#define V_PTP_TRACE_FWD_FIFO_CERR_CH3(x) ((x) << S_PTP_TRACE_FWD_FIFO_CERR_CH3)
+#define F_PTP_TRACE_FWD_FIFO_CERR_CH3    V_PTP_TRACE_FWD_FIFO_CERR_CH3(1U)
 
-#define S_PPROC2    8
-#define M_PPROC2    0xfU
-#define V_PPROC2(x) ((x) << S_PPROC2)
-#define G_PPROC2(x) (((x) >> S_PPROC2) & M_PPROC2)
+#define S_CRS_DATA_STORE_N_FWD_CH2    11
+#define V_CRS_DATA_STORE_N_FWD_CH2(x) ((x) << S_CRS_DATA_STORE_N_FWD_CH2)
+#define F_CRS_DATA_STORE_N_FWD_CH2    V_CRS_DATA_STORE_N_FWD_CH2(1U)
 
-#define S_PPROC1    4
-#define M_PPROC1    0xfU
-#define V_PPROC1(x) ((x) << S_PPROC1)
-#define G_PPROC1(x) (((x) >> S_PPROC1) & M_PPROC1)
+#define S_TRACE_FWD_FIFO_CERR_CH2    10
+#define V_TRACE_FWD_FIFO_CERR_CH2(x) ((x) << S_TRACE_FWD_FIFO_CERR_CH2)
+#define F_TRACE_FWD_FIFO_CERR_CH2    V_TRACE_FWD_FIFO_CERR_CH2(1U)
 
-#define S_PPROC0    0
-#define M_PPROC0    0xfU
-#define V_PPROC0(x) ((x) << S_PPROC0)
-#define G_PPROC0(x) (((x) >> S_PPROC0) & M_PPROC0)
+#define S_TRANSPARENT_ENCAP_FWD_FIFO_CERR_CH2    9
+#define V_TRANSPARENT_ENCAP_FWD_FIFO_CERR_CH2(x) ((x) << S_TRANSPARENT_ENCAP_FWD_FIFO_CERR_CH2)
+#define F_TRANSPARENT_ENCAP_FWD_FIFO_CERR_CH2    V_TRANSPARENT_ENCAP_FWD_FIFO_CERR_CH2(1U)
+
+#define S_PTP_TRACE_FWD_FIFO_CERR_CH2    8
+#define V_PTP_TRACE_FWD_FIFO_CERR_CH2(x) ((x) << S_PTP_TRACE_FWD_FIFO_CERR_CH2)
+#define F_PTP_TRACE_FWD_FIFO_CERR_CH2    V_PTP_TRACE_FWD_FIFO_CERR_CH2(1U)
+
+#define S_CRS_DATA_STORE_N_FWD_CH1    7
+#define V_CRS_DATA_STORE_N_FWD_CH1(x) ((x) << S_CRS_DATA_STORE_N_FWD_CH1)
+#define F_CRS_DATA_STORE_N_FWD_CH1    V_CRS_DATA_STORE_N_FWD_CH1(1U)
+
+#define S_TRACE_FWD_FIFO_CERR_CH1    6
+#define V_TRACE_FWD_FIFO_CERR_CH1(x) ((x) << S_TRACE_FWD_FIFO_CERR_CH1)
+#define F_TRACE_FWD_FIFO_CERR_CH1    V_TRACE_FWD_FIFO_CERR_CH1(1U)
+
+#define S_TRANSPARENT_ENCAP_FWD_FIFO_CERR_CH1    5
+#define V_TRANSPARENT_ENCAP_FWD_FIFO_CERR_CH1(x) ((x) << S_TRANSPARENT_ENCAP_FWD_FIFO_CERR_CH1)
+#define F_TRANSPARENT_ENCAP_FWD_FIFO_CERR_CH1    V_TRANSPARENT_ENCAP_FWD_FIFO_CERR_CH1(1U)
+
+#define S_PTP_TRACE_FWD_FIFO_CERR_CH1    4
+#define V_PTP_TRACE_FWD_FIFO_CERR_CH1(x) ((x) << S_PTP_TRACE_FWD_FIFO_CERR_CH1)
+#define F_PTP_TRACE_FWD_FIFO_CERR_CH1    V_PTP_TRACE_FWD_FIFO_CERR_CH1(1U)
+
+#define S_CRS_DATA_STORE_N_FWD_CH0    3
+#define V_CRS_DATA_STORE_N_FWD_CH0(x) ((x) << S_CRS_DATA_STORE_N_FWD_CH0)
+#define F_CRS_DATA_STORE_N_FWD_CH0    V_CRS_DATA_STORE_N_FWD_CH0(1U)
+
+#define S_TRACE_FWD_FIFO_CERR_CH0    2
+#define V_TRACE_FWD_FIFO_CERR_CH0(x) ((x) << S_TRACE_FWD_FIFO_CERR_CH0)
+#define F_TRACE_FWD_FIFO_CERR_CH0    V_TRACE_FWD_FIFO_CERR_CH0(1U)
+
+#define S_TRANSPARENT_ENCAP_FWD_FIFO_CERR_CH0    1
+#define V_TRANSPARENT_ENCAP_FWD_FIFO_CERR_CH0(x) ((x) << S_TRANSPARENT_ENCAP_FWD_FIFO_CERR_CH0)
+#define F_TRANSPARENT_ENCAP_FWD_FIFO_CERR_CH0    V_TRANSPARENT_ENCAP_FWD_FIFO_CERR_CH0(1U)
+
+#define S_PTP_TRACE_FWD_FIFO_CERR_CH0    0
+#define V_PTP_TRACE_FWD_FIFO_CERR_CH0(x) ((x) << S_PTP_TRACE_FWD_FIFO_CERR_CH0)
+#define F_PTP_TRACE_FWD_FIFO_CERR_CH0    V_PTP_TRACE_FWD_FIFO_CERR_CH0(1U)
 
 #define A_MPS_RX_PERR_INT_ENABLE4 0x11320
 #define A_MPS_RX_PERR_ENABLE4 0x11324
 #define A_MPS_RX_PERR_INT_CAUSE5 0x11328
 
-#define S_MPS2CRYP_RX_FIFO    26
-#define M_MPS2CRYP_RX_FIFO    0xfU
-#define V_MPS2CRYP_RX_FIFO(x) ((x) << S_MPS2CRYP_RX_FIFO)
-#define G_MPS2CRYP_RX_FIFO(x) (((x) >> S_MPS2CRYP_RX_FIFO) & M_MPS2CRYP_RX_FIFO)
+#define S_MPS2CRYP_RX_FIFO3_PERR    31
+#define V_MPS2CRYP_RX_FIFO3_PERR(x) ((x) << S_MPS2CRYP_RX_FIFO3_PERR)
+#define F_MPS2CRYP_RX_FIFO3_PERR    V_MPS2CRYP_RX_FIFO3_PERR(1U)
+
+#define S_MPS2CRYP_RX_FIFO2_PERR    30
+#define V_MPS2CRYP_RX_FIFO2_PERR(x) ((x) << S_MPS2CRYP_RX_FIFO2_PERR)
+#define F_MPS2CRYP_RX_FIFO2_PERR    V_MPS2CRYP_RX_FIFO2_PERR(1U)
+
+#define S_MPS2CRYP_RX_FIFO1_PERR    29
+#define V_MPS2CRYP_RX_FIFO1_PERR(x) ((x) << S_MPS2CRYP_RX_FIFO1_PERR)
+#define F_MPS2CRYP_RX_FIFO1_PERR    V_MPS2CRYP_RX_FIFO1_PERR(1U)
+
+#define S_MPS2CRYP_RX_FIFO0_PERR    28
+#define V_MPS2CRYP_RX_FIFO0_PERR(x) ((x) << S_MPS2CRYP_RX_FIFO0_PERR)
+#define F_MPS2CRYP_RX_FIFO0_PERR    V_MPS2CRYP_RX_FIFO0_PERR(1U)
+
+#define S_VNI_MULTICAST_SRAM2_PERR    27
+#define V_VNI_MULTICAST_SRAM2_PERR(x) ((x) << S_VNI_MULTICAST_SRAM2_PERR)
+#define F_VNI_MULTICAST_SRAM2_PERR    V_VNI_MULTICAST_SRAM2_PERR(1U)
+
+#define S_VNI_MULTICAST_SRAM1_PERR    26
+#define V_VNI_MULTICAST_SRAM1_PERR(x) ((x) << S_VNI_MULTICAST_SRAM1_PERR)
+#define F_VNI_MULTICAST_SRAM1_PERR    V_VNI_MULTICAST_SRAM1_PERR(1U)
+
+#define S_VNI_MULTICAST_SRAM0_PERR    25
+#define V_VNI_MULTICAST_SRAM0_PERR(x) ((x) << S_VNI_MULTICAST_SRAM0_PERR)
+#define F_VNI_MULTICAST_SRAM0_PERR    V_VNI_MULTICAST_SRAM0_PERR(1U)
+
+#define S_MAC_MULTICAST_SRAM4_PERR    24
+#define V_MAC_MULTICAST_SRAM4_PERR(x) ((x) << S_MAC_MULTICAST_SRAM4_PERR)
+#define F_MAC_MULTICAST_SRAM4_PERR    V_MAC_MULTICAST_SRAM4_PERR(1U)
+
+#define S_MAC_MULTICAST_SRAM3_PERR    23
+#define V_MAC_MULTICAST_SRAM3_PERR(x) ((x) << S_MAC_MULTICAST_SRAM3_PERR)
+#define F_MAC_MULTICAST_SRAM3_PERR    V_MAC_MULTICAST_SRAM3_PERR(1U)
+
+#define S_MAC_MULTICAST_SRAM2_PERR    22
+#define V_MAC_MULTICAST_SRAM2_PERR(x) ((x) << S_MAC_MULTICAST_SRAM2_PERR)
+#define F_MAC_MULTICAST_SRAM2_PERR    V_MAC_MULTICAST_SRAM2_PERR(1U)
+
+#define S_MAC_MULTICAST_SRAM1_PERR    21
+#define V_MAC_MULTICAST_SRAM1_PERR(x) ((x) << S_MAC_MULTICAST_SRAM1_PERR)
+#define F_MAC_MULTICAST_SRAM1_PERR    V_MAC_MULTICAST_SRAM1_PERR(1U)
+
+#define S_MAC_MULTICAST_SRAM0_PERR    20
+#define V_MAC_MULTICAST_SRAM0_PERR(x) ((x) << S_MAC_MULTICAST_SRAM0_PERR)
+#define F_MAC_MULTICAST_SRAM0_PERR    V_MAC_MULTICAST_SRAM0_PERR(1U)
+
+#define S_MEM_WRAP_IPSEC_HDR_UPD_FIFO3_PERR    19
+#define V_MEM_WRAP_IPSEC_HDR_UPD_FIFO3_PERR(x) ((x) << S_MEM_WRAP_IPSEC_HDR_UPD_FIFO3_PERR)
+#define F_MEM_WRAP_IPSEC_HDR_UPD_FIFO3_PERR    V_MEM_WRAP_IPSEC_HDR_UPD_FIFO3_PERR(1U)
+
+#define S_MEM_WRAP_IPSEC_HDR_UPD_FIFO2_PERR    18
+#define V_MEM_WRAP_IPSEC_HDR_UPD_FIFO2_PERR(x) ((x) << S_MEM_WRAP_IPSEC_HDR_UPD_FIFO2_PERR)
+#define F_MEM_WRAP_IPSEC_HDR_UPD_FIFO2_PERR    V_MEM_WRAP_IPSEC_HDR_UPD_FIFO2_PERR(1U)
+
+#define S_MEM_WRAP_IPSEC_HDR_UPD_FIFO1_PERR    17
+#define V_MEM_WRAP_IPSEC_HDR_UPD_FIFO1_PERR(x) ((x) << S_MEM_WRAP_IPSEC_HDR_UPD_FIFO1_PERR)
+#define F_MEM_WRAP_IPSEC_HDR_UPD_FIFO1_PERR    V_MEM_WRAP_IPSEC_HDR_UPD_FIFO1_PERR(1U)
+
+#define S_MEM_WRAP_IPSEC_HDR_UPD_FIFO0_PERR    16
+#define V_MEM_WRAP_IPSEC_HDR_UPD_FIFO0_PERR(x) ((x) << S_MEM_WRAP_IPSEC_HDR_UPD_FIFO0_PERR)
+#define F_MEM_WRAP_IPSEC_HDR_UPD_FIFO0_PERR    V_MEM_WRAP_IPSEC_HDR_UPD_FIFO0_PERR(1U)
+
+#define S_MEM_WRAP_CR2MPS_RX_FIFO3_PERR    15
+#define V_MEM_WRAP_CR2MPS_RX_FIFO3_PERR(x) ((x) << S_MEM_WRAP_CR2MPS_RX_FIFO3_PERR)
+#define F_MEM_WRAP_CR2MPS_RX_FIFO3_PERR    V_MEM_WRAP_CR2MPS_RX_FIFO3_PERR(1U)
+
+#define S_MEM_WRAP_CR2MPS_RX_FIFO2_PERR    14
+#define V_MEM_WRAP_CR2MPS_RX_FIFO2_PERR(x) ((x) << S_MEM_WRAP_CR2MPS_RX_FIFO2_PERR)
+#define F_MEM_WRAP_CR2MPS_RX_FIFO2_PERR    V_MEM_WRAP_CR2MPS_RX_FIFO2_PERR(1U)
+
+#define S_MEM_WRAP_CR2MPS_RX_FIFO1_PERR    13
+#define V_MEM_WRAP_CR2MPS_RX_FIFO1_PERR(x) ((x) << S_MEM_WRAP_CR2MPS_RX_FIFO1_PERR)
+#define F_MEM_WRAP_CR2MPS_RX_FIFO1_PERR    V_MEM_WRAP_CR2MPS_RX_FIFO1_PERR(1U)
+
+#define S_MEM_WRAP_CR2MPS_RX_FIFO0_PERR    12
+#define V_MEM_WRAP_CR2MPS_RX_FIFO0_PERR(x) ((x) << S_MEM_WRAP_CR2MPS_RX_FIFO0_PERR)
+#define F_MEM_WRAP_CR2MPS_RX_FIFO0_PERR    V_MEM_WRAP_CR2MPS_RX_FIFO0_PERR(1U)
 
-#define S_RX_OUT    20
-#define M_RX_OUT    0x3fU
-#define V_RX_OUT(x) ((x) << S_RX_OUT)
-#define G_RX_OUT(x) (((x) >> S_RX_OUT) & M_RX_OUT)
+#define S_MEM_WRAP_NON_IPSEC_FIFO3_PERR    11
+#define V_MEM_WRAP_NON_IPSEC_FIFO3_PERR(x) ((x) << S_MEM_WRAP_NON_IPSEC_FIFO3_PERR)
+#define F_MEM_WRAP_NON_IPSEC_FIFO3_PERR    V_MEM_WRAP_NON_IPSEC_FIFO3_PERR(1U)
 
-#define S_MEM_WRAP    0
-#define M_MEM_WRAP    0xfffffU
-#define V_MEM_WRAP(x) ((x) << S_MEM_WRAP)
-#define G_MEM_WRAP(x) (((x) >> S_MEM_WRAP) & M_MEM_WRAP)
+#define S_MEM_WRAP_NON_IPSEC_FIFO2_PERR    10
+#define V_MEM_WRAP_NON_IPSEC_FIFO2_PERR(x) ((x) << S_MEM_WRAP_NON_IPSEC_FIFO2_PERR)
+#define F_MEM_WRAP_NON_IPSEC_FIFO2_PERR    V_MEM_WRAP_NON_IPSEC_FIFO2_PERR(1U)
+
+#define S_MEM_WRAP_NON_IPSEC_FIFO1_PERR    9
+#define V_MEM_WRAP_NON_IPSEC_FIFO1_PERR(x) ((x) << S_MEM_WRAP_NON_IPSEC_FIFO1_PERR)
+#define F_MEM_WRAP_NON_IPSEC_FIFO1_PERR    V_MEM_WRAP_NON_IPSEC_FIFO1_PERR(1U)
+
+#define S_MEM_WRAP_NON_IPSEC_FIFO0_PERR    8
+#define V_MEM_WRAP_NON_IPSEC_FIFO0_PERR(x) ((x) << S_MEM_WRAP_NON_IPSEC_FIFO0_PERR)
+#define F_MEM_WRAP_NON_IPSEC_FIFO0_PERR    V_MEM_WRAP_NON_IPSEC_FIFO0_PERR(1U)
+
+#define S_MEM_WRAP_TP_DB_REQ_FIFO3_PERR    7
+#define V_MEM_WRAP_TP_DB_REQ_FIFO3_PERR(x) ((x) << S_MEM_WRAP_TP_DB_REQ_FIFO3_PERR)
+#define F_MEM_WRAP_TP_DB_REQ_FIFO3_PERR    V_MEM_WRAP_TP_DB_REQ_FIFO3_PERR(1U)
+
+#define S_MEM_WRAP_TP_DB_REQ_FIFO2_PERR    6
+#define V_MEM_WRAP_TP_DB_REQ_FIFO2_PERR(x) ((x) << S_MEM_WRAP_TP_DB_REQ_FIFO2_PERR)
+#define F_MEM_WRAP_TP_DB_REQ_FIFO2_PERR    V_MEM_WRAP_TP_DB_REQ_FIFO2_PERR(1U)
+
+#define S_MEM_WRAP_TP_DB_REQ_FIFO1_PERR    5
+#define V_MEM_WRAP_TP_DB_REQ_FIFO1_PERR(x) ((x) << S_MEM_WRAP_TP_DB_REQ_FIFO1_PERR)
+#define F_MEM_WRAP_TP_DB_REQ_FIFO1_PERR    V_MEM_WRAP_TP_DB_REQ_FIFO1_PERR(1U)
+
+#define S_MEM_WRAP_TP_DB_REQ_FIFO0_PERR    4
+#define V_MEM_WRAP_TP_DB_REQ_FIFO0_PERR(x) ((x) << S_MEM_WRAP_TP_DB_REQ_FIFO0_PERR)
+#define F_MEM_WRAP_TP_DB_REQ_FIFO0_PERR    V_MEM_WRAP_TP_DB_REQ_FIFO0_PERR(1U)
+
+#define S_MEM_WRAP_CNTRL_FIFO3_PERR    3
+#define V_MEM_WRAP_CNTRL_FIFO3_PERR(x) ((x) << S_MEM_WRAP_CNTRL_FIFO3_PERR)
+#define F_MEM_WRAP_CNTRL_FIFO3_PERR    V_MEM_WRAP_CNTRL_FIFO3_PERR(1U)
+
+#define S_MEM_WRAP_CNTRL_FIFO2_PERR    2
+#define V_MEM_WRAP_CNTRL_FIFO2_PERR(x) ((x) << S_MEM_WRAP_CNTRL_FIFO2_PERR)
+#define F_MEM_WRAP_CNTRL_FIFO2_PERR    V_MEM_WRAP_CNTRL_FIFO2_PERR(1U)
+
+#define S_MEM_WRAP_CNTRL_FIFO1_PERR    1
+#define V_MEM_WRAP_CNTRL_FIFO1_PERR(x) ((x) << S_MEM_WRAP_CNTRL_FIFO1_PERR)
+#define F_MEM_WRAP_CNTRL_FIFO1_PERR    V_MEM_WRAP_CNTRL_FIFO1_PERR(1U)
+
+#define S_MEM_WRAP_CNTRL_FIFO0_PERR    0
+#define V_MEM_WRAP_CNTRL_FIFO0_PERR(x) ((x) << S_MEM_WRAP_CNTRL_FIFO0_PERR)
+#define F_MEM_WRAP_CNTRL_FIFO0_PERR    V_MEM_WRAP_CNTRL_FIFO0_PERR(1U)
 
 #define A_MPS_RX_PERR_INT_ENABLE5 0x1132c
 #define A_MPS_RX_PERR_ENABLE5 0x11330
 #define A_MPS_RX_PERR_INT_CAUSE6 0x11334
 
-#define S_MPS_RX_MEM_WRAP    0
-#define M_MPS_RX_MEM_WRAP    0x1ffffffU
-#define V_MPS_RX_MEM_WRAP(x) ((x) << S_MPS_RX_MEM_WRAP)
-#define G_MPS_RX_MEM_WRAP(x) (((x) >> S_MPS_RX_MEM_WRAP) & M_MPS_RX_MEM_WRAP)
+#define S_T7_MEM_WRAP_IPSEC_HDR_UPD_FIFO3_PERR    23
+#define V_T7_MEM_WRAP_IPSEC_HDR_UPD_FIFO3_PERR(x) ((x) << S_T7_MEM_WRAP_IPSEC_HDR_UPD_FIFO3_PERR)
+#define F_T7_MEM_WRAP_IPSEC_HDR_UPD_FIFO3_PERR    V_T7_MEM_WRAP_IPSEC_HDR_UPD_FIFO3_PERR(1U)
+
+#define S_T7_MEM_WRAP_IPSEC_HDR_UPD_FIFO2_PERR    22
+#define V_T7_MEM_WRAP_IPSEC_HDR_UPD_FIFO2_PERR(x) ((x) << S_T7_MEM_WRAP_IPSEC_HDR_UPD_FIFO2_PERR)
+#define F_T7_MEM_WRAP_IPSEC_HDR_UPD_FIFO2_PERR    V_T7_MEM_WRAP_IPSEC_HDR_UPD_FIFO2_PERR(1U)
+
+#define S_T7_MEM_WRAP_IPSEC_HDR_UPD_FIFO1_PERR    21
+#define V_T7_MEM_WRAP_IPSEC_HDR_UPD_FIFO1_PERR(x) ((x) << S_T7_MEM_WRAP_IPSEC_HDR_UPD_FIFO1_PERR)
+#define F_T7_MEM_WRAP_IPSEC_HDR_UPD_FIFO1_PERR    V_T7_MEM_WRAP_IPSEC_HDR_UPD_FIFO1_PERR(1U)
+
+#define S_T7_MEM_WRAP_IPSEC_HDR_UPD_FIFO0_PERR    20
+#define V_T7_MEM_WRAP_IPSEC_HDR_UPD_FIFO0_PERR(x) ((x) << S_T7_MEM_WRAP_IPSEC_HDR_UPD_FIFO0_PERR)
+#define F_T7_MEM_WRAP_IPSEC_HDR_UPD_FIFO0_PERR    V_T7_MEM_WRAP_IPSEC_HDR_UPD_FIFO0_PERR(1U)
+
+#define S_MEM_WRAP_CR2MPS_UPDTD_HDR_FIFO3_PERR    19
+#define V_MEM_WRAP_CR2MPS_UPDTD_HDR_FIFO3_PERR(x) ((x) << S_MEM_WRAP_CR2MPS_UPDTD_HDR_FIFO3_PERR)
+#define F_MEM_WRAP_CR2MPS_UPDTD_HDR_FIFO3_PERR    V_MEM_WRAP_CR2MPS_UPDTD_HDR_FIFO3_PERR(1U)
+
+#define S_MEM_WRAP_CR2MPS_UPDTD_HDR_FIFO2_PERR    18
+#define V_MEM_WRAP_CR2MPS_UPDTD_HDR_FIFO2_PERR(x) ((x) << S_MEM_WRAP_CR2MPS_UPDTD_HDR_FIFO2_PERR)
+#define F_MEM_WRAP_CR2MPS_UPDTD_HDR_FIFO2_PERR    V_MEM_WRAP_CR2MPS_UPDTD_HDR_FIFO2_PERR(1U)
+
+#define S_MEM_WRAP_CR2MPS_UPDTD_HDR_FIFO1_PERR    17
+#define V_MEM_WRAP_CR2MPS_UPDTD_HDR_FIFO1_PERR(x) ((x) << S_MEM_WRAP_CR2MPS_UPDTD_HDR_FIFO1_PERR)
+#define F_MEM_WRAP_CR2MPS_UPDTD_HDR_FIFO1_PERR    V_MEM_WRAP_CR2MPS_UPDTD_HDR_FIFO1_PERR(1U)
+
+#define S_MEM_WRAP_CR2MPS_UPDTD_HDR_FIFO0_PERR    16
+#define V_MEM_WRAP_CR2MPS_UPDTD_HDR_FIFO0_PERR(x) ((x) << S_MEM_WRAP_CR2MPS_UPDTD_HDR_FIFO0_PERR)
+#define F_MEM_WRAP_CR2MPS_UPDTD_HDR_FIFO0_PERR    V_MEM_WRAP_CR2MPS_UPDTD_HDR_FIFO0_PERR(1U)
 
 #define A_MPS_RX_PERR_INT_ENABLE6 0x11338
 #define A_MPS_RX_PERR_ENABLE6 0x1133c
@@ -45844,6 +46424,18 @@
 #define V_SLVFIFO(x) ((x) << S_SLVFIFO)
 #define F_SLVFIFO    V_SLVFIFO(1U)
 
+#define S_T7_MSTTXFIFO    22
+#define V_T7_MSTTXFIFO(x) ((x) << S_T7_MSTTXFIFO)
+#define F_T7_MSTTXFIFO    V_T7_MSTTXFIFO(1U)
+
+#define S_T7_MSTRXFIFO    21
+#define V_T7_MSTRXFIFO(x) ((x) << S_T7_MSTRXFIFO)
+#define F_T7_MSTRXFIFO    V_T7_MSTRXFIFO(1U)
+
+#define S_T7_SLVFIFO    20
+#define V_T7_SLVFIFO(x) ((x) << S_T7_SLVFIFO)
+#define F_T7_SLVFIFO    V_T7_SLVFIFO(1U)
+
 #define A_SMB_PERR_INJ 0x1909c
 
 #define S_MSTTXINJDATAERR    3
@@ -46167,20 +46759,20 @@
 #define V_UART_CLKDIV(x) ((x) << S_UART_CLKDIV)
 #define G_UART_CLKDIV(x) (((x) >> S_UART_CLKDIV) & M_UART_CLKDIV)
 
-#define S_T7_STOPBITS    25
-#define M_T7_STOPBITS    0x3U
-#define V_T7_STOPBITS(x) ((x) << S_T7_STOPBITS)
-#define G_T7_STOPBITS(x) (((x) >> S_T7_STOPBITS) & M_T7_STOPBITS)
+#define S_T7_UART_STOPBITS    25
+#define M_T7_UART_STOPBITS    0x3U
+#define V_T7_UART_STOPBITS(x) ((x) << S_T7_UART_STOPBITS)
+#define G_T7_UART_STOPBITS(x) (((x) >> S_T7_UART_STOPBITS) & M_T7_UART_STOPBITS)
 
-#define S_T7_PARITY    23
-#define M_T7_PARITY    0x3U
-#define V_T7_PARITY(x) ((x) << S_T7_PARITY)
-#define G_T7_PARITY(x) (((x) >> S_T7_PARITY) & M_T7_PARITY)
+#define S_T7_UART_PARITY    23
+#define M_T7_UART_PARITY    0x3U
+#define V_T7_UART_PARITY(x) ((x) << S_T7_UART_PARITY)
+#define G_T7_UART_PARITY(x) (((x) >> S_T7_UART_PARITY) & M_T7_UART_PARITY)
 
-#define S_T7_DATABITS    19
-#define M_T7_DATABITS    0xfU
-#define V_T7_DATABITS(x) ((x) << S_T7_DATABITS)
-#define G_T7_DATABITS(x) (((x) >> S_T7_DATABITS) & M_T7_DATABITS)
+#define S_T7_UART_DATABITS    19
+#define M_T7_UART_DATABITS    0xfU
+#define V_T7_UART_DATABITS(x) ((x) << S_T7_UART_DATABITS)
+#define G_T7_UART_DATABITS(x) (((x) >> S_T7_UART_DATABITS) & M_T7_UART_DATABITS)
 
 #define S_T7_UART_CLKDIV    0
 #define M_T7_UART_CLKDIV    0x3ffffU
@@ -46607,13 +47199,13 @@
 #define V_T7_SE_CNT_MISMATCH_0(x) ((x) << S_T7_SE_CNT_MISMATCH_0)
 #define F_T7_SE_CNT_MISMATCH_0    V_T7_SE_CNT_MISMATCH_0(1U)
 
-#define S_ENABLE_CTX_3    7
-#define V_ENABLE_CTX_3(x) ((x) << S_ENABLE_CTX_3)
-#define F_ENABLE_CTX_3    V_ENABLE_CTX_3(1U)
+#define S_T7_ENABLE_CTX_3    7
+#define V_T7_ENABLE_CTX_3(x) ((x) << S_T7_ENABLE_CTX_3)
+#define F_T7_ENABLE_CTX_3    V_T7_ENABLE_CTX_3(1U)
 
-#define S_ENABLE_CTX_2    6
-#define V_ENABLE_CTX_2(x) ((x) << S_ENABLE_CTX_2)
-#define F_ENABLE_CTX_2    V_ENABLE_CTX_2(1U)
+#define S_T7_ENABLE_CTX_2    6
+#define V_T7_ENABLE_CTX_2(x) ((x) << S_T7_ENABLE_CTX_2)
+#define F_T7_ENABLE_CTX_2    V_T7_ENABLE_CTX_2(1U)
 
 #define S_T7_ENABLE_CTX_1    5
 #define V_T7_ENABLE_CTX_1(x) ((x) << S_T7_ENABLE_CTX_1)
@@ -46623,13 +47215,13 @@
 #define V_T7_ENABLE_CTX_0(x) ((x) << S_T7_ENABLE_CTX_0)
 #define F_T7_ENABLE_CTX_0    V_T7_ENABLE_CTX_0(1U)
 
-#define S_ENABLE_ALN_SDC_ERR_3    3
-#define V_ENABLE_ALN_SDC_ERR_3(x) ((x) << S_ENABLE_ALN_SDC_ERR_3)
-#define F_ENABLE_ALN_SDC_ERR_3    V_ENABLE_ALN_SDC_ERR_3(1U)
+#define S_T7_ENABLE_ALN_SDC_ERR_3    3
+#define V_T7_ENABLE_ALN_SDC_ERR_3(x) ((x) << S_T7_ENABLE_ALN_SDC_ERR_3)
+#define F_T7_ENABLE_ALN_SDC_ERR_3    V_T7_ENABLE_ALN_SDC_ERR_3(1U)
 
-#define S_ENABLE_ALN_SDC_ERR_2    2
-#define V_ENABLE_ALN_SDC_ERR_2(x) ((x) << S_ENABLE_ALN_SDC_ERR_2)
-#define F_ENABLE_ALN_SDC_ERR_2    V_ENABLE_ALN_SDC_ERR_2(1U)
+#define S_T7_ENABLE_ALN_SDC_ERR_2    2
+#define V_T7_ENABLE_ALN_SDC_ERR_2(x) ((x) << S_T7_ENABLE_ALN_SDC_ERR_2)
+#define F_T7_ENABLE_ALN_SDC_ERR_2    V_T7_ENABLE_ALN_SDC_ERR_2(1U)
 
 #define S_T7_ENABLE_ALN_SDC_ERR_1    1
 #define V_T7_ENABLE_ALN_SDC_ERR_1(x) ((x) << S_T7_ENABLE_ALN_SDC_ERR_1)
@@ -78548,6 +79140,17 @@
 #define A_MAC_MTIP_MAC400G_0_MTIP_MAC_ADDR_1 0x38210
 #define A_MAC_MTIP_MAC400G_0_MTIP_FRM_LENGTH 0x38214
 #define A_MAC_MTIP_MAC400G_0_MTIP_RX_FIFO_SECTIONS 0x3821c
+
+#define S_T7_MAC_EMPTY    16
+#define M_T7_MAC_EMPTY    0xffffU
+#define V_T7_MAC_EMPTY(x) ((x) << S_T7_MAC_EMPTY)
+#define G_T7_MAC_EMPTY(x) (((x) >> S_T7_MAC_EMPTY) & M_T7_MAC_EMPTY)
+
+#define S_T7_MAC_AVAIL    0
+#define M_T7_MAC_AVAIL    0xffffU
+#define V_T7_MAC_AVAIL(x) ((x) << S_T7_MAC_AVAIL)
+#define G_T7_MAC_AVAIL(x) (((x) >> S_T7_MAC_AVAIL) & M_T7_MAC_AVAIL)
+
 #define A_MAC_MTIP_MAC400G_0_MTIP_TX_FIFO_SECTIONS 0x38220
 #define A_MAC_MTIP_MAC400G_0_MTIP_RX_FIFO_ALMOST_F_E 0x38224
 #define A_MAC_MTIP_MAC400G_0_MTIP_TX_FIFO_ALMOST_F_E 0x38228
@@ -82543,7 +83146,6 @@
 #define F_DMA_PL_RST_N    V_DMA_PL_RST_N(1U)
 
 #define A_ARM_PLM_RID_CFG 0x4703c
-#define A_ARM_PLM_EROM_CFG 0x47040
 #define A_ARM_PL_ARM_HDR_CFG 0x4704c
 #define A_ARM_RC_INT_STATUS 0x4705c
 
@@ -85733,20 +86335,7 @@
 #define V_T7_ECC_UE_INT_CAUSE(x) ((x) << S_T7_ECC_UE_INT_CAUSE)
 #define F_T7_ECC_UE_INT_CAUSE    V_T7_ECC_UE_INT_CAUSE(1U)
 
-#define A_MC_P_ECC_UE_INT_ENABLE 0x49324
-
-#define S_BIST_RSP_SRAM_UERR_ENABLE    0
-#define V_BIST_RSP_SRAM_UERR_ENABLE(x) ((x) << S_BIST_RSP_SRAM_UERR_ENABLE)
-#define F_BIST_RSP_SRAM_UERR_ENABLE    V_BIST_RSP_SRAM_UERR_ENABLE(1U)
-
-#define A_MC_P_ECC_UE_INT_CAUSE 0x49328
-
-#define S_BIST_RSP_SRAM_UERR_CAUSE    0
-#define V_BIST_RSP_SRAM_UERR_CAUSE(x) ((x) << S_BIST_RSP_SRAM_UERR_CAUSE)
-#define F_BIST_RSP_SRAM_UERR_CAUSE    V_BIST_RSP_SRAM_UERR_CAUSE(1U)
-
 #define A_T7_MC_P_ECC_STATUS 0x4932c
-#define A_T7_MC_P_PHY_CTRL 0x49330
 #define A_T7_MC_P_STATIC_CFG_STATUS 0x49334
 
 #define S_DFIFREQRATIO    27
@@ -86100,6 +86689,7 @@
 #define V_FLIP_BIT_POS0(x) ((x) << S_FLIP_BIT_POS0)
 #define G_FLIP_BIT_POS0(x) (((x) >> S_FLIP_BIT_POS0) & M_FLIP_BIT_POS0)
 
+#define A_MC_REGB_DDRC_CH1_ECCSTAT 0x11608
 #define A_MC_REGB_DDRC_CH1_ECCCTL 0x1160c
 #define A_MC_REGB_DDRC_CH1_ECCERRCNT 0x11610
 #define A_MC_REGB_DDRC_CH1_ECCCADDR0 0x11614
diff --git a/sys/dev/cxgbe/firmware/t7fw_cfg.txt b/sys/dev/cxgbe/firmware/t7fw_cfg.txt
index 499af3675bd9..70b05da04a23 100644
--- a/sys/dev/cxgbe/firmware/t7fw_cfg.txt
+++ b/sys/dev/cxgbe/firmware/t7fw_cfg.txt
@@ -114,7 +114,8 @@
 
 	reg[0x7dc0] = 0x0e2f8849	# TP_SHIFT_CNT
 
-    reg[0x46004] = 0x3/0x3      #Crypto core reset
+    reg[0x46004] = 0x3/0x3      # Crypto core reset
+	reg[0x46000] = 0xa/0xe      # 16K ESH Hi Extraction window
 
 	#Tick granularities in kbps
 	tsch_ticks = 100000, 10000, 1000, 10
@@ -192,14 +193,15 @@
 	reg[0x19250] = 0x0/0x3   # Termimate_msg = 0
 	                         # Terminate_with_err = 0
 
-	gc_disable = 3 # 3 - disable gc for hma/mc1 and mc0,
+	#Enabling GC for HMA
+	gc_disable = 1 # 3 - disable gc for hma/mc1 and mc0,
 				    # 2 - disable gc for mc1/hma enable mc0,
 				    # 1 - enable gc for mc1/hma disable mc0,
 				    # 0 - enable gc for mc1/hma and for mc0,
 				    # default gc enabled.
 
 	# HMA configuration (uncomment following lines to enable HMA)
-	hma_size = 92 			# Size (in MBs) of host memory expected
+	hma_size = 128 			# Size (in MBs) of host memory expected
 	hma_regions = 	iscsi,rrq,tls,ddp,pmrx,stag,pbl,rq	# What all regions to place in host memory
 
     #mc[0]=0
@@ -429,7 +431,7 @@
 	nethofld = 1024		# number of user mode ethernet flow contexts
 	ncrypto_lookaside = 32
 	nclip = 320		# number of clip region entries
-	nfilter = 480		# number of filter region entries
+	nfilter = 448		# number of filter region entries
 	nserver = 480		# number of server region entries
 	nhash = 12288		# number of hash region entries
 	nhpfilter = 64		# number of high priority filter region entries
@@ -505,12 +507,20 @@
 	nfilter = 16		# number of filter region entries
 	#nhpfilter = 16		# number of high priority filter region entries
 	niqflint = 34		# NPORTS*NCPUS + NMSIX_EXTRA
-	nethctrl = 32		# NPORTS*NCPUS
-	neq = 64		# NPORTS*NCPUS * 2 (FL, ETHCTRL/TX)
+	nethctrl = 128		# NPORTS*NCPUS
+	neq = 256		# NPORTS*NCPUS * 2 (FL, ETHCTRL/TX)
 	nserver = 16
 	nhash = 1024
 	tp_l2t = 512
 	protocol = nic_vm, ofld, rddp, rdmac, tlskeys, ipsec_inline, rocev2, nvme_tcp
+	tp_ddp = 1
+	tp_ddp_iscsi = 1
+	tp_tls_key = 1
+	tp_stag = 1
+	tp_pbl = 3
+	tp_rq = 4
+	tp_rrq = 2
+	tp_srq = 96
 
 # The following function, 1023, is not an actual PCIE function but is used to
 # configure and reserve firmware internal resources that come from the global
@@ -523,7 +533,7 @@
 	cmask = all		# access to all channels
 	pmask = all		# access to all four ports ...
 	nexactf = 8		# NPORTS + DCBX +
-	nfilter = 16		# number of filter region entries
+	nfilter = 48		# number of filter region entries
 	#nhpfilter = 0		# number of high priority filter region entries
 
 
@@ -594,7 +604,7 @@
 #		Bytes)
 #
 [port "0"]
-	#dcb = ppp, dcbx, b2b	# configure for DCB PPP and enable DCBX offload
+	#dcb = ppp, dcbx	# configure for DCB PPP and enable DCBX offload
 	hwm = 30
 	lwm = 15
 	dwm = 30
@@ -604,7 +614,7 @@
 
 
 [port "1"]
-	#dcb = ppp, dcbx, b2b
+	#dcb = ppp, dcbx
 	hwm = 30
 	lwm = 15
 	dwm = 30
@@ -613,7 +623,7 @@
 	dcb_app_tlv[2] = 3260, socketnum, 5
 
 [port "2"]
-	#dcb = ppp, dcbx, b2b	# configure for DCB PPP and enable DCBX offload
+	#dcb = ppp, dcbx	# configure for DCB PPP and enable DCBX offload
 	hwm = 30
 	lwm = 15
 	dwm = 30
@@ -623,7 +633,7 @@
 
 
 [port "3"]
-	#dcb = ppp, dcbx, b2b
+	#dcb = ppp, dcbx
 	hwm = 30
 	lwm = 15
 	dwm = 30
@@ -633,7 +643,7 @@
 
 [fini]
 	version = 0x1425001d
-	checksum = 0x684e23fb
+	checksum = 0x3671da3b
 
 # Total resources used by above allocations:
 #   Virtual Interfaces: 104
diff --git a/sys/dev/cxgbe/firmware/t7fw_cfg_uwire.txt b/sys/dev/cxgbe/firmware/t7fw_cfg_uwire.txt
index 0bca1c194af8..b1f5129238eb 100644
--- a/sys/dev/cxgbe/firmware/t7fw_cfg_uwire.txt
+++ b/sys/dev/cxgbe/firmware/t7fw_cfg_uwire.txt
@@ -114,7 +114,8 @@
 
 	reg[0x7dc0] = 0x0e2f8849	# TP_SHIFT_CNT
 
-    reg[0x46004] = 0x3/0x3      #Crypto core reset
+    reg[0x46004] = 0x3/0x3      # Crypto core reset
+	reg[0x46000] = 0xa/0xe      # 16K ESH Hi Extraction window
 
 	#Tick granularities in kbps
 	tsch_ticks = 100000, 10000, 1000, 10
@@ -192,14 +193,15 @@
 	reg[0x19250] = 0x0/0x3   # Termimate_msg = 0
 	                         # Terminate_with_err = 0
 
-	gc_disable = 3 # 3 - disable gc for hma/mc1 and mc0,
+	#Enabling GC for HMA
+	gc_disable = 1 # 3 - disable gc for hma/mc1 and mc0,
 				    # 2 - disable gc for mc1/hma enable mc0,
 				    # 1 - enable gc for mc1/hma disable mc0,
 				    # 0 - enable gc for mc1/hma and for mc0,
 				    # default gc enabled.
 
 	# HMA configuration (uncomment following lines to enable HMA)
-	hma_size = 92 			# Size (in MBs) of host memory expected
+	hma_size = 128 			# Size (in MBs) of host memory expected
 	hma_regions = 	iscsi,rrq,tls,ddp,pmrx,stag,pbl,rq	# What all regions to place in host memory
 
     #mc[0]=0
@@ -429,7 +431,7 @@
 	nethofld = 1024		# number of user mode ethernet flow contexts
 	ncrypto_lookaside = 32
 	nclip = 320		# number of clip region entries
-	nfilter = 480		# number of filter region entries
+	nfilter = 448		# number of filter region entries
 	nserver = 480		# number of server region entries
 	nhash = 12288		# number of hash region entries
 	nhpfilter = 64		# number of high priority filter region entries
@@ -505,12 +507,20 @@
 	nfilter = 16		# number of filter region entries
 	#nhpfilter = 16		# number of high priority filter region entries
 	niqflint = 34		# NPORTS*NCPUS + NMSIX_EXTRA
-	nethctrl = 32		# NPORTS*NCPUS
-	neq = 64		# NPORTS*NCPUS * 2 (FL, ETHCTRL/TX)
+	nethctrl = 128		# NPORTS*NCPUS
+	neq = 256		# NPORTS*NCPUS * 2 (FL, ETHCTRL/TX)
 	nserver = 16
 	nhash = 1024
 	tp_l2t = 512
 	protocol = nic_vm, ofld, rddp, rdmac, tlskeys, ipsec_inline, rocev2, nvme_tcp
+	tp_ddp = 1
+	tp_ddp_iscsi = 1
+	tp_tls_key = 1
+	tp_stag = 1
+	tp_pbl = 3
+	tp_rq = 4
+	tp_rrq = 2
+	tp_srq = 96
 
 # The following function, 1023, is not an actual PCIE function but is used to
 # configure and reserve firmware internal resources that come from the global
@@ -523,7 +533,7 @@
 	cmask = all		# access to all channels
 	pmask = all		# access to all four ports ...
 	nexactf = 8		# NPORTS + DCBX +
-	nfilter = 16		# number of filter region entries
+	nfilter = 48		# number of filter region entries
 	#nhpfilter = 0		# number of high priority filter region entries
 
 
@@ -633,7 +643,7 @@
 
 [fini]
 	version = 0x1425001d
-	checksum = 0x5cab62d4
+	checksum = 0x96513217
 
 # Total resources used by above allocations:
 #   Virtual Interfaces: 104
diff --git a/usr.sbin/cxgbetool/reg_defs_t7.c b/usr.sbin/cxgbetool/reg_defs_t7.c
index 338c75946b1d..1fdcc7ed62e6 100644
--- a/usr.sbin/cxgbetool/reg_defs_t7.c
+++ b/usr.sbin/cxgbetool/reg_defs_t7.c
@@ -1,6 +1,6 @@
 /* This file is automatically generated --- changes will be lost */
-/* Generation Date : Tue Oct 28 05:24:53 PM IST 2025 */
-/* Directory name: t7_sw_reg.txt, Changeset: 5946:0b60ff298e7d */
+/* Generation Date : Thu Dec 11 08:42:53 PM IST 2025 */
+/* Directory name: t7_sw_reg.txt, Changeset: 5950:7c934148528c */
 
 struct reg_info t7_sge_regs[] = {
 	{ "SGE_PF_KDOORBELL", 0x1e000, 0 },
@@ -5785,7 +5785,6 @@ struct reg_info t7_ma_regs[] = {
 		{ "CL1_WR_DATA_TO_EN", 1, 1 },
 		{ "CL0_WR_DATA_TO_EN", 0, 1 },
 	{ "MA_WRITE_TIMEOUT_ERROR_STATUS", 0x78d8, 0 },
-		{ "FUTURE_CEXPANSION_WTS", 31, 1 },
 		{ "CL14_WR_CMD_TO_ERROR", 30, 1 },
 		{ "CL13_WR_CMD_TO_ERROR", 29, 1 },
 		{ "CL12_WR_CMD_TO_ERROR", 28, 1 },
@@ -5801,7 +5800,6 @@ struct reg_info t7_ma_regs[] = {
 		{ "CL2_WR_CMD_TO_ERROR", 18, 1 },
 		{ "CL1_WR_CMD_TO_ERROR", 17, 1 },
 		{ "CL0_WR_CMD_TO_ERROR", 16, 1 },
-		{ "FUTURE_DEXPANSION_WTS", 15, 1 },
 		{ "CL14_WR_DATA_TO_ERROR", 14, 1 },
 		{ "CL13_WR_DATA_TO_ERROR", 13, 1 },
 		{ "CL12_WR_DATA_TO_ERROR", 12, 1 },
@@ -5818,7 +5816,6 @@ struct reg_info t7_ma_regs[] = {
 		{ "CL1_WR_DATA_TO_ERROR", 1, 1 },
 		{ "CL0_WR_DATA_TO_ERROR", 0, 1 },
 	{ "MA_READ_TIMEOUT_ERROR_ENABLE", 0x78dc, 0 },
-		{ "FUTURE_CEXPANSION_RTE", 31, 1 },
 		{ "CL14_RD_CMD_TO_EN", 30, 1 },
 		{ "CL13_RD_CMD_TO_EN", 29, 1 },
 		{ "CL12_RD_CMD_TO_EN", 28, 1 },
@@ -5834,7 +5831,6 @@ struct reg_info t7_ma_regs[] = {
 		{ "CL2_RD_CMD_TO_EN", 18, 1 },
 		{ "CL1_RD_CMD_TO_EN", 17, 1 },
 		{ "CL0_RD_CMD_TO_EN", 16, 1 },
-		{ "FUTURE_DEXPANSION_RTE", 15, 1 },
 		{ "CL14_RD_DATA_TO_EN", 14, 1 },
 		{ "CL13_RD_DATA_TO_EN", 13, 1 },
 		{ "CL12_RD_DATA_TO_EN", 12, 1 },
@@ -5851,7 +5847,6 @@ struct reg_info t7_ma_regs[] = {
 		{ "CL1_RD_DATA_TO_EN", 1, 1 },
 		{ "CL0_RD_DATA_TO_EN", 0, 1 },
 	{ "MA_READ_TIMEOUT_ERROR_STATUS", 0x78e0, 0 },
-		{ "FUTURE_CEXPANSION_RTS", 31, 1 },
 		{ "CL14_RD_CMD_TO_ERROR", 30, 1 },
 		{ "CL13_RD_CMD_TO_ERROR", 29, 1 },
 		{ "CL12_RD_CMD_TO_ERROR", 28, 1 },
@@ -5867,7 +5862,7 @@ struct reg_info t7_ma_regs[] = {
 		{ "CL2_RD_CMD_TO_ERROR", 18, 1 },
 		{ "CL1_RD_CMD_TO_ERROR", 17, 1 },
 		{ "CL0_RD_CMD_TO_ERROR", 16, 1 },
-		{ "FUTURE_DEXPANSION_RTS", 14, 2 },
+		{ "CL14_RD_DATA_TO_ERROR", 14, 1 },
 		{ "CL13_RD_DATA_TO_ERROR", 13, 1 },
 		{ "CL12_RD_DATA_TO_ERROR", 12, 1 },
 		{ "CL11_RD_DATA_TO_ERROR", 11, 1 },
@@ -5892,7 +5887,7 @@ struct reg_info t7_ma_regs[] = {
 		{ "RD_WIN", 8, 8 },
 		{ "WR_WIN", 0, 8 },
 	{ "MA_IF_PARITY_ERROR_ENABLE", 0x78f0, 0 },
-		{ "FUTURE_DEXPANSION_IPE", 14, 18 },
+		{ "CL14_IF_PAR_EN", 14, 1 },
 		{ "CL13_IF_PAR_EN", 13, 1 },
 		{ "CL12_IF_PAR_EN", 12, 1 },
 		{ "CL11_IF_PAR_EN", 11, 1 },
@@ -5908,7 +5903,7 @@ struct reg_info t7_ma_regs[] = {
 		{ "CL1_IF_PAR_EN", 1, 1 },
 		{ "CL0_IF_PAR_EN", 0, 1 },
 	{ "MA_IF_PARITY_ERROR_STATUS", 0x78f4, 0 },
-		{ "FUTURE_DEXPANSION_IPS", 14, 18 },
+		{ "CL14_IF_PAR_ERROR", 14, 1 },
 		{ "CL13_IF_PAR_ERROR", 13, 1 },
 		{ "CL12_IF_PAR_ERROR", 12, 1 },
 		{ "CL11_IF_PAR_ERROR", 11, 1 },
@@ -9192,170 +9187,470 @@ struct reg_info t7_mps_regs[] = {
 	{ "MPS_RX_PORT_GAP", 0x1106c, 0 },
 	{ "MPS_CTL_STAT", 0x11070, 0 },
 	{ "MPS_RX_PERR_INT_CAUSE", 0x11074, 0 },
-		{ "MAC_IN_FIFO_768b", 30, 1 },
-		{ "INT_ERR_INT", 29, 1 },
+		{ "INT_ERR_INT", 30, 1 },
 		{ "FLOP_PERR", 28, 1 },
-		{ "ATRB", 18, 1 },
-		{ "RPLC_MAP", 13, 5 },
-		{ "TKN_RUNT_DROP_FIFO", 12, 1 },
-		{ "PPM3", 9, 3 },
-		{ "PPM2", 6, 3 },
-		{ "PPM1", 3, 3 },
-		{ "PPM0", 0, 3 },
+		{ "mps_rx_atrb_map_perr", 23, 1 },
+		{ "RPLC_MAP_vni_perr", 18, 5 },
+		{ "RPLC_MAP_mcast_perr", 13, 5 },
+		{ "PPM3_perr", 9, 3 },
+		{ "PPM2_perr", 6, 3 },
+		{ "PPM1_perr", 3, 3 },
+		{ "PPM0_perr", 0, 3 },
 	{ "MPS_RX_PERR_INT_ENABLE", 0x11078, 0 },
 		{ "INT_ERR_INT", 30, 1 },
 		{ "FLOP_PERR", 28, 1 },
-		{ "ATRB", 18, 1 },
-		{ "RPLC_MAP", 13, 5 },
-		{ "PPM3", 9, 3 },
-		{ "PPM2", 6, 3 },
-		{ "PPM1", 3, 3 },
-		{ "PPM0", 0, 3 },
+		{ "mps_rx_atrb_map_perr", 23, 1 },
+		{ "RPLC_MAP_vni_perr", 18, 5 },
+		{ "RPLC_MAP_mcast_perr", 13, 5 },
+		{ "PPM3_perr", 9, 3 },
+		{ "PPM2_perr", 6, 3 },
+		{ "PPM1_perr", 3, 3 },
+		{ "PPM0_perr", 0, 3 },
 	{ "MPS_RX_PERR_ENABLE", 0x1107c, 0 },
 		{ "INT_ERR_INT", 30, 1 },
 		{ "FLOP_PERR", 28, 1 },
-		{ "ATRB", 18, 1 },
-		{ "RPLC_MAP", 13, 5 },
-		{ "PPM3", 9, 3 },
-		{ "PPM2", 6, 3 },
-		{ "PPM1", 3, 3 },
-		{ "PPM0", 0, 3 },
+		{ "mps_rx_atrb_ma_perrp", 23, 1 },
+		{ "RPLC_MAP_vn_perri", 18, 5 },
+		{ "RPLC_MAP_mcast_perr", 13, 5 },
+		{ "PPM3_perr", 9, 3 },
+		{ "PPM2_perr", 6, 3 },
+		{ "PPM1_perr", 3, 3 },
+		{ "PPM0_perr", 0, 3 },
 	{ "MPS_RX_PERR_INT_CAUSE2", 0x1108c, 0 },
-		{ "crypt2mps_rx_intf_fifo", 28, 4 },
-		{ "inic2mps_tx0_perr", 27, 1 },
-		{ "inic2mps_tx1_perr", 26, 1 },
-		{ "xgmac2mps_rx0_perr", 25, 1 },
-		{ "xgmac2mps_rx1_perr", 24, 1 },
-		{ "mps2crypto_rx_intf_fifo", 20, 4 },
-		{ "mac_rx_pproc_mps2tp_tf", 19, 1 },
-		{ "mac_rx_pproc_lb_ch3", 18, 1 },
-		{ "mac_rx_pproc_lb_ch2", 17, 1 },
-		{ "mac_rx_pproc_lb_ch1", 16, 1 },
-		{ "mac_rx_pproc_lb_ch0", 15, 1 },
-		{ "mac_rx_pproc_dwrr_ch0_3", 14, 1 },
-		{ "mac_rx_fifo_perr", 13, 1 },
+		{ "crypto2mps_rx0_perr", 31, 1 },
+		{ "crypto2mps_rx1_perr", 30, 1 },
+		{ "crypto2mps_rx2_perr", 29, 1 },
+		{ "crypto2mps_rx3_perr", 28, 1 },
+		{ "inic2mps_tx1_perr", 27, 1 },
+		{ "inic2mps_tx0_perr", 26, 1 },
+		{ "xgmac2mps_rx1_perr", 25, 1 },
+		{ "xgmac2mps_rx0_perr", 24, 1 },
+		{ "mps2crypto_ch0_intf_fifo_perr", 20, 4 },
+		{ "rx_final_tf_fifo_perr", 19, 1 },
+		{ "mps_lb_fifo_perr", 15, 4 },
+		{ "mps_dwrr_fifo_perr", 14, 1 },
+		{ "MAC_tf_fifo_perr", 13, 1 },
 		{ "mac2mps_pt3_perr", 12, 1 },
 		{ "mac2mps_pt2_perr", 11, 1 },
 		{ "mac2mps_pt1_perr", 10, 1 },
 		{ "mac2mps_pt0_perr", 9, 1 },
-		{ "lpbk_fifo_perr", 8, 1 },
-		{ "tp2mps_tf_fifo_perr", 7, 1 },
+		{ "tp_lpbk_fifo_perr", 8, 1 },
+		{ "tp_lpbk_tf_perr", 7, 1 },
+		{ "RSDV1", 0, 7 },
 	{ "MPS_RX_PERR_INT_ENABLE2", 0x11090, 0 },
-		{ "crypt2mps_rx_intf_fifo", 28, 4 },
-		{ "inic2mps_tx0_perr", 27, 1 },
-		{ "inic2mps_tx1_perr", 26, 1 },
-		{ "xgmac2mps_rx0_perr", 25, 1 },
-		{ "xgmac2mps_rx1_perr", 24, 1 },
-		{ "mps2crypto_rx_intf_fifo", 20, 4 },
-		{ "mac_rx_pproc_mps2tp_tf", 19, 1 },
-		{ "mac_rx_pproc_lb_ch3", 18, 1 },
-		{ "mac_rx_pproc_lb_ch2", 17, 1 },
-		{ "mac_rx_pproc_lb_ch1", 16, 1 },
-		{ "mac_rx_pproc_lb_ch0", 15, 1 },
-		{ "mac_rx_pproc_dwrr_ch0_3", 14, 1 },
-		{ "mac_rx_fifo_perr", 13, 1 },
+		{ "crypto2mps_rx0_perr", 31, 1 },
+		{ "crypto2mps_rx1_perr", 30, 1 },
+		{ "crypto2mps_rx2_perr", 29, 1 },
+		{ "crypto2mps_rx3_perr", 28, 1 },
+		{ "inic2mps_tx1_perr", 27, 1 },
+		{ "inic2mps_tx0_perr", 26, 1 },
+		{ "xgmac2mps_rx1_perr", 25, 1 },
+		{ "xgmac2mps_rx0_perr", 24, 1 },
+		{ "mps2crypto_ch0_intf_fifo_perr", 20, 4 },
+		{ "rx_final_tf_fifo_perr", 19, 1 },
+		{ "mps_lb_fifo_perr", 15, 4 },
+		{ "mps_dwrr_fifo_perr", 14, 1 },
+		{ "MAC_tf_fifo_perr", 13, 1 },
 		{ "mac2mps_pt3_perr", 12, 1 },
 		{ "mac2mps_pt2_perr", 11, 1 },
 		{ "mac2mps_pt1_perr", 10, 1 },
 		{ "mac2mps_pt0_perr", 9, 1 },
-		{ "lpbk_fifo_perr", 8, 1 },
-		{ "tp2mps_tf_fifo_perr", 7, 1 },
+		{ "tp_lpbk_fifo_perr", 8, 1 },
+		{ "tp_lpbk_tf_perr", 7, 1 },
+		{ "RSDV1", 0, 7 },
 	{ "MPS_RX_PERR_ENABLE2", 0x11094, 0 },
-		{ "crypt2mps_rx_intf_fifo", 28, 4 },
-		{ "inic2mps_tx0_perr", 27, 1 },
-		{ "inic2mps_tx1_perr", 26, 1 },
-		{ "xgmac2mps_rx0_perr", 25, 1 },
-		{ "xgmac2mps_rx1_perr", 24, 1 },
-		{ "mps2crypto_rx_intf_fifo", 20, 4 },
-		{ "mac_rx_pproc_mps2tp_tf", 19, 1 },
-		{ "mac_rx_pproc_lb_ch3", 18, 1 },
-		{ "mac_rx_pproc_lb_ch2", 17, 1 },
-		{ "mac_rx_pproc_lb_ch1", 16, 1 },
-		{ "mac_rx_pproc_lb_ch0", 15, 1 },
-		{ "mac_rx_pproc_dwrr_ch0_3", 14, 1 },
-		{ "mac_rx_fifo_perr", 13, 1 },
+		{ "crypto2mps_rx0_perr", 31, 1 },
+		{ "crypto2mps_rx1_perr", 30, 1 },
+		{ "crypto2mps_rx2_perr", 29, 1 },
+		{ "crypto2mps_rx3_perr", 28, 1 },
+		{ "inic2mps_tx1_perr", 27, 1 },
+		{ "inic2mps_tx0_perr", 26, 1 },
+		{ "xgmac2mps_rx1_perr", 25, 1 },
+		{ "xgmac2mps_rx0_perr", 24, 1 },
+		{ "mps2crypto_ch0_intf_fifo_perr", 20, 4 },
+		{ "rx_final_tf_fifo_perr", 19, 1 },
+		{ "mps_lb_fifo_perr", 15, 4 },
+		{ "mps_dwrr_fifo_perr", 14, 1 },
+		{ "MAC_tf_fifo_perr", 13, 1 },
 		{ "mac2mps_pt3_perr", 12, 1 },
 		{ "mac2mps_pt2_perr", 11, 1 },
 		{ "mac2mps_pt1_perr", 10, 1 },
 		{ "mac2mps_pt0_perr", 9, 1 },
-		{ "lpbk_fifo_perr", 8, 1 },
-		{ "tp2mps_tf_fifo_perr", 7, 1 },
+		{ "tp_lpbk_fifo_perr", 8, 1 },
+		{ "tp_lpbk_tf_perr", 7, 1 },
+		{ "RSDV1", 0, 7 },
 	{ "MPS_RX_PERR_INT_CAUSE3", 0x11310, 0 },
+		{ "fifo_repl_ch3_cerr", 28, 1 },
+		{ "fifo_repl_ch2_cerr", 27, 1 },
+		{ "fifo_repl_ch1_cerr", 26, 1 },
+		{ "fifo_repl_ch0_cerr", 25, 1 },
+		{ "vlan_filter_ram_cerr", 24, 1 },
+		{ "mps_rx_td_stat_fifo_perr_ch3", 23, 1 },
+		{ "rplct_hdr_fifo_in_perr_ch3", 22, 1 },
+		{ "id_fifo_in_perr_ch3", 21, 1 },
+		{ "desc_hdr2_perr_ch3", 20, 1 },
+		{ "fifo_repl_perr_ch3", 19, 1 },
+		{ "mps_rx_td_perr_ch3", 18, 1 },
+		{ "mps_rx_td_stat_fifo_perr_ch2", 17, 1 },
+		{ "rplct_hdr_fifo_in_perr_ch2", 16, 1 },
+		{ "id_fifo_in_perr_ch2", 15, 1 },
+		{ "desc_hdr2_perr_ch2", 14, 1 },
+		{ "fifo_repl_perr_ch2", 13, 1 },
+		{ "mps_rx_td_perr_ch2", 12, 1 },
+		{ "mps_rx_td_stat_fifo_perr_ch1", 11, 1 },
+		{ "rplct_hdr_fifo_in_perr_ch1", 10, 1 },
+		{ "id_fifo_in_perr_ch1", 9, 1 },
+		{ "desc_hdr2_perr_ch1", 8, 1 },
+		{ "fifo_repl_perr_ch1", 7, 1 },
+		{ "mps_rx_td_perr_ch1", 6, 1 },
+		{ "mps_rx_td_stat_fifo_perr_ch0", 5, 1 },
+		{ "rplct_hdr_fifo_in_perr_ch0", 4, 1 },
+		{ "id_fifo_in_perr_ch0", 3, 1 },
+		{ "desc_hdr2_perr_ch0", 2, 1 },
+		{ "fifo_repl_perr_ch0", 1, 1 },
+		{ "mps_rx_td_perr_ch0", 0, 1 },
 	{ "MPS_RX_PERR_INT_ENABLE3", 0x11314, 0 },
+		{ "fifo_repl_ch3_cerr", 28, 1 },
+		{ "fifo_repl_ch2_cerr", 27, 1 },
+		{ "fifo_repl_ch1_cerr", 26, 1 },
+		{ "fifo_repl_ch0_cerr", 25, 1 },
+		{ "vlan_filter_ram_cerr", 24, 1 },
+		{ "mps_rx_td_stat_fifo_perr_ch3", 23, 1 },
+		{ "rplct_hdr_fifo_in_perr_ch3", 22, 1 },
+		{ "id_fifo_in_perr_ch3", 21, 1 },
+		{ "desc_hdr2_perr_ch3", 20, 1 },
+		{ "fifo_repl_perr_ch3", 19, 1 },
+		{ "mps_rx_td_perr_ch3", 18, 1 },
+		{ "mps_rx_td_stat_fifo_perr_ch2", 17, 1 },
+		{ "rplct_hdr_fifo_in_perr_ch2", 16, 1 },
+		{ "id_fifo_in_perr_ch2", 15, 1 },
+		{ "desc_hdr2_perr_ch2", 14, 1 },
+		{ "fifo_repl_perr_ch2", 13, 1 },
+		{ "mps_rx_td_perr_ch2", 12, 1 },
+		{ "mps_rx_td_stat_fifo_perr_ch1", 11, 1 },
+		{ "rplct_hdr_fifo_in_perr_ch1", 10, 1 },
+		{ "id_fifo_in_perr_ch1", 9, 1 },
+		{ "desc_hdr2_perr_ch1", 8, 1 },
+		{ "fifo_repl_perr_ch1", 7, 1 },
+		{ "mps_rx_td_perr_ch1", 6, 1 },
+		{ "mps_rx_td_stat_fifo_perr_ch0", 5, 1 },
+		{ "rplct_hdr_fifo_in_perr_ch0", 4, 1 },
+		{ "id_fifo_in_perr_ch0", 3, 1 },
+		{ "desc_hdr2_perr_ch0", 2, 1 },
+		{ "fifo_repl_perr_ch0", 1, 1 },
+		{ "mps_rx_td_perr_ch0", 0, 1 },
 	{ "MPS_RX_PERR_ENABLE3", 0x11318, 0 },
+		{ "fifo_repl_ch3_cerr", 28, 1 },
+		{ "fifo_repl_ch2_cerr", 27, 1 },
+		{ "fifo_repl_ch1_cerr", 26, 1 },
+		{ "fifo_repl_ch0_cerr", 25, 1 },
+		{ "vlan_filter_ram_cerr", 24, 1 },
+		{ "mps_rx_td_stat_fifo_perr_ch3", 23, 1 },
+		{ "rplct_hdr_fifo_in_perr_ch3", 22, 1 },
+		{ "id_fifo_in_perr_ch3", 21, 1 },
+		{ "desc_hdr2_perr_ch3", 20, 1 },
+		{ "fifo_repl_perr_ch3", 19, 1 },
+		{ "mps_rx_td_perr_ch3", 18, 1 },
+		{ "mps_rx_td_stat_fifo_perr_ch2", 17, 1 },
+		{ "rplct_hdr_fifo_in_perr_ch2", 16, 1 },
+		{ "id_fifo_in_perr_ch2", 15, 1 },
+		{ "desc_hdr2_perr_ch2", 14, 1 },
+		{ "fifo_repl_perr_ch2", 13, 1 },
+		{ "mps_rx_td_perr_ch2", 12, 1 },
+		{ "mps_rx_td_stat_fifo_perr_ch1", 11, 1 },
+		{ "rplct_hdr_fifo_in_perr_ch1", 10, 1 },
+		{ "id_fifo_in_perr_ch1", 9, 1 },
+		{ "desc_hdr2_perr_ch1", 8, 1 },
+		{ "fifo_repl_perr_ch1", 7, 1 },
+		{ "mps_rx_td_perr_ch1", 6, 1 },
+		{ "mps_rx_td_stat_fifo_perr_ch0", 5, 1 },
+		{ "rplct_hdr_fifo_in_perr_ch0", 4, 1 },
+		{ "id_fifo_in_perr_ch0", 3, 1 },
+		{ "desc_hdr2_perr_ch0", 2, 1 },
+		{ "fifo_repl_perr_ch0", 1, 1 },
+		{ "mps_rx_td_perr_ch0", 0, 1 },
 	{ "MPS_RX_PERR_INT_CAUSE4", 0x1131c, 0 },
-		{ "CLS", 20, 6 },
-		{ "rx_pre_proc", 16, 4 },
-		{ "pproc3", 12, 4 },
-		{ "pproc2", 8, 4 },
-		{ "pproc1", 4, 4 },
-		{ "pproc0", 0, 4 },
+		{ "vni_multicast_fifo_ecc_err_ch3", 30, 1 },
+		{ "vni_multicast_fifo_ecc_err_ch2", 29, 1 },
+		{ "hash_sram_cls_eng1", 28, 1 },
+		{ "hash_sram_cls_eng0", 27, 1 },
+		{ "cls_tcam_sram_cls_eng1", 26, 1 },
+		{ "cls_tcam_crc_sram_cls_eng1", 25, 1 },
+		{ "cls_tcam_sram_cls_eng0", 24, 1 },
+		{ "cls_tcam_crc_sram_cls_eng0", 23, 1 },
+		{ "lb_fifo_ecc_err", 19, 4 },
+		{ "dwrr_ch_fifo_ecc_err", 18, 1 },
+		{ "mac_rx_fifo_ecc_err", 17, 1 },
+		{ "lpbk_rx_fifo_ecc_err", 16, 1 },
+		{ "crs_data_store_n_fwd_ch3", 15, 1 },
+		{ "trace_fwd_fifo_cerr_ch3", 14, 1 },
+		{ "transparent_encap_fwd_fifo_cerr_ch3", 13, 1 },
+		{ "PTP_trace_fwd_fifo_cerr_ch3", 12, 1 },
+		{ "crs_data_store_n_fwd_ch2", 11, 1 },
+		{ "trace_fwd_fifo_cerr_ch2", 10, 1 },
+		{ "transparent_encap_fwd_fifo_cerr_ch2", 9, 1 },
+		{ "PTP_trace_fwd_fifo_cerr_ch2", 8, 1 },
+		{ "crs_data_store_n_fwd_ch1", 7, 1 },
+		{ "trace_fwd_fifo_cerr_ch1", 6, 1 },
+		{ "transparent_encap_fwd_fifo_cerr_ch1", 5, 1 },
+		{ "PTP_trace_fwd_fifo_cerr_ch1", 4, 1 },
+		{ "crs_data_store_n_fwd_ch0", 3, 1 },
+		{ "trace_fwd_fifo_cerr_ch0", 2, 1 },
+		{ "transparent_encap_fwd_fifo_cerr_ch0", 1, 1 },
+		{ "PTP_trace_fwd_fifo_cerr_ch0", 0, 1 },
 	{ "MPS_RX_PERR_INT_ENABLE4", 0x11320, 0 },
-		{ "CLS", 20, 6 },
-		{ "rx_pre_proc", 16, 4 },
-		{ "pproc3", 12, 4 },
-		{ "pproc2", 8, 4 },
-		{ "pproc1", 4, 4 },
-		{ "pproc0", 0, 4 },
+		{ "vni_multicast_fifo_ecc_err_ch3", 30, 1 },
+		{ "vni_multicast_fifo_ecc_err_ch2", 29, 1 },
+		{ "hash_sram_cls_eng1", 28, 1 },
+		{ "hash_sram_cls_eng0", 27, 1 },
+		{ "cls_tcam_sram_cls_eng1", 26, 1 },
+		{ "cls_tcam_crc_sram_cls_eng1", 25, 1 },
+		{ "cls_tcam_sram_cls_eng0", 24, 1 },
+		{ "cls_tcam_crc_sram_cls_eng0", 23, 1 },
+		{ "lb_fifo_ecc_err", 19, 4 },
+		{ "dwrr_ch_fifo_ecc_err", 18, 1 },
+		{ "mac_rx_fifo_ecc_err", 17, 1 },
+		{ "lpbk_rx_fifo_ecc_err", 16, 1 },
+		{ "crs_data_store_n_fwd_ch3", 15, 1 },
+		{ "trace_fwd_fifo_cerr_ch3", 14, 1 },
+		{ "transparent_encap_fwd_fifo_cerr_ch3", 13, 1 },
+		{ "PTP_trace_fwd_fifo_cerr_ch3", 12, 1 },
+		{ "crs_data_store_n_fwd_ch2", 11, 1 },
+		{ "trace_fwd_fifo_cerr_ch2", 10, 1 },
+		{ "transparent_encap_fwd_fifo_cerr_ch2", 9, 1 },
+		{ "PTP_trace_fwd_fifo_cerr_ch2", 8, 1 },
+		{ "crs_data_store_n_fwd_ch1", 7, 1 },
+		{ "trace_fwd_fifo_cerr_ch1", 6, 1 },
+		{ "transparent_encap_fwd_fifo_cerr_ch1", 5, 1 },
+		{ "PTP_trace_fwd_fifo_cerr_ch1", 4, 1 },
+		{ "crs_data_store_n_fwd_ch0", 3, 1 },
+		{ "trace_fwd_fifo_cerr_ch0", 2, 1 },
+		{ "transparent_encap_fwd_fifo_cerr_ch0", 1, 1 },
+		{ "PTP_trace_fwd_fifo_cerr_ch0", 0, 1 },
 	{ "MPS_RX_PERR_ENABLE4", 0x11324, 0 },
-		{ "CLS", 20, 6 },
-		{ "rx_pre_proc", 16, 4 },
-		{ "pproc3", 12, 4 },
-		{ "pproc2", 8, 4 },
-		{ "pproc1", 4, 4 },
-		{ "pproc0", 0, 4 },
+		{ "vni_multicast_fifo_ecc_err_ch3", 30, 1 },
+		{ "vni_multicast_fifo_ecc_err_ch2", 29, 1 },
+		{ "hash_sram_cls_eng1", 28, 1 },
+		{ "hash_sram_cls_eng0", 27, 1 },
+		{ "cls_tcam_sram_cls_eng1", 26, 1 },
+		{ "cls_tcam_crc_sram_cls_eng1", 25, 1 },
+		{ "cls_tcam_sram_cls_eng0", 24, 1 },
+		{ "cls_tcam_crc_sram_cls_eng0", 23, 1 },
+		{ "lb_fifo_ecc_err", 19, 4 },
+		{ "dwrr_ch_fifo_ecc_err", 18, 1 },
+		{ "mac_rx_fifo_ecc_err", 17, 1 },
+		{ "lpbk_rx_fifo_ecc_err", 16, 1 },
+		{ "crs_data_store_n_fwd_ch3", 15, 1 },
+		{ "trace_fwd_fifo_cerr_ch3", 14, 1 },
+		{ "transparent_encap_fwd_fifo_cerr_ch3", 13, 1 },
+		{ "PTP_trace_fwd_fifo_cerr_ch3", 12, 1 },
+		{ "crs_data_store_n_fwd_ch2", 11, 1 },
+		{ "trace_fwd_fifo_cerr_ch2", 10, 1 },
+		{ "transparent_encap_fwd_fifo_cerr_ch2", 9, 1 },
+		{ "PTP_trace_fwd_fifo_cerr_ch2", 8, 1 },
+		{ "crs_data_store_n_fwd_ch1", 7, 1 },
+		{ "trace_fwd_fifo_cerr_ch1", 6, 1 },
+		{ "transparent_encap_fwd_fifo_cerr_ch1", 5, 1 },
+		{ "PTP_trace_fwd_fifo_cerr_ch1", 4, 1 },
+		{ "crs_data_store_n_fwd_ch0", 3, 1 },
+		{ "trace_fwd_fifo_cerr_ch0", 2, 1 },
+		{ "transparent_encap_fwd_fifo_cerr_ch0", 1, 1 },
+		{ "PTP_trace_fwd_fifo_cerr_ch0", 0, 1 },
 	{ "MPS_RX_PERR_INT_CAUSE5", 0x11328, 0 },
-		{ "mps2cryp_rx_fifo", 26, 4 },
-		{ "rx_out", 20, 6 },
-		{ "MEM_WRAP", 0, 20 },
+		{ "mps2cryp_rx_fifo3_perr", 31, 1 },
+		{ "mps2cryp_rx_fifo2_perr", 30, 1 },
+		{ "mps2cryp_rx_fifo1_perr", 29, 1 },
+		{ "mps2cryp_rx_fifo0_perr", 28, 1 },
+		{ "vni_multicast_sram2_perr", 27, 1 },
+		{ "vni_multicast_sram1_perr", 26, 1 },
+		{ "vni_multicast_sram0_perr", 25, 1 },
+		{ "mac_multicast_sram4_perr", 24, 1 },
+		{ "mac_multicast_sram3_perr", 23, 1 },
+		{ "mac_multicast_sram2_perr", 22, 1 },
+		{ "mac_multicast_sram1_perr", 21, 1 },
+		{ "mac_multicast_sram0_perr", 20, 1 },
+		{ "mem_wrap_ipsec_hdr_upd_fifo3_perr", 19, 1 },
+		{ "mem_wrap_ipsec_hdr_upd_fifo2_perr", 18, 1 },
+		{ "mem_wrap_ipsec_hdr_upd_fifo1_perr", 17, 1 },
+		{ "mem_wrap_ipsec_hdr_upd_fifo0_perr", 16, 1 },
+		{ "mem_wrap_cr2mps_rx_fifo3_perr", 15, 1 },
+		{ "mem_wrap_cr2mps_rx_fifo2_perr", 14, 1 },
+		{ "mem_wrap_cr2mps_rx_fifo1_perr", 13, 1 },
+		{ "mem_wrap_cr2mps_rx_fifo0_perr", 12, 1 },
+		{ "mem_wrap_non_ipsec_fifo3_perr", 11, 1 },
+		{ "mem_wrap_non_ipsec_fifo2_perr", 10, 1 },
+		{ "mem_wrap_non_ipsec_fifo1_perr", 9, 1 },
+		{ "mem_wrap_non_ipsec_fifo0_perr", 8, 1 },
+		{ "mem_wrap_tp_db_req_fifo3_perr", 7, 1 },
+		{ "mem_wrap_tp_db_req_fifo2_perr", 6, 1 },
+		{ "mem_wrap_tp_db_req_fifo1_perr", 5, 1 },
+		{ "mem_wrap_tp_db_req_fifo0_perr", 4, 1 },
+		{ "mem_wrap_cntrl_fifo3_perr", 3, 1 },
+		{ "mem_wrap_cntrl_fifo2_perr", 2, 1 },
+		{ "mem_wrap_cntrl_fifo1_perr", 1, 1 },
+		{ "mem_wrap_cntrl_fifo0_perr", 0, 1 },
 	{ "MPS_RX_PERR_INT_ENABLE5", 0x1132c, 0 },
-		{ "mps2cryp_rx_fifo", 26, 4 },
-		{ "rx_out", 20, 6 },
-		{ "MEM_WRAP", 0, 20 },
+		{ "mps2cryp_rx_fifo3_perr", 31, 1 },
+		{ "mps2cryp_rx_fifo2_perr", 30, 1 },
+		{ "mps2cryp_rx_fifo1_perr", 29, 1 },
+		{ "mps2cryp_rx_fifo0_perr", 28, 1 },
+		{ "vni_multicast_sram2_perr", 27, 1 },
+		{ "vni_multicast_sram1_perr", 26, 1 },
+		{ "vni_multicast_sram0_perr", 25, 1 },
+		{ "mac_multicast_sram4_perr", 24, 1 },
+		{ "mac_multicast_sram3_perr", 23, 1 },
+		{ "mac_multicast_sram2_perr", 22, 1 },
+		{ "mac_multicast_sram1_perr", 21, 1 },
+		{ "mac_multicast_sram0_perr", 20, 1 },
+		{ "mem_wrap_ipsec_hdr_upd_fifo3_perr", 19, 1 },
+		{ "mem_wrap_ipsec_hdr_upd_fifo2_perr", 18, 1 },
+		{ "mem_wrap_ipsec_hdr_upd_fifo1_perr", 17, 1 },
+		{ "mem_wrap_ipsec_hdr_upd_fifo0_perr", 16, 1 },
+		{ "mem_wrap_cr2mps_rx_fifo3_perr", 15, 1 },
+		{ "mem_wrap_cr2mps_rx_fifo2_perr", 14, 1 },
+		{ "mem_wrap_cr2mps_rx_fifo1_perr", 13, 1 },
+		{ "mem_wrap_cr2mps_rx_fifo0_perr", 12, 1 },
+		{ "mem_wrap_non_ipsec_fifo3_perr", 11, 1 },
+		{ "mem_wrap_non_ipsec_fifo2_perr", 10, 1 },
+		{ "mem_wrap_non_ipsec_fifo1_perr", 9, 1 },
+		{ "mem_wrap_non_ipsec_fifo0_perr", 8, 1 },
+		{ "mem_wrap_tp_db_req_fifo3_perr", 7, 1 },
+		{ "mem_wrap_tp_db_req_fifo2_perr", 6, 1 },
+		{ "mem_wrap_tp_db_req_fifo1_perr", 5, 1 },
+		{ "mem_wrap_tp_db_req_fifo0_perr", 4, 1 },
+		{ "mem_wrap_cntrl_fifo3_perr", 3, 1 },
+		{ "mem_wrap_cntrl_fifo2_perr", 2, 1 },
+		{ "mem_wrap_cntrl_fifo1_perr", 1, 1 },
+		{ "mem_wrap_cntrl_fifo0_perr", 0, 1 },
 	{ "MPS_RX_PERR_ENABLE5", 0x11330, 0 },
-		{ "mps2cryp_rx_fifo", 26, 4 },
-		{ "rx_out", 20, 6 },
-		{ "MEM_WRAP", 0, 20 },
+		{ "mps2cryp_rx_fifo3_perr", 31, 1 },
+		{ "mps2cryp_rx_fifo2_perr", 30, 1 },
+		{ "mps2cryp_rx_fifo1_perr", 29, 1 },
+		{ "mps2cryp_rx_fifo0_perr", 28, 1 },
+		{ "vni_multicast_sram2_perr", 27, 1 },
+		{ "vni_multicast_sram1_perr", 26, 1 },
+		{ "vni_multicast_sram0_perr", 25, 1 },
+		{ "mac_multicast_sram4_perr", 24, 1 },
+		{ "mac_multicast_sram3_perr", 23, 1 },
+		{ "mac_multicast_sram2_perr", 22, 1 },
+		{ "mac_multicast_sram1_perr", 21, 1 },
+		{ "mac_multicast_sram0_perr", 20, 1 },
+		{ "mem_wrap_ipsec_hdr_upd_fifo3_perr", 19, 1 },
+		{ "mem_wrap_ipsec_hdr_upd_fifo2_perr", 18, 1 },
+		{ "mem_wrap_ipsec_hdr_upd_fifo1_perr", 17, 1 },
+		{ "mem_wrap_ipsec_hdr_upd_fifo0_perr", 16, 1 },
+		{ "mem_wrap_cr2mps_rx_fifo3_perr", 15, 1 },
+		{ "mem_wrap_cr2mps_rx_fifo2_perr", 14, 1 },
+		{ "mem_wrap_cr2mps_rx_fifo1_perr", 13, 1 },
+		{ "mem_wrap_cr2mps_rx_fifo0_perr", 12, 1 },
+		{ "mem_wrap_non_ipsec_fifo3_perr", 11, 1 },
+		{ "mem_wrap_non_ipsec_fifo2_perr", 10, 1 },
+		{ "mem_wrap_non_ipsec_fifo1_perr", 9, 1 },
+		{ "mem_wrap_non_ipsec_fifo0_perr", 8, 1 },
+		{ "mem_wrap_tp_db_req_fifo3_perr", 7, 1 },
+		{ "mem_wrap_tp_db_req_fifo2_perr", 6, 1 },
+		{ "mem_wrap_tp_db_req_fifo1_perr", 5, 1 },
+		{ "mem_wrap_tp_db_req_fifo0_perr", 4, 1 },
+		{ "mem_wrap_cntrl_fifo3_perr", 3, 1 },
+		{ "mem_wrap_cntrl_fifo2_perr", 2, 1 },
+		{ "mem_wrap_cntrl_fifo1_perr", 1, 1 },
+		{ "mem_wrap_cntrl_fifo0_perr", 0, 1 },
 	{ "MPS_RX_PERR_INJECT", 0x11080, 0 },
 		{ "MemSel", 1, 5 },
 		{ "InjectDataErr", 0, 1 },
 	{ "MPS_RX_PERR_INT_CAUSE6", 0x11334, 0 },
+		{ "mem_wrap_ipsec_hdr_upd_fifo3_perr", 23, 1 },
+		{ "mem_wrap_ipsec_hdr_upd_fifo2_perr", 22, 1 },
+		{ "mem_wrap_ipsec_hdr_upd_fifo1_perr", 21, 1 },
+		{ "mem_wrap_ipsec_hdr_upd_fifo0_perr", 20, 1 },
+		{ "mem_wrap_cr2mps_updtd_hdr_fifo3_perr", 19, 1 },
+		{ "mem_wrap_cr2mps_updtd_hdr_fifo2_perr", 18, 1 },
+		{ "mem_wrap_cr2mps_updtd_hdr_fifo1_perr", 17, 1 },
+		{ "mem_wrap_cr2mps_updtd_hdr_fifo0_perr", 16, 1 },
+		{ "mem_wrap_cr2mps_rx_fifo3_perr", 15, 1 },
+		{ "mem_wrap_cr2mps_rx_fifo2_perr", 14, 1 },
+		{ "mem_wrap_cr2mps_rx_fifo1_perr", 13, 1 },
+		{ "mem_wrap_cr2mps_rx_fifo0_perr", 12, 1 },
+		{ "mem_wrap_non_ipsec_fifo3_perr", 11, 1 },
+		{ "mem_wrap_non_ipsec_fifo2_perr", 10, 1 },
+		{ "mem_wrap_non_ipsec_fifo1_perr", 9, 1 },
+		{ "mem_wrap_non_ipsec_fifo0_perr", 8, 1 },
+		{ "mem_wrap_tp_db_req_fifo3_perr", 7, 1 },
+		{ "mem_wrap_tp_db_req_fifo2_perr", 6, 1 },
+		{ "mem_wrap_tp_db_req_fifo1_perr", 5, 1 },
+		{ "mem_wrap_tp_db_req_fifo0_perr", 4, 1 },
+		{ "mem_wrap_cntrl_fifo3_perr", 3, 1 },
+		{ "mem_wrap_cntrl_fifo2_perr", 2, 1 },
+		{ "mem_wrap_cntrl_fifo1_perr", 1, 1 },
+		{ "mem_wrap_cntrl_fifo0_perr", 0, 1 },
 	{ "MPS_RX_PERR_INT_ENABLE6", 0x11338, 0 },
+		{ "mem_wrap_ipsec_hdr_upd_fifo3_perr", 23, 1 },
+		{ "mem_wrap_ipsec_hdr_upd_fifo2_perr", 22, 1 },
+		{ "mem_wrap_ipsec_hdr_upd_fifo1_perr", 21, 1 },
+		{ "mem_wrap_ipsec_hdr_upd_fifo0_perr", 20, 1 },
+		{ "mem_wrap_cr2mps_updtd_hdr_fifo3_perr", 19, 1 },
+		{ "mem_wrap_cr2mps_updtd_hdr_fifo2_perr", 18, 1 },
+		{ "mem_wrap_cr2mps_updtd_hdr_fifo1_perr", 17, 1 },
+		{ "mem_wrap_cr2mps_updtd_hdr_fifo0_perr", 16, 1 },
+		{ "mem_wrap_cr2mps_rx_fifo3_perr", 15, 1 },
+		{ "mem_wrap_cr2mps_rx_fifo2_perr", 14, 1 },
+		{ "mem_wrap_cr2mps_rx_fifo1_perr", 13, 1 },
+		{ "mem_wrap_cr2mps_rx_fifo0_perr", 12, 1 },
+		{ "mem_wrap_non_ipsec_fifo3_perr", 11, 1 },
+		{ "mem_wrap_non_ipsec_fifo2_perr", 10, 1 },
+		{ "mem_wrap_non_ipsec_fifo1_perr", 9, 1 },
+		{ "mem_wrap_non_ipsec_fifo0_perr", 8, 1 },
+		{ "mem_wrap_tp_db_req_fifo3_perr", 7, 1 },
+		{ "mem_wrap_tp_db_req_fifo2_perr", 6, 1 },
+		{ "mem_wrap_tp_db_req_fifo1_perr", 5, 1 },
+		{ "mem_wrap_tp_db_req_fifo0_perr", 4, 1 },
+		{ "mem_wrap_cntrl_fifo3_perr", 3, 1 },
+		{ "mem_wrap_cntrl_fifo2_perr", 2, 1 },
+		{ "mem_wrap_cntrl_fifo1_perr", 1, 1 },
+		{ "mem_wrap_cntrl_fifo0_perr", 0, 1 },
 	{ "MPS_RX_PERR_ENABLE6", 0x1133c, 0 },
+		{ "mem_wrap_ipsec_hdr_upd_fifo3_perr", 23, 1 },
+		{ "mem_wrap_ipsec_hdr_upd_fifo2_perr", 22, 1 },
+		{ "mem_wrap_ipsec_hdr_upd_fifo1_perr", 21, 1 },
+		{ "mem_wrap_ipsec_hdr_upd_fifo0_perr", 20, 1 },
+		{ "mem_wrap_cr2mps_updtd_hdr_fifo3_perr", 19, 1 },
+		{ "mem_wrap_cr2mps_updtd_hdr_fifo2_perr", 18, 1 },
+		{ "mem_wrap_cr2mps_updtd_hdr_fifo1_perr", 17, 1 },
+		{ "mem_wrap_cr2mps_updtd_hdr_fifo0_perr", 16, 1 },
+		{ "mem_wrap_cr2mps_rx_fifo3_perr", 15, 1 },
+		{ "mem_wrap_cr2mps_rx_fifo2_perr", 14, 1 },
+		{ "mem_wrap_cr2mps_rx_fifo1_perr", 13, 1 },
+		{ "mem_wrap_cr2mps_rx_fifo0_perr", 12, 1 },
+		{ "mem_wrap_non_ipsec_fifo3_perr", 11, 1 },
+		{ "mem_wrap_non_ipsec_fifo2_perr", 10, 1 },
+		{ "mem_wrap_non_ipsec_fifo1_perr", 9, 1 },
+		{ "mem_wrap_non_ipsec_fifo0_perr", 8, 1 },
+		{ "mem_wrap_tp_db_req_fifo3_perr", 7, 1 },
+		{ "mem_wrap_tp_db_req_fifo2_perr", 6, 1 },
+		{ "mem_wrap_tp_db_req_fifo1_perr", 5, 1 },
+		{ "mem_wrap_tp_db_req_fifo0_perr", 4, 1 },
+		{ "mem_wrap_cntrl_fifo3_perr", 3, 1 },
+		{ "mem_wrap_cntrl_fifo2_perr", 2, 1 },
+		{ "mem_wrap_cntrl_fifo1_perr", 1, 1 },
+		{ "mem_wrap_cntrl_fifo0_perr", 0, 1 },
 	{ "MPS_RX_FUNC_INT_CAUSE", 0x11084, 0 },
-		{ "MTU_ERR_INT3", 19, 1 },
-		{ "MTU_ERR_INT2", 18, 1 },
-		{ "MTU_ERR_INT1", 17, 1 },
-		{ "MTU_ERR_INT0", 16, 1 },
-		{ "SE_CNT_ERR_INT", 15, 1 },
-		{ "FRM_ERR_INT", 14, 1 },
-		{ "LEN_ERR_INT", 13, 1 },
-		{ "INT_ERR_INT", 8, 5 },
-		{ "PG_TH_INT7", 7, 1 },
-		{ "PG_TH_INT6", 6, 1 },
-		{ "PG_TH_INT5", 5, 1 },
-		{ "PG_TH_INT4", 4, 1 },
-		{ "PG_TH_INT3", 3, 1 },
-		{ "PG_TH_INT2", 2, 1 },
-		{ "PG_TH_INT1", 1, 1 },
-		{ "PG_TH_INT0", 0, 1 },
+		{ "mtu_err3", 19, 1 },
+		{ "mtu_err2", 18, 1 },
+		{ "mtu_err1", 17, 1 },
+		{ "mtu_err0", 16, 1 },
+		{ "dbg_len_err", 15, 1 },
+		{ "dbg_spi_err", 14, 1 },
+		{ "dbg_se_cnt_err", 13, 1 },
+		{ "dbg_spi_len_se_cnt_err", 12, 1 },
 	{ "MPS_RX_FUNC_INT_ENABLE", 0x11088, 0 },
-		{ "MTU_ERR_INT3", 19, 1 },
-		{ "MTU_ERR_INT2", 18, 1 },
-		{ "MTU_ERR_INT1", 17, 1 },
-		{ "MTU_ERR_INT0", 16, 1 },
-		{ "SE_CNT_ERR_INT", 15, 1 },
-		{ "FRM_ERR_INT", 14, 1 },
-		{ "LEN_ERR_INT", 13, 1 },
-		{ "INT_ERR_INT", 8, 5 },
-		{ "PG_TH_INT7", 7, 1 },
-		{ "PG_TH_INT6", 6, 1 },
-		{ "PG_TH_INT5", 5, 1 },
-		{ "PG_TH_INT4", 4, 1 },
-		{ "PG_TH_INT3", 3, 1 },
-		{ "PG_TH_INT2", 2, 1 },
-		{ "PG_TH_INT1", 1, 1 },
-		{ "PG_TH_INT0", 0, 1 },
+		{ "mtu_err3", 19, 1 },
+		{ "mtu_err2", 18, 1 },
+		{ "mtu_err1", 17, 1 },
+		{ "mtu_err0", 16, 1 },
+		{ "dbg_len_err", 15, 1 },
+		{ "dbg_spi_err", 14, 1 },
+		{ "dbg_se_cnt_err", 13, 1 },
+		{ "dbg_spi_len_se_cnt_err", 12, 1 },
 	{ "MPS_RX_REPL_CTL", 0x11098, 0 },
 	{ "MPS_RX_PPP_ATRB", 0x1109c, 0 },
 		{ "ETYPE", 16, 16 },
@@ -10512,23 +10807,45 @@ struct reg_info t7_mps_regs[] = {
 		{ "FRMERR", 27, 1 },
 		{ "SECNTERR", 26, 1 },
 		{ "BUBBLE", 25, 1 },
-		{ "TxTokenFifo", 15, 10 },
-		{ "PERR_TP2MPS_TFIFO", 13, 2 },
-		{ "TxDescFifo", 9, 4 },
-		{ "TxDataFifo", 5, 4 },
-		{ "Ncsi", 4, 1 },
-		{ "TP", 0, 4 },
+		{ "tx_tf_fifo_perr", 19, 1 },
+		{ "tx_fifo_perr", 18, 1 },
+		{ "non_ipsec_tx_fifo3_perr", 17, 1 },
+		{ "non_ipsec_tx_fifo2_perr", 16, 1 },
+		{ "non_ipsec_tx_fifo1_perr", 15, 1 },
+		{ "non_ipsec_tx_fifo0_perr", 14, 1 },
+		{ "tp2mps_tx0", 13, 1 },
+		{ "crypto2mps_tx0", 12, 1 },
+		{ "tp2mps_tx1", 11, 1 },
+		{ "crypto2mps_tx1", 10, 1 },
+		{ "tp2mps_tx2", 9, 1 },
+		{ "crypto2mps_tx2", 8, 1 },
+		{ "tp2mps_tx3", 7, 1 },
+		{ "crypto2mps_tx3", 6, 1 },
+		{ "ncsi2mps", 5, 1 },
+		{ "Ncsi_perr", 4, 1 },
+		{ "TP_perr", 0, 4 },
 	{ "MPS_TX_INT_CAUSE", 0x9408, 0 },
 		{ "PortErr", 28, 1 },
 		{ "FRMERR", 27, 1 },
 		{ "SECNTERR", 26, 1 },
 		{ "BUBBLE", 25, 1 },
-		{ "TxTokenFifo", 15, 10 },
-		{ "PERR_TP2MPS_TFIFO", 13, 2 },
-		{ "TxDescFifo", 9, 4 },
-		{ "TxDataFifo", 5, 4 },
-		{ "Ncsi", 4, 1 },
-		{ "TP", 0, 4 },
+		{ "tx_tf_fifo_perr", 19, 1 },
+		{ "tx_fifo_perr", 18, 1 },
+		{ "non_ipsec_tx_fifo3_perr", 17, 1 },
+		{ "non_ipsec_tx_fifo2_perr", 16, 1 },
+		{ "non_ipsec_tx_fifo1_perr", 15, 1 },
+		{ "non_ipsec_tx_fifo0_perr", 14, 1 },
+		{ "tp2mps_tx0", 13, 1 },
+		{ "crypto2mps_tx0", 12, 1 },
+		{ "tp2mps_tx1", 11, 1 },
+		{ "crypto2mps_tx1", 10, 1 },
+		{ "tp2mps_tx2", 9, 1 },
+		{ "crypto2mps_tx2", 8, 1 },
+		{ "tp2mps_tx3", 7, 1 },
+		{ "crypto2mps_tx3", 6, 1 },
+		{ "ncsi2mps", 5, 1 },
+		{ "Ncsi_perr", 4, 1 },
+		{ "TP_perr", 0, 4 },
 	{ "MPS_TX_NCSI2MPS_CNT", 0x940c, 0 },
 	{ "MPS_TX_PERR_ENABLE", 0x9410, 0 },
 		{ "PortErrInt", 28, 1 },
@@ -10640,7 +10957,17 @@ struct reg_info t7_mps_regs[] = {
 	{ "MPS_TX_DBG_CNT_CTL", 0x9478, 0 },
 	{ "MPS_TX_DBG_CNT", 0x947c, 0 },
 	{ "MPS_TX_INT2_ENABLE", 0x9498, 0 },
+		{ "tx_fifo_perr", 4, 1 },
+		{ "non_ipsec_tx_fifo3", 3, 1 },
+		{ "non_ipsec_tx_fifo2", 2, 1 },
+		{ "non_ipsec_tx_fifo1", 1, 1 },
+		{ "non_ipsec_tx_fifo0", 0, 1 },
 	{ "MPS_TX_INT2_CAUSE", 0x949c, 0 },
+		{ "tx_fifo_perr", 4, 1 },
+		{ "non_ipsec_tx_fifo3_perr", 3, 1 },
+		{ "non_ipsec_tx_fifo2_perr", 2, 1 },
+		{ "non_ipsec_tx_fifo1_perr", 1, 1 },
+		{ "non_ipsec_tx_fifo0_perr", 0, 1 },
 	{ "MPS_TX_PERR2_ENABLE", 0x94a0, 0 },
 	{ "MPS_TX_INT3_ENABLE", 0x94a4, 0 },
 	{ "MPS_TX_INT3_CAUSE", 0x94a8, 0 },
@@ -11064,6 +11391,7 @@ struct reg_info t7_mps_regs[] = {
 		{ "MemSel", 1, 4 },
 		{ "InjectDataErr", 0, 1 },
 	{ "MPS_TRC_PERR_ENABLE", 0x9854, 0 },
+		{ "PLErrEnb", 17, 1 },
 		{ "MiscPerr", 16, 1 },
 		{ "PktFifo", 8, 8 },
 		{ "FiltMem", 0, 8 },
@@ -11093,34 +11421,39 @@ struct reg_info t7_mps_regs[] = {
 		{ "TF4_perr_0", 8, 1 },
 		{ "Perr_tf_in_ctl", 0, 8 },
 	{ "MPS_TRC_INT_ENABLE2", 0xa4f4, 0 },
-		{ "trc_tf_ecc", 24, 8 },
-		{ "mps2mac_conv_trc_cerr", 22, 2 },
-		{ "mps2mac_conv_trc", 18, 4 },
-		{ "TF0_perr_1", 17, 1 },
-		{ "TF1_perr_1", 16, 1 },
-		{ "TF2_perr_1", 15, 1 },
-		{ "TF3_perr_1", 14, 1 },
-		{ "TF4_perr_1", 13, 1 },
-		{ "TF0_perr_0", 12, 1 },
-		{ "TF1_perr_0", 11, 1 },
-		{ "TF2_perr_0", 10, 1 },
-		{ "TF3_perr_0", 9, 1 },
-		{ "TF4_perr_0", 8, 1 },
-		{ "Perr_tf_in_ctl", 0, 8 },
+		{ "tx2rx_dwn_conv_perr_pt3_cerr", 16, 1 },
+		{ "tx2rx_dwn_conv_perr_pt2_cerr", 15, 1 },
+		{ "tx2rx_dwn_conv_perr_pt1_cerr", 14, 1 },
+		{ "tx2rx_dwn_conv_perr_pt0_cerr", 13, 1 },
+		{ "mps2mac_dwn_conv_perr_pt1_cerr", 12, 1 },
+		{ "mps2mac_dwn_conv_perr_pt0_cerr", 11, 1 },
+		{ "mac2mps_dwn_conv_perr_pt1_cerr", 10, 1 },
+		{ "mac2mps_dwn_conv_perr_pt0_cerr", 9, 1 },
+		{ "tx2rx_dwn_conv_perr_pt3_perr", 8, 1 },
+		{ "tx2rx_dwn_conv_perr_pt2_perr", 7, 1 },
+		{ "tx2rx_dwn_conv_perr_pt1_perr", 6, 1 },
+		{ "tx2rx_dwn_conv_perr_pt0_perr", 5, 1 },
+		{ "mac2mps_dwn_conv_perr_pt1_perr", 4, 1 },
+		{ "mac2mps_dwn_conv_perr_pt0_perr", 3, 1 },
+		{ "mps2mac_dwn_conv_perr_pt1_perr", 2, 1 },
+		{ "mps2mac_dwn_conv_perr_pt0_perr", 1, 1 },
 	{ "MPS_TRC_INT_CAUSE2", 0xa4f8, 0 },
-		{ "trc_tf_ecc", 22, 8 },
-		{ "mps2mac_conv_trc", 18, 4 },
-		{ "TF0_perr_1", 17, 1 },
-		{ "TF1_perr_1", 16, 1 },
-		{ "TF2_perr_1", 15, 1 },
-		{ "TF3_perr_1", 14, 1 },
-		{ "TF4_perr_1", 13, 1 },
-		{ "TF0_perr_0", 12, 1 },
-		{ "TF1_perr_0", 11, 1 },
-		{ "TF2_perr_0", 10, 1 },
-		{ "TF3_perr_0", 9, 1 },
-		{ "TF4_perr_0", 8, 1 },
-		{ "Perr_tf_in_ctl", 0, 8 },
+		{ "tx2rx_dwn_conv_perr_pt3_cerr", 16, 1 },
+		{ "tx2rx_dwn_conv_perr_pt2_cerr", 15, 1 },
+		{ "tx2rx_dwn_conv_perr_pt1_cerr", 14, 1 },
+		{ "tx2rx_dwn_conv_perr_pt0_cerr", 13, 1 },
+		{ "mps2mac_dwn_conv_perr_pt1_cerr", 12, 1 },
+		{ "mps2mac_dwn_conv_perr_pt0_cerr", 11, 1 },
+		{ "mac2mps_dwn_conv_perr_pt1_cerr", 10, 1 },
+		{ "mac2mps_dwn_conv_perr_pt0_cerr", 9, 1 },
+		{ "tx2rx_dwn_conv_perr_pt3_perr", 8, 1 },
+		{ "tx2rx_dwn_conv_perr_pt2_perr", 7, 1 },
+		{ "tx2rx_dwn_conv_perr_pt1_perr", 6, 1 },
+		{ "tx2rx_dwn_conv_perr_pt0_perr", 5, 1 },
+		{ "mac2mps_dwn_conv_perr_pt1_perr", 4, 1 },
+		{ "mac2mps_dwn_conv_perr_pt0_perr", 3, 1 },
+		{ "mps2mac_dwn_conv_perr_pt1_perr", 2, 1 },
+		{ "mps2mac_dwn_conv_perr_pt0_perr", 1, 1 },
 	{ "MPS_TRC_TIMESTAMP_L", 0xa4e8, 0 },
 	{ "MPS_TRC_TIMESTAMP_H", 0xa4ec, 0 },
 	{ "MPS_TRC_FILTER0_MATCH", 0x9c00, 0 },
@@ -11593,6 +11926,7 @@ struct reg_info t7_mps_regs[] = {
 		{ "Lbport", 6, 5 },
 		{ "Txport", 0, 6 },
 	{ "MPS_STAT_PERR_INT_CAUSE_SRAM", 0x9614, 0 },
+		{ "Rxpp", 29, 2 },
 		{ "Rxbg", 27, 2 },
 		{ "Rxpf", 22, 5 },
 		{ "Txpf", 18, 4 },
@@ -11600,6 +11934,7 @@ struct reg_info t7_mps_regs[] = {
 		{ "Lbport", 6, 5 },
 		{ "Txport", 0, 6 },
 	{ "MPS_STAT_PERR_ENABLE_SRAM", 0x9618, 0 },
+		{ "Rxpp", 29, 2 },
 		{ "Rxbg", 27, 2 },
 		{ "Rxpf", 22, 5 },
 		{ "Txpf", 18, 4 },
@@ -11678,14 +12013,20 @@ struct reg_info t7_mps_regs[] = {
 	{ "MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L", 0x96b8, 0 },
 	{ "MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H", 0x96bc, 0 },
 	{ "MPS_STAT_PERR_INT_ENABLE_SRAM1", 0x96c0, 0 },
-		{ "Rxvf", 5, 3 },
-		{ "Txvf", 0, 5 },
+		{ "Rxvf_cerr", 12, 4 },
+		{ "Txvf_cerr", 8, 4 },
+		{ "Rxvf_perr", 5, 3 },
+		{ "Txvf_perr", 0, 5 },
 	{ "MPS_STAT_PERR_INT_CAUSE_SRAM1", 0x96c4, 0 },
-		{ "Rxvf", 5, 3 },
-		{ "Txvf", 0, 5 },
+		{ "Rxvf_cerr", 12, 4 },
+		{ "Txvf_cerr", 8, 4 },
+		{ "Rxvf_perr", 5, 3 },
+		{ "Txvf_perr", 0, 5 },
 	{ "MPS_STAT_PERR_ENABLE_SRAM1", 0x96c8, 0 },
-		{ "Rxvf", 5, 3 },
-		{ "Txvf", 0, 5 },
+		{ "Rxvf_cerr", 12, 4 },
+		{ "Txvf_cerr", 8, 4 },
+		{ "Rxvf_perr", 5, 3 },
+		{ "Txvf_perr", 0, 5 },
 	{ "MPS_STAT_STOP_UPD_BG", 0x96cc, 0 },
 	{ "MPS_STAT_STOP_UPD_PORT", 0x96d0, 0 },
 		{ "PtLpbk", 8, 4 },
@@ -16266,9 +16607,9 @@ struct reg_info t7_smb_regs[] = {
 		{ "DebugDataH", 16, 16 },
 		{ "DebugDataL", 0, 16 },
 	{ "SMB_PERR_EN", 0x19098, 0 },
-		{ "MstTxFifo", 21, 1 },
-		{ "MstRxFifo", 19, 1 },
-		{ "SlvFifo", 18, 1 },
+		{ "MstTxFifo", 22, 1 },
+		{ "MstRxFifo", 21, 1 },
+		{ "SlvFifo", 20, 1 },
 		{ "MstTxFifoPerrEn", 2, 1 },
 		{ "MstRxFifoPerrEn", 1, 1 },
 		{ "SlvFifoPerrEn", 0, 1 },
@@ -22731,11 +23072,11 @@ struct reg_info t7_mac_t7_regs[] = {
 	{ "MAC_MTIP_MAC400G_0_MTIP_MAC_ADDR_1", 0x38210, 0 },
 	{ "MAC_MTIP_MAC400G_0_MTIP_FRM_LENGTH", 0x38214, 0 },
 	{ "MAC_MTIP_MAC400G_0_MTIP_RX_FIFO_SECTIONS", 0x3821c, 0 },
-		{ "AVAIL", 16, 16 },
-		{ "EMPTY", 0, 16 },
+		{ "EMPTY", 16, 16 },
+		{ "AVAIL", 0, 16 },
 	{ "MAC_MTIP_MAC400G_0_MTIP_TX_FIFO_SECTIONS", 0x38220, 0 },
-		{ "AVAIL", 16, 16 },
-		{ "EMPTY", 0, 16 },
+		{ "EMPTY", 16, 16 },
+		{ "AVAIL", 0, 16 },
 	{ "MAC_MTIP_MAC400G_0_MTIP_RX_FIFO_ALMOST_F_E", 0x38224, 0 },
 		{ "AlmstFull", 16, 16 },
 		{ "AlmstEmpty", 0, 16 },
@@ -26677,7 +27018,6 @@ struct reg_info t7_arm_regs[] = {
 		{ "dftramhold", 1, 1 },
 		{ "dftcgen", 0, 1 },
 	{ "ARM_PLM_RID_CFG", 0x4703c, 0 },
-	{ "ARM_PLM_EROM_CFG", 0x47040, 0 },
 	{ "ARM_PL_ARM_HDR_CFG", 0x4704c, 0 },
 	{ "ARM_MBISTACK", 0x477d4, 0 },
 	{ "ARM_MBISTADDR", 0x477d8, 0 },
@@ -26919,12 +27259,9 @@ struct reg_info t7_mc_t70_regs[] = {
 		{ "ECC_CE_INT_CAUSE", 2, 1 },
 		{ "ECC_UE_INT_CAUSE", 1, 1 },
 		{ "PERR_INT_CAUSE", 0, 1 },
-	{ "MC_P_ECC_UE_INT_ENABLE", 0x49324, 0 },
-	{ "MC_P_ECC_UE_INT_CAUSE", 0x49328, 0 },
 	{ "MC_P_ECC_STATUS", 0x4932c, 0 },
 		{ "ECC_CECNT", 16, 16 },
 		{ "ECC_UECNT", 0, 16 },
-	{ "MC_P_PHY_CTRL", 0x49330, 0 },
 	{ "MC_P_STATIC_CFG_STATUS", 0x49334, 0 },
 		{ "DfiFreqRatio", 27, 1 },
 		{ "STATIC_PP64", 26, 1 },
@@ -27170,12 +27507,9 @@ struct reg_info t7_mc_t71_regs[] = {
 		{ "ECC_CE_INT_CAUSE", 2, 1 },
 		{ "ECC_UE_INT_CAUSE", 1, 1 },
 		{ "PERR_INT_CAUSE", 0, 1 },
-	{ "MC_P_ECC_UE_INT_ENABLE", 0x59324, 0 },
-	{ "MC_P_ECC_UE_INT_CAUSE", 0x59328, 0 },
 	{ "MC_P_ECC_STATUS", 0x5932c, 0 },
 		{ "ECC_CECNT", 16, 16 },
 		{ "ECC_UECNT", 0, 16 },
-	{ "MC_P_PHY_CTRL", 0x59330, 0 },
 	{ "MC_P_STATIC_CFG_STATUS", 0x59334, 0 },
 		{ "DfiFreqRatio", 27, 1 },
 		{ "STATIC_PP64", 26, 1 },