aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorMichal Meloun <mmel@FreeBSD.org>2018-01-04 12:18:24 +0000
committerMichal Meloun <mmel@FreeBSD.org>2020-12-28 13:12:41 +0000
commite903478919602c90fdc202a8628b89eb7c3bc104 (patch)
treeef181670bff962c0da9d95d98096d5604eebf33b
parent63f93c7e11e33149429ddc2831cd1683b2e7f3e1 (diff)
downloadsrc-e903478919602c90fdc202a8628b89eb7c3bc104.tar.gz
src-e903478919602c90fdc202a8628b89eb7c3bc104.zip
ARM64: Port FreeBSD to Nvidia Jetson TX1 and Nano.
Add support for the Tergra210 SoC and its companion PMIC MAX77620.
-rw-r--r--sys/arm64/nvidia/tegra210/max77620.c511
-rw-r--r--sys/arm64/nvidia/tegra210/max77620.h262
-rw-r--r--sys/arm64/nvidia/tegra210/max77620_gpio.c715
-rw-r--r--sys/arm64/nvidia/tegra210/max77620_regulators.c888
-rw-r--r--sys/arm64/nvidia/tegra210/max77620_rtc.c413
-rw-r--r--sys/arm64/nvidia/tegra210/tegra210_car.c601
-rw-r--r--sys/arm64/nvidia/tegra210/tegra210_car.h528
-rw-r--r--sys/arm64/nvidia/tegra210/tegra210_clk_per.c951
-rw-r--r--sys/arm64/nvidia/tegra210/tegra210_clk_pll.c1494
-rw-r--r--sys/arm64/nvidia/tegra210/tegra210_clk_super.c231
-rw-r--r--sys/arm64/nvidia/tegra210/tegra210_coretemp.c272
-rw-r--r--sys/arm64/nvidia/tegra210/tegra210_cpufreq.c502
-rw-r--r--sys/arm64/nvidia/tegra210/tegra210_pinmux.c758
-rw-r--r--sys/arm64/nvidia/tegra210/tegra210_pmc.c628
-rw-r--r--sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c1963
-rw-r--r--sys/conf/files.arm6448
-rw-r--r--sys/conf/options.arm641
-rw-r--r--sys/gnu/dts/arm64/nvidia/Makefile7
18 files changed, 10773 insertions, 0 deletions
diff --git a/sys/arm64/nvidia/tegra210/max77620.c b/sys/arm64/nvidia/tegra210/max77620.c
new file mode 100644
index 000000000000..d46417ce0e28
--- /dev/null
+++ b/sys/arm64/nvidia/tegra210/max77620.c
@@ -0,0 +1,511 @@
+/*-
+ * Copyright (c) 2019 Michal Meloun <mmel@FreeBSD.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+/*
+ * MAX77620 PMIC driver
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/gpio.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/malloc.h>
+#include <sys/rman.h>
+#include <sys/sx.h>
+
+#include <machine/bus.h>
+
+#include <dev/extres/regulator/regulator.h>
+#include <dev/fdt/fdt_pinctrl.h>
+#include <dev/gpio/gpiobusvar.h>
+#include <dev/iicbus/iiconf.h>
+#include <dev/iicbus/iicbus.h>
+#include <dev/ofw/ofw_bus.h>
+#include <dev/ofw/ofw_bus_subr.h>
+
+#include <gnu/dts/include/dt-bindings/mfd/max77620.h>
+
+#include "clock_if.h"
+#include "regdev_if.h"
+
+#include "max77620.h"
+
+static struct ofw_compat_data compat_data[] = {
+ {"maxim,max77620", 1},
+ {NULL, 0},
+};
+
+#define LOCK(_sc) sx_xlock(&(_sc)->lock)
+#define UNLOCK(_sc) sx_xunlock(&(_sc)->lock)
+#define LOCK_INIT(_sc) sx_init(&(_sc)->lock, "max77620")
+#define LOCK_DESTROY(_sc) sx_destroy(&(_sc)->lock);
+#define ASSERT_LOCKED(_sc) sx_assert(&(_sc)->lock, SA_XLOCKED);
+#define ASSERT_UNLOCKED(_sc) sx_assert(&(_sc)->lock, SA_UNLOCKED);
+
+#define MAX77620_DEVICE_ID 0x0C
+
+/*
+ * Raw register access function.
+ */
+int
+max77620_read(struct max77620_softc *sc, uint8_t reg, uint8_t *val)
+{
+ uint8_t addr;
+ int rv;
+ struct iic_msg msgs[2] = {
+ {0, IIC_M_WR, 1, &addr},
+ {0, IIC_M_RD, 1, val},
+ };
+
+ msgs[0].slave = sc->bus_addr;
+ msgs[1].slave = sc->bus_addr;
+ addr = reg;
+
+ rv = iicbus_transfer(sc->dev, msgs, 2);
+ if (rv != 0) {
+ device_printf(sc->dev,
+ "Error when reading reg 0x%02X, rv: %d\n", reg, rv);
+ return (EIO);
+ }
+
+ return (0);
+}
+
+int max77620_read_buf(struct max77620_softc *sc, uint8_t reg, uint8_t *buf,
+ size_t size)
+{
+ uint8_t addr;
+ int rv;
+ struct iic_msg msgs[2] = {
+ {0, IIC_M_WR, 1, &addr},
+ {0, IIC_M_RD, size, buf},
+ };
+
+ msgs[0].slave = sc->bus_addr;
+ msgs[1].slave = sc->bus_addr;
+ addr = reg;
+
+ rv = iicbus_transfer(sc->dev, msgs, 2);
+ if (rv != 0) {
+ device_printf(sc->dev,
+ "Error when reading reg 0x%02X, rv: %d\n", reg, rv);
+ return (EIO);
+ }
+
+ return (0);
+}
+
+int
+max77620_write(struct max77620_softc *sc, uint8_t reg, uint8_t val)
+{
+ uint8_t data[2];
+ int rv;
+
+ struct iic_msg msgs[1] = {
+ {0, IIC_M_WR, 2, data},
+ };
+
+ msgs[0].slave = sc->bus_addr;
+ data[0] = reg;
+ data[1] = val;
+
+ rv = iicbus_transfer(sc->dev, msgs, 1);
+ if (rv != 0) {
+ device_printf(sc->dev,
+ "Error when writing reg 0x%02X, rv: %d\n", reg, rv);
+ return (EIO);
+ }
+ return (0);
+}
+
+int
+max77620_write_buf(struct max77620_softc *sc, uint8_t reg, uint8_t *buf,
+ size_t size)
+{
+ uint8_t data[1];
+ int rv;
+ struct iic_msg msgs[2] = {
+ {0, IIC_M_WR, 1, data},
+ {0, IIC_M_WR | IIC_M_NOSTART, size, buf},
+ };
+
+ msgs[0].slave = sc->bus_addr;
+ msgs[1].slave = sc->bus_addr;
+ data[0] = reg;
+
+ rv = iicbus_transfer(sc->dev, msgs, 2);
+ if (rv != 0) {
+ device_printf(sc->dev,
+ "Error when writing reg 0x%02X, rv: %d\n", reg, rv);
+ return (EIO);
+ }
+ return (0);
+}
+
+int
+max77620_modify(struct max77620_softc *sc, uint8_t reg, uint8_t clear,
+ uint8_t set)
+{
+ uint8_t val;
+ int rv;
+
+ rv = max77620_read(sc, reg, &val);
+ if (rv != 0)
+ return (rv);
+
+ val &= ~clear;
+ val |= set;
+
+ rv = max77620_write(sc, reg, val);
+ if (rv != 0)
+ return (rv);
+
+ return (0);
+}
+
+static int
+max77620_parse_fps(struct max77620_softc *sc, int id, phandle_t node)
+{
+ int val;
+
+ if (OF_getencprop(node, "maxim,shutdown-fps-time-period-us", &val,
+ sizeof(val)) >= 0) {
+ val = min(val, MAX77620_FPS_PERIOD_MAX_US);
+ val = max(val, MAX77620_FPS_PERIOD_MIN_US);
+ sc->shutdown_fps[id] = val;
+ }
+ if (OF_getencprop(node, "maxim,suspend-fps-time-period-us", &val,
+ sizeof(val)) >= 0) {
+ val = min(val, MAX77620_FPS_PERIOD_MAX_US);
+ val = max(val, MAX77620_FPS_PERIOD_MIN_US);
+ sc->suspend_fps[id] = val;
+ }
+ if (OF_getencprop(node, "maxim,fps-event-source", &val,
+ sizeof(val)) >= 0) {
+ if (val > 2) {
+ device_printf(sc->dev, "Invalid 'fps-event-source' "
+ "value: %d\n", val);
+ return (EINVAL);
+ }
+ sc->event_source[id] = val;
+ }
+ return (0);
+}
+
+static int
+max77620_parse_fdt(struct max77620_softc *sc, phandle_t node)
+{
+ phandle_t fpsnode;
+ char fps_name[6];
+ int i, rv;
+
+ for (i = 0; i < MAX77620_FPS_COUNT; i++) {
+ sc->shutdown_fps[i] = -1;
+ sc->suspend_fps[i] = -1;
+ sc->event_source[i] = -1;
+ }
+
+ fpsnode = ofw_bus_find_child(node, "fps");
+ if (fpsnode > 0) {
+ for (i = 0; i < MAX77620_FPS_COUNT; i++) {
+ sprintf(fps_name, "fps%d", i);
+ node = ofw_bus_find_child(node, fps_name);
+ if (node <= 0)
+ continue;
+ rv = max77620_parse_fps(sc, i, node);
+ if (rv != 0)
+ return (rv);
+ }
+ }
+ return (0);
+}
+
+static int
+max77620_get_version(struct max77620_softc *sc)
+{
+ uint8_t buf[6];
+ int i;
+ int rv;
+
+ /* Verify ID string (5 bytes ). */
+ for (i = 0; i <= 6; i++) {
+ rv = RD1(sc, MAX77620_REG_CID0 + i , buf + i);
+ if (rv != 0) {
+ device_printf(sc->dev, "Cannot read chip ID: %d\n", rv);
+ return (ENXIO);
+ }
+ }
+ if (bootverbose) {
+ device_printf(sc->dev,
+ " ID: [0x%02X, 0x%02X, 0x%02X, 0x%02X]\n",
+ buf[0], buf[1], buf[2], buf[3]);
+ }
+ device_printf(sc->dev, " MAX77620 version - OTP: 0x%02X, ES: 0x%02X\n",
+ buf[4], buf[5]);
+
+ return (0);
+}
+
+static uint8_t
+max77620_encode_fps_period(struct max77620_softc *sc, int val)
+{
+ uint8_t i;
+ int period;
+
+ period = MAX77620_FPS_PERIOD_MIN_US;
+ for (i = 0; i < 7; i++) {
+ if (period >= val)
+ return (i);
+ period *= 2;
+ }
+ return (i);
+}
+
+static int
+max77620_init(struct max77620_softc *sc)
+{
+ uint8_t mask, val, tmp;;
+ int i, rv;
+
+ mask = 0;
+ val = 0;
+ for (i = 0; i < MAX77620_FPS_COUNT; i++) {
+ if (sc->shutdown_fps[i] != -1) {
+ mask |= MAX77620_FPS_TIME_PERIOD_MASK;
+ tmp = max77620_encode_fps_period(sc,
+ sc->shutdown_fps[i]);
+ val |= (tmp << MAX77620_FPS_TIME_PERIOD_SHIFT) &
+ MAX77620_FPS_TIME_PERIOD_MASK;
+ }
+
+ if (sc->event_source[i] != -1) {
+ mask |= MAX77620_FPS_EN_SRC_MASK;
+ tmp = sc->event_source[i];
+ val |= (tmp << MAX77620_FPS_EN_SRC_SHIFT) &
+ MAX77620_FPS_EN_SRC_MASK;
+ if (sc->event_source[i] == 2) {
+ mask |= MAX77620_FPS_ENFPS_SW_MASK;
+ val |= MAX77620_FPS_ENFPS_SW;
+ }
+
+ }
+ rv = RM1(sc, MAX77620_REG_FPS_CFG0 + i, mask, val);
+ if (rv != 0) {
+ device_printf(sc->dev, "I/O error: %d\n", rv);
+ return (ENXIO);
+ }
+ }
+
+ /* Global mask interrupts */
+ rv = RM1(sc, MAX77620_REG_INTENLBT, 0x81, 0x81);
+ rv = RM1(sc, MAX77620_REG_IRQTOPM, 0x81, 0x81);
+ if (rv != 0)
+ return (ENXIO);
+ return (0);
+}
+#ifdef notyet
+static void
+max77620_intr(void *arg)
+{
+ struct max77620_softc *sc;
+ uint8_t intenlbt, intlbt, irqtop, irqtopm, irqsd, irqmasksd;
+ uint8_t irq_lvl2_l0_7, irq_lvl2_l8, irq_lvl2_gpio, irq_msk_l0_7, irq_msk_l8;
+ uint8_t onoffirq, onoffirqm;
+
+ sc = (struct max77620_softc *)arg;
+ /* XXX Finish temperature alarms. */
+ RD1(sc, MAX77620_REG_INTENLBT, &intenlbt);
+ RD1(sc, MAX77620_REG_INTLBT, &intlbt);
+
+ RD1(sc, MAX77620_REG_IRQTOP, &irqtop);
+ RD1(sc, MAX77620_REG_IRQTOPM, &irqtopm);
+ RD1(sc, MAX77620_REG_IRQSD, &irqsd);
+ RD1(sc, MAX77620_REG_IRQMASKSD, &irqmasksd);
+ RD1(sc, MAX77620_REG_IRQ_LVL2_L0_7, &irq_lvl2_l0_7);
+ RD1(sc, MAX77620_REG_IRQ_MSK_L0_7, &irq_msk_l0_7);
+ RD1(sc, MAX77620_REG_IRQ_LVL2_L8, &irq_lvl2_l8);
+ RD1(sc, MAX77620_REG_IRQ_MSK_L8, &irq_msk_l8);
+ RD1(sc, MAX77620_REG_IRQ_LVL2_GPIO, &irq_lvl2_gpio);
+ RD1(sc, MAX77620_REG_ONOFFIRQ, &onoffirq);
+ RD1(sc, MAX77620_REG_ONOFFIRQM, &onoffirqm);
+ printf("%s: intlbt: 0x%02X, intenlbt: 0x%02X\n", __func__, intlbt, intenlbt);
+ printf("%s: irqtop: 0x%02X, irqtopm: 0x%02X\n", __func__, irqtop, irqtopm);
+ printf("%s: irqsd: 0x%02X, irqmasksd: 0x%02X\n", __func__, irqsd, irqmasksd);
+ printf("%s: onoffirq: 0x%02X, onoffirqm: 0x%02X\n", __func__, onoffirq, onoffirqm);
+ printf("%s: irq_lvl2_l0_7: 0x%02X, irq_msk_l0_7: 0x%02X\n", __func__, irq_lvl2_l0_7, irq_msk_l0_7);
+ printf("%s: irq_lvl2_l8: 0x%02X, irq_msk_l8: 0x%02X\n", __func__, irq_lvl2_l8, irq_msk_l8);
+ printf("%s: irq_lvl2_gpio: 0x%02X\n", __func__, irq_lvl2_gpio);
+}
+#endif
+
+static int
+max77620_probe(device_t dev)
+{
+
+ if (!ofw_bus_status_okay(dev))
+ return (ENXIO);
+
+ if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
+ return (ENXIO);
+
+ device_set_desc(dev, "MAX77620 PMIC");
+ return (BUS_PROBE_DEFAULT);
+}
+
+static int
+max77620_attach(device_t dev)
+{
+ struct max77620_softc *sc;
+ const char *dname;
+ int dunit, rv, rid;
+ phandle_t node;
+
+ sc = device_get_softc(dev);
+ sc->dev = dev;
+ sc->bus_addr = iicbus_get_addr(dev);
+ node = ofw_bus_get_node(sc->dev);
+ dname = device_get_name(dev);
+ dunit = device_get_unit(dev);
+ rv = 0;
+ LOCK_INIT(sc);
+
+#ifdef notyet /* Interrupt parent is not implemented */
+ rid = 0;
+ sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
+ RF_ACTIVE);
+ if (sc->irq_res == NULL) {
+ device_printf(dev, "Cannot allocate interrupt.\n");
+ rv = ENXIO;
+ goto fail;
+ }
+#endif
+ rv = max77620_parse_fdt(sc, node);
+ if (rv != 0)
+ goto fail;
+
+ rv = max77620_get_version(sc);
+ if (rv != 0)
+ goto fail;
+
+ rv = max77620_init(sc);
+ if (rv != 0)
+ goto fail;
+ rv = max77620_regulator_attach(sc, node);
+ if (rv != 0)
+ goto fail;
+ rv = max77620_gpio_attach(sc, node);
+ if (rv != 0)
+ goto fail;
+
+ rv = max77620_rtc_create(sc, node);
+ if (rv != 0)
+ goto fail;
+
+ fdt_pinctrl_register(dev, NULL);
+ fdt_pinctrl_configure_by_name(dev, "default");
+
+ /* Setup interrupt. */
+#ifdef notyet
+ rv = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
+ NULL, max77620_intr, sc, &sc->irq_h);
+ if (rv) {
+ device_printf(dev, "Cannot setup interrupt.\n");
+ goto fail;
+ }
+#endif
+ return (bus_generic_attach(dev));
+
+fail:
+ if (sc->irq_h != NULL)
+ bus_teardown_intr(dev, sc->irq_res, sc->irq_h);
+ if (sc->irq_res != NULL)
+ bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res);
+ LOCK_DESTROY(sc);
+ return (rv);
+}
+
+static int
+max77620_detach(device_t dev)
+{
+ struct max77620_softc *sc;
+
+ sc = device_get_softc(dev);
+ if (sc->irq_h != NULL)
+ bus_teardown_intr(dev, sc->irq_res, sc->irq_h);
+ if (sc->irq_res != NULL)
+ bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res);
+ LOCK_DESTROY(sc);
+
+ return (bus_generic_detach(dev));
+}
+
+static phandle_t
+max77620_gpio_get_node(device_t bus, device_t dev)
+{
+
+ /* We only have one child, the GPIO bus, which needs our own node. */
+ return (ofw_bus_get_node(bus));
+}
+
+static device_method_t max77620_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, max77620_probe),
+ DEVMETHOD(device_attach, max77620_attach),
+ DEVMETHOD(device_detach, max77620_detach),
+
+ /* Regdev interface */
+ DEVMETHOD(regdev_map, max77620_regulator_map),
+
+ /* GPIO protocol interface */
+ DEVMETHOD(gpio_get_bus, max77620_gpio_get_bus),
+ DEVMETHOD(gpio_pin_max, max77620_gpio_pin_max),
+ DEVMETHOD(gpio_pin_getname, max77620_gpio_pin_getname),
+ DEVMETHOD(gpio_pin_getflags, max77620_gpio_pin_getflags),
+ DEVMETHOD(gpio_pin_getcaps, max77620_gpio_pin_getcaps),
+ DEVMETHOD(gpio_pin_setflags, max77620_gpio_pin_setflags),
+ DEVMETHOD(gpio_pin_get, max77620_gpio_pin_get),
+ DEVMETHOD(gpio_pin_set, max77620_gpio_pin_set),
+ DEVMETHOD(gpio_pin_toggle, max77620_gpio_pin_toggle),
+ DEVMETHOD(gpio_map_gpios, max77620_gpio_map_gpios),
+
+ /* fdt_pinctrl interface */
+ DEVMETHOD(fdt_pinctrl_configure, max77620_pinmux_configure),
+
+ /* ofw_bus interface */
+ DEVMETHOD(ofw_bus_get_node, max77620_gpio_get_node),
+
+ DEVMETHOD_END
+};
+
+static devclass_t max77620_devclass;
+static DEFINE_CLASS_0(gpio, max77620_driver, max77620_methods,
+ sizeof(struct max77620_softc));
+EARLY_DRIVER_MODULE(max77620, iicbus, max77620_driver, max77620_devclass,
+ NULL, NULL, 74);
diff --git a/sys/arm64/nvidia/tegra210/max77620.h b/sys/arm64/nvidia/tegra210/max77620.h
new file mode 100644
index 000000000000..32d486add2b8
--- /dev/null
+++ b/sys/arm64/nvidia/tegra210/max77620.h
@@ -0,0 +1,262 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
+ *
+ * Copyright 2020 Michal Meloun <mmel@FreeBSD.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef _MAX77620_H_
+
+#include <sys/clock.h>
+
+#define MAX77620_REG_CNFGGLBL1 0x00
+#define MAX77620_REG_CNFGGLBL2 0x01
+#define MAX77620_REG_CNFGGLBL3 0x02
+#define MAX77620_REG_CNFG1_32K 0x03
+#define MAX77620_REG_CNFGBBC 0x04
+#define MAX77620_REG_IRQTOP 0x05
+#define MAX77620_REG_INTLBT 0x06
+#define MAX77620_REG_IRQSD 0x07
+#define MAX77620_REG_IRQ_LVL2_L0_7 0x08
+#define MAX77620_REG_IRQ_LVL2_L8 0x09
+#define MAX77620_REG_IRQ_LVL2_GPIO 0x0A
+#define MAX77620_REG_ONOFFIRQ 0x0B
+#define MAX77620_REG_NVERC 0x0C
+#define MAX77620_REG_IRQTOPM 0x0D
+#define MAX77620_REG_INTENLBT 0x0E
+#define MAX77620_REG_IRQMASKSD 0x0F
+#define MAX77620_REG_IRQ_MSK_L0_7 0x10
+#define MAX77620_REG_IRQ_MSK_L8 0x11
+#define MAX77620_REG_ONOFFIRQM 0x12
+#define MAX77620_REG_STATLBT 0x13
+#define MAX77620_REG_STATSD 0x14
+#define MAX77620_REG_ONOFFSTAT 0x15
+#define MAX77620_REG_SD0 0x16
+#define MAX77620_SD0_VSEL_MASK 0x3F
+
+#define MAX77620_REG_SD1 0x17
+#define MAX77620_SD1_VSEL_MASK 0x7F
+
+#define MAX77620_REG_SD2 0x18
+#define MAX77620_REG_SD3 0x19
+#define MAX77620_REG_SD4 0x1A
+#define MAX77620_SDX_VSEL_MASK 0xFF
+
+#define MAX77620_REG_DVSSD0 0x1B
+#define MAX77620_REG_DVSSD1 0x1C
+#define MAX77620_REG_CFG_SD0 0x1D
+#define MAX77620_REG_CFG_SD1 0x1E
+#define MAX77620_REG_CFG_SD2 0x1F
+#define MAX77620_REG_CFG_SD3 0x20
+#define MAX77620_REG_CFG_SD4 0x21
+#define MAX77620_SD_SR_MASK 0xC0
+#define MAX77620_SD_SR_SHIFT 6
+#define MAX77620_SD_POWER_MODE_MASK 0x30
+#define MAX77620_SD_POWER_MODE_SHIFT 4
+#define MAX77620_SD_FPWM_MASK 0x04
+#define MAX77620_SD_FPWM_SHIFT 2
+#define MAX77620_SD_FSRADE_MASK 0x01
+#define MAX77620_SD_FSRADE_SHIFT 0
+
+#define MAX77620_REG_CFG2_SD 0x22
+#define MAX77620_REG_CFG_LDO0 0x23
+#define MAX77620_REG_CFG2_LDO0 0x24
+#define MAX77620_REG_CFG_LDO1 0x25
+#define MAX77620_REG_CFG2_LDO1 0x26
+#define MAX77620_REG_CFG_LDO2 0x27
+#define MAX77620_REG_CFG2_LDO2 0x28
+#define MAX77620_REG_CFG_LDO3 0x29
+#define MAX77620_REG_CFG2_LDO3 0x2A
+#define MAX77620_REG_CFG_LDO4 0x2B
+#define MAX77620_REG_CFG2_LDO4 0x2C
+#define MAX77620_REG_CFG_LDO5 0x2D
+#define MAX77620_REG_CFG2_LDO5 0x2E
+#define MAX77620_REG_CFG_LDO6 0x2F
+#define MAX77620_REG_CFG2_LDO6 0x30
+#define MAX77620_REG_CFG_LDO7 0x31
+#define MAX77620_REG_CFG2_LDO7 0x32
+#define MAX77620_REG_CFG_LDO8 0x33
+#define MAX77620_LDO_POWER_MODE_MASK 0xC0
+#define MAX77620_LDO_POWER_MODE_SHIFT 6
+#define MAX77620_LDO_VSEL_MASK 0x3F
+
+#define MAX77620_REG_CFG2_LDO8 0x34
+#define MAX77620_LDO_SLEW_RATE_MASK 0x1
+#define MAX77620_LDO_SLEW_RATE_SHIFT 0x0
+
+#define MAX77620_REG_CFG3_LDO 0x35
+
+#define MAX77620_REG_GPIO0 0x36
+#define MAX77620_REG_GPIO1 0x37
+#define MAX77620_REG_GPIO2 0x38
+#define MAX77620_REG_GPIO3 0x39
+#define MAX77620_REG_GPIO4 0x3A
+#define MAX77620_REG_GPIO5 0x3B
+#define MAX77620_REG_GPIO6 0x3C
+#define MAX77620_REG_GPIO7 0x3D
+#define MAX77620_REG_GPIO_INT_GET(x) (((x) >> 5) & 0x3)
+#define MAX77620_REG_GPIO_INT(x) (((x) & 0x3) << 5)
+#define MAX77620_REG_GPIO_INT_NONE 0
+#define MAX77620_REG_GPIO_INT_FALLING 1
+#define MAX77620_REG_GPIO_INT_RISING 2
+#define MAX77620_REG_GPIO_INT_BOTH 3
+#define MAX77620_REG_GPIO_OUTPUT_VAL_GET(x) (((x) >> 3) & 0x1)
+#define MAX77620_REG_GPIO_OUTPUT_VAL(x) (((x) & 0x1) << 3)
+#define MAX77620_REG_GPIO_INPUT_VAL_GET(x) (((x) << 2) & 0x1)
+#define MAX77620_REG_GPIO_INPUT_VAL (1 << 2)
+#define MAX77620_REG_GPIO_DRV_GET(x) (((x) >> 0) & 0x1)
+#define MAX77620_REG_GPIO_DRV(x) (((x) & 0x1) << 0)
+#define MAX77620_REG_GPIO_DRV_PUSHPULL 1
+#define MAX77620_REG_GPIO_DRV_OPENDRAIN 0
+
+#define MAX77620_REG_PUE_GPIO 0x3E
+#define MAX77620_REG_PDE_GPIO 0x3F
+#define MAX77620_REG_AME_GPIO 0x40
+#define MAX77620_REG_ONOFFCNFG1 0x41
+#define MAX77620_REG_ONOFFCNFG2 0x42
+
+#define MAX77620_REG_FPS_CFG0 0x43
+#define MAX77620_REG_FPS_CFG1 0x44
+#define MAX77620_REG_FPS_CFG2 0x45
+#define MAX77620_FPS_TIME_PERIOD_MASK 0x38
+#define MAX77620_FPS_TIME_PERIOD_SHIFT 3
+#define MAX77620_FPS_EN_SRC_MASK 0x06
+#define MAX77620_FPS_EN_SRC_SHIFT 1
+#define MAX77620_FPS_ENFPS_SW_MASK 0x01
+#define MAX77620_FPS_ENFPS_SW 0x01
+
+#define MAX77620_REG_FPS_LDO0 0x46
+#define MAX77620_REG_FPS_LDO1 0x47
+#define MAX77620_REG_FPS_LDO2 0x48
+#define MAX77620_REG_FPS_LDO3 0x49
+#define MAX77620_REG_FPS_LDO4 0x4A
+#define MAX77620_REG_FPS_LDO5 0x4B
+#define MAX77620_REG_FPS_LDO6 0x4C
+#define MAX77620_REG_FPS_LDO7 0x4D
+#define MAX77620_REG_FPS_LDO8 0x4E
+#define MAX77620_REG_FPS_SD0 0x4F
+#define MAX77620_REG_FPS_SD1 0x50
+#define MAX77620_REG_FPS_SD2 0x51
+#define MAX77620_REG_FPS_SD3 0x52
+#define MAX77620_REG_FPS_SD4 0x53
+#define MAX77620_REG_FPS_GPIO1 0x54
+#define MAX77620_REG_FPS_GPIO2 0x55
+#define MAX77620_REG_FPS_GPIO3 0x56
+#define MAX77620_REG_FPS_RSO 0x57
+#define MAX77620_FPS_SRC_MASK 0xC0
+#define MAX77620_FPS_SRC_SHIFT 6
+#define MAX77620_FPS_PU_PERIOD_MASK 0x38
+#define MAX77620_FPS_PU_PERIOD_SHIFT 3
+#define MAX77620_FPS_PD_PERIOD_MASK 0x07
+#define MAX77620_FPS_PD_PERIOD_SHIFT 0
+
+#define MAX77620_REG_CID0 0x58
+#define MAX77620_REG_CID1 0x59
+#define MAX77620_REG_CID2 0x5A
+#define MAX77620_REG_CID3 0x5B
+#define MAX77620_REG_CID4 0x5C
+#define MAX77620_REG_CID5 0x5D
+#define MAX77620_REG_DVSSD4 0x5E
+#define MAX20024_REG_MAX_ADD 0x70
+
+/* MIsc FPS definitions. */
+#define MAX77620_FPS_COUNT 3
+#define MAX77620_FPS_PERIOD_MIN_US 40
+#define MAX77620_FPS_PERIOD_MAX_US 2560
+
+/* Power modes */
+#define MAX77620_POWER_MODE_NORMAL 3
+#define MAX77620_POWER_MODE_LPM 2
+#define MAX77620_POWER_MODE_GLPM 1
+#define MAX77620_POWER_MODE_DISABLE 0
+
+
+struct max77620_reg_sc;
+struct max77620_gpio_pin;
+
+struct max77620_softc {
+ device_t dev;
+ struct sx lock;
+ int bus_addr;
+ struct resource *irq_res;
+ void *irq_h;
+
+ int shutdown_fps[MAX77620_FPS_COUNT];
+ int suspend_fps[MAX77620_FPS_COUNT];
+ int event_source[MAX77620_FPS_COUNT];
+
+ /* Regulators. */
+ struct max77620_reg_sc **regs;
+ int nregs;
+
+ /* GPIO */
+ device_t gpio_busdev;
+ struct max77620_gpio_pin **gpio_pins;
+ int gpio_npins;
+ struct sx gpio_lock;
+ uint8_t gpio_reg_pue; /* pull-up enables */
+ uint8_t gpio_reg_pde; /* pull-down enables */
+ uint8_t gpio_reg_ame; /* alternate fnc */
+
+
+};
+
+#define RD1(sc, reg, val) max77620_read(sc, reg, val)
+#define WR1(sc, reg, val) max77620_write(sc, reg, val)
+#define RM1(sc, reg, clr, set) max77620_modify(sc, reg, clr, set)
+
+int max77620_read(struct max77620_softc *sc, uint8_t reg, uint8_t *val);
+int max77620_write(struct max77620_softc *sc, uint8_t reg, uint8_t val);
+int max77620_modify(struct max77620_softc *sc, uint8_t reg, uint8_t clear,
+ uint8_t set);
+int max77620_read_buf(struct max77620_softc *sc, uint8_t reg, uint8_t *buf,
+ size_t size);
+int max77620_write_buf(struct max77620_softc *sc, uint8_t reg, uint8_t *buf,
+ size_t size);
+
+/* Regulators */
+int max77620_regulator_attach(struct max77620_softc *sc, phandle_t node);
+int max77620_regulator_map(device_t dev, phandle_t xref, int ncells,
+ pcell_t *cells, intptr_t *num);
+
+/* RTC */
+int max77620_rtc_create(struct max77620_softc *sc, phandle_t node);
+
+/* GPIO */
+device_t max77620_gpio_get_bus(device_t dev);
+int max77620_gpio_pin_max(device_t dev, int *maxpin);
+int max77620_gpio_pin_getname(device_t dev, uint32_t pin, char *name);
+int max77620_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags);
+int max77620_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps);
+int max77620_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags);
+int max77620_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value);
+int max77620_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val);
+int max77620_gpio_pin_toggle(device_t dev, uint32_t pin);
+int max77620_gpio_map_gpios(device_t dev, phandle_t pdev, phandle_t gparent,
+ int gcells, pcell_t *gpios, uint32_t *pin, uint32_t *flags);
+int max77620_gpio_attach(struct max77620_softc *sc, phandle_t node);
+int max77620_pinmux_configure(device_t dev, phandle_t cfgxref);
+
+#endif /* _MAX77620_H_ */
diff --git a/sys/arm64/nvidia/tegra210/max77620_gpio.c b/sys/arm64/nvidia/tegra210/max77620_gpio.c
new file mode 100644
index 000000000000..2e9156801d97
--- /dev/null
+++ b/sys/arm64/nvidia/tegra210/max77620_gpio.c
@@ -0,0 +1,715 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
+ *
+ * Copyright 2020 Michal Meloun <mmel@FreeBSD.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/gpio.h>
+#include <sys/kernel.h>
+#include <sys/malloc.h>
+#include <sys/sx.h>
+
+#include <machine/bus.h>
+
+#include <dev/fdt/fdt_common.h>
+#include <dev/gpio/gpiobusvar.h>
+
+#include "max77620.h"
+
+MALLOC_DEFINE(M_MAX77620_GPIO, "MAX77620 gpio", "MAX77620 GPIO");
+
+#define NGPIO 8
+
+#define GPIO_LOCK(_sc) sx_slock(&(_sc)->gpio_lock)
+#define GPIO_UNLOCK(_sc) sx_unlock(&(_sc)->gpio_lock)
+#define GPIO_ASSERT(_sc) sx_assert(&(_sc)->gpio_lock, SA_LOCKED)
+
+enum prop_id {
+ CFG_BIAS_PULL_UP,
+ CFG_BIAS_PULL_DOWN,
+ CFG_OPEN_DRAIN,
+ CFG_PUSH_PULL,
+
+ CFG_ACTIVE_FPS_SRC,
+ CFG_ACTIVE_PWRUP_SLOT,
+ CFG_ACTIVE_PWRDOWN_SLOT,
+ CFG_SUSPEND_FPS_SRC,
+ CFG_SUSPEND_PWRUP_SLOT,
+ CFG_SUSPEND_PWRDOWN_SLOT,
+
+ PROP_ID_MAX_ID
+};
+
+static const struct {
+ const char *name;
+ enum prop_id id;
+} max77620_prop_names[] = {
+ {"bias-pull-up", CFG_BIAS_PULL_UP},
+ {"bias-pull-down", CFG_BIAS_PULL_DOWN},
+ {"drive-open-drain", CFG_OPEN_DRAIN},
+ {"drive-push-pull", CFG_PUSH_PULL},
+ {"maxim,active-fps-source", CFG_ACTIVE_FPS_SRC},
+ {"maxim,active-fps-power-up-slot", CFG_ACTIVE_PWRUP_SLOT},
+ {"maxim,active-fps-power-down-slot", CFG_ACTIVE_PWRDOWN_SLOT},
+ {"maxim,suspend-fps-source", CFG_SUSPEND_FPS_SRC},
+ {"maxim,suspend-fps-power-up-slot", CFG_SUSPEND_PWRUP_SLOT},
+ {"maxim,suspend-fps-power-down-slot", CFG_SUSPEND_PWRDOWN_SLOT},
+};
+
+/* Configuration for one pin group. */
+struct max77620_pincfg {
+ bool alt_func;
+ int params[PROP_ID_MAX_ID];
+};
+
+static char *altfnc_table[] = {
+ "lpm-control-in",
+ "fps-out",
+ "32k-out1",
+ "sd0-dvs-in",
+ "sd1-dvs-in",
+ "reference-out",
+};
+
+struct max77620_gpio_pin {
+ int pin_caps;
+ char pin_name[GPIOMAXNAME];
+ uint8_t reg;
+
+ /* Runtime data */
+ bool alt_func; /* GPIO or alternate function */
+};
+
+/* --------------------------------------------------------------------------
+ *
+ * Pinmux functions.
+ */
+static int
+max77620_pinmux_get_function(struct max77620_softc *sc, char *name,
+ struct max77620_pincfg *cfg)
+{
+ int i;
+
+ if (strcmp("gpio", name) == 0) {
+ cfg->alt_func = false;
+ return (0);
+ }
+ for (i = 0; i < nitems(altfnc_table); i++) {
+ if (strcmp(altfnc_table[i], name) == 0) {
+ cfg->alt_func = true;
+ return (0);
+ }
+ }
+ return (-1);
+}
+
+static int
+max77620_pinmux_set_fps(struct max77620_softc *sc, int pin_num,
+ struct max77620_gpio_pin *pin)
+{
+#if 0
+ struct max77620_fps_config *fps_config = &mpci->fps_config[pin];
+ int addr, ret;
+ int param_val;
+ int mask, shift;
+
+ if ((pin < 1) || (pin > 3))
+ return (0);
+
+ switch (param) {
+ case MAX77620_ACTIVE_FPS_SOURCE:
+ case MAX77620_SUSPEND_FPS_SOURCE:
+ mask = MAX77620_FPS_SRC_MASK;
+ shift = MAX77620_FPS_SRC_SHIFT;
+ param_val = fps_config->active_fps_src;
+ if (param == MAX77620_SUSPEND_FPS_SOURCE)
+ param_val = fps_config->suspend_fps_src;
+ break;
+
+ case MAX77620_ACTIVE_FPS_POWER_ON_SLOTS:
+ case MAX77620_SUSPEND_FPS_POWER_ON_SLOTS:
+ mask = MAX77620_FPS_PU_PERIOD_MASK;
+ shift = MAX77620_FPS_PU_PERIOD_SHIFT;
+ param_val = fps_config->active_power_up_slots;
+ if (param == MAX77620_SUSPEND_FPS_POWER_ON_SLOTS)
+ param_val = fps_config->suspend_power_up_slots;
+ break;
+
+ case MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS:
+ case MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS:
+ mask = MAX77620_FPS_PD_PERIOD_MASK;
+ shift = MAX77620_FPS_PD_PERIOD_SHIFT;
+ param_val = fps_config->active_power_down_slots;
+ if (param == MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS)
+ param_val = fps_config->suspend_power_down_slots;
+ break;
+
+ default:
+ dev_err(mpci->dev, "Invalid parameter %d for pin %d\n",
+ param, pin);
+ return -EINVAL;
+ }
+
+ if (param_val < 0)
+ return 0;
+
+ ret = regmap_update_bits(mpci->rmap, addr, mask, param_val << shift);
+ if (ret < 0)
+ dev_err(mpci->dev, "Reg 0x%02x update failed %d\n", addr, ret);
+
+ return ret;
+#endif
+ return (0);
+}
+
+static int
+max77620_pinmux_config_node(struct max77620_softc *sc, char *pin_name,
+ struct max77620_pincfg *cfg)
+{
+ struct max77620_gpio_pin *pin;
+ uint8_t reg;
+ int pin_num, rv;
+
+ for (pin_num = 0; pin_num < sc->gpio_npins; pin_num++) {
+ if (strcmp(sc->gpio_pins[pin_num]->pin_name, pin_name) == 0)
+ break;
+ }
+ if (pin_num >= sc->gpio_npins) {
+ device_printf(sc->dev, "Unknown pin: %s\n", pin_name);
+ return (ENXIO);
+ }
+ pin = sc->gpio_pins[pin_num];
+
+ rv = max77620_pinmux_set_fps(sc, pin_num, pin);
+ if (rv != 0)
+ return (rv);
+
+ rv = RD1(sc, pin->reg, &reg);
+ if (rv != 0) {
+ device_printf(sc->dev, "Cannot read GIPO_CFG register\n");
+ return (ENXIO);
+ }
+
+ if (cfg->alt_func) {
+ pin->alt_func = true;
+ sc->gpio_reg_ame |= 1 << pin_num;
+ } else {
+ pin->alt_func = false;
+ sc->gpio_reg_ame &= ~(1 << pin_num);
+ }
+
+ /* Pull up/down. */
+ switch (cfg->params[CFG_BIAS_PULL_UP]) {
+ case 1:
+ sc->gpio_reg_pue |= 1 << pin_num;
+ break;
+ case 0:
+ sc->gpio_reg_pue &= ~(1 << pin_num);
+ break;
+ default:
+ break;
+ }
+
+ switch (cfg->params[CFG_BIAS_PULL_DOWN]) {
+ case 1:
+ sc->gpio_reg_pde |= 1 << pin_num;
+ break;
+ case 0:
+ sc->gpio_reg_pde &= ~(1 << pin_num);
+ break;
+ default:
+ break;
+ }
+
+ /* Open drain/push-pull modes. */
+ if (cfg->params[CFG_OPEN_DRAIN] == 1) {
+ reg &= ~MAX77620_REG_GPIO_DRV(~0);
+ reg |= MAX77620_REG_GPIO_DRV(MAX77620_REG_GPIO_DRV_OPENDRAIN);
+ }
+
+ if (cfg->params[CFG_PUSH_PULL] == 1) {
+ reg &= ~MAX77620_REG_GPIO_DRV(~0);
+ reg |= MAX77620_REG_GPIO_DRV(MAX77620_REG_GPIO_DRV_PUSHPULL);
+ }
+
+ rv = WR1(sc, pin->reg, reg);
+ if (rv != 0) {
+ device_printf(sc->dev, "Cannot read GIPO_CFG register\n");
+ return (ENXIO);
+ }
+
+ return (0);
+}
+
+static int
+max77620_pinmux_read_node(struct max77620_softc *sc, phandle_t node,
+ struct max77620_pincfg *cfg, char **pins, int *lpins)
+{
+ char *function;
+ int rv, i;
+
+ *lpins = OF_getprop_alloc(node, "pins", (void **)pins);
+ if (*lpins <= 0)
+ return (ENOENT);
+
+ /* Read function (mux) settings. */
+ rv = OF_getprop_alloc(node, "function", (void **)&function);
+ if (rv > 0) {
+ rv = max77620_pinmux_get_function(sc, function, cfg);
+ if (rv == -1) {
+ device_printf(sc->dev,
+ "Unknown function %s\n", function);
+ OF_prop_free(function);
+ return (ENXIO);
+ }
+ }
+
+ /* Read numeric properties. */
+ for (i = 0; i < PROP_ID_MAX_ID; i++) {
+ rv = OF_getencprop(node, max77620_prop_names[i].name,
+ &cfg->params[i], sizeof(cfg->params[i]));
+ if (rv <= 0)
+ cfg->params[i] = -1;
+ }
+
+ OF_prop_free(function);
+ return (0);
+}
+
+static int
+max77620_pinmux_process_node(struct max77620_softc *sc, phandle_t node)
+{
+ struct max77620_pincfg cfg;
+ char *pins, *pname;
+ int i, len, lpins, rv;
+
+ rv = max77620_pinmux_read_node(sc, node, &cfg, &pins, &lpins);
+ if (rv != 0)
+ return (rv);
+
+ len = 0;
+ pname = pins;
+ do {
+ i = strlen(pname) + 1;
+ rv = max77620_pinmux_config_node(sc, pname, &cfg);
+ if (rv != 0) {
+ device_printf(sc->dev,
+ "Cannot configure pin: %s: %d\n", pname, rv);
+ }
+ len += i;
+ pname += i;
+ } while (len < lpins);
+
+ if (pins != NULL)
+ OF_prop_free(pins);
+
+ return (rv);
+}
+
+int max77620_pinmux_configure(device_t dev, phandle_t cfgxref)
+{
+ struct max77620_softc *sc;
+ phandle_t node, cfgnode;
+ uint8_t old_reg_pue, old_reg_pde, old_reg_ame;
+ int rv;
+
+ sc = device_get_softc(dev);
+ cfgnode = OF_node_from_xref(cfgxref);
+
+ old_reg_pue = sc->gpio_reg_pue;
+ old_reg_pde = sc->gpio_reg_pde;
+ old_reg_ame = sc->gpio_reg_ame;
+
+ for (node = OF_child(cfgnode); node != 0; node = OF_peer(node)) {
+ if (!ofw_bus_node_status_okay(node))
+ continue;
+ rv = max77620_pinmux_process_node(sc, node);
+ if (rv != 0)
+ device_printf(dev, "Failed to process pinmux");
+
+ }
+
+ if (old_reg_pue != sc->gpio_reg_pue) {
+ rv = WR1(sc, MAX77620_REG_PUE_GPIO, sc->gpio_reg_pue);
+ if (rv != 0) {
+ device_printf(sc->dev,
+ "Cannot update PUE_GPIO register\n");
+ return (ENXIO);
+ }
+ }
+
+ if (old_reg_pde != sc->gpio_reg_pde) {
+ rv = WR1(sc, MAX77620_REG_PDE_GPIO, sc->gpio_reg_pde);
+ if (rv != 0) {
+ device_printf(sc->dev,
+ "Cannot update PDE_GPIO register\n");
+ return (ENXIO);
+ }
+ }
+
+ if (old_reg_ame != sc->gpio_reg_ame) {
+ rv = WR1(sc, MAX77620_REG_AME_GPIO, sc->gpio_reg_ame);
+ if (rv != 0) {
+ device_printf(sc->dev,
+ "Cannot update PDE_GPIO register\n");
+ return (ENXIO);
+ }
+ }
+
+ return (0);
+}
+
+/* --------------------------------------------------------------------------
+ *
+ * GPIO
+ */
+device_t
+max77620_gpio_get_bus(device_t dev)
+{
+ struct max77620_softc *sc;
+
+ sc = device_get_softc(dev);
+ return (sc->gpio_busdev);
+}
+
+int
+max77620_gpio_pin_max(device_t dev, int *maxpin)
+{
+
+ *maxpin = NGPIO - 1;
+ return (0);
+}
+
+int
+max77620_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
+{
+ struct max77620_softc *sc;
+
+ sc = device_get_softc(dev);
+ if (pin >= sc->gpio_npins)
+ return (EINVAL);
+ GPIO_LOCK(sc);
+ *caps = sc->gpio_pins[pin]->pin_caps;
+ GPIO_UNLOCK(sc);
+ return (0);
+}
+
+int
+max77620_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
+{
+ struct max77620_softc *sc;
+
+ sc = device_get_softc(dev);
+ if (pin >= sc->gpio_npins)
+ return (EINVAL);
+ GPIO_LOCK(sc);
+ memcpy(name, sc->gpio_pins[pin]->pin_name, GPIOMAXNAME);
+ GPIO_UNLOCK(sc);
+ return (0);
+}
+
+static int
+max77620_gpio_get_mode(struct max77620_softc *sc, uint32_t pin_num,
+ uint32_t *out_flags)
+{
+ struct max77620_gpio_pin *pin;
+ uint8_t reg;
+ int rv;
+
+ pin = sc->gpio_pins[pin_num];
+ *out_flags = 0;
+
+ rv = RD1(sc, pin->reg, &reg);
+ if (rv != 0) {
+ device_printf(sc->dev, "Cannot read GIPO_CFG register\n");
+ return (ENXIO);
+ }
+
+ /* Pin function */
+ pin->alt_func = sc->gpio_reg_ame & (1 << pin_num);
+
+ /* Pull up/down. */
+ if (sc->gpio_reg_pue & (1 << pin_num))
+ *out_flags |= GPIO_PIN_PULLUP;
+ if (sc->gpio_reg_pde & (1 << pin_num))
+ *out_flags |= GPIO_PIN_PULLDOWN;
+
+ /* Open drain/push-pull modes. */
+ if (MAX77620_REG_GPIO_DRV_GET(reg) == MAX77620_REG_GPIO_DRV_PUSHPULL)
+ *out_flags |= GPIO_PIN_PUSHPULL;
+ else
+ *out_flags |= GPIO_PIN_OPENDRAIN;
+
+ /* Input/output modes. */
+ if (MAX77620_REG_GPIO_DRV_GET(reg) == MAX77620_REG_GPIO_DRV_PUSHPULL)
+ *out_flags |= GPIO_PIN_OUTPUT;
+ else
+ *out_flags |= GPIO_PIN_OUTPUT | GPIO_PIN_INPUT;
+ return (0);
+}
+
+int
+max77620_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *out_flags)
+{
+ struct max77620_softc *sc;
+ int rv;
+
+ sc = device_get_softc(dev);
+ if (pin >= sc->gpio_npins)
+ return (EINVAL);
+
+ GPIO_LOCK(sc);
+#if 0 /* It colide with GPIO regulators */
+ /* Is pin in GPIO mode ? */
+ if (sc->gpio_pins[pin]->alt_func) {
+ GPIO_UNLOCK(sc);
+ return (ENXIO);
+ }
+#endif
+ rv = max77620_gpio_get_mode(sc, pin, out_flags);
+ GPIO_UNLOCK(sc);
+
+ return (rv);
+}
+
+int
+max77620_gpio_pin_setflags(device_t dev, uint32_t pin_num, uint32_t flags)
+{
+ struct max77620_softc *sc;
+ struct max77620_gpio_pin *pin;
+ uint8_t reg;
+ uint8_t old_reg_pue, old_reg_pde;
+ int rv;
+
+ sc = device_get_softc(dev);
+ if (pin_num >= sc->gpio_npins)
+ return (EINVAL);
+
+ pin = sc->gpio_pins[pin_num];
+
+ GPIO_LOCK(sc);
+
+#if 0 /* It colide with GPIO regulators */
+ /* Is pin in GPIO mode ? */
+ if (pin->alt_func) {
+ GPIO_UNLOCK(sc);
+ return (ENXIO);
+ }
+#endif
+
+ old_reg_pue = sc->gpio_reg_pue;
+ old_reg_pde = sc->gpio_reg_pde;
+
+ rv = RD1(sc, pin->reg, &reg);
+ if (rv != 0) {
+ device_printf(sc->dev, "Cannot read GIPO_CFG register\n");
+ GPIO_UNLOCK(sc);
+ return (ENXIO);
+ }
+
+ if (flags & GPIO_PIN_PULLUP)
+ sc->gpio_reg_pue |= 1 << pin_num;
+ else
+ sc->gpio_reg_pue &= ~(1 << pin_num);
+
+ if (flags & GPIO_PIN_PULLDOWN)
+ sc->gpio_reg_pde |= 1 << pin_num;
+ else
+ sc->gpio_reg_pde &= ~(1 << pin_num);
+
+ if (flags & GPIO_PIN_INPUT) {
+ reg &= ~MAX77620_REG_GPIO_DRV(~0);
+ reg |= MAX77620_REG_GPIO_DRV(MAX77620_REG_GPIO_DRV_OPENDRAIN);
+ reg &= ~MAX77620_REG_GPIO_OUTPUT_VAL(~0);
+ reg |= MAX77620_REG_GPIO_OUTPUT_VAL(1);
+
+ } else if (((flags & GPIO_PIN_OUTPUT) &&
+ (flags & GPIO_PIN_OPENDRAIN) == 0) ||
+ (flags & GPIO_PIN_PUSHPULL)) {
+ reg &= ~MAX77620_REG_GPIO_DRV(~0);
+ reg |= MAX77620_REG_GPIO_DRV(MAX77620_REG_GPIO_DRV_PUSHPULL);
+ } else {
+ reg &= ~MAX77620_REG_GPIO_DRV(~0);
+ reg |= MAX77620_REG_GPIO_DRV(MAX77620_REG_GPIO_DRV_OPENDRAIN);
+ }
+
+ rv = WR1(sc, pin->reg, reg);
+ if (rv != 0) {
+ device_printf(sc->dev, "Cannot read GIPO_CFG register\n");
+ return (ENXIO);
+ }
+ if (old_reg_pue != sc->gpio_reg_pue) {
+ rv = WR1(sc, MAX77620_REG_PUE_GPIO, sc->gpio_reg_pue);
+ if (rv != 0) {
+ device_printf(sc->dev,
+ "Cannot update PUE_GPIO register\n");
+ GPIO_UNLOCK(sc);
+ return (ENXIO);
+ }
+ }
+
+ if (old_reg_pde != sc->gpio_reg_pde) {
+ rv = WR1(sc, MAX77620_REG_PDE_GPIO, sc->gpio_reg_pde);
+ if (rv != 0) {
+ device_printf(sc->dev,
+ "Cannot update PDE_GPIO register\n");
+ GPIO_UNLOCK(sc);
+ return (ENXIO);
+ }
+ }
+
+ GPIO_UNLOCK(sc);
+ return (0);
+}
+
+int
+max77620_gpio_pin_set(device_t dev, uint32_t pin, uint32_t val)
+{
+ struct max77620_softc *sc;
+ int rv;
+
+ sc = device_get_softc(dev);
+ if (pin >= sc->gpio_npins)
+ return (EINVAL);
+
+ GPIO_LOCK(sc);
+ rv = RM1(sc, sc->gpio_pins[pin]->reg, MAX77620_REG_GPIO_OUTPUT_VAL(~0),
+ MAX77620_REG_GPIO_OUTPUT_VAL(val));
+ GPIO_UNLOCK(sc);
+ return (rv);
+}
+
+int
+max77620_gpio_pin_get(device_t dev, uint32_t pin, uint32_t *val)
+{
+ struct max77620_softc *sc;
+ uint8_t tmp;
+ int rv;
+
+ sc = device_get_softc(dev);
+ if (pin >= sc->gpio_npins)
+ return (EINVAL);
+
+ GPIO_LOCK(sc);
+ rv = RD1(sc, sc->gpio_pins[pin]->reg, &tmp);
+
+ if (MAX77620_REG_GPIO_DRV_GET(tmp) == MAX77620_REG_GPIO_DRV_PUSHPULL)
+ *val = MAX77620_REG_GPIO_OUTPUT_VAL_GET(tmp);
+ else
+ *val = MAX77620_REG_GPIO_INPUT_VAL_GET(tmp);
+ GPIO_UNLOCK(sc);
+ if (rv != 0)
+ return (rv);
+
+ return (0);
+}
+
+int
+max77620_gpio_pin_toggle(device_t dev, uint32_t pin)
+{
+ struct max77620_softc *sc;
+ uint8_t tmp;
+ int rv;
+
+ sc = device_get_softc(dev);
+ if (pin >= sc->gpio_npins)
+ return (EINVAL);
+
+ GPIO_LOCK(sc);
+ rv = RD1(sc, sc->gpio_pins[pin]->reg, &tmp);
+ if (rv != 0) {
+ GPIO_UNLOCK(sc);
+ return (rv);
+ }
+ tmp ^= MAX77620_REG_GPIO_OUTPUT_VAL(~0);
+ rv = RM1(sc, sc->gpio_pins[pin]->reg, MAX77620_REG_GPIO_OUTPUT_VAL(~0),
+ tmp);
+ GPIO_UNLOCK(sc);
+ return (0);
+}
+
+int
+max77620_gpio_map_gpios(device_t dev, phandle_t pdev, phandle_t gparent,
+ int gcells, pcell_t *gpios, uint32_t *pin, uint32_t *flags)
+{
+
+ if (gcells != 2)
+ return (ERANGE);
+ *pin = gpios[0];
+ *flags= gpios[1];
+ return (0);
+}
+
+int
+max77620_gpio_attach(struct max77620_softc *sc, phandle_t node)
+{
+ struct max77620_gpio_pin *pin;
+ int i, rv;
+
+ sx_init(&sc->gpio_lock, "MAX77620 GPIO lock");
+
+ sc->gpio_busdev = gpiobus_attach_bus(sc->dev);
+ if (sc->gpio_busdev == NULL)
+ return (ENXIO);
+
+ rv = RD1(sc, MAX77620_REG_PUE_GPIO, &sc->gpio_reg_pue);
+ if (rv != 0) {
+ device_printf(sc->dev, "Cannot read PUE_GPIO register\n");
+ return (ENXIO);
+ }
+
+ rv = RD1(sc, MAX77620_REG_PDE_GPIO, &sc->gpio_reg_pde);
+ if (rv != 0) {
+ device_printf(sc->dev, "Cannot read PDE_GPIO register\n");
+ return (ENXIO);
+ }
+
+ rv = RD1(sc, MAX77620_REG_AME_GPIO, &sc->gpio_reg_ame);
+ if (rv != 0) {
+ device_printf(sc->dev, "Cannot read AME_GPIO register\n");
+ return (ENXIO);
+ }
+
+ sc->gpio_npins = NGPIO;
+ sc->gpio_pins = malloc(sizeof(struct max77620_gpio_pin *) *
+ sc->gpio_npins, M_MAX77620_GPIO, M_WAITOK | M_ZERO);
+ for (i = 0; i < sc->gpio_npins; i++) {
+ sc->gpio_pins[i] = malloc(sizeof(struct max77620_gpio_pin),
+ M_MAX77620_GPIO, M_WAITOK | M_ZERO);
+ pin = sc->gpio_pins[i];
+ sprintf(pin->pin_name, "gpio%d", i);
+ pin->pin_caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT |
+ GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL |
+ GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN;
+ pin->reg = MAX77620_REG_GPIO0 + i;
+ }
+
+ return (0);
+}
diff --git a/sys/arm64/nvidia/tegra210/max77620_regulators.c b/sys/arm64/nvidia/tegra210/max77620_regulators.c
new file mode 100644
index 000000000000..b70f96e2db4f
--- /dev/null
+++ b/sys/arm64/nvidia/tegra210/max77620_regulators.c
@@ -0,0 +1,888 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
+ *
+ * Copyright 2020 Michal Meloun <mmel@FreeBSD.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/gpio.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/malloc.h>
+#include <sys/rman.h>
+#include <sys/sx.h>
+
+#include <machine/bus.h>
+
+#include <dev/extres/regulator/regulator.h>
+#include <dev/gpio/gpiobusvar.h>
+
+#include <gnu/dts/include/dt-bindings/mfd/max77620.h>
+
+#include "max77620.h"
+
+MALLOC_DEFINE(M_MAX77620_REG, "MAX77620 regulator", "MAX77620 power regulator");
+
+#define DIV_ROUND_UP(n,d) howmany(n, d)
+
+enum max77620_reg_id {
+ MAX77620_REG_ID_SD0,
+ MAX77620_REG_ID_SD1,
+ MAX77620_REG_ID_SD2,
+ MAX77620_REG_ID_SD3,
+ MAX77620_REG_ID_LDO0,
+ MAX77620_REG_ID_LDO1,
+ MAX77620_REG_ID_LDO2,
+ MAX77620_REG_ID_LDO3,
+ MAX77620_REG_ID_LDO4,
+ MAX77620_REG_ID_LDO5,
+ MAX77620_REG_ID_LDO6,
+ MAX77620_REG_ID_LDO7,
+ MAX77620_REG_ID_LDO8,
+};
+
+/* Initial configuration. */
+struct max77620_regnode_init_def {
+ struct regnode_init_def reg_init_def;
+ int active_fps_src;
+ int active_fps_pu_slot;
+ int active_fps_pd_slot;
+ int suspend_fps_src;
+ int suspend_fps_pu_slot;
+ int suspend_fps_pd_slot;
+ int ramp_rate_setting;
+};
+
+/* Regulator HW definition. */
+struct reg_def {
+ intptr_t id; /* ID */
+ char *name; /* Regulator name */
+ char *supply_name; /* Source property name */
+ bool is_sd_reg; /* SD or LDO regulator? */
+ uint8_t volt_reg;
+ uint8_t volt_vsel_mask;
+ uint8_t cfg_reg;
+ uint8_t fps_reg;
+ uint8_t pwr_mode_reg;
+ uint8_t pwr_mode_mask;
+ uint8_t pwr_mode_shift;
+ struct regulator_range *ranges;
+ int nranges;
+};
+
+struct max77620_reg_sc {
+ struct regnode *regnode;
+ struct max77620_softc *base_sc;
+ struct reg_def *def;
+ phandle_t xref;
+
+ struct regnode_std_param *param;
+ /* Configured values */
+ int active_fps_src;
+ int active_fps_pu_slot;
+ int active_fps_pd_slot;
+ int suspend_fps_src;
+ int suspend_fps_pu_slot;
+ int suspend_fps_pd_slot;
+ int ramp_rate_setting;
+ int enable_usec;
+ uint8_t enable_pwr_mode;
+
+ /* Cached values */
+ uint8_t fps_src;
+ uint8_t pwr_mode;
+ int pwr_ramp_delay;
+};
+
+static struct regulator_range max77620_sd0_ranges[] = {
+ REG_RANGE_INIT(0, 64, 600000, 12500), /* 0.6V - 1.4V / 12.5mV */
+};
+
+static struct regulator_range max77620_sd1_ranges[] = {
+ REG_RANGE_INIT(0, 76, 600000, 12500), /* 0.6V - 1.55V / 12.5mV */
+};
+
+static struct regulator_range max77620_sdx_ranges[] = {
+ REG_RANGE_INIT(0, 255, 600000, 12500), /* 0.6V - 3.7875V / 12.5mV */
+};
+
+static struct regulator_range max77620_ldo0_1_ranges[] = {
+ REG_RANGE_INIT(0, 63, 800000, 25000), /* 0.8V - 2.375V / 25mV */
+};
+
+static struct regulator_range max77620_ldo4_ranges[] = {
+ REG_RANGE_INIT(0, 63, 800000, 12500), /* 0.8V - 1.5875V / 12.5mV */
+};
+
+static struct regulator_range max77620_ldox_ranges[] = {
+ REG_RANGE_INIT(0, 63, 800000, 50000), /* 0.8V - 3.95V / 50mV */
+};
+
+static struct reg_def max77620s_def[] = {
+ {
+ .id = MAX77620_REG_ID_SD0,
+ .name = "sd0",
+ .supply_name = "in-sd0",
+ .is_sd_reg = true,
+ .volt_reg = MAX77620_REG_SD0,
+ .volt_vsel_mask = MAX77620_SD0_VSEL_MASK,
+ .cfg_reg = MAX77620_REG_CFG_SD0,
+ .fps_reg = MAX77620_REG_FPS_SD0,
+ .pwr_mode_reg = MAX77620_REG_CFG_SD0,
+ .pwr_mode_mask = MAX77620_SD_POWER_MODE_MASK,
+ .pwr_mode_shift = MAX77620_SD_POWER_MODE_SHIFT,
+ .ranges = max77620_sd0_ranges,
+ .nranges = nitems(max77620_sd0_ranges),
+ },
+ {
+ .id = MAX77620_REG_ID_SD1,
+ .name = "sd1",
+ .supply_name = "in-sd1",
+ .is_sd_reg = true,
+ .volt_reg = MAX77620_REG_SD1,
+ .volt_vsel_mask = MAX77620_SD1_VSEL_MASK,
+ .cfg_reg = MAX77620_REG_CFG_SD1,
+ .fps_reg = MAX77620_REG_FPS_SD1,
+ .pwr_mode_reg = MAX77620_REG_CFG_SD1,
+ .pwr_mode_mask = MAX77620_SD_POWER_MODE_MASK,
+ .pwr_mode_shift = MAX77620_SD_POWER_MODE_SHIFT,
+ .ranges = max77620_sd1_ranges,
+ .nranges = nitems(max77620_sd1_ranges),
+ },
+ {
+ .id = MAX77620_REG_ID_SD2,
+ .name = "sd2",
+ .supply_name = "in-sd2",
+ .is_sd_reg = true,
+ .volt_reg = MAX77620_REG_SD2,
+ .volt_vsel_mask = MAX77620_SDX_VSEL_MASK,
+ .cfg_reg = MAX77620_REG_CFG_SD2,
+ .fps_reg = MAX77620_REG_FPS_SD2,
+ .pwr_mode_reg = MAX77620_REG_CFG_SD2,
+ .pwr_mode_mask = MAX77620_SD_POWER_MODE_MASK,
+ .pwr_mode_shift = MAX77620_SD_POWER_MODE_SHIFT,
+ .ranges = max77620_sdx_ranges,
+ .nranges = nitems(max77620_sdx_ranges),
+ },
+ {
+ .id = MAX77620_REG_ID_SD3,
+ .name = "sd3",
+ .supply_name = "in-sd3",
+ .is_sd_reg = true,
+ .volt_reg = MAX77620_REG_SD3,
+ .volt_vsel_mask = MAX77620_SDX_VSEL_MASK,
+ .cfg_reg = MAX77620_REG_CFG_SD3,
+ .fps_reg = MAX77620_REG_FPS_SD3,
+ .pwr_mode_reg = MAX77620_REG_CFG_SD3,
+ .pwr_mode_mask = MAX77620_SD_POWER_MODE_MASK,
+ .pwr_mode_shift = MAX77620_SD_POWER_MODE_SHIFT,
+ .ranges = max77620_sdx_ranges,
+ .nranges = nitems(max77620_sdx_ranges),
+ },
+ {
+ .id = MAX77620_REG_ID_LDO0,
+ .name = "ldo0",
+ .supply_name = "vin-ldo0-1",
+ .volt_reg = MAX77620_REG_CFG_LDO0,
+ .volt_vsel_mask = MAX77620_LDO_VSEL_MASK,
+ .is_sd_reg = false,
+ .cfg_reg = MAX77620_REG_CFG2_LDO0,
+ .fps_reg = MAX77620_REG_FPS_LDO0,
+ .pwr_mode_reg = MAX77620_REG_CFG_LDO0,
+ .pwr_mode_mask = MAX77620_LDO_POWER_MODE_MASK,
+ .pwr_mode_shift = MAX77620_LDO_POWER_MODE_SHIFT,
+ .ranges = max77620_ldo0_1_ranges,
+ .nranges = nitems(max77620_ldo0_1_ranges),
+ },
+ {
+ .id = MAX77620_REG_ID_LDO1,
+ .name = "ldo1",
+ .supply_name = "in-ldo0-1",
+ .is_sd_reg = false,
+ .volt_reg = MAX77620_REG_CFG_LDO1,
+ .volt_vsel_mask = MAX77620_LDO_VSEL_MASK,
+ .cfg_reg = MAX77620_REG_CFG2_LDO1,
+ .fps_reg = MAX77620_REG_FPS_LDO1,
+ .pwr_mode_reg = MAX77620_REG_CFG_LDO1,
+ .pwr_mode_mask = MAX77620_LDO_POWER_MODE_MASK,
+ .pwr_mode_shift = MAX77620_LDO_POWER_MODE_SHIFT,
+ .ranges = max77620_ldo0_1_ranges,
+ .nranges = nitems(max77620_ldo0_1_ranges),
+ },
+ {
+ .id = MAX77620_REG_ID_LDO2,
+ .name = "ldo2",
+ .supply_name = "in-ldo2",
+ .is_sd_reg = false,
+ .volt_reg = MAX77620_REG_CFG_LDO2,
+ .volt_vsel_mask = MAX77620_LDO_VSEL_MASK,
+ .cfg_reg = MAX77620_REG_CFG2_LDO2,
+ .fps_reg = MAX77620_REG_FPS_LDO2,
+ .pwr_mode_reg = MAX77620_REG_CFG_LDO2,
+ .pwr_mode_mask = MAX77620_LDO_POWER_MODE_MASK,
+ .pwr_mode_shift = MAX77620_LDO_POWER_MODE_SHIFT,
+ .ranges = max77620_ldox_ranges,
+ .nranges = nitems(max77620_ldox_ranges),
+ },
+ {
+ .id = MAX77620_REG_ID_LDO3,
+ .name = "ldo3",
+ .supply_name = "in-ldo3-5",
+ .is_sd_reg = false,
+ .volt_reg = MAX77620_REG_CFG_LDO3,
+ .volt_vsel_mask = MAX77620_LDO_VSEL_MASK,
+ .cfg_reg = MAX77620_REG_CFG2_LDO3,
+ .fps_reg = MAX77620_REG_FPS_LDO3,
+ .pwr_mode_reg = MAX77620_REG_CFG_LDO3,
+ .pwr_mode_mask = MAX77620_LDO_POWER_MODE_MASK,
+ .pwr_mode_shift = MAX77620_LDO_POWER_MODE_SHIFT,
+ .ranges = max77620_ldox_ranges,
+ .nranges = nitems(max77620_ldox_ranges),
+ },
+ {
+ .id = MAX77620_REG_ID_LDO4,
+ .name = "ldo4",
+ .supply_name = "in-ldo4-6",
+ .is_sd_reg = false,
+ .volt_reg = MAX77620_REG_CFG_LDO4,
+ .volt_vsel_mask = MAX77620_LDO_VSEL_MASK,
+ .cfg_reg = MAX77620_REG_CFG2_LDO4,
+ .fps_reg = MAX77620_REG_FPS_LDO4,
+ .pwr_mode_reg = MAX77620_REG_CFG_LDO4,
+ .pwr_mode_mask = MAX77620_LDO_POWER_MODE_MASK,
+ .pwr_mode_shift = MAX77620_LDO_POWER_MODE_SHIFT,
+ .ranges = max77620_ldo4_ranges,
+ .nranges = nitems(max77620_ldo4_ranges),
+ },
+ {
+ .id = MAX77620_REG_ID_LDO5,
+ .name = "ldo5",
+ .supply_name = "in-ldo3-5",
+ .is_sd_reg = false,
+ .volt_reg = MAX77620_REG_CFG_LDO5,
+ .volt_vsel_mask = MAX77620_LDO_VSEL_MASK,
+ .cfg_reg = MAX77620_REG_CFG2_LDO5,
+ .fps_reg = MAX77620_REG_FPS_LDO5,
+ .pwr_mode_reg = MAX77620_REG_CFG_LDO5,
+ .pwr_mode_mask = MAX77620_LDO_POWER_MODE_MASK,
+ .pwr_mode_shift = MAX77620_LDO_POWER_MODE_SHIFT,
+ .ranges = max77620_ldox_ranges,
+ .nranges = nitems(max77620_ldox_ranges),
+ },
+ {
+ .id = MAX77620_REG_ID_LDO6,
+ .name = "ldo6",
+ .supply_name = "in-ldo4-6",
+ .is_sd_reg = false,
+ .volt_reg = MAX77620_REG_CFG_LDO6,
+ .volt_vsel_mask = MAX77620_LDO_VSEL_MASK,
+ .cfg_reg = MAX77620_REG_CFG2_LDO6,
+ .fps_reg = MAX77620_REG_FPS_LDO6,
+ .pwr_mode_reg = MAX77620_REG_CFG_LDO6,
+ .pwr_mode_mask = MAX77620_LDO_POWER_MODE_MASK,
+ .pwr_mode_shift = MAX77620_LDO_POWER_MODE_SHIFT,
+ .ranges = max77620_ldox_ranges,
+ .nranges = nitems(max77620_ldox_ranges),
+ },
+ {
+ .id = MAX77620_REG_ID_LDO7,
+ .name = "ldo7",
+ .supply_name = "in-ldo7-8",
+ .is_sd_reg = false,
+ .volt_reg = MAX77620_REG_CFG_LDO7,
+ .volt_vsel_mask = MAX77620_LDO_VSEL_MASK,
+ .cfg_reg = MAX77620_REG_CFG2_LDO7,
+ .fps_reg = MAX77620_REG_FPS_LDO7,
+ .pwr_mode_reg = MAX77620_REG_CFG_LDO7,
+ .pwr_mode_mask = MAX77620_LDO_POWER_MODE_MASK,
+ .pwr_mode_shift = MAX77620_LDO_POWER_MODE_SHIFT,
+ .ranges = max77620_ldox_ranges,
+ .nranges = nitems(max77620_ldox_ranges),
+ },
+ {
+ .id = MAX77620_REG_ID_LDO8,
+ .name = "ldo8",
+ .supply_name = "in-ldo7-8",
+ .is_sd_reg = false,
+ .volt_reg = MAX77620_REG_CFG_LDO8,
+ .volt_vsel_mask = MAX77620_LDO_VSEL_MASK,
+ .cfg_reg = MAX77620_REG_CFG2_LDO8,
+ .fps_reg = MAX77620_REG_FPS_LDO8,
+ .pwr_mode_reg = MAX77620_REG_CFG_LDO8,
+ .pwr_mode_mask = MAX77620_LDO_POWER_MODE_MASK,
+ .pwr_mode_shift = MAX77620_LDO_POWER_MODE_SHIFT,
+ .ranges = max77620_ldox_ranges,
+ .nranges = nitems(max77620_ldox_ranges),
+ },
+};
+
+
+static int max77620_regnode_init(struct regnode *regnode);
+static int max77620_regnode_enable(struct regnode *regnode, bool enable,
+ int *udelay);
+static int max77620_regnode_set_volt(struct regnode *regnode, int min_uvolt,
+ int max_uvolt, int *udelay);
+static int max77620_regnode_get_volt(struct regnode *regnode, int *uvolt);
+static regnode_method_t max77620_regnode_methods[] = {
+ /* Regulator interface */
+ REGNODEMETHOD(regnode_init, max77620_regnode_init),
+ REGNODEMETHOD(regnode_enable, max77620_regnode_enable),
+ REGNODEMETHOD(regnode_set_voltage, max77620_regnode_set_volt),
+ REGNODEMETHOD(regnode_get_voltage, max77620_regnode_get_volt),
+ REGNODEMETHOD_END
+};
+DEFINE_CLASS_1(max77620_regnode, max77620_regnode_class, max77620_regnode_methods,
+ sizeof(struct max77620_reg_sc), regnode_class);
+
+static int
+max77620_get_sel(struct max77620_reg_sc *sc, uint8_t *sel)
+{
+ int rv;
+
+ rv = RD1(sc->base_sc, sc->def->volt_reg, sel);
+ if (rv != 0) {
+ printf("%s: cannot read volatge selector: %d\n",
+ regnode_get_name(sc->regnode), rv);
+ return (rv);
+ }
+ *sel &= sc->def->volt_vsel_mask;
+ *sel >>= ffs(sc->def->volt_vsel_mask) - 1;
+ return (0);
+}
+
+static int
+max77620_set_sel(struct max77620_reg_sc *sc, uint8_t sel)
+{
+ int rv;
+
+ sel <<= ffs(sc->def->volt_vsel_mask) - 1;
+ sel &= sc->def->volt_vsel_mask;
+
+ rv = RM1(sc->base_sc, sc->def->volt_reg,
+ sc->def->volt_vsel_mask, sel);
+ if (rv != 0) {
+ printf("%s: cannot set volatge selector: %d\n",
+ regnode_get_name(sc->regnode), rv);
+ return (rv);
+ }
+ return (rv);
+}
+
+static int
+max77620_get_fps_src(struct max77620_reg_sc *sc, uint8_t *fps_src)
+{
+ uint8_t val;
+ int rv;
+
+ rv = RD1(sc->base_sc, sc->def->fps_reg, &val);
+ if (rv != 0)
+ return (rv);
+
+ *fps_src = (val & MAX77620_FPS_SRC_MASK) >> MAX77620_FPS_SRC_SHIFT;
+ return (0);
+}
+
+static int
+max77620_set_fps_src(struct max77620_reg_sc *sc, uint8_t fps_src)
+{
+ int rv;
+
+ rv = RM1(sc->base_sc, sc->def->fps_reg, MAX77620_FPS_SRC_MASK,
+ fps_src << MAX77620_FPS_SRC_SHIFT);
+ if (rv != 0)
+ return (rv);
+ sc->fps_src = fps_src;
+ return (0);
+}
+
+static int
+max77620_set_fps_slots(struct max77620_reg_sc *sc, bool suspend)
+{
+ uint8_t mask, val;
+ int pu_slot, pd_slot, rv;
+
+ if (suspend) {
+ pu_slot = sc->suspend_fps_pu_slot;
+ pd_slot = sc->suspend_fps_pd_slot;
+ } else {
+ pu_slot = sc->active_fps_pu_slot;
+ pd_slot = sc->active_fps_pd_slot;
+ }
+
+ mask = 0;
+ val = 0;
+ if (pu_slot >= 0) {
+ mask |= MAX77620_FPS_PU_PERIOD_MASK;
+ val |= ((uint8_t)pu_slot << MAX77620_FPS_PU_PERIOD_SHIFT) &
+ MAX77620_FPS_PU_PERIOD_MASK;
+ }
+ if (pd_slot >= 0) {
+ mask |= MAX77620_FPS_PD_PERIOD_MASK;
+ val |= ((uint8_t)pd_slot << MAX77620_FPS_PD_PERIOD_SHIFT) &
+ MAX77620_FPS_PD_PERIOD_MASK;
+ }
+
+ rv = RM1(sc->base_sc, sc->def->fps_reg, mask, val);
+ if (rv != 0)
+ return (rv);
+ return (0);
+}
+
+static int
+max77620_get_pwr_mode(struct max77620_reg_sc *sc, uint8_t *pwr_mode)
+{
+ uint8_t val;
+ int rv;
+
+ rv = RD1(sc->base_sc, sc->def->pwr_mode_reg, &val);
+ if (rv != 0)
+ return (rv);
+
+ *pwr_mode = (val & sc->def->pwr_mode_mask) >> sc->def->pwr_mode_shift;
+ return (0);
+}
+
+static int
+max77620_set_pwr_mode(struct max77620_reg_sc *sc, uint8_t pwr_mode)
+{
+ int rv;
+
+ rv = RM1(sc->base_sc, sc->def->pwr_mode_reg, sc->def->pwr_mode_shift,
+ pwr_mode << sc->def->pwr_mode_shift);
+ if (rv != 0)
+ return (rv);
+ sc->pwr_mode = pwr_mode;
+ return (0);
+}
+
+static int
+max77620_get_pwr_ramp_delay(struct max77620_reg_sc *sc, int *rate)
+{
+ uint8_t val;
+ int rv;
+
+ rv = RD1(sc->base_sc, sc->def->cfg_reg, &val);
+ if (rv != 0)
+ return (rv);
+
+ if (sc->def->is_sd_reg) {
+ val = (val & MAX77620_SD_SR_MASK) >> MAX77620_SD_SR_SHIFT;
+ if (val == 0)
+ *rate = 13750;
+ else if (val == 1)
+ *rate = 27500;
+ else if (val == 2)
+ *rate = 55000;
+ else
+ *rate = 100000;
+ } else {
+ val = (val & MAX77620_LDO_SLEW_RATE_MASK) >>
+ MAX77620_LDO_SLEW_RATE_SHIFT;
+ if (val == 0)
+ *rate = 100000;
+ else
+ *rate = 5000;
+ }
+ sc->pwr_ramp_delay = *rate;
+ return (0);
+}
+
+static int
+max77620_set_pwr_ramp_delay(struct max77620_reg_sc *sc, int rate)
+{
+ uint8_t val, mask;
+ int rv;
+
+ if (sc->def->is_sd_reg) {
+ if (rate <= 13750)
+ val = 0;
+ else if (rate <= 27500)
+ val = 1;
+ else if (rate <= 55000)
+ val = 2;
+ else
+ val = 3;
+ val <<= MAX77620_SD_SR_SHIFT;
+ mask = MAX77620_SD_SR_MASK;
+ } else {
+ if (rate <= 5000)
+ val = 1;
+ else
+ val = 0;
+ val <<= MAX77620_LDO_SLEW_RATE_SHIFT;
+ mask = MAX77620_LDO_SLEW_RATE_MASK;
+ }
+ rv = RM1(sc->base_sc, sc->def->cfg_reg, mask, val);
+ if (rv != 0)
+ return (rv);
+ return (0);
+}
+
+static int
+max77620_regnode_init(struct regnode *regnode)
+{
+ struct max77620_reg_sc *sc;
+ uint8_t val;
+ int intval, rv;
+
+ sc = regnode_get_softc(regnode);
+ sc->enable_usec = 500;
+ sc->enable_pwr_mode = MAX77620_POWER_MODE_NORMAL;
+#if 0
+{
+uint8_t val1, val2, val3;
+RD1(sc->base_sc, sc->def->volt_reg, &val1);
+RD1(sc->base_sc, sc->def->cfg_reg, &val2);
+RD1(sc->base_sc, sc->def->fps_reg, &val3);
+printf("%s: Volt: 0x%02X, CFG: 0x%02X, FPS: 0x%02X\n", regnode_get_name(sc->regnode), val1, val2, val3);
+}
+#endif
+ /* Get current power mode */
+ rv = max77620_get_pwr_mode(sc, &val);
+ if (rv != 0) {
+ printf("%s: cannot read current power mode: %d\n",
+ regnode_get_name(sc->regnode), rv);
+ return (rv);
+ }
+ sc->pwr_mode = val;
+
+ /* Get current power ramp delay */
+ rv = max77620_get_pwr_ramp_delay(sc, &intval);
+ if (rv != 0) {
+ printf("%s: cannot read current power mode: %d\n",
+ regnode_get_name(sc->regnode), rv);
+ return (rv);
+ }
+ sc->pwr_ramp_delay = intval;
+
+ /* Get FPS source if is not specified. */
+ if (sc->active_fps_src == -1) {
+ rv = max77620_get_fps_src(sc, &val);
+ if (rv != 0) {
+ printf("%s: cannot read current FPS source: %d\n",
+ regnode_get_name(sc->regnode), rv);
+ return (rv);
+ }
+ sc->active_fps_src = val;
+ }
+
+ /* Configure power mode non-FPS controlled regulators. */
+ if (sc->active_fps_src != MAX77620_FPS_SRC_NONE ||
+ (sc->pwr_mode != MAX77620_POWER_MODE_DISABLE &&
+ sc->pwr_mode != sc->enable_pwr_mode)) {
+ rv = max77620_set_pwr_mode(sc, (uint8_t)sc->enable_pwr_mode);
+ if (rv != 0) {
+ printf("%s: cannot set power mode: %d\n",
+ regnode_get_name(sc->regnode), rv);
+ return (rv);
+ }
+ }
+
+ /* Set FPS source. */
+ rv = max77620_set_fps_src(sc, sc->active_fps_src);
+ if (rv != 0) {
+ printf("%s: cannot setup FPS source: %d\n",
+ regnode_get_name(sc->regnode), rv);
+ return (rv);
+ }
+ /* Set FPS slots. */
+ rv = max77620_set_fps_slots(sc, false);
+ if (rv != 0) {
+ printf("%s: cannot setup power slots: %d\n",
+ regnode_get_name(sc->regnode), rv);
+ return (rv);
+ }
+ /* Setup power ramp . */
+ if (sc->ramp_rate_setting != -1) {
+ rv = max77620_set_pwr_ramp_delay(sc, sc->pwr_ramp_delay);
+ if (rv != 0) {
+ printf("%s: cannot set power ramp delay: %d\n",
+ regnode_get_name(sc->regnode), rv);
+ return (rv);
+ }
+ }
+
+ return (0);
+}
+
+static void
+max77620_fdt_parse(struct max77620_softc *sc, phandle_t node, struct reg_def *def,
+struct max77620_regnode_init_def *init_def)
+{
+ int rv;
+ phandle_t parent, supply_node;
+ char prop_name[64]; /* Maximum OFW property name length. */
+
+ rv = regulator_parse_ofw_stdparam(sc->dev, node,
+ &init_def->reg_init_def);
+
+ rv = OF_getencprop(node, "maxim,active-fps-source",
+ &init_def->active_fps_src, sizeof(init_def->active_fps_src));
+ if (rv <= 0)
+ init_def->active_fps_src = MAX77620_FPS_SRC_DEF;
+
+ rv = OF_getencprop(node, "maxim,active-fps-power-up-slot",
+ &init_def->active_fps_pu_slot, sizeof(init_def->active_fps_pu_slot));
+ if (rv <= 0)
+ init_def->active_fps_pu_slot = -1;
+
+ rv = OF_getencprop(node, "maxim,active-fps-power-down-slot",
+ &init_def->active_fps_pd_slot, sizeof(init_def->active_fps_pd_slot));
+ if (rv <= 0)
+ init_def->active_fps_pd_slot = -1;
+
+ rv = OF_getencprop(node, "maxim,suspend-fps-source",
+ &init_def->suspend_fps_src, sizeof(init_def->suspend_fps_src));
+ if (rv <= 0)
+ init_def->suspend_fps_src = -1;
+
+ rv = OF_getencprop(node, "maxim,suspend-fps-power-up-slot",
+ &init_def->suspend_fps_pu_slot, sizeof(init_def->suspend_fps_pu_slot));
+ if (rv <= 0)
+ init_def->suspend_fps_pu_slot = -1;
+
+ rv = OF_getencprop(node, "maxim,suspend-fps-power-down-slot",
+ &init_def->suspend_fps_pd_slot, sizeof(init_def->suspend_fps_pd_slot));
+ if (rv <= 0)
+ init_def->suspend_fps_pd_slot = -1;
+
+ rv = OF_getencprop(node, "maxim,ramp-rate-setting",
+ &init_def->ramp_rate_setting, sizeof(init_def->ramp_rate_setting));
+ if (rv <= 0)
+ init_def->ramp_rate_setting = -1;
+
+ /* Get parent supply. */
+ if (def->supply_name == NULL)
+ return;
+
+ parent = OF_parent(node);
+ snprintf(prop_name, sizeof(prop_name), "%s-supply",
+ def->supply_name);
+ rv = OF_getencprop(parent, prop_name, &supply_node,
+ sizeof(supply_node));
+ if (rv <= 0)
+ return;
+ supply_node = OF_node_from_xref(supply_node);
+ rv = OF_getprop_alloc(supply_node, "regulator-name",
+ (void **)&init_def->reg_init_def.parent_name);
+ if (rv <= 0)
+ init_def->reg_init_def.parent_name = NULL;
+}
+
+static struct max77620_reg_sc *
+max77620_attach(struct max77620_softc *sc, phandle_t node, struct reg_def *def)
+{
+ struct max77620_reg_sc *reg_sc;
+ struct max77620_regnode_init_def init_def;
+ struct regnode *regnode;
+
+ bzero(&init_def, sizeof(init_def));
+
+ max77620_fdt_parse(sc, node, def, &init_def);
+ init_def.reg_init_def.id = def->id;
+ init_def.reg_init_def.ofw_node = node;
+ regnode = regnode_create(sc->dev, &max77620_regnode_class,
+ &init_def.reg_init_def);
+ if (regnode == NULL) {
+ device_printf(sc->dev, "Cannot create regulator.\n");
+ return (NULL);
+ }
+ reg_sc = regnode_get_softc(regnode);
+
+ /* Init regulator softc. */
+ reg_sc->regnode = regnode;
+ reg_sc->base_sc = sc;
+ reg_sc->def = def;
+ reg_sc->xref = OF_xref_from_node(node);
+ reg_sc->param = regnode_get_stdparam(regnode);
+ reg_sc->active_fps_src = init_def.active_fps_src;
+ reg_sc->active_fps_pu_slot = init_def.active_fps_pu_slot;
+ reg_sc->active_fps_pd_slot = init_def.active_fps_pd_slot;
+ reg_sc->suspend_fps_src = init_def.suspend_fps_src;
+ reg_sc->suspend_fps_pu_slot = init_def.suspend_fps_pu_slot;
+ reg_sc->suspend_fps_pd_slot = init_def.suspend_fps_pd_slot;
+ reg_sc->ramp_rate_setting = init_def.ramp_rate_setting;
+
+ regnode_register(regnode);
+ if (bootverbose) {
+ int volt, rv;
+ regnode_topo_slock();
+ rv = regnode_get_voltage(regnode, &volt);
+ if (rv == ENODEV) {
+ device_printf(sc->dev,
+ " Regulator %s: parent doesn't exist yet.\n",
+ regnode_get_name(regnode));
+ } else if (rv != 0) {
+ device_printf(sc->dev,
+ " Regulator %s: voltage: INVALID!!!\n",
+ regnode_get_name(regnode));
+ } else {
+ device_printf(sc->dev,
+ " Regulator %s: voltage: %d uV\n",
+ regnode_get_name(regnode), volt);
+ device_printf(sc->dev,
+ " FPS source: %d, mode: %d, ramp delay: %d\n",
+ reg_sc->fps_src, reg_sc->pwr_mode,
+ reg_sc->pwr_ramp_delay);
+ }
+ regnode_topo_unlock();
+ }
+
+ return (reg_sc);
+}
+
+int
+max77620_regulator_attach(struct max77620_softc *sc, phandle_t node)
+{
+ struct max77620_reg_sc *reg;
+ phandle_t child, rnode;
+ int i;
+
+ rnode = ofw_bus_find_child(node, "regulators");
+ if (rnode <= 0) {
+ device_printf(sc->dev, " Cannot find regulators subnode\n");
+ return (ENXIO);
+ }
+
+ sc->nregs = nitems(max77620s_def);
+ sc->regs = malloc(sizeof(struct max77620_reg_sc *) * sc->nregs,
+ M_MAX77620_REG, M_WAITOK | M_ZERO);
+
+
+ /* Attach all known regulators if exist in DT. */
+ for (i = 0; i < sc->nregs; i++) {
+ child = ofw_bus_find_child(rnode, max77620s_def[i].name);
+ if (child == 0) {
+ if (bootverbose)
+ device_printf(sc->dev,
+ "Regulator %s missing in DT\n",
+ max77620s_def[i].name);
+ continue;
+ }
+ if (ofw_bus_node_status_okay(child) == 0)
+ continue;
+ reg = max77620_attach(sc, child, max77620s_def + i);
+ if (reg == NULL) {
+ device_printf(sc->dev, "Cannot attach regulator: %s\n",
+ max77620s_def[i].name);
+ return (ENXIO);
+ }
+ sc->regs[i] = reg;
+ }
+ return (0);
+}
+
+int
+max77620_regulator_map(device_t dev, phandle_t xref, int ncells,
+ pcell_t *cells, intptr_t *num)
+{
+ struct max77620_softc *sc;
+ int i;
+
+ sc = device_get_softc(dev);
+ for (i = 0; i < sc->nregs; i++) {
+ if (sc->regs[i] == NULL)
+ continue;
+ if (sc->regs[i]->xref == xref) {
+ *num = sc->regs[i]->def->id;
+ return (0);
+ }
+ }
+
+ return (ENXIO);
+}
+
+static int
+max77620_regnode_enable(struct regnode *regnode, bool val, int *udelay)
+{
+
+ struct max77620_reg_sc *sc;
+ uint8_t mode;
+ int rv;
+
+ sc = regnode_get_softc(regnode);
+
+ if (sc->active_fps_src != MAX77620_FPS_SRC_NONE) {
+ *udelay = 0;
+ return (0);
+ }
+
+ if (val)
+ mode = sc->enable_pwr_mode;
+ else
+ mode = MAX77620_POWER_MODE_DISABLE;
+
+ rv = max77620_set_pwr_mode(sc, mode);
+ if (rv != 0) {
+ printf("%s: cannot set power mode: %d\n",
+ regnode_get_name(sc->regnode), rv);
+ return (rv);
+ }
+
+ *udelay = sc->enable_usec;
+ return (0);
+}
+
+static int
+max77620_regnode_set_volt(struct regnode *regnode, int min_uvolt, int max_uvolt,
+ int *udelay)
+{
+ struct max77620_reg_sc *sc;
+ uint8_t sel;
+ int rv;
+
+ sc = regnode_get_softc(regnode);
+
+ *udelay = 0;
+ rv = regulator_range_volt_to_sel8(sc->def->ranges, sc->def->nranges,
+ min_uvolt, max_uvolt, &sel);
+ if (rv != 0)
+ return (rv);
+ rv = max77620_set_sel(sc, sel);
+ return (rv);
+}
+
+static int
+max77620_regnode_get_volt(struct regnode *regnode, int *uvolt)
+{
+
+ struct max77620_reg_sc *sc;
+ uint8_t sel;
+ int rv;
+
+ sc = regnode_get_softc(regnode);
+ rv = max77620_get_sel(sc, &sel);
+ if (rv != 0)
+ return (rv);
+
+ rv = regulator_range_sel8_to_volt(sc->def->ranges, sc->def->nranges,
+ sel, uvolt);
+ return (rv);
+ return(0);
+}
diff --git a/sys/arm64/nvidia/tegra210/max77620_rtc.c b/sys/arm64/nvidia/tegra210/max77620_rtc.c
new file mode 100644
index 000000000000..09da17ad7d8f
--- /dev/null
+++ b/sys/arm64/nvidia/tegra210/max77620_rtc.c
@@ -0,0 +1,413 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
+ *
+ * Copyright 2020 Michal Meloun <mmel@FreeBSD.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/clock.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/rman.h>
+#include <sys/sx.h>
+
+#include <dev/iicbus/iiconf.h>
+#include <dev/iicbus/iicbus.h>
+#include <dev/ofw/ofw_bus.h>
+
+#include "clock_if.h"
+#include "max77620.h"
+#define MAX77620_RTC_INT 0x00
+#define MAX77620_RTC_INTM 0x01
+#define MAX77620_RTC_CONTROLM 0x02
+#define MAX77620_RTC_CONTROL 0x03
+#define RTC_CONTROL_MODE_24 (1 << 1)
+#define RTC_CONTROL_BCD_EN (1 << 0)
+
+#define MAX77620_RTC_UPDATE0 0x04
+#define RTC_UPDATE0_RTC_RBUDR (1 << 4)
+#define RTC_UPDATE0_RTC_UDR (1 << 0)
+
+#define MAX77620_WTSR_SMPL_CNTL 0x06
+#define MAX77620_RTC_SEC 0x07
+#define MAX77620_RTC_MIN 0x08
+#define MAX77620_RTC_HOUR 0x09
+#define MAX77620_RTC_WEEKDAY 0x0A
+#define MAX77620_RTC_MONTH 0x0B
+#define MAX77620_RTC_YEAR 0x0C
+#define MAX77620_RTC_DATE 0x0D
+#define MAX77620_ALARM1_SEC 0x0E
+#define MAX77620_ALARM1_MIN 0x0F
+#define MAX77620_ALARM1_HOUR 0x10
+#define MAX77620_ALARM1_WEEKDAY 0x11
+#define MAX77620_ALARM1_MONTH 0x12
+#define MAX77620_ALARM1_YEAR 0x13
+#define MAX77620_ALARM1_DATE 0x14
+#define MAX77620_ALARM2_SEC 0x15
+#define MAX77620_ALARM2_MIN 0x16
+#define MAX77620_ALARM2_HOUR 0x17
+#define MAX77620_ALARM2_WEEKDAY 0x18
+#define MAX77620_ALARM2_MONTH 0x19
+#define MAX77620_ALARM2_YEAR 0x1A
+#define MAX77620_ALARM2_DATE 0x1B
+
+#define MAX77620_RTC_START_YEAR 2000
+#define MAX77620_RTC_I2C_ADDR 0x68
+
+#define LOCK(_sc) sx_xlock(&(_sc)->lock)
+#define UNLOCK(_sc) sx_xunlock(&(_sc)->lock)
+#define LOCK_INIT(_sc) sx_init(&(_sc)->lock, "max77620_rtc")
+#define LOCK_DESTROY(_sc) sx_destroy(&(_sc)->lock);
+
+struct max77620_rtc_softc {
+ device_t dev;
+ struct sx lock;
+ int bus_addr;
+};
+
+/*
+ * Raw register access function.
+ */
+static int
+max77620_rtc_read(struct max77620_rtc_softc *sc, uint8_t reg, uint8_t *val)
+{
+ uint8_t addr;
+ int rv;
+ struct iic_msg msgs[2] = {
+ {0, IIC_M_WR, 1, &addr},
+ {0, IIC_M_RD, 1, val},
+ };
+
+ msgs[0].slave = sc->bus_addr;
+ msgs[1].slave = sc->bus_addr;
+ addr = reg;
+
+ rv = iicbus_transfer(sc->dev, msgs, 2);
+ if (rv != 0) {
+ device_printf(sc->dev,
+ "Error when reading reg 0x%02X, rv: %d\n", reg, rv);
+ return (EIO);
+ }
+
+ return (0);
+}
+
+static int
+max77620_rtc_read_buf(struct max77620_rtc_softc *sc, uint8_t reg,
+ uint8_t *buf, size_t size)
+{
+ uint8_t addr;
+ int rv;
+ struct iic_msg msgs[2] = {
+ {0, IIC_M_WR, 1, &addr},
+ {0, IIC_M_RD, size, buf},
+ };
+
+ msgs[0].slave = sc->bus_addr;
+ msgs[1].slave = sc->bus_addr;
+ addr = reg;
+
+ rv = iicbus_transfer(sc->dev, msgs, 2);
+ if (rv != 0) {
+ device_printf(sc->dev,
+ "Error when reading reg 0x%02X, rv: %d\n", reg, rv);
+ return (EIO);
+ }
+
+ return (0);
+}
+
+static int
+max77620_rtc_write(struct max77620_rtc_softc *sc, uint8_t reg, uint8_t val)
+{
+ uint8_t data[2];
+ int rv;
+
+ struct iic_msg msgs[1] = {
+ {0, IIC_M_WR, 2, data},
+ };
+
+ msgs[0].slave = sc->bus_addr;
+ data[0] = reg;
+ data[1] = val;
+
+ rv = iicbus_transfer(sc->dev, msgs, 1);
+ if (rv != 0) {
+ device_printf(sc->dev,
+ "Error when writing reg 0x%02X, rv: %d\n", reg, rv);
+ return (EIO);
+ }
+ return (0);
+}
+
+static int
+max77620_rtc_write_buf(struct max77620_rtc_softc *sc, uint8_t reg, uint8_t *buf,
+ size_t size)
+{
+ uint8_t data[1];
+ int rv;
+ struct iic_msg msgs[2] = {
+ {0, IIC_M_WR, 1, data},
+ {0, IIC_M_WR | IIC_M_NOSTART, size, buf},
+ };
+
+ msgs[0].slave = sc->bus_addr;
+ msgs[1].slave = sc->bus_addr;
+ data[0] = reg;
+
+ rv = iicbus_transfer(sc->dev, msgs, 2);
+ if (rv != 0) {
+ device_printf(sc->dev,
+ "Error when writing reg 0x%02X, rv: %d\n", reg, rv);
+ return (EIO);
+ }
+ return (0);
+}
+
+static int
+max77620_rtc_modify(struct max77620_rtc_softc *sc, uint8_t reg, uint8_t clear,
+ uint8_t set)
+{
+ uint8_t val;
+ int rv;
+
+ rv = max77620_rtc_read(sc, reg, &val);
+ if (rv != 0)
+ return (rv);
+
+ val &= ~clear;
+ val |= set;
+
+ rv = max77620_rtc_write(sc, reg, val);
+ if (rv != 0)
+ return (rv);
+
+ return (0);
+}
+
+static int
+max77620_rtc_update(struct max77620_rtc_softc *sc, bool for_read)
+{
+ uint8_t reg;
+ int rv;
+
+ reg = for_read ? RTC_UPDATE0_RTC_RBUDR: RTC_UPDATE0_RTC_UDR;
+ rv = max77620_rtc_modify(sc, MAX77620_RTC_UPDATE0, reg, reg);
+ if (rv != 0)
+ return (rv);
+
+ DELAY(16000);
+ return (rv);
+}
+
+static int
+max77620_rtc_gettime(device_t dev, struct timespec *ts)
+{
+ struct max77620_rtc_softc *sc;
+ struct clocktime ct;
+ uint8_t buf[7];
+ int rv;
+
+ sc = device_get_softc(dev);
+
+ LOCK(sc);
+ rv = max77620_rtc_update(sc, true);
+ if (rv != 0) {
+ UNLOCK(sc);
+ device_printf(sc->dev, "Failed to strobe RTC data\n");
+ return (rv);
+ }
+
+ rv = max77620_rtc_read_buf(sc, MAX77620_RTC_SEC, buf, nitems(buf));
+ UNLOCK(sc);
+ if (rv != 0) {
+ device_printf(sc->dev, "Failed to read RTC data\n");
+ return (rv);
+ }
+ ct.nsec = 0;
+ ct.sec = bcd2bin(buf[0] & 0x7F);
+ ct.min = bcd2bin(buf[1] & 0x7F);
+ ct.hour = bcd2bin(buf[2] & 0x3F);
+ ct.dow = ffs(buf[3] & 07);
+ ct.mon = bcd2bin(buf[4] & 0x1F);
+ ct.year = bcd2bin(buf[5] & 0x7F) + MAX77620_RTC_START_YEAR;
+ ct.day = bcd2bin(buf[6] & 0x3F);
+
+ return (clock_ct_to_ts(&ct, ts));
+}
+
+static int
+max77620_rtc_settime(device_t dev, struct timespec *ts)
+{
+ struct max77620_rtc_softc *sc;
+ struct clocktime ct;
+ uint8_t buf[7];
+ int rv;
+
+ sc = device_get_softc(dev);
+ clock_ts_to_ct(ts, &ct);
+
+ if (ct.year < MAX77620_RTC_START_YEAR)
+ return (EINVAL);
+
+ buf[0] = bin2bcd(ct.sec);
+ buf[1] = bin2bcd(ct.min);
+ buf[2] = bin2bcd(ct.hour);
+ buf[3] = 1 << ct.dow;
+ buf[4] = bin2bcd(ct.mon);
+ buf[5] = bin2bcd(ct.year - MAX77620_RTC_START_YEAR);
+ buf[6] = bin2bcd(ct.day);
+
+ LOCK(sc);
+ rv = max77620_rtc_write_buf(sc, MAX77620_RTC_SEC, buf, nitems(buf));
+ if (rv != 0) {
+ UNLOCK(sc);
+ device_printf(sc->dev, "Failed to write RTC data\n");
+ return (rv);
+ }
+ rv = max77620_rtc_update(sc, false);
+ UNLOCK(sc);
+ if (rv != 0) {
+ device_printf(sc->dev, "Failed to update RTC data\n");
+ return (rv);
+ }
+
+ return (0);
+}
+
+static int
+max77620_rtc_probe(device_t dev)
+{
+ struct iicbus_ivar *dinfo;
+
+ dinfo = device_get_ivars(dev);
+ if (dinfo == NULL)
+ return (ENXIO);
+ if (dinfo->addr != MAX77620_RTC_I2C_ADDR << 1)
+ return (ENXIO);
+
+ device_set_desc(dev, "MAX77620 RTC");
+ return (BUS_PROBE_DEFAULT);
+}
+
+static int
+max77620_rtc_attach(device_t dev)
+{
+ struct max77620_rtc_softc *sc;
+ uint8_t reg;
+ int rv;
+
+ sc = device_get_softc(dev);
+ sc->dev = dev;
+ sc->bus_addr = iicbus_get_addr(dev);
+
+ LOCK_INIT(sc);
+
+ reg = RTC_CONTROL_MODE_24 | RTC_CONTROL_BCD_EN;
+ rv = max77620_rtc_modify(sc, MAX77620_RTC_CONTROLM, reg, reg);
+ if (rv != 0) {
+ device_printf(sc->dev, "Failed to configure RTC\n");
+ goto fail;
+ }
+
+ rv = max77620_rtc_modify(sc, MAX77620_RTC_CONTROL, reg, reg);
+ if (rv != 0) {
+ device_printf(sc->dev, "Failed to configure RTC\n");
+ goto fail;
+ }
+ rv = max77620_rtc_update(sc, false);
+ if (rv != 0) {
+ device_printf(sc->dev, "Failed to update RTC data\n");
+ return (rv);
+ }
+
+ clock_register(sc->dev, 1000000);
+
+ return (bus_generic_attach(dev));
+
+fail:
+ LOCK_DESTROY(sc);
+ return (rv);
+}
+
+/*
+ * The secondary address of MAX77620 (RTC function) is not in DTB,
+ * add it manualy
+ */
+static int
+max77620_rtc_detach(device_t dev)
+{
+ struct max77620_softc *sc;
+
+ sc = device_get_softc(dev);
+ LOCK_DESTROY(sc);
+
+ return (bus_generic_detach(dev));
+}
+
+int
+max77620_rtc_create(struct max77620_softc *sc, phandle_t node)
+{
+ device_t parent, child;
+ struct iicbus_ivar *dinfo;
+
+ parent = device_get_parent(sc->dev);
+ child = BUS_ADD_CHILD(parent, 0, NULL, -1);
+ if (child == 0) {
+ device_printf(sc->dev, "Cannot add MAX77620 RTC device.\n");
+ return (ENXIO);
+ }
+ dinfo = device_get_ivars(child);
+ if (dinfo == NULL) {
+ device_printf(sc->dev,
+ "Cannot set I2Caddress for MAX77620 RTC.\n");
+ return (ENXIO);
+ }
+ dinfo->addr = MAX77620_RTC_I2C_ADDR << 1;
+ return (0);
+}
+
+static device_method_t max77620_rtc_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, max77620_rtc_probe),
+ DEVMETHOD(device_attach, max77620_rtc_attach),
+ DEVMETHOD(device_detach, max77620_rtc_detach),
+
+ /* RTC interface */
+ DEVMETHOD(clock_gettime, max77620_rtc_gettime),
+ DEVMETHOD(clock_settime, max77620_rtc_settime),
+
+ DEVMETHOD_END
+};
+
+static devclass_t max77620_rtc_devclass;
+static DEFINE_CLASS_0(rtc, max77620_rtc_driver, max77620_rtc_methods,
+ sizeof(struct max77620_rtc_softc));
+EARLY_DRIVER_MODULE(max77620rtc_, iicbus, max77620_rtc_driver,
+ max77620_rtc_devclass, NULL, NULL, 74);
diff --git a/sys/arm64/nvidia/tegra210/tegra210_car.c b/sys/arm64/nvidia/tegra210/tegra210_car.c
new file mode 100644
index 000000000000..20249942a7cc
--- /dev/null
+++ b/sys/arm64/nvidia/tegra210/tegra210_car.c
@@ -0,0 +1,601 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
+ *
+ * Copyright 2020 Michal Meloun <mmel@FreeBSD.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/kobj.h>
+#include <sys/module.h>
+#include <sys/malloc.h>
+#include <sys/rman.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+
+#include <machine/bus.h>
+#include <machine/cpu.h>
+
+#include <dev/extres/clk/clk_div.h>
+#include <dev/extres/clk/clk_fixed.h>
+#include <dev/extres/clk/clk_gate.h>
+#include <dev/extres/clk/clk_mux.h>
+#include <dev/extres/hwreset/hwreset.h>
+#include <dev/ofw/openfirm.h>
+#include <dev/ofw/ofw_bus.h>
+#include <dev/ofw/ofw_bus_subr.h>
+
+#include <gnu/dts/include/dt-bindings/clock/tegra210-car.h>
+
+#include "clkdev_if.h"
+#include "hwreset_if.h"
+#include "tegra210_car.h"
+
+static struct ofw_compat_data compat_data[] = {
+ {"nvidia,tegra210-car", 1},
+ {NULL, 0},
+};
+
+#define PLIST(x) static const char *x[]
+
+/* Pure multiplexer. */
+#define MUX(_id, cname, plists, o, s, w) \
+{ \
+ .clkdef.id = _id, \
+ .clkdef.name = cname, \
+ .clkdef.parent_names = plists, \
+ .clkdef.parent_cnt = nitems(plists), \
+ .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
+ .offset = o, \
+ .shift = s, \
+ .width = w, \
+}
+
+/* Fractional divider (7.1). */
+#define DIV7_1(_id, cname, plist, o, s) \
+{ \
+ .clkdef.id = _id, \
+ .clkdef.name = cname, \
+ .clkdef.parent_names = (const char *[]){plist}, \
+ .clkdef.parent_cnt = 1, \
+ .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
+ .offset = o, \
+ .i_shift = (s) + 1, \
+ .i_width = 7, \
+ .f_shift = s, \
+ .f_width = 1, \
+}
+
+/* Integer divider. */
+#define DIV(_id, cname, plist, o, s, w, f) \
+{ \
+ .clkdef.id = _id, \
+ .clkdef.name = cname, \
+ .clkdef.parent_names = (const char *[]){plist}, \
+ .clkdef.parent_cnt = 1, \
+ .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
+ .offset = o, \
+ .i_shift = s, \
+ .i_width = w, \
+ .div_flags = f, \
+}
+
+/* Gate in PLL block. */
+#define GATE_PLL(_id, cname, plist, o, s) \
+{ \
+ .clkdef.id = _id, \
+ .clkdef.name = cname, \
+ .clkdef.parent_names = (const char *[]){plist}, \
+ .clkdef.parent_cnt = 1, \
+ .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
+ .offset = o, \
+ .shift = s, \
+ .mask = 3, \
+ .on_value = 3, \
+ .off_value = 0, \
+}
+
+/* Standard gate. */
+#define GATE(_id, cname, plist, o, s) \
+{ \
+ .clkdef.id = _id, \
+ .clkdef.name = cname, \
+ .clkdef.parent_names = (const char *[]){plist}, \
+ .clkdef.parent_cnt = 1, \
+ .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
+ .offset = o, \
+ .shift = s, \
+ .mask = 1, \
+ .on_value = 1, \
+ .off_value = 0, \
+}
+
+/* Inverted gate. */
+#define GATE_INV(_id, cname, plist, o, s) \
+{ \
+ .clkdef.id = _id, \
+ .clkdef.name = cname, \
+ .clkdef.parent_names = (const char *[]){plist}, \
+ .clkdef.parent_cnt = 1, \
+ .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
+ .offset = o, \
+ .shift = s, \
+ .mask = 1, \
+ .on_value = 0, \
+ .off_value = 1, \
+}
+
+/* Fixed rate clock. */
+#define FRATE(_id, cname, _freq) \
+{ \
+ .clkdef.id = _id, \
+ .clkdef.name = cname, \
+ .clkdef.parent_names = NULL, \
+ .clkdef.parent_cnt = 0, \
+ .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
+ .freq = _freq, \
+}
+
+/* Fixed rate multipier/divider. */
+#define FACT(_id, cname, pname, _mult, _div) \
+{ \
+ .clkdef.id = _id, \
+ .clkdef.name = cname, \
+ .clkdef.parent_names = (const char *[]){pname}, \
+ .clkdef.parent_cnt = 1, \
+ .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
+ .mult = _mult, \
+ .div = _div, \
+}
+
+static uint32_t osc_freqs[16] = {
+ [0] = 13000000,
+ [1] = 16800000,
+ [4] = 19200000,
+ [5] = 38400000,
+ [8] = 12000000,
+ [9] = 48000000,
+};
+
+
+/* Parent lists. */
+PLIST(mux_xusb_hs) = {"xusb_ss_div2", "pllU_60", "pc_xusb_ss" };
+PLIST(mux_xusb_ssp) = {"xusb_ss", "osc_div_clk"};
+
+
+/* Clocks ajusted online. */
+static struct clk_fixed_def fixed_osc =
+ FRATE(TEGRA210_CLK_CLK_M, "osc", 38400000);
+static struct clk_fixed_def fixed_clk_m =
+ FACT(0, "clk_m", "osc", 1, 1);
+static struct clk_fixed_def fixed_osc_div =
+ FACT(0, "osc_div_clk", "osc", 1, 1);
+
+static struct clk_fixed_def tegra210_fixed_clks[] = {
+ /* Core clocks. */
+ FRATE(0, "bogus", 1),
+ FRATE(0, "clk_s", 32768),
+
+ /* Audio clocks. */
+ FRATE(0, "vimclk_sync", 1),
+ FRATE(0, "i2s1_sync", 1),
+ FRATE(0, "i2s2_sync", 1),
+ FRATE(0, "i2s3_sync", 1),
+ FRATE(0, "i2s4_sync", 1),
+ FRATE(0, "i2s5_sync", 1),
+ FRATE(0, "spdif_in_sync", 1),
+
+ /* XUSB */
+ FACT(TEGRA210_CLK_XUSB_SS_DIV2, "xusb_ss_div2", "xusb_ss", 1, 2),
+
+ /* SOR */
+ FACT(0, "sor_safe_div", "pllP_out0", 1, 17),
+ FACT(0, "dpaux_div", "sor_safe", 1, 17),
+ FACT(0, "dpaux1_div", "sor_safe", 1, 17),
+
+ /* Not Yet Implemented */
+ FRATE(0, "audio", 10000000),
+ FRATE(0, "audio0", 10000000),
+ FRATE(0, "audio1", 10000000),
+ FRATE(0, "audio2", 10000000),
+ FRATE(0, "audio3", 10000000),
+ FRATE(0, "audio4", 10000000),
+ FRATE(0, "ext_vimclk", 10000000),
+ FRATE(0, "audiod1", 10000000),
+ FRATE(0, "audiod2", 10000000),
+ FRATE(0, "audiod3", 10000000),
+ FRATE(0, "dfllCPU_out", 10000000),
+
+};
+
+
+static struct clk_mux_def tegra210_mux_clks[] = {
+ /* USB. */
+ MUX(TEGRA210_CLK_XUSB_HS_SRC, "xusb_hs", mux_xusb_hs, CLK_SOURCE_XUSB_SS, 25, 2),
+ MUX(0, "xusb_ssp", mux_xusb_ssp, CLK_SOURCE_XUSB_SS, 24, 1),
+
+};
+
+
+static struct clk_gate_def tegra210_gate_clks[] = {
+ /* Base peripheral clocks. */
+ GATE_INV(TEGRA210_CLK_HCLK, "hclk", "hclk_div", CLK_SYSTEM_RATE, 7),
+ GATE_INV(TEGRA210_CLK_PCLK, "pclk", "pclk_div", CLK_SYSTEM_RATE, 3),
+ GATE(TEGRA210_CLK_CML0, "cml0", "pllE_out0", PLLE_AUX, 0),
+ GATE(TEGRA210_CLK_CML1, "cml1", "pllE_out0", PLLE_AUX, 1),
+ GATE(0, "pllD_dsi_csi", "pllD_out0", PLLD_MISC, 21),
+ GATE(0, "pllP_hsio", "pllP_out0", PLLP_MISC1, 29),
+ GATE(0, "pllP_xusb", "pllP_hsio", PLLP_MISC1, 28),
+};
+
+static struct clk_div_def tegra210_div_clks[] = {
+ /* Base peripheral clocks. */
+ DIV(0, "hclk_div", "sclk", CLK_SYSTEM_RATE, 4, 2, 0),
+ DIV(0, "pclk_div", "hclk", CLK_SYSTEM_RATE, 0, 2, 0),
+};
+
+/* Initial setup table. */
+static struct tegra210_init_item clk_init_table[] = {
+ /* clock, partent, frequency, enable */
+ {"uarta", "pllP_out0", 408000000, 0},
+ {"uartb", "pllP_out0", 408000000, 0},
+ {"uartc", "pllP_out0", 408000000, 0},
+ {"uartd", "pllP_out0", 408000000, 0},
+ {"pllA", NULL, 564480000, 1},
+ {"pllA_out0", NULL, 11289600, 1},
+ {"extperiph1", "pllA_out0", 0, 1},
+ {"i2s1", "pllA_out0", 11289600, 0},
+ {"i2s2", "pllA_out0", 11289600, 0},
+ {"i2s3", "pllA_out0", 11289600, 0},
+ {"i2s4", "pllA_out0", 11289600, 0},
+ {"i2s5", "pllA_out0", 11289600, 0},
+ {"host1x", "pllP_out0", 136000000, 1},
+ {"sclk", "pllP_out2", 102000000, 1},
+ {"dvfs_soc", "pllP_out0", 51000000, 1},
+ {"dvfs_ref", "pllP_out0", 51000000, 1},
+ {"spi4", "pllP_out0", 12000000, 1},
+ {"pllREFE", NULL, 672000000, 0},
+
+ {"xusb", NULL, 0, 1},
+ {"xusb_ss", "pllU_480", 120000000, 0},
+ {"pc_xusb_fs", "pllU_48", 48000000, 0},
+ {"xusb_hs", "pc_xusb_ss", 120000000, 0},
+ {"xusb_ssp", "xusb_ss", 120000000, 0},
+ {"pc_xusb_falcon", "pllP_xusb", 204000000, 0},
+ {"pc_xusb_core_host", "pllP_xusb", 102000000, 0},
+ {"pc_xusb_core_dev", "pllP_xusb", 102000000, 0},
+
+ {"sata", "pllP_out0", 104000000, 0},
+ {"sata_oob", "pllP_out0", 204000000, 0},
+ {"emc", NULL, 0, 1},
+ {"mselect", NULL, 0, 1},
+ {"csite", NULL, 0, 1},
+
+ {"dbgapb", NULL, 0, 1 },
+ {"tsensor", "clk_m", 400000, 0},
+ {"i2c1", "pllP_out0", 0, 0},
+ {"i2c2", "pllP_out0", 0, 0},
+ {"i2c3", "pllP_out0", 0, 0},
+ {"i2c4", "pllP_out0", 0, 0},
+ {"i2c5", "pllP_out0", 0, 0},
+ {"i2c6", "pllP_out0", 0, 0},
+
+ {"pllDP_out0", NULL, 270000000, 0},
+ {"soc_therm", "pllP_out0", 51000000, 0},
+ {"cclk_g", NULL, 0, 1},
+ {"pllU_out1", NULL, 48000000, 1},
+ {"pllU_out2", NULL, 60000000, 1},
+ {"pllC4", NULL, 1000000000, 1},
+ {"pllC4_out0", NULL, 1000000000, 1},
+};
+
+static void
+init_divs(struct tegra210_car_softc *sc, struct clk_div_def *clks, int nclks)
+{
+ int i, rv;
+
+ for (i = 0; i < nclks; i++) {
+ rv = clknode_div_register(sc->clkdom, clks + i);
+ if (rv != 0)
+ panic("clk_div_register failed");
+ }
+}
+
+static void
+init_gates(struct tegra210_car_softc *sc, struct clk_gate_def *clks, int nclks)
+{
+ int i, rv;
+
+
+ for (i = 0; i < nclks; i++) {
+ rv = clknode_gate_register(sc->clkdom, clks + i);
+ if (rv != 0)
+ panic("clk_gate_register failed");
+ }
+}
+
+static void
+init_muxes(struct tegra210_car_softc *sc, struct clk_mux_def *clks, int nclks)
+{
+ int i, rv;
+
+
+ for (i = 0; i < nclks; i++) {
+ rv = clknode_mux_register(sc->clkdom, clks + i);
+ if (rv != 0)
+ panic("clk_mux_register failed");
+ }
+}
+
+static void
+init_fixeds(struct tegra210_car_softc *sc, struct clk_fixed_def *clks,
+ int nclks)
+{
+ int i, rv;
+ uint32_t val;
+ int osc_idx;
+
+ CLKDEV_READ_4(sc->dev, OSC_CTRL, &val);
+ osc_idx = OSC_CTRL_OSC_FREQ_GET(val);
+ fixed_osc.freq = osc_freqs[osc_idx];
+ if (fixed_osc.freq == 0)
+ panic("Undefined input frequency");
+ rv = clknode_fixed_register(sc->clkdom, &fixed_osc);
+ if (rv != 0)
+ panic("clk_fixed_register failed");
+
+ fixed_osc_div.div = 1 << OSC_CTRL_PLL_REF_DIV_GET(val);
+ rv = clknode_fixed_register(sc->clkdom, &fixed_osc_div);
+ if (rv != 0)
+ panic("clk_fixed_register failed");
+
+ CLKDEV_READ_4(sc->dev, SPARE_REG0, &val);
+ fixed_clk_m.div = SPARE_REG0_MDIV_GET(val) + 1;
+ rv = clknode_fixed_register(sc->clkdom, &fixed_clk_m);
+ if (rv != 0)
+ panic("clk_fixed_register failed");
+
+ for (i = 0; i < nclks; i++) {
+ rv = clknode_fixed_register(sc->clkdom, clks + i);
+ if (rv != 0)
+ panic("clk_fixed_register failed");
+ }
+}
+
+static void
+postinit_clock(struct tegra210_car_softc *sc)
+{
+ int i;
+ struct tegra210_init_item *tbl;
+ struct clknode *clknode;
+ int rv;
+
+ for (i = 0; i < nitems(clk_init_table); i++) {
+ tbl = &clk_init_table[i];
+
+ clknode = clknode_find_by_name(tbl->name);
+ if (clknode == NULL) {
+ device_printf(sc->dev, "Cannot find clock %s\n",
+ tbl->name);
+ continue;
+ }
+ if (tbl->parent != NULL) {
+ rv = clknode_set_parent_by_name(clknode, tbl->parent);
+ if (rv != 0) {
+ device_printf(sc->dev,
+ "Cannot set parent for %s (to %s): %d\n",
+ tbl->name, tbl->parent, rv);
+ continue;
+ }
+ }
+ if (tbl->frequency != 0) {
+ rv = clknode_set_freq(clknode, tbl->frequency, 0 , 9999);
+ if (rv != 0) {
+ device_printf(sc->dev,
+ "Cannot set frequency for %s: %d\n",
+ tbl->name, rv);
+ continue;
+ }
+ }
+ if (tbl->enable!= 0) {
+ rv = clknode_enable(clknode);
+ if (rv != 0) {
+ device_printf(sc->dev,
+ "Cannot enable %s: %d\n", tbl->name, rv);
+ continue;
+ }
+ }
+ }
+}
+
+static void
+register_clocks(device_t dev)
+{
+ struct tegra210_car_softc *sc;
+
+ sc = device_get_softc(dev);
+ sc->clkdom = clkdom_create(dev);
+ if (sc->clkdom == NULL)
+ panic("clkdom == NULL");
+
+ init_fixeds(sc, tegra210_fixed_clks, nitems(tegra210_fixed_clks));
+ tegra210_init_plls(sc);
+ init_muxes(sc, tegra210_mux_clks, nitems(tegra210_mux_clks));
+ init_divs(sc, tegra210_div_clks, nitems(tegra210_div_clks));
+ init_gates(sc, tegra210_gate_clks, nitems(tegra210_gate_clks));
+ tegra210_periph_clock(sc);
+ tegra210_super_mux_clock(sc);
+ clkdom_finit(sc->clkdom);
+ clkdom_xlock(sc->clkdom);
+ postinit_clock(sc);
+ clkdom_unlock(sc->clkdom);
+ if (bootverbose)
+ clkdom_dump(sc->clkdom);
+}
+
+static int
+tegra210_car_clkdev_read_4(device_t dev, bus_addr_t addr, uint32_t *val)
+{
+ struct tegra210_car_softc *sc;
+
+ sc = device_get_softc(dev);
+ *val = bus_read_4(sc->mem_res, addr);
+ return (0);
+}
+
+static int
+tegra210_car_clkdev_write_4(device_t dev, bus_addr_t addr, uint32_t val)
+{
+ struct tegra210_car_softc *sc;
+
+ sc = device_get_softc(dev);
+ bus_write_4(sc->mem_res, addr, val);
+ return (0);
+}
+
+static int
+tegra210_car_clkdev_modify_4(device_t dev, bus_addr_t addr, uint32_t clear_mask,
+ uint32_t set_mask)
+{
+ struct tegra210_car_softc *sc;
+ uint32_t reg;
+
+ sc = device_get_softc(dev);
+ reg = bus_read_4(sc->mem_res, addr);
+ reg &= ~clear_mask;
+ reg |= set_mask;
+ bus_write_4(sc->mem_res, addr, reg);
+ return (0);
+}
+
+static void
+tegra210_car_clkdev_device_lock(device_t dev)
+{
+ struct tegra210_car_softc *sc;
+
+ sc = device_get_softc(dev);
+ mtx_lock(&sc->mtx);
+}
+
+static void
+tegra210_car_clkdev_device_unlock(device_t dev)
+{
+ struct tegra210_car_softc *sc;
+
+ sc = device_get_softc(dev);
+ mtx_unlock(&sc->mtx);
+}
+
+static int
+tegra210_car_detach(device_t dev)
+{
+
+ device_printf(dev, "Error: Clock driver cannot be detached\n");
+ return (EBUSY);
+}
+
+static int
+tegra210_car_probe(device_t dev)
+{
+
+ if (!ofw_bus_status_okay(dev))
+ return (ENXIO);
+
+ if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) {
+ device_set_desc(dev, "Tegra Clock Driver");
+ return (BUS_PROBE_DEFAULT);
+ }
+
+ return (ENXIO);
+}
+
+static int
+tegra210_car_attach(device_t dev)
+{
+ struct tegra210_car_softc *sc = device_get_softc(dev);
+ int rid, rv;
+
+ sc->dev = dev;
+
+ mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF);
+ sc->type = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
+
+ /* Resource setup. */
+ rid = 0;
+ sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
+ RF_ACTIVE);
+ if (!sc->mem_res) {
+ device_printf(dev, "cannot allocate memory resource\n");
+ rv = ENXIO;
+ goto fail;
+ }
+
+ register_clocks(dev);
+ hwreset_register_ofw_provider(dev);
+ return (0);
+
+fail:
+ if (sc->mem_res)
+ bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
+
+ return (rv);
+}
+
+static int
+tegra210_car_hwreset_assert(device_t dev, intptr_t id, bool value)
+{
+ struct tegra210_car_softc *sc = device_get_softc(dev);
+
+ return (tegra210_hwreset_by_idx(sc, id, value));
+}
+
+static device_method_t tegra210_car_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, tegra210_car_probe),
+ DEVMETHOD(device_attach, tegra210_car_attach),
+ DEVMETHOD(device_detach, tegra210_car_detach),
+
+ /* Clkdev interface*/
+ DEVMETHOD(clkdev_read_4, tegra210_car_clkdev_read_4),
+ DEVMETHOD(clkdev_write_4, tegra210_car_clkdev_write_4),
+ DEVMETHOD(clkdev_modify_4, tegra210_car_clkdev_modify_4),
+ DEVMETHOD(clkdev_device_lock, tegra210_car_clkdev_device_lock),
+ DEVMETHOD(clkdev_device_unlock, tegra210_car_clkdev_device_unlock),
+
+ /* Reset interface */
+ DEVMETHOD(hwreset_assert, tegra210_car_hwreset_assert),
+
+ DEVMETHOD_END
+};
+
+static devclass_t tegra210_car_devclass;
+static DEFINE_CLASS_0(car, tegra210_car_driver, tegra210_car_methods,
+ sizeof(struct tegra210_car_softc));
+EARLY_DRIVER_MODULE(tegra210_car, simplebus, tegra210_car_driver,
+ tegra210_car_devclass, NULL, NULL, BUS_PASS_TIMER);
diff --git a/sys/arm64/nvidia/tegra210/tegra210_car.h b/sys/arm64/nvidia/tegra210/tegra210_car.h
new file mode 100644
index 000000000000..bfbe09e87933
--- /dev/null
+++ b/sys/arm64/nvidia/tegra210/tegra210_car.h
@@ -0,0 +1,528 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
+ *
+ * Copyright 2020 Michal Meloun <mmel@FreeBSD.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef _TEGRA210_CAR_
+#define _TEGRA210_CAR_
+
+#include "clkdev_if.h"
+
+#define RD4(sc, reg, val) CLKDEV_READ_4((sc)->clkdev, reg, val)
+#define WR4(sc, reg, val) CLKDEV_WRITE_4((sc)->clkdev, reg, val)
+#define MD4(sc, reg, mask, set) CLKDEV_MODIFY_4((sc)->clkdev, reg, mask, set)
+#define DEVICE_LOCK(sc) CLKDEV_DEVICE_LOCK((sc)->clkdev)
+#define DEVICE_UNLOCK(sc) CLKDEV_DEVICE_UNLOCK((sc)->clkdev)
+
+#define RST_SOURCE 0x000
+#define RST_DEVICES_L 0x004
+#define RST_DEVICES_H 0x008
+#define RST_DEVICES_U 0x00C
+#define CLK_OUT_ENB_L 0x010
+#define CLK_OUT_ENB_H 0x014
+#define CLK_OUT_ENB_U 0x018
+#define SUPER_CCLK_DIVIDER 0x024
+#define SCLK_BURST_POLICY 0x028
+#define SUPER_SCLK_DIVIDER 0x02c
+#define CLK_SYSTEM_RATE 0x030
+#define CLK_MASK_ARM 0x044
+#define MISC_CLK_ENB 0x048
+
+#define OSC_CTRL 0x050
+ #define OSC_CTRL_OSC_FREQ_GET(x) (((x) >> 28) & 0x0F)
+ #define OSC_CTRL_PLL_REF_DIV_GET(x) (((x) >> 26) & 0x03)
+
+#define OSC_FREQ_DET_STATUS 0x05c
+#define PLLE_SS_CNTL 0x068
+#define PLLE_SS_CNTL_INTEGOFFSET(x) (((x) & 0x03) << 30)
+#define PLLE_SS_CNTL_SSCINCINTRV(x) (((x) & 0x3f) << 24)
+#define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16)
+#define PLLE_SS_CNTL_SSCINVERT (1 << 15)
+#define PLLE_SS_CNTL_SSCCENTER (1 << 14)
+#define PLLE_SS_CNTL_SSCPDMBYP (1 << 13)
+#define PLLE_SS_CNTL_SSCBYP (1 << 12)
+#define PLLE_SS_CNTL_INTERP_RESET (1 << 11)
+#define PLLE_SS_CNTL_BYPASS_SS (1 << 10)
+#define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0)
+
+#define PLLE_SS_CNTL_SSCINCINTRV_MASK (0x3f << 24)
+#define PLLE_SS_CNTL_SSCINCINTRV_VAL (0x20 << 24)
+#define PLLE_SS_CNTL_SSCINC_MASK (0xff << 16)
+#define PLLE_SS_CNTL_SSCINC_VAL (0x1 << 16)
+#define PLLE_SS_CNTL_SSCMAX_MASK 0x1ff
+#define PLLE_SS_CNTL_SSCMAX_VAL 0x25
+#define PLLE_SS_CNTL_DISABLE (PLLE_SS_CNTL_BYPASS_SS | \
+ PLLE_SS_CNTL_INTERP_RESET | \
+ PLLE_SS_CNTL_SSCBYP)
+#define PLLE_SS_CNTL_COEFFICIENTS_MASK (PLLE_SS_CNTL_SSCMAX_MASK | \
+ PLLE_SS_CNTL_SSCINC_MASK | \
+ PLLE_SS_CNTL_SSCINCINTRV_MASK)
+#define PLLE_SS_CNTL_COEFFICIENTS_VAL (PLLE_SS_CNTL_SSCMAX_VAL | \
+ PLLE_SS_CNTL_SSCINC_VAL | \
+ PLLE_SS_CNTL_SSCINCINTRV_VAL)
+
+#define PLLE_MISC1 0x06C
+#define PLLC_BASE 0x080
+#define PLLC_OUT 0x084
+#define PLLC_MISC_0 0x088
+#define PLLC_MISC_1 0x08c
+#define PLLM_BASE 0x090
+#define PLLM_MISC1 0x099
+#define PLLM_MISC2 0x09c
+#define PLLP_BASE 0x0a0
+#define PLLP_OUTA 0x0a4
+#define PLLP_OUTB 0x0a8
+#define PLLP_MISC 0x0ac
+#define PLLA_BASE 0x0b0
+#define PLLA_OUT 0x0b4
+#define PLLA_MISC1 0x0b8
+#define PLLA_MISC 0x0bc
+#define PLLU_BASE 0x0c0
+#define PLLU_OUTA 0x0c4
+#define PLLU_MISC1 0x0c8
+#define PLLU_MISC 0x0cc
+#define PLLD_BASE 0x0d0
+#define PLLD_MISC1 0x0d8
+#define PLLD_MISC 0x0dc
+#define PLLX_BASE 0x0e0
+#define PLLX_MISC 0x0e4
+#define PLLX_MISC_LOCK_ENABLE (1 << 18)
+
+#define PLLE_BASE 0x0e8
+#define PLLE_BASE_ENABLE (1U << 31)
+#define PLLE_BASE_LOCK_OVERRIDE (1 << 30)
+
+#define PLLE_MISC 0x0ec
+#define PLLE_MISC_SETUP_BASE(x) (((x) & 0xFFFF) << 16)
+#define PLLE_MISC_CLKENABLE (1 << 15)
+#define PLLE_MISC_IDDQ_SWCTL (1 << 14)
+#define PLLE_MISC_IDDQ_OVERRIDE_VALUE (1 << 13)
+#define PLLE_MISC_IDDQ_FREQLOCK (1 << 12)
+#define PLLE_MISC_LOCK (1 << 11)
+#define PLLE_MISC_REF_DIS (1 << 10)
+#define PLLE_MISC_LOCK_ENABLE (1 << 9)
+#define PLLE_MISC_PTS (1 << 8)
+#define PLLE_MISC_KCP(x) (((x) & 0x03) << 6)
+#define PLLE_MISC_VREG_BG_CTRL(x) (((x) & 0x03) << 4)
+#define PLLE_MISC_VREG_CTRL(x) (((x) & 0x03) << 2)
+#define PLLE_MISC_KVCO (1 << 0)
+
+#define PLLE_MISC_VREG_BG_CTRL_SHIFT 4
+#define PLLE_MISC_VREG_BG_CTRL_MASK (3 << PLLE_MISC_VREG_BG_CTRL_SHIFT)
+#define PLLE_MISC_VREG_CTRL_SHIFT 2
+#define PLLE_MISC_VREG_CTRL_MASK (2 << PLLE_MISC_VREG_CTRL_SHIFT)
+#define PLLE_MISC_SETUP_BASE_SHIFT 16
+#define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT)
+
+#define PLLE_SS_CNTL1 0x0f0
+#define PLLE_SS_CNTL2 0x0f4
+#define LVL2_CLK_GATE_OVRA 0x0f8
+#define LVL2_CLK_GATE_OVRB 0x0fc
+#define LVL2_CLK_GATE_OVRC 0x3a0 /* Misordered in TRM */
+#define LVL2_CLK_GATE_OVRD 0x3a4
+#define LVL2_CLK_GATE_OVRE 0x554
+
+#define CLK_SOURCE_I2S2 0x100
+#define CLK_SOURCE_I2S3 0x104
+#define CLK_SOURCE_SPDIF_OUT 0x108
+#define CLK_SOURCE_SPDIF_IN 0x10c
+#define CLK_SOURCE_PWM 0x110
+#define CLK_SOURCE_SPI2 0x118
+#define CLK_SOURCE_SPI3 0x11c
+#define CLK_SOURCE_I2C1 0x124
+#define CLK_SOURCE_I2C5 0x128
+#define CLK_SOURCE_SPI1 0x134
+#define CLK_SOURCE_DISP1 0x138
+#define CLK_SOURCE_DISP2 0x13c
+#define CLK_SOURCE_ISP 0x144
+#define CLK_SOURCE_VI 0x148
+#define CLK_SOURCE_SDMMC1 0x150
+#define CLK_SOURCE_SDMMC2 0x154
+#define CLK_SOURCE_SDMMC4 0x164
+#define CLK_SOURCE_UARTA 0x178
+#define CLK_SOURCE_UARTB 0x17c
+#define CLK_SOURCE_HOST1X 0x180
+#define CLK_SOURCE_I2C2 0x198
+#define CLK_SOURCE_EMC 0x19c
+#define CLK_SOURCE_UARTC 0x1a0
+#define CLK_SOURCE_VI_SENSOR 0x1a8
+#define CLK_SOURCE_SPI4 0x1b4
+#define CLK_SOURCE_I2C3 0x1b8
+#define CLK_SOURCE_SDMMC3 0x1bc
+#define CLK_SOURCE_UARTD 0x1c0
+#define CLK_SOURCE_OWR 0x1cc
+#define CLK_SOURCE_CSITE 0x1d4
+#define CLK_SOURCE_I2S1 0x1d8
+#define CLK_SOURCE_DTV 0x1dc
+#define CLK_SOURCE_TSEC 0x1f4
+#define CLK_SOURCE_SPARE2 0x1f8
+
+#define CLK_OUT_ENB_X 0x280
+#define CLK_ENB_X_SET 0x284
+#define CLK_ENB_X_CLR 0x288
+#define RST_DEVICES_X 0x28C
+#define RST_DEV_X_SET 0x290
+#define RST_DEV_X_CLR 0x294
+#define CLK_OUT_ENB_Y 0x298
+#define CLK_ENB_Y_SET 0x29c
+#define CLK_ENB_Y_CLR 0x2a0
+#define RST_DEVICES_Y 0x2a4
+#define RST_DEV_Y_SET 0x2a8
+#define RST_DEV_Y_CLR 0x2ac
+#define DFLL_BASE 0x2f4
+#define DFLL_BASE_DVFS_DFLL_RESET (1 << 0)
+
+#define RST_DEV_L_SET 0x300
+#define RST_DEV_L_CLR 0x304
+#define RST_DEV_H_SET 0x308
+#define RST_DEV_H_CLR 0x30c
+#define RST_DEV_U_SET 0x310
+#define RST_DEV_U_CLR 0x314
+#define CLK_ENB_L_SET 0x320
+#define CLK_ENB_L_CLR 0x324
+#define CLK_ENB_H_SET 0x328
+#define CLK_ENB_H_CLR 0x32c
+#define CLK_ENB_U_SET 0x330
+#define CLK_ENB_U_CLR 0x334
+#define CCPLEX_PG_SM_OVRD 0x33c
+#define CPU_CMPLX_SET 0x340
+#define RST_DEVICES_V 0x358
+#define RST_DEVICES_W 0x35c
+#define CLK_OUT_ENB_V 0x360
+#define CLK_OUT_ENB_W 0x364
+#define CCLKG_BURST_POLICY 0x368
+#define SUPER_CCLKG_DIVIDER 0x36C
+#define CCLKLP_BURST_POLICY 0x370
+#define SUPER_CCLKLP_DIVIDER 0x374
+#define CLK_CPUG_CMPLX 0x378
+#define CPU_SOFTRST_CTRL 0x380
+#define CPU_SOFTRST_CTRL1 0x384
+#define CPU_SOFTRST_CTRL2 0x388
+#define CLK_SOURCE_MSELECT 0x3b4
+#define CLK_SOURCE_TSENSOR 0x3b8
+#define CLK_SOURCE_I2S4 0x3bc
+#define CLK_SOURCE_I2S5 0x3c0
+#define CLK_SOURCE_I2C4 0x3c4
+#define CLK_SOURCE_AHUB 0x3d0
+#define CLK_SOURCE_HDA2CODEC_2X 0x3e4
+#define CLK_SOURCE_ACTMON 0x3e8
+#define CLK_SOURCE_EXTPERIPH1 0x3ec
+#define CLK_SOURCE_EXTPERIPH2 0x3f0
+#define CLK_SOURCE_EXTPERIPH3 0x3f4
+#define CLK_SOURCE_I2C_SLOW 0x3fc
+
+#define CLK_SOURCE_SYS 0x400
+#define CLK_SOURCE_ISPB 0x404
+#define CLK_SOURCE_SOR1 0x410
+#define CLK_SOURCE_SOR0 0x414
+#define CLK_SOURCE_SATA_OOB 0x420
+#define CLK_SOURCE_SATA 0x424
+#define CLK_SOURCE_HDA 0x428
+#define RST_DEV_V_SET 0x430
+#define RST_DEV_V_CLR 0x434
+#define RST_DEV_W_SET 0x438
+#define RST_DEV_W_CLR 0x43c
+#define CLK_ENB_V_SET 0x440
+#define CLK_ENB_V_CLR 0x444
+#define CLK_ENB_W_SET 0x448
+#define CLK_ENB_W_CLR 0x44c
+#define RST_CPUG_CMPLX_SET 0x450
+#define RST_CPUG_CMPLX_CLR 0x454
+#define CLK_CPUG_CMPLX_SET 0x460
+#define CLK_CPUG_CMPLX_CLR 0x464
+#define CPU_CMPLX_STATUS 0x470
+#define INTSTATUS 0x478
+#define INTMASK 0x47c
+#define UTMIP_PLL_CFG0 0x480
+
+#define UTMIP_PLL_CFG1 0x484
+#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP (1 << 17)
+#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN (1 << 16)
+#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP (1 << 15)
+#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN (1 << 14)
+#define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN (1 << 12)
+#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6)
+#define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
+
+#define UTMIP_PLL_CFG2 0x488
+#define UTMIP_PLL_CFG2_PHY_XTAL_CLOCKEN (1 << 30)
+#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP (1 << 25)
+#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN (1 << 24)
+#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
+#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6)
+#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP (1 << 5)
+#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN (1 << 4)
+#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP (1 << 3)
+#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN (1 << 2)
+#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP (1 << 1)
+#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN (1 << 0)
+
+#define PLLE_AUX 0x48c
+#define PLLE_AUX_SS_SEQ_INCLUDE (1U << 31)
+#define PLLE_AUX_REF_SEL_PLLREFE (1 << 28)
+#define PLLE_AUX_SEQ_STATE_GET(x) (((x) >> 26) & 0x03)
+#define PLLE_AUX_SEQ_STATE_OFF 0
+#define PLLE_AUX_SEQ_STATE_ON 1
+#define PLLE_AUX_SEQ_STATE_BUSY 2
+#define PLLE_AUX_SEQ_START_STATE (1 << 25)
+#define PLLE_AUX_SEQ_ENABLE (1 << 24)
+#define PLLE_AUX_SS_DLY(x) (((x) & 0xFF) << 16)
+#define PLLE_AUX_SS_LOCK_DLY(x) (((x) & 0xFF) << 8)
+#define PLLE_AUX_SS_TEST_FAST_PT (1 << 7)
+#define PLLE_AUX_SS_SWCTL (1 << 6)
+#define PLLE_AUX_CONFIG_SWCTL (1 << 6)
+#define PLLE_AUX_ENABLE_SWCTL (1 << 4)
+#define PLLE_AUX_USE_LOCKDET (1 << 3)
+#define PLLE_AUX_REF_SRC (1 << 2)
+#define PLLE_AUX_PLLP_CML1_OEN (1 << 1)
+#define PLLE_AUX_PLLP_CML0_OEN (1 << 0)
+
+#define SATA_PLL_CFG0 0x490
+#define SATA_PLL_CFG0_SEQ_START_STATE (1 << 25)
+#define SATA_PLL_CFG0_SEQ_ENABLE (1 << 24)
+#define SATA_PLL_CFG0_PADPLL_SLEEP_IDDQ (1 << 13)
+#define SATA_PLL_CFG0_SEQ_PADPLL_PD_INPUT_VALUE (1 << 7)
+#define SATA_PLL_CFG0_SEQ_LANE_PD_INPUT_VALUE (1 << 6)
+#define SATA_PLL_CFG0_SEQ_RESET_INPUT_VALUE (1 << 5)
+#define SATA_PLL_CFG0_SEQ_IN_SWCTL (1 << 4)
+#define SATA_PLL_CFG0_PADPLL_USE_LOCKDET (1 << 2)
+#define SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE (1 << 1)
+#define SATA_PLL_CFG0_PADPLL_RESET_SWCTL (1 << 0)
+
+#define SATA_PLL_CFG1 0x494
+#define PCIE_PLL_CFG 0x498
+#define PCIE_PLL_CFG_SEQ_START_STATE (1 << 25)
+#define PCIE_PLL_CFG_SEQ_ENABLE (1 << 24)
+
+#define PROG_AUDIO_DLY_CLK 0x49c
+#define AUDIO_SYNC_CLK_I2S1 0x4a0
+#define AUDIO_SYNC_CLK_I2S2 0x4a4
+#define AUDIO_SYNC_CLK_I2S3 0x4a8
+#define AUDIO_SYNC_CLK_I2S4 0x4ac
+#define AUDIO_SYNC_CLK_I2S5 0x4b0
+#define AUDIO_SYNC_CLK_SPDIF 0x4b4
+#define PLLD2_BASE 0x4b8
+#define PLLD2_MISC 0x4bc
+#define UTMIP_PLL_CFG3 0x4c0
+#define PLLREFE_BASE 0x4c4
+#define PLLREFE_MISC 0x4c8
+#define PLLREFE_OUT 0x4cc
+#define CPU_FINETRIM_BYP 0x4d0
+#define CPU_FINETRIM_SELECT 0x4d4
+#define CPU_FINETRIM_DR 0x4d8
+#define CPU_FINETRIM_DF 0x4dc
+#define CPU_FINETRIM_F 0x4e0
+#define CPU_FINETRIM_R 0x4e4
+#define PLLC2_BASE 0x4e8
+#define PLLC2_MISC_0 0x4ec
+#define PLLC2_MISC_1 0x4f0
+#define PLLC2_MISC_2 0x4f4
+#define PLLC2_MISC_3 0x4f8
+#define PLLC3_BASE 0x4fc
+
+#define PLLC3_MISC_0 0x500
+#define PLLC3_MISC_1 0x504
+#define PLLC3_MISC_2 0x508
+#define PLLC3_MISC_3 0x50c
+#define PLLX_MISC_2 0x514
+#define PLLX_MISC_2 0x514
+#define PLLX_MISC_2_DYNRAMP_STEPB(x) (((x) & 0xFF) << 24)
+#define PLLX_MISC_2_DYNRAMP_STEPA(x) (((x) & 0xFF) << 16)
+#define PLLX_MISC_2_NDIV_NEW(x) (((x) & 0xFF) << 8)
+#define PLLX_MISC_2_EN_FSTLCK (1 << 5)
+#define PLLX_MISC_2_LOCK_OVERRIDE (1 << 4)
+#define PLLX_MISC_2_PLL_FREQLOCK (1 << 3)
+#define PLLX_MISC_2_DYNRAMP_DONE (1 << 2)
+#define PLLX_MISC_2_EN_DYNRAMP (1 << 0)
+
+#define PLLX_MISC_3 0x518
+
+#define XUSBIO_PLL_CFG0 0x51c
+#define XUSBIO_PLL_CFG0_SEQ_START_STATE (1 << 25)
+#define XUSBIO_PLL_CFG0_SEQ_ENABLE (1 << 24)
+#define XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ (1 << 13)
+#define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET (1 << 6)
+#define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL (1 << 2)
+#define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL (1 << 0)
+
+#define XUSBIO_PLL_CFG1 0x520
+#define PLLE_AUX1 0x524
+#define PLLP_RESHIFT 0x528
+#define UTMIPLL_HW_PWRDN_CFG0 0x52c
+#define UTMIPLL_HW_PWRDN_CFG0_UTMIPLL_LOCK (1U << 31)
+#define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE (1 << 25)
+#define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE (1 << 24)
+#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE (1 << 7)
+#define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET (1 << 6)
+#define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE (1 << 5)
+#define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL (1 << 4)
+#define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL (1 << 2)
+#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE (1 << 1)
+#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL (1 << 0)
+
+#define PLLU_HW_PWRDN_CFG0 0x530
+#define PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE (1 << 28)
+#define PLLU_HW_PWRDN_CFG0_SEQ_ENABLE (1 << 24)
+#define PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT (1 << 7)
+#define PLLU_HW_PWRDN_CFG0_USE_LOCKDET (1 << 6)
+#define PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL (1 << 2)
+#define PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL (1 << 0)
+
+#define XUSB_PLL_CFG0 0x534
+#define XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY 0x3ff
+#define XUSB_PLL_CFG0_PLLU_LOCK_DLY_MASK (0x3ff << 14)
+
+#define CLK_CPU_MISC 0x53c
+#define CLK_CPUG_MISC 0x540
+#define PLLX_HW_CTRL_CFG 0x548
+#define PLLX_SW_RAMP_CFG 0x54c
+#define PLLX_HW_CTRL_STATUS 0x550
+#define SPARE_REG0 0x55c
+#define SPARE_REG0_MDIV_GET(x) (((x) >> 2) & 0x03)
+
+#define AUDIO_SYNC_CLK_DMIC1 0x560
+#define AUDIO_SYNC_CLK_DMIC2 0x564
+#define PLLD2_SS_CFG 0x570
+#define PLLD2_SS_CTRL1 0x574
+#define PLLD2_SS_CTRL2 0x578
+#define PLLDP_BASE 0x590
+#define PLLDP_MISC 0x594
+#define PLLDP_SS_CFG 0x594
+#define PLLDP_SS_CTRL1 0x598
+#define PLLDP_SS_CTRL2 0x5a0
+#define PLLC4_BASE 0x5a4
+#define PLLC4_MISC 0x5a8
+#define SPARE0 0x5c4
+#define SPARE1 0x5c8
+#define GPU_ISOB_CTRL 0x5cc
+#define PLLC_MISC_2 0x5d0
+#define PLLC_MISC_3 0x5d4
+#define PLLA_MISC2 0x5d8
+#define PLLC4_OUT 0x5e4
+#define PLLMB_BASE 0x5e8
+#define PLLMB_MISC1 0x5ec
+#define PLLX_MISC_4 0x5f0
+#define PLLX_MISC_5 0x5f4
+
+#define CLK_SOURCE_XUSB_CORE_HOST 0x600
+#define CLK_SOURCE_XUSB_FALCON 0x604
+#define CLK_SOURCE_XUSB_FS 0x608
+#define CLK_SOURCE_XUSB_CORE_DEV 0x60c
+#define CLK_SOURCE_XUSB_SS 0x610
+#define CLK_SOURCE_CILAB 0x614
+#define CLK_SOURCE_CILCD 0x618
+#define CLK_SOURCE_CILEF 0x61c
+#define CLK_SOURCE_DSIA_LP 0x620
+#define CLK_SOURCE_DSIB_LP 0x624
+#define CLK_SOURCE_ENTROPY 0x628
+#define CLK_SOURCE_DVFS_REF 0x62c
+#define CLK_SOURCE_DVFS_SOC 0x630
+#define CLK_SOURCE_EMC_LATENCY 0x640
+#define CLK_SOURCE_SOC_THERM 0x644
+#define CLK_SOURCE_DMIC1 0x64c
+#define CLK_SOURCE_DMIC2 0x650
+#define CLK_SOURCE_VI_SENSOR2 0x658
+#define CLK_SOURCE_I2C6 0x65c
+#define CLK_SOURCE_MIPIBIF 0x660
+#define CLK_SOURCE_EMC_DLL 0x664
+#define CLK_SOURCE_UART_FST_MIPI_CAL 0x66c
+#define CLK_SOURCE_VIC 0x678
+#define PLLP_OUTC 0x67c
+#define PLLP_MISC1 0x680
+#define EMC_DIV_CLK_SHAPER_CTRL 0x68c
+#define EMC_PLLC_SHAPER_CTRL 0x690
+#define CLK_SOURCE_SDMMC_LEGACY_TM 0x694
+#define CLK_SOURCE_NVDEC 0x698
+#define CLK_SOURCE_NVJPG 0x69c
+#define CLK_SOURCE_NVENC 0x6a0
+#define PLLA1_BASE 0x6a4
+#define PLLA1_MISC_0 0x6a8
+#define PLLA1_MISC_1 0x6ac
+#define PLLA1_MISC_2 0x6b0
+#define PLLA1_MISC_3 0x6b4
+#define AUDIO_SYNC_CLK_DMIC3 0x6b8
+#define CLK_SOURCE_DMIC3 0x6bc
+#define CLK_SOURCE_APE 0x6c0
+#define CLK_SOURCE_QSPI 0x6c4
+#define CLK_SOURCE_VI_I2C 0x6c8
+#define CLK_SOURCE_USB2_HSIC_TRK 0x6cc
+#define CLK_SOURCE_PEX_SATA_USB_RX_BYP 0x6d0
+#define CLK_SOURCE_MAUD 0x6d4
+#define CLK_SOURCE_TSECB 0x6d8
+#define CLK_CPUG_MISC1 0x6d8
+#define ACLK_BURST_POLICY 0x6e0
+#define SUPER_ACLK_DIVIDER 0x6e4
+#define NVENC_SUPER_CLK_DIVIDER 0x6e8
+#define VI_SUPER_CLK_DIVIDER 0x6ec
+#define VIC_SUPER_CLK_DIVIDER 0x6f0
+#define NVDEC_SUPER_CLK_DIVIDER 0x6f4
+#define ISP_SUPER_CLK_DIVIDER 0x6f8
+#define ISPB_SUPER_CLK_DIVIDER 0x6fc
+
+#define NVJPG_SUPER_CLK_DIVIDER 0x700
+#define SE_SUPER_CLK_DIVIDER 0x704
+#define TSEC_SUPER_CLK_DIVIDER 0x708
+#define TSECB_SUPER_CLK_DIVIDER 0x70c
+#define CLK_SOURCE_UARTAPE 0x710
+#define CLK_CPUG_MISC2 0x714
+#define CLK_SOURCE_DBGAPB 0x718
+#define CLK_CCPLEX_CC4_RET_CLK_ENB 0x71c
+#define ACTMON_CPU_CLK 0x720
+#define CLK_SOURCE_EMC_SAFE 0x724
+#define SDMMC2_PLLC4_OUT0_SHAPER_CTRL 0x728
+#define SDMMC2_PLLC4_OUT1_SHAPER_CTRL 0x72c
+#define SDMMC2_PLLC4_OUT2_SHAPER_CTRL 0x730
+#define SDMMC2_DIV_CLK_SHAPER_CTRL 0x734
+#define SDMMC4_PLLC4_OUT0_SHAPER_CTRL 0x738
+#define SDMMC4_PLLC4_OUT1_SHAPER_CTRL 0x73c
+#define SDMMC4_PLLC4_OUT2_SHAPER_CTRL 0x740
+#define SDMMC4_DIV_CLK_SHAPER_CTRL 0x744
+
+struct tegra210_car_softc {
+ device_t dev;
+ struct resource * mem_res;
+ struct mtx mtx;
+ struct clkdom *clkdom;
+ int type;
+};
+
+struct tegra210_init_item {
+ char *name;
+ char *parent;
+ uint64_t frequency;
+ int enable;
+};
+
+void tegra210_init_plls(struct tegra210_car_softc *sc);
+
+void tegra210_periph_clock(struct tegra210_car_softc *sc);
+void tegra210_super_mux_clock(struct tegra210_car_softc *sc);
+
+int tegra210_hwreset_by_idx(struct tegra210_car_softc *sc, intptr_t idx,
+ bool reset);
+
+#endif /*_TEGRA210_CAR_*/ \ No newline at end of file
diff --git a/sys/arm64/nvidia/tegra210/tegra210_clk_per.c b/sys/arm64/nvidia/tegra210/tegra210_clk_per.c
new file mode 100644
index 000000000000..32ad855b5a55
--- /dev/null
+++ b/sys/arm64/nvidia/tegra210/tegra210_clk_per.c
@@ -0,0 +1,951 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
+ *
+ * Copyright 2020 Michal Meloun <mmel@FreeBSD.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+#include <sys/rman.h>
+
+#include <machine/bus.h>
+
+#include <dev/extres/clk/clk.h>
+
+#include <gnu/dts/include/dt-bindings/clock/tegra210-car.h>
+#include <gnu/dts/include/dt-bindings/reset/tegra210-car.h>
+
+#include "tegra210_car.h"
+
+/* Bits in base register. */
+#define PERLCK_AMUX_MASK 0x0F
+#define PERLCK_AMUX_SHIFT 16
+#define PERLCK_AMUX_DIS (1 << 20)
+#define PERLCK_UDIV_DIS (1 << 24)
+#define PERLCK_ENA_MASK (1 << 28)
+#define PERLCK_MUX_SHIFT 29
+#define PERLCK_MUX_MASK 0x07
+
+
+struct periph_def {
+ struct clknode_init_def clkdef;
+ uint32_t base_reg;
+ uint32_t div_width;
+ uint32_t div_mask;
+ uint32_t div_f_width;
+ uint32_t div_f_mask;
+ uint32_t flags;
+};
+
+struct pgate_def {
+ struct clknode_init_def clkdef;
+ uint32_t idx;
+ uint32_t flags;
+};
+#define PLIST(x) static const char *x[]
+
+#define GATE(_id, cname, plist, _idx) \
+{ \
+ .clkdef.id = TEGRA210_CLK_##_id, \
+ .clkdef.name = cname, \
+ .clkdef.parent_names = (const char *[]){plist}, \
+ .clkdef.parent_cnt = 1, \
+ .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
+ .idx = _idx, \
+ .flags = 0, \
+}
+/* Sources for multiplexors. */
+PLIST(mux_N_N_c_N_p_N_a) =
+ {"bogus", NULL, "pllC_out0", NULL,
+ "pllP_out0", NULL, "pllA_out0", NULL};
+PLIST(mux_N_N_p_N_N_N_clkm) =
+ {NULL, NULL, "pllP_out0", NULL,
+ NULL, NULL, "clk_m", NULL};
+PLIST(mux_N_c_p_a1_c2_c3_clkm) =
+ {NULL, "pllC_out0", "pllP_out0", "pllA1_out0",
+ "pllC2_out0", "pllC3_out0", "clk_m", NULL};
+PLIST(mux_N_c_p_a1_c2_c3_clkm_c4) =
+ {NULL, "pllC_out0", "pllP_out0", "pllA1_out0",
+ "pllC2_out0", "pllC3_out0", "clk_m", "pllC4_out0"};
+PLIST(mux_N_c_p_clkm_N_c4_c4o1_c4o1) =
+ {NULL, "pllC_out0", "pllP_out0", "clk_m",
+ NULL, "pllC4_out0", "pllC4_out1", "pllC4_out1"};
+PLIST(mux_N_c_p_clkm_N_c4_c4o1_c4o2) =
+ {NULL, "pllC_out0", "pllP_out0", "clk_m",
+ NULL, "pllC4_out0", "pllC4_out1", "pllC4_out2"};
+
+PLIST(mux_N_c2_c_c3_p_N_a) =
+ {NULL, "pllC2_out0", "pllC_out0", "pllC3_out0",
+ "pllP_out0", NULL, "pllA_out0", NULL};
+PLIST(mux_N_c2_c_c3_p_clkm_a1_c4) =
+ {NULL, "pllC2_out0", "pllC_out0", "pllC3_out0",
+ "pllP_out0", "clk_m", "pllA1_out0", "pllC4_out0"};
+PLIST(mux_N_c2_c_c3_p_N_a1_clkm) =
+ {NULL, "pllC2_out0", "pllC_out0", "pllC3_out0",
+ "pllP_out0", NULL, "pllA1_out0", "clk_m"};
+
+PLIST(mux_a_N_audio_N_p_N_clkm) =
+ {"pllA_out0", NULL, "audio", NULL,
+ "pllP_out0", NULL, "clk_m"};
+PLIST(mux_a_N_audio0_N_p_N_clkm) =
+ {"pllA_out0", NULL, "audio0", NULL,
+ "pllP_out0", NULL, "clk_m"};
+PLIST(mux_a_N_audio1_N_p_N_clkm) =
+ {"pllA_out0", NULL, "audio1", NULL,
+ "pllP_out0", NULL, "clk_m"};
+PLIST(mux_a_N_audio2_N_p_N_clkm) =
+ {"pllA_out0", NULL, "audio2", NULL,
+ "pllP_out0", NULL, "clk_m"};
+PLIST(mux_a_N_audio3_N_p_N_clkm) =
+ {"pllA_out0", NULL, "audio3", NULL,
+ "pllP_out0", NULL, "clk_m"};
+PLIST(mux_a_N_audio4_N_p_N_clkm) =
+ {"pllA_out0", NULL, "audio4", NULL,
+ "pllP_out0", NULL, "clk_m"};
+PLIST(mux_a_audiod1_p_clkm) =
+ {"pllA_out0", "audiod1", "pllP_out0", "clk_m",
+ NULL, NULL, NULL, NULL};
+PLIST(mux_a_audiod2_p_clkm) =
+ {"pllA_out0", "audiod2", "pllP_out0", "clk_m",
+ NULL, NULL, NULL, NULL};
+PLIST(mux_a_audiod3_p_clkm) =
+ {"pllA_out0", "audiod3", "pllP_out0", "clk_m",
+ NULL, NULL, NULL, NULL};
+PLIST(mux_a_c4_c_c4o1_p_N_clkm_c4o2) =
+ {"pllA_out0", "pllC4_out0", "pllC_out0", "pllC4_out1",
+ "pllP_out0", NULL, "clk_m", "pllC4_out2"};
+
+PLIST(mux_a_clks_p_clkm_e) =
+ {"pllA_out0", "clk_s", "pllP_out0", "clk_m",
+ "pllE_out0"};
+PLIST(mux_c4o1_c2_c_c4_p_clkm_a_c4) =
+ {"pllC4_out1", "pllC2_out0", "pllC_out0", "pllC4_out0",
+ "pllP_out0", "clk_m","pllA_out0", "pllC4_out0", };
+
+PLIST(mux_m_c_p_clkm_mud_mbud_mb_pud) =
+ {"pllM_out0", "pllC_out0", "pllP_out0", "clk_m",
+ "pllM_UD", "pllMB_UD", "pllMB_out0", "pllP_UD"};
+PLIST(mux_p_N_N_c4o2_c4o1_N_clkm_c4) =
+ {"pllP_out0", NULL, NULL, "pllC4_out2",
+ "pllC4_out1", NULL, "clk_m", "pllC4_out0"};
+PLIST(mux_p_N_c_c4_c4o1_c4o2_clkm) =
+ {"pllP_out0", NULL, "pllC_out0", "pllC4_out0",
+ "pllC4_out1", "pllC4_out2", "clk_m"};
+PLIST(mux_p_N_c_c4_N_c4o1_clkm_c4o2) =
+ {"pllP_out0", NULL, "pllC_out0", "pllC4_out0",
+ NULL, "pllC4_out1", "clk_m", "pllC4_out2"};
+PLIST(mux_p_N_d_N_N_d2_clkm) =
+ {"pllP_out0", NULL, "pllD_out0", NULL,
+ NULL, "pllD2_out0", "clk_m"};
+PLIST(mux_p_N_clkm_N_clks_N_E) =
+ {"pllP_out0", NULL, "clk_m", NULL,
+ NULL, "clk_s", NULL, "pllE_out0"};
+PLIST(mux_p_c_c2_N_c2_N_clkm) =
+ {"pllP_out0", "pllC_out0", "pllC2_out0", NULL,
+ "pllC2_out0", NULL, "clk_m", NULL};
+PLIST(mux_p_co1_c_N_c4o2_c4o1_clkm_c4) =
+ {"pllP_out0", "pllC_out1", "pllC_out0", NULL,
+ "pllC4_out2", "pllC4_out1" ,"clk_m", "pllC4_out0"};
+PLIST(mux_p_c2_c_c3_N_a1_clkm_c4) =
+ {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC3_out0",
+ NULL, "pllA1_out0", "clk_m", "pllC4_out0"};
+PLIST(mux_p_c2_c_c3_N_N_clkm) =
+ {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC3_out0",
+ NULL, NULL, "clk_m", NULL};
+PLIST(mux_p_c2_c_c3_m_e_clkm) =
+ {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC3_out0",
+ "pllM_out0", "pllE_out0", "clk_m"};
+PLIST(mux_p_c2_c_c4_N_c4o1_clkm_c4o2) =
+ {"pllP_out0", "pllC2_out0", "pllC4_out0",
+ NULL, "pllC4_out1", "clk_m", "pllC4_out2"};
+PLIST(mux_p_c2_c_c4_a_c4o1_clkm_c4o2) =
+ {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC4_out0",
+ "pllA_out0", "pllC4_out1", "clk_m", "pllC4_out2"};
+PLIST(mux_p_c2_c_c4o2_c4o1_clks_clkm_c4) =
+ {"pllP_out0", "pllC2_out0", "pllC4_out2",
+ "pllC4_out1", "clk_s", "clk_m", "pllC4_out0"};
+
+PLIST(mux_p_c2_c_c4_c4o1_clkm_c4o2) =
+ {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC4_out0",
+ "pllC4_out1", "clk_m", "pllC4_out2"};
+PLIST(mux_p_c2_c_c4_clkm_c4o1_c4o2) =
+ {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC4_out0",
+ "clk_m", "pllC4_out1", "pllC4_out2"};
+PLIST(mux_p_c2_c_c4_clks_c4o1_clkm_c4o2) =
+ {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC4_out0",
+ "clk_s", "pllC4_out1", "clk_m", "pllC4_out2"};
+PLIST(mux_p_c2_c_c4_clkm_c4o1_clks_c4o2) =
+ {"pllP_out0", "pllC2_out0", "pllC_out0", "pllC4_out0",
+ "clk_m", "pllC4_out1", "clk_s", "pllC4_out2"};
+PLIST(mux_p_c2_refe1_c3_m_a1_clkm_C4) =
+ {"pllP_out0", "pllC2_out0", "pllREFE_out1", "pllC3_out0",
+ "pllM_out0", "pllA1_out0", "clk_m", "pllC4_out0"};
+PLIST(mux_p_c4_c_c4o1_N_c4o2_clkm) =
+ {"pllP_out0", "pllC4_out0", "pllC_out0", "pllC4_out1",
+ NULL, "pllC4_out2", "clk_m", NULL};
+PLIST(mux_p_m_d_a_c_d2_clkm) =
+ {"pllP_out0", "pllM_out0", "pllD_out0", "pllA_out0",
+ "pllC_out0", "pllD2_out0", "clk_m"};
+PLIST(mux_p_po3_clkm_clks_a) =
+ {"pllP_out0", "pllP_out3", "clk_m", "clk_s",
+ "pllA_out0", NULL, NULL, NULL};
+
+PLIST(mux_po3_c_c2_clkm_p_c4_c4o1_c4o2) =
+ {"pllP_out3", "pllC_out0", "pllC2_out0", "clk_m",
+ "pllP_out0", "pllC4_out0", "pllC4_out1", "pllC4_out2"};
+
+PLIST(mux_clkm_p_N_N_N_refre) =
+ {"clk_m", "pllP_xusb", NULL, NULL,
+ NULL, "pllREFE_out0", NULL, NULL};
+PLIST(mux_clkm_N_u48_N_p_N_u480) =
+ {"clk_m", NULL, "pllU_48", NULL,
+ "pllP_out0", NULL, "pllU_480"};
+PLIST(mux_clkm_refe_clks_u480) =
+ {"clk_m", "pllREFE_out0", "clk_s", "pllU_480",
+ NULL, NULL, NULL, NULL};
+
+PLIST(mux_sep_audio) =
+ {"pllA_out0", "pllC4_out0", "pllC_out0", "pllC4_out0",
+ "pllP_out0", "pllC4_out0", "clk_m", NULL,
+ "spdif_in", "i2s1", "i2s2", "i2s3",
+ "i2s4", "i2s5", "pllA_out0", "ext_vimclk"};
+
+static uint32_t clk_enable_reg[] = {
+ CLK_OUT_ENB_L,
+ CLK_OUT_ENB_H,
+ CLK_OUT_ENB_U,
+ CLK_OUT_ENB_V,
+ CLK_OUT_ENB_W,
+ CLK_OUT_ENB_X,
+ CLK_OUT_ENB_Y,
+};
+
+static uint32_t clk_reset_reg[] = {
+ RST_DEVICES_L,
+ RST_DEVICES_H,
+ RST_DEVICES_U,
+ RST_DEVICES_V,
+ RST_DEVICES_W,
+ RST_DEVICES_X,
+ RST_DEVICES_Y,
+};
+
+#define L(n) ((0 * 32) + (n))
+#define H(n) ((1 * 32) + (n))
+#define U(n) ((2 * 32) + (n))
+#define V(n) ((3 * 32) + (n))
+#define W(n) ((4 * 32) + (n))
+#define X(n) ((5 * 32) + (n))
+#define Y(n) ((6 * 32) + (n))
+
+/* Clock IDs not yet defined in binding header file. */
+#define TEGRA210_CLK_STAT_MON H(5)
+#define TEGRA210_CLK_IRAMA U(20)
+#define TEGRA210_CLK_IRAMB U(21)
+#define TEGRA210_CLK_IRAMC U(22)
+#define TEGRA210_CLK_IRAMD U(23)
+#define TEGRA210_CLK_CRAM2 U(24)
+#define TEGRA210_CLK_M_DOUBLER U(26)
+#define TEGRA210_CLK_DEVD2_OUT U(29)
+#define TEGRA210_CLK_DEVD1_OUT U(30)
+#define TEGRA210_CLK_CPUG V(0)
+#define TEGRA210_CLK_ATOMICS V(16)
+#define TEGRA210_CLK_PCIERX0 W(2)
+#define TEGRA210_CLK_PCIERX1 W(3)
+#define TEGRA210_CLK_PCIERX2 W(4)
+#define TEGRA210_CLK_PCIERX3 W(5)
+#define TEGRA210_CLK_PCIERX4 W(6)
+#define TEGRA210_CLK_PCIERX5 W(7)
+#define TEGRA210_CLK_PCIE2_IOBIST W(9)
+#define TEGRA210_CLK_EMC_IOBIST W(10)
+#define TEGRA210_CLK_SATA_IOBIST W(12)
+#define TEGRA210_CLK_MIPI_IOBIST W(13)
+#define TEGRA210_CLK_EMC_LATENCY W(29)
+#define TEGRA210_CLK_MC1 W(30)
+#define TEGRA210_CLK_ETR X(3)
+#define TEGRA210_CLK_CAM_MCLK X(4)
+#define TEGRA210_CLK_CAM_MCLK2 X(5)
+#define TEGRA210_CLK_MC_CAPA X(7)
+#define TEGRA210_CLK_MC_CBPA X(8)
+#define TEGRA210_CLK_MC_CPU X(9)
+#define TEGRA210_CLK_MC_BBC X(10)
+#define TEGRA210_CLK_EMC_DLL X(14)
+#define TEGRA210_CLK_UART_FST_MIPI_CAL X(17)
+#define TEGRA210_CLK_HPLL_ADSP X(26)
+#define TEGRA210_CLK_PLLP_ADSP X(27)
+#define TEGRA210_CLK_PLLA_ADSP X(28)
+#define TEGRA210_CLK_PLLG_REF X(29)
+#define TEGRA210_CLK_AXIAP Y(4)
+#define TEGRA210_CLK_MC_CDPA Y(8)
+#define TEGRA210_CLK_MC_CCPA Y(9)
+
+
+static struct pgate_def pgate_def[] = {
+ /* bank L -> 0-31 */
+ GATE(ISPB, "ispb", "clk_m", L(3)),
+ GATE(RTC, "rtc", "clk_s", L(4)),
+ GATE(TIMER, "timer", "clk_m", L(5)),
+ GATE(UARTA, "uarta", "pc_uarta" , L(6)),
+ GATE(UARTB, "uartb", "pc_uartb", L(7)),
+ GATE(GPIO, "gpio", "clk_m", L(8)),
+ GATE(SDMMC2, "sdmmc2", "pc_sdmmc2", L(9)),
+ GATE(SPDIF_OUT, "spdif_out", "pc_spdif_out", L(10)),
+ GATE(SPDIF_IN, "spdif_in", "pc_spdif_in", L(10)),
+ GATE(I2S1, "i2s2", "pc_i2s2", L(11)),
+ GATE(I2C1, "i2c1", "pc_i2c1", L(12)),
+ GATE(SDMMC1, "sdmmc1", "pc_sdmmc1", L(14)),
+ GATE(SDMMC4, "sdmmc4", "pc_sdmmc4", L(15)),
+ GATE(PWM, "pwm", "pc_pwm", L(17)),
+ GATE(I2S2, "i2s3", "pc_i2s3", L(18)),
+ GATE(VI, "vi", "pc_vi", L(20)),
+ GATE(USBD, "usbd", "clk_m", L(22)),
+ GATE(ISP, "isp", "pc_isp", L(23)),
+ GATE(DISP2, "disp2", "pc_disp2", L(26)),
+ GATE(DISP1, "disp1", "pc_disp1", L(27)),
+ GATE(HOST1X, "host1x", "pc_host1x", L(28)),
+ GATE(I2S0, "i2s1", "pc_i2s1", L(30)),
+
+ /* bank H -> 32-63 */
+ GATE(MC, "mem", "clk_m", H(0)),
+ GATE(AHBDMA, "ahbdma", "clk_m", H(1)),
+ GATE(APBDMA, "apbdma", "clk_m", H(2)),
+ GATE(STAT_MON, "stat_mon", "clk_s", H(5)),
+ GATE(PMC, "pmc", "clk_s", H(6)),
+ GATE(FUSE, "fuse", "clk_m", H(7)),
+ GATE(KFUSE, "kfuse", "clk_m", H(8)),
+ GATE(SBC1, "spi1", "pc_spi1", H(9)),
+ GATE(SBC2, "spi2", "pc_spi2", H(12)),
+ GATE(SBC3, "spi3", "pc_spi3", H(14)),
+ GATE(I2C5, "i2c5", "pc_i2c5", H(15)),
+ GATE(DSIA, "dsia", "pllD_dsi_csi", H(16)),
+ GATE(CSI, "csi", "pllP_out3", H(20)),
+ GATE(I2C2, "i2c2", "pc_i2c2", H(22)),
+ GATE(UARTC, "uartc", "pc_uartc", H(23)),
+ GATE(MIPI_CAL, "mipi_cal", "clk_m", H(24)),
+ GATE(EMC, "emc", "pc_emc", H(25)),
+ GATE(USB2, "usb2", "clk_m", H(26)),
+ GATE(BSEV, "bsev", "clk_m", H(31)),
+
+ /* bank U -> 64-95 */
+ GATE(UARTD, "uartd", "pc_uartd", U(1)),
+ GATE(I2C3, "i2c3", "pc_i2c3", U(3)),
+ GATE(SBC4, "spi4", "pc_spi4", U(4)),
+ GATE(SDMMC3, "sdmmc3", "pc_sdmmc3", U(5)),
+ GATE(PCIE, "pcie", "clk_m", U(6)),
+ GATE(AFI, "afi", "clk_m", U(8)),
+ GATE(CSITE, "csite", "pc_csite", U(9)),
+ GATE(SOC_THERM, "soc_therm", "pc_soc_therm", U(14)),
+ GATE(DTV, "dtv", "clk_m", U(15)),
+ GATE(I2CSLOW, "i2c_slow", "pc_i2c_slow", U(17)),
+ GATE(DSIB, "dsib", "pllD_dsi_csi", U(18)),
+ GATE(TSEC, "tsec", "pc_tsec", U(19)),
+ GATE(IRAMA, "irama", "clk_m", U(20)),
+ GATE(IRAMB, "iramb", "clk_m", U(21)),
+ GATE(IRAMC, "iramc", "clk_m", U(22)),
+ GATE(IRAMD, "iramd", "clk_m", U(23)),
+ GATE(CRAM2, "cram2", "clk_m", U(24)),
+ GATE(XUSB_HOST, "xusb_host", "pc_xusb_core_host", U(25)),
+ GATE(M_DOUBLER, "m_doubler", "clk_m", U(26)),
+ GATE(CSUS, "sus_out", "clk_m", U(28)),
+ GATE(DEVD2_OUT, "devd2_out", "clk_m", U(29)),
+ GATE(DEVD1_OUT, "devd1_out", "clk_m", U(30)),
+ GATE(XUSB_DEV, "xusb_core_dev", "pc_xusb_core_dev", U(31)),
+
+ /* bank V -> 96-127 */
+ GATE(CPUG, "cpug", "clk_m", V(0)),
+ GATE(MSELECT, "mselect", "pc_mselect", V(3)),
+ GATE(TSENSOR, "tsensor", "pc_tsensor", V(4)),
+ GATE(I2S4, "i2s5", "pc_i2s5", V(5)),
+ GATE(I2S3, "i2s4", "pc_i2s4", V(6)),
+ GATE(I2C4, "i2c4", "pc_i2c4", V(7)),
+ GATE(D_AUDIO, "ahub", "pc_ahub", V(10)),
+ GATE(APB2APE, "apb2ape", "clk_m", V(11)),
+ GATE(HDA2CODEC_2X, "hda2codec_2x", "pc_hda2codec_2x", V(15)),
+ GATE(ATOMICS, "atomics", "clk_m", V(16)),
+ GATE(SPDIF_2X, "spdif_doubler", "clk_m", V(22)),
+ GATE(ACTMON, "actmon", "pc_actmon", V(23)),
+ GATE(EXTERN1, "extperiph1", "pc_extperiph1", V(24)),
+ GATE(EXTERN2, "extperiph2", "pc_extperiph2", V(25)),
+ GATE(EXTERN3, "extperiph3", "pc_extperiph3", V(26)),
+ GATE(SATA_OOB, "sata_oob", "pc_sata_oob", V(27)),
+ GATE(SATA, "sata", "pc_sata", V(28)),
+ GATE(HDA, "hda", "pc_hda", V(29)),
+
+ /* bank W -> 128-159*/
+ GATE(HDA2HDMI, "hda2hdmi", "clk_m", W(0)),
+ /* GATE(SATA_COLD, "sata_cold", "clk_m", W(1)),*/ /* Reset only */
+ GATE(PCIERX0, "pcierx0", "clk_m", W(2)),
+ GATE(PCIERX1, "pcierx1", "clk_m", W(3)),
+ GATE(PCIERX2, "pcierx2", "clk_m", W(4)),
+ GATE(PCIERX3, "pcierx3", "clk_m", W(5)),
+ GATE(PCIERX4, "pcierx4", "clk_m", W(6)),
+ GATE(PCIERX5, "pcierx5", "clk_m", W(7)),
+ GATE(CEC, "cec", "clk_m", W(8)),
+ GATE(PCIE2_IOBIST, "pcie2_iobist", "clk_m", W(9)),
+ GATE(EMC_IOBIST, "emc_iobist", "clk_m", W(10)),
+ GATE(SATA_IOBIST, "sata_iobist", "clk_m", W(12)),
+ GATE(MIPI_IOBIST, "mipi_iobist", "clk_m", W(13)),
+ GATE(XUSB_GATE, "xusb", "clk_m", W(15)),
+ GATE(CILAB, "cilab", "pc_cilab", W(16)),
+ GATE(CILCD, "cilcd", "pc_cilcd", W(17)),
+ GATE(CILE, "cilef", "pc_cilef", W(18)),
+ GATE(DSIALP, "dsia_lp", "pc_dsia_lp", W(19)),
+ GATE(DSIBLP, "dsib_lp", "pc_dsib_lp", W(20)),
+ GATE(ENTROPY, "entropy", "pc_entropy", W(21)),
+ GATE(DFLL_REF, "dvfs_ref", "pc_dvfs_ref", W(27)),
+ GATE(DFLL_SOC, "dvfs_soc", "pc_dvfs_soc", W(27)),
+ GATE(XUSB_SS, "xusb_ss", "pc_xusb_ss", W(28)),
+ GATE(EMC_LATENCY, "emc_latency", "pc_emc_latency", W(29)),
+ GATE(MC1, "mc1", "clk_m", W(30)),
+
+ /* bank X -> 160-191*/
+ /*GATE(SPARE, "spare", "clk_m", X(0)), */
+ GATE(DMIC1, "dmic1", "clk_m", X(1)),
+ GATE(DMIC2, "dmic2", "clk_m", X(2)),
+ GATE(ETR, "etr", "clk_m", X(3)),
+ GATE(CAM_MCLK, "CAM_MCLK", "clk_m", X(4)),
+ GATE(CAM_MCLK2, "CAM_MCLK2", "clk_m", X(5)),
+ GATE(I2C6, "i2c6", "pc_i2c6", X(6)),
+ GATE(MC_CAPA, "mc_capa", "clk_m", X(7)),
+ GATE(MC_CBPA, "mc_cbpa", "clk_m", X(8)),
+ GATE(MC_CPU, "mc_cpu", "clk_m", X(9)),
+ GATE(MC_BBC, "mc_bbc", "clk_m", X(10)),
+ GATE(VIM2_CLK, "vim2_clk", "clk_m", X(11)),
+ GATE(MIPIBIF, "mipibif", "clk_m", X(13)),
+ GATE(EMC_DLL, "emc_dll", "pc_emc_dll", X(14)),
+ GATE(UART_FST_MIPI_CAL, "uart_fst_mipi_cal", "clk_m", X(17)),
+ GATE(VIC03, "vic", "pc_vic", X(18)),
+ GATE(DPAUX, "dpaux", "dpaux_div", X(21)),
+ GATE(SOR0, "sor0", "pc_sor0", X(22)),
+ GATE(SOR1, "sor1", "pc_sor1", X(23)),
+ GATE(GPU, "gpu", "osc_div_clk", X(24)),
+ GATE(DBGAPB, "dbgapb", "clk_m", X(25)),
+ GATE(HPLL_ADSP, "hpll_adsp", "clk_m", X(26)),
+ GATE(PLLP_ADSP, "pllp_adsp", "clk_m", X(27)),
+ GATE(PLLA_ADSP, "plla_adsp", "clk_m", X(28)),
+ GATE(PLLG_REF, "pllg_ref", "clk_m", X(29)),
+
+ /* bank Y -> 192-224*/
+ /* GATE(SPARE1, "spare1", "clk_m", Y(0)), */
+ GATE(SDMMC_LEGACY, "sdmmc_legacy_tm", "pc_sdmmc_legacy_tm", Y(1)),
+ GATE(NVDEC, "nvdec", "pc_nvdec", Y(2)),
+ GATE(NVJPG, "nvjpg", "clk_m", Y(3)),
+ GATE(AXIAP, "axiap", "clk_m", Y(4)),
+ GATE(DMIC3, "dmic3", "clk_m", Y(5)),
+ GATE(APE, "ape", "clk_m", Y(6)),
+ GATE(ADSP, "adsp", "clk_m", Y(7)),
+ GATE(MC_CDPA, "mc_cdpa", "clk_m", Y(8)),
+ GATE(MC_CCPA, "mc_ccpa", "clk_m", Y(9)),
+ GATE(MAUD, "mc_maud", "clk_m", Y(10)),
+ GATE(TSECB, "tsecb", "clk_m", Y(14)),
+ GATE(DPAUX1, "dpaux1", "dpaux1_div", Y(15)),
+ GATE(VI_I2C, "vi_i2c", "clk_m", Y(16)),
+ GATE(HSIC_TRK, "hsic_trk", "clk_m", Y(17)),
+ GATE(USB2_TRK, "usb2_trk", "clk_m", Y(18)),
+ GATE(QSPI, "qspi", "clk_m", Y(19)),
+ GATE(UARTAPE, "uarape", "clk_m", Y(20)),
+ GATE(ADSP_NEON, "adspneon", "clk_m", Y(26)),
+ GATE(NVENC, "nvenc", "clk_m", Y(27)),
+ GATE(IQC2, "iqc2", "clk_m", Y(28)),
+ GATE(IQC1, "iqc1", "clk_m", Y(29)),
+ GATE(SOR_SAFE, "sor_safe", "sor_safe_div", Y(30)),
+ GATE(PLL_P_OUT_CPU, "pllp_out_cpu", "clk_m", Y(31)),
+};
+
+/* Peripheral clock clock */
+#define DCF_HAVE_MUX 0x0100 /* Block with multipexor */
+#define DCF_HAVE_ENA 0x0200 /* Block with enable bit */
+#define DCF_HAVE_DIV 0x0400 /* Block with divider */
+
+/* Mark block with additional bits / functionality. */
+#define DCF_IS_MASK 0x00FF
+#define DCF_IS_UART 0x0001
+#define DCF_IS_VI 0x0002
+#define DCF_IS_HOST1X 0x0003
+#define DCF_IS_XUSB_SS 0x0004
+#define DCF_IS_EMC_DLL 0x0005
+#define DCF_IS_SATA 0x0006
+#define DCF_IS_VIC 0x0007
+#define DCF_IS_AHUB 0x0008
+#define DCF_IS_SOR0 0x0009
+#define DCF_IS_EMC 0x000A
+#define DCF_IS_QSPI 0x000B
+#define DCF_IS_EMC_SAFE 0x000C
+/* Basic pheripheral clock */
+#define PER_CLK(_id, cn, pl, r, diw, fiw, f) \
+{ \
+ .clkdef.id = _id, \
+ .clkdef.name = cn, \
+ .clkdef.parent_names = pl, \
+ .clkdef.parent_cnt = nitems(pl), \
+ .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
+ .base_reg = r, \
+ .div_width = diw, \
+ .div_f_width = fiw, \
+ .flags = f, \
+}
+
+/* Mux with fractional 8.1 divider. */
+#define CLK_8_1(id, cn, pl, r, f) \
+ PER_CLK(id, cn, pl, r, 8, 1, (f) | DCF_HAVE_MUX | DCF_HAVE_DIV)
+/* Mux with integer 8bits divider. */
+#define CLK_8_0(id, cn, pl, r, f) \
+ PER_CLK(id, cn, pl, r, 8, 0, (f) | DCF_HAVE_MUX | DCF_HAVE_DIV)
+
+/* Mux with fractional 16.1 divider. */
+#define CLK16_1(id, cn, pl, r, f) \
+ PER_CLK(id, cn, pl, r, 16, 1, (f) | DCF_HAVE_MUX | DCF_HAVE_DIV)
+/* Mux with integer 16bits divider. */
+#define CLK16_0(id, cn, pl, r, f) \
+ PER_CLK(id, cn, pl, r, 16, 0, (f) | DCF_HAVE_MUX | DCF_HAVE_DIV)
+/* Mux wihout divider. */
+#define CLK_0_0(id, cn, pl, r, f) \
+ PER_CLK(id, cn, pl, r, 0, 0, (f) | DCF_HAVE_MUX)
+
+static struct periph_def periph_def[] = {
+ CLK_8_1(0, "pc_i2s2", mux_a_N_audio1_N_p_N_clkm, CLK_SOURCE_I2S2, DCF_HAVE_ENA),
+ CLK_8_1(0, "pc_i2s3", mux_a_N_audio2_N_p_N_clkm, CLK_SOURCE_I2S3, DCF_HAVE_ENA),
+ CLK_8_1(0, "pc_spdif_out", mux_a_N_audio_N_p_N_clkm, CLK_SOURCE_SPDIF_OUT, 0),
+ CLK_8_1(0, "pc_spdif_in", mux_p_c2_c_c4_clkm_c4o1_c4o2, CLK_SOURCE_SPDIF_IN, 0),
+ CLK_8_1(0, "pc_pwm", mux_p_c2_c_c4_clks_c4o1_clkm_c4o2, CLK_SOURCE_PWM, 0),
+ CLK_8_1(0, "pc_spi2", mux_p_c2_c_c4_N_c4o1_clkm_c4o2, CLK_SOURCE_SPI2, 0),
+ CLK_8_1(0, "pc_spi3", mux_p_c2_c_c4_N_c4o1_clkm_c4o2, CLK_SOURCE_SPI3, 0),
+ CLK16_0(0, "pc_i2c1", mux_p_c2_c_c4_N_c4o1_clkm_c4o2, CLK_SOURCE_I2C1, 0),
+ CLK16_0(0, "pc_i2c5", mux_p_c2_c_c4_N_c4o1_clkm_c4o2, CLK_SOURCE_I2C5, 0),
+ CLK_8_1(0, "pc_spi1", mux_p_c2_c_c4_N_c4o1_clkm_c4o2, CLK_SOURCE_SPI1, 0),
+ CLK_0_0(0, "pc_disp1", mux_p_N_d_N_N_d2_clkm, CLK_SOURCE_DISP1, 0),
+ CLK_0_0(0, "pc_disp2", mux_p_N_d_N_N_d2_clkm, CLK_SOURCE_DISP2, 0),
+ CLK_8_1(0, "pc_isp", mux_N_c_p_a1_c2_c3_clkm_c4, CLK_SOURCE_ISP, 0),
+ CLK_8_1(0, "pc_vi", mux_N_c2_c_c3_p_clkm_a1_c4, CLK_SOURCE_VI, DCF_IS_VI),
+ CLK_8_1(0, "pc_sdmmc1", mux_p_N_N_c4o2_c4o1_N_clkm_c4, CLK_SOURCE_SDMMC1, 0),
+ CLK_8_1(0, "pc_sdmmc2", mux_p_N_N_c4o2_c4o1_N_clkm_c4, CLK_SOURCE_SDMMC2, 0),
+ CLK_8_1(0, "pc_sdmmc4", mux_p_N_N_c4o2_c4o1_N_clkm_c4, CLK_SOURCE_SDMMC4, 0),
+ CLK16_1(0, "pc_uarta", mux_p_c2_c_c4_c4o1_clkm_c4o2, CLK_SOURCE_UARTA, DCF_IS_UART),
+ CLK16_1(0, "pc_uartb", mux_p_c2_c_c4_N_c4o1_clkm_c4o2, CLK_SOURCE_UARTB, DCF_IS_UART),
+ CLK_8_1(0, "pc_host1x", mux_c4o1_c2_c_c4_p_clkm_a_c4, CLK_SOURCE_HOST1X, DCF_IS_HOST1X),
+ CLK16_0(0, "pc_i2c2", mux_p_c2_c_c4_N_c4o1_clkm_c4o2, CLK_SOURCE_I2C2, 0),
+ CLK_8_1(0, "pc_emc", mux_m_c_p_clkm_mud_mbud_mb_pud, CLK_SOURCE_EMC, DCF_IS_EMC),
+ CLK16_1(0, "pc_uartc", mux_p_c2_c_c4_c4o1_clkm_c4o2, CLK_SOURCE_UARTC, DCF_IS_UART),
+ CLK_8_1(0, "pc_vi_sensor", mux_N_c2_c_c3_p_N_a, CLK_SOURCE_VI_SENSOR, 0),
+ CLK_8_1(0, "pc_spi4", mux_p_c2_c_c4_N_c4o1_clkm_c4o2, CLK_SOURCE_SPI4, 0),
+ CLK16_0(0, "pc_i2c3", mux_p_c2_c_c4_N_c4o1_clkm_c4o2, CLK_SOURCE_I2C3, 0),
+ CLK_8_1(0, "pc_sdmmc3", mux_p_c2_c_c3_m_e_clkm, CLK_SOURCE_SDMMC3, 0),
+ CLK16_1(0, "pc_uartd", mux_p_c2_c_c4_c4o1_clkm_c4o2, CLK_SOURCE_UARTD, DCF_IS_UART),
+ CLK_8_1(0, "pc_csite", mux_p_c2_refe1_c3_m_a1_clkm_C4, CLK_SOURCE_CSITE, 0),
+ CLK_8_1(0, "pc_i2s1", mux_a_N_audio0_N_p_N_clkm, CLK_SOURCE_I2S1, 0),
+/* DTV xxx */
+ CLK_8_1(0, "pc_tsec", mux_p_c2_c_c3_N_a1_clkm_c4, CLK_SOURCE_TSEC, 0),
+/* SPARE2 */
+ CLK_8_1(0, "pc_mselect", mux_p_c2_c_c4o2_c4o1_clks_clkm_c4, CLK_SOURCE_MSELECT, 0),
+ CLK_8_1(0, "pc_tsensor", mux_p_c2_c_c4_clkm_c4o1_clks_c4o2, CLK_SOURCE_TSENSOR, 0),
+ CLK_8_1(0, "pc_i2s4", mux_a_N_audio3_N_p_N_clkm, CLK_SOURCE_I2S3, DCF_HAVE_ENA),
+ CLK_8_1(0, "pc_i2s5", mux_a_N_audio4_N_p_N_clkm, CLK_SOURCE_I2S4, DCF_HAVE_ENA),
+ CLK16_0(0, "pc_i2c4", mux_p_c2_c_c4_N_c4o1_clkm_c4o2, CLK_SOURCE_I2C4, 0),
+ CLK_8_1(0, "pc_ahub", mux_sep_audio, CLK_SOURCE_AHUB, DCF_IS_AHUB),
+ CLK_8_1(0, "pc_hda2codec_2x", mux_p_c2_c_c4_a_c4o1_clkm_c4o2, CLK_SOURCE_HDA2CODEC_2X, 0),
+ CLK_8_1(0, "pc_actmon", mux_p_c2_c_c4_clks_c4o1_clkm_c4o2, CLK_SOURCE_ACTMON, 0),
+ CLK_8_1(0, "pc_extperiph1", mux_a_clks_p_clkm_e, CLK_SOURCE_EXTPERIPH1, 0),
+ CLK_8_1(0, "pc_extperiph2", mux_a_clks_p_clkm_e, CLK_SOURCE_EXTPERIPH2, 0),
+ CLK_8_1(0, "pc_extperiph3", mux_a_clks_p_clkm_e, CLK_SOURCE_EXTPERIPH3, 0),
+ CLK_8_1(0, "pc_i2c_slow", mux_p_c2_c_c4_clks_c4o1_clkm_c4o2, CLK_SOURCE_I2C_SLOW, 0),
+/* SYS */
+ CLK_8_1(0, "pc_ispb", mux_N_N_c_N_p_N_a, CLK_SOURCE_ISPB, 0),
+ CLK_8_1(0, "pc_sor1", mux_p_N_d_N_N_d2_clkm, CLK_SOURCE_SOR1, DCF_IS_SOR0),
+ CLK_8_1(0, "pc_sor0", mux_p_m_d_a_c_d2_clkm, CLK_SOURCE_SOR0, DCF_IS_SOR0),
+ CLK_8_1(0, "pc_sata_oob", mux_p_c4_c_c4o1_N_c4o2_clkm, CLK_SOURCE_SATA_OOB, 0),
+ CLK_8_1(0, "pc_sata", mux_p_N_c_c4_N_c4o1_clkm_c4o2, CLK_SOURCE_SATA, DCF_IS_SATA),
+ CLK_8_1(0, "pc_hda", mux_p_c2_c_c4_N_c4o1_clkm_c4o2, CLK_SOURCE_HDA, 0),
+ CLK_8_1(TEGRA210_CLK_XUSB_HOST_SRC,
+ "pc_xusb_core_host", mux_clkm_p_N_N_N_refre, CLK_SOURCE_XUSB_CORE_HOST, 0),
+ CLK_8_1(TEGRA210_CLK_XUSB_FALCON_SRC,
+ "pc_xusb_falcon", mux_clkm_p_N_N_N_refre, CLK_SOURCE_XUSB_FALCON, 0),
+ CLK_8_1(TEGRA210_CLK_XUSB_FS_SRC,
+ "pc_xusb_fs", mux_clkm_N_u48_N_p_N_u480, CLK_SOURCE_XUSB_FS, 0),
+ CLK_8_1(TEGRA210_CLK_XUSB_DEV_SRC,
+ "pc_xusb_core_dev", mux_clkm_p_N_N_N_refre, CLK_SOURCE_XUSB_CORE_DEV, 0),
+ CLK_8_1(TEGRA210_CLK_XUSB_SS_SRC,
+ "pc_xusb_ss", mux_clkm_refe_clks_u480, CLK_SOURCE_XUSB_SS, DCF_IS_XUSB_SS),
+ CLK_8_1(0, "pc_cilab", mux_p_N_c_c4_c4o1_c4o2_clkm, CLK_SOURCE_CILAB, 0),
+ CLK_8_1(0, "pc_cilcd", mux_p_N_c_c4_c4o1_c4o2_clkm, CLK_SOURCE_CILCD, 0),
+ CLK_8_1(0, "pc_cilef", mux_p_N_c_c4_c4o1_c4o2_clkm, CLK_SOURCE_CILEF, 0),
+ CLK_8_1(0, "pc_dsia_lp", mux_p_N_c_c4_c4o1_c4o2_clkm, CLK_SOURCE_DSIA_LP, 0),
+ CLK_8_1(0, "pc_dsib_lp", mux_p_N_c_c4_c4o1_c4o2_clkm, CLK_SOURCE_DSIB_LP, 0),
+ CLK_8_1(0, "pc_entropy", mux_p_N_clkm_N_clks_N_E, CLK_SOURCE_ENTROPY, 0),
+ CLK_8_1(0, "pc_dvfs_ref", mux_p_c2_c_c4_N_c4o1_clkm_c4o2, CLK_SOURCE_DVFS_REF, DCF_HAVE_ENA),
+ CLK_8_1(0, "pc_dvfs_soc", mux_p_c2_c_c4_N_c4o1_clkm_c4o2, CLK_SOURCE_DVFS_SOC, DCF_HAVE_ENA),
+ CLK_8_1(0, "pc_emc_latency", mux_N_c_p_clkm_N_c4_c4o1_c4o2, CLK_SOURCE_EMC_LATENCY, 0),
+ CLK_8_1(0, "pc_soc_therm", mux_N_c_p_clkm_N_c4_c4o1_c4o1, CLK_SOURCE_SOC_THERM, 0),
+ CLK_8_1(0, "pc_dmic1", mux_a_audiod1_p_clkm, CLK_SOURCE_DMIC1, 0),
+ CLK_8_1(0, "pc_dmic2", mux_a_audiod2_p_clkm, CLK_SOURCE_DMIC2, 0),
+ CLK_8_1(0, "pc_vi_sensor2", mux_N_c2_c_c3_p_N_a, CLK_SOURCE_VI_SENSOR2, 0),
+ CLK16_0(0, "pc_i2c6", mux_p_c2_c_c4_N_c4o1_clkm_c4o2, CLK_SOURCE_I2C6, 0),
+/* MIPIBIF */
+ CLK_8_1(0, "pc_emc_dll", mux_m_c_p_clkm_mud_mbud_mb_pud, CLK_SOURCE_EMC_DLL, DCF_IS_EMC_DLL),
+ CLK_8_1(0, "pc_uart_fst_mipi_cal", mux_p_c_c2_N_c2_N_clkm, CLK_SOURCE_UART_FST_MIPI_CAL, 0),
+ CLK_8_1(0, "pc_vic", mux_N_c_p_a1_c2_c3_clkm, CLK_SOURCE_VIC, DCF_IS_VIC),
+
+ CLK_8_1(0, "pc_sdmmc_legacy_tm", mux_po3_c_c2_clkm_p_c4_c4o1_c4o2, CLK_SOURCE_SDMMC_LEGACY_TM, 0),
+ CLK_8_1(0, "pc_nvdec", mux_N_c2_c_c3_p_N_a1_clkm, CLK_SOURCE_NVDEC, 0),
+ CLK_8_1(0, "pc_nvjpg", mux_N_c2_c_c3_p_N_a1_clkm, CLK_SOURCE_NVJPG, 0),
+ CLK_8_1(0, "pc_nvenc", mux_N_c2_c_c3_p_N_a1_clkm, CLK_SOURCE_NVENC, 0),
+ CLK_8_1(0, "pc_dmic3", mux_a_audiod3_p_clkm, CLK_SOURCE_DMIC3, 0),
+ CLK_8_1(0, "pc_ape", mux_a_c4_c_c4o1_p_N_clkm_c4o2, CLK_SOURCE_APE, 0),
+ CLK_8_1(0, "pc_qspi", mux_p_co1_c_N_c4o2_c4o1_clkm_c4, CLK_SOURCE_QSPI, DCF_IS_QSPI),
+ CLK_8_1(0, "pc_vi_i2c", mux_p_c2_c_c3_N_N_clkm, CLK_SOURCE_VI_I2C, 0),
+/* USB2_HSIC_TRK */
+ CLK_8_0(0, "pc_maud", mux_p_po3_clkm_clks_a, CLK_SOURCE_MAUD, 0),
+ CLK_8_1(0, "pc_tsecb", mux_p_c2_c_c3_N_a1_clkm_c4, CLK_SOURCE_TSECB, 0),
+ CLK_8_1(0, "pc_uartape", mux_p_c2_c_c3_N_N_clkm, CLK_SOURCE_UARTAPE, 0),
+ CLK_8_1(0, "pc_dbgapb", mux_N_N_p_N_N_N_clkm, CLK_SOURCE_DBGAPB, 0),
+ CLK_8_1(0, "pc_emc_safe", mux_m_c_p_clkm_mud_mbud_mb_pud, CLK_SOURCE_EMC_SAFE, DCF_IS_EMC_SAFE),
+};
+
+static int periph_init(struct clknode *clk, device_t dev);
+static int periph_recalc(struct clknode *clk, uint64_t *freq);
+static int periph_set_freq(struct clknode *clk, uint64_t fin,
+ uint64_t *fout, int flags, int *stop);
+static int periph_set_mux(struct clknode *clk, int idx);
+
+struct periph_sc {
+ device_t clkdev;
+ uint32_t base_reg;
+ uint32_t div_shift;
+ uint32_t div_width;
+ uint32_t div_mask;
+ uint32_t div_f_width;
+ uint32_t div_f_mask;
+ uint32_t flags;
+
+ uint32_t divider;
+ int mux;
+};
+
+static clknode_method_t periph_methods[] = {
+ /* Device interface */
+ CLKNODEMETHOD(clknode_init, periph_init),
+ CLKNODEMETHOD(clknode_recalc_freq, periph_recalc),
+ CLKNODEMETHOD(clknode_set_freq, periph_set_freq),
+ CLKNODEMETHOD(clknode_set_mux, periph_set_mux),
+ CLKNODEMETHOD_END
+};
+DEFINE_CLASS_1(tegra210_periph, tegra210_periph_class, periph_methods,
+ sizeof(struct periph_sc), clknode_class);
+
+static int
+periph_init(struct clknode *clk, device_t dev)
+{
+ struct periph_sc *sc;
+ uint32_t reg;
+ sc = clknode_get_softc(clk);
+
+ DEVICE_LOCK(sc);
+ if (sc->flags & DCF_HAVE_ENA)
+ MD4(sc, sc->base_reg, PERLCK_ENA_MASK, PERLCK_ENA_MASK);
+
+ RD4(sc, sc->base_reg, &reg);
+ DEVICE_UNLOCK(sc);
+
+ /* Stnadard mux. */
+ if (sc->flags & DCF_HAVE_MUX)
+ sc->mux = (reg >> PERLCK_MUX_SHIFT) & PERLCK_MUX_MASK;
+ else
+ sc->mux = 0;
+ if (sc->flags & DCF_HAVE_DIV)
+ sc->divider = (reg & sc->div_mask) + 2;
+ else
+ sc->divider = 1;
+ if ((sc->flags & DCF_IS_MASK) == DCF_IS_UART) {
+ if (!(reg & PERLCK_UDIV_DIS))
+ sc->divider = 2;
+ }
+
+ /* AUDIO MUX */
+ if ((sc->flags & DCF_IS_MASK) == DCF_IS_AHUB) {
+ if (!(reg & PERLCK_AMUX_DIS) && (sc->mux == 7)) {
+ sc->mux = 8 +
+ ((reg >> PERLCK_AMUX_SHIFT) & PERLCK_MUX_MASK);
+ }
+ }
+ clknode_init_parent_idx(clk, sc->mux);
+ return(0);
+}
+
+static int
+periph_set_mux(struct clknode *clk, int idx)
+{
+ struct periph_sc *sc;
+ uint32_t reg;
+
+
+ sc = clknode_get_softc(clk);
+ if (!(sc->flags & DCF_HAVE_MUX))
+ return (ENXIO);
+
+ sc->mux = idx;
+ DEVICE_LOCK(sc);
+ RD4(sc, sc->base_reg, &reg);
+ reg &= ~(PERLCK_MUX_MASK << PERLCK_MUX_SHIFT);
+ if ((sc->flags & DCF_IS_MASK) == DCF_IS_AHUB) {
+ reg &= ~PERLCK_AMUX_DIS;
+ reg &= ~(PERLCK_MUX_MASK << PERLCK_AMUX_SHIFT);
+
+ if (idx <= 7) {
+ reg |= idx << PERLCK_MUX_SHIFT;
+ } else {
+ reg |= 7 << PERLCK_MUX_SHIFT;
+ reg |= (idx - 8) << PERLCK_AMUX_SHIFT;
+ }
+ } else {
+ reg |= idx << PERLCK_MUX_SHIFT;
+ }
+ WR4(sc, sc->base_reg, reg);
+ DEVICE_UNLOCK(sc);
+
+ return(0);
+}
+
+static int
+periph_recalc(struct clknode *clk, uint64_t *freq)
+{
+ struct periph_sc *sc;
+ uint32_t reg;
+
+ sc = clknode_get_softc(clk);
+
+ if (sc->flags & DCF_HAVE_DIV) {
+ DEVICE_LOCK(sc);
+ RD4(sc, sc->base_reg, &reg);
+ DEVICE_UNLOCK(sc);
+ *freq = (*freq << sc->div_f_width) / sc->divider;
+ }
+ return (0);
+}
+
+static int
+periph_set_freq(struct clknode *clk, uint64_t fin, uint64_t *fout,
+ int flags, int *stop)
+{
+ struct periph_sc *sc;
+ uint64_t tmp, divider;
+
+ sc = clknode_get_softc(clk);
+ if (!(sc->flags & DCF_HAVE_DIV)) {
+ *stop = 0;
+ return (0);
+ }
+
+ tmp = fin << sc->div_f_width;
+ divider = tmp / *fout;
+ if ((tmp % *fout) != 0)
+ divider++;
+
+ if (divider < (1 << sc->div_f_width))
+ divider = 1 << (sc->div_f_width - 1);
+
+ if (flags & CLK_SET_DRYRUN) {
+ if (((flags & (CLK_SET_ROUND_UP | CLK_SET_ROUND_DOWN)) == 0) &&
+ (*fout != (tmp / divider)))
+ return (ERANGE);
+ } else {
+ DEVICE_LOCK(sc);
+ MD4(sc, sc->base_reg, sc->div_mask,
+ (divider - (1 << sc->div_f_width)));
+ DEVICE_UNLOCK(sc);
+ sc->divider = divider;
+ }
+ *fout = tmp / divider;
+ *stop = 1;
+ return (0);
+}
+
+static int
+periph_register(struct clkdom *clkdom, struct periph_def *clkdef)
+{
+ struct clknode *clk;
+ struct periph_sc *sc;
+
+ clk = clknode_create(clkdom, &tegra210_periph_class, &clkdef->clkdef);
+ if (clk == NULL)
+ return (1);
+
+ sc = clknode_get_softc(clk);
+ sc->clkdev = clknode_get_device(clk);
+ sc->base_reg = clkdef->base_reg;
+ sc->div_width = clkdef->div_width;
+ sc->div_mask = (1 <<clkdef->div_width) - 1;
+ sc->div_f_width = clkdef->div_f_width;
+ sc->div_f_mask = (1 <<clkdef->div_f_width) - 1;
+ sc->flags = clkdef->flags;
+
+ clknode_register(clkdom, clk);
+ return (0);
+}
+
+/* -------------------------------------------------------------------------- */
+static int pgate_init(struct clknode *clk, device_t dev);
+static int pgate_set_gate(struct clknode *clk, bool enable);
+
+struct pgate_sc {
+ device_t clkdev;
+ uint32_t idx;
+ uint32_t flags;
+ uint32_t enabled;
+
+};
+
+static clknode_method_t pgate_methods[] = {
+ /* Device interface */
+ CLKNODEMETHOD(clknode_init, pgate_init),
+ CLKNODEMETHOD(clknode_set_gate, pgate_set_gate),
+ CLKNODEMETHOD_END
+};
+DEFINE_CLASS_1(tegra210_pgate, tegra210_pgate_class, pgate_methods,
+ sizeof(struct pgate_sc), clknode_class);
+
+static uint32_t
+get_enable_reg(int idx)
+{
+ KASSERT(idx / 32 < nitems(clk_enable_reg),
+ ("Invalid clock index for enable: %d", idx));
+ return (clk_enable_reg[idx / 32]);
+}
+
+static uint32_t
+get_reset_reg(int idx)
+{
+ KASSERT(idx / 32 < nitems(clk_reset_reg),
+ ("Invalid clock index for reset: %d", idx));
+ return (clk_reset_reg[idx / 32]);
+}
+
+static int
+pgate_init(struct clknode *clk, device_t dev)
+{
+ struct pgate_sc *sc;
+ uint32_t ena_reg, rst_reg, mask;
+
+ sc = clknode_get_softc(clk);
+ mask = 1 << (sc->idx % 32);
+
+ DEVICE_LOCK(sc);
+ RD4(sc, get_enable_reg(sc->idx), &ena_reg);
+ RD4(sc, get_reset_reg(sc->idx), &rst_reg);
+ DEVICE_UNLOCK(sc);
+
+ sc->enabled = ena_reg & mask ? 1 : 0;
+ clknode_init_parent_idx(clk, 0);
+
+ return(0);
+}
+
+static int
+pgate_set_gate(struct clknode *clk, bool enable)
+{
+ struct pgate_sc *sc;
+ uint32_t reg, mask, base_reg;
+
+ sc = clknode_get_softc(clk);
+ mask = 1 << (sc->idx % 32);
+ sc->enabled = enable;
+ base_reg = get_enable_reg(sc->idx);
+
+ DEVICE_LOCK(sc);
+ MD4(sc, base_reg, mask, enable ? mask : 0);
+ RD4(sc, base_reg, &reg);
+ DEVICE_UNLOCK(sc);
+
+ DELAY(2);
+ return(0);
+}
+
+int
+tegra210_hwreset_by_idx(struct tegra210_car_softc *sc, intptr_t idx, bool reset)
+{
+ uint32_t reg, mask, reset_reg;
+
+ CLKDEV_DEVICE_LOCK(sc->dev);
+ if (idx == TEGRA210_RST_DFLL_DVCO) {
+ CLKDEV_MODIFY_4(sc->dev, DFLL_BASE, DFLL_BASE_DVFS_DFLL_RESET,
+ reset ? DFLL_BASE_DVFS_DFLL_RESET : 0);
+ CLKDEV_READ_4(sc->dev, DFLL_BASE, &reg);
+ }
+ if (idx == TEGRA210_RST_ADSP) {
+ reset_reg = (reset) ? RST_DEV_Y_SET: RST_DEV_Y_CLR;
+ mask = (0x1F << 22) |(1 << 7);
+ CLKDEV_WRITE_4(sc->dev, reset_reg, mask);
+ CLKDEV_READ_4(sc->dev, reset_reg, &reg);
+ } else {
+ mask = 1 << (idx % 32);
+ reset_reg = get_reset_reg(idx);
+
+ CLKDEV_MODIFY_4(sc->dev, reset_reg, mask, reset ? mask : 0);
+ CLKDEV_READ_4(sc->dev, reset_reg, &reg);
+ }
+ CLKDEV_DEVICE_UNLOCK(sc->dev);
+
+ return(0);
+}
+
+static int
+pgate_register(struct clkdom *clkdom, struct pgate_def *clkdef)
+{
+ struct clknode *clk;
+ struct pgate_sc *sc;
+
+ clk = clknode_create(clkdom, &tegra210_pgate_class, &clkdef->clkdef);
+ if (clk == NULL)
+ return (1);
+
+ sc = clknode_get_softc(clk);
+ sc->clkdev = clknode_get_device(clk);
+ sc->idx = clkdef->idx;
+ sc->flags = clkdef->flags;
+
+ clknode_register(clkdom, clk);
+ return (0);
+}
+
+void
+tegra210_periph_clock(struct tegra210_car_softc *sc)
+{
+ int i, rv;
+
+ for (i = 0; i < nitems(periph_def); i++) {
+ rv = periph_register(sc->clkdom, &periph_def[i]);
+ if (rv != 0)
+ panic("tegra210_periph_register failed");
+ }
+ for (i = 0; i < nitems(pgate_def); i++) {
+ rv = pgate_register(sc->clkdom, &pgate_def[i]);
+ if (rv != 0)
+ panic("tegra210_pgate_register failed");
+ }
+
+}
diff --git a/sys/arm64/nvidia/tegra210/tegra210_clk_pll.c b/sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
new file mode 100644
index 000000000000..88c3916f4eae
--- /dev/null
+++ b/sys/arm64/nvidia/tegra210/tegra210_clk_pll.c
@@ -0,0 +1,1494 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
+ *
+ * Copyright 2020 Michal Meloun <mmel@FreeBSD.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+#include <sys/rman.h>
+
+#include <machine/bus.h>
+
+#include <dev/extres/clk/clk_div.h>
+#include <dev/extres/clk/clk_fixed.h>
+#include <dev/extres/clk/clk_gate.h>
+#include <dev/extres/clk/clk_mux.h>
+
+#include <gnu/dts/include/dt-bindings/clock/tegra210-car.h>
+#include "tegra210_car.h"
+
+#if 0
+#define dprintf(...) printf(__VA_ARGS__)
+#else
+#define dprintf(...)
+#endif
+
+/* All PLLs. */
+enum pll_type {
+ PLL_M,
+ PLL_MB,
+ PLL_X,
+ PLL_C,
+ PLL_C2,
+ PLL_C3,
+ PLL_C4,
+ PLL_P,
+ PLL_A,
+ PLL_A1,
+ PLL_U,
+ PLL_D,
+ PLL_D2,
+ PLL_DP,
+ PLL_E,
+ PLL_REFE};
+/* Flags for PLLs */
+
+#define PLL_FLAG_PDIV_POWER2 0x01 /* P Divider is 2^n */
+#define PLL_FLAG_VCO_OUT 0x02 /* Output VCO directly */
+#define PLL_FLAG_HAVE_SDM 0x04 /* Have SDM implemented */
+#define PLL_FLAG_HAVE_SDA 0x04 /* Have SDA implemented */
+
+/* Common base register bits. */
+#define PLL_BASE_BYPASS (1U << 31)
+#define PLL_BASE_ENABLE (1 << 30)
+#define PLL_BASE_REFDISABLE (1 << 29)
+#define PLL_BASE_LOCK (1 << 27)
+
+#define PLLREFE_MISC_LOCK (1 << 27)
+
+#define PLL_MISC_LOCK_ENABLE (1 << 18)
+#define PLLM_LOCK_ENABLE (1 << 4)
+#define PLLMB_LOCK_ENABLE (1 << 16)
+#define PLLC_LOCK_ENABLE (1 << 24)
+#define PLLC4_LOCK_ENABLE (1 << 30)
+#define PLLA_LOCK_ENABLE (1 << 28)
+#define PLLD2_LOCK_ENABLE (1 << 30)
+#define PLLU_LOCK_ENABLE (1 << 29)
+#define PLLREFE_LOCK_ENABLE (1 << 30)
+#define PLLPD_LOCK_ENABLE (1 << 30)
+#define PLLE_LOCK_ENABLE (1 << 9)
+
+#define PLLM_IDDQ_BIT 5
+#define PLLMB_IDDQ_BIT 17
+#define PLLC_IDDQ_BIT 27
+#define PLLC4_IDDQ_BIT 18
+#define PLLP_IDDQ_BIT 3
+#define PLLA_IDDQ_BIT 25
+#define PLLA1_IDDQ_BIT 27
+#define PLLU_IDDQ_BIT 31
+#define PLLD_IDDQ_BIT 20
+#define PLLD2_IDDQ_BIT 18
+#define PLLX_IDDQ_BIT 3
+#define PLLREFE_IDDQ_BIT 24
+#define PLLDP_IDDQ_BIT 18
+
+
+#define PLL_LOCK_TIMEOUT 5000
+
+/* Post divider <-> register value mapping. */
+struct pdiv_table {
+ uint32_t divider; /* real divider */
+ uint32_t value; /* register value */
+};
+
+/* Bits definition of M, N and P fields. */
+struct mnp_bits {
+ uint32_t m_width;
+ uint32_t n_width;
+ uint32_t p_width;
+ uint32_t m_shift;
+ uint32_t n_shift;
+ uint32_t p_shift;
+};
+
+struct clk_pll_def {
+ struct clknode_init_def clkdef;
+ enum pll_type type;
+ uint32_t base_reg;
+ uint32_t misc_reg;
+ uint32_t lock_enable;
+ uint32_t iddq_reg;
+ uint32_t iddq_mask;
+ uint32_t flags;
+ struct pdiv_table *pdiv_table;
+ struct mnp_bits mnp_bits;
+};
+
+#define PLIST(x) static const char *x[]
+
+#define PLL(_id, cname, pname) \
+ .clkdef.id = _id, \
+ .clkdef.name = cname, \
+ .clkdef.parent_names = (const char *[]){pname}, \
+ .clkdef.parent_cnt = 1, \
+ .clkdef.flags = CLK_NODE_STATIC_STRINGS
+
+/* multiplexer for pll sources. */
+#define MUX(_id, cname, plists, o, s, w) \
+{ \
+ .clkdef.id = _id, \
+ .clkdef.name = cname, \
+ .clkdef.parent_names = plists, \
+ .clkdef.parent_cnt = nitems(plists), \
+ .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
+ .offset = o, \
+ .shift = s, \
+ .width = w, \
+}
+
+/* Fractional divider (7.1) for PLL branch. */
+#define DIV7_1(_id, cname, plist, o, s) \
+{ \
+ .clkdef.id = _id, \
+ .clkdef.name = cname, \
+ .clkdef.parent_names = (const char *[]){plist}, \
+ .clkdef.parent_cnt = 1, \
+ .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
+ .offset = o, \
+ .i_shift = (s) + 1, \
+ .i_width = 7, \
+ .f_shift = s, \
+ .f_width = 1, \
+}
+
+/* P divider (2^n). for PLL branch. */
+#define DIV5_E(_id, cname, plist, o, s) \
+{ \
+ .clkdef.id = _id, \
+ .clkdef.name = cname, \
+ .clkdef.parent_names = (const char *[]){plist}, \
+ .clkdef.parent_cnt = 1, \
+ .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
+ .offset = o, \
+ .i_shift = s, \
+ .i_width = 5, \
+}
+
+/* P divider (2^n). for PLL branch. */
+#define DIV_TB(_id, cname, plist, o, s, n, table) \
+{ \
+ .clkdef.id = _id, \
+ .clkdef.name = cname, \
+ .clkdef.parent_names = (const char *[]){plist}, \
+ .clkdef.parent_cnt = 1, \
+ .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
+ .div_flags = CLK_DIV_WITH_TABLE | CLK_DIV_ZERO_BASED, \
+ .offset = o, \
+ .i_shift = s, \
+ .i_width = n, \
+ .div_table = table, \
+}
+
+/* Standard gate. */
+#define GATE(_id, cname, plist, o, s) \
+{ \
+ .clkdef.id = _id, \
+ .clkdef.name = cname, \
+ .clkdef.parent_names = (const char *[]){plist}, \
+ .clkdef.parent_cnt = 1, \
+ .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
+ .offset = o, \
+ .shift = s, \
+ .mask = 1, \
+ .on_value = 1, \
+ .off_value = 0, \
+}
+/* Gate for PLL branch. */
+#define GATE_PLL(_id, cname, plist, o, s) \
+{ \
+ .clkdef.id = _id, \
+ .clkdef.name = cname, \
+ .clkdef.parent_names = (const char *[]){plist}, \
+ .clkdef.parent_cnt = 1, \
+ .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
+ .offset = o, \
+ .shift = s, \
+ .mask = 3, \
+ .on_value = 3, \
+ .off_value = 0, \
+}
+
+/* Fixed rate multipier/divider. */
+#define FACT(_id, cname, pname, _mult, _div) \
+{ \
+ .clkdef.id = _id, \
+ .clkdef.name = cname, \
+ .clkdef.parent_names = (const char *[]){pname}, \
+ .clkdef.parent_cnt = 1, \
+ .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
+ .mult = _mult, \
+ .div = _div, \
+}
+
+static struct pdiv_table qlin_map[] = {
+ { 1, 0},
+ { 2, 1},
+ { 3, 2},
+ { 4, 3},
+ { 5, 4},
+ { 6, 5},
+ { 8, 6},
+ { 9, 7},
+ {10, 8},
+ {12, 9},
+ {15, 10},
+ {16, 11},
+ {18, 12},
+ {20, 13},
+ {24, 14},
+ {30, 15},
+ {32, 16},
+ { 0, 0},
+};
+
+static struct clk_pll_def pll_clks[] = {
+/* PLLM: 880 MHz Clock source for EMC 2x clock */
+ {
+ PLL(TEGRA210_CLK_PLL_M, "pllM_out0", "osc"),
+ .type = PLL_M,
+ .base_reg = PLLM_BASE,
+ .misc_reg = PLLM_MISC2,
+ .lock_enable = PLLM_LOCK_ENABLE,
+ .iddq_reg = PLLM_MISC2,
+ .iddq_mask = 1 << PLLM_IDDQ_BIT,
+ .pdiv_table = qlin_map,
+ .mnp_bits = {8, 8, 5, 0, 8, 20},
+ },
+/* PLLMB: 880 MHz Clock source for EMC 2x clock */
+ {
+ PLL(TEGRA210_CLK_PLL_M, "pllMB_out0", "osc"),
+ .type = PLL_MB,
+ .base_reg = PLLMB_BASE,
+ .misc_reg = PLLMB_MISC1,
+ .lock_enable = PLLMB_LOCK_ENABLE,
+ .iddq_reg = PLLMB_MISC1,
+ .iddq_mask = 1 << PLLMB_IDDQ_BIT,
+ .pdiv_table = qlin_map,
+ .mnp_bits = {8, 8, 5, 0, 8, 20},
+ },
+/* PLLX: 1GHz Clock source for the fast CPU cluster and the shadow CPU */
+ {
+ PLL(TEGRA210_CLK_PLL_X, "pllX_out0", "osc_div_clk"),
+ .type = PLL_X,
+ .base_reg = PLLX_BASE,
+ .misc_reg = PLLX_MISC,
+ .lock_enable = PLL_MISC_LOCK_ENABLE,
+ .iddq_reg = PLLX_MISC_3,
+ .iddq_mask = 1 << PLLX_IDDQ_BIT,
+ .pdiv_table = qlin_map,
+ .mnp_bits = {8, 8, 5, 0, 8, 20},
+ },
+/* PLLC: 510 MHz Clock source for camera use */
+ {
+ PLL(TEGRA210_CLK_PLL_C, "pllC_out0", "osc_div_clk"),
+ .type = PLL_C,
+ .base_reg = PLLC_BASE,
+ .misc_reg = PLLC_MISC_0,
+ .iddq_reg = PLLC_MISC_1,
+ .iddq_mask = 1 << PLLC_IDDQ_BIT,
+ .pdiv_table = qlin_map,
+ .mnp_bits = {8, 8, 5, 0, 10, 20},
+ },
+/* PLLC2: 510 MHz Clock source for SE, VIC, TSECB, NVJPG scaling */
+ {
+ PLL(TEGRA210_CLK_PLL_C2, "pllC2_out0", "osc_div_clk"),
+ .type = PLL_C2,
+ .base_reg = PLLC2_BASE,
+ .misc_reg = PLLC2_MISC_0,
+ .iddq_reg = PLLC2_MISC_1,
+ .iddq_mask = 1 << PLLC_IDDQ_BIT,
+ .pdiv_table = qlin_map,
+ .mnp_bits = {8, 8, 5, 0, 10, 20},
+ },
+/* PLLC3: 510 MHz Clock source for NVENC, NVDEC scaling */
+ {
+ PLL(TEGRA210_CLK_PLL_C3, "pllC3_out0", "osc_div_clk"),
+ .type = PLL_C3,
+ .base_reg = PLLC3_BASE,
+ .misc_reg = PLLC3_MISC_0,
+ .lock_enable = PLL_MISC_LOCK_ENABLE,
+ .iddq_reg = PLLC3_MISC_1,
+ .iddq_mask = 1 << PLLC_IDDQ_BIT,
+ .mnp_bits = {8, 8, 5, 0, 10, 20},
+ },
+/* PLLC4: 600 MHz Clock source for SD/eMMC ans system busses */
+ {
+ PLL(TEGRA210_CLK_PLL_C4, "pllC4", "pllC4_src"),
+ .type = PLL_C4,
+ .flags = PLL_FLAG_VCO_OUT,
+ .base_reg = PLLC4_BASE,
+ .misc_reg = PLLC4_MISC,
+ .lock_enable = PLLC4_LOCK_ENABLE,
+ .iddq_reg = PLLC4_BASE,
+ .iddq_mask = 1 << PLLC4_IDDQ_BIT,
+ .pdiv_table = qlin_map,
+ .mnp_bits = {8, 8, 5, 0, 8, 19},
+ },
+/* PLLP: 408 MHz Clock source for most peripherals */
+ {
+ /*
+ * VCO is directly exposed as pllP_out0, P div is used for
+ * pllP_out2
+ */
+ PLL(TEGRA210_CLK_PLL_P, "pllP_out0", "osc_div_clk"),
+ .type = PLL_P,
+ .flags = PLL_FLAG_VCO_OUT,
+ .base_reg = PLLP_BASE,
+ .misc_reg = PLLP_MISC,
+ .lock_enable = PLL_MISC_LOCK_ENABLE,
+ .iddq_reg = PLLP_MISC,
+ .iddq_mask = 1 << PLLA_IDDQ_BIT,
+ .mnp_bits = {8, 8, 5, 0, 10, 20},
+ },
+/* PLLA: Audio clock for precise codec sampling */
+ {
+ PLL(TEGRA210_CLK_PLL_A, "pllA", "osc_div_clk"),
+ .type = PLL_A,
+ .base_reg = PLLA_BASE,
+ .misc_reg = PLLA_MISC,
+ .lock_enable = PLLA_LOCK_ENABLE,
+ .iddq_reg = PLLA_BASE,
+ .iddq_mask = 1 << PLLA_IDDQ_BIT,
+ .pdiv_table = qlin_map,
+ .mnp_bits = {8, 8, 5, 0, 8, 20},
+ },
+/* PLLA1: Audio clock for ADSP */
+ {
+ PLL(TEGRA210_CLK_PLL_A1, "pllA1_out0", "osc_div_clk"),
+ .type = PLL_A1,
+ .base_reg = PLLA1_BASE,
+ .misc_reg = PLLA1_MISC_1,
+ .iddq_reg = PLLA1_MISC_1,
+ .iddq_mask = 1 << PLLA_IDDQ_BIT,
+ .pdiv_table = qlin_map,
+ .mnp_bits = {8, 8, 5, 0, 8, 20},
+ },
+/* PLLU: 480 MHz Clock source for USB PHY, provides 12/60/480 MHz */
+ {
+ PLL(TEGRA210_CLK_PLL_U, "pllU", "osc_div_clk"),
+ .type = PLL_U,
+ .flags = PLL_FLAG_VCO_OUT | PLL_FLAG_HAVE_SDA,
+ .base_reg = PLLU_BASE,
+ .misc_reg = PLLU_MISC,
+ .lock_enable = PLLU_LOCK_ENABLE,
+ .iddq_reg = PLLU_MISC,
+ .iddq_mask = 1 << PLLU_IDDQ_BIT,
+ .pdiv_table = qlin_map,
+ .mnp_bits = {8, 8, 5, 0, 8, 16},
+ },
+/* PLLD: 594 MHz Clock sources for the DSI and display subsystem */
+ {
+ PLL(TEGRA210_CLK_PLL_D, "pllD_out", "osc_div_clk"),
+ .type = PLL_D,
+ .flags = PLL_FLAG_PDIV_POWER2,
+ .base_reg = PLLD_BASE,
+ .misc_reg = PLLD_MISC,
+ .lock_enable = PLL_MISC_LOCK_ENABLE,
+ .iddq_reg = PLLA1_MISC_1,
+ .iddq_mask = 1 << PLLA_IDDQ_BIT,
+ .mnp_bits = {8, 8, 3, 0, 11, 20},
+ },
+/* PLLD2: 594 MHz Clock sources for the DSI and display subsystem */
+ {
+ PLL(TEGRA210_CLK_PLL_D2, "pllD2_out", "pllD2_src"),
+ .type = PLL_D2,
+ .flags = PLL_FLAG_HAVE_SDM,
+ .base_reg = PLLD2_BASE,
+ .misc_reg = PLLD2_MISC,
+ .lock_enable = PLLD2_LOCK_ENABLE,
+ .iddq_reg = PLLD2_BASE,
+ .iddq_mask = 1 << PLLD_IDDQ_BIT,
+ .pdiv_table = qlin_map,
+ .mnp_bits = {8, 8, 5, 0, 8, 19},
+ },
+/* PLLREFE: 624 Mhz*/
+ {
+ PLL(0, "pllREFE", "osc_div_clk"),
+ .type = PLL_REFE,
+ .flags = PLL_FLAG_VCO_OUT,
+ .base_reg = PLLREFE_BASE,
+ .misc_reg = PLLREFE_MISC,
+ .lock_enable = PLLREFE_LOCK_ENABLE,
+ .iddq_reg = PLLREFE_MISC,
+ .iddq_mask = 1 << PLLREFE_IDDQ_BIT,
+ .pdiv_table = qlin_map,
+ .mnp_bits = {8, 8, 5, 0, 8, 16},
+ },
+/* PLLE: 100 MHz reference clock for PCIe/SATA/USB 3.0 (spread spectrum) */
+ {
+ PLL(TEGRA210_CLK_PLL_E, "pllE_out0", "pllE_src"),
+ .type = PLL_E,
+ .base_reg = PLLE_BASE,
+ .misc_reg = PLLE_MISC,
+ .lock_enable = PLLE_LOCK_ENABLE,
+ .pdiv_table = qlin_map,
+ .mnp_bits = {8, 8, 5, 0, 8, 24},
+ },
+/* PLLDP: 270 MHz Clock source fordisplay SOR (spread spectrum) */
+ {
+ PLL(0, "pllDP_out0", "pllDP_src"),
+ .type = PLL_DP,
+ .flags = PLL_FLAG_HAVE_SDM,
+ .base_reg = PLLDP_BASE,
+ .misc_reg = PLLDP_MISC,
+ .lock_enable = PLLPD_LOCK_ENABLE,
+ .iddq_reg = PLLDP_BASE,
+ .iddq_mask = 1 << PLLDP_IDDQ_BIT,
+ .pdiv_table = qlin_map,
+ .mnp_bits = {8, 8, 5, 0, 8, 19},
+ },
+};
+
+/* Fixed rate dividers. */
+static struct clk_fixed_def tegra210_pll_fdivs[] = {
+ FACT(0, "pllP_UD", "pllP_out0", 1, 1),
+ FACT(0, "pllC_UD", "pllC_out0", 1, 1),
+ FACT(0, "pllD_UD", "pllD_out0", 1, 1),
+ FACT(0, "pllM_UD", "pllM_out0", 1, 1),
+ FACT(0, "pllMB_UD", "pllMB_out0", 1, 1),
+ FACT(TEGRA210_CLK_PLL_D_OUT0, "pllD_out0", "pllD_out", 1, 2),
+
+ FACT(0, "pllC4_out1", "pllC4", 1, 3),
+ FACT(0, "pllC4_out2", "pllC4", 1, 5),
+ FACT(0, "pllD2_out0", "pllD2_out", 1, 2),
+
+ /* Aliases used in super mux. */
+ FACT(0, "pllX_out0_alias", "pllX_out0", 1, 1),
+ FACT(0, "dfllCPU_out_alias", "dfllCPU_out", 1, 1),
+};
+
+/* MUXes for PLL sources. */
+PLIST(mux_pll_srcs) = {"osc_div_clk", NULL, "pllP_out0", NULL}; /* FIXME */
+PLIST(mux_plle_src1) = {"osc_div_clk", "pllP_out0"};
+PLIST(mux_plle_src) = {"pllE_src1", "pllREFE_out0"};
+static struct clk_mux_def tegra210_pll_sources[] = {
+ /* Core clocks. */
+ MUX(0, "pllD2_src", mux_pll_srcs, PLLD2_BASE, 25, 2),
+ MUX(0, "pllDP_src", mux_pll_srcs, PLLDP_BASE, 25, 2),
+ MUX(0, "pllC4_src", mux_pll_srcs, PLLC4_BASE, 25, 2),
+ MUX(0, "pllE_src1", mux_plle_src1, PLLE_AUX, 2, 1),
+ MUX(0, "pllE_src", mux_plle_src, PLLE_AUX, 28, 1),
+};
+
+/* Gates for PLL branches. */
+static struct clk_gate_def tegra210_pll_gates[] = {
+ /* Core clocks. */
+ GATE_PLL(0, "pllC_out1", "pllC_out1_div", PLLC_OUT, 0),
+
+ GATE_PLL(0, "pllP_out1", "pllP_out1_div", PLLP_OUTA, 0),
+ GATE_PLL(0, "pllP_out3", "pllP_out3_div", PLLP_OUTB, 0),
+ GATE_PLL(TEGRA210_CLK_PLL_P_OUT4, "pllP_out4", "pllP_out4_div", PLLP_OUTB, 16),
+ GATE_PLL(0, "pllP_out5", "pllP_out5_div", PLLP_OUTC, 16),
+
+ GATE_PLL(0, "pllU_out1", "pllU_out1_div", PLLU_OUTA, 0),
+ GATE_PLL(0, "pllU_out2", "pllU_out2_div", PLLU_OUTA, 16),
+ GATE(0, "pllU_480", "pllU", PLLU_BASE, 22),
+ GATE(0, "pllU_60", "pllU_out2", PLLU_BASE, 23),
+ GATE(0, "pllU_48", "pllU_out1", PLLU_BASE, 25),
+
+ GATE_PLL(0, "pllREFE_out1", "pllREFE_out1_div", PLLREFE_OUT, 0),
+ GATE_PLL(0, "pllC4_out3", "pllC4_out3_div", PLLC4_OUT, 0),
+
+ GATE_PLL(0, "pllA_out0", "pllA_out0_div", PLLA_OUT, 0),
+};
+
+struct clk_div_table tegra210_pll_pdiv_tbl[] = {
+ /* value , divider */
+ { 0, 1 },
+ { 1, 2 },
+ { 2, 3 },
+ { 3, 4 },
+ { 4, 5 },
+ { 5, 6 },
+ { 6, 8 },
+ { 7, 10 },
+ { 8, 12 },
+ { 9, 16 },
+ {10, 12 },
+ {11, 16 },
+ {12, 20 },
+ {13, 24 },
+ {14, 32 },
+ { 0, 0 },
+};
+
+/* Dividers for PLL branches. */
+static struct clk_div_def tegra210_pll_divs[] = {
+ /* Core clocks. */
+ DIV7_1(0, "pllC_out1_div", "pllC_out0", PLLC_OUT, 8),
+
+ DIV7_1(0, "pllP_out1_div", "pllP_out0", PLLP_OUTA, 8),
+ DIV_TB(0, "pllP_out2", "pllP_out0", PLLP_BASE, 20, 5, tegra210_pll_pdiv_tbl),
+ DIV7_1(0, "pllP_out3_div", "pllP_out0", PLLP_OUTB, 8),
+ DIV7_1(0, "pllP_out4_div", "pllP_out0", PLLP_OUTB, 24),
+ DIV7_1(0, "pllP_out5_div", "pllP_out0", PLLP_OUTC, 24),
+
+ DIV_TB(0, "pllU_out0", "pllU", PLLU_BASE, 16, 5, tegra210_pll_pdiv_tbl),
+ DIV7_1(0, "pllU_out1_div", "pllU_out0", PLLU_OUTA, 8),
+ DIV7_1(0, "pllU_out2_div", "pllU_out0", PLLU_OUTA, 24),
+
+ DIV_TB(0, "pllREFE_out0", "pllREFE", PLLREFE_BASE, 16, 5, tegra210_pll_pdiv_tbl),
+ DIV7_1(0, "pllREFE_out1_div", "pllREFE", PLLREFE_OUT, 8),
+
+ DIV_TB(TEGRA210_CLK_PLL_C4_OUT0,
+ "pllC4_out0", "pllC4", PLLC4_BASE, 19, 5, tegra210_pll_pdiv_tbl),
+ DIV7_1(0, "pllC4_out3_div", "pllC4_out0", PLLC4_OUT, 8),
+
+ DIV7_1(0, "pllA_out0_div", "pllA", PLLA_OUT, 8),
+
+};
+
+static int tegra210_pll_init(struct clknode *clk, device_t dev);
+static int tegra210_pll_set_gate(struct clknode *clk, bool enable);
+static int tegra210_pll_recalc(struct clknode *clk, uint64_t *freq);
+static int tegra210_pll_set_freq(struct clknode *clknode, uint64_t fin,
+ uint64_t *fout, int flags, int *stop);
+struct pll_sc {
+ device_t clkdev;
+ enum pll_type type;
+ uint32_t base_reg;
+ uint32_t misc_reg;
+ uint32_t lock_enable;
+ uint32_t iddq_reg;
+ uint32_t iddq_mask;
+ uint32_t flags;
+ struct pdiv_table *pdiv_table;
+ struct mnp_bits mnp_bits;
+};
+
+static clknode_method_t tegra210_pll_methods[] = {
+ /* Device interface */
+ CLKNODEMETHOD(clknode_init, tegra210_pll_init),
+ CLKNODEMETHOD(clknode_set_gate, tegra210_pll_set_gate),
+ CLKNODEMETHOD(clknode_recalc_freq, tegra210_pll_recalc),
+ CLKNODEMETHOD(clknode_set_freq, tegra210_pll_set_freq),
+ CLKNODEMETHOD_END
+};
+DEFINE_CLASS_1(tegra210_pll, tegra210_pll_class, tegra210_pll_methods,
+ sizeof(struct pll_sc), clknode_class);
+
+static int
+pll_enable(struct pll_sc *sc)
+{
+ uint32_t reg;
+
+
+ RD4(sc, sc->base_reg, &reg);
+ if (sc->type != PLL_E)
+ reg &= ~PLL_BASE_BYPASS;
+ reg |= PLL_BASE_ENABLE;
+ WR4(sc, sc->base_reg, reg);
+ return (0);
+}
+
+static int
+pll_disable(struct pll_sc *sc)
+{
+ uint32_t reg;
+
+ RD4(sc, sc->base_reg, &reg);
+ if (sc->type != PLL_E)
+ reg |= PLL_BASE_BYPASS;
+ reg &= ~PLL_BASE_ENABLE;
+ WR4(sc, sc->base_reg, reg);
+ return (0);
+}
+
+static uint32_t
+pdiv_to_reg(struct pll_sc *sc, uint32_t p_div)
+{
+ struct pdiv_table *tbl;
+
+ tbl = sc->pdiv_table;
+ if (tbl == NULL) {
+ if (sc->flags & PLL_FLAG_PDIV_POWER2)
+ return (ffs(p_div) - 1);
+ else
+ return (p_div);
+ }
+
+ while (tbl->divider != 0) {
+ if (p_div <= tbl->divider)
+ return (tbl->value);
+ tbl++;
+ }
+ return (0xFFFFFFFF);
+}
+
+static uint32_t
+reg_to_pdiv(struct pll_sc *sc, uint32_t reg)
+{
+ struct pdiv_table *tbl;
+
+ tbl = sc->pdiv_table;
+ if (tbl == NULL) {
+ if (sc->flags & PLL_FLAG_PDIV_POWER2)
+ return (1 << reg);
+ else
+ return (reg == 0 ? 1: reg);
+ }
+ while (tbl->divider) {
+ if (reg == tbl->value)
+ return (tbl->divider);
+ tbl++;
+ }
+ return (0);
+}
+
+static uint32_t
+get_masked(uint32_t val, uint32_t shift, uint32_t width)
+{
+
+ return ((val >> shift) & ((1 << width) - 1));
+}
+
+static uint32_t
+set_masked(uint32_t val, uint32_t v, uint32_t shift, uint32_t width)
+{
+
+ val &= ~(((1 << width) - 1) << shift);
+ val |= (v & ((1 << width) - 1)) << shift;
+ return (val);
+}
+
+static void
+get_divisors(struct pll_sc *sc, uint32_t *m, uint32_t *n, uint32_t *p)
+{
+ uint32_t val;
+ struct mnp_bits *mnp_bits;
+
+ mnp_bits = &sc->mnp_bits;
+ RD4(sc, sc->base_reg, &val);
+ *m = get_masked(val, mnp_bits->m_shift, mnp_bits->m_width);
+ *n = get_masked(val, mnp_bits->n_shift, mnp_bits->n_width);
+ *p = get_masked(val, mnp_bits->p_shift, mnp_bits->p_width);
+}
+
+static uint32_t
+set_divisors(struct pll_sc *sc, uint32_t val, uint32_t m, uint32_t n,
+ uint32_t p)
+{
+ struct mnp_bits *mnp_bits;
+
+ mnp_bits = &sc->mnp_bits;
+ val = set_masked(val, m, mnp_bits->m_shift, mnp_bits->m_width);
+ val = set_masked(val, n, mnp_bits->n_shift, mnp_bits->n_width);
+ val = set_masked(val, p, mnp_bits->p_shift, mnp_bits->p_width);
+ return (val);
+}
+
+static bool
+is_locked(struct pll_sc *sc)
+{
+ uint32_t reg;
+
+ switch (sc->type) {
+ case PLL_REFE:
+ RD4(sc, sc->misc_reg, &reg);
+ reg &= PLLREFE_MISC_LOCK;
+ break;
+
+ case PLL_E:
+ RD4(sc, sc->misc_reg, &reg);
+ reg &= PLLE_MISC_LOCK;
+ break;
+
+ default:
+ RD4(sc, sc->base_reg, &reg);
+ reg &= PLL_BASE_LOCK;
+ break;
+ }
+ return (reg != 0);
+}
+
+static int
+wait_for_lock(struct pll_sc *sc)
+{
+ int i;
+
+ for (i = PLL_LOCK_TIMEOUT / 10; i > 0; i--) {
+ if (is_locked(sc))
+ break;
+ DELAY(10);
+ }
+ if (i <= 0) {
+ printf("PLL lock timeout\n");
+ return (ETIMEDOUT);
+ }
+ return (0);
+}
+
+static int
+plle_enable(struct pll_sc *sc)
+{
+ uint32_t reg;
+ int rv;
+ struct mnp_bits *mnp_bits;
+ uint32_t pll_m = 2;
+ uint32_t pll_n = 125;
+ uint32_t pll_cml = 14;
+
+ mnp_bits = &sc->mnp_bits;
+
+ /* Disable lock override. */
+ RD4(sc, sc->base_reg, &reg);
+ reg &= ~PLLE_BASE_LOCK_OVERRIDE;
+ WR4(sc, sc->base_reg, reg);
+
+ /* Enable SW control */
+ RD4(sc, PLLE_AUX, &reg);
+ reg |= PLLE_AUX_ENABLE_SWCTL;
+ reg &= ~PLLE_AUX_SEQ_ENABLE;
+ WR4(sc, PLLE_AUX, reg);
+ DELAY(10);
+
+ RD4(sc, sc->misc_reg, &reg);
+ reg |= PLLE_MISC_LOCK_ENABLE;
+ reg |= PLLE_MISC_IDDQ_SWCTL;
+ reg &= ~PLLE_MISC_IDDQ_OVERRIDE_VALUE;
+ reg |= PLLE_MISC_PTS;
+ reg &= ~PLLE_MISC_VREG_BG_CTRL(~0);
+ reg &= ~PLLE_MISC_VREG_CTRL(~0);
+ WR4(sc, sc->misc_reg, reg);
+ DELAY(10);
+
+ RD4(sc, PLLE_SS_CNTL, &reg);
+ reg |= PLLE_SS_CNTL_DISABLE;
+ WR4(sc, PLLE_SS_CNTL, reg);
+
+ RD4(sc, sc->base_reg, &reg);
+ reg = set_divisors(sc, reg, pll_m, pll_n, pll_cml);
+ WR4(sc, sc->base_reg, reg);
+ DELAY(10);
+
+ pll_enable(sc);
+ rv = wait_for_lock(sc);
+ if (rv != 0)
+ return (rv);
+
+ RD4(sc, PLLE_SS_CNTL, &reg);
+ reg &= ~PLLE_SS_CNTL_SSCINCINTRV(~0);
+ reg &= ~PLLE_SS_CNTL_SSCINC(~0);
+ reg &= ~PLLE_SS_CNTL_SSCINVERT;
+ reg &= ~PLLE_SS_CNTL_SSCCENTER;
+ reg &= ~PLLE_SS_CNTL_SSCMAX(~0);
+ reg |= PLLE_SS_CNTL_SSCINCINTRV(0x23);
+ reg |= PLLE_SS_CNTL_SSCINC(0x1);
+ reg |= PLLE_SS_CNTL_SSCMAX(0x21);
+ WR4(sc, PLLE_SS_CNTL, reg);
+ reg &= ~PLLE_SS_CNTL_SSCBYP;
+ reg &= ~PLLE_SS_CNTL_BYPASS_SS;
+ WR4(sc, PLLE_SS_CNTL, reg);
+ DELAY(10);
+
+ reg &= ~PLLE_SS_CNTL_INTERP_RESET;
+ WR4(sc, PLLE_SS_CNTL, reg);
+ DELAY(10);
+
+ /* HW control of brick pll. */
+ RD4(sc, sc->misc_reg, &reg);
+ reg &= ~PLLE_MISC_IDDQ_SWCTL;
+ WR4(sc, sc->misc_reg, reg);
+
+ RD4(sc, PLLE_AUX, &reg);
+ reg |= PLLE_AUX_USE_LOCKDET;
+ reg |= PLLE_AUX_SS_SEQ_INCLUDE;
+ reg &= ~PLLE_AUX_ENABLE_SWCTL;
+ reg &= ~PLLE_AUX_SS_SWCTL;
+ WR4(sc, PLLE_AUX, reg);
+ reg |= PLLE_AUX_SEQ_START_STATE;
+ DELAY(10);
+ reg |= PLLE_AUX_SEQ_ENABLE;
+ WR4(sc, PLLE_AUX, reg);
+
+ /* Enable and start XUSBIO PLL HW control*/
+ RD4(sc, XUSBIO_PLL_CFG0, &reg);
+ reg &= ~XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL;
+ reg &= ~XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL;
+ reg |= XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET;
+ reg |= XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ;
+ reg &= ~XUSBIO_PLL_CFG0_SEQ_ENABLE;
+ WR4(sc, XUSBIO_PLL_CFG0, reg);
+ DELAY(10);
+
+ reg |= XUSBIO_PLL_CFG0_SEQ_ENABLE;
+ WR4(sc, XUSBIO_PLL_CFG0, reg);
+
+
+ /* Enable and start SATA PLL HW control */
+ RD4(sc, SATA_PLL_CFG0, &reg);
+ reg &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL;
+ reg &= ~SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE;
+ reg |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET;
+ reg |= SATA_PLL_CFG0_PADPLL_SLEEP_IDDQ;
+ reg &= ~SATA_PLL_CFG0_SEQ_IN_SWCTL;
+ reg &= ~SATA_PLL_CFG0_SEQ_RESET_INPUT_VALUE;
+ reg &= ~SATA_PLL_CFG0_SEQ_LANE_PD_INPUT_VALUE;
+ reg &= ~SATA_PLL_CFG0_SEQ_PADPLL_PD_INPUT_VALUE;
+ reg &= ~SATA_PLL_CFG0_SEQ_ENABLE;
+ WR4(sc, SATA_PLL_CFG0, reg);
+ DELAY(10);
+ reg |= SATA_PLL_CFG0_SEQ_ENABLE;
+ WR4(sc, SATA_PLL_CFG0, reg);
+
+ /* Enable HW control of PCIe PLL. */
+ RD4(sc, PCIE_PLL_CFG, &reg);
+ reg |= PCIE_PLL_CFG_SEQ_ENABLE;
+ WR4(sc, PCIE_PLL_CFG, reg);
+
+ return (0);
+}
+
+static int
+tegra210_pll_set_gate(struct clknode *clknode, bool enable)
+{
+ int rv;
+ struct pll_sc *sc;
+
+ sc = clknode_get_softc(clknode);
+ if (enable == 0) {
+ rv = pll_disable(sc);
+ return(rv);
+ }
+
+ if (sc->type == PLL_E)
+ rv = plle_enable(sc);
+ else
+ rv = pll_enable(sc);
+ return (rv);
+}
+
+static int
+pll_set_std(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags,
+ uint32_t m, uint32_t n, uint32_t p)
+{
+ uint32_t reg;
+ struct mnp_bits *mnp_bits;
+ int rv;
+
+ mnp_bits = &sc->mnp_bits;
+ if (m >= (1 << mnp_bits->m_width))
+ return (ERANGE);
+ if (n >= (1 << mnp_bits->n_width))
+ return (ERANGE);
+ if (pdiv_to_reg(sc, p) >= (1 << mnp_bits->p_width))
+ return (ERANGE);
+
+ if (flags & CLK_SET_DRYRUN) {
+ if (((flags & (CLK_SET_ROUND_UP | CLK_SET_ROUND_DOWN)) == 0) &&
+ (*fout != (((fin / m) * n) /p)))
+ return (ERANGE);
+
+ *fout = ((fin / m) * n) /p;
+
+ return (0);
+ }
+
+ pll_disable(sc);
+
+ /* take pll out of IDDQ */
+ if (sc->iddq_reg != 0)
+ MD4(sc, sc->iddq_reg, sc->iddq_mask, 0);
+
+ RD4(sc, sc->base_reg, &reg);
+ reg = set_masked(reg, m, mnp_bits->m_shift, mnp_bits->m_width);
+ reg = set_masked(reg, n, mnp_bits->n_shift, mnp_bits->n_width);
+ reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift,
+ mnp_bits->p_width);
+ WR4(sc, sc->base_reg, reg);
+
+ /* Enable PLL. */
+ RD4(sc, sc->base_reg, &reg);
+ reg |= PLL_BASE_ENABLE;
+ WR4(sc, sc->base_reg, reg);
+
+ /* Enable lock detection. */
+ RD4(sc, sc->misc_reg, &reg);
+ reg |= sc->lock_enable;
+ WR4(sc, sc->misc_reg, reg);
+
+ rv = wait_for_lock(sc);
+ if (rv != 0) {
+ /* Disable PLL */
+ RD4(sc, sc->base_reg, &reg);
+ reg &= ~PLL_BASE_ENABLE;
+ WR4(sc, sc->base_reg, reg);
+ return (rv);
+ }
+ RD4(sc, sc->misc_reg, &reg);
+
+ pll_enable(sc);
+ *fout = ((fin / m) * n) / p;
+ return 0;
+}
+
+static int
+plla_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)
+{
+ uint32_t m, n, p;
+
+ p = 1;
+ m = 3;
+ n = (*fout * p * m + fin / 2)/ fin;
+ dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p);
+ return (pll_set_std(sc, fin, fout, flags, m, n, p));
+}
+
+static int
+pllc_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)
+{
+ uint32_t m, n, p;
+
+ p = 2;
+ m = 3;
+ n = (*fout * p * m + fin / 2)/ fin;
+ dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p);
+ return (pll_set_std( sc, fin, fout, flags, m, n, p));
+}
+
+static int
+pllc4_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)
+{
+ uint32_t m, n, p;
+
+ p = 1;
+ m = 4;
+ n = (*fout * p * m + fin / 2)/ fin;
+ dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p);
+ return (pll_set_std( sc, fin, fout, flags, m, n, p));
+}
+
+static int
+plldp_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)
+{
+ uint32_t m, n, p;
+
+ p = 1;
+ m = 4;
+ n = (*fout * p * m + fin / 2)/ fin;
+ dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p);
+ return (pll_set_std( sc, fin, fout, flags, m, n, p));
+}
+
+
+/*
+ * PLLD2 is used as source for pixel clock for HDMI.
+ * We must be able to set it frequency very flexibly and
+ * precisely (within 5% tolerance limit allowed by HDMI specs).
+ *
+ * For this reason, it is necessary to search the full state space.
+ * Fortunately, thanks to early cycle terminations, performance
+ * is within acceptable limits.
+ */
+#define PLLD2_PFD_MIN 12000000 /* 12 MHz */
+#define PLLD2_PFD_MAX 38400000 /* 38.4 MHz */
+#define PLLD2_VCO_MIN 750000000 /* 750 MHz */
+#define PLLD2_VCO_MAX 1500000000 /* 1.5 GHz */
+
+static int
+plld2_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)
+{
+ uint32_t m, n, p;
+ uint32_t best_m, best_n, best_p;
+ uint64_t vco, pfd;
+ int64_t err, best_err;
+ struct mnp_bits *mnp_bits;
+ struct pdiv_table *tbl;
+ int p_idx, rv;
+
+ mnp_bits = &sc->mnp_bits;
+ tbl = sc->pdiv_table;
+ best_err = INT64_MAX;
+
+ for (p_idx = 0; tbl[p_idx].divider != 0; p_idx++) {
+ p = tbl[p_idx].divider;
+
+ /* Check constraints */
+ vco = *fout * p;
+ if (vco < PLLD2_VCO_MIN)
+ continue;
+ if (vco > PLLD2_VCO_MAX)
+ break;
+
+ for (m = 1; m < (1 << mnp_bits->m_width); m++) {
+ n = (*fout * p * m + fin / 2) / fin;
+
+ /* Check constraints */
+ if (n == 0)
+ continue;
+ if (n >= (1 << mnp_bits->n_width))
+ break;
+ vco = (fin * n) / m;
+ if (vco > PLLD2_VCO_MAX || vco < PLLD2_VCO_MIN)
+ continue;
+ pfd = fin / m;
+ if (pfd > PLLD2_PFD_MAX || vco < PLLD2_PFD_MIN)
+ continue;
+
+ /* Constraints passed, save best result */
+ err = *fout - vco / p;
+ if (err < 0)
+ err = -err;
+ if (err < best_err) {
+ best_err = err;
+ best_p = p;
+ best_m = m;
+ best_n = n;
+ }
+ if (err == 0)
+ goto done;
+ }
+ }
+done:
+ /*
+ * HDMI specification allows 5% pixel clock tolerance,
+ * we will by a slightly stricter
+ */
+ if (best_err > ((*fout * 100) / 4))
+ return (ERANGE);
+
+ if (flags & CLK_SET_DRYRUN)
+ return (0);
+ rv = pll_set_std(sc, fin, fout, flags, best_m, best_n, best_p);
+ /* XXXX Panic for rv == ERANGE ? */
+ return (rv);
+}
+
+static int
+pllrefe_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)
+{
+ uint32_t m, n, p;
+
+ m = 1;
+ p = 1;
+ n = *fout * p * m / fin;
+ dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p);
+ return (pll_set_std(sc, fin, fout, flags, m, n, p));
+}
+
+#define PLLX_PFD_MIN 12000000LL /* 12 MHz */
+#define PLLX_PFD_MAX 38400000LL /* 38.4 MHz */
+#define PLLX_VCO_MIN 900000000LL /* 0.9 GHz */
+#define PLLX_VCO_MAX 3000000000LL /* 3 GHz */
+
+static int
+pllx_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)
+{
+ struct mnp_bits *mnp_bits;
+ uint32_t m, n, p;
+ uint32_t old_m, old_n, old_p;
+ uint32_t reg;
+ int i, rv;
+
+ mnp_bits = &sc->mnp_bits;
+
+ get_divisors(sc, &old_m, &old_n, &old_p);
+ old_p = reg_to_pdiv(sc, old_p);
+
+ /* Pre-divider is fixed, Compute post-divider */
+ m = old_m;
+ p = 1;
+ while ((*fout * p) < PLLX_VCO_MIN)
+ p++;
+ if ((*fout * p) > PLLX_VCO_MAX)
+ return (ERANGE);
+
+ n = (*fout * p * m + fin / 2) / fin;
+ dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p);
+
+ if (m >= (1 << mnp_bits->m_width))
+ return (ERANGE);
+ if (n >= (1 << mnp_bits->n_width))
+ return (ERANGE);
+ if (pdiv_to_reg(sc, p) >= (1 << mnp_bits->p_width))
+ return (ERANGE);
+
+ if (flags & CLK_SET_DRYRUN) {
+ if (((flags & (CLK_SET_ROUND_UP | CLK_SET_ROUND_DOWN)) == 0) &&
+ (*fout != (((fin / m) * n) /p)))
+ return (ERANGE);
+ *fout = ((fin / m) * n) /p;
+ return (0);
+ }
+
+ /* If new post-divider is bigger that original, set it now. */
+ if (p < old_p) {
+ RD4(sc, sc->base_reg, &reg);
+ reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift,
+ mnp_bits->p_width);
+ WR4(sc, sc->base_reg, reg);
+ }
+ DELAY(100);
+
+ /* vvv Program dynamic VCO ramp. vvv */
+ /* 1 - disable dynamic ramp mode. */
+ RD4(sc, PLLX_MISC_2, &reg);
+ reg &= ~PLLX_MISC_2_EN_DYNRAMP;
+ WR4(sc, PLLX_MISC_2, reg);
+
+ /* 2 - Setup new ndiv. */
+ RD4(sc, PLLX_MISC_2, &reg);
+ reg &= ~PLLX_MISC_2_NDIV_NEW(~0);
+ reg |= PLLX_MISC_2_NDIV_NEW(n);
+ WR4(sc, PLLX_MISC_2, reg);
+
+ /* 3 - enable dynamic ramp. */
+ RD4(sc, PLLX_MISC_2, &reg);
+ reg |= PLLX_MISC_2_EN_DYNRAMP;
+ WR4(sc, PLLX_MISC_2, reg);
+
+ /* 4 - wait for done. */
+ for (i = PLL_LOCK_TIMEOUT / 10; i > 0; i--) {
+ RD4(sc, PLLX_MISC_2, &reg);
+ if (reg & PLLX_MISC_2_DYNRAMP_DONE)
+ break;
+ DELAY(10);
+ }
+ if (i <= 0) {
+ printf("PLL X dynamic ramp timedout\n");
+ return (ETIMEDOUT);
+ }
+
+ /* 5 - copy new ndiv to base register. */
+ RD4(sc, sc->base_reg, &reg);
+ reg = set_masked(reg, n, mnp_bits->n_shift,
+ mnp_bits->n_width);
+ WR4(sc, sc->base_reg, reg);
+
+ /* 6 - disable dynamic ramp mode. */
+ RD4(sc, PLLX_MISC_2, &reg);
+ reg &= ~PLLX_MISC_2_EN_DYNRAMP;
+ WR4(sc, PLLX_MISC_2, reg);
+
+ rv = wait_for_lock(sc);
+ if (rv != 0) {
+ printf("PLL X is not locked !!\n");
+ }
+ /* ^^^ Dynamic ramp done. ^^^ */
+
+ /* If new post-divider is smaller that original, set it. */
+ if (p > old_p) {
+ RD4(sc, sc->base_reg, &reg);
+ reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift,
+ mnp_bits->p_width);
+ WR4(sc, sc->base_reg, reg);
+ }
+
+ *fout = ((fin / m) * n) / p;
+ return (0);
+}
+
+/* Simplified setup for 38.4 MHz clock. */
+#define PLLX_STEP_A 0x04
+#define PLLX_STEP_B 0x05
+static int
+pllx_init(struct pll_sc *sc)
+{
+ uint32_t reg;
+
+ RD4(sc, PLLX_MISC, &reg);
+ reg = PLLX_MISC_LOCK_ENABLE;
+ WR4(sc, PLLX_MISC, reg);
+
+ /* Setup dynamic ramp. */
+ reg = 0;
+ reg |= PLLX_MISC_2_DYNRAMP_STEPA(PLLX_STEP_A);
+ reg |= PLLX_MISC_2_DYNRAMP_STEPB(PLLX_STEP_B);
+ WR4(sc, PLLX_MISC_2, reg);
+
+ /* Disable SDM. */
+ reg = 0;
+ WR4(sc, PLLX_MISC_4, reg);
+ WR4(sc, PLLX_MISC_5, reg);
+
+ return (0);
+}
+
+static int
+tegra210_pll_set_freq(struct clknode *clknode, uint64_t fin, uint64_t *fout,
+ int flags, int *stop)
+{
+ *stop = 1;
+ int rv;
+ struct pll_sc *sc;
+
+ sc = clknode_get_softc(clknode);
+ dprintf("%s: %s requested freq: %lu, input freq: %lu\n", __func__,
+ clknode_get_name(clknode), *fout, fin);
+ switch (sc->type) {
+ case PLL_A:
+ rv = plla_set_freq(sc, fin, fout, flags);
+ break;
+
+ case PLL_C:
+ case PLL_C2:
+ case PLL_C3:
+ rv = pllc_set_freq(sc, fin, fout, flags);
+ break;
+
+ case PLL_C4:
+ rv = pllc4_set_freq(sc, fin, fout, flags);
+ break;
+
+ case PLL_D2:
+ rv = plld2_set_freq(sc, fin, fout, flags);
+ break;
+
+ case PLL_DP:
+ rv = plldp_set_freq(sc, fin, fout, flags);
+ break;
+
+ case PLL_REFE:
+ rv = pllrefe_set_freq(sc, fin, fout, flags);
+ break;
+
+ case PLL_X:
+ rv = pllx_set_freq(sc, fin, fout, flags);
+ break;
+
+ case PLL_U:
+ if (*fout == 480000000) /* PLLU is fixed to 480 MHz */
+ rv = 0;
+ else
+ rv = ERANGE;
+ break;
+ default:
+ rv = ENXIO;
+ break;
+ }
+
+ return (rv);
+}
+
+
+static int
+tegra210_pll_init(struct clknode *clk, device_t dev)
+{
+ struct pll_sc *sc;
+ uint32_t reg, rv;
+
+ sc = clknode_get_softc(clk);
+
+ if (sc->type == PLL_X) {
+ rv = pllx_init(sc);
+ if (rv != 0)
+ return (rv);
+ }
+
+ /* If PLL is enabled, enable lock detect too. */
+ RD4(sc, sc->base_reg, &reg);
+ if (reg & PLL_BASE_ENABLE) {
+ RD4(sc, sc->misc_reg, &reg);
+ reg |= sc->lock_enable;
+ WR4(sc, sc->misc_reg, reg);
+ }
+ if (sc->type == PLL_REFE) {
+ RD4(sc, sc->misc_reg, &reg);
+ reg &= ~(1 << 29); /* Disable lock override */
+ WR4(sc, sc->misc_reg, reg);
+ }
+ clknode_init_parent_idx(clk, 0);
+ return(0);
+}
+
+static int
+tegra210_pll_recalc(struct clknode *clk, uint64_t *freq)
+{
+ struct pll_sc *sc;
+ uint32_t m, n, p, pr;
+ uint32_t reg, misc_reg;
+ int locked;
+
+ sc = clknode_get_softc(clk);
+
+ RD4(sc, sc->base_reg, &reg);
+ RD4(sc, sc->misc_reg, &misc_reg);
+
+ get_divisors(sc, &m, &n, &pr);
+
+ /* If VCO is directlu exposed, P divider is handled by external node */
+ if (sc->flags & PLL_FLAG_VCO_OUT)
+ p = 1;
+ else
+ p = reg_to_pdiv(sc, pr);
+
+ locked = is_locked(sc);
+
+ dprintf("%s: %s (0x%08x, 0x%08x) - m: %d, n: %d, p: %d (%d): "
+ "e: %d, r: %d, o: %d - %s\n", __func__,
+ clknode_get_name(clk), reg, misc_reg, m, n, p, pr,
+ (reg >> 30) & 1, (reg >> 29) & 1, (reg >> 28) & 1,
+ locked ? "locked" : "unlocked");
+
+ if ((m == 0) || (n == 0) || (p == 0)) {
+ *freq = 0;
+ return (EINVAL);
+ }
+ if (!locked) {
+ *freq = 0;
+ return (0);
+ }
+ *freq = ((*freq / m) * n) / p;
+ return (0);
+}
+
+static int
+pll_register(struct clkdom *clkdom, struct clk_pll_def *clkdef)
+{
+ struct clknode *clk;
+ struct pll_sc *sc;
+
+ clk = clknode_create(clkdom, &tegra210_pll_class, &clkdef->clkdef);
+ if (clk == NULL)
+ return (ENXIO);
+
+ sc = clknode_get_softc(clk);
+ sc->clkdev = clknode_get_device(clk);
+ sc->type = clkdef->type;
+ sc->base_reg = clkdef->base_reg;
+ sc->misc_reg = clkdef->misc_reg;
+ sc->lock_enable = clkdef->lock_enable;
+ sc->iddq_reg = clkdef->iddq_reg;
+ sc->iddq_mask = clkdef->iddq_mask;
+ sc->flags = clkdef->flags;
+ sc->pdiv_table = clkdef->pdiv_table;
+ sc->mnp_bits = clkdef->mnp_bits;
+ clknode_register(clkdom, clk);
+ return (0);
+}
+
+static void config_utmi_pll(struct tegra210_car_softc *sc)
+{
+ uint32_t reg;
+ /*
+ * XXX Simplified UTMIP settings for 38.4MHz base clock.
+ */
+#define ENABLE_DELAY_COUNT 0x00
+#define STABLE_COUNT 0x00
+#define ACTIVE_DELAY_COUNT 0x06
+#define XTAL_FREQ_COUNT 0x80
+
+ CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, &reg);
+ reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
+ CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg);
+
+ CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG2, &reg);
+ reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
+ reg |= UTMIP_PLL_CFG2_STABLE_COUNT(STABLE_COUNT);
+ reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
+ reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(ACTIVE_DELAY_COUNT);
+ CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG2, reg);
+
+ CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG1, &reg);
+ reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
+ reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(ENABLE_DELAY_COUNT);
+ reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
+ reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(XTAL_FREQ_COUNT);
+ reg |= UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP;
+ CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG1, reg);
+
+ reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
+ reg |= UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
+ CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG1, reg);
+ DELAY(20);
+
+ /* Setup samplers. */
+ CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG2, &reg);
+ reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP;
+ reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP;
+ reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP;
+ reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
+ reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
+ reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN;
+ CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG2, reg);
+
+ /* Powerup UTMIP. */
+ CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG1, &reg);
+ reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
+ reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
+ CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG1, reg);
+ DELAY(10);
+
+ /* Prepare UTMIP sequencer. */
+ CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, &reg);
+ reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
+ reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
+ CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg);
+ DELAY(10);
+
+ CLKDEV_READ_4(sc->dev, XUSB_PLL_CFG0, &reg);
+ reg &= ~XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY;
+ CLKDEV_WRITE_4(sc->dev, XUSB_PLL_CFG0, reg);
+ DELAY(10);
+
+ /* HW control of UTMIPLL. */
+ CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, &reg);
+ reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
+ CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg);
+}
+
+void
+tegra210_init_plls(struct tegra210_car_softc *sc)
+{
+ int i, rv;
+
+ for (i = 0; i < nitems(tegra210_pll_sources); i++) {
+ rv = clknode_mux_register(sc->clkdom, tegra210_pll_sources + i);
+ if (rv != 0)
+ panic("clk_mux_register failed");
+ }
+
+ for (i = 0; i < nitems(pll_clks); i++) {
+ rv = pll_register(sc->clkdom, pll_clks + i);
+ if (rv != 0)
+ panic("pll_register failed");
+ }
+
+ config_utmi_pll(sc);
+
+ for (i = 0; i < nitems(tegra210_pll_fdivs); i++) {
+ rv = clknode_fixed_register(sc->clkdom, tegra210_pll_fdivs + i);
+ if (rv != 0)
+ panic("clk_fixed_register failed");
+ }
+
+ for (i = 0; i < nitems(tegra210_pll_gates); i++) {
+ rv = clknode_gate_register(sc->clkdom, tegra210_pll_gates + i);
+ if (rv != 0)
+ panic("clk_gate_register failed");
+ }
+
+ for (i = 0; i < nitems(tegra210_pll_divs); i++) {
+ rv = clknode_div_register(sc->clkdom, tegra210_pll_divs + i);
+ if (rv != 0)
+ panic("clk_div_register failed");
+ }
+}
diff --git a/sys/arm64/nvidia/tegra210/tegra210_clk_super.c b/sys/arm64/nvidia/tegra210/tegra210_clk_super.c
new file mode 100644
index 000000000000..63005165c9ba
--- /dev/null
+++ b/sys/arm64/nvidia/tegra210/tegra210_clk_super.c
@@ -0,0 +1,231 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
+ *
+ * Copyright 2020 Michal Meloun <mmel@FreeBSD.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+#include <sys/rman.h>
+
+#include <machine/bus.h>
+
+#include <dev/extres/clk/clk.h>
+
+#include <gnu/dts/include/dt-bindings/clock/tegra210-car.h>
+#include "tegra210_car.h"
+
+struct super_mux_def {
+ struct clknode_init_def clkdef;
+ uint32_t base_reg;
+ uint32_t flags;
+};
+
+#define PLIST(x) static const char *x[]
+#define SM(_id, cn, pl, r) \
+{ \
+ .clkdef.id = _id, \
+ .clkdef.name = cn, \
+ .clkdef.parent_names = pl, \
+ .clkdef.parent_cnt = nitems(pl), \
+ .clkdef.flags = CLK_NODE_STATIC_STRINGS, \
+ .base_reg = r, \
+}
+
+
+PLIST(cclk_g_parents) = {
+ "clk_m", NULL, "clk_s", NULL,
+ "pllP_out0", "pllP_out4", NULL, NULL,
+ "pllX_out0", "dfllCPU_out_alias", NULL, NULL,
+ NULL, NULL, "pllX_out0_alias", "dfllCPU_out",
+};
+
+PLIST(cclk_lp_parents) = {
+ "clk_m", NULL, "clk_s", NULL,
+ "pllP_out0", "pllP_out4", NULL, NULL,
+ "pllX_out0", "dfllCPU_out_alias", NULL, NULL,
+ NULL, NULL, "pllX_out0_alias", "dfllCPU_out",
+};
+
+PLIST(sclk_parents) = {
+ "clk_m", "pllC_out1", "pllC4_out3", "pllP_out0",
+ "pllP_out2", "pllC4_out1", "clk_s", "pllC4_out1",
+};
+
+static struct super_mux_def super_mux_def[] = {
+ SM(TEGRA210_CLK_CCLK_G, "cclk_g", cclk_g_parents, CCLKG_BURST_POLICY),
+ SM(TEGRA210_CLK_CCLK_LP, "cclk_lp", cclk_lp_parents, CCLKLP_BURST_POLICY),
+ SM(TEGRA210_CLK_SCLK, "sclk", sclk_parents, SCLK_BURST_POLICY),
+};
+
+static int super_mux_init(struct clknode *clk, device_t dev);
+static int super_mux_set_mux(struct clknode *clk, int idx);
+
+struct super_mux_sc {
+ device_t clkdev;
+ uint32_t base_reg;
+ uint32_t flags;
+
+ int mux;
+};
+
+static clknode_method_t super_mux_methods[] = {
+ /* Device interface */
+ CLKNODEMETHOD(clknode_init, super_mux_init),
+ CLKNODEMETHOD(clknode_set_mux, super_mux_set_mux),
+ CLKNODEMETHOD_END
+};
+DEFINE_CLASS_1(tegra210_super_mux, tegra210_super_mux_class, super_mux_methods,
+ sizeof(struct super_mux_sc), clknode_class);
+
+/* Mux status. */
+#define SUPER_MUX_STATE_STDBY 0
+#define SUPER_MUX_STATE_IDLE 1
+#define SUPER_MUX_STATE_RUN 2
+#define SUPER_MUX_STATE_IRQ 3
+#define SUPER_MUX_STATE_FIQ 4
+
+/* Mux register bits. */
+#define SUPER_MUX_STATE_BIT_SHIFT 28
+#define SUPER_MUX_STATE_BIT_MASK 0xF
+/* State is Priority encoded */
+#define SUPER_MUX_STATE_BIT_STDBY 0x00
+#define SUPER_MUX_STATE_BIT_IDLE 0x01
+#define SUPER_MUX_STATE_BIT_RUN 0x02
+#define SUPER_MUX_STATE_BIT_IRQ 0x04
+#define SUPER_MUX_STATE_BIT_FIQ 0x08
+
+#define SUPER_MUX_MUX_WIDTH 4
+
+static uint32_t
+super_mux_get_state(uint32_t reg)
+{
+ reg = (reg >> SUPER_MUX_STATE_BIT_SHIFT) & SUPER_MUX_STATE_BIT_MASK;
+ if (reg & SUPER_MUX_STATE_BIT_FIQ)
+ return (SUPER_MUX_STATE_FIQ);
+ if (reg & SUPER_MUX_STATE_BIT_IRQ)
+ return (SUPER_MUX_STATE_IRQ);
+ if (reg & SUPER_MUX_STATE_BIT_RUN)
+ return (SUPER_MUX_STATE_RUN);
+ if (reg & SUPER_MUX_STATE_BIT_IDLE)
+ return (SUPER_MUX_STATE_IDLE);
+ return (SUPER_MUX_STATE_STDBY);
+}
+
+static int
+super_mux_init(struct clknode *clk, device_t dev)
+{
+ struct super_mux_sc *sc;
+ uint32_t reg;
+ int shift, state;
+
+ sc = clknode_get_softc(clk);
+
+ DEVICE_LOCK(sc);
+ RD4(sc, sc->base_reg, &reg);
+ DEVICE_UNLOCK(sc);
+ state = super_mux_get_state(reg);
+
+ if ((state != SUPER_MUX_STATE_RUN) &&
+ (state != SUPER_MUX_STATE_IDLE)) {
+ panic("Unexpected super mux state: %u", state);
+ }
+
+ shift = state * SUPER_MUX_MUX_WIDTH;
+ sc->mux = (reg >> shift) & ((1 << SUPER_MUX_MUX_WIDTH) - 1);
+
+ clknode_init_parent_idx(clk, sc->mux);
+
+ return(0);
+}
+
+static int
+super_mux_set_mux(struct clknode *clk, int idx)
+{
+
+ struct super_mux_sc *sc;
+ int shift, state;
+ uint32_t reg, dummy;
+
+ sc = clknode_get_softc(clk);
+
+ DEVICE_LOCK(sc);
+ RD4(sc, sc->base_reg, &reg);
+ state = super_mux_get_state(reg);
+
+ if ((state != SUPER_MUX_STATE_RUN) &&
+ (state != SUPER_MUX_STATE_IDLE)) {
+ panic("Unexpected super mux state: %u", state);
+ }
+
+ shift = (state - 1) * SUPER_MUX_MUX_WIDTH;
+ sc->mux = idx;
+ reg &= ~(((1 << SUPER_MUX_MUX_WIDTH) - 1) << shift);
+ reg |= idx << shift;
+
+ WR4(sc, sc->base_reg, reg);
+ RD4(sc, sc->base_reg, &dummy);
+ DEVICE_UNLOCK(sc);
+
+ return(0);
+}
+
+static int
+super_mux_register(struct clkdom *clkdom, struct super_mux_def *clkdef)
+{
+ struct clknode *clk;
+ struct super_mux_sc *sc;
+
+ clk = clknode_create(clkdom, &tegra210_super_mux_class,
+ &clkdef->clkdef);
+ if (clk == NULL)
+ return (1);
+
+ sc = clknode_get_softc(clk);
+ sc->clkdev = clknode_get_device(clk);
+ sc->base_reg = clkdef->base_reg;
+ sc->flags = clkdef->flags;
+
+ clknode_register(clkdom, clk);
+ return (0);
+}
+
+void
+tegra210_super_mux_clock(struct tegra210_car_softc *sc)
+{
+ int i, rv;
+
+ for (i = 0; i < nitems(super_mux_def); i++) {
+ rv = super_mux_register(sc->clkdom, &super_mux_def[i]);
+ if (rv != 0)
+ panic("super_mux_register failed");
+ }
+
+}
diff --git a/sys/arm64/nvidia/tegra210/tegra210_coretemp.c b/sys/arm64/nvidia/tegra210/tegra210_coretemp.c
new file mode 100644
index 000000000000..0b637954eceb
--- /dev/null
+++ b/sys/arm64/nvidia/tegra210/tegra210_coretemp.c
@@ -0,0 +1,272 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
+ *
+ * Copyright 2020 Michal Meloun <mmel@FreeBSD.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/cpu.h>
+#include <sys/kernel.h>
+#include <sys/lock.h>
+#include <sys/malloc.h>
+#include <sys/module.h>
+#include <sys/sysctl.h>
+
+#include <machine/bus.h>
+#include <machine/cpu.h>
+
+#include <dev/extres/clk/clk.h>
+#include <dev/ofw/ofw_bus_subr.h>
+
+#include "tegra_soctherm_if.h"
+
+
+enum therm_info {
+ CORETEMP_TEMP,
+ CORETEMP_DELTA,
+ CORETEMP_RESOLUTION,
+ CORETEMP_TJMAX,
+};
+
+struct tegra210_coretemp_softc {
+ device_t dev;
+ int overheat_log;
+ int core_max_temp;
+ int cpu_id;
+ device_t tsens_dev;
+ intptr_t tsens_id;
+};
+
+static int
+coretemp_get_val_sysctl(SYSCTL_HANDLER_ARGS)
+{
+ device_t dev;
+ int val, temp, rv;
+ struct tegra210_coretemp_softc *sc;
+ enum therm_info type;
+ char stemp[16];
+
+
+ dev = (device_t) arg1;
+ sc = device_get_softc(dev);
+ type = arg2;
+
+
+ rv = TEGRA_SOCTHERM_GET_TEMPERATURE(sc->tsens_dev, sc->dev,
+ sc->tsens_id, &temp);
+ if (rv != 0) {
+ device_printf(sc->dev,
+ "Cannot read temperature sensor %u: %d\n",
+ (unsigned int)sc->tsens_id, rv);
+ return (rv);
+ }
+
+ switch (type) {
+ case CORETEMP_TEMP:
+ val = temp / 100;
+ val += 2731;
+ break;
+ case CORETEMP_DELTA:
+ val = (sc->core_max_temp - temp) / 1000;
+ break;
+ case CORETEMP_RESOLUTION:
+ val = 1;
+ break;
+ case CORETEMP_TJMAX:
+ val = sc->core_max_temp / 100;
+ val += 2731;
+ break;
+ }
+
+
+ if ((temp > sc->core_max_temp) && !sc->overheat_log) {
+ sc->overheat_log = 1;
+
+ /*
+ * Check for Critical Temperature Status and Critical
+ * Temperature Log. It doesn't really matter if the
+ * current temperature is invalid because the "Critical
+ * Temperature Log" bit will tell us if the Critical
+ * Temperature has * been reached in past. It's not
+ * directly related to the current temperature.
+ *
+ * If we reach a critical level, allow devctl(4)
+ * to catch this and shutdown the system.
+ */
+ device_printf(dev, "critical temperature detected, "
+ "suggest system shutdown\n");
+ snprintf(stemp, sizeof(stemp), "%d", val);
+ devctl_notify("coretemp", "Thermal", stemp,
+ "notify=0xcc");
+ } else {
+ sc->overheat_log = 0;
+ }
+
+ return (sysctl_handle_int(oidp, 0, val, req));
+}
+
+static int
+tegra210_coretemp_ofw_parse(struct tegra210_coretemp_softc *sc)
+{
+ int rv, ncells;
+ phandle_t node, xnode;
+ pcell_t *cells;
+
+ node = OF_peer(0);
+ node = ofw_bus_find_child(node, "thermal-zones");
+ if (node <= 0) {
+ device_printf(sc->dev, "Cannot find 'thermal-zones'.\n");
+ return (ENXIO);
+ }
+
+ node = ofw_bus_find_child(node, "cpu");
+ if (node <= 0) {
+ device_printf(sc->dev, "Cannot find 'cpu'\n");
+ return (ENXIO);
+ }
+ rv = ofw_bus_parse_xref_list_alloc(node, "thermal-sensors",
+ "#thermal-sensor-cells", 0, &xnode, &ncells, &cells);
+ if (rv != 0) {
+ device_printf(sc->dev,
+ "Cannot parse 'thermal-sensors' property.\n");
+ return (ENXIO);
+ }
+ if (ncells != 1) {
+ device_printf(sc->dev,
+ "Invalid format of 'thermal-sensors' property(%d).\n",
+ ncells);
+ return (ENXIO);
+ }
+
+ sc->tsens_id = 0x100 + sc->cpu_id;
+ OF_prop_free(cells);
+
+ sc->tsens_dev = OF_device_from_xref(xnode);
+ if (sc->tsens_dev == NULL) {
+ device_printf(sc->dev,
+ "Cannot find thermal sensors device.");
+ return (ENXIO);
+ }
+ return (0);
+}
+
+static void
+tegra210_coretemp_identify(driver_t *driver, device_t parent)
+{
+ phandle_t root;
+
+ root = OF_finddevice("/");
+ if (!ofw_bus_node_is_compatible(root, "nvidia,tegra210"))
+ return;
+ if (device_find_child(parent, "tegra210_coretemp", -1) != NULL)
+ return;
+ if (BUS_ADD_CHILD(parent, 0, "tegra210_coretemp", -1) == NULL)
+ device_printf(parent, "add child failed\n");
+}
+
+static int
+tegra210_coretemp_probe(device_t dev)
+{
+
+ device_set_desc(dev, "CPU Thermal Sensor");
+ return (0);
+}
+
+static int
+tegra210_coretemp_attach(device_t dev)
+{
+ struct tegra210_coretemp_softc *sc;
+ device_t pdev;
+ struct sysctl_oid *oid;
+ struct sysctl_ctx_list *ctx;
+ int rv;
+
+ sc = device_get_softc(dev);
+ sc->dev = dev;
+ sc->cpu_id = device_get_unit(dev);
+ sc->core_max_temp = 102000;
+ pdev = device_get_parent(dev);
+
+ rv = tegra210_coretemp_ofw_parse(sc);
+ if (rv != 0)
+ return (rv);
+
+ ctx = device_get_sysctl_ctx(dev);
+
+ oid = SYSCTL_ADD_NODE(ctx,
+ SYSCTL_CHILDREN(device_get_sysctl_tree(pdev)), OID_AUTO,
+ "coretemp", CTLFLAG_RD, NULL, "Per-CPU thermal information");
+
+ /*
+ * Add the MIBs to dev.cpu.N and dev.cpu.N.coretemp.
+ */
+ SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(device_get_sysctl_tree(pdev)),
+ OID_AUTO, "temperature", CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE,
+ dev, CORETEMP_TEMP, coretemp_get_val_sysctl, "IK",
+ "Current temperature");
+ SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "delta",
+ CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, dev, CORETEMP_DELTA,
+ coretemp_get_val_sysctl, "I",
+ "Delta between TCC activation and current temperature");
+ SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "resolution",
+ CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, dev, CORETEMP_RESOLUTION,
+ coretemp_get_val_sysctl, "I",
+ "Resolution of CPU thermal sensor");
+ SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "tjmax",
+ CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, dev, CORETEMP_TJMAX,
+ coretemp_get_val_sysctl, "IK",
+ "TCC activation temperature");
+
+ return (0);
+}
+
+static int
+tegra210_coretemp_detach(device_t dev)
+{
+ struct tegra210_coretemp_softc *sc;
+
+ sc = device_get_softc(dev);
+ return (0);
+}
+
+static device_method_t tegra210_coretemp_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_identify, tegra210_coretemp_identify),
+ DEVMETHOD(device_probe, tegra210_coretemp_probe),
+ DEVMETHOD(device_attach, tegra210_coretemp_attach),
+ DEVMETHOD(device_detach, tegra210_coretemp_detach),
+
+ DEVMETHOD_END
+};
+
+static devclass_t tegra210_coretemp_devclass;
+static DEFINE_CLASS_0(tegra210_coretemp, tegra210_coretemp_driver,
+ tegra210_coretemp_methods, sizeof(struct tegra210_coretemp_softc));
+DRIVER_MODULE(tegra210_coretemp, cpu, tegra210_coretemp_driver,
+ tegra210_coretemp_devclass, NULL, NULL);
diff --git a/sys/arm64/nvidia/tegra210/tegra210_cpufreq.c b/sys/arm64/nvidia/tegra210/tegra210_cpufreq.c
new file mode 100644
index 000000000000..4519dc3ca9d6
--- /dev/null
+++ b/sys/arm64/nvidia/tegra210/tegra210_cpufreq.c
@@ -0,0 +1,502 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
+ *
+ * Copyright 2020 Michal Meloun <mmel@FreeBSD.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/cpu.h>
+#include <sys/kernel.h>
+#include <sys/lock.h>
+#include <sys/malloc.h>
+#include <sys/module.h>
+
+#include <machine/bus.h>
+#include <machine/cpu.h>
+
+#include <dev/extres/clk/clk.h>
+#include <dev/extres/regulator/regulator.h>
+#include <dev/ofw/ofw_bus_subr.h>
+
+#include <arm/nvidia/tegra_efuse.h>
+
+#include "cpufreq_if.h"
+
+/* CPU voltage table entry */
+struct speedo_entry {
+ uint64_t freq; /* Frequency point */
+ int c0; /* Coeeficient values for */
+ int c1; /* quadratic equation: */
+ int c2; /* c2 * speedo^2 + c1 * speedo + c0 */
+};
+
+struct cpu_volt_def {
+ int min_uvolt; /* Min allowed CPU voltage */
+ int max_uvolt; /* Max allowed CPU voltage */
+ int step_uvolt; /* Step of CPU voltage */
+ int speedo_scale; /* Scaling factor for cvt */
+ int speedo_nitems; /* Size of speedo table */
+ struct speedo_entry *speedo_tbl; /* CPU voltage table */
+};
+
+struct cpu_speed_point {
+ uint64_t freq; /* Frequecy */
+ int uvolt; /* Requested voltage */
+};
+
+static struct speedo_entry tegra210_speedo_tbl[] =
+{
+ {204000000UL, 1007452, -23865, 370},
+ {306000000UL, 1052709, -24875, 370},
+ {408000000UL, 1099069, -25895, 370},
+ {510000000UL, 1146534, -26905, 370},
+ {612000000UL, 1195102, -27915, 370},
+ {714000000UL, 1244773, -28925, 370},
+ {816000000UL, 1295549, -29935, 370},
+ {918000000UL, 1347428, -30955, 370},
+ {1020000000UL, 1400411, -31965, 370},
+ {1122000000UL, 1454497, -32975, 370},
+ {1224000000UL, 1509687, -33985, 370},
+ {1326000000UL, 1565981, -35005, 370},
+ {1428000000UL, 1623379, -36015, 370},
+ {1530000000UL, 1681880, -37025, 370},
+ {1632000000UL, 1741485, -38035, 370},
+ {1734000000UL, 1802194, -39055, 370},
+ {1836000000UL, 1864006, -40065, 370},
+ {1912500000UL, 1910780, -40815, 370},
+ {2014500000UL, 1227000, 0, 0},
+ {2218500000UL, 1227000, 0, 0},
+};
+
+static struct cpu_volt_def tegra210_cpu_volt_def =
+{
+ .min_uvolt = 900000, /* 0.9 V */
+ .max_uvolt = 1227000, /* 1.227 */
+ .step_uvolt = 10000, /* 10 mV */
+ .speedo_scale = 100,
+ .speedo_nitems = nitems(tegra210_speedo_tbl),
+ .speedo_tbl = tegra210_speedo_tbl,
+};
+
+static uint64_t cpu_max_freq[] = {
+ 1912500000UL,
+ 1912500000UL,
+ 2218500000UL,
+ 1785000000UL,
+ 1632000000UL,
+ 1912500000UL,
+ 2014500000UL,
+ 1734000000UL,
+ 1683000000UL,
+ 1555500000UL,
+ 1504500000UL,
+};
+
+static uint64_t cpu_freq_tbl[] = {
+ 204000000UL,
+ 306000000UL,
+ 408000000UL,
+ 510000000UL,
+ 612000000UL,
+ 714000000UL,
+ 816000000UL,
+ 918000000UL,
+ 1020000000UL,
+ 1122000000UL,
+ 1224000000UL,
+ 1326000000UL,
+ 1428000000UL,
+ 1530000000UL,
+ 1632000000UL,
+ 1734000000UL,
+ 1836000000UL,
+ 1912500000UL,
+ 2014500000UL,
+ 2218500000UL,
+};
+
+struct tegra210_cpufreq_softc {
+ device_t dev;
+ phandle_t node;
+
+ clk_t clk_cpu_g;
+ clk_t clk_pll_x;
+ clk_t clk_pll_p;
+ clk_t clk_dfll;
+
+ int process_id;
+ int speedo_id;
+ int speedo_value;
+
+ uint64_t cpu_max_freq;
+ struct cpu_volt_def *cpu_def;
+ struct cpu_speed_point *speed_points;
+ int nspeed_points;
+
+ struct cpu_speed_point *act_speed_point;
+
+ int latency;
+};
+
+static int cpufreq_lowest_freq = 1;
+TUNABLE_INT("hw.tegra210.cpufreq.lowest_freq", &cpufreq_lowest_freq);
+
+#define DIV_ROUND_CLOSEST(val, div) (((val) + ((div) / 2)) / (div))
+
+#define ROUND_UP(val, div) roundup(val, div)
+#define ROUND_DOWN(val, div) rounddown(val, div)
+
+/*
+ * Compute requesetd voltage for given frequency and SoC process variations,
+ * - compute base voltage from speedo value using speedo table
+ * - round up voltage to next regulator step
+ * - clamp it to regulator limits
+ */
+static int
+freq_to_voltage(struct tegra210_cpufreq_softc *sc, uint64_t freq)
+{
+ int uv, scale, min_uvolt, max_uvolt, step_uvolt;
+ struct speedo_entry *ent;
+ int i;
+
+ /* Get speedo entry with higher frequency */
+ ent = NULL;
+ for (i = 0; i < sc->cpu_def->speedo_nitems; i++) {
+ if (sc->cpu_def->speedo_tbl[i].freq >= freq) {
+ ent = &sc->cpu_def->speedo_tbl[i];
+ break;
+ }
+ }
+ if (ent == NULL)
+ ent = &sc->cpu_def->speedo_tbl[sc->cpu_def->speedo_nitems - 1];
+ scale = sc->cpu_def->speedo_scale;
+
+
+ /* uV = (c2 * speedo / scale + c1) * speedo / scale + c0) */
+ uv = DIV_ROUND_CLOSEST(ent->c2 * sc->speedo_value, scale);
+ uv = DIV_ROUND_CLOSEST((uv + ent->c1) * sc->speedo_value, scale) +
+ ent->c0;
+ step_uvolt = sc->cpu_def->step_uvolt;
+ /* Round up it to next regulator step */
+ uv = ROUND_UP(uv, step_uvolt);
+
+ /* Clamp result */
+ min_uvolt = ROUND_UP(sc->cpu_def->min_uvolt, step_uvolt);
+ max_uvolt = ROUND_DOWN(sc->cpu_def->max_uvolt, step_uvolt);
+ if (uv < min_uvolt)
+ uv = min_uvolt;
+ if (uv > max_uvolt)
+ uv = max_uvolt;
+ return (uv);
+
+}
+
+static void
+build_speed_points(struct tegra210_cpufreq_softc *sc) {
+ int i;
+
+ sc->nspeed_points = nitems(cpu_freq_tbl);
+ sc->speed_points = malloc(sizeof(struct cpu_speed_point) *
+ sc->nspeed_points, M_DEVBUF, M_NOWAIT);
+ for (i = 0; i < sc->nspeed_points; i++) {
+ sc->speed_points[i].freq = cpu_freq_tbl[i];
+ sc->speed_points[i].uvolt = freq_to_voltage(sc,
+ cpu_freq_tbl[i]);
+ }
+}
+
+static struct cpu_speed_point *
+get_speed_point(struct tegra210_cpufreq_softc *sc, uint64_t freq)
+{
+ int i;
+
+ if (sc->speed_points[0].freq >= freq)
+ return (sc->speed_points + 0);
+
+ for (i = 0; i < sc->nspeed_points - 1; i++) {
+ if (sc->speed_points[i + 1].freq > freq)
+ return (sc->speed_points + i);
+ }
+
+ return (sc->speed_points + sc->nspeed_points - 1);
+}
+
+static int
+tegra210_cpufreq_settings(device_t dev, struct cf_setting *sets, int *count)
+{
+ struct tegra210_cpufreq_softc *sc;
+ int i, j, max_cnt;
+
+ if (sets == NULL || count == NULL)
+ return (EINVAL);
+
+ sc = device_get_softc(dev);
+ memset(sets, CPUFREQ_VAL_UNKNOWN, sizeof(*sets) * (*count));
+
+ max_cnt = min(sc->nspeed_points, *count);
+ for (i = 0, j = sc->nspeed_points - 1; j >= 0; j--) {
+ if (sc->cpu_max_freq < sc->speed_points[j].freq)
+ continue;
+ sets[i].freq = sc->speed_points[j].freq / 1000000;
+ sets[i].volts = sc->speed_points[j].uvolt / 1000;
+ sets[i].lat = sc->latency;
+ sets[i].dev = dev;
+ i++;
+ }
+ *count = i;
+
+ return (0);
+}
+
+static int
+set_cpu_freq(struct tegra210_cpufreq_softc *sc, uint64_t freq)
+{
+ struct cpu_speed_point *point;
+ int rv;
+
+ point = get_speed_point(sc, freq);
+
+ /* Set PLLX frequency */
+ rv = clk_set_freq(sc->clk_pll_x, point->freq, CLK_SET_ROUND_DOWN);
+ if (rv != 0) {
+ device_printf(sc->dev, "Can't set CPU clock frequency\n");
+ return (rv);
+ }
+
+ sc->act_speed_point = point;
+
+ return (0);
+}
+
+static int
+tegra210_cpufreq_set(device_t dev, const struct cf_setting *cf)
+{
+ struct tegra210_cpufreq_softc *sc;
+ uint64_t freq;
+ int rv;
+
+ if (cf == NULL || cf->freq < 0)
+ return (EINVAL);
+
+ sc = device_get_softc(dev);
+
+ freq = cf->freq;
+ if (freq < cpufreq_lowest_freq)
+ freq = cpufreq_lowest_freq;
+ freq *= 1000000;
+ if (freq >= sc->cpu_max_freq)
+ freq = sc->cpu_max_freq;
+ rv = set_cpu_freq(sc, freq);
+
+ return (rv);
+}
+
+static int
+tegra210_cpufreq_get(device_t dev, struct cf_setting *cf)
+{
+ struct tegra210_cpufreq_softc *sc;
+
+ if (cf == NULL)
+ return (EINVAL);
+
+ sc = device_get_softc(dev);
+ memset(cf, CPUFREQ_VAL_UNKNOWN, sizeof(*cf));
+ cf->dev = NULL;
+ cf->freq = sc->act_speed_point->freq / 1000000;
+ cf->volts = sc->act_speed_point->uvolt / 1000;
+ /* Transition latency in us. */
+ cf->lat = sc->latency;
+ /* Driver providing this setting. */
+ cf->dev = dev;
+
+ return (0);
+}
+
+
+static int
+tegra210_cpufreq_type(device_t dev, int *type)
+{
+
+ if (type == NULL)
+ return (EINVAL);
+ *type = CPUFREQ_TYPE_ABSOLUTE;
+
+ return (0);
+}
+
+static int
+get_fdt_resources(struct tegra210_cpufreq_softc *sc, phandle_t node)
+{
+ int rv;
+ device_t parent_dev;
+
+ parent_dev = device_get_parent(sc->dev);
+
+ rv = clk_get_by_ofw_name(parent_dev, 0, "cpu_g", &sc->clk_cpu_g);
+ if (rv != 0) {
+ device_printf(sc->dev, "Cannot get 'cpu_g' clock: %d\n", rv);
+ return (ENXIO);
+ }
+
+ rv = clk_get_by_ofw_name(parent_dev, 0, "pll_x", &sc->clk_pll_x);
+ if (rv != 0) {
+ device_printf(sc->dev, "Cannot get 'pll_x' clock\n");
+ return (ENXIO);
+ }
+ rv = clk_get_by_ofw_name(parent_dev, 0, "pll_p", &sc->clk_pll_p);
+ if (rv != 0) {
+ device_printf(parent_dev, "Cannot get 'pll_p' clock\n");
+ return (ENXIO);
+ }
+ rv = clk_get_by_ofw_name(parent_dev, 0, "dfll", &sc->clk_dfll);
+
+ /* XXX DPLL is not implemented yet */
+#if 0
+ if (rv != 0) {
+ device_printf(sc->dev, "Cannot get 'dfll' clock\n");
+ return (ENXIO);
+ }
+#endif
+ return (0);
+}
+
+static void
+tegra210_cpufreq_identify(driver_t *driver, device_t parent)
+{
+ phandle_t root;
+
+ root = OF_finddevice("/");
+ if (!ofw_bus_node_is_compatible(root, "nvidia,tegra210"))
+ return;
+
+ if (device_get_unit(parent) != 0)
+ return;
+ if (device_find_child(parent, "tegra210_cpufreq", -1) != NULL)
+ return;
+ if (BUS_ADD_CHILD(parent, 0, "tegra210_cpufreq", -1) == NULL)
+ device_printf(parent, "add child failed\n");
+}
+
+static int
+tegra210_cpufreq_probe(device_t dev)
+{
+
+ device_set_desc(dev, "CPU Frequency Control");
+
+ return (0);
+}
+
+static int
+tegra210_cpufreq_attach(device_t dev)
+{
+ struct tegra210_cpufreq_softc *sc;
+ uint64_t freq;
+ int rv;
+
+ sc = device_get_softc(dev);
+ sc->dev = dev;
+ sc->node = ofw_bus_get_node(device_get_parent(dev));
+
+ sc->process_id = tegra_sku_info.cpu_process_id;
+ sc->speedo_id = tegra_sku_info.cpu_speedo_id;
+ sc->speedo_value = tegra_sku_info.cpu_speedo_value;
+
+ sc->cpu_def = &tegra210_cpu_volt_def;
+
+ rv = get_fdt_resources(sc, sc->node);
+ if (rv != 0) {
+ return (rv);
+ }
+
+ build_speed_points(sc);
+
+ rv = clk_get_freq(sc->clk_cpu_g, &freq);
+ if (rv != 0) {
+ device_printf(dev, "Can't get CPU clock frequency\n");
+ return (rv);
+ }
+ if (sc->speedo_id < nitems(cpu_max_freq))
+ sc->cpu_max_freq = cpu_max_freq[sc->speedo_id];
+ else
+ sc->cpu_max_freq = cpu_max_freq[0];
+ sc->act_speed_point = get_speed_point(sc, freq);
+
+ /* Set safe startup CPU frequency. */
+ rv = set_cpu_freq(sc, 1632000000);
+ if (rv != 0) {
+ device_printf(dev, "Can't set initial CPU clock frequency\n");
+ return (rv);
+ }
+
+ /* This device is controlled by cpufreq(4). */
+ cpufreq_register(dev);
+
+ return (0);
+}
+
+static int
+tegra210_cpufreq_detach(device_t dev)
+{
+ struct tegra210_cpufreq_softc *sc;
+
+ sc = device_get_softc(dev);
+ cpufreq_unregister(dev);
+
+ if (sc->clk_cpu_g != NULL)
+ clk_release(sc->clk_cpu_g);
+ if (sc->clk_pll_x != NULL)
+ clk_release(sc->clk_pll_x);
+ if (sc->clk_pll_p != NULL)
+ clk_release(sc->clk_pll_p);
+ if (sc->clk_dfll != NULL)
+ clk_release(sc->clk_dfll);
+ return (0);
+}
+
+static device_method_t tegra210_cpufreq_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_identify, tegra210_cpufreq_identify),
+ DEVMETHOD(device_probe, tegra210_cpufreq_probe),
+ DEVMETHOD(device_attach, tegra210_cpufreq_attach),
+ DEVMETHOD(device_detach, tegra210_cpufreq_detach),
+
+ /* cpufreq interface */
+ DEVMETHOD(cpufreq_drv_set, tegra210_cpufreq_set),
+ DEVMETHOD(cpufreq_drv_get, tegra210_cpufreq_get),
+ DEVMETHOD(cpufreq_drv_settings, tegra210_cpufreq_settings),
+ DEVMETHOD(cpufreq_drv_type, tegra210_cpufreq_type),
+
+ DEVMETHOD_END
+};
+
+static devclass_t tegra210_cpufreq_devclass;
+static DEFINE_CLASS_0(tegra210_cpufreq, tegra210_cpufreq_driver,
+ tegra210_cpufreq_methods, sizeof(struct tegra210_cpufreq_softc));
+DRIVER_MODULE(tegra210_cpufreq, cpu, tegra210_cpufreq_driver,
+ tegra210_cpufreq_devclass, NULL, NULL);
diff --git a/sys/arm64/nvidia/tegra210/tegra210_pinmux.c b/sys/arm64/nvidia/tegra210/tegra210_pinmux.c
new file mode 100644
index 000000000000..9f4f05368026
--- /dev/null
+++ b/sys/arm64/nvidia/tegra210/tegra210_pinmux.c
@@ -0,0 +1,758 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
+ *
+ * Copyright 2020 Michal Meloun <mmel@FreeBSD.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+/*
+ * Pin multiplexer driver for Tegra SoCs.
+ */
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/malloc.h>
+#include <sys/rman.h>
+
+#include <machine/bus.h>
+
+#include <dev/fdt/fdt_common.h>
+#include <dev/fdt/fdt_pinctrl.h>
+#include <dev/ofw/openfirm.h>
+#include <dev/ofw/ofw_bus.h>
+#include <dev/ofw/ofw_bus_subr.h>
+
+/* Pin multipexor register. */
+#define TEGRA_MUX_FUNCTION_MASK 0x03
+#define TEGRA_MUX_FUNCTION_SHIFT 0
+#define TEGRA_MUX_PUPD_MASK 0x03
+#define TEGRA_MUX_PUPD_SHIFT 2
+#define TEGRA_MUX_TRISTATE_SHIFT 4
+#define TEGRA_MUX_ENABLE_INPUT_SHIFT 5
+#define TEGRA_MUX_OPEN_DRAIN_SHIFT 6
+#define TEGRA_MUX_LOCK_SHIFT 7
+#define TEGRA_MUX_IORESET_SHIFT 8
+#define TEGRA_MUX_RCV_SEL_SHIFT 9
+
+
+/* Pin goup register. */
+#define TEGRA_GRP_HSM_SHIFT 2
+#define TEGRA_GRP_SCHMT_SHIFT 3
+#define TEGRA_GRP_DRV_TYPE_SHIFT 6
+#define TEGRA_GRP_DRV_TYPE_MASK 0x03
+#define TEGRA_GRP_DRV_DRVDN_SLWR_SHIFT 28
+#define TEGRA_GRP_DRV_DRVDN_SLWR_MASK 0x03
+#define TEGRA_GRP_DRV_DRVUP_SLWF_SHIFT 30
+#define TEGRA_GRP_DRV_DRVUP_SLWF_MASK 0x03
+
+struct pinmux_softc {
+ device_t dev;
+ struct resource *pad_mem_res;
+ struct resource *mux_mem_res;
+};
+
+static struct ofw_compat_data compat_data[] = {
+ {"nvidia,tegra210-pinmux", 1},
+ {NULL, 0},
+};
+
+enum prop_id {
+ PROP_ID_PULL,
+ PROP_ID_TRISTATE,
+ PROP_ID_ENABLE_INPUT,
+ PROP_ID_OPEN_DRAIN,
+ PROP_ID_LOCK,
+ PROP_ID_IORESET,
+ PROP_ID_RCV_SEL,
+ PROP_ID_HIGH_SPEED_MODE,
+ PROP_ID_SCHMITT,
+ PROP_ID_LOW_POWER_MODE,
+ PROP_ID_DRIVE_DOWN_STRENGTH,
+ PROP_ID_DRIVE_UP_STRENGTH,
+ PROP_ID_SLEW_RATE_FALLING,
+ PROP_ID_SLEW_RATE_RISING,
+ PROP_ID_DRIVE_TYPE,
+
+ PROP_ID_MAX_ID
+};
+
+/* Numeric based parameters. */
+static const struct prop_name {
+ const char *name;
+ enum prop_id id;
+} prop_names[] = {
+ {"nvidia,pull", PROP_ID_PULL},
+ {"nvidia,tristate", PROP_ID_TRISTATE},
+ {"nvidia,enable-input", PROP_ID_ENABLE_INPUT},
+ {"nvidia,open-drain", PROP_ID_OPEN_DRAIN},
+ {"nvidia,lock", PROP_ID_LOCK},
+ {"nvidia,io-reset", PROP_ID_IORESET},
+ {"nvidia,rcv-sel", PROP_ID_RCV_SEL},
+ {"nvidia,io-hv", PROP_ID_RCV_SEL},
+ {"nvidia,high-speed-mode", PROP_ID_HIGH_SPEED_MODE},
+ {"nvidia,schmitt", PROP_ID_SCHMITT},
+ {"nvidia,low-power-mode", PROP_ID_LOW_POWER_MODE},
+ {"nvidia,pull-down-strength", PROP_ID_DRIVE_DOWN_STRENGTH},
+ {"nvidia,pull-up-strength", PROP_ID_DRIVE_UP_STRENGTH},
+ {"nvidia,slew-rate-falling", PROP_ID_SLEW_RATE_FALLING},
+ {"nvidia,slew-rate-rising", PROP_ID_SLEW_RATE_RISING},
+ {"nvidia,drive-type", PROP_ID_DRIVE_TYPE},
+};
+
+/*
+ * configuration for one pin group.
+ */
+struct pincfg {
+ char *function;
+ int params[PROP_ID_MAX_ID];
+};
+#define GPIO_BANK_A 0
+#define GPIO_BANK_B 1
+#define GPIO_BANK_C 2
+#define GPIO_BANK_D 3
+#define GPIO_BANK_E 4
+#define GPIO_BANK_F 5
+#define GPIO_BANK_G 6
+#define GPIO_BANK_H 7
+#define GPIO_BANK_I 8
+#define GPIO_BANK_J 9
+#define GPIO_BANK_K 10
+#define GPIO_BANK_L 11
+#define GPIO_BANK_M 12
+#define GPIO_BANK_N 13
+#define GPIO_BANK_O 14
+#define GPIO_BANK_P 15
+#define GPIO_BANK_Q 16
+#define GPIO_BANK_R 17
+#define GPIO_BANK_S 18
+#define GPIO_BANK_T 19
+#define GPIO_BANK_U 20
+#define GPIO_BANK_V 21
+#define GPIO_BANK_W 22
+#define GPIO_BANK_X 23
+#define GPIO_BANK_Y 24
+#define GPIO_BANK_Z 25
+#define GPIO_BANK_AA 26
+#define GPIO_BANK_BB 27
+#define GPIO_BANK_CC 28
+#define GPIO_BANK_DD 29
+#define GPIO_BANK_EE 30
+#define GPIO_NUM(b, p) (8 * (b) + (p))
+
+struct tegra_grp {
+ char *name;
+ bus_size_t reg;
+ int drvdn_shift;
+ int drvdn_mask;
+ int drvup_shift;
+ int drvup_mask;
+};
+
+#define GRP(r, nm, dn_s, dn_w, up_s, up_w) \
+{ \
+ .name = #nm, \
+ .reg = r - 0x8D4, \
+ .drvdn_shift = dn_s, \
+ .drvdn_mask = (1 << dn_w) - 1, \
+ .drvup_shift = up_s, \
+ .drvup_mask = (1 << up_w) - 1, \
+}
+
+/* Use register offsets from TRM */
+static const struct tegra_grp pin_grp_tbl[] = {
+ GRP(0x9c0, pa6, 12, 5, 20, 5),
+ GRP(0x9c4, pcc7, 12, 5, 20, 5),
+ GRP(0x9c8, pe6, 12, 5, 20, 5),
+ GRP(0x9cc, pe7, 12, 5, 20, 5),
+ GRP(0x9d0, ph6, 12, 5, 20, 5),
+ GRP(0x9d4, pk0, 0, 0, 0, 0),
+ GRP(0x9d8, pk1, 0, 0, 0, 0),
+ GRP(0x9dc, pk2, 0, 0, 0, 0),
+ GRP(0x9e0, pk3, 0, 0, 0, 0),
+ GRP(0x9e4, pk4, 0, 0, 0, 0),
+ GRP(0x9e8, pk5, 0, 0, 0, 0),
+ GRP(0x9ec, pk6, 0, 0, 0, 0),
+ GRP(0x9f0, pk7, 0, 0, 0, 0),
+ GRP(0x9f4, pl0, 0, 0, 0, 0),
+ GRP(0x9f8, pl1, 0, 0, 0, 0),
+ GRP(0x9fc, pz0, 12, 7, 20, 7),
+ GRP(0xa00, pz1, 12, 7, 20, 7),
+ GRP(0xa04, pz2, 12, 7, 20, 7),
+ GRP(0xa08, pz3, 12, 7, 20, 7),
+ GRP(0xa0c, pz4, 12, 7, 20, 7),
+ GRP(0xa10, pz5, 12, 7, 20, 7),
+ GRP(0xa98, sdmmc1, 12, 7, 20, 7),
+ GRP(0xa9c, sdmmc2, 2, 6, 8, 6),
+ GRP(0xab0, sdmmc3, 12, 7, 20, 7),
+ GRP(0xab4, sdmmc4, 2, 6, 8, 6),
+};
+
+struct tegra_mux {
+ struct tegra_grp grp;
+ char *name;
+ bus_size_t reg;
+ char *functions[4];
+ int gpio_num;
+
+};
+
+#define GMUX(r, gb, gi, nm, f1, f2, f3, f4, gr, dn_s, dn_w, up_s, up_w) \
+{ \
+ .name = #nm, \
+ .reg = r, \
+ .gpio_num = GPIO_NUM(GPIO_BANK_##gb, gi), \
+ .functions = {#f1, #f2, #f3, #f4}, \
+ .grp.name = #nm, \
+ .grp.reg = gr - 0x8D4, \
+ .grp.drvdn_shift = dn_s, \
+ .grp.drvdn_mask = (1 << dn_w) - 1, \
+ .grp.drvup_shift = up_s, \
+ .grp.drvup_mask = (1 << up_w) - 1, \
+}
+
+#define FMUX(r, nm, f1, f2, f3, f4, gr, dn_s, dn_w, up_s, up_w) \
+{ \
+ .name = #nm, \
+ .reg = r, \
+ .gpio_num = -1, \
+ .functions = {#f1, #f2, #f3, #f4}, \
+ .grp.name = #nm, \
+ .grp.reg = gr - 0x8D4, \
+ .grp.drvdn_shift = dn_s, \
+ .grp.drvdn_mask = (1 << dn_w) - 1, \
+ .grp.drvup_shift = up_s, \
+ .grp.drvup_mask = (1 << up_w) - 1, \
+}
+
+static const struct tegra_mux pin_mux_tbl[] = {
+ GMUX(0x000, M, 0, sdmmc1_clk_pm0, sdmmc1, rsvd1, rsvd2, rsvd3, -1, 0, 0, 0, 0),
+ GMUX(0x004, M, 1, sdmmc1_cmd_pm1, sdmmc1, spi3, rsvd2, rsvd3, -1, 0, 0, 0, 0),
+ GMUX(0x008, M, 2, sdmmc1_dat3_pm2, sdmmc1, spi3, rsvd2, rsvd3, -1, 0, 0, 0, 0),
+ GMUX(0x00c, M, 3, sdmmc1_dat2_pm3, sdmmc1, spi3, rsvd2, rsvd3, -1, 0, 0, 0, 0),
+ GMUX(0x010, M, 4, sdmmc1_dat1_pm4, sdmmc1, spi3, rsvd2, rsvd3, -1, 0, 0, 0, 0),
+ GMUX(0x014, M, 5, sdmmc1_dat0_pm5, sdmmc1, rsvd1, rsvd2, rsvd3, -1, 0, 0, 0, 0),
+ GMUX(0x01c, P, 0, sdmmc3_clk_pp0, sdmmc3, rsvd1, rsvd2, rsvd3, -1, 0, 0, 0, 0),
+ GMUX(0x020, P, 1, sdmmc3_cmd_pp1, sdmmc3, rsvd1, rsvd2, rsvd3, -1, 0, 0, 0, 0),
+ GMUX(0x024, P, 5, sdmmc3_dat0_pp5, sdmmc3, rsvd1, rsvd2, rsvd3, -1, 0, 0, 0, 0),
+ GMUX(0x028, P, 4, sdmmc3_dat1_pp4, sdmmc3, rsvd1, rsvd2, rsvd3, -1, 0, 0, 0, 0),
+ GMUX(0x02c, P, 3, sdmmc3_dat2_pp3, sdmmc3, rsvd1, rsvd2, rsvd3, -1, 0, 0, 0, 0),
+ GMUX(0x030, P, 2, sdmmc3_dat3_pp2, sdmmc3, rsvd1, rsvd2, rsvd3, -1, 0, 0, 0, 0),
+ GMUX(0x038, A, 0, pex_l0_rst_n_pa0, pe0, rsvd1, rsvd2, rsvd3, 0xa5c, 12, 5, 20, 5),
+ GMUX(0x03c, A, 1, pex_l0_clkreq_n_pa1, pe0, rsvd1, rsvd2, rsvd3, 0xa58, 12, 5, 20, 5),
+ GMUX(0x040, A, 2, pex_wake_n_pa2, pe, rsvd1, rsvd2, rsvd3, 0xa68, 12, 5, 20, 5),
+ GMUX(0x044, A, 3, pex_l1_rst_n_pa3, pe1, rsvd1, rsvd2, rsvd3, 0xa64, 12, 5, 20, 5),
+ GMUX(0x048, A, 4, pex_l1_clkreq_n_pa4, pe1, rsvd1, rsvd2, rsvd3, 0xa60, 12, 5, 20, 5),
+ GMUX(0x04c, A, 5, sata_led_active_pa5, sata, rsvd1, rsvd2, rsvd3, 0xa94, 12, 5, 20, 5),
+ GMUX(0x050, C, 0, spi1_mosi_pc0, spi1, rsvd1, rsvd2, rsvd3, 0xae0, 0, 0, 0, 0),
+ GMUX(0x054, C, 1, spi1_miso_pc1, spi1, rsvd1, rsvd2, rsvd3, 0xadc, 0, 0, 0, 0),
+ GMUX(0x058, C, 2, spi1_sck_pc2, spi1, rsvd1, rsvd2, rsvd3, 0xae4, 0, 0, 0, 0),
+ GMUX(0x05c, C, 3, spi1_cs0_pc3, spi1, rsvd1, rsvd2, rsvd3, 0xad4, 0, 0, 0, 0),
+ GMUX(0x060, C, 4, spi1_cs1_pc4, spi1, rsvd1, rsvd2, rsvd3, 0xad8, 0, 0, 0, 0),
+ GMUX(0x064, B, 4, spi2_mosi_pb4, spi2, dtv, rsvd2, rsvd3, 0xaf4, 0, 0, 0, 0),
+ GMUX(0x068, B, 5, spi2_miso_pb5, spi2, dtv, rsvd2, rsvd3, 0xaf0, 0, 0, 0, 0),
+ GMUX(0x06c, B, 6, spi2_sck_pb6, spi2, dtv, rsvd2, rsvd3, 0xaf8, 0, 0, 0, 0),
+ GMUX(0x070, B, 7, spi2_cs0_pb7, spi2, dtv, rsvd2, rsvd3, 0xae8, 0, 0, 0, 0),
+ GMUX(0x074, DD, 0, spi2_cs1_pdd0, spi2, rsvd1, rsvd2, rsvd3, 0xaec, 0, 0, 0, 0),
+ GMUX(0x078, C, 7, spi4_mosi_pc7, spi4, rsvd1, rsvd2, rsvd3, 0xb04, 0, 0, 0, 0),
+ GMUX(0x07c, D, 0, spi4_miso_pd0, spi4, rsvd1, rsvd2, rsvd3, 0xb00, 0, 0, 0, 0),
+ GMUX(0x080, C, 5, spi4_sck_pc5, spi4, rsvd1, rsvd2, rsvd3, 0xb08, 0, 0, 0, 0),
+ GMUX(0x084, C, 6, spi4_cs0_pc6, spi4, rsvd1, rsvd2, rsvd3, 0xafc, 0, 0, 0, 0),
+ GMUX(0x088, EE, 0, qspi_sck_pee0, qspi, rsvd1, rsvd2, rsvd3, 0xa90, 0, 0, 0, 0),
+ GMUX(0x08c, EE, 1, qspi_cs_n_pee1, qspi, rsvd1, rsvd2, rsvd3, -1, 0, 0, 0, 0),
+ GMUX(0x090, EE, 2, qspi_io0_pee2, qspi, rsvd1, rsvd2, rsvd3, -1, 0, 0, 0, 0),
+ GMUX(0x094, EE, 3, qspi_io1_pee3, qspi, rsvd1, rsvd2, rsvd3, -1, 0, 0, 0, 0),
+ GMUX(0x098, EE, 4, qspi_io2_pee4, qspi, rsvd1, rsvd2, rsvd3, -1, 0, 0, 0, 0),
+ GMUX(0x09c, EE, 5, qspi_io3_pee5, qspi, rsvd1, rsvd2, rsvd3, -1, 0, 0, 0, 0),
+ GMUX(0x0a4, E, 0, dmic1_clk_pe0, dmic1, i2s3, rsvd2, rsvd3, 0x984, 12, 5, 20, 5),
+ GMUX(0x0a8, E, 1, dmic1_dat_pe1, dmic1, i2s3, rsvd2, rsvd3, 0x988, 12, 5, 20, 5),
+ GMUX(0x0ac, E, 2, dmic2_clk_pe2, dmic2, i2s3, rsvd2, rsvd3, 0x98c, 12, 5, 20, 5),
+ GMUX(0x0b0, E, 3, dmic2_dat_pe3, dmic2, i2s3, rsvd2, rsvd3, 0x990, 12, 5, 20, 5),
+ GMUX(0x0b4, E, 4, dmic3_clk_pe4, dmic3, i2s5a, rsvd2, rsvd3, 0x994, 12, 5, 20, 5),
+ GMUX(0x0b8, E, 5, dmic3_dat_pe5, dmic3, i2s5a, rsvd2, rsvd3, 0x998, 12, 5, 20, 5),
+ GMUX(0x0bc, J, 1, gen1_i2c_scl_pj1, i2c1, rsvd1, rsvd2, rsvd3, 0x9a8, 12, 5, 20, 5),
+ GMUX(0x0c0, J, 0, gen1_i2c_sda_pj0, i2c1, rsvd1, rsvd2, rsvd3, 0x9ac, 12, 5, 20, 5),
+ GMUX(0x0c4, J, 2, gen2_i2c_scl_pj2, i2c2, rsvd1, rsvd2, rsvd3, 0x9b0, 12, 5, 20, 5),
+ GMUX(0x0c8, J, 3, gen2_i2c_sda_pj3, i2c2, rsvd1, rsvd2, rsvd3, 0x9b4, 12, 5, 20, 5),
+ GMUX(0x0cc, F, 0, gen3_i2c_scl_pf0, i2c3, rsvd1, rsvd2, rsvd3, 0x9b8, 12, 5, 20, 5),
+ GMUX(0x0d0, F, 1, gen3_i2c_sda_pf1, i2c3, rsvd1, rsvd2, rsvd3, 0x9bc, 12, 5, 20, 5),
+ GMUX(0x0d4, S, 2, cam_i2c_scl_ps2, i2c3, i2cvi, rsvd2, rsvd3, 0x934, 12, 5, 20, 5),
+ GMUX(0x0d8, S, 3, cam_i2c_sda_ps3, i2c3, i2cvi, rsvd2, rsvd3, 0x938, 12, 5, 20, 5),
+ GMUX(0x0dc, Y, 3, pwr_i2c_scl_py3, i2cpmu, rsvd1, rsvd2, rsvd3, 0xa6c, 12, 5, 20, 5),
+ GMUX(0x0e0, Y, 4, pwr_i2c_sda_py4, i2cpmu, rsvd1, rsvd2, rsvd3, 0xa70, 12, 5, 20, 5),
+ GMUX(0x0e4, U, 0, uart1_tx_pu0, uarta, rsvd1, rsvd2, rsvd3, 0xb28, 12, 5, 20, 5),
+ GMUX(0x0e8, U, 1, uart1_rx_pu1, uarta, rsvd1, rsvd2, rsvd3, 0xb24, 12, 5, 20, 5),
+ GMUX(0x0ec, U, 2, uart1_rts_pu2, uarta, rsvd1, rsvd2, rsvd3, 0xb20, 12, 5, 20, 5),
+ GMUX(0x0f0, U, 3, uart1_cts_pu3, uarta, rsvd1, rsvd2, rsvd3, 0xb1c, 12, 5, 20, 5),
+ GMUX(0x0f4, G, 0, uart2_tx_pg0, uartb, i2s4a, spdif, uart, 0xb38, 12, 5, 20, 5),
+ GMUX(0x0f8, G, 1, uart2_rx_pg1, uartb, i2s4a, spdif, uart, 0xb34, 12, 5, 20, 5),
+ GMUX(0x0fc, G, 2, uart2_rts_pg2, uartb, i2s4a, rsvd2, uart, 0xb30, 12, 5, 20, 5),
+ GMUX(0x100, G, 3, uart2_cts_pg3, uartb, i2s4a, rsvd2, uart, 0xb2c, 12, 5, 20, 5),
+ GMUX(0x104, D, 1, uart3_tx_pd1, uartc, spi4, rsvd2, rsvd3, 0xb48, 12, 5, 20, 5),
+ GMUX(0x108, D, 2, uart3_rx_pd2, uartc, spi4, rsvd2, rsvd3, 0xb44, 12, 5, 20, 5),
+ GMUX(0x10c, D, 3, uart3_rts_pd3, uartc, spi4, rsvd2, rsvd3, 0xb40, 12, 5, 20, 5),
+ GMUX(0x110, D, 4, uart3_cts_pd4, uartc, spi4, rsvd2, rsvd3, 0xb3c, 12, 5, 20, 5),
+ GMUX(0x114, I, 4, uart4_tx_pi4, uartd, uart, rsvd2, rsvd3, 0xb58, 12, 5, 20, 5),
+ GMUX(0x118, I, 5, uart4_rx_pi5, uartd, uart, rsvd2, rsvd3, 0xb54, 12, 5, 20, 5),
+ GMUX(0x11c, I, 6, uart4_rts_pi6, uartd, uart, rsvd2, rsvd3, 0xb50, 12, 5, 20, 5),
+ GMUX(0x120, I, 7, uart4_cts_pi7, uartd, uart, rsvd2, rsvd3, 0xb4c, 12, 5, 20, 5),
+ GMUX(0x124, B, 0, dap1_fs_pb0, i2s1, rsvd1, rsvd2, rsvd3, 0x95c, 0, 0, 0, 0),
+ GMUX(0x128, B, 1, dap1_din_pb1, i2s1, rsvd1, rsvd2, rsvd3, 0x954, 0, 0, 0, 0),
+ GMUX(0x12c, B, 2, dap1_dout_pb2, i2s1, rsvd1, rsvd2, rsvd3, 0x958, 0, 0, 0, 0),
+ GMUX(0x130, B, 3, dap1_sclk_pb3, i2s1, rsvd1, rsvd2, rsvd3, 0x960, 0, 0, 0, 0),
+ GMUX(0x134, AA, 0, dap2_fs_paa0, i2s2, rsvd1, rsvd2, rsvd3, 0x96c, 0, 0, 0, 0),
+ GMUX(0x138, AA, 2, dap2_din_paa2, i2s2, rsvd1, rsvd2, rsvd3, 0x964, 0, 0, 0, 0),
+ GMUX(0x13c, AA, 3, dap2_dout_paa3, i2s2, rsvd1, rsvd2, rsvd3, 0x968, 0, 0, 0, 0),
+ GMUX(0x140, AA, 1, dap2_sclk_paa1, i2s2, rsvd1, rsvd2, rsvd3, 0x970, 0, 0, 0, 0),
+ GMUX(0x144, J, 4, dap4_fs_pj4, i2s4b, rsvd1, rsvd2, rsvd3, 0x97c, 12, 5, 20, 5),
+ GMUX(0x148, J, 5, dap4_din_pj5, i2s4b, rsvd1, rsvd2, rsvd3, 0x974, 12, 5, 20, 5),
+ GMUX(0x14c, J, 6, dap4_dout_pj6, i2s4b, rsvd1, rsvd2, rsvd3, 0x978, 12, 5, 20, 5),
+ GMUX(0x150, J, 7, dap4_sclk_pj7, i2s4b, rsvd1, rsvd2, rsvd3, 0x980, 12, 5, 20, 5),
+ GMUX(0x154, S, 0, cam1_mclk_ps0, extperiph3, rsvd1, rsvd2, rsvd3, 0x918, 12, 5, 20, 5),
+ GMUX(0x158, S, 1, cam2_mclk_ps1, extperiph3, rsvd1, rsvd2, rsvd3, 0x924, 12, 5, 20, 5),
+ FMUX(0x15c, jtag_rtck, jtag, rsvd1, rsvd2, rsvd3, 0xa2c, 12, 5, 20, 5),
+ FMUX(0x160, clk_32k_in, clk, rsvd1, rsvd2, rsvd3, 0x940, 12, 5, 20, 5),
+ GMUX(0x164, Y, 5, clk_32k_out_py5, soc, blink, rsvd2, rsvd3, 0x944, 12, 5, 20, 5),
+ FMUX(0x168, batt_bcl, bcl, rsvd1, rsvd2, rsvd3, 0x8f8, 12, 5, 20, 5),
+ FMUX(0x16c, clk_req, sys, rsvd1, rsvd2, rsvd3, 0x948, 12, 5, 20, 5),
+ FMUX(0x170, cpu_pwr_req, cpu, rsvd1, rsvd2, rsvd3, 0x950, 12, 5, 20, 5),
+ FMUX(0x174, pwr_int_n, pmi, rsvd1, rsvd2, rsvd3, 0xa74, 12, 5, 20, 5),
+ FMUX(0x178, shutdown, shutdown, rsvd1, rsvd2, rsvd3, 0xac8, 12, 5, 20, 5),
+ FMUX(0x17c, core_pwr_req, core, rsvd1, rsvd2, rsvd3, 0x94c, 12, 5, 20, 5),
+ GMUX(0x180, BB, 0, aud_mclk_pbb0, aud, rsvd1, rsvd2, rsvd3, 0x8f4, 12, 5, 20, 5),
+ GMUX(0x184, BB, 1, dvfs_pwm_pbb1, rsvd0, cldvfs, spi3, rsvd3, 0x9a4, 12, 5, 20, 5),
+ GMUX(0x188, BB, 2, dvfs_clk_pbb2, rsvd0, cldvfs, spi3, rsvd3, 0x9a0, 12, 5, 20, 5),
+ GMUX(0x18c, BB, 3, gpio_x1_aud_pbb3, rsvd0, rsvd1, spi3, rsvd3, 0xa14, 12, 5, 20, 5),
+ GMUX(0x190, BB, 4, gpio_x3_aud_pbb4, rsvd0, rsvd1, spi3, rsvd3, 0xa18, 12, 5, 20, 5),
+ GMUX(0x194, CC, 7, pcc7, rsvd0, rsvd1, rsvd2, rsvd3, -1, 0, 0, 0, 0),
+ GMUX(0x198, CC, 0, hdmi_cec_pcc0, cec, rsvd1, rsvd2, rsvd3, 0xa24, 12, 5, 20, 5),
+ GMUX(0x19c, CC, 1, hdmi_int_dp_hpd_pcc1, dp, rsvd1, rsvd2, rsvd3, 0xa28, 12, 5, 20, 5),
+ GMUX(0x1a0, CC, 2, spdif_out_pcc2, spdif, rsvd1, rsvd2, rsvd3, 0xad0, 12, 5, 20, 5),
+ GMUX(0x1a4, CC, 3, spdif_in_pcc3, spdif, rsvd1, rsvd2, rsvd3, 0xacc, 12, 5, 20, 5),
+ GMUX(0x1a8, CC, 4, usb_vbus_en0_pcc4, usb, rsvd1, rsvd2, rsvd3, 0xb5c, 12, 5, 20, 5),
+ GMUX(0x1ac, CC, 5, usb_vbus_en1_pcc5, usb, rsvd1, rsvd2, rsvd3, 0xb60, 12, 5, 20, 5),
+ GMUX(0x1b0, CC, 6, dp_hpd0_pcc6, dp, rsvd1, rsvd2, rsvd3, 0x99c, 12, 5, 20, 5),
+ GMUX(0x1b4, H, 0, wifi_en_ph0, rsvd0, rsvd1, rsvd2, rsvd3, 0xb64, 12, 5, 20, 5),
+ GMUX(0x1b8, H, 1, wifi_rst_ph1, rsvd0, rsvd1, rsvd2, rsvd3, 0xb68, 12, 5, 20, 5),
+ GMUX(0x1bc, H, 2, wifi_wake_ap_ph2, rsvd0, rsvd1, rsvd2, rsvd3, 0xb6c, 12, 5, 20, 5),
+ GMUX(0x1c0, H, 3, ap_wake_bt_ph3, rsvd0, uartb, spdif, rsvd3, 0x8ec, 12, 5, 20, 5),
+ GMUX(0x1c4, H, 4, bt_rst_ph4, rsvd0, uartb, spdif, rsvd3, 0x8fc, 12, 5, 20, 5),
+ GMUX(0x1c8, H, 5, bt_wake_ap_ph5, rsvd0, rsvd1, rsvd2, rsvd3, 0x900, 12, 5, 20, 5),
+ GMUX(0x1cc, H, 7, ap_wake_nfc_ph7, rsvd0, rsvd1, rsvd2, rsvd3, 0x8f0, 12, 5, 20, 5),
+ GMUX(0x1d0, I, 0, nfc_en_pi0, rsvd0, rsvd1, rsvd2, rsvd3, 0xa50, 12, 5, 20, 5),
+ GMUX(0x1d4, I, 1, nfc_int_pi1, rsvd0, rsvd1, rsvd2, rsvd3, 0xa54, 12, 5, 20, 5),
+ GMUX(0x1d8, I, 2, gps_en_pi2, rsvd0, rsvd1, rsvd2, rsvd3, 0xa1c, 12, 5, 20, 5),
+ GMUX(0x1dc, I, 3, gps_rst_pi3, rsvd0, rsvd1, rsvd2, rsvd3, 0xa20, 12, 5, 20, 5),
+ GMUX(0x1e0, S, 4, cam_rst_ps4, vgp1, rsvd1, rsvd2, rsvd3, 0x93c, 12, 5, 20, 5),
+ GMUX(0x1e4, S, 5, cam_af_en_ps5, vimclk, vgp2, rsvd2, rsvd3, 0x92c, 12, 5, 20, 5),
+ GMUX(0x1e8, S, 6, cam_flash_en_ps6, vimclk, vgp3, rsvd2, rsvd3, 0x930, 12, 5, 20, 5),
+ GMUX(0x1ec, S, 7, cam1_pwdn_ps7, vgp4, rsvd1, rsvd2, rsvd3, 0x91c, 12, 5, 20, 5),
+ GMUX(0x1f0, T, 0, cam2_pwdn_pt0, vgp5, rsvd1, rsvd2, rsvd3, 0x928, 12, 5, 20, 5),
+ GMUX(0x1f4, T, 1, cam1_strobe_pt1, vgp6, rsvd1, rsvd2, rsvd3, 0x920, 12, 5, 20, 5),
+ GMUX(0x1f8, Y, 2, lcd_te_py2, displaya, rsvd1, rsvd2, rsvd3, 0xa44, 12, 5, 20, 5),
+ GMUX(0x1fc, V, 0, lcd_bl_pwm_pv0, displaya, pwm0, sor0, rsvd3, 0xa34, 12, 5, 20, 5),
+ GMUX(0x200, V, 1, lcd_bl_en_pv1, rsvd0, rsvd1, rsvd2, rsvd3, 0xa30, 12, 5, 20, 5),
+ GMUX(0x204, V, 2, lcd_rst_pv2, rsvd0, rsvd1, rsvd2, rsvd3, 0xa40, 12, 5, 20, 5),
+ GMUX(0x208, V, 3, lcd_gpio1_pv3, displayb, rsvd1, rsvd2, rsvd3, 0xa38, 12, 5, 20, 5),
+ GMUX(0x20c, V, 4, lcd_gpio2_pv4, displayb, pwm1, rsvd2, sor1, 0xa3c, 12, 5, 20, 5),
+ GMUX(0x210, V, 5, ap_ready_pv5, rsvd0, rsvd1, rsvd2, rsvd3, 0x8e8, 12, 5, 20, 5),
+ GMUX(0x214, V, 6, touch_rst_pv6, rsvd0, rsvd1, rsvd2, rsvd3, 0xb18, 12, 5, 20, 5),
+ GMUX(0x218, V, 7, touch_clk_pv7, touch, rsvd1, rsvd2, rsvd3, 0xb10, 12, 5, 20, 5),
+ GMUX(0x21c, X, 0, modem_wake_ap_px0, rsvd0, rsvd1, rsvd2, rsvd3, 0xa48, 12, 5, 20, 5),
+ GMUX(0x220, X, 1, touch_int_px1, rsvd0, rsvd1, rsvd2, rsvd3, 0xb14, 12, 5, 20, 5),
+ GMUX(0x224, X, 2, motion_int_px2, rsvd0, rsvd1, rsvd2, rsvd3, 0xa4c, 12, 5, 20, 5),
+ GMUX(0x228, X, 3, als_prox_int_px3, rsvd0, rsvd1, rsvd2, rsvd3, 0x8e4, 12, 5, 20, 5),
+ GMUX(0x22c, X, 4, temp_alert_px4, rsvd0, rsvd1, rsvd2, rsvd3, 0xb0c, 12, 5, 20, 5),
+ GMUX(0x230, X, 5, button_power_on_px5, rsvd0, rsvd1, rsvd2, rsvd3, 0x908, 12, 5, 20, 5),
+ GMUX(0x234, X, 6, button_vol_up_px6, rsvd0, rsvd1, rsvd2, rsvd3, 0x914, 12, 5, 20, 5),
+ GMUX(0x238, X, 7, button_vol_down_px7, rsvd0, rsvd1, rsvd2, rsvd3, 0x910, 12, 5, 20, 5),
+ GMUX(0x23c, Y, 0, button_slide_sw_py0, rsvd0, rsvd1, rsvd2, rsvd3, 0x90c, 12, 5, 20, 5),
+ GMUX(0x240, Y, 1, button_home_py1, rsvd0, rsvd1, rsvd2, rsvd3, 0x904, 12, 5, 20, 5),
+ GMUX(0x244, A, 6, pa6, sata, rsvd1, rsvd2, rsvd3, -1, 0, 0, 0, 0),
+ GMUX(0x248, E, 6, pe6, rsvd0, i2s5a, pwm2, rsvd3, -1, 0, 0, 0, 0),
+ GMUX(0x24c, E, 7, pe7, rsvd0, i2s5a, pwm3, rsvd3, -1, 0, 0, 0, 0),
+ GMUX(0x250, H, 6, ph6, rsvd0, rsvd1, rsvd2, rsvd3, -1, 0, 0, 0, 0),
+ GMUX(0x254, K, 0, pk0, iqc0, i2s5b, rsvd2, rsvd3, -1, 0, 0, 0, 0),
+ GMUX(0x258, K, 1, pk1, iqc0, i2s5b, rsvd2, rsvd3, -1, 0, 0, 0, 0),
+ GMUX(0x25c, K, 2, pk2, iqc0, i2s5b, rsvd2, rsvd3, -1, 0, 0, 0, 0),
+ GMUX(0x260, K, 3, pk3, iqc0, i2s5b, rsvd2, rsvd3, -1, 0, 0, 0, 0),
+ GMUX(0x264, K, 4, pk4, iqc1, rsvd1, rsvd2, rsvd3, -1, 0, 0, 0, 0),
+ GMUX(0x268, K, 5, pk5, iqc1, rsvd1, rsvd2, rsvd3, -1, 0, 0, 0, 0),
+ GMUX(0x26c, K, 6, pk6, iqc1, rsvd1, rsvd2, rsvd3, -1, 0, 0, 0, 0),
+ GMUX(0x270, K, 7, pk7, iqc1, rsvd1, rsvd2, rsvd3, -1, 0, 0, 0, 0),
+ GMUX(0x274, L, 0, pl0, rsvd0, rsvd1, rsvd2, rsvd3, -1, 0, 0, 0, 0),
+ GMUX(0x278, L, 1, pl1, soc, rsvd1, rsvd2, rsvd3, -1, 0, 0, 0, 0),
+ GMUX(0x27c, Z, 0, pz0, vimclk2, rsvd1, rsvd2, rsvd3, -1, 0, 0, 0, 0),
+ GMUX(0x280, Z, 1, pz1, vimclk2, sdmmc1, rsvd2, rsvd3, -1, 0, 0, 0, 0),
+ GMUX(0x284, Z, 2, pz2, sdmmc3, ccla, rsvd2, rsvd3, -1, 0, 0, 0, 0),
+ GMUX(0x288, Z, 3, pz3, sdmmc3, rsvd1, rsvd2, rsvd3, -1, 0, 0, 0, 0),
+ GMUX(0x28c, Z, 4, pz4, sdmmc1, rsvd1, rsvd2, rsvd3, -1, 0, 0, 0, 0),
+ GMUX(0x290, Z, 5, pz5, soc, rsvd1, rsvd2, rsvd3, -1, 0, 0, 0, 0),
+};
+
+
+static const struct tegra_grp *
+pinmux_search_grp(char *grp_name)
+{
+ int i;
+
+ for (i = 0; i < nitems(pin_grp_tbl); i++) {
+ if (strcmp(grp_name, pin_grp_tbl[i].name) == 0)
+ return (&pin_grp_tbl[i]);
+ }
+ return (NULL);
+}
+
+static const struct tegra_mux *
+pinmux_search_mux(char *pin_name)
+{
+ int i;
+
+ for (i = 0; i < nitems(pin_mux_tbl); i++) {
+ if (strcmp(pin_name, pin_mux_tbl[i].name) == 0)
+ return (&pin_mux_tbl[i]);
+ }
+ return (NULL);
+}
+
+static int
+pinmux_mux_function(const struct tegra_mux *mux, char *fnc_name)
+{
+ int i;
+
+ for (i = 0; i < 4; i++) {
+ if (strcmp(fnc_name, mux->functions[i]) == 0)
+ return (i);
+ }
+ return (-1);
+}
+
+static int
+pinmux_config_mux(struct pinmux_softc *sc, char *pin_name,
+ const struct tegra_mux *mux, struct pincfg *cfg)
+{
+ int tmp;
+ uint32_t reg;
+
+ reg = bus_read_4(sc->mux_mem_res, mux->reg);
+
+ if (cfg->function != NULL) {
+ tmp = pinmux_mux_function(mux, cfg->function);
+ if (tmp == -1) {
+ device_printf(sc->dev,
+ "Unknown function %s for pin %s\n", cfg->function,
+ pin_name);
+ return (ENXIO);
+ }
+ reg &= ~(TEGRA_MUX_FUNCTION_MASK << TEGRA_MUX_FUNCTION_SHIFT);
+ reg |= (tmp & TEGRA_MUX_FUNCTION_MASK) <<
+ TEGRA_MUX_FUNCTION_SHIFT;
+ }
+ if (cfg->params[PROP_ID_PULL] != -1) {
+ reg &= ~(TEGRA_MUX_PUPD_MASK << TEGRA_MUX_PUPD_SHIFT);
+ reg |= (cfg->params[PROP_ID_PULL] & TEGRA_MUX_PUPD_MASK) <<
+ TEGRA_MUX_PUPD_SHIFT;
+ }
+ if (cfg->params[PROP_ID_TRISTATE] != -1) {
+ reg &= ~(1 << TEGRA_MUX_TRISTATE_SHIFT);
+ reg |= (cfg->params[PROP_ID_TRISTATE] & 1) <<
+ TEGRA_MUX_TRISTATE_SHIFT;
+ }
+ if (cfg->params[TEGRA_MUX_ENABLE_INPUT_SHIFT] != -1) {
+ reg &= ~(1 << TEGRA_MUX_ENABLE_INPUT_SHIFT);
+ reg |= (cfg->params[TEGRA_MUX_ENABLE_INPUT_SHIFT] & 1) <<
+ TEGRA_MUX_ENABLE_INPUT_SHIFT;
+ }
+ if (cfg->params[PROP_ID_ENABLE_INPUT] != -1) {
+ reg &= ~(1 << TEGRA_MUX_ENABLE_INPUT_SHIFT);
+ reg |= (cfg->params[PROP_ID_ENABLE_INPUT] & 1) <<
+ TEGRA_MUX_ENABLE_INPUT_SHIFT;
+ }
+ if (cfg->params[PROP_ID_ENABLE_INPUT] != -1) {
+ reg &= ~(1 << TEGRA_MUX_ENABLE_INPUT_SHIFT);
+ reg |= (cfg->params[PROP_ID_OPEN_DRAIN] & 1) <<
+ TEGRA_MUX_ENABLE_INPUT_SHIFT;
+ }
+ if (cfg->params[PROP_ID_LOCK] != -1) {
+ reg &= ~(1 << TEGRA_MUX_LOCK_SHIFT);
+ reg |= (cfg->params[PROP_ID_LOCK] & 1) <<
+ TEGRA_MUX_LOCK_SHIFT;
+ }
+ if (cfg->params[PROP_ID_IORESET] != -1) {
+ reg &= ~(1 << TEGRA_MUX_IORESET_SHIFT);
+ reg |= (cfg->params[PROP_ID_IORESET] & 1) <<
+ TEGRA_MUX_IORESET_SHIFT;
+ }
+ if (cfg->params[PROP_ID_RCV_SEL] != -1) {
+ reg &= ~(1 << TEGRA_MUX_RCV_SEL_SHIFT);
+ reg |= (cfg->params[PROP_ID_RCV_SEL] & 1) <<
+ TEGRA_MUX_RCV_SEL_SHIFT;
+ }
+ bus_write_4(sc->mux_mem_res, mux->reg, reg);
+ return (0);
+}
+
+static int
+pinmux_config_grp(struct pinmux_softc *sc, char *grp_name,
+ const struct tegra_grp *grp, struct pincfg *cfg)
+{
+ uint32_t reg;
+
+ reg = bus_read_4(sc->pad_mem_res, grp->reg);
+
+ if (cfg->params[PROP_ID_HIGH_SPEED_MODE] != -1) {
+ reg &= ~(1 << TEGRA_GRP_HSM_SHIFT);
+ reg |= (cfg->params[PROP_ID_HIGH_SPEED_MODE] & 1) <<
+ TEGRA_GRP_HSM_SHIFT;
+ }
+ if (cfg->params[PROP_ID_SCHMITT] != -1) {
+ reg &= ~(1 << TEGRA_GRP_SCHMT_SHIFT);
+ reg |= (cfg->params[PROP_ID_SCHMITT] & 1) <<
+ TEGRA_GRP_SCHMT_SHIFT;
+ }
+ if (cfg->params[PROP_ID_DRIVE_TYPE] != -1) {
+ reg &= ~(TEGRA_GRP_DRV_TYPE_MASK << TEGRA_GRP_DRV_TYPE_SHIFT);
+ reg |= (cfg->params[PROP_ID_DRIVE_TYPE] &
+ TEGRA_GRP_DRV_TYPE_MASK) << TEGRA_GRP_DRV_TYPE_SHIFT;
+ }
+ if (cfg->params[PROP_ID_SLEW_RATE_RISING] != -1) {
+ reg &= ~(TEGRA_GRP_DRV_DRVDN_SLWR_MASK <<
+ TEGRA_GRP_DRV_DRVDN_SLWR_SHIFT);
+ reg |= (cfg->params[PROP_ID_SLEW_RATE_RISING] &
+ TEGRA_GRP_DRV_DRVDN_SLWR_MASK) <<
+ TEGRA_GRP_DRV_DRVDN_SLWR_SHIFT;
+ }
+ if (cfg->params[PROP_ID_SLEW_RATE_FALLING] != -1) {
+ reg &= ~(TEGRA_GRP_DRV_DRVUP_SLWF_MASK <<
+ TEGRA_GRP_DRV_DRVUP_SLWF_SHIFT);
+ reg |= (cfg->params[PROP_ID_SLEW_RATE_FALLING] &
+ TEGRA_GRP_DRV_DRVUP_SLWF_MASK) <<
+ TEGRA_GRP_DRV_DRVUP_SLWF_SHIFT;
+ }
+ if ((cfg->params[PROP_ID_DRIVE_DOWN_STRENGTH] != -1) &&
+ (grp->drvdn_mask != 0)) {
+ reg &= ~(grp->drvdn_shift << grp->drvdn_mask);
+ reg |= (cfg->params[PROP_ID_DRIVE_DOWN_STRENGTH] &
+ grp->drvdn_mask) << grp->drvdn_shift;
+ }
+ if ((cfg->params[PROP_ID_DRIVE_UP_STRENGTH] != -1) &&
+ (grp->drvup_mask != 0)) {
+ reg &= ~(grp->drvup_shift << grp->drvup_mask);
+ reg |= (cfg->params[PROP_ID_DRIVE_UP_STRENGTH] &
+ grp->drvup_mask) << grp->drvup_shift;
+ }
+ bus_write_4(sc->pad_mem_res, grp->reg, reg);
+ return (0);
+}
+
+static int
+pinmux_config_node(struct pinmux_softc *sc, char *pin_name, struct pincfg *cfg)
+{
+ const struct tegra_mux *mux;
+ const struct tegra_grp *grp;
+ bool handled;
+ int rv;
+
+ /* Handle pin muxes */
+ mux = pinmux_search_mux(pin_name);
+ handled = false;
+ if (mux != NULL) {
+ if (mux->gpio_num != -1) {
+ /* XXXX TODO: Reserve gpio here */
+ }
+ rv = pinmux_config_mux(sc, pin_name, mux, cfg);
+ if (rv != 0)
+ return (rv);
+ if (mux->grp.reg <= 0) {
+ rv = pinmux_config_grp(sc, pin_name, &mux->grp, cfg);
+ return (rv);
+ }
+ handled = true;
+ }
+
+ /* And/or handle pin groups */
+ grp = pinmux_search_grp(pin_name);
+ if (grp != NULL) {
+ rv = pinmux_config_grp(sc, pin_name, grp, cfg);
+ if (rv != 0)
+ return (rv);
+ handled = true;
+ }
+
+ if (!handled) {
+ device_printf(sc->dev, "Unknown pin: %s\n", pin_name);
+ return (ENXIO);
+ }
+ return (0);
+}
+
+static int
+pinmux_read_node(struct pinmux_softc *sc, phandle_t node, struct pincfg *cfg,
+ char **pins, int *lpins)
+{
+ int rv, i;
+
+ *lpins = OF_getprop_alloc(node, "nvidia,pins", (void **)pins);
+ if (*lpins <= 0)
+ return (ENOENT);
+
+ /* Read function (mux) settings. */
+ rv = OF_getprop_alloc(node, "nvidia,function", (void **)&cfg->function);
+ if (rv <= 0)
+ cfg->function = NULL;
+
+ /* Read numeric properties. */
+ for (i = 0; i < PROP_ID_MAX_ID; i++) {
+ rv = OF_getencprop(node, prop_names[i].name, &cfg->params[i],
+ sizeof(cfg->params[i]));
+ if (rv <= 0)
+ cfg->params[i] = -1;
+ }
+ return (0);
+}
+
+static int
+pinmux_process_node(struct pinmux_softc *sc, phandle_t node)
+{
+ struct pincfg cfg;
+ char *pins, *pname;
+ int i, len, lpins, rv;
+
+ rv = pinmux_read_node(sc, node, &cfg, &pins, &lpins);
+ if (rv != 0)
+ return (rv);
+
+ len = 0;
+ pname = pins;
+ do {
+ i = strlen(pname) + 1;
+ rv = pinmux_config_node(sc, pname, &cfg);
+ if (rv != 0)
+ device_printf(sc->dev, "Cannot configure pin: %s: %d\n",
+ pname, rv);
+ len += i;
+ pname += i;
+ } while (len < lpins);
+
+ if (pins != NULL)
+ OF_prop_free(pins);
+ if (cfg.function != NULL)
+ OF_prop_free(cfg.function);
+ return (rv);
+}
+
+static int pinmux_configure(device_t dev, phandle_t cfgxref)
+{
+ struct pinmux_softc *sc;
+ phandle_t node, cfgnode;
+ int rv;
+
+ sc = device_get_softc(dev);
+ cfgnode = OF_node_from_xref(cfgxref);
+
+
+ for (node = OF_child(cfgnode); node != 0; node = OF_peer(node)) {
+ if (!ofw_bus_node_status_okay(node))
+ continue;
+ rv = pinmux_process_node(sc, node);
+ }
+ return (0);
+}
+
+static int
+pinmux_probe(device_t dev)
+{
+
+ if (!ofw_bus_status_okay(dev))
+ return (ENXIO);
+
+ if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
+ return (ENXIO);
+
+ device_set_desc(dev, "Tegra pin configuration");
+ return (BUS_PROBE_DEFAULT);
+}
+
+static int
+pinmux_detach(device_t dev)
+{
+
+ /* This device is always present. */
+ return (EBUSY);
+}
+
+static int
+pinmux_attach(device_t dev)
+{
+ struct pinmux_softc * sc;
+ int rid;
+
+ sc = device_get_softc(dev);
+ sc->dev = dev;
+
+ rid = 0;
+ sc->pad_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
+ RF_ACTIVE);
+ if (sc->pad_mem_res == NULL) {
+ device_printf(dev, "Cannot allocate memory resources\n");
+ return (ENXIO);
+ }
+
+ rid = 1;
+ sc->mux_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
+ RF_ACTIVE);
+ if (sc->mux_mem_res == NULL) {
+ device_printf(dev, "Cannot allocate memory resources\n");
+ return (ENXIO);
+ }
+
+
+ /* Register as a pinctrl device and process default configuration */
+ fdt_pinctrl_register(dev, NULL);
+ fdt_pinctrl_configure_by_name(dev, "boot");
+
+ return (0);
+}
+
+
+static device_method_t tegra210_pinmux_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, pinmux_probe),
+ DEVMETHOD(device_attach, pinmux_attach),
+ DEVMETHOD(device_detach, pinmux_detach),
+
+ /* fdt_pinctrl interface */
+ DEVMETHOD(fdt_pinctrl_configure,pinmux_configure),
+
+ DEVMETHOD_END
+};
+
+static devclass_t tegra210_pinmux_devclass;
+static DEFINE_CLASS_0(pinmux, tegra210_pinmux_driver, tegra210_pinmux_methods,
+ sizeof(struct pinmux_softc));
+EARLY_DRIVER_MODULE(tegra210_pinmux, simplebus, tegra210_pinmux_driver,
+ tegra210_pinmux_devclass, NULL, NULL, 71);
diff --git a/sys/arm64/nvidia/tegra210/tegra210_pmc.c b/sys/arm64/nvidia/tegra210/tegra210_pmc.c
new file mode 100644
index 000000000000..5ffa8cb97512
--- /dev/null
+++ b/sys/arm64/nvidia/tegra210/tegra210_pmc.c
@@ -0,0 +1,628 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
+ *
+ * Copyright 2020 Michal Meloun <mmel@FreeBSD.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/malloc.h>
+#include <sys/mutex.h>
+#include <sys/rman.h>
+
+#include <machine/bus.h>
+
+#include <dev/extres/clk/clk.h>
+#include <dev/extres/hwreset/hwreset.h>
+#include <dev/ofw/ofw_bus.h>
+#include <dev/ofw/ofw_bus_subr.h>
+#include <dev/psci/smccc.h>
+
+#include <arm/nvidia/tegra_pmc.h>
+
+#define PMC_CNTRL 0x000
+#define PMC_CNTRL_SHUTDOWN_OE (1 << 22)
+#define PMC_CNTRL_CPUPWRGOOD_SEL_MASK (0x3 << 20)
+#define PMC_CNTRL_CPUPWRGOOD_SEL_SHIFT 20
+#define PMC_CNTRL_CPUPWRGOOD_EN (1 << 19)
+#define PMC_CNTRL_FUSE_OVERRIDE (1 << 18)
+#define PMC_CNTRL_INTR_POLARITY (1 << 17)
+#define PMC_CNTRL_CPU_PWRREQ_OE (1 << 16)
+#define PMC_CNTRL_CPU_PWRREQ_POLARITY (1 << 15)
+#define PMC_CNTRL_SIDE_EFFECT_LP0 (1 << 14)
+#define PMC_CNTRL_AOINIT (1 << 13)
+#define PMC_CNTRL_PWRGATE_DIS (1 << 12)
+#define PMC_CNTRL_SYSCLK_OE (1 << 11)
+#define PMC_CNTRL_SYSCLK_POLARITY (1 << 10)
+#define PMC_CNTRL_PWRREQ_OE (1 << 9)
+#define PMC_CNTRL_PWRREQ_POLARITY (1 << 8)
+#define PMC_CNTRL_BLINK_EN (1 << 7)
+#define PMC_CNTRL_GLITCHDET_DIS (1 << 6)
+#define PMC_CNTRL_LATCHWAKE_EN (1 << 5)
+#define PMC_CNTRL_MAIN_RST (1 << 4)
+#define PMC_CNTRL_KBC_RST (1 << 3)
+#define PMC_CNTRL_RTC_RST (1 << 2)
+#define PMC_CNTRL_RTC_CLK_DIS (1 << 1)
+#define PMC_CNTRL_KBC_CLK_DIS (1 << 0)
+
+#define PMC_DPD_SAMPLE 0x020
+
+#define PMC_CLAMP_STATUS 0x02C
+#define PMC_CLAMP_STATUS_PARTID(x) (1 << ((x) & 0x1F))
+
+#define PMC_PWRGATE_TOGGLE 0x030
+#define PMC_PWRGATE_TOGGLE_START (1 << 8)
+#define PMC_PWRGATE_TOGGLE_PARTID(x) (((x) & 0x1F) << 0)
+
+#define PMC_REMOVE_CLAMPING_CMD 0x034
+#define PMC_REMOVE_CLAMPING_CMD_PARTID(x) (1 << ((x) & 0x1F))
+
+#define PMC_PWRGATE_STATUS 0x038
+#define PMC_PWRGATE_STATUS_PARTID(x) (1 << ((x) & 0x1F))
+
+#define PMC_SCRATCH0 0x050
+#define PMC_SCRATCH0_MODE_RECOVERY (1 << 31)
+#define PMC_SCRATCH0_MODE_BOOTLOADER (1 << 30)
+#define PMC_SCRATCH0_MODE_RCM (1 << 1)
+#define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \
+ PMC_SCRATCH0_MODE_BOOTLOADER | \
+ PMC_SCRATCH0_MODE_RCM)
+
+#define PMC_CPUPWRGOOD_TIMER 0x0c8
+#define PMC_CPUPWROFF_TIMER 0x0cc
+
+#define PMC_SCRATCH41 0x140
+
+#define PMC_SENSOR_CTRL 0x1b0
+#define PMC_SENSOR_CTRL_BLOCK_SCRATCH_WRITE (1 << 2)
+#define PMC_SENSOR_CTRL_ENABLE_RST (1 << 1)
+#define PMC_SENSOR_CTRL_ENABLE_PG (1 << 0)
+
+#define PMC_IO_DPD_REQ 0x1b8
+#define PMC_IO_DPD_REQ_CODE_IDLE (0 << 30)
+#define PMC_IO_DPD_REQ_CODE_OFF (1 << 30)
+#define PMC_IO_DPD_REQ_CODE_ON (2 << 30)
+#define PMC_IO_DPD_REQ_CODE_MASK (3 << 30)
+
+#define PMC_IO_DPD_STATUS 0x1bc
+#define PMC_IO_DPD_STATUS_HDMI (1 << 28)
+#define PMC_IO_DPD2_REQ 0x1c0
+#define PMC_IO_DPD2_STATUS 0x1c4
+#define PMC_IO_DPD2_STATUS_HV (1 << 6)
+#define PMC_SEL_DPD_TIM 0x1c8
+
+#define PMC_SCRATCH54 0x258
+#define PMC_SCRATCH54_DATA_SHIFT 8
+#define PMC_SCRATCH54_ADDR_SHIFT 0
+
+#define PMC_SCRATCH55 0x25c
+#define PMC_SCRATCH55_RST_ENABLE (1 << 31)
+#define PMC_SCRATCH55_CNTRL_TYPE (1 << 30)
+#define PMC_SCRATCH55_CNTRL_ID_SHIFT 27
+#define PMC_SCRATCH55_CNTRL_ID_MASK 0x07
+#define PMC_SCRATCH55_PINMUX_SHIFT 24
+#define PMC_SCRATCH55_PINMUX_MASK 0x07
+#define PMC_SCRATCH55_CHECKSUM_SHIFT 16
+#define PMC_SCRATCH55_CHECKSUM_MASK 0xFF
+#define PMC_SCRATCH55_16BITOP (1 << 15)
+#define PMC_SCRATCH55_I2CSLV1_SHIFT 0
+#define PMC_SCRATCH55_I2CSLV1_MASK 0x7F
+
+#define PMC_GPU_RG_CNTRL 0x2d4
+
+/* Secure access */
+#define PMC_SMC 0xc2fffe00
+#define PMC_SMC_READ 0xaa
+#define PMC_SMC_WRITE 0xbb
+
+#define PMC_LOCK(_sc) mtx_lock(&(_sc)->mtx)
+#define PMC_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx)
+#define PMC_LOCK_INIT(_sc) mtx_init(&(_sc)->mtx, \
+ device_get_nameunit(_sc->dev), "tegra210_pmc", MTX_DEF)
+#define PMC_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx);
+#define PMC_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED);
+#define PMC_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->mtx, MA_NOTOWNED);
+
+struct tegra210_pmc_softc {
+ device_t dev;
+ struct resource *mem_res;
+ clk_t clk;
+ struct mtx mtx;
+ bool secure_access;
+
+ uint32_t rate;
+ enum tegra_suspend_mode suspend_mode;
+ uint32_t cpu_good_time;
+ uint32_t cpu_off_time;
+ uint32_t core_osc_time;
+ uint32_t core_pmu_time;
+ uint32_t core_off_time;
+ int corereq_high;
+ int sysclkreq_high;
+ int combined_req;
+ int cpu_pwr_good_en;
+ uint32_t lp0_vec_phys;
+ uint32_t lp0_vec_size;
+};
+
+static struct ofw_compat_data compat_data[] = {
+ {"nvidia,tegra210-pmc", 1},
+ {NULL, 0},
+};
+
+static struct tegra210_pmc_softc *pmc_sc;
+
+static inline struct tegra210_pmc_softc *
+tegra210_pmc_get_sc(void)
+{
+ if (pmc_sc == NULL)
+ panic("To early call to Tegra PMC driver.\n");
+ return (pmc_sc);
+}
+
+static void
+WR4(struct tegra210_pmc_softc *sc, bus_size_t r, uint32_t v)
+{
+ struct arm_smccc_res res;
+
+ if (sc->secure_access) {
+ arm_smccc_smc(PMC_SMC, PMC_SMC_WRITE, r, v, 0, 0, 0, 0, &res);
+ if (res.a0 != 0)
+ device_printf(sc->dev," PMC SMC write failed: %lu\n",
+ res.a0);
+ }
+
+ bus_write_4(sc->mem_res, r, v);
+}
+
+static uint32_t
+RD4(struct tegra210_pmc_softc *sc, bus_size_t r)
+{
+ struct arm_smccc_res res;
+
+ if (sc->secure_access) {
+ arm_smccc_smc(PMC_SMC, PMC_SMC_READ, r, 0, 0, 0, 0, 0, &res);
+ if (res.a0 != 0)
+ device_printf(sc->dev," PMC SMC write failed: %lu\n",
+ res.a0);
+ return((uint32_t)res.a1);
+ }
+
+ return(bus_read_4(sc->mem_res, r));
+}
+
+static int
+tegra210_pmc_set_powergate(struct tegra210_pmc_softc *sc,
+ enum tegra_powergate_id id, int ena)
+{
+ uint32_t reg;
+ int i;
+
+ PMC_LOCK(sc);
+
+ reg = RD4(sc, PMC_PWRGATE_STATUS) & PMC_PWRGATE_STATUS_PARTID(id);
+ if (((reg != 0) && ena) || ((reg == 0) && !ena)) {
+ PMC_UNLOCK(sc);
+ return (0);
+ }
+
+ for (i = 100; i > 0; i--) {
+ reg = RD4(sc, PMC_PWRGATE_TOGGLE);
+ if ((reg & PMC_PWRGATE_TOGGLE_START) == 0)
+ break;
+ DELAY(1);
+ }
+ if (i <= 0)
+ device_printf(sc->dev,
+ "Timeout when waiting for TOGGLE_START\n");
+
+ WR4(sc, PMC_PWRGATE_TOGGLE,
+ PMC_PWRGATE_TOGGLE_START | PMC_PWRGATE_TOGGLE_PARTID(id));
+
+ for (i = 100; i > 0; i--) {
+ reg = RD4(sc, PMC_PWRGATE_TOGGLE);
+ if ((reg & PMC_PWRGATE_TOGGLE_START) == 0)
+ break;
+ DELAY(1);
+ }
+ if (i <= 0)
+ device_printf(sc->dev,
+ "Timeout when waiting for TOGGLE_START\n");
+ PMC_UNLOCK(sc);
+ return (0);
+}
+
+int
+tegra_powergate_remove_clamping(enum tegra_powergate_id id)
+{
+ struct tegra210_pmc_softc *sc;
+ uint32_t reg;
+ enum tegra_powergate_id swid;
+ int i;
+
+ sc = tegra210_pmc_get_sc();
+
+ if (id == TEGRA_POWERGATE_3D) {
+ WR4(sc, PMC_GPU_RG_CNTRL, 0);
+ return (0);
+ }
+
+ reg = RD4(sc, PMC_PWRGATE_STATUS);
+ if ((reg & PMC_PWRGATE_STATUS_PARTID(id)) == 0)
+ panic("Attempt to remove clamping for unpowered partition.\n");
+
+ if (id == TEGRA_POWERGATE_PCX)
+ swid = TEGRA_POWERGATE_VDE;
+ else if (id == TEGRA_POWERGATE_VDE)
+ swid = TEGRA_POWERGATE_PCX;
+ else
+ swid = id;
+ WR4(sc, PMC_REMOVE_CLAMPING_CMD, PMC_REMOVE_CLAMPING_CMD_PARTID(swid));
+
+ for (i = 100; i > 0; i--) {
+ reg = RD4(sc, PMC_REMOVE_CLAMPING_CMD);
+ if ((reg & PMC_REMOVE_CLAMPING_CMD_PARTID(swid)) == 0)
+ break;
+ DELAY(1);
+ }
+ if (i <= 0)
+ device_printf(sc->dev, "Timeout when remove clamping\n");
+
+ reg = RD4(sc, PMC_CLAMP_STATUS);
+ if ((reg & PMC_CLAMP_STATUS_PARTID(id)) != 0)
+ panic("Cannot remove clamping\n");
+
+ return (0);
+}
+
+int
+tegra_powergate_is_powered(enum tegra_powergate_id id)
+{
+ struct tegra210_pmc_softc *sc;
+ uint32_t reg;
+
+ sc = tegra210_pmc_get_sc();
+
+ reg = RD4(sc, PMC_PWRGATE_STATUS);
+ return ((reg & PMC_PWRGATE_STATUS_PARTID(id)) ? 1 : 0);
+}
+
+int
+tegra_powergate_power_on(enum tegra_powergate_id id)
+{
+ struct tegra210_pmc_softc *sc;
+ int rv, i;
+
+ sc = tegra210_pmc_get_sc();
+
+ rv = tegra210_pmc_set_powergate(sc, id, 1);
+ if (rv != 0) {
+ device_printf(sc->dev, "Cannot set powergate: %d\n", id);
+ return (rv);
+ }
+
+ for (i = 100; i > 0; i--) {
+ if (tegra_powergate_is_powered(id))
+ break;
+ DELAY(1);
+ }
+ if (i <= 0) {
+ device_printf(sc->dev, "Timeout when waiting on power up\n");
+ return(ETIMEDOUT);
+ }
+
+ return (rv);
+}
+
+int
+tegra_powergate_power_off(enum tegra_powergate_id id)
+{
+ struct tegra210_pmc_softc *sc;
+ int rv, i;
+
+ sc = tegra210_pmc_get_sc();
+
+ rv = tegra210_pmc_set_powergate(sc, id, 0);
+ if (rv != 0) {
+ device_printf(sc->dev, "Cannot set powergate: %d\n", id);
+ return (rv);
+ }
+ for (i = 100; i > 0; i--) {
+ if (!tegra_powergate_is_powered(id))
+ break;
+ DELAY(1);
+ }
+ if (i <= 0)
+ device_printf(sc->dev, "Timeout when waiting on power off\n");
+
+ return (rv);
+}
+
+int
+tegra_powergate_sequence_power_up(enum tegra_powergate_id id, clk_t clk,
+ hwreset_t rst)
+{
+ struct tegra210_pmc_softc *sc;
+ int rv;
+
+ sc = tegra210_pmc_get_sc();
+
+ rv = hwreset_assert(rst);
+ if (rv != 0) {
+ device_printf(sc->dev, "Cannot assert reset\n");
+ return (rv);
+ }
+
+ rv = clk_stop(clk);
+ if (rv != 0) {
+ device_printf(sc->dev, "Cannot stop clock\n");
+ goto clk_fail;
+ }
+
+ rv = tegra_powergate_power_on(id);
+ if (rv != 0) {
+ device_printf(sc->dev, "Cannot power on powergate\n");
+ goto clk_fail;
+ }
+
+ rv = clk_enable(clk);
+ if (rv != 0) {
+ device_printf(sc->dev, "Cannot enable clock\n");
+ goto clk_fail;
+ }
+ DELAY(20);
+
+ rv = tegra_powergate_remove_clamping(id);
+ if (rv != 0) {
+ device_printf(sc->dev, "Cannot remove clamping\n");
+ goto fail;
+ }
+ rv = hwreset_deassert(rst);
+ if (rv != 0) {
+ device_printf(sc->dev, "Cannot unreset reset\n");
+ goto fail;
+ }
+ return 0;
+
+fail:
+ clk_disable(clk);
+clk_fail:
+ hwreset_assert(rst);
+ tegra_powergate_power_off(id);
+ return (rv);
+}
+
+static int
+tegra210_pmc_parse_fdt(struct tegra210_pmc_softc *sc, phandle_t node)
+{
+ int rv;
+ uint32_t tmp;
+ uint32_t tmparr[2];
+
+ rv = OF_getencprop(node, "nvidia,suspend-mode", &tmp, sizeof(tmp));
+ if (rv > 0) {
+ switch (tmp) {
+ case 0:
+ sc->suspend_mode = TEGRA_SUSPEND_LP0;
+ break;
+
+ case 1:
+ sc->suspend_mode = TEGRA_SUSPEND_LP1;
+ break;
+
+ case 2:
+ sc->suspend_mode = TEGRA_SUSPEND_LP2;
+ break;
+
+ default:
+ sc->suspend_mode = TEGRA_SUSPEND_NONE;
+ break;
+ }
+ }
+
+ rv = OF_getencprop(node, "nvidia,cpu-pwr-good-time", &tmp, sizeof(tmp));
+ if (rv > 0) {
+ sc->cpu_good_time = tmp;
+ sc->suspend_mode = TEGRA_SUSPEND_NONE;
+ }
+
+ rv = OF_getencprop(node, "nvidia,cpu-pwr-off-time", &tmp, sizeof(tmp));
+ if (rv > 0) {
+ sc->cpu_off_time = tmp;
+ sc->suspend_mode = TEGRA_SUSPEND_NONE;
+ }
+
+ rv = OF_getencprop(node, "nvidia,core-pwr-good-time", tmparr,
+ sizeof(tmparr));
+ if (rv == sizeof(tmparr)) {
+ sc->core_osc_time = tmparr[0];
+ sc->core_pmu_time = tmparr[1];
+ sc->suspend_mode = TEGRA_SUSPEND_NONE;
+ }
+
+ rv = OF_getencprop(node, "nvidia,core-pwr-off-time", &tmp, sizeof(tmp));
+ if (rv > 0) {
+ sc->core_off_time = tmp;
+ sc->suspend_mode = TEGRA_SUSPEND_NONE;
+ }
+
+ sc->corereq_high =
+ OF_hasprop(node, "nvidia,core-power-req-active-high");
+ sc->sysclkreq_high =
+ OF_hasprop(node, "nvidia,sys-clock-req-active-high");
+ sc->combined_req =
+ OF_hasprop(node, "nvidia,combined-power-req");
+ sc->cpu_pwr_good_en =
+ OF_hasprop(node, "nvidia,cpu-pwr-good-en");
+
+ rv = OF_getencprop(node, "nvidia,lp0-vec", tmparr, sizeof(tmparr));
+ if (rv == sizeof(tmparr)) {
+
+ sc->lp0_vec_phys = tmparr[0];
+ sc->core_pmu_time = tmparr[1];
+ sc->lp0_vec_size = TEGRA_SUSPEND_NONE;
+ if (sc->suspend_mode == TEGRA_SUSPEND_LP0)
+ sc->suspend_mode = TEGRA_SUSPEND_LP1;
+ }
+ return 0;
+}
+
+static void
+tegra210_pmc_check_secure(struct tegra210_pmc_softc *sc)
+{
+ uint32_t orig;
+
+ sc->secure_access = false;
+
+ /*
+ * If PMC is coverd by secure trust zone, all reads returns 0,
+ * Use scratch0 register acvcess test
+ */
+ orig = RD4(sc, PMC_SCRATCH0);
+ WR4(sc, PMC_SCRATCH0, 0xDEADBEEF);
+ if (RD4(sc, PMC_SCRATCH0) == 0) {
+ sc->secure_access = true;
+ return;
+ }
+ WR4(sc, PMC_SCRATCH0, 0xBADC0DE);
+ if (RD4(sc, PMC_SCRATCH0) == 0) {
+ sc->secure_access = true;
+ return;
+ }
+ WR4(sc, PMC_SCRATCH0, orig);
+}
+
+static int
+tegra210_pmc_probe(device_t dev)
+{
+
+ if (!ofw_bus_status_okay(dev))
+ return (ENXIO);
+
+ if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
+ return (ENXIO);
+
+ device_set_desc(dev, "Tegra PMC");
+ return (BUS_PROBE_DEFAULT);
+}
+
+static int
+tegra210_pmc_detach(device_t dev)
+{
+
+ /* This device is always present. */
+ return (EBUSY);
+}
+
+static int
+tegra210_pmc_attach(device_t dev)
+{
+ struct tegra210_pmc_softc *sc;
+ int rid, rv;
+ uint32_t reg;
+ phandle_t node;
+
+ sc = device_get_softc(dev);
+ sc->dev = dev;
+ node = ofw_bus_get_node(dev);
+ PMC_LOCK_INIT(sc);
+
+ rv = tegra210_pmc_parse_fdt(sc, node);
+ if (rv != 0) {
+ device_printf(sc->dev, "Cannot parse FDT data\n");
+ return (rv);
+ }
+
+ rv = clk_get_by_ofw_name(sc->dev, 0, "pclk", &sc->clk);
+ if (rv != 0) {
+ device_printf(sc->dev, "Cannot get \"pclk\" clock\n");
+ return (ENXIO);
+ }
+
+ rid = 0;
+ sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
+ RF_ACTIVE);
+ if (sc->mem_res == NULL) {
+ device_printf(dev, "Cannot allocate memory resources\n");
+ return (ENXIO);
+ }
+
+ tegra210_pmc_check_secure(sc);
+
+ /* Enable CPU power request. */
+ reg = RD4(sc, PMC_CNTRL);
+ reg |= PMC_CNTRL_CPU_PWRREQ_OE;
+ WR4(sc, PMC_CNTRL, reg);
+
+ /* Set sysclk output polarity */
+ reg = RD4(sc, PMC_CNTRL);
+ if (sc->sysclkreq_high)
+ reg &= ~PMC_CNTRL_SYSCLK_POLARITY;
+ else
+ reg |= PMC_CNTRL_SYSCLK_POLARITY;
+ WR4(sc, PMC_CNTRL, reg);
+
+ /* Enable sysclk request. */
+ reg = RD4(sc, PMC_CNTRL);
+ reg |= PMC_CNTRL_SYSCLK_OE;
+ WR4(sc, PMC_CNTRL, reg);
+
+ /*
+ * Remove HDMI from deep power down mode.
+ * XXX mote this to HDMI driver
+ */
+ reg = RD4(sc, PMC_IO_DPD_STATUS);
+ reg &= ~ PMC_IO_DPD_STATUS_HDMI;
+ WR4(sc, PMC_IO_DPD_STATUS, reg);
+
+ reg = RD4(sc, PMC_IO_DPD2_STATUS);
+ reg &= ~ PMC_IO_DPD2_STATUS_HV;
+ WR4(sc, PMC_IO_DPD2_STATUS, reg);
+
+ if (pmc_sc != NULL)
+ panic("tegra210_pmc: double driver attach");
+ pmc_sc = sc;
+ return (0);
+}
+
+static device_method_t tegra210_pmc_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, tegra210_pmc_probe),
+ DEVMETHOD(device_attach, tegra210_pmc_attach),
+ DEVMETHOD(device_detach, tegra210_pmc_detach),
+
+ DEVMETHOD_END
+};
+
+static devclass_t tegra210_pmc_devclass;
+static DEFINE_CLASS_0(pmc, tegra210_pmc_driver, tegra210_pmc_methods,
+ sizeof(struct tegra210_pmc_softc));
+EARLY_DRIVER_MODULE(tegra210_pmc, simplebus, tegra210_pmc_driver,
+ tegra210_pmc_devclass, NULL, NULL, 70);
diff --git a/sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c b/sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
new file mode 100644
index 000000000000..f3ad8cf53222
--- /dev/null
+++ b/sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
@@ -0,0 +1,1963 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
+ *
+ * Copyright 2020 Michal Meloun <mmel@FreeBSD.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/malloc.h>
+#include <sys/rman.h>
+
+#include <machine/bus.h>
+
+#include <dev/extres/clk/clk.h>
+#include <dev/extres/hwreset/hwreset.h>
+#include <dev/extres/phy/phy.h>
+#include <dev/extres/regulator/regulator.h>
+#include <dev/fdt/fdt_common.h>
+#include <dev/fdt/fdt_pinctrl.h>
+#include <dev/ofw/openfirm.h>
+#include <dev/ofw/ofw_bus.h>
+#include <dev/ofw/ofw_bus_subr.h>
+
+#include <arm/nvidia/tegra_efuse.h>
+
+#include <gnu/dts/include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
+
+#include "phynode_if.h"
+
+/* FUSE calibration data. */
+#define FUSE_SKU_CALIB_0 0x0F0
+#define FUSE_SKU_CALIB_0_HS_CURR_LEVEL_123(x, i) (((x) >> (11 + ((i) - 1) * 6)) & 0x3F);
+#define FUSE_SKU_CALIB_0_HS_TERM_RANGE_ADJ(x) (((x) >> 7) & 0x0F);
+#define FUSE_SKU_CALIB_0_HS_CURR_LEVEL_0(x) (((x) >> 0) & 0x3F);
+
+#define FUSE_USB_CALIB_EXT_0 0x250
+#define FUSE_USB_CALIB_EXT_0_RPD_CTRL(x) (((x) >> 0) & 0x1F);
+
+
+/* Registers. */
+#define XUSB_PADCTL_USB2_PAD_MUX 0x004
+
+#define XUSB_PADCTL_USB2_PORT_CAP 0x008
+#define USB2_PORT_CAP_PORT_REVERSE_ID(p) (1 << (3 + (p) * 4))
+#define USB2_PORT_CAP_PORT_INTERNAL(p) (1 << (2 + (p) * 4))
+#define USB2_PORT_CAP_PORT_CAP(p, x) (((x) & 3) << ((p) * 4))
+#define USB2_PORT_CAP_PORT_CAP_OTG 0x3
+#define USB2_PORT_CAP_PORT_CAP_DEVICE 0x2
+#define USB2_PORT_CAP_PORT_CAP_HOST 0x1
+#define USB2_PORT_CAP_PORT_CAP_DISABLED 0x0
+
+#define XUSB_PADCTL_SS_PORT_MAP 0x014
+#define SS_PORT_MAP_PORT_INTERNAL(p) (1 << (3 + (p) * 4))
+#define SS_PORT_MAP_PORT_MAP(p, x) (((x) & 7) << ((p) * 4))
+
+#define XUSB_PADCTL_ELPG_PROGRAM1 0x024
+#define ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN (1 << 31)
+#define ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 30)
+#define ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN (1 << 29)
+#define ELPG_PROGRAM1_SSP_ELPG_VCORE_DOWN(x) (1 << (2 + (x) * 3))
+#define ELPG_PROGRAM1_SSP_ELPG_CLAMP_EN_EARLY(x) (1 << (1 + (x) * 3))
+#define ELPG_PROGRAM1_SSP_ELPG_CLAMP_EN(x) (1 << (0 + (x) * 3))
+
+#define XUSB_PADCTL_USB3_PAD_MUX 0x028
+#define USB3_PAD_MUX_SATA_IDDQ_DISABLE(x) (1 << (8 + (x)))
+#define USB3_PAD_MUX_PCIE_IDDQ_DISABLE(x) (1 << (1 + (x)))
+
+#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1(x) (0x084 + (x) * 0x40)
+#define USB2_BATTERY_CHRG_OTGPAD_CTL1_USBON_RPU_OVRD_VAL (1 << 23)
+#define USB2_BATTERY_CHRG_OTGPAD_CTL1_USBON_RPU_OVRD ( 1 << 22)
+#define USB2_BATTERY_CHRG_OTGPAD_CTL1_USBON_RPD_OVRD_VAL (1 << 21)
+#define USB2_BATTERY_CHRG_OTGPAD_CTL1_USBON_RPD_OVRD (1 << 20)
+#define USB2_BATTERY_CHRG_OTGPAD_CTL1_USBOP_RPU_OVRD_VAL (1 << 19)
+#define USB2_BATTERY_CHRG_OTGPAD_CTL1_USBOP_RPU_OVRD (1 << 18)
+#define USB2_BATTERY_CHRG_OTGPAD_CTL1_USBOP_RPD_OVRD_VAL (1 << 17)
+#define USB2_BATTERY_CHRG_OTGPAD_CTL1_USBOP_RPD_OVRD (1 << 16)
+#define USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_DYN_DLY(x) (((x) & 0x3) << 9)
+#define USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV(x) (((x) & 0x3) << 7)
+#define USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_FIX18 (1 << 6)
+#define USB2_BATTERY_CHRG_OTGPAD_CTL1_DIV_DET_EN (1 << 4)
+#define USB2_BATTERY_CHRG_OTGPAD_CTL1_VOP_DIV2P7_DET (1 << 3)
+#define USB2_BATTERY_CHRG_OTGPAD_CTL1_VOP_DIV2P0_DET (1 << 2)
+#define USB2_BATTERY_CHRG_OTGPAD_CTL1_VON_DIV2P7_DET (1 << 1)
+#define USB2_BATTERY_CHRG_OTGPAD_CTL1_VON_DIV2P0_DET (1 << 0)
+
+#define XUSB_PADCTL_USB2_OTG_PAD_CTL0(x) (0x088 + (x) * 0x40)
+#define USB2_OTG_PAD_CTL0_PD_ZI (1 << 29)
+#define USB2_OTG_PAD_CTL0_PD2_OVRD_EN (1 << 28)
+#define USB2_OTG_PAD_CTL0_PD2 (1 << 27)
+#define USB2_OTG_PAD_CTL0_PD (1 << 26)
+#define USB2_OTG_PAD_CTL0_TERM_EN (1 << 25)
+#define USB2_OTG_PAD_CTL0_LS_FSLEW(x) (((x) & 0x0F) << 21)
+#define USB2_OTG_PAD_CTL0_LS_RSLEW(x) (((x) & 0x0F) << 17)
+#define USB2_OTG_PAD_CTL0_FS_FSLEW(x) (((x) & 0x0F) << 13)
+#define USB2_OTG_PAD_CTL0_FS_RSLEW(x) (((x) & 0x0F) << 9)
+#define USB2_OTG_PAD_CTL0_HS_SLEW(x) (((x) & 0x3F) << 6)
+#define USB2_OTG_PAD_CTL0_HS_CURR_LEVEL(x) (((x) & 0x3F) << 0)
+
+#define XUSB_PADCTL_USB2_OTG_PAD_CTL1(x) (0x08C + (x) * 0x40)
+#define USB2_OTG_PAD_CTL1_RPD_CTRL(x) (((x) & 0x1F) << 26)
+#define USB2_OTG_PAD_CTL1_RPU_STATUS_HIGH (1 << 25)
+#define USB2_OTG_PAD_CTL1_RPU_SWITCH_LOW (1 << 24)
+#define USB2_OTG_PAD_CTL1_RPU_SWITCH_OVRD (1 << 23)
+#define USB2_OTG_PAD_CTL1_HS_LOOPBACK_OVRD_VAL (1 << 22)
+#define USB2_OTG_PAD_CTL1_HS_LOOPBACK_OVRD_EN (1 << 21)
+#define USB2_OTG_PAD_CTL1_PTERM_RANGE_ADJ(x) (((x) & 0x0F) << 17)
+#define USB2_OTG_PAD_CTL1_PD_DISC_OVRD_VAL (1 << 16)
+#define USB2_OTG_PAD_CTL1_PD_CHRP_OVRD_VAL (1 << 15)
+#define USB2_OTG_PAD_CTL1_RPU_RANGE_ADJ(x) (((x) & 0x03) << 13)
+#define USB2_OTG_PAD_CTL1_HS_COUP_EN(x) (((x) & 0x03) << 11)
+#define USB2_OTG_PAD_CTL1_SPARE(x) (((x) & 0x0F) << 7)
+#define USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ(x) (((x) & 0x0F) << 3)
+#define USB2_OTG_PAD_CTL1_PD_DR (1 << 2)
+#define USB2_OTG_PAD_CTL1_PD_DISC_OVRD (1 << 1)
+#define USB2_OTG_PAD_CTL1_PD_CHRP_OVRD (1 << 0)
+
+#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL0(x) (0x0C0 + (x) * 0x40)
+#define XUSB_PADCTL_USB2_BIAS_PAD_CTL0 0x0284
+#define USB2_BIAS_PAD_CTL0_TRK_PWR_ENA (1 << 29)
+#define USB2_BIAS_PAD_CTL0_SPARE(x) (((x) & 0xF) << 25)
+#define USB2_BIAS_PAD_CTL0_CHG_DIV(x) (((x) & 0xF) << 21)
+#define USB2_BIAS_PAD_CTL0_TEMP_COEF(x) (((x) & 0x7) << 18)
+#define USB2_BIAS_PAD_CTL0_VREF_CTRL(x) (((x) & 0x7) << 15)
+#define USB2_BIAS_PAD_CTL0_ADJRPU(x) (((x) & 0x7) << 12)
+#define USB2_BIAS_PAD_CTL0_PD (1 << 11)
+#define USB2_BIAS_PAD_CTL0_TERM_OFFSETL(x) (((x) & 0x7) << 8)
+#define USB2_BIAS_PAD_CTL0_HS_CHIRP_LEVEL(x) (((x) & 0x3) << 6)
+#define USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL(x) (((x) & 0x7) << 3)
+#define USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL(x) (((x) & 0x7) << 0)
+
+#define XUSB_PADCTL_USB2_BIAS_PAD_CTL1 0x0288
+#define USB2_BIAS_PAD_CTL1_FORCE_TRK_CLK_EN (1 << 30)
+#define USB2_BIAS_PAD_CTL1_TRK_SW_OVRD (1 << 29)
+#define USB2_BIAS_PAD_CTL1_TRK_DONE (1 << 28)
+#define USB2_BIAS_PAD_CTL1_TRK_START (1 << 27)
+#define USB2_BIAS_PAD_CTL1_PD_TRK (1 << 26)
+#define USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER(x) (((x) & 0x7F) << 19)
+#define USB2_BIAS_PAD_CTL1_TRK_START_TIMER(x) (((x) & 0x7F) << 12)
+#define USB2_BIAS_PAD_CTL1_PCTRL(x) (((x) & 0x3F) << 6)
+#define USB2_BIAS_PAD_CTL1_TCTRL(x) (((x) & 0x3F) << 0)
+
+#define XUSB_PADCTL_HSIC_PAD_CTL0(x) (0x300 + (x) * 0x20)
+#define HSIC_PAD_CTL0_RPU_STROBE (1 << 18)
+#define HSIC_PAD_CTL0_RPU_DATA1 (1 << 17)
+#define HSIC_PAD_CTL0_RPU_DATA0 (1 << 16)
+#define HSIC_PAD_CTL0_RPD_STROBE (1 << 15)
+#define HSIC_PAD_CTL0_RPD_DATA1 (1 << 14)
+#define HSIC_PAD_CTL0_RPD_DATA0 (1 << 13)
+#define HSIC_PAD_CTL0_LPBK_STROBE (1 << 12)
+#define HSIC_PAD_CTL0_LPBK_DATA1 (1 << 11)
+#define HSIC_PAD_CTL0_LPBK_DATA0 (1 << 10)
+#define HSIC_PAD_CTL0_PD_ZI_STROBE (1 << 9)
+#define HSIC_PAD_CTL0_PD_ZI_DATA1 (1 << 8)
+#define HSIC_PAD_CTL0_PD_ZI_DATA0 (1 << 7)
+#define HSIC_PAD_CTL0_PD_RX_STROBE (1 << 6)
+#define HSIC_PAD_CTL0_PD_RX_DATA1 (1 << 5)
+#define HSIC_PAD_CTL0_PD_RX_DATA0 (1 << 4)
+#define HSIC_PAD_CTL0_PD_TX_STROBE (1 << 3)
+#define HSIC_PAD_CTL0_PD_TX_DATA1 (1 << 2)
+#define HSIC_PAD_CTL0_PD_TX_DATA0 (1 << 1)
+#define HSIC_PAD_CTL0_IDDQ (1 << 0)
+
+#define XUSB_PADCTL_HSIC_PAD_CTL1(x) (0x304 + (x) * 0x20)
+#define HSIC_PAD_CTL1_RTERM(x) (((x) & 0xF) << 12)
+#define HSIC_PAD_CTL1_HSIC_OPT(x) (((x) & 0xF) << 8)
+#define HSIC_PAD_CTL1_TX_SLEW(x) (((x) & 0xF) << 4)
+#define HSIC_PAD_CTL1_TX_RTUNEP(x) (((x) & 0xF) << 0)
+
+#define XUSB_PADCTL_HSIC_PAD_CTL2(x) (0x308 + (x) * 0x20)
+#define HSIC_PAD_CTL2_RX_STROBE_TRIM(x) (((x) & 0xF) << 8)
+#define HSIC_PAD_CTL2_RX_DATA1_TRIM(x) (((x) & 0xF) << 4)
+#define HSIC_PAD_CTL2_RX_DATA0_TRIM(x) (((x) & 0xF) << 0)
+
+#define XUSB_PADCTL_HSIC_PAD_TRK_CTL 0x340
+#define HSIC_PAD_TRK_CTL_AUTO_RTERM_EN (1 << 24)
+#define HSIC_PAD_TRK_CTL_FORCE_TRK_CLK_EN (1 << 23)
+#define HSIC_PAD_TRK_CTL_TRK_SW_OVRD (1 << 22)
+#define HSIC_PAD_TRK_CTL_TRK_DONE (1 << 21)
+#define HSIC_PAD_TRK_CTL_TRK_START (1 << 20)
+#define HSIC_PAD_TRK_CTL_PD_TRK (1 << 19)
+#define HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER(x) (((x) & 0x3F) << 12)
+#define HSIC_PAD_TRK_CTL_TRK_START_TIMER(x) (((x) & 0x7F) << 5)
+#define HSIC_PAD_TRK_CTL_RTERM_OUT(x) (((x) & 0x1F) << 0)
+
+#define XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL 0x344
+
+#define XUSB_PADCTL_UPHY_PLL_P0_CTL1 0x360
+#define UPHY_PLL_P0_CTL1_PLL0_FREQ_PSDIV(x) (((x) & 0x03) << 28)
+#define UPHY_PLL_P0_CTL1_PLL0_FREQ_NDIV(x) (((x) & 0xFF) << 20)
+#define UPHY_PLL_P0_CTL1_PLL0_FREQ_MDIV(x) (((x) & 0x03) << 16)
+#define UPHY_PLL_P0_CTL1_PLL0_LOCKDET_STATUS (1 << 15)
+#define UPHY_PLL_P0_CTL1_PLL0_MODE_GET(x) (((x) >> 8) & 0x03)
+#define UPHY_PLL_P0_CTL1_PLL0_BYPASS_EN (1 << 7)
+#define UPHY_PLL_P0_CTL1_PLL0_FREERUN_EN (1 << 6)
+#define UPHY_PLL_P0_CTL1_PLL0_PWR_OVRD (1 << 4)
+#define UPHY_PLL_P0_CTL1_PLL0_ENABLE (1 << 3)
+#define UPHY_PLL_P0_CTL1_PLL0_SLEEP(x) (((x) & 0x03) << 1)
+#define UPHY_PLL_P0_CTL1_PLL0_IDDQ (1 << 0)
+
+#define XUSB_PADCTL_UPHY_PLL_P0_CTL2 0x364
+#define UPHY_PLL_P0_CTL2_PLL0_CAL_CTRL(x) (((x) & 0xFFFFFF) << 4)
+#define UPHY_PLL_P0_CTL2_PLL0_CAL_RESET (1 << 3)
+#define UPHY_PLL_P0_CTL2_PLL0_CAL_OVRD (1 << 2)
+#define UPHY_PLL_P0_CTL2_PLL0_CAL_DONE (1 << 1)
+#define UPHY_PLL_P0_CTL2_PLL0_CAL_EN (1 << 0)
+
+#define XUSB_PADCTL_UPHY_PLL_P0_CTL4 0x36c
+#define UPHY_PLL_P0_CTL4_PLL0_TCLKOUT_EN (1 << 28)
+#define UPHY_PLL_P0_CTL4_PLL0_CLKDIST_CTRL(x) (((x) & 0xF) << 20)
+#define UPHY_PLL_P0_CTL4_PLL0_XDIGCLK_EN (1 << 19)
+#define UPHY_PLL_P0_CTL4_PLL0_XDIGCLK_SEL(x) (((x) & 0x7) << 16)
+#define UPHY_PLL_P0_CTL4_PLL0_TXCLKREF_EN (1 << 15)
+#define UPHY_PLL_P0_CTL4_PLL0_TXCLKREF_SEL(x) (((x) & 0x3) << 12)
+#define UPHY_PLL_P0_CTL4_PLL0_FBCLKBUF_EN (1 << 9)
+#define UPHY_PLL_P0_CTL4_PLL0_REFCLKBUF_EN (1 << 8)
+#define UPHY_PLL_P0_CTL4_PLL0_REFCLK_SEL(x) (((x) & 0xF) << 4)
+#define UPHY_PLL_P0_CTL4_PLL0_REFCLK_TERM100 (1 << 0)
+
+#define XUSB_PADCTL_UPHY_PLL_P0_CTL5 0x370
+#define UPHY_PLL_P0_CTL5_PLL0_DCO_CTRL(x) (((x) & 0xFF) << 16)
+#define UPHY_PLL_P0_CTL5_PLL0_LPF_CTRL(x) (((x) & 0xFF) << 8)
+#define UPHY_PLL_P0_CTL5_PLL0_CP_CTRL(x) (((x) & 0x0F) << 4)
+#define UPHY_PLL_P0_CTL5_PLL0_PFD_CTRL(x) (((x) & 0x03) << 0)
+
+#define XUSB_PADCTL_UPHY_PLL_P0_CTL8 0x37c
+#define UPHY_PLL_P0_CTL8_PLL0_RCAL_DONE (1U << 31)
+#define UPHY_PLL_P0_CTL8_PLL0_RCAL_VAL(x) (((x) & 0x1F) << 24)
+#define UPHY_PLL_P0_CTL8_PLL0_RCAL_BYP_EN (1 << 23)
+#define UPHY_PLL_P0_CTL8_PLL0_RCAL_BYP_CODE(x) (((x) & 0x1F) << 16)
+#define UPHY_PLL_P0_CTL8_PLL0_RCAL_OVRD (1 << 15)
+#define UPHY_PLL_P0_CTL8_PLL0_RCAL_CLK_EN (1 << 13)
+#define UPHY_PLL_P0_CTL8_PLL0_RCAL_EN (1 << 12)
+#define UPHY_PLL_P0_CTL8_PLL0_BGAP_CTRL(x) (((x) & 0xFFF) << 0)
+
+#define XUSB_PADCTL_UPHY_MISC_PAD_P_CTL1(x) (0x460 + (x) * 0x40)
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL1 0x860
+#define UPHY_PLL_S0_CTL1_PLL0_FREQ_PSDIV(x) (((x) & 0x03) << 28)
+#define UPHY_PLL_S0_CTL1_PLL0_FREQ_NDIV(x) (((x) & 0xFF) << 20)
+#define UPHY_PLL_S0_CTL1_PLL0_FREQ_MDIV(x) (((x) & 0x03) << 16)
+#define UPHY_PLL_S0_CTL1_PLL0_LOCKDET_STATUS (1 << 15)
+#define UPHY_PLL_S0_CTL1_PLL0_MODE_GET(x) (((x) >> 8) & 0x03)
+#define UPHY_PLL_S0_CTL1_PLL0_BYPASS_EN (1 << 7)
+#define UPHY_PLL_S0_CTL1_PLL0_FREERUN_EN (1 << 6)
+#define UPHY_PLL_S0_CTL1_PLL0_PWR_OVRD (1 << 4)
+#define UPHY_PLL_S0_CTL1_PLL0_ENABLE (1 << 3)
+#define UPHY_PLL_S0_CTL1_PLL0_SLEEP(x) (((x) & 0x03) << 1)
+#define UPHY_PLL_S0_CTL1_PLL0_IDDQ (1 << 0)
+
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL2 0x864
+#define UPHY_PLL_S0_CTL2_PLL0_CAL_CTRL(x) (((x) & 0xFFFFFF) << 4)
+#define UPHY_PLL_S0_CTL2_PLL0_CAL_RESET (1 << 3)
+#define UPHY_PLL_S0_CTL2_PLL0_CAL_OVRD (1 << 2)
+#define UPHY_PLL_S0_CTL2_PLL0_CAL_DONE (1 << 1)
+#define UPHY_PLL_S0_CTL2_PLL0_CAL_EN (1 << 0)
+
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL4 0x86c
+#define UPHY_PLL_S0_CTL4_PLL0_TCLKOUT_EN (1 << 28)
+#define UPHY_PLL_S0_CTL4_PLL0_CLKDIST_CTRL(x) (((x) & 0xF) << 20)
+#define UPHY_PLL_S0_CTL4_PLL0_XDIGCLK_EN (1 << 19)
+#define UPHY_PLL_S0_CTL4_PLL0_XDIGCLK_SEL(x) (((x) & 0x7) << 16)
+#define UPHY_PLL_S0_CTL4_PLL0_TXCLKREF_EN (1 << 15)
+#define UPHY_PLL_S0_CTL4_PLL0_TXCLKREF_SEL(x) (((x) & 0x3) << 12)
+#define UPHY_PLL_S0_CTL4_PLL0_FBCLKBUF_EN (1 << 9)
+#define UPHY_PLL_S0_CTL4_PLL0_REFCLKBUF_EN (1 << 8)
+#define UPHY_PLL_S0_CTL4_PLL0_REFCLK_SEL(x) (((x) & 0xF) << 4)
+#define UPHY_PLL_S0_CTL4_PLL0_REFCLK_TERM100 (1 << 0)
+
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL5 0x870
+#define UPHY_PLL_S0_CTL5_PLL0_DCO_CTRL(x) (((x) & 0xFF) << 16)
+#define UPHY_PLL_S0_CTL5_PLL0_LPF_CTRL(x) (((x) & 0xFF) << 8)
+#define UPHY_PLL_S0_CTL5_PLL0_CP_CTRL(x) (((x) & 0x0F) << 4)
+#define UPHY_PLL_S0_CTL5_PLL0_PFD_CTRL(x) (((x) & 0x03) << 0)
+
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL8 0x87c
+#define UPHY_PLL_S0_CTL8_PLL0_RCAL_DONE (1U << 31)
+#define UPHY_PLL_S0_CTL8_PLL0_RCAL_VAL(x) (((x) & 0x1F) << 24)
+#define UPHY_PLL_S0_CTL8_PLL0_RCAL_BYP_EN (1 << 23)
+#define UPHY_PLL_S0_CTL8_PLL0_RCAL_BYP_CODE(x) (((x) & 0x1F) << 16)
+#define UPHY_PLL_S0_CTL8_PLL0_RCAL_OVRD (1 << 15)
+#define UPHY_PLL_S0_CTL8_PLL0_RCAL_CLK_EN (1 << 13)
+#define UPHY_PLL_S0_CTL8_PLL0_RCAL_EN (1 << 12)
+#define UPHY_PLL_S0_CTL8_PLL0_BGAP_CTRL(x) (((x) & 0xFFF) << 0)
+
+#define XUSB_PADCTL_UPHY_MISC_PAD_S0_CTL1 0x960
+#define XUSB_PADCTL_UPHY_USB3_PAD_ECTL1(x) (0xa60 + (x) * 0x40)
+#define UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL(x) (((x) & 0x3) << 16)
+
+#define XUSB_PADCTL_UPHY_USB3_PAD_ECTL2(x) (0xa64 + (x) * 0x40)
+#define UPHY_USB3_PAD_ECTL2_RX_IQ_CTRL(x) (((x) & 0x000F) << 16)
+#define UPHY_USB3_PAD_ECTL2_RX_CTLE(x) (((x) & 0xFFFF) << 0)
+
+#define XUSB_PADCTL_UPHY_USB3_PAD_ECTL3(x) (0xa68 + (x) * 0x40)
+#define XUSB_PADCTL_UPHY_USB3_PAD_ECTL4(x) (0xa6c + (x) * 0x40)
+#define UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL(x) (((x) & 0xFFFF) << 16)
+#define UPHY_USB3_PAD_ECTL4_RX_PI_CTRL(x) (((x) & 0x00FF) << 0)
+
+#define XUSB_PADCTL_UPHY_USB3_PAD_ECTL6(x) (0xa74 + (x) * 0x40)
+
+
+#define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v))
+#define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r))
+
+
+struct padctl_softc {
+ device_t dev;
+ struct resource *mem_res;
+ hwreset_t rst;
+ int phy_ena_cnt;
+ int pcie_ena_cnt;
+ int sata_ena_cnt;
+
+ /* Fuses calibration data */
+ /* USB2 */
+ uint32_t hs_curr_level[4];
+ uint32_t hs_curr_level_offs; /* Not inited yet, always 0 */
+ uint32_t hs_term_range_adj;
+ uint32_t rpd_ctrl;
+
+ /* HSIC */
+ uint32_t rx_strobe_trim; /* Not inited yet, always 0 */
+ uint32_t rx_data0_trim; /* Not inited yet, always 0 */
+ uint32_t rx_data1_trim; /* Not inited yet, always 0 */
+ uint32_t tx_rtune_p; /* Not inited yet, always 0 */
+ uint32_t strobe_trim; /* Not inited yet, always 0 */
+};
+
+static struct ofw_compat_data compat_data[] = {
+ {"nvidia,tegra210-xusb-padctl", 1},
+ {NULL, 0},
+};
+
+/* Ports. */
+enum padctl_port_type {
+ PADCTL_PORT_USB2,
+ PADCTL_PORT_HSIC,
+ PADCTL_PORT_USB3,
+};
+
+struct padctl_lane;
+struct padctl_port {
+ enum padctl_port_type type;
+ const char *name;
+ const char *base_name;
+ int idx;
+ int (*init)(struct padctl_softc *sc,
+ struct padctl_port *port);
+
+ /* Runtime data. */
+ phandle_t xref;
+ bool enabled;
+ bool internal;
+ uint32_t companion;
+ regulator_t supply_vbus;
+ struct padctl_lane *lane;
+};
+
+static int usb3_port_init(struct padctl_softc *sc, struct padctl_port *port);
+
+#define PORT(t, n, p, i) { \
+ .type = t, \
+ .name = n "-" #p, \
+ .base_name = n, \
+ .idx = p, \
+ .init = i, \
+}
+static struct padctl_port ports_tbl[] = {
+ PORT(PADCTL_PORT_USB2, "usb2", 0, NULL),
+ PORT(PADCTL_PORT_USB2, "usb2", 1, NULL),
+ PORT(PADCTL_PORT_USB2, "usb2", 2, NULL),
+ PORT(PADCTL_PORT_USB2, "usb2", 3, NULL),
+ PORT(PADCTL_PORT_HSIC, "hsic", 0, NULL),
+ PORT(PADCTL_PORT_HSIC, "hsic", 1, NULL),
+ PORT(PADCTL_PORT_USB3, "usb3", 0, usb3_port_init),
+ PORT(PADCTL_PORT_USB3, "usb3", 1, usb3_port_init),
+};
+
+/* Pads - a group of lannes. */
+enum padctl_pad_type {
+ PADCTL_PAD_USB2,
+ PADCTL_PAD_HSIC,
+ PADCTL_PAD_PCIE,
+ PADCTL_PAD_SATA,
+};
+
+struct padctl_lane;
+struct padctl_pad {
+ const char *name;
+ enum padctl_pad_type type;
+ const char *clock_name;
+ char *reset_name; /* XXX constify !!!!!! */
+ int (*enable)(struct padctl_softc *sc,
+ struct padctl_lane *lane);
+ int (*disable)(struct padctl_softc *sc,
+ struct padctl_lane *lane);
+ /* Runtime data. */
+ bool enabled;
+ clk_t clk;
+ hwreset_t reset;
+ int nlanes;
+ struct padctl_lane *lanes[8]; /* Safe maximum value. */
+};
+
+static int usb2_enable(struct padctl_softc *sc, struct padctl_lane *lane);
+static int usb2_disable(struct padctl_softc *sc, struct padctl_lane *lane);
+static int hsic_enable(struct padctl_softc *sc, struct padctl_lane *lane);
+static int hsic_disable(struct padctl_softc *sc, struct padctl_lane *lane);
+static int pcie_enable(struct padctl_softc *sc, struct padctl_lane *lane);
+static int pcie_disable(struct padctl_softc *sc, struct padctl_lane *lane);
+static int sata_enable(struct padctl_softc *sc, struct padctl_lane *lane);
+static int sata_disable(struct padctl_softc *sc, struct padctl_lane *lane);
+
+#define PAD(n, t, cn, rn, e, d) { \
+ .name = n, \
+ .type = t, \
+ .clock_name = cn, \
+ .reset_name = rn, \
+ .enable = e, \
+ .disable = d, \
+}
+static struct padctl_pad pads_tbl[] = {
+ PAD("usb2", PADCTL_PAD_USB2, "trk", NULL, usb2_enable, usb2_disable),
+ PAD("hsic", PADCTL_PAD_HSIC, "trk", NULL, hsic_enable, hsic_disable),
+ PAD("pcie", PADCTL_PAD_PCIE, "pll", "phy", pcie_enable, pcie_disable),
+ PAD("sata", PADCTL_PAD_SATA, "pll", "phy", sata_enable, sata_disable),
+};
+
+/* Lanes. */
+static char *usb_mux[] = {"snps", "xusb", "uart", "rsvd"};
+static char *hsic_mux[] = {"snps", "xusb"};
+static char *pci_mux[] = {"pcie-x1", "usb3-ss", "sata", "pcie-x4"};
+
+struct padctl_lane {
+ const char *name;
+ int idx;
+ bus_size_t reg;
+ uint32_t shift;
+ uint32_t mask;
+ char **mux;
+ int nmux;
+ /* Runtime data. */
+ bool enabled;
+ phandle_t xref;
+ struct padctl_pad *pad;
+ struct padctl_port *port;
+ int mux_idx;
+
+};
+
+#define LANE(n, p, r, s, m, mx) { \
+ .name = n "-" #p, \
+ .idx = p, \
+ .reg = r, \
+ .shift = s, \
+ .mask = m, \
+ .mux = mx, \
+ .nmux = nitems(mx), \
+}
+static struct padctl_lane lanes_tbl[] = {
+ LANE("usb2", 0, XUSB_PADCTL_USB2_PAD_MUX, 0, 0x3, usb_mux),
+ LANE("usb2", 1, XUSB_PADCTL_USB2_PAD_MUX, 2, 0x3, usb_mux),
+ LANE("usb2", 2, XUSB_PADCTL_USB2_PAD_MUX, 4, 0x3, usb_mux),
+ LANE("usb2", 3, XUSB_PADCTL_USB2_PAD_MUX, 6, 0x3, usb_mux),
+ LANE("hsic", 0, XUSB_PADCTL_USB2_PAD_MUX, 14, 0x1, hsic_mux),
+ LANE("hsic", 1, XUSB_PADCTL_USB2_PAD_MUX, 15, 0x1, hsic_mux),
+ LANE("pcie", 0, XUSB_PADCTL_USB3_PAD_MUX, 12, 0x3, pci_mux),
+ LANE("pcie", 1, XUSB_PADCTL_USB3_PAD_MUX, 14, 0x3, pci_mux),
+ LANE("pcie", 2, XUSB_PADCTL_USB3_PAD_MUX, 16, 0x3, pci_mux),
+ LANE("pcie", 3, XUSB_PADCTL_USB3_PAD_MUX, 18, 0x3, pci_mux),
+ LANE("pcie", 4, XUSB_PADCTL_USB3_PAD_MUX, 20, 0x3, pci_mux),
+ LANE("pcie", 5, XUSB_PADCTL_USB3_PAD_MUX, 22, 0x3, pci_mux),
+ LANE("pcie", 6, XUSB_PADCTL_USB3_PAD_MUX, 24, 0x3, pci_mux),
+ LANE("sata", 0, XUSB_PADCTL_USB3_PAD_MUX, 30, 0x3, pci_mux),
+};
+
+/* Define all possible mappings for USB3 port lanes */
+struct padctl_lane_map {
+ int port_idx;
+ enum padctl_pad_type pad_type;
+ int lane_idx;
+};
+
+#define LANE_MAP(pi, pt, li) { \
+ .port_idx = pi, \
+ .pad_type = pt, \
+ .lane_idx = li, \
+}
+static struct padctl_lane_map lane_map_tbl[] = {
+ LANE_MAP(0, PADCTL_PAD_PCIE, 6), /* port USB3-0 -> lane PCIE-0 */
+ LANE_MAP(1, PADCTL_PAD_PCIE, 5), /* port USB3-1 -> lane PCIE-1 */
+ LANE_MAP(2, PADCTL_PAD_PCIE, 0), /* port USB3-2 -> lane PCIE-0 */
+ LANE_MAP(2, PADCTL_PAD_PCIE, 2), /* port USB3-2 -> lane PCIE-2 */
+ LANE_MAP(3, PADCTL_PAD_PCIE, 4), /* port USB3-3 -> lane PCIE-4 */
+};
+
+/* Phy class and methods. */
+static int xusbpadctl_phy_enable(struct phynode *phy, bool enable);
+static phynode_method_t xusbpadctl_phynode_methods[] = {
+ PHYNODEMETHOD(phynode_enable, xusbpadctl_phy_enable),
+ PHYNODEMETHOD_END
+
+};
+DEFINE_CLASS_1(xusbpadctl_phynode, xusbpadctl_phynode_class,
+ xusbpadctl_phynode_methods, 0, phynode_class);
+
+static struct padctl_port *search_lane_port(struct padctl_softc *sc,
+ struct padctl_lane *lane);
+
+
+static void tegra210_xusb_pll_hw_control_enable(void) {}
+static void tegra210_xusb_pll_hw_sequence_start(void) {}
+static void tegra210_sata_pll_hw_control_enable(void) {}
+static void tegra210_sata_pll_hw_sequence_start(void) {}
+
+/* -------------------------------------------------------------------------
+ *
+ * PEX functions
+ */
+static int
+uphy_pex_enable(struct padctl_softc *sc, struct padctl_pad *pad)
+{
+ uint32_t reg;
+ int rv, i;
+
+ if (sc->pcie_ena_cnt > 0) {
+ sc->pcie_ena_cnt++;
+ return (0);
+ }
+
+ /* 22.8.4 UPHY PLLs, Step 4, page 1346 */
+ /* 1. Deassert PLL/Lane resets. */
+ rv = clk_enable(pad->clk);
+ if (rv < 0) {
+ device_printf(sc->dev, "Cannot enable clock for pad '%s': %d\n",
+ pad->name, rv);
+ return (rv);
+ }
+
+ rv = hwreset_deassert(pad->reset);
+ if (rv < 0) {
+ device_printf(sc->dev, "Cannot unreset pad '%s': %d\n",
+ pad->name, rv);
+ clk_disable(pad->clk);
+ return (rv);
+ }
+
+ reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
+ reg &= ~UPHY_PLL_P0_CTL2_PLL0_CAL_CTRL(~0);
+ reg |= UPHY_PLL_P0_CTL2_PLL0_CAL_CTRL(0x136);
+ WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg);
+
+ reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL5);
+ reg &= ~UPHY_PLL_P0_CTL5_PLL0_DCO_CTRL(~0);
+ reg |= UPHY_PLL_P0_CTL5_PLL0_DCO_CTRL(0x2a);
+ WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL5, reg);
+
+ reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
+ reg |= UPHY_PLL_P0_CTL1_PLL0_PWR_OVRD;
+ WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg);
+
+ reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
+ reg |= UPHY_PLL_P0_CTL2_PLL0_CAL_OVRD;
+ WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg);
+
+ reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
+ reg |= UPHY_PLL_P0_CTL8_PLL0_RCAL_OVRD;
+ WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8, reg);
+
+ /*
+ * 2. For the following registers, default values
+ * take care of the desired frequency.
+ */
+ reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
+ reg &= ~UPHY_PLL_P0_CTL4_PLL0_TXCLKREF_SEL(~0);
+ reg &= ~UPHY_PLL_P0_CTL4_PLL0_REFCLK_SEL(~0);
+ reg |= UPHY_PLL_P0_CTL4_PLL0_TXCLKREF_SEL(0x2);
+ reg |= UPHY_PLL_P0_CTL4_PLL0_TXCLKREF_EN;
+ WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL4, reg);
+
+ reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
+ reg &= ~UPHY_PLL_P0_CTL1_PLL0_FREQ_MDIV(~0);
+ reg &= ~UPHY_PLL_P0_CTL1_PLL0_FREQ_NDIV(~0);
+ reg |= UPHY_PLL_P0_CTL1_PLL0_FREQ_NDIV(0x19);
+ WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg);
+
+ reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
+ reg &= ~UPHY_PLL_P0_CTL1_PLL0_IDDQ;
+ WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg);
+
+ reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
+ reg &= ~UPHY_PLL_P0_CTL1_PLL0_SLEEP(~0);
+ WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg);
+
+ /* 3. Wait 100 ns. */
+ DELAY(10);
+
+ /* XXX This in not in TRM */
+ reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
+ reg |= UPHY_PLL_P0_CTL4_PLL0_REFCLKBUF_EN;
+ WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL4, reg);
+
+ /* 4. Calibration. */
+ reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
+ reg |= UPHY_PLL_P0_CTL2_PLL0_CAL_EN;
+ WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg);
+ for (i = 30; i > 0; i--) {
+ reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
+ if (reg & UPHY_PLL_P0_CTL2_PLL0_CAL_DONE)
+ break;
+ DELAY(10);
+ }
+ if (i <= 0) {
+ device_printf(sc->dev, "Timedout in calibration step 1 "
+ "for pad '%s' (0x%08X).\n", pad->name, reg);
+ rv = ETIMEDOUT;
+ goto err;
+ }
+
+ reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
+ reg &= ~UPHY_PLL_P0_CTL2_PLL0_CAL_EN;
+ WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg);
+ for (i = 10; i > 0; i--) {
+ reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
+ if ((reg & UPHY_PLL_P0_CTL2_PLL0_CAL_DONE) == 0)
+ break;
+ DELAY(10);
+ }
+ if (i <= 0) {
+ device_printf(sc->dev, "Timedout in calibration step 2 "
+ "for pad '%s'.\n", pad->name);
+ rv = ETIMEDOUT;
+ goto err;
+ }
+
+ /* 5. Enable the PLL (20 Ás Lock time) */
+ reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
+ reg |= UPHY_PLL_P0_CTL1_PLL0_ENABLE;
+ WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg);
+ for (i = 10; i > 0; i--) {
+ reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
+ if (reg & UPHY_PLL_P0_CTL1_PLL0_LOCKDET_STATUS)
+ break;
+ DELAY(10);
+ }
+ if (i <= 0) {
+ device_printf(sc->dev, "Timedout while enabling PLL "
+ "for pad '%s'.\n", pad->name);
+ rv = ETIMEDOUT;
+ goto err;
+ }
+
+ /* 6. RCAL. */
+ reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
+ reg |= UPHY_PLL_P0_CTL8_PLL0_RCAL_EN;
+ reg |= UPHY_PLL_P0_CTL8_PLL0_RCAL_CLK_EN;
+ WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8, reg);
+
+ for (i = 10; i > 0; i--) {
+ reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
+ if (reg & UPHY_PLL_P0_CTL8_PLL0_RCAL_DONE)
+ break;
+ DELAY(10);
+ }
+ if (i <= 0) {
+ device_printf(sc->dev, "Timedout in RX calibration step 1 "
+ "for pad '%s'.\n", pad->name);
+ rv = ETIMEDOUT;
+ goto err;
+ }
+
+ reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
+ reg &= ~UPHY_PLL_P0_CTL8_PLL0_RCAL_EN;
+ WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8, reg);
+
+ for (i = 10; i > 0; i--) {
+ reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
+ if (!(reg & UPHY_PLL_P0_CTL8_PLL0_RCAL_DONE))
+ break;
+
+ DELAY(10);
+ }
+ if (i <= 0) {
+ device_printf(sc->dev, "Timedout in RX calibration step 2 "
+ "for pad '%s'.\n", pad->name);
+ rv = ETIMEDOUT;
+ goto err;
+ }
+
+ reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
+ reg &= ~UPHY_PLL_P0_CTL8_PLL0_RCAL_CLK_EN;
+ WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8, reg);
+
+ /* Enable Hardware Power Sequencer. */
+ tegra210_xusb_pll_hw_control_enable();
+
+ reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
+ reg &= ~UPHY_PLL_P0_CTL1_PLL0_PWR_OVRD;
+ WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg);
+
+ reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
+ reg &= ~UPHY_PLL_P0_CTL2_PLL0_CAL_OVRD;
+ WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg);
+
+ reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
+ reg &= ~UPHY_PLL_P0_CTL8_PLL0_RCAL_OVRD;
+ WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8, reg);
+
+ DELAY(50);
+
+ tegra210_xusb_pll_hw_sequence_start();
+
+ sc->pcie_ena_cnt++;
+
+ return (0);
+
+err:
+ hwreset_deassert(pad->reset);
+ clk_disable(pad->clk);
+ return (rv);
+}
+
+static void
+uphy_pex_disable(struct padctl_softc *sc, struct padctl_pad *pad)
+{
+ int rv;
+
+ sc->pcie_ena_cnt--;
+ if (sc->pcie_ena_cnt <= 0) {
+ rv = hwreset_assert(pad->reset);
+ if (rv != 0) {
+ device_printf(sc->dev, "Cannot reset pad '%s': %d\n",
+ pad->name, rv);
+ }
+ rv = clk_disable(pad->clk);
+ if (rv != 0) {
+ device_printf(sc->dev,
+ "Cannot dicable clock for pad '%s': %d\n",
+ pad->name, rv);
+ }
+ }
+}
+
+static int
+uphy_sata_enable(struct padctl_softc *sc, struct padctl_pad *pad, bool usb)
+{
+ uint32_t reg;
+ int rv, i;
+
+ /* 22.8.4 UPHY PLLs, Step 4, page 1346 */
+ /* 1. Deassert PLL/Lane resets. */
+ if (sc->sata_ena_cnt > 0) {
+ sc->sata_ena_cnt++;
+ return (0);
+ }
+
+ rv = clk_enable(pad->clk);
+ if (rv < 0) {
+ device_printf(sc->dev, "Cannot enable clock for pad '%s': %d\n",
+ pad->name, rv);
+ return (rv);
+ }
+
+ rv = hwreset_deassert(pad->reset);
+ if (rv < 0) {
+ device_printf(sc->dev, "Cannot unreset pad '%s': %d\n",
+ pad->name, rv);
+ clk_disable(pad->clk);
+ return (rv);
+ }
+ reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
+ reg &= ~UPHY_PLL_P0_CTL2_PLL0_CAL_CTRL(~0);
+ reg |= UPHY_PLL_P0_CTL2_PLL0_CAL_CTRL(0x136);
+ WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg);
+
+ reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL5);
+ reg &= ~UPHY_PLL_P0_CTL5_PLL0_DCO_CTRL(~0);
+ reg |= UPHY_PLL_P0_CTL5_PLL0_DCO_CTRL(0x2a);
+ WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL5, reg);
+
+ reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
+ reg |= UPHY_PLL_S0_CTL1_PLL0_PWR_OVRD;
+ WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1, reg);
+
+ reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
+ reg |= UPHY_PLL_S0_CTL2_PLL0_CAL_OVRD;
+ WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2, reg);
+
+ reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
+ reg |= UPHY_PLL_S0_CTL8_PLL0_RCAL_OVRD;
+ WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8, reg);
+
+ /*
+ * 2. For the following registers, default values
+ * take care of the desired frequency.
+ */
+ reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL4);
+ reg &= ~UPHY_PLL_S0_CTL4_PLL0_TXCLKREF_SEL(~0);
+ reg &= ~UPHY_PLL_S0_CTL4_PLL0_REFCLK_SEL(~0);
+ reg |= UPHY_PLL_S0_CTL4_PLL0_TXCLKREF_EN;
+
+ if (usb)
+ reg |= UPHY_PLL_S0_CTL4_PLL0_TXCLKREF_SEL(0x2);
+ else
+ reg |= UPHY_PLL_S0_CTL4_PLL0_TXCLKREF_SEL(0x0);
+
+ /* XXX PLL0_XDIGCLK_EN */
+ /*
+ value &= ~(1 << 19);
+ WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL4, reg);
+ */
+
+ reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
+ reg &= ~UPHY_PLL_S0_CTL1_PLL0_FREQ_MDIV(~0);
+ reg &= ~UPHY_PLL_S0_CTL1_PLL0_FREQ_NDIV(~0);
+ if (usb)
+ reg |= UPHY_PLL_S0_CTL1_PLL0_FREQ_NDIV(0x19);
+ else
+ reg |= UPHY_PLL_S0_CTL1_PLL0_FREQ_NDIV(0x1e);
+ WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1, reg);
+
+ reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
+ reg &= ~UPHY_PLL_S0_CTL1_PLL0_IDDQ;
+ WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1, reg);
+
+ reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
+ reg &= ~UPHY_PLL_S0_CTL1_PLL0_SLEEP(~0);
+ WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1, reg);
+
+ /* 3. Wait 100 ns. */
+ DELAY(1);
+
+ /* XXX This in not in TRM */
+ reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL4);
+ reg |= UPHY_PLL_S0_CTL4_PLL0_REFCLKBUF_EN;
+ WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL4, reg);
+
+ /* 4. Calibration. */
+ reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
+ reg |= UPHY_PLL_S0_CTL2_PLL0_CAL_EN;
+ WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2, reg);
+ for (i = 30; i > 0; i--) {
+ reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
+ if (reg & UPHY_PLL_S0_CTL2_PLL0_CAL_DONE)
+ break;
+ DELAY(10);
+ }
+ if (i <= 0) {
+ device_printf(sc->dev, "Timedout in calibration step 1 "
+ "for pad '%s'.\n", pad->name);
+ rv = ETIMEDOUT;
+ goto err;
+ }
+
+ reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
+ reg &= ~UPHY_PLL_S0_CTL2_PLL0_CAL_EN;
+ WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2, reg);
+ for (i = 10; i > 0; i--) {
+ reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
+ if ((reg & UPHY_PLL_S0_CTL2_PLL0_CAL_DONE) == 0)
+ break;
+ DELAY(10);
+ }
+ if (i <= 0) {
+ device_printf(sc->dev, "Timedout in calibration step 2 "
+ "for pad '%s'.\n", pad->name);
+ rv = ETIMEDOUT;
+ goto err;
+ }
+
+ /* 5. Enable the PLL (20 Ás Lock time) */
+ reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
+ reg |= UPHY_PLL_S0_CTL1_PLL0_ENABLE;
+ WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1, reg);
+ for (i = 10; i > 0; i--) {
+ reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
+ if (reg & UPHY_PLL_S0_CTL1_PLL0_LOCKDET_STATUS)
+ break;
+ DELAY(10);
+ }
+ if (i <= 0) {
+ device_printf(sc->dev, "Timedout while enabling PLL "
+ "for pad '%s'.\n", pad->name);
+ rv = ETIMEDOUT;
+ goto err;
+ }
+
+ /* 6. RCAL. */
+ reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
+ reg |= UPHY_PLL_S0_CTL8_PLL0_RCAL_EN;
+ reg |= UPHY_PLL_S0_CTL8_PLL0_RCAL_CLK_EN;
+ WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8, reg);
+ for (i = 10; i > 0; i--) {
+ reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
+ if (reg & UPHY_PLL_S0_CTL8_PLL0_RCAL_DONE)
+ break;
+ DELAY(10);
+ }
+ if (i <= 0) {
+ device_printf(sc->dev, "Timedout in RX calibration step 1 "
+ "for pad '%s'.\n", pad->name);
+ rv = ETIMEDOUT;
+ goto err;
+ }
+
+ reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
+ reg &= ~UPHY_PLL_S0_CTL8_PLL0_RCAL_EN;
+ WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8, reg);
+ for (i = 10; i > 0; i--) {
+ reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
+ if (!(reg & UPHY_PLL_S0_CTL8_PLL0_RCAL_DONE))
+ break;
+ DELAY(10);
+ }
+ if (i <= 0) {
+ device_printf(sc->dev, "Timedout in RX calibration step 2 "
+ "for pad '%s'.\n", pad->name);
+ rv = ETIMEDOUT;
+ goto err;
+ }
+
+ reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
+ reg &= ~UPHY_PLL_S0_CTL8_PLL0_RCAL_CLK_EN;
+ WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8, reg);
+
+ /* Enable Hardware Power Sequencer. */
+ tegra210_sata_pll_hw_control_enable();
+
+ reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
+ reg &= ~UPHY_PLL_S0_CTL1_PLL0_PWR_OVRD;
+ WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1, reg);
+
+ reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
+ reg &= ~UPHY_PLL_S0_CTL2_PLL0_CAL_OVRD;
+ WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2, reg);
+
+ reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
+ reg &= ~UPHY_PLL_S0_CTL8_PLL0_RCAL_OVRD;
+ WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8, reg);
+
+ DELAY(50);
+
+ tegra210_sata_pll_hw_sequence_start();
+
+ sc->sata_ena_cnt++;
+
+ return (0);
+
+err:
+ hwreset_deassert(pad->reset);
+ clk_disable(pad->clk);
+ return (rv);
+}
+
+static void
+uphy_sata_disable(struct padctl_softc *sc, struct padctl_pad *pad)
+{
+ int rv;
+
+ sc->sata_ena_cnt--;
+ if (sc->sata_ena_cnt <= 0) {
+ rv = hwreset_assert(pad->reset);
+ if (rv != 0) {
+ device_printf(sc->dev, "Cannot reset pad '%s': %d\n",
+ pad->name, rv);
+ }
+ rv = clk_disable(pad->clk);
+ if (rv != 0) {
+ device_printf(sc->dev,
+ "Cannot dicable clock for pad '%s': %d\n",
+ pad->name, rv);
+ }
+ }
+}
+
+
+static int
+usb3_port_init(struct padctl_softc *sc, struct padctl_port *port)
+{
+ uint32_t reg;
+ struct padctl_pad *pad;
+ int rv;
+
+ pad = port->lane->pad;
+ reg = RD4(sc, XUSB_PADCTL_SS_PORT_MAP);
+ if (port->internal)
+ reg &= ~SS_PORT_MAP_PORT_INTERNAL(port->idx);
+ else
+ reg |= SS_PORT_MAP_PORT_INTERNAL(port->idx);
+ reg &= ~SS_PORT_MAP_PORT_MAP(port->idx, ~0);
+ reg |= SS_PORT_MAP_PORT_MAP(port->idx, port->companion);
+ WR4(sc, XUSB_PADCTL_SS_PORT_MAP, reg);
+
+ if (port->supply_vbus != NULL) {
+ rv = regulator_enable(port->supply_vbus);
+ if (rv != 0) {
+ device_printf(sc->dev,
+ "Cannot enable vbus regulator\n");
+ return (rv);
+ }
+ }
+
+ reg = RD4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL1(port->idx));
+ reg &= ~UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL(~0);
+ reg |= UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL(2);
+ WR4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL1(port->idx), reg);
+
+ reg = RD4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL2(port->idx));
+ reg &= ~UPHY_USB3_PAD_ECTL2_RX_CTLE(~0);
+ reg |= UPHY_USB3_PAD_ECTL2_RX_CTLE(0x00fc);
+ WR4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL2(port->idx), reg);
+
+ WR4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL3(port->idx), 0xc0077f1f);
+
+ reg = RD4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL4(port->idx));
+ reg &= ~UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL(~0);
+ reg |= UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL(0x01c7);
+ WR4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL4(port->idx), reg);
+
+ WR4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL6(port->idx), 0xfcf01368);
+
+ if (pad->type == PADCTL_PAD_SATA)
+ rv = uphy_sata_enable(sc, pad, true);
+ else
+ rv = uphy_pex_enable(sc, pad);
+ if (rv != 0)
+ return (rv);
+
+ reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1);
+ reg &= ~ELPG_PROGRAM1_SSP_ELPG_VCORE_DOWN(port->idx);
+ WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);
+ DELAY(100);
+
+ reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1);
+ reg &= ~ELPG_PROGRAM1_SSP_ELPG_CLAMP_EN_EARLY(port->idx);
+ WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);
+ DELAY(100);
+
+ reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1);
+ reg &= ~ELPG_PROGRAM1_SSP_ELPG_CLAMP_EN(port->idx);
+ WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);
+ DELAY(100);
+
+ return (0);
+}
+
+static int
+pcie_enable(struct padctl_softc *sc, struct padctl_lane *lane)
+{
+ uint32_t reg;
+ int rv;
+
+ rv = uphy_pex_enable(sc, lane->pad);
+ if (rv != 0)
+ return (rv);
+
+ reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX);
+ reg |= USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->idx);
+ WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);
+
+ return (0);
+}
+
+static int
+pcie_disable(struct padctl_softc *sc, struct padctl_lane *lane)
+{
+ uint32_t reg;
+
+ reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX);
+ reg &= ~USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->idx);
+ WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);
+
+ uphy_pex_disable(sc, lane->pad);
+
+ return (0);
+
+}
+
+static int
+sata_enable(struct padctl_softc *sc, struct padctl_lane *lane)
+{
+ uint32_t reg;
+ int rv;
+
+ rv = uphy_sata_enable(sc, lane->pad, false);
+ if (rv != 0)
+ return (rv);
+
+ reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX);
+ reg |= USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane->idx);
+ WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);
+
+ return (0);
+}
+
+static int
+sata_disable(struct padctl_softc *sc, struct padctl_lane *lane)
+{
+ uint32_t reg;
+
+ reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX);
+ reg &= ~USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane->idx);
+ WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg);
+
+ uphy_sata_disable(sc, lane->pad);
+
+ return (0);
+}
+
+static int
+hsic_enable(struct padctl_softc *sc, struct padctl_lane *lane)
+{
+ uint32_t reg;
+ struct padctl_pad *pad;
+ struct padctl_port *port;
+ int rv;
+
+ port = search_lane_port(sc, lane);
+ if (port == NULL) {
+ device_printf(sc->dev, "Cannot find port for lane: %s\n",
+ lane->name);
+ }
+ pad = lane->pad;
+
+ if (port->supply_vbus != NULL) {
+ rv = regulator_enable(port->supply_vbus);
+ if (rv != 0) {
+ device_printf(sc->dev,
+ "Cannot enable vbus regulator\n");
+ return (rv);
+ }
+ }
+
+ WR4(sc, XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL, sc->strobe_trim);
+
+ reg = RD4(sc, XUSB_PADCTL_HSIC_PAD_CTL1(lane->idx));
+ reg &= ~HSIC_PAD_CTL1_TX_RTUNEP(~0);
+ reg |= HSIC_PAD_CTL1_TX_RTUNEP(sc->tx_rtune_p);
+ WR4(sc, XUSB_PADCTL_HSIC_PAD_CTL1(lane->idx), reg);
+
+ reg = RD4(sc, XUSB_PADCTL_HSIC_PAD_CTL2(lane->idx));
+ reg &= ~HSIC_PAD_CTL2_RX_STROBE_TRIM(~0);
+ reg &= ~HSIC_PAD_CTL2_RX_DATA1_TRIM(~0);
+ reg &= ~HSIC_PAD_CTL2_RX_DATA0_TRIM(~0);
+ reg |= HSIC_PAD_CTL2_RX_STROBE_TRIM(sc->rx_strobe_trim);
+ reg |= HSIC_PAD_CTL2_RX_DATA1_TRIM(sc->rx_data1_trim);
+ reg |= HSIC_PAD_CTL2_RX_DATA0_TRIM(sc->rx_data0_trim);
+ WR4(sc, XUSB_PADCTL_HSIC_PAD_CTL2(lane->idx), reg);
+
+ reg = RD4(sc, XUSB_PADCTL_HSIC_PAD_CTL0(lane->idx));
+ reg &= ~HSIC_PAD_CTL0_RPU_DATA0;
+ reg &= ~HSIC_PAD_CTL0_RPU_DATA1;
+ reg &= ~HSIC_PAD_CTL0_RPU_STROBE;
+ reg &= ~HSIC_PAD_CTL0_PD_RX_DATA0;
+ reg &= ~HSIC_PAD_CTL0_PD_RX_DATA1;
+ reg &= ~HSIC_PAD_CTL0_PD_RX_STROBE;
+ reg &= ~HSIC_PAD_CTL0_PD_ZI_DATA0;
+ reg &= ~HSIC_PAD_CTL0_PD_ZI_DATA1;
+ reg &= ~HSIC_PAD_CTL0_PD_ZI_STROBE;
+ reg &= ~HSIC_PAD_CTL0_PD_TX_DATA0;
+ reg &= ~HSIC_PAD_CTL0_PD_TX_DATA1;
+ reg &= ~HSIC_PAD_CTL0_PD_TX_STROBE;
+ reg |= HSIC_PAD_CTL0_RPD_DATA0;
+ reg |= HSIC_PAD_CTL0_RPD_DATA1;
+ reg |= HSIC_PAD_CTL0_RPD_STROBE;
+ WR4(sc, XUSB_PADCTL_HSIC_PAD_CTL0(lane->idx), reg);
+
+ rv = clk_enable(pad->clk);
+ if (rv < 0) {
+ device_printf(sc->dev, "Cannot enable clock for pad '%s': %d\n",
+ pad->name, rv);
+ if (port->supply_vbus != NULL)
+ regulator_disable(port->supply_vbus);
+ return (rv);
+ }
+
+ reg = RD4(sc, XUSB_PADCTL_HSIC_PAD_TRK_CTL);
+ reg &= ~HSIC_PAD_TRK_CTL_TRK_START_TIMER(~0);
+ reg &= ~HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER(~0);
+ reg |= HSIC_PAD_TRK_CTL_TRK_START_TIMER(0x1e);
+ reg |= HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER(0x0a);
+ WR4(sc, XUSB_PADCTL_HSIC_PAD_TRK_CTL, reg);
+
+ DELAY(10);
+
+ reg = RD4(sc, XUSB_PADCTL_HSIC_PAD_TRK_CTL);
+ reg &= ~HSIC_PAD_TRK_CTL_PD_TRK;
+ WR4(sc, XUSB_PADCTL_HSIC_PAD_TRK_CTL, reg);
+
+ DELAY(50);
+ clk_disable(pad->clk);
+ return (0);
+}
+
+static int
+hsic_disable(struct padctl_softc *sc, struct padctl_lane *lane)
+{
+ uint32_t reg;
+ struct padctl_port *port;
+ int rv;
+
+ port = search_lane_port(sc, lane);
+ if (port == NULL) {
+ device_printf(sc->dev, "Cannot find port for lane: %s\n",
+ lane->name);
+ }
+
+ reg = RD4(sc, XUSB_PADCTL_HSIC_PAD_CTL0(lane->idx));
+ reg |= HSIC_PAD_CTL0_PD_RX_DATA0;
+ reg |= HSIC_PAD_CTL0_PD_RX_DATA1;
+ reg |= HSIC_PAD_CTL0_PD_RX_STROBE;
+ reg |= HSIC_PAD_CTL0_PD_ZI_DATA0;
+ reg |= HSIC_PAD_CTL0_PD_ZI_DATA1;
+ reg |= HSIC_PAD_CTL0_PD_ZI_STROBE;
+ reg |= HSIC_PAD_CTL0_PD_TX_DATA0;
+ reg |= HSIC_PAD_CTL0_PD_TX_DATA1;
+ reg |= HSIC_PAD_CTL0_PD_TX_STROBE;
+ WR4(sc, XUSB_PADCTL_HSIC_PAD_CTL1(lane->idx), reg);
+
+ if (port->supply_vbus != NULL) {
+ rv = regulator_disable(port->supply_vbus);
+ if (rv != 0) {
+ device_printf(sc->dev,
+ "Cannot disable vbus regulator\n");
+ return (rv);
+ }
+ }
+
+ return (0);
+}
+
+static int
+usb2_enable(struct padctl_softc *sc, struct padctl_lane *lane)
+{
+ uint32_t reg;
+ struct padctl_pad *pad;
+ struct padctl_port *port;
+ int rv;
+
+ port = search_lane_port(sc, lane);
+ if (port == NULL) {
+ device_printf(sc->dev, "Cannot find port for lane: %s\n",
+ lane->name);
+ }
+ pad = lane->pad;
+
+ reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
+ reg &= ~USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL(~0);
+ reg &= ~USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL(~0);
+ reg |= USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL(0x7);
+ WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0, reg);
+
+ reg = RD4(sc, XUSB_PADCTL_USB2_PORT_CAP);
+ reg &= ~USB2_PORT_CAP_PORT_CAP(lane->idx, ~0);
+ reg |= USB2_PORT_CAP_PORT_CAP(lane->idx, USB2_PORT_CAP_PORT_CAP_HOST);
+ WR4(sc, XUSB_PADCTL_USB2_PORT_CAP, reg);
+
+ reg = RD4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL0(lane->idx));
+ reg &= ~USB2_OTG_PAD_CTL0_HS_CURR_LEVEL(~0);
+ reg &= ~USB2_OTG_PAD_CTL0_HS_SLEW(~0);
+ reg &= ~USB2_OTG_PAD_CTL0_PD;
+ reg &= ~USB2_OTG_PAD_CTL0_PD2;
+ reg &= ~USB2_OTG_PAD_CTL0_PD_ZI;
+ reg |= USB2_OTG_PAD_CTL0_HS_SLEW(14);
+ reg |= USB2_OTG_PAD_CTL0_HS_CURR_LEVEL(sc->hs_curr_level[lane->idx] +
+ sc->hs_curr_level_offs);
+ WR4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL0(lane->idx), reg);
+
+ reg = RD4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL1(lane->idx));
+ reg &= ~USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ(~0);
+ reg &= ~USB2_OTG_PAD_CTL1_RPD_CTRL(~0);
+ reg &= ~USB2_OTG_PAD_CTL1_PD_DR;
+ reg &= ~USB2_OTG_PAD_CTL1_PD_CHRP_OVRD;
+ reg &= ~USB2_OTG_PAD_CTL1_PD_DISC_OVRD;
+ reg |= USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ(sc->hs_term_range_adj);
+ reg |= USB2_OTG_PAD_CTL1_RPD_CTRL(sc->rpd_ctrl);
+ WR4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL1(lane->idx), reg);
+
+ reg = RD4(sc, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1(lane->idx));
+ reg &= ~USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV(~0);
+ reg |= USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_FIX18;
+ WR4(sc, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1(lane->idx), reg);
+
+ if (port->supply_vbus != NULL) {
+ rv = regulator_enable(port->supply_vbus);
+ if (rv != 0) {
+ device_printf(sc->dev,
+ "Cannot enable vbus regulator\n");
+ return (rv);
+ }
+ }
+ rv = clk_enable(pad->clk);
+ if (rv < 0) {
+ device_printf(sc->dev, "Cannot enable clock for pad '%s': %d\n",
+ pad->name, rv);
+ if (port->supply_vbus != NULL)
+ regulator_disable(port->supply_vbus);
+ return (rv);
+ }
+ reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
+ reg &= ~USB2_BIAS_PAD_CTL1_TRK_START_TIMER(~0);
+ reg &= ~USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER(~0);
+ reg |= USB2_BIAS_PAD_CTL1_TRK_START_TIMER(0x1e);
+ reg |= USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER(0x0a);
+ WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL1, reg);
+
+ reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
+ reg &= ~USB2_BIAS_PAD_CTL0_PD;
+ WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0, reg);
+ return (0);
+}
+
+static int
+usb2_disable(struct padctl_softc *sc, struct padctl_lane *lane)
+{
+ uint32_t reg;
+ struct padctl_pad *pad;
+ struct padctl_port *port;
+ int rv;
+
+ port = search_lane_port(sc, lane);
+ if (port == NULL) {
+ device_printf(sc->dev, "Cannot find port for lane: %s\n",
+ lane->name);
+ }
+ pad = lane->pad;
+
+ reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
+ reg |= USB2_BIAS_PAD_CTL0_PD;
+ WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0, reg);
+
+ if (port->supply_vbus != NULL) {
+ rv = regulator_disable(port->supply_vbus);
+ if (rv != 0) {
+ device_printf(sc->dev,
+ "Cannot disable vbus regulator\n");
+ return (rv);
+ }
+ }
+
+ rv = clk_disable(pad->clk);
+ if (rv < 0) {
+ device_printf(sc->dev, "Cannot disable clock for pad '%s': %d\n",
+ pad->name, rv);
+ return (rv);
+ }
+
+ return (0);
+}
+
+
+static int
+pad_common_enable(struct padctl_softc *sc)
+{
+ uint32_t reg;
+
+ reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1);
+ reg &= ~ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN;
+ WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);
+ DELAY(100);
+
+ reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1);
+ reg &= ~ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY;
+ WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);
+ DELAY(100);
+
+ reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1);
+ reg &= ~ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN;
+ WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);
+ DELAY(100);
+
+ return (0);
+}
+
+static int
+pad_common_disable(struct padctl_softc *sc)
+{
+ uint32_t reg;
+
+ reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1);
+ reg |= ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN;
+ WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);
+ DELAY(100);
+
+ reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1);
+ reg |= ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY;
+ WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);
+ DELAY(100);
+
+ reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1);
+ reg |= ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN;
+ WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg);
+ DELAY(100);
+
+ return (0);
+}
+
+static int
+xusbpadctl_phy_enable(struct phynode *phy, bool enable)
+{
+ device_t dev;
+ intptr_t id;
+ struct padctl_softc *sc;
+ struct padctl_lane *lane;
+ struct padctl_pad *pad;
+ int rv;
+
+ dev = phynode_get_device(phy);
+ id = phynode_get_id(phy);
+ sc = device_get_softc(dev);
+
+ if (id < 0 || id >= nitems(lanes_tbl)) {
+ device_printf(dev, "Unknown phy: %d\n", (int)id);
+ return (ENXIO);
+ }
+
+ lane = lanes_tbl + id;
+ if (!lane->enabled) {
+ device_printf(dev, "Lane is not enabled/configured: %s\n",
+ lane->name);
+ return (ENXIO);
+ }
+
+ pad = lane->pad;
+ if (enable) {
+ if (sc->phy_ena_cnt == 0) {
+ rv = pad_common_enable(sc);
+ if (rv != 0)
+ return (rv);
+ }
+ sc->phy_ena_cnt++;
+ }
+
+ if (enable)
+ rv = pad->enable(sc, lane);
+ else
+ rv = pad->disable(sc, lane);
+ if (rv != 0)
+ return (rv);
+
+ if (!enable) {
+ if (sc->phy_ena_cnt == 1) {
+ rv = pad_common_disable(sc);
+ if (rv != 0)
+ return (rv);
+ }
+ sc->phy_ena_cnt--;
+ }
+
+ return (0);
+}
+
+/* -------------------------------------------------------------------------
+ *
+ * FDT processing
+ */
+static struct padctl_port *
+search_port(struct padctl_softc *sc, char *port_name)
+{
+ int i;
+
+ for (i = 0; i < nitems(ports_tbl); i++) {
+ if (strcmp(port_name, ports_tbl[i].name) == 0)
+ return (&ports_tbl[i]);
+ }
+ return (NULL);
+}
+
+static struct padctl_port *
+search_lane_port(struct padctl_softc *sc, struct padctl_lane *lane)
+{
+ int i;
+
+ for (i = 0; i < nitems(ports_tbl); i++) {
+ if (!ports_tbl[i].enabled)
+ continue;
+ if (ports_tbl[i].lane == lane)
+ return (ports_tbl + i);
+ }
+ return (NULL);
+}
+
+static struct padctl_lane *
+search_lane(struct padctl_softc *sc, char *lane_name)
+{
+ int i;
+
+ for (i = 0; i < nitems(lanes_tbl); i++) {
+ if (strcmp(lane_name, lanes_tbl[i].name) == 0)
+ return (lanes_tbl + i);
+ }
+ return (NULL);
+}
+
+static struct padctl_lane *
+search_pad_lane(struct padctl_softc *sc, enum padctl_pad_type type, int idx)
+{
+ int i;
+
+ for (i = 0; i < nitems(lanes_tbl); i++) {
+ if (!lanes_tbl[i].enabled)
+ continue;
+ if (type == lanes_tbl[i].pad->type && idx == lanes_tbl[i].idx)
+ return (lanes_tbl + i);
+ }
+ return (NULL);
+}
+
+static struct padctl_lane *
+search_usb3_pad_lane(struct padctl_softc *sc, int idx)
+{
+ int i;
+ struct padctl_lane *lane, *tmp;
+
+ lane = NULL;
+ for (i = 0; i < nitems(lane_map_tbl); i++) {
+ if (idx != lane_map_tbl[i].port_idx)
+ continue;
+ tmp = search_pad_lane(sc, lane_map_tbl[i].pad_type,
+ lane_map_tbl[i].lane_idx);
+ if (tmp == NULL)
+ continue;
+ if (strcmp(tmp->mux[tmp->mux_idx], "usb3-ss") != 0)
+ continue;
+ if (lane != NULL) {
+ device_printf(sc->dev, "Duplicated mappings found for"
+ " lanes: %s and %s\n", lane->name, tmp->name);
+ return (NULL);
+ }
+ lane = tmp;
+ }
+ return (lane);
+}
+
+static struct padctl_pad *
+search_pad(struct padctl_softc *sc, char *pad_name)
+{
+ int i;
+
+ for (i = 0; i < nitems(pads_tbl); i++) {
+ if (strcmp(pad_name, pads_tbl[i].name) == 0)
+ return (pads_tbl + i);
+ }
+ return (NULL);
+}
+
+static int
+search_mux(struct padctl_softc *sc, struct padctl_lane *lane, char *fnc_name)
+{
+ int i;
+
+ for (i = 0; i < lane->nmux; i++) {
+ if (strcmp(fnc_name, lane->mux[i]) == 0)
+ return (i);
+ }
+ return (-1);
+}
+
+static int
+config_lane(struct padctl_softc *sc, struct padctl_lane *lane)
+{
+ uint32_t reg;
+
+ reg = RD4(sc, lane->reg);
+ reg &= ~(lane->mask << lane->shift);
+ reg |= (lane->mux_idx & lane->mask) << lane->shift;
+ WR4(sc, lane->reg, reg);
+ return (0);
+}
+
+static int
+process_lane(struct padctl_softc *sc, phandle_t node, struct padctl_pad *pad)
+{
+ struct padctl_lane *lane;
+ struct phynode *phynode;
+ struct phynode_init_def phy_init;
+ char *name;
+ char *function;
+ int rv;
+
+ name = NULL;
+ function = NULL;
+ rv = OF_getprop_alloc(node, "name", (void **)&name);
+ if (rv <= 0) {
+ device_printf(sc->dev, "Cannot read lane name.\n");
+ return (ENXIO);
+ }
+
+ lane = search_lane(sc, name);
+ if (lane == NULL) {
+ device_printf(sc->dev, "Unknown lane: %s\n", name);
+ rv = ENXIO;
+ goto end;
+ }
+
+ /* Read function (mux) settings. */
+ rv = OF_getprop_alloc(node, "nvidia,function", (void **)&function);
+ if (rv <= 0) {
+ device_printf(sc->dev, "Cannot read lane function.\n");
+ rv = ENXIO;
+ goto end;
+ }
+
+ lane->mux_idx = search_mux(sc, lane, function);
+ if (lane->mux_idx == ~0) {
+ device_printf(sc->dev, "Unknown function %s for lane %s\n",
+ function, name);
+ rv = ENXIO;
+ goto end;
+ }
+
+ rv = config_lane(sc, lane);
+ if (rv != 0) {
+ device_printf(sc->dev, "Cannot configure lane: %s: %d\n",
+ name, rv);
+ rv = ENXIO;
+ goto end;
+ }
+ lane->xref = OF_xref_from_node(node);
+ lane->pad = pad;
+ lane->enabled = true;
+ pad->lanes[pad->nlanes++] = lane;
+
+ /* Create and register phy. */
+ bzero(&phy_init, sizeof(phy_init));
+ phy_init.id = lane - lanes_tbl;
+ phy_init.ofw_node = node;
+ phynode = phynode_create(sc->dev, &xusbpadctl_phynode_class, &phy_init);
+ if (phynode == NULL) {
+ device_printf(sc->dev, "Cannot create phy\n");
+ rv = ENXIO;
+ goto end;
+ }
+ if (phynode_register(phynode) == NULL) {
+ device_printf(sc->dev, "Cannot create phy\n");
+ return (ENXIO);
+ }
+
+ rv = 0;
+
+end:
+ if (name != NULL)
+ OF_prop_free(name);
+ if (function != NULL)
+ OF_prop_free(function);
+ return (rv);
+}
+
+static int
+process_pad(struct padctl_softc *sc, phandle_t node)
+{
+ phandle_t xref;
+ struct padctl_pad *pad;
+ char *name;
+ int rv;
+
+ name = NULL;
+ rv = OF_getprop_alloc(node, "name", (void **)&name);
+ if (rv <= 0) {
+ device_printf(sc->dev, "Cannot read pad name.\n");
+ return (ENXIO);
+ }
+
+ pad = search_pad(sc, name);
+ if (pad == NULL) {
+ device_printf(sc->dev, "Unknown pad: %s\n", name);
+ rv = ENXIO;
+ goto end;
+ }
+
+ if (pad->clock_name != NULL) {
+ rv = clk_get_by_ofw_name(sc->dev, node, pad->clock_name,
+ &pad->clk);
+ if (rv != 0) {
+ device_printf(sc->dev, "Cannot get '%s' clock\n",
+ pad->clock_name);
+ return (ENXIO);
+ }
+ }
+
+ if (pad->reset_name != NULL) {
+ rv = hwreset_get_by_ofw_name(sc->dev, node, pad->reset_name,
+ &pad->reset);
+ if (rv != 0) {
+ device_printf(sc->dev, "Cannot get '%s' reset\n",
+ pad->reset_name);
+ return (ENXIO);
+ }
+ }
+
+ /* Read and process associated lanes. */
+ node = ofw_bus_find_child(node, "lanes");
+ if (node <= 0) {
+ device_printf(sc->dev, "Cannot find 'lanes' subnode\n");
+ rv = ENXIO;
+ goto end;
+ }
+
+ for (node = OF_child(node); node != 0; node = OF_peer(node)) {
+ if (!ofw_bus_node_status_okay(node))
+ continue;
+
+ rv = process_lane(sc, node, pad);
+ if (rv != 0)
+ goto end;
+
+ xref = OF_xref_from_node(node);
+ OF_device_register_xref(xref, sc->dev);
+ }
+ pad->enabled = true;
+ rv = 0;
+end:
+ if (name != NULL)
+ OF_prop_free(name);
+ return (rv);
+}
+
+static int
+process_port(struct padctl_softc *sc, phandle_t node)
+{
+
+ struct padctl_port *port;
+ struct padctl_pad *pad;
+ char *name;
+ int rv;
+
+ name = NULL;
+ rv = OF_getprop_alloc(node, "name", (void **)&name);
+ if (rv <= 0) {
+ device_printf(sc->dev, "Cannot read port name.\n");
+ return (ENXIO);
+ }
+
+ port = search_port(sc, name);
+ if (port == NULL) {
+ device_printf(sc->dev, "Unknown port: %s\n", name);
+ rv = ENXIO;
+ goto end;
+ }
+
+ regulator_get_by_ofw_property(sc->dev, node,
+ "vbus-supply", &port->supply_vbus);
+
+ if (OF_hasprop(node, "nvidia,internal"))
+ port->internal = true;
+
+ /* Find assigned lane */
+ if (port->lane == NULL) {
+ switch(port->type) {
+ /* Routing is fixed for USB2 AND HSIC. */
+ case PADCTL_PORT_USB2:
+ port->lane = search_pad_lane(sc, PADCTL_PAD_USB2,
+ port->idx);
+ break;
+ case PADCTL_PORT_HSIC:
+ port->lane = search_pad_lane(sc, PADCTL_PAD_HSIC,
+ port->idx);
+ break;
+ case PADCTL_PORT_USB3:
+ port->lane = search_usb3_pad_lane(sc, port->idx);
+ break;
+ }
+ }
+ if (port->lane == NULL) {
+ device_printf(sc->dev, "Cannot find lane for port: %s\n", name);
+ rv = ENXIO;
+ goto end;
+ }
+
+ pad = port->lane->pad;
+ if (port->type == PADCTL_PORT_USB3) {
+ rv = OF_getencprop(node, "nvidia,usb2-companion",
+ &(port->companion), sizeof(port->companion));
+ if (rv <= 0) {
+ device_printf(sc->dev,
+ "Missing 'nvidia,usb2-companion' property "
+ "for port: %s\n", name);
+ rv = ENXIO;
+ goto end;
+ }
+ }
+
+ port->enabled = true;
+ rv = 0;
+end:
+ if (name != NULL)
+ OF_prop_free(name);
+ return (rv);
+}
+
+static int
+parse_fdt(struct padctl_softc *sc, phandle_t base_node)
+{
+ phandle_t node;
+ int rv;
+
+ rv = 0;
+ node = ofw_bus_find_child(base_node, "pads");
+
+ if (node <= 0) {
+ device_printf(sc->dev, "Cannot find pads subnode.\n");
+ return (ENXIO);
+ }
+ for (node = OF_child(node); node != 0; node = OF_peer(node)) {
+ if (!ofw_bus_node_status_okay(node))
+ continue;
+ rv = process_pad(sc, node);
+ if (rv != 0)
+ return (rv);
+ }
+
+ node = ofw_bus_find_child(base_node, "ports");
+ if (node <= 0) {
+ device_printf(sc->dev, "Cannot find ports subnode.\n");
+ return (ENXIO);
+ }
+ for (node = OF_child(node); node != 0; node = OF_peer(node)) {
+ if (!ofw_bus_node_status_okay(node))
+ continue;
+ rv = process_port(sc, node);
+ if (rv != 0)
+ return (rv);
+ }
+
+ return (0);
+}
+
+static void
+load_calibration(struct padctl_softc *sc)
+{
+ uint32_t reg;
+ int i;
+
+ reg = tegra_fuse_read_4(FUSE_SKU_CALIB_0);
+ sc->hs_curr_level[0] = FUSE_SKU_CALIB_0_HS_CURR_LEVEL_0(reg);
+ for (i = 1; i < nitems(sc->hs_curr_level); i++) {
+ sc->hs_curr_level[i] =
+ FUSE_SKU_CALIB_0_HS_CURR_LEVEL_123(reg, i);
+ }
+ sc->hs_term_range_adj = FUSE_SKU_CALIB_0_HS_TERM_RANGE_ADJ(reg);
+
+ tegra_fuse_read_4(FUSE_USB_CALIB_EXT_0);
+ sc->rpd_ctrl = FUSE_USB_CALIB_EXT_0_RPD_CTRL(reg);
+}
+
+/* -------------------------------------------------------------------------
+ *
+ * BUS functions
+ */
+static int
+xusbpadctl_probe(device_t dev)
+{
+
+ if (!ofw_bus_status_okay(dev))
+ return (ENXIO);
+
+ if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
+ return (ENXIO);
+
+ device_set_desc(dev, "Tegra XUSB phy");
+ return (BUS_PROBE_DEFAULT);
+}
+
+static int
+xusbpadctl_detach(device_t dev)
+{
+
+ /* This device is always present. */
+ return (EBUSY);
+}
+
+static int
+xusbpadctl_attach(device_t dev)
+{
+ struct padctl_softc * sc;
+ int i, rid, rv;
+ struct padctl_port *port;
+ phandle_t node;
+
+ sc = device_get_softc(dev);
+ sc->dev = dev;
+ node = ofw_bus_get_node(dev);
+ rid = 0;
+ sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
+ RF_ACTIVE);
+ if (sc->mem_res == NULL) {
+ device_printf(dev, "Cannot allocate memory resources\n");
+ return (ENXIO);
+ }
+
+ rv = hwreset_get_by_ofw_name(dev, 0, "padctl", &sc->rst);
+ if (rv != 0) {
+ device_printf(dev, "Cannot get 'padctl' reset: %d\n", rv);
+ return (rv);
+ }
+ rv = hwreset_deassert(sc->rst);
+ if (rv != 0) {
+ device_printf(dev, "Cannot unreset 'padctl' reset: %d\n", rv);
+ return (rv);
+ }
+
+ load_calibration(sc);
+
+ rv = parse_fdt(sc, node);
+ if (rv != 0) {
+ device_printf(dev, "Cannot parse fdt configuration: %d\n", rv);
+ return (rv);
+ }
+ for (i = 0; i < nitems(ports_tbl); i++) {
+ port = ports_tbl + i;
+ if (!port->enabled)
+ continue;
+ if (port->init == NULL)
+ continue;
+ rv = port->init(sc, port);
+ if (rv != 0) {
+ device_printf(dev, "Cannot init port '%s'\n",
+ port->name);
+ return (rv);
+ }
+ }
+ return (0);
+}
+
+static device_method_t tegra_xusbpadctl_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, xusbpadctl_probe),
+ DEVMETHOD(device_attach, xusbpadctl_attach),
+ DEVMETHOD(device_detach, xusbpadctl_detach),
+
+ DEVMETHOD_END
+};
+
+static devclass_t tegra_xusbpadctl_devclass;
+static DEFINE_CLASS_0(xusbpadctl, tegra_xusbpadctl_driver,
+ tegra_xusbpadctl_methods, sizeof(struct padctl_softc));
+EARLY_DRIVER_MODULE(tegra_xusbpadctl, simplebus, tegra_xusbpadctl_driver,
+ tegra_xusbpadctl_devclass, NULL, NULL, 73);
diff --git a/sys/conf/files.arm64 b/sys/conf/files.arm64
index 9a23f31dc057..439b37c12cd0 100644
--- a/sys/conf/files.arm64
+++ b/sys/conf/files.arm64
@@ -125,6 +125,21 @@ arm/mv/mv_cp110_icu.c optional mv_cp110_icu fdt
arm/mv/mv_cp110_icu_bus.c optional mv_cp110_icu fdt
arm/mv/mv_thermal.c optional SOC_MARVELL_8K mv_thermal fdt
arm/mv/armada38x/armada38x_rtc.c optional mv_rtc fdt
+arm/nvidia/tegra_abpmisc.c optional fdt soc_nvidia_tegra210
+arm/nvidia/tegra_ahci.c optional fdt soc_nvidia_tegra210
+arm/nvidia/tegra_efuse.c optional fdt soc_nvidia_tegra210
+arm/nvidia/tegra_ehci.c optional fdt soc_nvidia_tegra210
+arm/nvidia/tegra_gpio.c optional fdt soc_nvidia_tegra210
+arm/nvidia/tegra_i2c.c optional fdt soc_nvidia_tegra210
+arm/nvidia/tegra_lic.c optional fdt soc_nvidia_tegra210
+arm/nvidia/tegra_mc.c optional fdt soc_nvidia_tegra210
+arm/nvidia/tegra_pcie.c optional fdt soc_nvidia_tegra210
+arm/nvidia/tegra_sdhci.c optional fdt soc_nvidia_tegra210
+arm/nvidia/tegra_soctherm_if.m optional fdt soc_nvidia_tegra210
+arm/nvidia/tegra_soctherm.c optional fdt soc_nvidia_tegra210
+arm/nvidia/tegra_uart.c optional fdt soc_nvidia_tegra210
+arm/nvidia/tegra_usbphy.c optional fdt soc_nvidia_tegra210
+arm/nvidia/tegra_xhci.c optional fdt soc_nvidia_tegra210
arm/xilinx/uart_dev_cdnc.c optional uart soc_xilinx_zynq
arm64/acpica/acpi_iort.c optional acpi
arm64/acpica/acpi_machdep.c optional acpi
@@ -216,6 +231,19 @@ arm64/iommu/iommu_if.m optional iommu
arm64/iommu/smmu.c optional iommu
arm64/iommu/smmu_acpi.c optional acpi iommu
arm64/iommu/smmu_quirks.c optional iommu
+arm64/nvidia/tegra210/max77620.c optional fdt soc_nvidia_tegra210
+arm64/nvidia/tegra210/max77620_gpio.c optional fdt soc_nvidia_tegra210
+arm64/nvidia/tegra210/max77620_regulators.c optional fdt soc_nvidia_tegra210
+arm64/nvidia/tegra210/max77620_rtc.c optional fdt soc_nvidia_tegra210
+arm64/nvidia/tegra210/tegra210_car.c optional fdt soc_nvidia_tegra210
+arm64/nvidia/tegra210/tegra210_clk_per.c optional fdt soc_nvidia_tegra210
+arm64/nvidia/tegra210/tegra210_clk_pll.c optional fdt soc_nvidia_tegra210
+arm64/nvidia/tegra210/tegra210_clk_super.c optional fdt soc_nvidia_tegra210
+arm64/nvidia/tegra210/tegra210_coretemp.c optional fdt soc_nvidia_tegra210
+arm64/nvidia/tegra210/tegra210_cpufreq.c optional fdt soc_nvidia_tegra210
+arm64/nvidia/tegra210/tegra210_pinmux.c optional fdt soc_nvidia_tegra210
+arm64/nvidia/tegra210/tegra210_pmc.c optional fdt soc_nvidia_tegra210
+arm64/nvidia/tegra210/tegra210_xusbpadctl.c optional fdt soc_nvidia_tegra210
arm64/qoriq/ls1046_gpio.c optional ls1046_gpio gpio fdt SOC_NXP_LS
arm64/qoriq/qoriq_dw_pci.c optional pci fdt SOC_NXP_LS
arm64/qoriq/qoriq_therm.c optional pci fdt SOC_NXP_LS
@@ -426,6 +454,7 @@ arm64/rockchip/clk/rk3328_cru.c optional fdt soc_rockchip_rk3328
arm64/rockchip/clk/rk3399_cru.c optional fdt soc_rockchip_rk3399
arm64/rockchip/clk/rk3399_pmucru.c optional fdt soc_rockchip_rk3399
+
# i.MX8 Clock support
arm64/freescale/imx/imx8mq_ccm.c optional fdt soc_freescale_imx8
arm64/freescale/imx/clk/imx_clk_gate.c optional fdt soc_freescale_imx8
@@ -440,3 +469,22 @@ arm/freescale/imx/imx_i2c.c optional fsliic
arm/freescale/imx/imx_machdep.c optional fdt soc_freescale_imx8
arm64/freescale/imx/imx7gpc.c optional fdt soc_freescale_imx8
dev/ffec/if_ffec.c optional ffec
+
+# Nvidia firmware for Tegra
+tegra210_xusb_fw.c optional tegra210_xusb_fw \
+ dependency "$S/conf/files.arm64" \
+ compile-with "${AWK} -f $S/tools/fw_stub.awk tegra210_xusb.fw:tegra210_xusb_fw -mtegra210_xusb_fw -c${.TARGET}" \
+ no-implicit-rule before-depend local \
+ clean "tegra210_xusb_fw.c"
+
+tegra210_xusb.fwo optional tegra210_xusb_fw \
+ dependency "tegra210_xusb.fw" \
+ compile-with "${NORMAL_FWO}" \
+ no-implicit-rule \
+ clean "tegra210_xusb.fwo"
+
+tegra210_xusb.fw optional tegra210_xusb_fw \
+ dependency "$S/contrib/dev/nvidia/tegra210_xusb.bin.uu" \
+ compile-with "${NORMAL_FW}" \
+ no-obj no-implicit-rule \
+ clean "tegra210_xusb.fw"
diff --git a/sys/conf/options.arm64 b/sys/conf/options.arm64
index db6550ad3ae7..24e34c1e3b6a 100644
--- a/sys/conf/options.arm64
+++ b/sys/conf/options.arm64
@@ -26,6 +26,7 @@ SOC_FREESCALE_IMX8 opt_soc.h
SOC_HISI_HI6220 opt_soc.h
SOC_INTEL_STRATIX10 opt_soc.h
SOC_MARVELL_8K opt_soc.h
+SOC_NVIDIA_TEGRA210 opt_soc.h
SOC_NXP_LS opt_soc.h
SOC_ROCKCHIP_RK3328 opt_soc.h
SOC_ROCKCHIP_RK3399 opt_soc.h
diff --git a/sys/gnu/dts/arm64/nvidia/Makefile b/sys/gnu/dts/arm64/nvidia/Makefile
new file mode 100644
index 000000000000..676aa2f238d1
--- /dev/null
+++ b/sys/gnu/dts/arm64/nvidia/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra132-norrin.dtb
+dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-0000.dtb
+dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-2180.dtb
+dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2571.dtb
+dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-smaug.dtb
+dtb-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-p2771-0000.dtb