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authorRuslan Bukin <br@FreeBSD.org>2019-05-10 11:21:57 +0000
committerRuslan Bukin <br@FreeBSD.org>2019-05-10 11:21:57 +0000
commitef68f03ec2bb74993d888995c336fece24f362de (patch)
treee6842d0c98bfa0b57fb294fbef62e59e01abe036
parent16e55b9e0e8134a0847ce21bda677a55c767ab2b (diff)
downloadsrc-ef68f03ec2bb74993d888995c336fece24f362de.tar.gz
src-ef68f03ec2bb74993d888995c336fece24f362de.zip
RISC-V ISA does not specify how to manage physical memory attributes (PMA).
So do nothing in pmap_page_set_memattr() and don't panic. Reviewed by: markj Sponsored by: DARPA, AFRL Differential Revision: https://reviews.freebsd.org/D20209
Notes
Notes: svn path=/head/; revision=347427
-rw-r--r--sys/riscv/riscv/pmap.c10
1 files changed, 0 insertions, 10 deletions
diff --git a/sys/riscv/riscv/pmap.c b/sys/riscv/riscv/pmap.c
index eeeb48bb4972..96c7752699e5 100644
--- a/sys/riscv/riscv/pmap.c
+++ b/sys/riscv/riscv/pmap.c
@@ -4200,16 +4200,6 @@ pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
{
m->md.pv_memattr = ma;
-
- /*
- * RISCVTODO: Implement the below (from the amd64 pmap)
- * If "m" is a normal page, update its direct mapping. This update
- * can be relied upon to perform any cache operations that are
- * required for data coherence.
- */
- if ((m->flags & PG_FICTITIOUS) == 0 &&
- PHYS_IN_DMAP(VM_PAGE_TO_PHYS(m)))
- panic("RISCVTODO: pmap_page_set_memattr");
}
/*