diff options
author | Leandro Lupori <luporl@FreeBSD.org> | 2021-03-25 16:30:56 +0000 |
---|---|---|
committer | Leandro Lupori <luporl@FreeBSD.org> | 2021-04-22 14:29:15 +0000 |
commit | f05174ed354797143200492b8fc9ea059e4fea10 (patch) | |
tree | fc7d4eb6453c13d22005a0a828dd6fefcfb47676 | |
parent | 0e0aa1eed8fa18ab31fb6a3e6fe135b41d2a9923 (diff) | |
download | src-f05174ed354.tar.gz src-f05174ed354.zip |
powerpc64: clear low-order bits of ARPN
PowerISA 2.07B says that the low-order p-12 bits of the real page number
contained in ARPN and LP fields of a PTE must be 0s and are ignored
by the hardware (Book III-S, 5.7.7.1), where 2^p is the actual page size
in bytes, but we were clearing only the LP field.
This worked on bare metal and QEMU with KVM, that ignore these bits,
but caused a kernel panic on QEMU with TCG, that expects them to be
cleared.
This fixes running FreeBSD with HPT superpages enabled on QEMU
with TCG.
Sponsored by: Eldorado Research Institute (eldorado.org.br)
(cherry picked from commit 3d0399c718b260da087d28825069f26d4f670065)
-rw-r--r-- | sys/powerpc/aim/mmu_oea64.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/sys/powerpc/aim/mmu_oea64.c b/sys/powerpc/aim/mmu_oea64.c index f311b61188e7..0e9b15661758 100644 --- a/sys/powerpc/aim/mmu_oea64.c +++ b/sys/powerpc/aim/mmu_oea64.c @@ -3719,7 +3719,7 @@ moea64_sp_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, pvo = pvos[i]; pvo->pvo_pte.prot = prot; - pvo->pvo_pte.pa = (pa & ~LPTE_LP_MASK) | LPTE_LP_4K_16M | + pvo->pvo_pte.pa = (pa & ~HPT_SP_MASK) | LPTE_LP_4K_16M | moea64_calc_wimg(pa, pmap_page_get_memattr(m)); if ((flags & PMAP_ENTER_WIRED) != 0) @@ -3876,7 +3876,7 @@ moea64_sp_promote(pmap_t pmap, vm_offset_t va, vm_page_t m) for (pvo = first, va_end = PVO_VADDR(pvo) + HPT_SP_SIZE; pvo != NULL && PVO_VADDR(pvo) < va_end; pvo = RB_NEXT(pvo_tree, &pmap->pmap_pvo, pvo)) { - pvo->pvo_pte.pa &= ~LPTE_LP_MASK; + pvo->pvo_pte.pa &= ADDR_POFF | ~HPT_SP_MASK; pvo->pvo_pte.pa |= LPTE_LP_4K_16M; pvo->pvo_vaddr |= PVO_LARGE; } |