qat: Rename to qat_c2xxx and remove support for modern chipsets

A replacement QAT driver will be imported, but this replacement does not
support Atom C2xxx hardware.  So, the existing driver will be kept
around to provide opencrypto offload support for those chipsets.

Reviewed by:	pauamma, emaste
Sponsored by:	The FreeBSD Foundation
Differential Revision:	https://reviews.freebsd.org/D35817

40 files changed, 30 insertions, 5228 deletions

diff --git a/share/man/man4/Makefile b/share/man/man4/Makefile
index 4a7f323e2c5c..192bab4155a2 100644
--- a/share/man/man4/Makefile
+++ b/share/man/man4/Makefile
@@ -452,7 +452,7 @@ MAN=	aac.4 \
 	pty.4 \
 	puc.4 \
 	pwmc.4 \
-	${_qat.4} \
+	${_qat_c2xxx.4} \
 	${_qlxge.4} \
 	${_qlxgb.4} \
 	${_qlxgbe.4} \
@@ -830,7 +830,7 @@ _nvme.4=	nvme.4
 _nvram.4=	nvram.4
 _padlock.4=	padlock.4
 _pchtherm.4=	pchtherm.4
-_qat.4=		qat.4
+_qat_c2xxx.4=	qat_c2xxx.4
 _rr232x.4=	rr232x.4
 _speaker.4=	speaker.4
 _spkr.4=	spkr.4
diff --git a/share/man/man4/qat.4 b/share/man/man4/qat_c2xxx.4
index bd021304dc4d..6f831fe94712 100644
--- a/share/man/man4/qat.4
+++ b/share/man/man4/qat_c2xxx.4
@@ -24,12 +24,12 @@
 .\"
 .\" $FreeBSD$
 .\"
-.Dd May 7, 2021
-.Dt QAT 4
+.Dd July 21, 2022
+.Dt QAT_C2XXX 4
 .Os
 .Sh NAME
-.Nm qat
-.Nd Intel QuickAssist Technology (QAT) driver
+.Nm qat_c2xxx
+.Nd Intel QuickAssist Technology (QAT) driver for Atom C2000 chipsets
 .Sh SYNOPSIS
 To compile this driver into the kernel,
 place the following lines in your
@@ -44,12 +44,8 @@ Alternatively, to load the driver as a
 module at boot time, place the following lines in
 .Xr loader.conf 5 :
 .Bd -literal -offset indent
-qat_load="YES"
+qat_c2xxx_load="YES"
 qat_c2xxxfw_load="YES"
-qat_c3xxxfw_load="YES"
-qat_c62xfw_load="YES"
-qat_d15xxfw_load="YES"
-qat_dh895xccfw_load="YES"
 .Ed
 .Sh DESCRIPTION
 The
@@ -57,20 +53,15 @@ The
 driver implements
 .Xr crypto 4
 support for some of the cryptographic acceleration functions of the Intel
-QuickAssist (QAT) device.
-The
-.Nm
-driver supports the QAT devices integrated with Atom C2000 and C3000 and Xeon
-C620 and D-1500 platforms, and the Intel QAT Adapter 8950.
-Other platforms and adapters not listed here may also be supported.
+QuickAssist (QAT) device found on Atom C2000 devices.
 QAT devices are enumerated through PCIe and are thus visible in
 .Xr pciconf 8
 output.
 .Pp
 The
 .Nm
-driver can accelerate AES in CBC, CTR, XTS (except for the C2000) and GCM modes,
-and can perform authenticated encryption combining the CBC, CTR and XTS modes
+driver can accelerate AES in CBC, CTR, and GCM modes,
+and can perform authenticated encryption combining the CBC, and CTR modes
 with SHA1-HMAC and SHA2-HMAC.
 The
 .Nm
@@ -84,6 +75,7 @@ requests that do not satisfy this constraint.
 .Xr crypto 4 ,
 .Xr ipsec 4 ,
 .Xr pci 4 ,
+.Xr qat 4 ,
 .Xr random 4 ,
 .Xr crypto 7 ,
 .Xr crypto 9
diff --git a/sys/amd64/conf/NOTES b/sys/amd64/conf/NOTES
index cf284ec8e5f0..ba6e99c0f8eb 100644
--- a/sys/amd64/conf/NOTES
+++ b/sys/amd64/conf/NOTES
@@ -467,8 +467,10 @@ device		vmd
 device		pmspcv
 
 #
-# Intel QuickAssist
-device		qat
+# Intel QuickAssist driver with OpenCrypto support
+#
+# Only for legacy Atom C2XXX chipsets.
+device		qat_c2xxx
 
 #
 # SafeNet crypto driver: can be moved to the MI NOTES as soon as
diff --git a/sys/conf/files.x86 b/sys/conf/files.x86
index 2866c5617593..a78570a423c9 100644
--- a/sys/conf/files.x86
+++ b/sys/conf/files.x86
@@ -288,15 +288,10 @@ dev/mana/mana_sysctl.c		optional	mana
 dev/mana/shm_channel.c		optional	mana
 dev/mana/hw_channel.c		optional	mana
 dev/mana/gdma_util.c		optional	mana
-dev/qat/qat.c			optional qat
-dev/qat/qat_ae.c		optional qat
-dev/qat/qat_c2xxx.c		optional qat
-dev/qat/qat_c3xxx.c		optional qat
-dev/qat/qat_c62x.c		optional qat
-dev/qat/qat_d15xx.c		optional qat
-dev/qat/qat_dh895xcc.c		optional qat
-dev/qat/qat_hw15.c		optional qat
-dev/qat/qat_hw17.c		optional qat
+dev/qat_c2xxx/qat.c		optional	qat_c2xxx
+dev/qat_c2xxx/qat_ae.c		optional	qat_c2xxx
+dev/qat_c2xxx/qat_c2xxx.c	optional	qat_c2xxx
+dev/qat_c2xxx/qat_hw15.c	optional	qat_c2xxx
 libkern/x86/crc32_sse42.c	standard
 #
 # x86 shared code between IA32 and AMD64 architectures
diff --git a/sys/contrib/dev/qat/qat_895xcc.bin b/sys/contrib/dev/qat/qat_895xcc.bin
deleted file mode 100644
index 5433dcc8408b..000000000000
--- a/sys/contrib/dev/qat/qat_895xcc.bin
+++ /dev/null
diff --git a/sys/contrib/dev/qat/qat_895xcc_mmp.bin b/sys/contrib/dev/qat/qat_895xcc_mmp.bin
deleted file mode 100644
index b0b3e7d8e3d2..000000000000
--- a/sys/contrib/dev/qat/qat_895xcc_mmp.bin
+++ /dev/null
diff --git a/sys/contrib/dev/qat/qat_c3xxx.bin b/sys/contrib/dev/qat/qat_c3xxx.bin
deleted file mode 100644
index ad8f81c5c331..000000000000
--- a/sys/contrib/dev/qat/qat_c3xxx.bin
+++ /dev/null
diff --git a/sys/contrib/dev/qat/qat_c3xxx_mmp.bin b/sys/contrib/dev/qat/qat_c3xxx_mmp.bin
deleted file mode 100644
index dfbf3ae5a19e..000000000000
--- a/sys/contrib/dev/qat/qat_c3xxx_mmp.bin
+++ /dev/null
diff --git a/sys/contrib/dev/qat/qat_c62x.bin b/sys/contrib/dev/qat/qat_c62x.bin
deleted file mode 100644
index fe7fa07b0d05..000000000000
--- a/sys/contrib/dev/qat/qat_c62x.bin
+++ /dev/null
diff --git a/sys/contrib/dev/qat/qat_c62x_mmp.bin b/sys/contrib/dev/qat/qat_c62x_mmp.bin
deleted file mode 100644
index 829861d4d498..000000000000
--- a/sys/contrib/dev/qat/qat_c62x_mmp.bin
+++ /dev/null
diff --git a/sys/contrib/dev/qat/qat_d15xx.bin b/sys/contrib/dev/qat/qat_d15xx.bin
deleted file mode 100644
index 26786a704cc5..000000000000
--- a/sys/contrib/dev/qat/qat_d15xx.bin
+++ /dev/null
diff --git a/sys/contrib/dev/qat/qat_d15xx_mmp.bin b/sys/contrib/dev/qat/qat_d15xx_mmp.bin
deleted file mode 100644
index dd84ed5aff92..000000000000
--- a/sys/contrib/dev/qat/qat_d15xx_mmp.bin
+++ /dev/null
diff --git a/sys/dev/qat/qat_c3xxx.c b/sys/dev/qat/qat_c3xxx.c
deleted file mode 100644
index 83d39da7d0af..000000000000
--- a/sys/dev/qat/qat_c3xxx.c
+++ /dev/null
@@ -1,298 +0,0 @@
-/* SPDX-License-Identifier: BSD-2-Clause-NetBSD AND BSD-3-Clause */
-/*	$NetBSD: qat_c3xxx.c,v 1.1 2019/11/20 09:37:46 hikaru Exp $	*/
-
-/*
- * Copyright (c) 2019 Internet Initiative Japan, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-/*
- *   Copyright(c) 2014 Intel Corporation.
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions
- *   are met:
- *
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in
- *       the documentation and/or other materials provided with the
- *       distribution.
- *     * Neither the name of Intel Corporation nor the names of its
- *       contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-#if 0
-__KERNEL_RCSID(0, "$NetBSD: qat_c3xxx.c,v 1.1 2019/11/20 09:37:46 hikaru Exp $");
-#endif
-
-#include <sys/param.h>
-#include <sys/bus.h>
-#include <sys/systm.h>
-
-#include <machine/bus.h>
-
-#include <dev/pci/pcireg.h>
-#include <dev/pci/pcivar.h>
-
-#include "qatreg.h"
-#include "qat_hw17reg.h"
-#include "qat_c3xxxreg.h"
-#include "qatvar.h"
-#include "qat_hw17var.h"
-
-static uint32_t
-qat_c3xxx_get_accel_mask(struct qat_softc *sc)
-{
-	uint32_t fusectl, strap;
-
-	fusectl = pci_read_config(sc->sc_dev, FUSECTL_REG, 4);
-	strap = pci_read_config(sc->sc_dev, SOFTSTRAP_REG_C3XXX, 4);
-
-	return (((~(fusectl | strap)) >> ACCEL_REG_OFFSET_C3XXX) &
-	    ACCEL_MASK_C3XXX);
-}
-
-static uint32_t
-qat_c3xxx_get_ae_mask(struct qat_softc *sc)
-{
-	uint32_t fusectl, me_strap, me_disable, ssms_disabled;
-
-	fusectl = pci_read_config(sc->sc_dev, FUSECTL_REG, 4);
-	me_strap = pci_read_config(sc->sc_dev, SOFTSTRAP_REG_C3XXX, 4);
-
-	/* If SSMs are disabled, then disable the corresponding MEs */
-	ssms_disabled = (~qat_c3xxx_get_accel_mask(sc)) & ACCEL_MASK_C3XXX;
-	me_disable = 0x3;
-	while (ssms_disabled) {
-		if (ssms_disabled & 1)
-			me_strap |= me_disable;
-		ssms_disabled >>= 1;
-		me_disable <<= 2;
-	}
-
-	return (~(fusectl | me_strap)) & AE_MASK_C3XXX;
-}
-
-static enum qat_sku
-qat_c3xxx_get_sku(struct qat_softc *sc)
-{
-	switch (sc->sc_ae_num) {
-	case MAX_AE_C3XXX:
-		return QAT_SKU_4;
-	}
-
-	return QAT_SKU_UNKNOWN;
-}
-
-static uint32_t
-qat_c3xxx_get_accel_cap(struct qat_softc *sc)
-{
-	uint32_t cap, legfuse, strap;
-
-	legfuse = pci_read_config(sc->sc_dev, LEGFUSE_REG, 4);
-	strap = pci_read_config(sc->sc_dev, SOFTSTRAP_REG_C3XXX, 4);
-
-	cap = QAT_ACCEL_CAP_CRYPTO_SYMMETRIC +
-		QAT_ACCEL_CAP_CRYPTO_ASYMMETRIC +
-		QAT_ACCEL_CAP_CIPHER +
-		QAT_ACCEL_CAP_AUTHENTICATION +
-		QAT_ACCEL_CAP_COMPRESSION +
-		QAT_ACCEL_CAP_ZUC +
-		QAT_ACCEL_CAP_SHA3;
-
-	if (legfuse & LEGFUSE_ACCEL_MASK_CIPHER_SLICE) {
-		cap &= ~QAT_ACCEL_CAP_CRYPTO_SYMMETRIC;
-		cap &= ~QAT_ACCEL_CAP_CIPHER;
-	}
-	if (legfuse & LEGFUSE_ACCEL_MASK_AUTH_SLICE)
-		cap &= ~QAT_ACCEL_CAP_AUTHENTICATION;
-	if (legfuse & LEGFUSE_ACCEL_MASK_PKE_SLICE)
-		cap &= ~QAT_ACCEL_CAP_CRYPTO_ASYMMETRIC;
-	if (legfuse & LEGFUSE_ACCEL_MASK_COMPRESS_SLICE)
-		cap &= ~QAT_ACCEL_CAP_COMPRESSION;
-	if (legfuse & LEGFUSE_ACCEL_MASK_EIA3_SLICE)
-		cap &= ~QAT_ACCEL_CAP_ZUC;
-
-	if ((strap | legfuse) & SOFTSTRAP_SS_POWERGATE_PKE_C3XXX)
-		cap &= ~QAT_ACCEL_CAP_CRYPTO_ASYMMETRIC;
-	if ((strap | legfuse) & SOFTSTRAP_SS_POWERGATE_CY_C3XXX)
-		cap &= ~QAT_ACCEL_CAP_COMPRESSION;
-
-	return cap;
-}
-
-static const char *
-qat_c3xxx_get_fw_uof_name(struct qat_softc *sc)
-{
-
-	return AE_FW_UOF_NAME_C3XXX;
-}
-
-static void
-qat_c3xxx_enable_intr(struct qat_softc *sc)
-{
-
-	/* Enable bundle and misc interrupts */
-	qat_misc_write_4(sc, SMIAPF0_C3XXX, SMIA0_MASK_C3XXX);
-	qat_misc_write_4(sc, SMIAPF1_C3XXX, SMIA1_MASK_C3XXX);
-}
-
-/* Worker thread to service arbiter mappings */
-static uint32_t thrd_to_arb_map[] = {
-	0x12222AAA, 0x11222AAA, 0x12222AAA,
-	0x11222AAA, 0x12222AAA, 0x11222AAA
-};
-
-static void
-qat_c3xxx_get_arb_mapping(struct qat_softc *sc, const uint32_t **arb_map_config)
-{
-	int i;
-
-	for (i = 1; i < MAX_AE_C3XXX; i++) {
-		if ((~sc->sc_ae_mask) & (1 << i))
-			thrd_to_arb_map[i] = 0;
-	}
-	*arb_map_config = thrd_to_arb_map;
-}
-
-static void
-qat_c3xxx_enable_error_interrupts(struct qat_softc *sc)
-{
-	qat_misc_write_4(sc, ERRMSK0, ERRMSK0_CERR_C3XXX); /* ME0-ME3 */
-	qat_misc_write_4(sc, ERRMSK1, ERRMSK1_CERR_C3XXX); /* ME4-ME5 */
-	qat_misc_write_4(sc, ERRMSK5, ERRMSK5_CERR_C3XXX); /* SSM2 */
-
-	/* Reset everything except VFtoPF1_16. */
-	qat_misc_read_write_and_4(sc, ERRMSK3, VF2PF1_16_C3XXX);
-
-	/* RI CPP bus interface error detection and reporting. */
-	qat_misc_write_4(sc, RICPPINTCTL_C3XXX, RICPP_EN_C3XXX);
-
-	/* TI CPP bus interface error detection and reporting. */
-	qat_misc_write_4(sc, TICPPINTCTL_C3XXX, TICPP_EN_C3XXX);
-
-	/* Enable CFC Error interrupts and logging. */
-	qat_misc_write_4(sc, CPP_CFC_ERR_CTRL_C3XXX, CPP_CFC_UE_C3XXX);
-}
-
-static void
-qat_c3xxx_disable_error_interrupts(struct qat_softc *sc)
-{
-	/* ME0-ME3 */
-	qat_misc_write_4(sc, ERRMSK0, ERRMSK0_UERR_C3XXX | ERRMSK0_CERR_C3XXX);
-	/* ME4-ME5 */
-	qat_misc_write_4(sc, ERRMSK1, ERRMSK1_UERR_C3XXX | ERRMSK1_CERR_C3XXX);
-	/* CPP Push Pull, RI, TI, SSM0-SSM1, CFC */
-	qat_misc_write_4(sc, ERRMSK3, ERRMSK3_UERR_C3XXX);
-	/* SSM2 */
-	qat_misc_write_4(sc, ERRMSK5, ERRMSK5_UERR_C3XXX);
-}
-
-static void
-qat_c3xxx_enable_error_correction(struct qat_softc *sc)
-{
-	u_int i, mask;
-
-	/* Enable Accel Engine error detection & correction */
-	for (i = 0, mask = sc->sc_ae_mask; mask; i++, mask >>= 1) {
-		if (!(mask & 1))
-			continue;
-		qat_misc_read_write_or_4(sc, AE_CTX_ENABLES_C3XXX(i),
-		    ENABLE_AE_ECC_ERR_C3XXX);
-		qat_misc_read_write_or_4(sc, AE_MISC_CONTROL_C3XXX(i),
-		    ENABLE_AE_ECC_PARITY_CORR_C3XXX);
-	}
-
-	/* Enable shared memory error detection & correction */
-	for (i = 0, mask = sc->sc_accel_mask; mask; i++, mask >>= 1) {
-		if (!(mask & 1))
-			continue;
-
-		qat_misc_read_write_or_4(sc, UERRSSMSH(i), ERRSSMSH_EN_C3XXX);
-		qat_misc_read_write_or_4(sc, CERRSSMSH(i), ERRSSMSH_EN_C3XXX);
-		qat_misc_read_write_or_4(sc, PPERR(i), PPERR_EN_C3XXX);
-	}
-
-	qat_c3xxx_enable_error_interrupts(sc);
-}
-
-const struct qat_hw qat_hw_c3xxx = {
-	.qhw_sram_bar_id = BAR_SRAM_ID_C3XXX,
-	.qhw_misc_bar_id = BAR_PMISC_ID_C3XXX,
-	.qhw_etr_bar_id = BAR_ETR_ID_C3XXX,
-	.qhw_cap_global_offset = CAP_GLOBAL_OFFSET_C3XXX,
-	.qhw_ae_offset = AE_OFFSET_C3XXX,
-	.qhw_ae_local_offset = AE_LOCAL_OFFSET_C3XXX,
-	.qhw_etr_bundle_size = ETR_BUNDLE_SIZE_C3XXX,
-	.qhw_num_banks = ETR_MAX_BANKS_C3XXX,
-	.qhw_num_rings_per_bank = ETR_MAX_RINGS_PER_BANK,
-	.qhw_num_accel = MAX_ACCEL_C3XXX,
-	.qhw_num_engines = MAX_AE_C3XXX,
-	.qhw_tx_rx_gap = ETR_TX_RX_GAP_C3XXX,
-	.qhw_tx_rings_mask = ETR_TX_RINGS_MASK_C3XXX,
-	.qhw_clock_per_sec = CLOCK_PER_SEC_C3XXX,
-	.qhw_fw_auth = true,
-	.qhw_fw_req_size = FW_REQ_DEFAULT_SZ_HW17,
-	.qhw_fw_resp_size = FW_RESP_DEFAULT_SZ_HW17,
-	.qhw_ring_asym_tx = 0,
-	.qhw_ring_asym_rx = 8,
-	.qhw_ring_sym_tx = 2,
-	.qhw_ring_sym_rx = 10,
-	.qhw_mof_fwname = AE_FW_MOF_NAME_C3XXX,
-	.qhw_mmp_fwname = AE_FW_MMP_NAME_C3XXX,
-	.qhw_prod_type = AE_FW_PROD_TYPE_C3XXX,
-	.qhw_get_accel_mask = qat_c3xxx_get_accel_mask,
-	.qhw_get_ae_mask = qat_c3xxx_get_ae_mask,
-	.qhw_get_sku = qat_c3xxx_get_sku,
-	.qhw_get_accel_cap = qat_c3xxx_get_accel_cap,
-	.qhw_get_fw_uof_name = qat_c3xxx_get_fw_uof_name,
-	.qhw_enable_intr = qat_c3xxx_enable_intr,
-	.qhw_init_admin_comms = qat_adm_mailbox_init,
-	.qhw_send_admin_init = qat_adm_mailbox_send_init,
-	.qhw_init_arb = qat_arb_init,
-	.qhw_get_arb_mapping = qat_c3xxx_get_arb_mapping,
-	.qhw_enable_error_correction = qat_c3xxx_enable_error_correction,
-	.qhw_disable_error_interrupts = qat_c3xxx_disable_error_interrupts,
-	.qhw_set_ssm_wdtimer = qat_set_ssm_wdtimer,
-	.qhw_check_slice_hang = qat_check_slice_hang,
-	.qhw_crypto_setup_desc = qat_hw17_crypto_setup_desc,
-	.qhw_crypto_setup_req_params = qat_hw17_crypto_setup_req_params,
-	.qhw_crypto_opaque_offset = offsetof(struct fw_la_resp, opaque_data),
-};
diff --git a/sys/dev/qat/qat_c3xxxreg.h b/sys/dev/qat/qat_c3xxxreg.h
deleted file mode 100644
index a5cb957e47fe..000000000000
--- a/sys/dev/qat/qat_c3xxxreg.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/* SPDX-License-Identifier: BSD-2-Clause-NetBSD AND BSD-3-Clause */
-/*	$NetBSD: qat_c3xxxreg.h,v 1.1 2019/11/20 09:37:46 hikaru Exp $	*/
-
-/*
- * Copyright (c) 2019 Internet Initiative Japan, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-/*
- *   Copyright(c) 2014 Intel Corporation.
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions
- *   are met:
- *
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in
- *       the documentation and/or other materials provided with the
- *       distribution.
- *     * Neither the name of Intel Corporation nor the names of its
- *       contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/* $FreeBSD$ */
-
-#ifndef _DEV_PCI_QAT_C3XXXREG_H_
-#define _DEV_PCI_QAT_C3XXXREG_H_
-
-/* Max number of accelerators and engines */
-#define MAX_ACCEL_C3XXX			3
-#define MAX_AE_C3XXX			6
-
-/* PCIe BAR index */
-#define BAR_SRAM_ID_C3XXX		NO_PCI_REG
-#define BAR_PMISC_ID_C3XXX		0
-#define BAR_ETR_ID_C3XXX		1
-
-/* BAR PMISC sub-regions */
-#define AE_OFFSET_C3XXX			0x20000
-#define AE_LOCAL_OFFSET_C3XXX		0x20800
-#define CAP_GLOBAL_OFFSET_C3XXX		0x30000
-
-#define SOFTSTRAP_REG_C3XXX			0x2EC
-#define SOFTSTRAP_SS_POWERGATE_CY_C3XXX		__BIT(23)
-#define SOFTSTRAP_SS_POWERGATE_PKE_C3XXX	__BIT(24)
-
-#define ACCEL_REG_OFFSET_C3XXX		16
-#define ACCEL_MASK_C3XXX		0x7
-#define AE_MASK_C3XXX			0x3F
-
-#define SMIAPF0_C3XXX			0x3A028
-#define SMIAPF1_C3XXX			0x3A030
-#define SMIA0_MASK_C3XXX		0xFFFF
-#define SMIA1_MASK_C3XXX		0x1
-
-/* Error detection and correction */
-#define AE_CTX_ENABLES_C3XXX(i)		((i) * 0x1000 + 0x20818)
-#define AE_MISC_CONTROL_C3XXX(i)	((i) * 0x1000 + 0x20960)
-#define ENABLE_AE_ECC_ERR_C3XXX		__BIT(28)
-#define ENABLE_AE_ECC_PARITY_CORR_C3XXX	(__BIT(24) | __BIT(12))
-#define ERRSSMSH_EN_C3XXX		__BIT(3)
-/* BIT(2) enables the logging of push/pull data errors. */
-#define PPERR_EN_C3XXX			(__BIT(2))
-
-/* Mask for VF2PF interrupts */
-#define VF2PF1_16_C3XXX			(0xFFFF << 9)
-#define ERRSOU3_VF2PF_C3XXX(errsou3)	(((errsou3) & 0x01FFFE00) >> 9)
-#define ERRMSK3_VF2PF_C3XXX(vf_mask)	(((vf_mask) & 0xFFFF) << 9)
-
-/* Masks for correctable error interrupts. */
-#define ERRMSK0_CERR_C3XXX		(__BIT(24) | __BIT(16) | __BIT(8) | __BIT(0))
-#define ERRMSK1_CERR_C3XXX		(__BIT(8) | __BIT(0))
-#define ERRMSK5_CERR_C3XXX		(0)
-
-/* Masks for uncorrectable error interrupts. */
-#define ERRMSK0_UERR_C3XXX		(__BIT(25) | __BIT(17) | __BIT(9) | __BIT(1))
-#define ERRMSK1_UERR_C3XXX		(__BIT(9) | __BIT(1))
-#define ERRMSK3_UERR_C3XXX		(__BIT(6) | __BIT(5) | __BIT(4) | __BIT(3) | \
-					 __BIT(2) | __BIT(0))
-#define ERRMSK5_UERR_C3XXX		(__BIT(16))
-
-/* RI CPP control */
-#define RICPPINTCTL_C3XXX		(0x3A000 + 0x110)
-/*
- * BIT(2) enables error detection and reporting on the RI Parity Error.
- * BIT(1) enables error detection and reporting on the RI CPP Pull interface.
- * BIT(0) enables error detection and reporting on the RI CPP Push interface.
- */
-#define RICPP_EN_C3XXX			(__BIT(2) | __BIT(1) | __BIT(0))
-
-/* TI CPP control */
-#define TICPPINTCTL_C3XXX		(0x3A400 + 0x138)
-/*
- * BIT(3) enables error detection and reporting on the ETR Parity Error.
- * BIT(2) enables error detection and reporting on the TI Parity Error.
- * BIT(1) enables error detection and reporting on the TI CPP Pull interface.
- * BIT(0) enables error detection and reporting on the TI CPP Push interface.
- */
-#define TICPP_EN_C3XXX		\
-	(__BIT(3) | __BIT(2) | __BIT(1) | __BIT(0))
-
-/* CFC Uncorrectable Errors */
-#define CPP_CFC_ERR_CTRL_C3XXX	(0x30000 + 0xC00)
-/*
- * BIT(1) enables interrupt.
- * BIT(0) enables detecting and logging of push/pull data errors.
- */
-#define CPP_CFC_UE_C3XXX		(__BIT(1) | __BIT(0))
-
-#define SLICEPWRDOWN_C3XXX(i)	((i) * 0x4000 + 0x2C)
-/* Enabling PKE4-PKE0. */
-#define MMP_PWR_UP_MSK_C3XXX		\
-	(__BIT(20) | __BIT(19) | __BIT(18) | __BIT(17) | __BIT(16))
-
-/* CPM Uncorrectable Errors */
-#define INTMASKSSM_C3XXX(i)		((i) * 0x4000 + 0x0)
-/* Disabling interrupts for correctable errors. */
-#define INTMASKSSM_UERR_C3XXX	\
-	(__BIT(11) | __BIT(9) | __BIT(7) | __BIT(5) | __BIT(3) | __BIT(1))
-
-/* MMP */
-/* BIT(3) enables correction. */
-#define CERRSSMMMP_EN_C3XXX		(__BIT(3))
-
-/* BIT(3) enables logging. */
-#define UERRSSMMMP_EN_C3XXX		(__BIT(3))
-
-/* ETR */
-#define ETR_MAX_BANKS_C3XXX		16
-#define ETR_TX_RX_GAP_C3XXX		8
-#define ETR_TX_RINGS_MASK_C3XXX		0xFF
-#define ETR_BUNDLE_SIZE_C3XXX		0x1000
-
-/* AE firmware */
-#define AE_FW_PROD_TYPE_C3XXX		0x02000000
-#define AE_FW_MOF_NAME_C3XXX	"qat_c3xxxfw"
-#define AE_FW_MMP_NAME_C3XXX	"qat_c3xxx_mmp"
-#define AE_FW_UOF_NAME_C3XXX	"icp_qat_ae.suof"
-
-/* Clock frequency */
-#define CLOCK_PER_SEC_C3XXX		(685 * 1000000 / 16)
-
-#endif
diff --git a/sys/dev/qat/qat_c62x.c b/sys/dev/qat/qat_c62x.c
deleted file mode 100644
index 826c68db9854..000000000000
--- a/sys/dev/qat/qat_c62x.c
+++ /dev/null
@@ -1,314 +0,0 @@
-/* SPDX-License-Identifier: BSD-2-Clause-NetBSD AND BSD-3-Clause */
-/*	$NetBSD: qat_c62x.c,v 1.1 2019/11/20 09:37:46 hikaru Exp $	*/
-
-/*
- * Copyright (c) 2019 Internet Initiative Japan, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-/*
- *   Copyright(c) 2014 Intel Corporation.
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions
- *   are met:
- *
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in
- *       the documentation and/or other materials provided with the
- *       distribution.
- *     * Neither the name of Intel Corporation nor the names of its
- *       contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-#if 0
-__KERNEL_RCSID(0, "$NetBSD: qat_c62x.c,v 1.1 2019/11/20 09:37:46 hikaru Exp $");
-#endif
-
-#include <sys/param.h>
-#include <sys/bus.h>
-#include <sys/systm.h>
-
-#include <machine/bus.h>
-
-#include <dev/pci/pcireg.h>
-#include <dev/pci/pcivar.h>
-
-#include "qatreg.h"
-#include "qat_hw17reg.h"
-#include "qat_c62xreg.h"
-#include "qatvar.h"
-#include "qat_hw17var.h"
-
-static uint32_t
-qat_c62x_get_accel_mask(struct qat_softc *sc)
-{
-	uint32_t fusectl, strap;
-
-	fusectl = pci_read_config(sc->sc_dev, FUSECTL_REG, 4);
-	strap = pci_read_config(sc->sc_dev, SOFTSTRAP_REG_C62X, 4);
-
-	return (((~(fusectl | strap)) >> ACCEL_REG_OFFSET_C62X) &
-	    ACCEL_MASK_C62X);
-}
-
-static uint32_t
-qat_c62x_get_ae_mask(struct qat_softc *sc)
-{
-	uint32_t fusectl, me_strap, me_disable, ssms_disabled;
-
-	fusectl = pci_read_config(sc->sc_dev, FUSECTL_REG, 4);
-	me_strap = pci_read_config(sc->sc_dev, SOFTSTRAP_REG_C62X, 4);
-
-	/* If SSMs are disabled, then disable the corresponding MEs */
-	ssms_disabled = (~qat_c62x_get_accel_mask(sc)) & ACCEL_MASK_C62X;
-	me_disable = 0x3;
-	while (ssms_disabled) {
-		if (ssms_disabled & 1)
-			me_strap |= me_disable;
-		ssms_disabled >>= 1;
-		me_disable <<= 2;
-	}
-
-	return (~(fusectl | me_strap)) & AE_MASK_C62X;
-}
-
-static enum qat_sku
-qat_c62x_get_sku(struct qat_softc *sc)
-{
-	switch (sc->sc_ae_num) {
-	case 8:
-		return QAT_SKU_2;
-	case MAX_AE_C62X:
-		return QAT_SKU_4;
-	}
-
-	return QAT_SKU_UNKNOWN;
-}
-
-static uint32_t
-qat_c62x_get_accel_cap(struct qat_softc *sc)
-{
-	uint32_t cap, legfuse, strap;
-
-	legfuse = pci_read_config(sc->sc_dev, LEGFUSE_REG, 4);
-	strap = pci_read_config(sc->sc_dev, SOFTSTRAP_REG_C62X, 4);
-
-	cap = QAT_ACCEL_CAP_CRYPTO_SYMMETRIC +
-		QAT_ACCEL_CAP_CRYPTO_ASYMMETRIC +
-		QAT_ACCEL_CAP_CIPHER +
-		QAT_ACCEL_CAP_AUTHENTICATION +
-		QAT_ACCEL_CAP_COMPRESSION +
-		QAT_ACCEL_CAP_ZUC +
-		QAT_ACCEL_CAP_SHA3;
-
-	if (legfuse & LEGFUSE_ACCEL_MASK_CIPHER_SLICE) {
-		cap &= ~QAT_ACCEL_CAP_CRYPTO_SYMMETRIC;
-		cap &= ~QAT_ACCEL_CAP_CIPHER;
-	}
-	if (legfuse & LEGFUSE_ACCEL_MASK_AUTH_SLICE)
-		cap &= ~QAT_ACCEL_CAP_AUTHENTICATION;
-	if (legfuse & LEGFUSE_ACCEL_MASK_PKE_SLICE)
-		cap &= ~QAT_ACCEL_CAP_CRYPTO_ASYMMETRIC;
-	if (legfuse & LEGFUSE_ACCEL_MASK_COMPRESS_SLICE)
-		cap &= ~QAT_ACCEL_CAP_COMPRESSION;
-	if (legfuse & LEGFUSE_ACCEL_MASK_EIA3_SLICE)
-		cap &= ~QAT_ACCEL_CAP_ZUC;
-
-	if ((strap | legfuse) & SOFTSTRAP_SS_POWERGATE_PKE_C62X)
-		cap &= ~QAT_ACCEL_CAP_CRYPTO_ASYMMETRIC;
-	if ((strap | legfuse) & SOFTSTRAP_SS_POWERGATE_CY_C62X)
-		cap &= ~QAT_ACCEL_CAP_COMPRESSION;
-
-	return cap;
-}
-
-static const char *
-qat_c62x_get_fw_uof_name(struct qat_softc *sc)
-{
-
-	return AE_FW_UOF_NAME_C62X;
-}
-
-static void
-qat_c62x_enable_intr(struct qat_softc *sc)
-{
-
-	/* Enable bundle and misc interrupts */
-	qat_misc_write_4(sc, SMIAPF0_C62X, SMIA0_MASK_C62X);
-	qat_misc_write_4(sc, SMIAPF1_C62X, SMIA1_MASK_C62X);
-}
-
-/* Worker thread to service arbiter mappings */
-static uint32_t thrd_to_arb_map[] = {
-	0x12222AAA, 0x11222AAA, 0x12222AAA, 0x11222AAA, 0x12222AAA,
-	0x11222AAA, 0x12222AAA, 0x11222AAA, 0x12222AAA, 0x11222AAA
-};
-
-static void
-qat_c62x_get_arb_mapping(struct qat_softc *sc, const uint32_t **arb_map_config)
-{
-	int i;
-
-	for (i = 1; i < MAX_AE_C62X; i++) {
-		if ((~sc->sc_ae_mask) & (1 << i))
-			thrd_to_arb_map[i] = 0;
-	}
-	*arb_map_config = thrd_to_arb_map;
-}
-
-static void
-qat_c62x_enable_error_interrupts(struct qat_softc *sc)
-{
-	qat_misc_write_4(sc, ERRMSK0, ERRMSK0_CERR_C62X); /* ME0-ME3 */
-	qat_misc_write_4(sc, ERRMSK1, ERRMSK1_CERR_C62X); /* ME4-ME7 */
-	qat_misc_write_4(sc, ERRMSK4, ERRMSK4_CERR_C62X); /* ME8-ME9 */
-	qat_misc_write_4(sc, ERRMSK5, ERRMSK5_CERR_C62X); /* SSM2-SSM4 */
-
-	/* Reset everything except VFtoPF1_16. */
-	qat_misc_read_write_and_4(sc, ERRMSK3, VF2PF1_16_C62X);
-	/* Disable Secure RAM correctable error interrupt */
-	qat_misc_read_write_or_4(sc, ERRMSK3, ERRMSK3_CERR_C62X);
-
-	/* RI CPP bus interface error detection and reporting. */
-	qat_misc_write_4(sc, RICPPINTCTL_C62X, RICPP_EN_C62X);
-
-	/* TI CPP bus interface error detection and reporting. */
-	qat_misc_write_4(sc, TICPPINTCTL_C62X, TICPP_EN_C62X);
-
-	/* Enable CFC Error interrupts and logging. */
-	qat_misc_write_4(sc, CPP_CFC_ERR_CTRL_C62X, CPP_CFC_UE_C62X);
-
-	/* Enable SecureRAM to fix and log Correctable errors */
-	qat_misc_write_4(sc, SECRAMCERR_C62X, SECRAM_CERR_C62X);
-
-	/* Enable SecureRAM Uncorrectable error interrupts and logging */
-	qat_misc_write_4(sc, SECRAMUERR, SECRAM_UERR_C62X);
-
-	/* Enable Push/Pull Misc Uncorrectable error interrupts and logging */
-	qat_misc_write_4(sc, CPPMEMTGTERR, TGT_UERR_C62X);
-}
-
-static void
-qat_c62x_disable_error_interrupts(struct qat_softc *sc)
-{
-	/* ME0-ME3 */
-	qat_misc_write_4(sc, ERRMSK0, ERRMSK0_UERR_C62X | ERRMSK0_CERR_C62X);
-	/* ME4-ME7 */
-	qat_misc_write_4(sc, ERRMSK1, ERRMSK1_UERR_C62X | ERRMSK1_CERR_C62X);
-	/* Secure RAM, CPP Push Pull, RI, TI, SSM0-SSM1, CFC */
-	qat_misc_write_4(sc, ERRMSK3, ERRMSK3_UERR_C62X | ERRMSK3_CERR_C62X);
-	/* ME8-ME9 */
-	qat_misc_write_4(sc, ERRMSK4, ERRMSK4_UERR_C62X | ERRMSK4_CERR_C62X);
-	/* SSM2-SSM4 */
-	qat_misc_write_4(sc, ERRMSK5, ERRMSK5_UERR_C62X | ERRMSK5_CERR_C62X);
-}
-
-static void
-qat_c62x_enable_error_correction(struct qat_softc *sc)
-{
-	u_int i, mask;
-
-	/* Enable Accel Engine error detection & correction */
-	for (i = 0, mask = sc->sc_ae_mask; mask; i++, mask >>= 1) {
-		if (!(mask & 1))
-			continue;
-		qat_misc_read_write_or_4(sc, AE_CTX_ENABLES_C62X(i),
-		    ENABLE_AE_ECC_ERR_C62X);
-		qat_misc_read_write_or_4(sc, AE_MISC_CONTROL_C62X(i),
-		    ENABLE_AE_ECC_PARITY_CORR_C62X);
-	}
-
-	/* Enable shared memory error detection & correction */
-	for (i = 0, mask = sc->sc_accel_mask; mask; i++, mask >>= 1) {
-		if (!(mask & 1))
-			continue;
-
-		qat_misc_read_write_or_4(sc, UERRSSMSH(i), ERRSSMSH_EN_C62X);
-		qat_misc_read_write_or_4(sc, CERRSSMSH(i), ERRSSMSH_EN_C62X);
-		qat_misc_read_write_or_4(sc, PPERR(i), PPERR_EN_C62X);
-	}
-
-	qat_c62x_enable_error_interrupts(sc);
-}
-
-const struct qat_hw qat_hw_c62x = {
-	.qhw_sram_bar_id = BAR_SRAM_ID_C62X,
-	.qhw_misc_bar_id = BAR_PMISC_ID_C62X,
-	.qhw_etr_bar_id = BAR_ETR_ID_C62X,
-	.qhw_cap_global_offset = CAP_GLOBAL_OFFSET_C62X,
-	.qhw_ae_offset = AE_OFFSET_C62X,
-	.qhw_ae_local_offset = AE_LOCAL_OFFSET_C62X,
-	.qhw_etr_bundle_size = ETR_BUNDLE_SIZE_C62X,
-	.qhw_num_banks = ETR_MAX_BANKS_C62X,
-	.qhw_num_rings_per_bank = ETR_MAX_RINGS_PER_BANK,
-	.qhw_num_accel = MAX_ACCEL_C62X,
-	.qhw_num_engines = MAX_AE_C62X,
-	.qhw_tx_rx_gap = ETR_TX_RX_GAP_C62X,
-	.qhw_tx_rings_mask = ETR_TX_RINGS_MASK_C62X,
-	.qhw_clock_per_sec = CLOCK_PER_SEC_C62X,
-	.qhw_fw_auth = true,
-	.qhw_fw_req_size = FW_REQ_DEFAULT_SZ_HW17,
-	.qhw_fw_resp_size = FW_RESP_DEFAULT_SZ_HW17,
-	.qhw_ring_asym_tx = 0,
-	.qhw_ring_asym_rx = 8,
-	.qhw_ring_sym_tx = 2,
-	.qhw_ring_sym_rx = 10,
-	.qhw_mof_fwname = AE_FW_MOF_NAME_C62X,
-	.qhw_mmp_fwname = AE_FW_MMP_NAME_C62X,
-	.qhw_prod_type = AE_FW_PROD_TYPE_C62X,
-	.qhw_get_accel_mask = qat_c62x_get_accel_mask,
-	.qhw_get_ae_mask = qat_c62x_get_ae_mask,
-	.qhw_get_sku = qat_c62x_get_sku,
-	.qhw_get_accel_cap = qat_c62x_get_accel_cap,
-	.qhw_get_fw_uof_name = qat_c62x_get_fw_uof_name,
-	.qhw_enable_intr = qat_c62x_enable_intr,
-	.qhw_init_admin_comms = qat_adm_mailbox_init,
-	.qhw_send_admin_init = qat_adm_mailbox_send_init,
-	.qhw_init_arb = qat_arb_init,
-	.qhw_get_arb_mapping = qat_c62x_get_arb_mapping,
-	.qhw_enable_error_correction = qat_c62x_enable_error_correction,
-	.qhw_disable_error_interrupts = qat_c62x_disable_error_interrupts,
-	.qhw_set_ssm_wdtimer = qat_set_ssm_wdtimer,
-	.qhw_check_slice_hang = qat_check_slice_hang,
-	.qhw_crypto_setup_desc = qat_hw17_crypto_setup_desc,
-	.qhw_crypto_setup_req_params = qat_hw17_crypto_setup_req_params,
-	.qhw_crypto_opaque_offset = offsetof(struct fw_la_resp, opaque_data),
-};
diff --git a/sys/dev/qat/qat_c62xreg.h b/sys/dev/qat/qat_c62xreg.h
deleted file mode 100644
index 7e85d4a663c1..000000000000
--- a/sys/dev/qat/qat_c62xreg.h
+++ /dev/null
@@ -1,201 +0,0 @@
-/* SPDX-License-Identifier: BSD-2-Clause-NetBSD AND BSD-3-Clause */
-/*	$NetBSD: qat_c62xreg.h,v 1.1 2019/11/20 09:37:46 hikaru Exp $	*/
-
-/*
- * Copyright (c) 2019 Internet Initiative Japan, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-/*
- *   Copyright(c) 2014 Intel Corporation.
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions
- *   are met:
- *
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in
- *       the documentation and/or other materials provided with the
- *       distribution.
- *     * Neither the name of Intel Corporation nor the names of its
- *       contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/* $FreeBSD$ */
-
-#ifndef _DEV_PCI_QAT_C62XREG_H_
-#define _DEV_PCI_QAT_C62XREG_H_
-
-/* Max number of accelerators and engines */
-#define MAX_ACCEL_C62X			5
-#define MAX_AE_C62X			10
-
-/* PCIe BAR index */
-#define BAR_SRAM_ID_C62X		0
-#define BAR_PMISC_ID_C62X		1
-#define BAR_ETR_ID_C62X			2
-
-/* BAR PMISC sub-regions */
-#define AE_OFFSET_C62X			0x20000
-#define AE_LOCAL_OFFSET_C62X		0x20800
-#define CAP_GLOBAL_OFFSET_C62X		0x30000
-
-#define SOFTSTRAP_REG_C62X			0x2EC
-#define SOFTSTRAP_SS_POWERGATE_CY_C62X		__BIT(23)
-#define SOFTSTRAP_SS_POWERGATE_PKE_C62X		__BIT(24)
-
-#define ACCEL_REG_OFFSET_C62X		16
-#define ACCEL_MASK_C62X			0x1F
-#define AE_MASK_C62X			0x3FF
-
-#define SMIAPF0_C62X			0x3A028
-#define SMIAPF1_C62X			0x3A030
-#define SMIA0_MASK_C62X			0xFFFF
-#define SMIA1_MASK_C62X			0x1
-
-/* Error detection and correction */
-#define AE_CTX_ENABLES_C62X(i)		((i) * 0x1000 + 0x20818)
-#define AE_MISC_CONTROL_C62X(i)		((i) * 0x1000 + 0x20960)
-#define ENABLE_AE_ECC_ERR_C62X		__BIT(28)
-#define ENABLE_AE_ECC_PARITY_CORR_C62X	(__BIT(24) | __BIT(12))
-#define ERRSSMSH_EN_C62X		__BIT(3)
-/* BIT(2) enables the logging of push/pull data errors. */
-#define PPERR_EN_C62X			(__BIT(2))
-
-/* Mask for VF2PF interrupts */
-#define VF2PF1_16_C62X			(0xFFFF << 9)
-#define ERRSOU3_VF2PF_C62X(errsou3)	(((errsou3) & 0x01FFFE00) >> 9)
-#define ERRMSK3_VF2PF_C62X(vf_mask)	(((vf_mask) & 0xFFFF) << 9)
-
-/* Masks for correctable error interrupts. */
-#define ERRMSK0_CERR_C62X	(__BIT(24) | __BIT(16) | __BIT(8) | __BIT(0))
-#define ERRMSK1_CERR_C62X	(__BIT(24) | __BIT(16) | __BIT(8) | __BIT(0))
-#define ERRMSK3_CERR_C62X	(__BIT(7))
-#define ERRMSK4_CERR_C62X	(__BIT(8) | __BIT(0))
-#define ERRMSK5_CERR_C62X	(0)
-
-/* Masks for uncorrectable error interrupts. */
-#define ERRMSK0_UERR_C62X	(__BIT(25) | __BIT(17) | __BIT(9) | __BIT(1))
-#define ERRMSK1_UERR_C62X	(__BIT(25) | __BIT(17) | __BIT(9) | __BIT(1))
-#define ERRMSK3_UERR_C62X	(__BIT(8) | __BIT(6) | __BIT(5) | __BIT(4) | \
-				 __BIT(3) | __BIT(2) | __BIT(0))
-#define ERRMSK4_UERR_C62X	(__BIT(9) | __BIT(1))
-#define ERRMSK5_UERR_C62X	(__BIT(18) | __BIT(17) | __BIT(16))
-
-/* RI CPP control */
-#define RICPPINTCTL_C62X		(0x3A000 + 0x110)
-/*
- * BIT(2) enables error detection and reporting on the RI Parity Error.
- * BIT(1) enables error detection and reporting on the RI CPP Pull interface.
- * BIT(0) enables error detection and reporting on the RI CPP Push interface.
- */
-#define RICPP_EN_C62X			(__BIT(2) | __BIT(1) | __BIT(0))
-
-/* TI CPP control */
-#define TICPPINTCTL_C62X		(0x3A400 + 0x138)
-/*
- * BIT(3) enables error detection and reporting on the ETR Parity Error.
- * BIT(2) enables error detection and reporting on the TI Parity Error.
- * BIT(1) enables error detection and reporting on the TI CPP Pull interface.
- * BIT(0) enables error detection and reporting on the TI CPP Push interface.
- */
-#define TICPP_EN_C62X		\
-	(__BIT(4) | __BIT(3) | __BIT(2) | __BIT(1) | __BIT(0))
-
-/* CFC Uncorrectable Errors */
-#define CPP_CFC_ERR_CTRL_C62X	(0x30000 + 0xC00)
-/*
- * BIT(1) enables interrupt.
- * BIT(0) enables detecting and logging of push/pull data errors.
- */
-#define CPP_CFC_UE_C62X		(__BIT(1) | __BIT(0))
-
-/* Correctable SecureRAM Error Reg */
-#define SECRAMCERR_C62X			(0x3AC00 + 0x00)
-/* BIT(3) enables fixing and logging of correctable errors. */
-#define SECRAM_CERR_C62X		(__BIT(3))
-
-/* Uncorrectable SecureRAM Error Reg */
-/*
- * BIT(17) enables interrupt.
- * BIT(3) enables detecting and logging of uncorrectable errors.
- */
-#define SECRAM_UERR_C62X		(__BIT(17) | __BIT(3))
-
-/* Miscellaneous Memory Target Errors Register */
-/*
- * BIT(3) enables detecting and logging push/pull data errors.
- * BIT(2) enables interrupt.
- */
-#define TGT_UERR_C62X			(__BIT(3) | __BIT(2))
-
-
-#define SLICEPWRDOWN_C62X(i)	((i) * 0x4000 + 0x2C)
-/* Enabling PKE4-PKE0. */
-#define MMP_PWR_UP_MSK_C62X		\
-	(__BIT(20) | __BIT(19) | __BIT(18) | __BIT(17) | __BIT(16))
-
-/* CPM Uncorrectable Errors */
-#define INTMASKSSM_C62X(i)		((i) * 0x4000 + 0x0)
-/* Disabling interrupts for correctable errors. */
-#define INTMASKSSM_UERR_C62X	\
-	(__BIT(11) | __BIT(9) | __BIT(7) | __BIT(5) | __BIT(3) | __BIT(1))
-
-/* MMP */
-/* BIT(3) enables correction. */
-#define CERRSSMMMP_EN_C62X		(__BIT(3))
-
-/* BIT(3) enables logging. */
-#define UERRSSMMMP_EN_C62X		(__BIT(3))
-
-/* ETR */
-#define ETR_MAX_BANKS_C62X		16
-#define ETR_TX_RX_GAP_C62X		8
-#define ETR_TX_RINGS_MASK_C62X		0xFF
-#define ETR_BUNDLE_SIZE_C62X		0x1000
-
-/* AE firmware */
-#define AE_FW_PROD_TYPE_C62X		0x01000000
-#define AE_FW_MOF_NAME_C62X	"qat_c62xfw"
-#define AE_FW_MMP_NAME_C62X	"qat_c62x_mmp"
-#define AE_FW_UOF_NAME_C62X	"icp_qat_ae.suof"
-
-/* Clock frequency */
-#define CLOCK_PER_SEC_C62X		(685 * 1000000 / 16)
-
-#endif
diff --git a/sys/dev/qat/qat_d15xx.c b/sys/dev/qat/qat_d15xx.c
deleted file mode 100644
index cc0effb75934..000000000000
--- a/sys/dev/qat/qat_d15xx.c
+++ /dev/null
@@ -1,314 +0,0 @@
-/* SPDX-License-Identifier: BSD-2-Clause-NetBSD AND BSD-3-Clause */
-/*	$NetBSD: qat_d15xx.c,v 1.1 2019/11/20 09:37:46 hikaru Exp $	*/
-
-/*
- * Copyright (c) 2019 Internet Initiative Japan, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-/*
- *   Copyright(c) 2014 Intel Corporation.
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions
- *   are met:
- *
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in
- *       the documentation and/or other materials provided with the
- *       distribution.
- *     * Neither the name of Intel Corporation nor the names of its
- *       contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-#if 0
-__KERNEL_RCSID(0, "$NetBSD: qat_d15xx.c,v 1.1 2019/11/20 09:37:46 hikaru Exp $");
-#endif
-
-#include <sys/param.h>
-#include <sys/bus.h>
-#include <sys/systm.h>
-
-#include <machine/bus.h>
-
-#include <dev/pci/pcireg.h>
-#include <dev/pci/pcivar.h>
-
-#include "qatreg.h"
-#include "qat_hw17reg.h"
-#include "qat_d15xxreg.h"
-#include "qatvar.h"
-#include "qat_hw17var.h"
-
-static uint32_t
-qat_d15xx_get_accel_mask(struct qat_softc *sc)
-{
-	uint32_t fusectl, strap;
-
-	fusectl = pci_read_config(sc->sc_dev, FUSECTL_REG, 4);
-	strap = pci_read_config(sc->sc_dev, SOFTSTRAP_REG_D15XX, 4);
-
-	return (((~(fusectl | strap)) >> ACCEL_REG_OFFSET_D15XX) &
-	    ACCEL_MASK_D15XX);
-}
-
-static uint32_t
-qat_d15xx_get_ae_mask(struct qat_softc *sc)
-{
-	uint32_t fusectl, me_strap, me_disable, ssms_disabled;
-
-	fusectl = pci_read_config(sc->sc_dev, FUSECTL_REG, 4);
-	me_strap = pci_read_config(sc->sc_dev, SOFTSTRAP_REG_D15XX, 4);
-
-	/* If SSMs are disabled, then disable the corresponding MEs */
-	ssms_disabled = (~qat_d15xx_get_accel_mask(sc)) & ACCEL_MASK_D15XX;
-	me_disable = 0x3;
-	while (ssms_disabled) {
-		if (ssms_disabled & 1)
-			me_strap |= me_disable;
-		ssms_disabled >>= 1;
-		me_disable <<= 2;
-	}
-
-	return (~(fusectl | me_strap)) & AE_MASK_D15XX;
-}
-
-static enum qat_sku
-qat_d15xx_get_sku(struct qat_softc *sc)
-{
-	switch (sc->sc_ae_num) {
-	case 8:
-		return QAT_SKU_2;
-	case MAX_AE_D15XX:
-		return QAT_SKU_4;
-	}
-
-	return QAT_SKU_UNKNOWN;
-}
-
-static uint32_t
-qat_d15xx_get_accel_cap(struct qat_softc *sc)
-{
-	uint32_t cap, legfuse, strap;
-
-	legfuse = pci_read_config(sc->sc_dev, LEGFUSE_REG, 4);
-	strap = pci_read_config(sc->sc_dev, SOFTSTRAP_REG_D15XX, 4);
-
-	cap = QAT_ACCEL_CAP_CRYPTO_SYMMETRIC +
-		QAT_ACCEL_CAP_CRYPTO_ASYMMETRIC +
-		QAT_ACCEL_CAP_CIPHER +
-		QAT_ACCEL_CAP_AUTHENTICATION +
-		QAT_ACCEL_CAP_COMPRESSION +
-		QAT_ACCEL_CAP_ZUC +
-		QAT_ACCEL_CAP_SHA3;
-
-	if (legfuse & LEGFUSE_ACCEL_MASK_CIPHER_SLICE) {
-		cap &= ~QAT_ACCEL_CAP_CRYPTO_SYMMETRIC;
-		cap &= ~QAT_ACCEL_CAP_CIPHER;
-	}
-	if (legfuse & LEGFUSE_ACCEL_MASK_AUTH_SLICE)
-		cap &= ~QAT_ACCEL_CAP_AUTHENTICATION;
-	if (legfuse & LEGFUSE_ACCEL_MASK_PKE_SLICE)
-		cap &= ~QAT_ACCEL_CAP_CRYPTO_ASYMMETRIC;
-	if (legfuse & LEGFUSE_ACCEL_MASK_COMPRESS_SLICE)
-		cap &= ~QAT_ACCEL_CAP_COMPRESSION;
-	if (legfuse & LEGFUSE_ACCEL_MASK_EIA3_SLICE)
-		cap &= ~QAT_ACCEL_CAP_ZUC;
-
-	if ((strap | legfuse) & SOFTSTRAP_SS_POWERGATE_PKE_D15XX)
-		cap &= ~QAT_ACCEL_CAP_CRYPTO_ASYMMETRIC;
-	if ((strap | legfuse) & SOFTSTRAP_SS_POWERGATE_CY_D15XX)
-		cap &= ~QAT_ACCEL_CAP_COMPRESSION;
-
-	return cap;
-}
-
-static const char *
-qat_d15xx_get_fw_uof_name(struct qat_softc *sc)
-{
-
-	return AE_FW_UOF_NAME_D15XX;
-}
-
-static void
-qat_d15xx_enable_intr(struct qat_softc *sc)
-{
-
-	/* Enable bundle and misc interrupts */
-	qat_misc_write_4(sc, SMIAPF0_D15XX, SMIA0_MASK_D15XX);
-	qat_misc_write_4(sc, SMIAPF1_D15XX, SMIA1_MASK_D15XX);
-}
-
-/* Worker thread to service arbiter mappings */
-static uint32_t thrd_to_arb_map[] = {
-	0x12222AAA, 0x11222AAA, 0x12222AAA, 0x11222AAA, 0x12222AAA,
-	0x11222AAA, 0x12222AAA, 0x11222AAA, 0x12222AAA, 0x11222AAA
-};
-
-static void
-qat_d15xx_get_arb_mapping(struct qat_softc *sc, const uint32_t **arb_map_config)
-{
-	int i;
-
-	for (i = 1; i < MAX_AE_D15XX; i++) {
-		if ((~sc->sc_ae_mask) & (1 << i))
-			thrd_to_arb_map[i] = 0;
-	}
-	*arb_map_config = thrd_to_arb_map;
-}
-
-static void
-qat_d15xx_enable_error_interrupts(struct qat_softc *sc)
-{
-	qat_misc_write_4(sc, ERRMSK0, ERRMSK0_CERR_D15XX); /* ME0-ME3 */
-	qat_misc_write_4(sc, ERRMSK1, ERRMSK1_CERR_D15XX); /* ME4-ME7 */
-	qat_misc_write_4(sc, ERRMSK4, ERRMSK4_CERR_D15XX); /* ME8-ME9 */
-	qat_misc_write_4(sc, ERRMSK5, ERRMSK5_CERR_D15XX); /* SSM2-SSM4 */
-
-	/* Reset everything except VFtoPF1_16. */
-	qat_misc_read_write_and_4(sc, ERRMSK3, VF2PF1_16_D15XX);
-	/* Disable Secure RAM correctable error interrupt */
-	qat_misc_read_write_or_4(sc, ERRMSK3, ERRMSK3_CERR_D15XX);
-
-	/* RI CPP bus interface error detection and reporting. */
-	qat_misc_write_4(sc, RICPPINTCTL_D15XX, RICPP_EN_D15XX);
-
-	/* TI CPP bus interface error detection and reporting. */
-	qat_misc_write_4(sc, TICPPINTCTL_D15XX, TICPP_EN_D15XX);
-
-	/* Enable CFC Error interrupts and logging. */
-	qat_misc_write_4(sc, CPP_CFC_ERR_CTRL_D15XX, CPP_CFC_UE_D15XX);
-
-	/* Enable SecureRAM to fix and log Correctable errors */
-	qat_misc_write_4(sc, SECRAMCERR_D15XX, SECRAM_CERR_D15XX);
-
-	/* Enable SecureRAM Uncorrectable error interrupts and logging */
-	qat_misc_write_4(sc, SECRAMUERR, SECRAM_UERR_D15XX);
-
-	/* Enable Push/Pull Misc Uncorrectable error interrupts and logging */
-	qat_misc_write_4(sc, CPPMEMTGTERR, TGT_UERR_D15XX);
-}
-
-static void
-qat_d15xx_disable_error_interrupts(struct qat_softc *sc)
-{
-	/* ME0-ME3 */
-	qat_misc_write_4(sc, ERRMSK0, ERRMSK0_UERR_D15XX | ERRMSK0_CERR_D15XX);
-	/* ME4-ME7 */
-	qat_misc_write_4(sc, ERRMSK1, ERRMSK1_UERR_D15XX | ERRMSK1_CERR_D15XX);
-	/* Secure RAM, CPP Push Pull, RI, TI, SSM0-SSM1, CFC */
-	qat_misc_write_4(sc, ERRMSK3, ERRMSK3_UERR_D15XX | ERRMSK3_CERR_D15XX);
-	/* ME8-ME9 */
-	qat_misc_write_4(sc, ERRMSK4, ERRMSK4_UERR_D15XX | ERRMSK4_CERR_D15XX);
-	/* SSM2-SSM4 */
-	qat_misc_write_4(sc, ERRMSK5, ERRMSK5_UERR_D15XX | ERRMSK5_CERR_D15XX);
-}
-
-static void
-qat_d15xx_enable_error_correction(struct qat_softc *sc)
-{
-	u_int i, mask;
-
-	/* Enable Accel Engine error detection & correction */
-	for (i = 0, mask = sc->sc_ae_mask; mask; i++, mask >>= 1) {
-		if (!(mask & 1))
-			continue;
-		qat_misc_read_write_or_4(sc, AE_CTX_ENABLES_D15XX(i),
-		    ENABLE_AE_ECC_ERR_D15XX);
-		qat_misc_read_write_or_4(sc, AE_MISC_CONTROL_D15XX(i),
-		    ENABLE_AE_ECC_PARITY_CORR_D15XX);
-	}
-
-	/* Enable shared memory error detection & correction */
-	for (i = 0, mask = sc->sc_accel_mask; mask; i++, mask >>= 1) {
-		if (!(mask & 1))
-			continue;
-
-		qat_misc_read_write_or_4(sc, UERRSSMSH(i), ERRSSMSH_EN_D15XX);
-		qat_misc_read_write_or_4(sc, CERRSSMSH(i), ERRSSMSH_EN_D15XX);
-		qat_misc_read_write_or_4(sc, PPERR(i), PPERR_EN_D15XX);
-	}
-
-	qat_d15xx_enable_error_interrupts(sc);
-}
-
-const struct qat_hw qat_hw_d15xx = {
-	.qhw_sram_bar_id = BAR_SRAM_ID_D15XX,
-	.qhw_misc_bar_id = BAR_PMISC_ID_D15XX,
-	.qhw_etr_bar_id = BAR_ETR_ID_D15XX,
-	.qhw_cap_global_offset = CAP_GLOBAL_OFFSET_D15XX,
-	.qhw_ae_offset = AE_OFFSET_D15XX,
-	.qhw_ae_local_offset = AE_LOCAL_OFFSET_D15XX,
-	.qhw_etr_bundle_size = ETR_BUNDLE_SIZE_D15XX,
-	.qhw_num_banks = ETR_MAX_BANKS_D15XX,
-	.qhw_num_rings_per_bank = ETR_MAX_RINGS_PER_BANK,
-	.qhw_num_accel = MAX_ACCEL_D15XX,
-	.qhw_num_engines = MAX_AE_D15XX,
-	.qhw_tx_rx_gap = ETR_TX_RX_GAP_D15XX,
-	.qhw_tx_rings_mask = ETR_TX_RINGS_MASK_D15XX,
-	.qhw_clock_per_sec = CLOCK_PER_SEC_D15XX,
-	.qhw_fw_auth = true,
-	.qhw_fw_req_size = FW_REQ_DEFAULT_SZ_HW17,
-	.qhw_fw_resp_size = FW_RESP_DEFAULT_SZ_HW17,
-	.qhw_ring_asym_tx = 0,
-	.qhw_ring_asym_rx = 8,
-	.qhw_ring_sym_tx = 2,
-	.qhw_ring_sym_rx = 10,
-	.qhw_mof_fwname = AE_FW_MOF_NAME_D15XX,
-	.qhw_mmp_fwname = AE_FW_MMP_NAME_D15XX,
-	.qhw_prod_type = AE_FW_PROD_TYPE_D15XX,
-	.qhw_get_accel_mask = qat_d15xx_get_accel_mask,
-	.qhw_get_ae_mask = qat_d15xx_get_ae_mask,
-	.qhw_get_sku = qat_d15xx_get_sku,
-	.qhw_get_accel_cap = qat_d15xx_get_accel_cap,
-	.qhw_get_fw_uof_name = qat_d15xx_get_fw_uof_name,
-	.qhw_enable_intr = qat_d15xx_enable_intr,
-	.qhw_init_admin_comms = qat_adm_mailbox_init,
-	.qhw_send_admin_init = qat_adm_mailbox_send_init,
-	.qhw_init_arb = qat_arb_init,
-	.qhw_get_arb_mapping = qat_d15xx_get_arb_mapping,
-	.qhw_enable_error_correction = qat_d15xx_enable_error_correction,
-	.qhw_disable_error_interrupts = qat_d15xx_disable_error_interrupts,
-	.qhw_set_ssm_wdtimer = qat_set_ssm_wdtimer,
-	.qhw_check_slice_hang = qat_check_slice_hang,
-	.qhw_crypto_setup_desc = qat_hw17_crypto_setup_desc,
-	.qhw_crypto_setup_req_params = qat_hw17_crypto_setup_req_params,
-	.qhw_crypto_opaque_offset = offsetof(struct fw_la_resp, opaque_data),
-};
diff --git a/sys/dev/qat/qat_d15xxreg.h b/sys/dev/qat/qat_d15xxreg.h
deleted file mode 100644
index 4690ce325307..000000000000
--- a/sys/dev/qat/qat_d15xxreg.h
+++ /dev/null
@@ -1,201 +0,0 @@
-/* SPDX-License-Identifier: BSD-2-Clause-NetBSD AND BSD-3-Clause */
-/*	$NetBSD: qat_d15xxreg.h,v 1.1 2019/11/20 09:37:46 hikaru Exp $	*/
-
-/*
- * Copyright (c) 2019 Internet Initiative Japan, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-/*
- *   Copyright(c) 2014 Intel Corporation.
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions
- *   are met:
- *
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in
- *       the documentation and/or other materials provided with the
- *       distribution.
- *     * Neither the name of Intel Corporation nor the names of its
- *       contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/* $FreeBSD$ */
-
-#ifndef _DEV_PCI_QAT_D15XXREG_H_
-#define _DEV_PCI_QAT_D15XXREG_H_
-
-/* Max number of accelerators and engines */
-#define MAX_ACCEL_D15XX			5
-#define MAX_AE_D15XX			10
-
-/* PCIe BAR index */
-#define BAR_SRAM_ID_D15XX		0
-#define BAR_PMISC_ID_D15XX		1
-#define BAR_ETR_ID_D15XX		2
-
-/* BAR PMISC sub-regions */
-#define AE_OFFSET_D15XX			0x20000
-#define AE_LOCAL_OFFSET_D15XX		0x20800
-#define CAP_GLOBAL_OFFSET_D15XX		0x30000
-
-#define SOFTSTRAP_REG_D15XX			0x2EC
-#define SOFTSTRAP_SS_POWERGATE_CY_D15XX		__BIT(23)
-#define SOFTSTRAP_SS_POWERGATE_PKE_D15XX	__BIT(24)
-
-#define ACCEL_REG_OFFSET_D15XX		16
-#define ACCEL_MASK_D15XX		0x1F
-#define AE_MASK_D15XX			0x3FF
-
-#define SMIAPF0_D15XX			0x3A028
-#define SMIAPF1_D15XX			0x3A030
-#define SMIA0_MASK_D15XX		0xFFFF
-#define SMIA1_MASK_D15XX		0x1
-
-/* Error detection and correction */
-#define AE_CTX_ENABLES_D15XX(i)		((i) * 0x1000 + 0x20818)
-#define AE_MISC_CONTROL_D15XX(i)		((i) * 0x1000 + 0x20960)
-#define ENABLE_AE_ECC_ERR_D15XX		__BIT(28)
-#define ENABLE_AE_ECC_PARITY_CORR_D15XX	(__BIT(24) | __BIT(12))
-#define ERRSSMSH_EN_D15XX		__BIT(3)
-/* BIT(2) enables the logging of push/pull data errors. */
-#define PPERR_EN_D15XX			(__BIT(2))
-
-/* Mask for VF2PF interrupts */
-#define VF2PF1_16_D15XX			(0xFFFF << 9)
-#define ERRSOU3_VF2PF_D15XX(errsou3)	(((errsou3) & 0x01FFFE00) >> 9)
-#define ERRMSK3_VF2PF_D15XX(vf_mask)	(((vf_mask) & 0xFFFF) << 9)
-
-/* Masks for correctable error interrupts. */
-#define ERRMSK0_CERR_D15XX	(__BIT(24) | __BIT(16) | __BIT(8) | __BIT(0))
-#define ERRMSK1_CERR_D15XX	(__BIT(24) | __BIT(16) | __BIT(8) | __BIT(0))
-#define ERRMSK3_CERR_D15XX	(__BIT(7))
-#define ERRMSK4_CERR_D15XX	(__BIT(8) | __BIT(0))
-#define ERRMSK5_CERR_D15XX	(0)
-
-/* Masks for uncorrectable error interrupts. */
-#define ERRMSK0_UERR_D15XX	(__BIT(25) | __BIT(17) | __BIT(9) | __BIT(1))
-#define ERRMSK1_UERR_D15XX	(__BIT(25) | __BIT(17) | __BIT(9) | __BIT(1))
-#define ERRMSK3_UERR_D15XX	(__BIT(8) | __BIT(6) | __BIT(5) | __BIT(4) | \
-				 __BIT(3) | __BIT(2) | __BIT(0))
-#define ERRMSK4_UERR_D15XX	(__BIT(9) | __BIT(1))
-#define ERRMSK5_UERR_D15XX	(__BIT(18) | __BIT(17) | __BIT(16))
-
-/* RI CPP control */
-#define RICPPINTCTL_D15XX		(0x3A000 + 0x110)
-/*
- * BIT(2) enables error detection and reporting on the RI Parity Error.
- * BIT(1) enables error detection and reporting on the RI CPP Pull interface.
- * BIT(0) enables error detection and reporting on the RI CPP Push interface.
- */
-#define RICPP_EN_D15XX			(__BIT(2) | __BIT(1) | __BIT(0))
-
-/* TI CPP control */
-#define TICPPINTCTL_D15XX		(0x3A400 + 0x138)
-/*
- * BIT(3) enables error detection and reporting on the ETR Parity Error.
- * BIT(2) enables error detection and reporting on the TI Parity Error.
- * BIT(1) enables error detection and reporting on the TI CPP Pull interface.
- * BIT(0) enables error detection and reporting on the TI CPP Push interface.
- */
-#define TICPP_EN_D15XX		\
-	(__BIT(4) | __BIT(3) | __BIT(2) | __BIT(1) | __BIT(0))
-
-/* CFC Uncorrectable Errors */
-#define CPP_CFC_ERR_CTRL_D15XX	(0x30000 + 0xC00)
-/*
- * BIT(1) enables interrupt.
- * BIT(0) enables detecting and logging of push/pull data errors.
- */
-#define CPP_CFC_UE_D15XX		(__BIT(1) | __BIT(0))
-
-/* Correctable SecureRAM Error Reg */
-#define SECRAMCERR_D15XX			(0x3AC00 + 0x00)
-/* BIT(3) enables fixing and logging of correctable errors. */
-#define SECRAM_CERR_D15XX		(__BIT(3))
-
-/* Uncorrectable SecureRAM Error Reg */
-/*
- * BIT(17) enables interrupt.
- * BIT(3) enables detecting and logging of uncorrectable errors.
- */
-#define SECRAM_UERR_D15XX		(__BIT(17) | __BIT(3))
-
-/* Miscellaneous Memory Target Errors Register */
-/*
- * BIT(3) enables detecting and logging push/pull data errors.
- * BIT(2) enables interrupt.
- */
-#define TGT_UERR_D15XX			(__BIT(3) | __BIT(2))
-
-
-#define SLICEPWRDOWN_D15XX(i)	((i) * 0x4000 + 0x2C)
-/* Enabling PKE4-PKE0. */
-#define MMP_PWR_UP_MSK_D15XX		\
-	(__BIT(20) | __BIT(19) | __BIT(18) | __BIT(17) | __BIT(16))
-
-/* CPM Uncorrectable Errors */
-#define INTMASKSSM_D15XX(i)		((i) * 0x4000 + 0x0)
-/* Disabling interrupts for correctable errors. */
-#define INTMASKSSM_UERR_D15XX	\
-	(__BIT(11) | __BIT(9) | __BIT(7) | __BIT(5) | __BIT(3) | __BIT(1))
-
-/* MMP */
-/* BIT(3) enables correction. */
-#define CERRSSMMMP_EN_D15XX		(__BIT(3))
-
-/* BIT(3) enables logging. */
-#define UERRSSMMMP_EN_D15XX		(__BIT(3))
-
-/* ETR */
-#define ETR_MAX_BANKS_D15XX		16
-#define ETR_TX_RX_GAP_D15XX		8
-#define ETR_TX_RINGS_MASK_D15XX		0xFF
-#define ETR_BUNDLE_SIZE_D15XX		0x1000
-
-/* AE firmware */
-#define AE_FW_PROD_TYPE_D15XX	0x01000000
-#define AE_FW_MOF_NAME_D15XX	"qat_d15xxfw"
-#define AE_FW_MMP_NAME_D15XX	"qat_d15xx_mmp"
-#define AE_FW_UOF_NAME_D15XX	"icp_qat_ae.suof"
-
-/* Clock frequency */
-#define CLOCK_PER_SEC_D15XX		(685 * 1000000 / 16)
-
-#endif
diff --git a/sys/dev/qat/qat_dh895xcc.c b/sys/dev/qat/qat_dh895xcc.c
deleted file mode 100644
index 8b566f3925d4..000000000000
--- a/sys/dev/qat/qat_dh895xcc.c
+++ /dev/null
@@ -1,271 +0,0 @@
-/* SPDX-License-Identifier: BSD-2-Clause AND BSD-3-Clause */
-/*
- * Copyright (c) 2020 Rubicon Communications, LLC (Netgate)
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-/*
- *   Copyright(c) 2014 - 2020 Intel Corporation.
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions
- *   are met:
- *
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in
- *       the documentation and/or other materials provided with the
- *       distribution.
- *     * Neither the name of Intel Corporation nor the names of its
- *       contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include <sys/param.h>
-#include <sys/bus.h>
-
-#include <machine/bus.h>
-
-#include <dev/pci/pcireg.h>
-#include <dev/pci/pcivar.h>
-
-#include "qatreg.h"
-#include "qatvar.h"
-#include "qat_hw17reg.h"
-#include "qat_hw17var.h"
-#include "qat_dh895xccreg.h"
-
-static uint32_t
-qat_dh895xcc_get_accel_mask(struct qat_softc *sc)
-{
-	uint32_t fusectl, strap;
-
-	fusectl = pci_read_config(sc->sc_dev, FUSECTL_REG, 4);
-	strap = pci_read_config(sc->sc_dev, SOFTSTRAP_REG_DH895XCC, 4);
-
-	return (((~(fusectl | strap)) >> ACCEL_REG_OFFSET_DH895XCC) &
-	    ACCEL_MASK_DH895XCC);
-}
-
-static uint32_t
-qat_dh895xcc_get_ae_mask(struct qat_softc *sc)
-{
-	uint32_t fusectl, strap;
-
-	fusectl = pci_read_config(sc->sc_dev, FUSECTL_REG, 4);
-	strap = pci_read_config(sc->sc_dev, SOFTSTRAP_REG_DH895XCC, 4);
-
-	return (~(fusectl | strap)) & AE_MASK_DH895XCC;
-}
-
-static enum qat_sku
-qat_dh895xcc_get_sku(struct qat_softc *sc)
-{
-	uint32_t fusectl, sku;
-
-	fusectl = pci_read_config(sc->sc_dev, FUSECTL_REG, 4);
-	sku = (fusectl & FUSECTL_SKU_MASK_DH895XCC) >>
-	    FUSECTL_SKU_SHIFT_DH895XCC;
-	switch (sku) {
-	case FUSECTL_SKU_1_DH895XCC:
-		return QAT_SKU_1;
-	case FUSECTL_SKU_2_DH895XCC:
-		return QAT_SKU_2;
-	case FUSECTL_SKU_3_DH895XCC:
-		return QAT_SKU_3;
-	case FUSECTL_SKU_4_DH895XCC:
-		return QAT_SKU_4;
-	default:
-		return QAT_SKU_UNKNOWN;
-	}
-}
-
-static uint32_t
-qat_dh895xcc_get_accel_cap(struct qat_softc *sc)
-{
-	uint32_t cap, legfuse;
-
-	legfuse = pci_read_config(sc->sc_dev, LEGFUSE_REG, 4);
-
-	cap = QAT_ACCEL_CAP_CRYPTO_SYMMETRIC +
-		QAT_ACCEL_CAP_CRYPTO_ASYMMETRIC +
-		QAT_ACCEL_CAP_CIPHER +
-		QAT_ACCEL_CAP_AUTHENTICATION +
-		QAT_ACCEL_CAP_COMPRESSION +
-		QAT_ACCEL_CAP_ZUC +
-		QAT_ACCEL_CAP_SHA3;
-
-	if (legfuse & LEGFUSE_ACCEL_MASK_CIPHER_SLICE) {
-		cap &= ~QAT_ACCEL_CAP_CRYPTO_SYMMETRIC;
-		cap &= ~QAT_ACCEL_CAP_CIPHER;
-	}
-	if (legfuse & LEGFUSE_ACCEL_MASK_AUTH_SLICE)
-		cap &= ~QAT_ACCEL_CAP_AUTHENTICATION;
-	if (legfuse & LEGFUSE_ACCEL_MASK_PKE_SLICE)
-		cap &= ~QAT_ACCEL_CAP_CRYPTO_ASYMMETRIC;
-	if (legfuse & LEGFUSE_ACCEL_MASK_COMPRESS_SLICE)
-		cap &= ~QAT_ACCEL_CAP_COMPRESSION;
-	if (legfuse & LEGFUSE_ACCEL_MASK_EIA3_SLICE)
-		cap &= ~QAT_ACCEL_CAP_ZUC;
-
-	return cap;
-}
-
-static const char *
-qat_dh895xcc_get_fw_uof_name(struct qat_softc *sc)
-{
-	return AE_FW_UOF_NAME_DH895XCC;
-}
-
-static void
-qat_dh895xcc_enable_intr(struct qat_softc *sc)
-{
-	/* Enable bundle and misc interrupts */
-	qat_misc_write_4(sc, SMIAPF0_DH895XCC, SMIA0_MASK_DH895XCC);
-	qat_misc_write_4(sc, SMIAPF1_DH895XCC, SMIA1_MASK_DH895XCC);
-}
-
-/* Worker thread to service arbiter mappings based on dev SKUs */
-static uint32_t thrd_to_arb_map_sku4[] = {
-	0x12222AAA, 0x11666666, 0x12222AAA, 0x11666666,
-	0x12222AAA, 0x11222222, 0x12222AAA, 0x11222222,
-	0x00000000, 0x00000000, 0x00000000, 0x00000000,
-};
-
-static uint32_t thrd_to_arb_map_sku6[] = {
-	0x12222AAA, 0x11666666, 0x12222AAA, 0x11666666,
-	0x12222AAA, 0x11222222, 0x12222AAA, 0x11222222,
-	0x12222AAA, 0x11222222, 0x12222AAA, 0x11222222,
-};
-
-static void
-qat_dh895xcc_get_arb_mapping(struct qat_softc *sc,
-    const uint32_t **arb_map_config)
-{
-	uint32_t *map, sku;
-	int i;
-
-	sku = qat_dh895xcc_get_sku(sc);
-	switch (sku) {
-	case QAT_SKU_1:
-		map = thrd_to_arb_map_sku4;
-		break;
-	case QAT_SKU_2:
-	case QAT_SKU_4:
-		map = thrd_to_arb_map_sku6;
-		break;
-	default:
-		*arb_map_config = NULL;
-		return;
-	}
-
-	for (i = 1; i < MAX_AE_DH895XCC; i++) {
-		if ((~sc->sc_ae_mask) & (1 << i))
-			map[i] = 0;
-	}
-	*arb_map_config = map;
-}
-
-static void
-qat_dh895xcc_enable_error_correction(struct qat_softc *sc)
-{
-	uint32_t mask;
-	u_int i;
-
-	/* Enable Accel Engine error detection & correction */
-	for (i = 0, mask = sc->sc_ae_mask; mask; i++, mask >>= 1) {
-		if (!(mask & 1))
-			continue;
-		qat_misc_read_write_or_4(sc, AE_CTX_ENABLES_DH895XCC(i),
-		    ENABLE_AE_ECC_ERR_DH895XCC);
-		qat_misc_read_write_or_4(sc, AE_MISC_CONTROL_DH895XCC(i),
-		    ENABLE_AE_ECC_PARITY_CORR_DH895XCC);
-	}
-
-	/* Enable shared memory error detection & correction */
-	for (i = 0, mask = sc->sc_accel_mask; mask; i++, mask >>= 1) {
-		if (!(mask & 1))
-			continue;
-
-		qat_misc_read_write_or_4(sc, UERRSSMSH(i), ERRSSMSH_EN_DH895XCC);
-		qat_misc_read_write_or_4(sc, CERRSSMSH(i), ERRSSMSH_EN_DH895XCC);
-		qat_misc_read_write_or_4(sc, PPERR(i), PPERR_EN_DH895XCC);
-	}
-}
-
-const struct qat_hw qat_hw_dh895xcc = {
-	.qhw_sram_bar_id = BAR_SRAM_ID_DH895XCC,
-	.qhw_misc_bar_id = BAR_PMISC_ID_DH895XCC,
-	.qhw_etr_bar_id = BAR_ETR_ID_DH895XCC,
-	.qhw_cap_global_offset = CAP_GLOBAL_OFFSET_DH895XCC,
-	.qhw_ae_offset = AE_OFFSET_DH895XCC,
-	.qhw_ae_local_offset = AE_LOCAL_OFFSET_DH895XCC,
-	.qhw_etr_bundle_size = ETR_BUNDLE_SIZE_DH895XCC,
-	.qhw_num_banks = ETR_MAX_BANKS_DH895XCC,
-	.qhw_num_rings_per_bank = ETR_MAX_RINGS_PER_BANK,
-	.qhw_num_accel = MAX_ACCEL_DH895XCC,
-	.qhw_num_engines = MAX_AE_DH895XCC,
-	.qhw_tx_rx_gap = ETR_TX_RX_GAP_DH895XCC,
-	.qhw_tx_rings_mask = ETR_TX_RINGS_MASK_DH895XCC,
-	.qhw_clock_per_sec = CLOCK_PER_SEC_DH895XCC,
-	.qhw_fw_auth = false,
-	.qhw_fw_req_size = FW_REQ_DEFAULT_SZ_HW17,
-	.qhw_fw_resp_size = FW_RESP_DEFAULT_SZ_HW17,
-	.qhw_ring_asym_tx = 0,
-	.qhw_ring_asym_rx = 8,
-	.qhw_ring_sym_tx = 2,
-	.qhw_ring_sym_rx = 10,
-	.qhw_mof_fwname = AE_FW_MOF_NAME_DH895XCC,
-	.qhw_mmp_fwname = AE_FW_MMP_NAME_DH895XCC,
-	.qhw_prod_type = AE_FW_PROD_TYPE_DH895XCC,
-	.qhw_get_accel_mask = qat_dh895xcc_get_accel_mask,
-	.qhw_get_ae_mask = qat_dh895xcc_get_ae_mask,
-	.qhw_get_sku = qat_dh895xcc_get_sku,
-	.qhw_get_accel_cap = qat_dh895xcc_get_accel_cap,
-	.qhw_get_fw_uof_name = qat_dh895xcc_get_fw_uof_name,
-	.qhw_enable_intr = qat_dh895xcc_enable_intr,
-	.qhw_init_admin_comms = qat_adm_mailbox_init,
-	.qhw_send_admin_init = qat_adm_mailbox_send_init,
-	.qhw_init_arb = qat_arb_init,
-	.qhw_get_arb_mapping = qat_dh895xcc_get_arb_mapping,
-	.qhw_enable_error_correction = qat_dh895xcc_enable_error_correction,
-	.qhw_check_slice_hang = qat_check_slice_hang,
-	.qhw_crypto_setup_desc = qat_hw17_crypto_setup_desc,
-	.qhw_crypto_setup_req_params = qat_hw17_crypto_setup_req_params,
-	.qhw_crypto_opaque_offset = offsetof(struct fw_la_resp, opaque_data),
-};
diff --git a/sys/dev/qat/qat_dh895xccreg.h b/sys/dev/qat/qat_dh895xccreg.h
deleted file mode 100644
index 5d57d82a597e..000000000000
--- a/sys/dev/qat/qat_dh895xccreg.h
+++ /dev/null
@@ -1,119 +0,0 @@
-/* SPDX-License-Identifier: BSD-2-Clause-NetBSD AND BSD-3-Clause */
-
-/*
- * Copyright (c) 2019 Internet Initiative Japan, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-/*
- *   Copyright(c) 2014-2020 Intel Corporation.
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions
- *   are met:
- *
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in
- *       the documentation and/or other materials provided with the
- *       distribution.
- *     * Neither the name of Intel Corporation nor the names of its
- *       contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/* $FreeBSD$ */
-
-#ifndef _DEV_PCI_QAT_DH895XCCREG_H_
-#define _DEV_PCI_QAT_DH895XCCREG_H_
-
-/* Max number of accelerators and engines */
-#define MAX_ACCEL_DH895XCC		6
-#define MAX_AE_DH895XCC			12
-
-/* PCIe BAR index */
-#define BAR_SRAM_ID_DH895XCC		0
-#define BAR_PMISC_ID_DH895XCC		1
-#define BAR_ETR_ID_DH895XCC		2
-
-/* BAR PMISC sub-regions */
-#define AE_OFFSET_DH895XCC		0x20000
-#define AE_LOCAL_OFFSET_DH895XCC	0x20800
-#define CAP_GLOBAL_OFFSET_DH895XCC	0x30000
-
-#define SOFTSTRAP_REG_DH895XCC			0x2EC
-
-#define	FUSECTL_SKU_MASK_DH895XCC	0x300000
-#define	FUSECTL_SKU_SHIFT_DH895XCC	20
-#define	FUSECTL_SKU_1_DH895XCC		0
-#define	FUSECTL_SKU_2_DH895XCC		1
-#define	FUSECTL_SKU_3_DH895XCC		2
-#define	FUSECTL_SKU_4_DH895XCC		3
-
-#define ACCEL_REG_OFFSET_DH895XCC	13
-#define ACCEL_MASK_DH895XCC		0x3F
-#define AE_MASK_DH895XCC		0xFFF
-
-#define SMIAPF0_DH895XCC		0x3A028
-#define SMIAPF1_DH895XCC		0x3A030
-#define SMIA0_MASK_DH895XCC		0xFFFFFFFF
-#define SMIA1_MASK_DH895XCC		0x1
-
-/* Error detection and correction */
-#define AE_CTX_ENABLES_DH895XCC(i)	((i) * 0x1000 + 0x20818)
-#define AE_MISC_CONTROL_DH895XCC(i)	((i) * 0x1000 + 0x20960)
-#define ENABLE_AE_ECC_ERR_DH895XCC	__BIT(28)
-#define ENABLE_AE_ECC_PARITY_CORR_DH895XCC (__BIT(24) | __BIT(12))
-#define ERRSSMSH_EN_DH895XCC		__BIT(3)
-/* BIT(2) enables the logging of push/pull data errors. */
-#define PPERR_EN_DH895XCC		(__BIT(2))
-
-/* ETR */
-#define ETR_MAX_BANKS_DH895XCC		32
-#define ETR_TX_RX_GAP_DH895XCC		8
-#define ETR_TX_RINGS_MASK_DH895XCC	0xFF
-#define ETR_BUNDLE_SIZE_DH895XCC	0x1000
-
-/* AE firmware */
-#define AE_FW_PROD_TYPE_DH895XCC	0x00400000
-#define AE_FW_MOF_NAME_DH895XCC		"qat_dh895xccfw"
-#define AE_FW_MMP_NAME_DH895XCC		"qat_895xcc_mmp"
-#define AE_FW_UOF_NAME_DH895XCC		"icp_qat_ae.uof"
-
-/* Clock frequency */
-#define CLOCK_PER_SEC_DH895XCC		(685 * 1000000 / 16)
-
-#endif
diff --git a/sys/dev/qat/qat_hw17.c b/sys/dev/qat/qat_hw17.c
deleted file mode 100644
index 92f2c1ee251d..000000000000
--- a/sys/dev/qat/qat_hw17.c
+++ /dev/null
@@ -1,674 +0,0 @@
-/* SPDX-License-Identifier: BSD-2-Clause-NetBSD AND BSD-3-Clause */
-/*	$NetBSD: qat_hw17.c,v 1.1 2019/11/20 09:37:46 hikaru Exp $	*/
-
-/*
- * Copyright (c) 2019 Internet Initiative Japan, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-/*
- *   Copyright(c) 2014 Intel Corporation.
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions
- *   are met:
- *
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in
- *       the documentation and/or other materials provided with the
- *       distribution.
- *     * Neither the name of Intel Corporation nor the names of its
- *       contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-#if 0
-__KERNEL_RCSID(0, "$NetBSD: qat_hw17.c,v 1.1 2019/11/20 09:37:46 hikaru Exp $");
-#endif
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/bus.h>
-#include <sys/proc.h>
-
-#include <machine/bus.h>
-
-#include <opencrypto/xform.h>
-
-#include <dev/pci/pcireg.h>
-#include <dev/pci/pcivar.h>
-
-#include "qatreg.h"
-#include "qat_hw17reg.h"
-#include "qatvar.h"
-#include "qat_hw17var.h"
-
-int		qat_adm_mailbox_put_msg_sync(struct qat_softc *, uint32_t,
-		    void *, void *);
-int		qat_adm_mailbox_send(struct qat_softc *,
-		    struct fw_init_admin_req *, struct fw_init_admin_resp *);
-int		qat_adm_mailbox_send_init_me(struct qat_softc *);
-int		qat_adm_mailbox_send_hb_timer(struct qat_softc *);
-int		qat_adm_mailbox_send_fw_status(struct qat_softc *);
-int		qat_adm_mailbox_send_constants(struct qat_softc *);
-
-int
-qat_adm_mailbox_init(struct qat_softc *sc)
-{
-	uint64_t addr;
-	int error;
-	struct qat_dmamem *qdm;
-
-	error = qat_alloc_dmamem(sc, &sc->sc_admin_comms.qadc_dma, 1,
-	    PAGE_SIZE, PAGE_SIZE);
-	if (error)
-		return error;
-
-	qdm = &sc->sc_admin_comms.qadc_const_tbl_dma;
-	error = qat_alloc_dmamem(sc, qdm, 1, PAGE_SIZE, PAGE_SIZE);
-	if (error)
-		return error;
-
-	memcpy(qdm->qdm_dma_vaddr,
-	    mailbox_const_tab, sizeof(mailbox_const_tab));
-
-	bus_dmamap_sync(qdm->qdm_dma_tag, qdm->qdm_dma_map,
-	    BUS_DMASYNC_PREWRITE);
-
-	error = qat_alloc_dmamem(sc, &sc->sc_admin_comms.qadc_hb_dma, 1,
-	    PAGE_SIZE, PAGE_SIZE);
-	if (error)
-		return error;
-
-	addr = (uint64_t)sc->sc_admin_comms.qadc_dma.qdm_dma_seg.ds_addr;
-	qat_misc_write_4(sc, ADMINMSGUR, addr >> 32);
-	qat_misc_write_4(sc, ADMINMSGLR, addr);
-
-	return 0;
-}
-
-int
-qat_adm_mailbox_put_msg_sync(struct qat_softc *sc, uint32_t ae,
-    void *in, void *out)
-{
-	struct qat_dmamem *qdm;
-	uint32_t mailbox;
-	bus_size_t mb_offset = MAILBOX_BASE + (ae * MAILBOX_STRIDE);
-	int offset = ae * ADMINMSG_LEN * 2;
-	int times, received;
-	uint8_t *buf = (uint8_t *)sc->sc_admin_comms.qadc_dma.qdm_dma_vaddr + offset;
-
-	mailbox = qat_misc_read_4(sc, mb_offset);
-	if (mailbox == 1)
-		return EAGAIN;
-
-	qdm = &sc->sc_admin_comms.qadc_dma;
-	memcpy(buf, in, ADMINMSG_LEN);
-	bus_dmamap_sync(qdm->qdm_dma_tag, qdm->qdm_dma_map,
-	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
-	qat_misc_write_4(sc, mb_offset, 1);
-
-	received = 0;
-	for (times = 0; times < 50; times++) {
-		DELAY(20000);
-		if (qat_misc_read_4(sc, mb_offset) == 0) {
-			received = 1;
-			break;
-		}
-	}
-	if (received) {
-		bus_dmamap_sync(qdm->qdm_dma_tag, qdm->qdm_dma_map,
-		    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
-		memcpy(out, buf + ADMINMSG_LEN, ADMINMSG_LEN);
-	} else {
-		device_printf(sc->sc_dev,
-		    "Failed to send admin msg to accelerator\n");
-	}
-
-	return received ? 0 : EFAULT;
-}
-
-int
-qat_adm_mailbox_send(struct qat_softc *sc,
-    struct fw_init_admin_req *req, struct fw_init_admin_resp *resp)
-{
-	int error;
-	uint32_t mask;
-	uint8_t ae;
-
-	for (ae = 0, mask = sc->sc_ae_mask; mask; ae++, mask >>= 1) {
-		if (!(mask & 1))
-			continue;
-
-		error = qat_adm_mailbox_put_msg_sync(sc, ae, req, resp);
-		if (error)
-			return error;
-		if (resp->init_resp_hdr.status) {
-			device_printf(sc->sc_dev,
-			    "Failed to send admin msg: cmd %d\n",
-			    req->init_admin_cmd_id);
-			return EFAULT;
-		}
-	}
-
-	return 0;
-}
-
-int
-qat_adm_mailbox_send_init_me(struct qat_softc *sc)
-{
-	struct fw_init_admin_req req;
-	struct fw_init_admin_resp resp;
-
-	memset(&req, 0, sizeof(req));
-	req.init_admin_cmd_id = FW_INIT_ME;
-
-	return qat_adm_mailbox_send(sc, &req, &resp);
-}
-
-int
-qat_adm_mailbox_send_hb_timer(struct qat_softc *sc)
-{
-	struct fw_init_admin_req req;
-	struct fw_init_admin_resp resp;
-
-	memset(&req, 0, sizeof(req));
-	req.init_admin_cmd_id = FW_HEARTBEAT_TIMER_SET;
-
-	req.init_cfg_ptr = sc->sc_admin_comms.qadc_hb_dma.qdm_dma_seg.ds_addr;
-	req.heartbeat_ticks =
-	    sc->sc_hw.qhw_clock_per_sec / 1000 * QAT_HB_INTERVAL;
-
-	return qat_adm_mailbox_send(sc, &req, &resp);
-}
-
-int
-qat_adm_mailbox_send_fw_status(struct qat_softc *sc)
-{
-	int error;
-	struct fw_init_admin_req req;
-	struct fw_init_admin_resp resp;
-
-	memset(&req, 0, sizeof(req));
-	req.init_admin_cmd_id = FW_STATUS_GET;
-
-	error = qat_adm_mailbox_send(sc, &req, &resp);
-	if (error)
-		return error;
-
-	return 0;
-}
-
-int
-qat_adm_mailbox_send_constants(struct qat_softc *sc)
-{
-	struct fw_init_admin_req req;
-	struct fw_init_admin_resp resp;
-
-	memset(&req, 0, sizeof(req));
-	req.init_admin_cmd_id = FW_CONSTANTS_CFG;
-
-	req.init_cfg_sz = 1024;
-	req.init_cfg_ptr =
-	    sc->sc_admin_comms.qadc_const_tbl_dma.qdm_dma_seg.ds_addr;
-
-	return qat_adm_mailbox_send(sc, &req, &resp);
-}
-
-int
-qat_adm_mailbox_send_init(struct qat_softc *sc)
-{
-	int error;
-
-	error = qat_adm_mailbox_send_init_me(sc);
-	if (error)
-		return error;
-
-	error = qat_adm_mailbox_send_hb_timer(sc);
-	if (error)
-		return error;
-
-	error = qat_adm_mailbox_send_fw_status(sc);
-	if (error)
-		return error;
-
-	return qat_adm_mailbox_send_constants(sc);
-}
-
-int
-qat_arb_init(struct qat_softc *sc)
-{
-	uint32_t arb_cfg = 0x1 << 31 | 0x4 << 4 | 0x1;
-	uint32_t arb, i;
-	const uint32_t *thd_2_arb_cfg;
-
-	/* Service arb configured for 32 bytes responses and
-	 * ring flow control check enabled. */
-	for (arb = 0; arb < MAX_ARB; arb++)
-		qat_arb_sarconfig_write_4(sc, arb, arb_cfg);
-
-	/* Map worker threads to service arbiters */
-	sc->sc_hw.qhw_get_arb_mapping(sc, &thd_2_arb_cfg);
-
-	if (!thd_2_arb_cfg)
-		return EINVAL;
-
-	for (i = 0; i < sc->sc_hw.qhw_num_engines; i++)
-		qat_arb_wrk_2_ser_map_write_4(sc, i, *(thd_2_arb_cfg + i));
-
-	return 0;
-}
-
-int
-qat_set_ssm_wdtimer(struct qat_softc *sc)
-{
-	uint32_t timer;
-	u_int mask;
-	int i;
-
-	timer = sc->sc_hw.qhw_clock_per_sec / 1000 * QAT_SSM_WDT;
-	for (i = 0, mask = sc->sc_accel_mask; mask; i++, mask >>= 1) {
-		if (!(mask & 1))
-			continue;
-		qat_misc_write_4(sc, SSMWDT(i), timer);
-		qat_misc_write_4(sc, SSMWDTPKE(i), timer);
-	}
-
-	return 0;
-}
-
-int
-qat_check_slice_hang(struct qat_softc *sc)
-{
-	int handled = 0;
-
-	return handled;
-}
-
-static uint32_t
-qat_hw17_crypto_setup_cipher_ctrl(struct qat_crypto_desc *desc,
-    struct qat_session *qs, uint32_t cd_blk_offset,
-    struct fw_la_bulk_req *req_tmpl, enum fw_slice next_slice)
-{
-	struct fw_cipher_cd_ctrl_hdr *cipher_cd_ctrl =
-	    (struct fw_cipher_cd_ctrl_hdr *)&req_tmpl->cd_ctrl;
-
-	desc->qcd_cipher_blk_sz = HW_AES_BLK_SZ;
-	desc->qcd_cipher_offset = cd_blk_offset;
-
-	cipher_cd_ctrl->cipher_state_sz = desc->qcd_cipher_blk_sz >> 3;
-	cipher_cd_ctrl->cipher_key_sz = qs->qs_cipher_klen >> 3;
-	cipher_cd_ctrl->cipher_cfg_offset = cd_blk_offset >> 3;
-	FW_COMN_CURR_ID_SET(cipher_cd_ctrl, FW_SLICE_CIPHER);
-	FW_COMN_NEXT_ID_SET(cipher_cd_ctrl, next_slice);
-
-	return roundup(sizeof(struct hw_cipher_config) + qs->qs_cipher_klen, 8);
-}
-
-static void
-qat_hw17_crypto_setup_cipher_cdesc(const struct qat_crypto_desc *desc,
-    const struct qat_session *qs, const struct cryptop *crp,
-    union hw_cipher_algo_blk *cipher)
-{
-	const uint8_t *key;
-
-	cipher->max.cipher_config.val =
-	    qat_crypto_load_cipher_session(desc, qs);
-	if (crp != NULL && crp->crp_cipher_key != NULL)
-		key = crp->crp_cipher_key;
-	else
-		key = qs->qs_cipher_key;
-	memcpy(cipher->max.key, key, qs->qs_cipher_klen);
-}
-
-static uint32_t
-qat_hw17_crypto_setup_auth_ctrl(struct qat_crypto_desc *desc,
-    struct qat_session *qs, uint32_t cd_blk_offset,
-    struct fw_la_bulk_req *req_tmpl, enum fw_slice next_slice)
-{
-	struct fw_auth_cd_ctrl_hdr *auth_cd_ctrl =
-	    (struct fw_auth_cd_ctrl_hdr *)&req_tmpl->cd_ctrl;
-	struct qat_sym_hash_def const *hash_def;
-
-	(void)qat_crypto_load_auth_session(desc, qs, &hash_def);
-
-	auth_cd_ctrl->hash_cfg_offset = cd_blk_offset >> 3;
-	auth_cd_ctrl->hash_flags = FW_AUTH_HDR_FLAG_NO_NESTED;
-	auth_cd_ctrl->inner_res_sz = hash_def->qshd_alg->qshai_digest_len;
-	auth_cd_ctrl->final_sz = hash_def->qshd_alg->qshai_sah->hashsize;
-
-	auth_cd_ctrl->inner_state1_sz =
-	    roundup(hash_def->qshd_qat->qshqi_state1_len, 8);
-	auth_cd_ctrl->inner_state2_sz =
-	    roundup(hash_def->qshd_qat->qshqi_state2_len, 8);
-	auth_cd_ctrl->inner_state2_offset =
-	    auth_cd_ctrl->hash_cfg_offset +
-	    ((sizeof(struct hw_auth_setup) +
-	    auth_cd_ctrl->inner_state1_sz) >> 3);
-
-	FW_COMN_CURR_ID_SET(auth_cd_ctrl, FW_SLICE_AUTH);
-	FW_COMN_NEXT_ID_SET(auth_cd_ctrl, next_slice);
-
-	desc->qcd_auth_sz = auth_cd_ctrl->final_sz;
-	desc->qcd_auth_offset = cd_blk_offset;
-	desc->qcd_gcm_aad_sz_offset1 =
-	    cd_blk_offset + offsetof(union hw_auth_algo_blk, max.state1) +
-	    auth_cd_ctrl->inner_state1_sz + AES_BLOCK_LEN;
-
-	return roundup(auth_cd_ctrl->inner_state1_sz +
-	    auth_cd_ctrl->inner_state2_sz +
-	    sizeof(struct hw_auth_setup), 8);
-}
-
-static void
-qat_hw17_crypto_setup_auth_cdesc(const struct qat_crypto_desc *desc,
-    const struct qat_session *qs, const struct cryptop *crp,
-    union hw_auth_algo_blk *auth)
-{
-	struct qat_sym_hash_def const *hash_def;
-	uint8_t inner_state1_sz, *state1, *state2;
-	const uint8_t *key;
-
-	auth->max.inner_setup.auth_config.config =
-	    qat_crypto_load_auth_session(desc, qs, &hash_def);
-	auth->max.inner_setup.auth_counter.counter =
-	    htobe32(hash_def->qshd_qat->qshqi_auth_counter);
-	inner_state1_sz = roundup(hash_def->qshd_qat->qshqi_state1_len, 8);
-
-	state1 = auth->max.state1;
-	state2 = auth->max.state1 + inner_state1_sz;
-	switch (qs->qs_auth_algo) {
-	case HW_AUTH_ALGO_GALOIS_128:
-		key = NULL;
-		if (crp != NULL && crp->crp_cipher_key != NULL)
-			key = crp->crp_cipher_key;
-		else if (qs->qs_cipher_key != NULL)
-			key = qs->qs_cipher_key;
-		if (key != NULL) {
-			qat_crypto_gmac_precompute(desc, key,
-			    qs->qs_cipher_klen, hash_def, state2);
-		}
-		break;
-	case HW_AUTH_ALGO_SHA1:
-	case HW_AUTH_ALGO_SHA256:
-	case HW_AUTH_ALGO_SHA384:
-	case HW_AUTH_ALGO_SHA512:
-		switch (qs->qs_auth_mode) {
-		case HW_AUTH_MODE0:
-			memcpy(state1, hash_def->qshd_alg->qshai_init_state,
-			    inner_state1_sz);
-			/* Override for mode 0 hashes. */
-			auth->max.inner_setup.auth_counter.counter = 0;
-			break;
-		case HW_AUTH_MODE1:
-			if (crp != NULL && crp->crp_auth_key != NULL)
-				key = crp->crp_auth_key;
-			else
-				key = qs->qs_auth_key;
-			if (key != NULL) {
-				qat_crypto_hmac_precompute(desc, key,
-				    qs->qs_auth_klen, hash_def, state1, state2);
-			}
-			break;
-		default:
-			panic("%s: unhandled auth mode %d", __func__,
-			    qs->qs_auth_mode);
-		}
-		break;
-	default:
-		panic("%s: unhandled auth algorithm %d", __func__,
-		    qs->qs_auth_algo);
-	}
-}
-
-static void
-qat_hw17_init_comn_req_hdr(struct qat_crypto_desc *desc,
-    struct fw_la_bulk_req *req)
-{
-	union fw_comn_req_hdr_cd_pars *cd_pars = &req->cd_pars;
-	struct fw_comn_req_hdr *req_hdr = &req->comn_hdr;
-
-	req_hdr->service_cmd_id = desc->qcd_cmd_id;
-	req_hdr->hdr_flags = FW_COMN_VALID;
-	req_hdr->service_type = FW_COMN_REQ_CPM_FW_LA;
-	req_hdr->comn_req_flags = FW_COMN_FLAGS_BUILD(
-	    COMN_CD_FLD_TYPE_64BIT_ADR, COMN_PTR_TYPE_SGL);
-	req_hdr->serv_specif_flags = 0;
-	cd_pars->s.content_desc_addr = desc->qcd_desc_paddr;
-}
-
-void
-qat_hw17_crypto_setup_desc(struct qat_crypto *qcy, struct qat_session *qs,
-    struct qat_crypto_desc *desc)
-{
-	union hw_cipher_algo_blk *cipher;
-	union hw_auth_algo_blk *auth;
-	struct fw_la_bulk_req *req_tmpl;
-	struct fw_comn_req_hdr *req_hdr;
-	uint32_t cd_blk_offset = 0;
-	int i;
-	uint8_t *cd_blk_ptr;
-
-	req_tmpl = (struct fw_la_bulk_req *)desc->qcd_req_cache;
-	req_hdr = &req_tmpl->comn_hdr;
-	cd_blk_ptr = desc->qcd_content_desc;
-
-	memset(req_tmpl, 0, sizeof(struct fw_la_bulk_req));
-	qat_hw17_init_comn_req_hdr(desc, req_tmpl);
-
-	for (i = 0; i < MAX_FW_SLICE; i++) {
-		switch (desc->qcd_slices[i]) {
-		case FW_SLICE_CIPHER:
-			cipher = (union hw_cipher_algo_blk *)(cd_blk_ptr +
-			    cd_blk_offset);
-			cd_blk_offset += qat_hw17_crypto_setup_cipher_ctrl(desc,
-			    qs, cd_blk_offset, req_tmpl,
-			    desc->qcd_slices[i + 1]);
-			qat_hw17_crypto_setup_cipher_cdesc(desc, qs, NULL,
-			    cipher);
-			break;
-		case FW_SLICE_AUTH:
-			auth = (union hw_auth_algo_blk *)(cd_blk_ptr +
-			    cd_blk_offset);
-			cd_blk_offset += qat_hw17_crypto_setup_auth_ctrl(desc,
-			    qs, cd_blk_offset, req_tmpl,
-			    desc->qcd_slices[i + 1]);
-			qat_hw17_crypto_setup_auth_cdesc(desc, qs, NULL, auth);
-			req_hdr->serv_specif_flags |= FW_LA_RET_AUTH_RES;
-			break;
-		case FW_SLICE_DRAM_WR:
-			i = MAX_FW_SLICE; /* end of chain */
-			break;
-		default:
-			MPASS(0);
-			break;
-		}
-	}
-
-	req_tmpl->cd_pars.s.content_desc_params_sz =
-	    roundup(cd_blk_offset, QAT_OPTIMAL_ALIGN) >> 3;
-	if (qs->qs_auth_algo == HW_AUTH_ALGO_GALOIS_128)
-		req_hdr->serv_specif_flags |=
-		    FW_LA_PROTO_GCM | FW_LA_GCM_IV_LEN_12_OCTETS;
-
-	bus_dmamap_sync(qs->qs_desc_mem.qdm_dma_tag,
-	    qs->qs_desc_mem.qdm_dma_map, BUS_DMASYNC_PREWRITE);
-}
-
-static void
-qat_hw17_crypto_req_setkey(const struct qat_crypto_desc *desc,
-    const struct qat_session *qs, struct qat_sym_cookie *qsc,
-    struct fw_la_bulk_req *bulk_req, const struct cryptop *crp)
-{
-	union hw_auth_algo_blk *auth;
-	union hw_cipher_algo_blk *cipher;
-	uint8_t *cdesc;
-	int i;
-
-	cdesc = qsc->qsc_content_desc;
-	memcpy(cdesc, desc->qcd_content_desc, CONTENT_DESC_MAX_SIZE);
-	for (i = 0; i < MAX_FW_SLICE; i++) {
-		switch (desc->qcd_slices[i]) {
-		case FW_SLICE_CIPHER:
-			cipher = (union hw_cipher_algo_blk *)
-			    (cdesc + desc->qcd_cipher_offset);
-			qat_hw17_crypto_setup_cipher_cdesc(desc, qs, crp,
-			    cipher);
-			break;
-		case FW_SLICE_AUTH:
-			auth = (union hw_auth_algo_blk *)
-			    (cdesc + desc->qcd_auth_offset);
-			qat_hw17_crypto_setup_auth_cdesc(desc, qs, crp, auth);
-			break;
-		case FW_SLICE_DRAM_WR:
-			i = MAX_FW_SLICE; /* end of chain */
-			break;
-		default:
-			MPASS(0);
-		}
-	}
-
-	bulk_req->cd_pars.s.content_desc_addr = qsc->qsc_content_desc_paddr;
-}
-
-void
-qat_hw17_crypto_setup_req_params(struct qat_crypto_bank *qcb __unused,
-    struct qat_session *qs, const struct qat_crypto_desc *desc,
-    struct qat_sym_cookie *qsc, struct cryptop *crp)
-{
-	struct qat_sym_bulk_cookie *qsbc;
-	struct fw_la_bulk_req *bulk_req;
-	struct fw_la_cipher_req_params *cipher_param;
-	struct fw_la_auth_req_params *auth_param;
-	bus_addr_t digest_paddr;
-	uint32_t aad_sz, *aad_szp;
-	uint8_t *req_params_ptr;
-	enum fw_la_cmd_id cmd_id = desc->qcd_cmd_id;
-
-	qsbc = &qsc->qsc_bulk_cookie;
-	bulk_req = (struct fw_la_bulk_req *)qsbc->qsbc_msg;
-
-	memcpy(bulk_req, desc->qcd_req_cache, sizeof(struct fw_la_bulk_req));
-	bulk_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)qsc;
-	bulk_req->comn_mid.src_data_addr = qsc->qsc_buffer_list_desc_paddr;
-	if (CRYPTO_HAS_OUTPUT_BUFFER(crp)) {
-		bulk_req->comn_mid.dest_data_addr =
-		    qsc->qsc_obuffer_list_desc_paddr;
-	} else {
-		bulk_req->comn_mid.dest_data_addr =
-		    qsc->qsc_buffer_list_desc_paddr;
-	}
-	if (__predict_false(crp->crp_cipher_key != NULL ||
-	    crp->crp_auth_key != NULL))
-		qat_hw17_crypto_req_setkey(desc, qs, qsc, bulk_req, crp);
-
-	digest_paddr = 0;
-	if (desc->qcd_auth_sz != 0)
-		digest_paddr = qsc->qsc_auth_res_paddr;
-
-	req_params_ptr = (uint8_t *)&bulk_req->serv_specif_rqpars;
-	cipher_param = (struct fw_la_cipher_req_params *)req_params_ptr;
-	auth_param = (struct fw_la_auth_req_params *)
-	    (req_params_ptr + sizeof(struct fw_la_cipher_req_params));
-
-	cipher_param->u.s.cipher_IV_ptr = qsc->qsc_iv_buf_paddr;
-
-	/*
-	 * The SG list layout is a bit different for GCM and GMAC, it's simpler
-	 * to handle those cases separately.
-	 */
-	if (qs->qs_auth_algo == HW_AUTH_ALGO_GALOIS_128) {
-		if (cmd_id != FW_LA_CMD_AUTH) {
-			/*
-			 * Don't fill out the cipher block if we're doing GMAC
-			 * only.
-			 */
-			cipher_param->cipher_offset = 0;
-			cipher_param->cipher_length = crp->crp_payload_length;
-		}
-		auth_param->auth_off = 0;
-		auth_param->auth_len = crp->crp_payload_length;
-		auth_param->auth_res_addr = digest_paddr;
-		auth_param->auth_res_sz = desc->qcd_auth_sz;
-		auth_param->u1.aad_adr =
-		    crp->crp_aad_length > 0 ? qsc->qsc_gcm_aad_paddr : 0;
-		auth_param->u2.aad_sz =
-		    roundup2(crp->crp_aad_length, QAT_AES_GCM_AAD_ALIGN);
-		auth_param->hash_state_sz = auth_param->u2.aad_sz >> 3;
-
-		/*
-		 * Update the hash state block if necessary.  This only occurs
-		 * when the AAD length changes between requests in a session and
-		 * is synchronized by qat_process().
-		 */
-		aad_sz = htobe32(crp->crp_aad_length);
-		aad_szp = (uint32_t *)(
-		    __DECONST(uint8_t *, desc->qcd_content_desc) +
-		    desc->qcd_gcm_aad_sz_offset1);
-		if (__predict_false(*aad_szp != aad_sz)) {
-			*aad_szp = aad_sz;
-			bus_dmamap_sync(qs->qs_desc_mem.qdm_dma_tag,
-			    qs->qs_desc_mem.qdm_dma_map,
-			    BUS_DMASYNC_PREWRITE);
-		}
-	} else {
-		if (cmd_id != FW_LA_CMD_AUTH) {
-			if (crp->crp_aad_length == 0) {
-				cipher_param->cipher_offset = 0;
-			} else if (crp->crp_aad == NULL) {
-				cipher_param->cipher_offset =
-				    crp->crp_payload_start - crp->crp_aad_start;
-			} else {
-				cipher_param->cipher_offset =
-				    crp->crp_aad_length;
-			}
-			cipher_param->cipher_length = crp->crp_payload_length;
-		}
-		if (cmd_id != FW_LA_CMD_CIPHER) {
-			auth_param->auth_off = 0;
-			auth_param->auth_len =
-			    crp->crp_payload_length + crp->crp_aad_length;
-			auth_param->auth_res_addr = digest_paddr;
-			auth_param->auth_res_sz = desc->qcd_auth_sz;
-			auth_param->u1.aad_adr = 0;
-			auth_param->u2.aad_sz = 0;
-			auth_param->hash_state_sz = 0;
-		}
-	}
-}
diff --git a/sys/dev/qat/qat_hw17reg.h b/sys/dev/qat/qat_hw17reg.h
deleted file mode 100644
index 6655b905dde0..000000000000
--- a/sys/dev/qat/qat_hw17reg.h
+++ /dev/null
@@ -1,2460 +0,0 @@
-/* SPDX-License-Identifier: BSD-2-Clause-NetBSD AND BSD-3-Clause */
-/*	$NetBSD: qat_hw17reg.h,v 1.1 2019/11/20 09:37:46 hikaru Exp $	*/
-
-/*
- * Copyright (c) 2019 Internet Initiative Japan, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-/*
- *   Copyright(c) 2014 Intel Corporation.
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions
- *   are met:
- *
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in
- *       the documentation and/or other materials provided with the
- *       distribution.
- *     * Neither the name of Intel Corporation nor the names of its
- *       contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/* $FreeBSD$ */
-
-#ifndef _DEV_PCI_QAT_HW17REG_H_
-#define _DEV_PCI_QAT_HW17REG_H_
-
-/* Default message size in bytes */
-#define FW_REQ_DEFAULT_SZ_HW17		128
-#define FW_RESP_DEFAULT_SZ_HW17		32
-
-/* -------------------------------------------------------------------------- */
-/* accel */
-
-enum fw_init_admin_cmd_id {
-	FW_INIT_ME = 0,
-	FW_TRNG_ENABLE = 1,
-	FW_TRNG_DISABLE = 2,
-	FW_CONSTANTS_CFG = 3,
-	FW_STATUS_GET = 4,
-	FW_COUNTERS_GET = 5,
-	FW_LOOPBACK = 6,
-	FW_HEARTBEAT_SYNC = 7,
-	FW_HEARTBEAT_GET = 8,
-	FW_COMP_CAPABILITY_GET = 9,
-	FW_CRYPTO_CAPABILITY_GET = 10,
-	FW_HEARTBEAT_TIMER_SET = 13,
-};
-
-enum fw_init_admin_resp_status {
-	FW_INIT_RESP_STATUS_SUCCESS = 0,
-	FW_INIT_RESP_STATUS_FAIL = 1,
-	FW_INIT_RESP_STATUS_UNSUPPORTED = 4
-};
-
-struct fw_init_admin_req {
-	uint16_t init_cfg_sz;
-	uint8_t resrvd1;
-	uint8_t init_admin_cmd_id;
-	uint32_t resrvd2;
-	uint64_t opaque_data;
-	uint64_t init_cfg_ptr;
-
-	union {
-		struct {
-			uint16_t ibuf_size_in_kb;
-			uint16_t resrvd3;
-		};
-		uint32_t heartbeat_ticks;
-	};
-
-	uint32_t resrvd4;
-};
-
-struct fw_init_admin_resp_hdr {
-	uint8_t flags;
-	uint8_t resrvd1;
-	uint8_t status;
-	uint8_t init_admin_cmd_id;
-};
-
-enum fw_init_admin_init_flag {
-	FW_INIT_FLAG_PKE_DISABLED = 0
-};
-
-struct fw_init_admin_fw_capability_resp_hdr {
-	uint16_t     reserved;
-	uint8_t     status;
-	uint8_t     init_admin_cmd_id;
-};
-
-struct fw_init_admin_capability_resp {
-	struct fw_init_admin_fw_capability_resp_hdr init_resp_hdr;
-	uint32_t extended_features;
-	uint64_t opaque_data;
-	union {
-		struct {
-			uint16_t    compression_algos;
-			uint16_t    checksum_algos;
-			uint32_t    deflate_capabilities;
-			uint32_t    resrvd1;
-			uint32_t    lzs_capabilities;
-		} compression;
-		struct {
-			uint32_t    cipher_algos;
-			uint32_t    hash_algos;
-			uint16_t    keygen_algos;
-			uint16_t    other;
-			uint16_t    public_key_algos;
-			uint16_t    prime_algos;
-		} crypto;
-	};
-};
-
-struct fw_init_admin_resp_pars {
-	union {
-		uint32_t resrvd1[4];
-		struct {
-			uint32_t version_patch_num;
-			uint8_t context_id;
-			uint8_t ae_id;
-			uint16_t resrvd1;
-			uint64_t resrvd2;
-		} s1;
-		struct {
-			uint64_t req_rec_count;
-			uint64_t resp_sent_count;
-		} s2;
-	} u;
-};
-
-struct fw_init_admin_hb_cnt {
-	uint16_t resp_heartbeat_cnt;
-	uint16_t req_heartbeat_cnt;
-};
-
-#define QAT_NUM_THREADS 8
-
-struct fw_init_admin_hb_stats {
-	struct fw_init_admin_hb_cnt stats[QAT_NUM_THREADS];
-};
-
-struct fw_init_admin_resp {
-	struct fw_init_admin_resp_hdr init_resp_hdr;
-	union {
-		uint32_t resrvd2;
-		struct {
-			uint16_t version_minor_num;
-			uint16_t version_major_num;
-		} s;
-	} u;
-	uint64_t opaque_data;
-	struct fw_init_admin_resp_pars init_resp_pars;
-};
-
-#define FW_COMN_HEARTBEAT_OK 0
-#define FW_COMN_HEARTBEAT_BLOCKED 1
-#define FW_COMN_HEARTBEAT_FLAG_BITPOS 0
-#define FW_COMN_HEARTBEAT_FLAG_MASK 0x1
-#define FW_COMN_STATUS_RESRVD_FLD_MASK 0xFE
-#define FW_COMN_HEARTBEAT_HDR_FLAG_GET(hdr_t) \
-	FW_COMN_HEARTBEAT_FLAG_GET(hdr_t.flags)
-
-#define FW_COMN_HEARTBEAT_HDR_FLAG_SET(hdr_t, val) \
-	FW_COMN_HEARTBEAT_FLAG_SET(hdr_t, val)
-
-#define FW_COMN_HEARTBEAT_FLAG_GET(flags) \
-	QAT_FIELD_GET(flags, \
-		 FW_COMN_HEARTBEAT_FLAG_BITPOS, \
-		 FW_COMN_HEARTBEAT_FLAG_MASK)
-
-/* -------------------------------------------------------------------------- */
-
-/* Big assumptions that both bitpos and mask are constants */
-#define FIELD_SET(flags, val, bitpos, mask)                                \
-    (flags) =                                                                  \
-        (((flags) & (~((mask) << (bitpos)))) | (((val) & (mask)) << (bitpos)))
-
-#define FIELD_GET(flags, bitpos, mask) (((flags) >> (bitpos)) & (mask))
-
-#define FLAG_SET(flags, bitpos) (flags) = ((flags) | (1 << (bitpos)))
-
-#define FLAG_CLEAR(flags, bitpos) (flags) = ((flags) & (~(1 << (bitpos))))
-
-#define FLAG_GET(flags, bitpos) (((flags) >> (bitpos)) & 1)
-
-/* Default request and response ring size in bytes  */
-#define FW_REQ_DEFAULT_SZ 128
-#define FW_RESP_DEFAULT_SZ 32
-
-#define FW_COMN_ONE_BYTE_SHIFT 8
-#define FW_COMN_SINGLE_BYTE_MASK 0xFF
-
-/* Common Request - Block sizes definitions in multiples of individual long
- * words  */
-#define FW_NUM_LONGWORDS_1 1
-#define FW_NUM_LONGWORDS_2 2
-#define FW_NUM_LONGWORDS_3 3
-#define FW_NUM_LONGWORDS_4 4
-#define FW_NUM_LONGWORDS_5 5
-#define FW_NUM_LONGWORDS_6 6
-#define FW_NUM_LONGWORDS_7 7
-#define FW_NUM_LONGWORDS_10 10
-#define FW_NUM_LONGWORDS_13 13
-
-/* Definition of the associated service Id for NULL service type.
-   Note: the response is expected to use FW_COMN_RESP_SERV_CPM_FW  */
-#define FW_NULL_REQ_SERV_ID 1
-
-/*
- * Definition of the firmware interface service users, for
- * responses.
- * Enumeration which is used to indicate the ids of the services
- * for responses using the external firmware interfaces.
- */
-
-enum fw_comn_resp_serv_id {
-	FW_COMN_RESP_SERV_NULL,     /* NULL service id type */
-	FW_COMN_RESP_SERV_CPM_FW,   /* CPM FW Service ID */
-	FW_COMN_RESP_SERV_DELIMITER /* Delimiter service id type */
-};
-
-/*
- * Definition of the request types
- * Enumeration which is used to indicate the ids of the request
- * types used in each of the external firmware interfaces
- */
-
-enum fw_comn_request_id {
-	FW_COMN_REQ_NULL = 0,        /* NULL request type */
-	FW_COMN_REQ_CPM_FW_PKE = 3,  /* CPM FW PKE Request */
-	FW_COMN_REQ_CPM_FW_LA = 4,   /* CPM FW Lookaside Request */
-	FW_COMN_REQ_CPM_FW_DMA = 7,  /* CPM FW DMA Request */
-	FW_COMN_REQ_CPM_FW_COMP = 9, /* CPM FW Compression Request */
-	FW_COMN_REQ_DELIMITER        /* End delimiter */
-
-};
-
-/*
- * Definition of the common QAT FW request content descriptor field -
- * points to the content descriptor parameters or itself contains service-
- * specific data. Also specifies content descriptor parameter size.
- * Contains reserved fields.
- * Common section of the request used across all of the services exposed
- * by the QAT FW. Each of the services inherit these common fields
- */
-union fw_comn_req_hdr_cd_pars {
-	/* LWs 2-5 */
-	struct
-	{
-		uint64_t content_desc_addr;
-		/* Address of the content descriptor */
-
-		uint16_t content_desc_resrvd1;
-		/* Content descriptor reserved field */
-
-		uint8_t content_desc_params_sz;
-		/* Size of the content descriptor parameters in quad words. These
-		 * parameters describe the session setup configuration info for the
-		 * slices that this request relies upon i.e. the configuration word and
-		 * cipher key needed by the cipher slice if there is a request for
-		 * cipher processing. */
-
-		uint8_t content_desc_hdr_resrvd2;
-		/* Content descriptor reserved field */
-
-		uint32_t content_desc_resrvd3;
-		/* Content descriptor reserved field */
-	} s;
-
-	struct
-	{
-		uint32_t serv_specif_fields[FW_NUM_LONGWORDS_4];
-
-	} s1;
-
-};
-
-/*
- * Definition of the common QAT FW request middle block.
- * Common section of the request used across all of the services exposed
- * by the QAT FW. Each of the services inherit these common fields
- */
-struct fw_comn_req_mid
-{
-	/* LWs 6-13 */
-	uint64_t opaque_data;
-	/* Opaque data passed unmodified from the request to response messages by
-	 * firmware (fw) */
-
-	uint64_t src_data_addr;
-	/* Generic definition of the source data supplied to the QAT AE. The
-	 * common flags are used to further describe the attributes of this
-	 * field */
-
-	uint64_t dest_data_addr;
-	/* Generic definition of the destination data supplied to the QAT AE. The
-	 * common flags are used to further describe the attributes of this
-	 * field */
-
-	uint32_t src_length;
-	/* Length of source flat buffer incase src buffer
-	 * type is flat */
-
-	uint32_t dst_length;
-	/* Length of source flat buffer incase dst buffer
-	 * type is flat */
-
-};
-
-/*
- * Definition of the common QAT FW request content descriptor control
- * block.
- *
- * Service specific section of the request used across all of the services
- * exposed by the QAT FW. Each of the services populates this block
- * uniquely. Refer to the service-specific header structures e.g.
- * 'fw_cipher_hdr_s' (for Cipher) etc.
- */
-struct fw_comn_req_cd_ctrl
-{
-	/* LWs 27-31 */
-	uint32_t content_desc_ctrl_lw[FW_NUM_LONGWORDS_5];
-
-};
-
-/*
- * Definition of the common QAT FW request header.
- * Common section of the request used across all of the services exposed
- * by the QAT FW. Each of the services inherit these common fields. The
- * reserved field of 7 bits and the service command Id field are all
- * service-specific fields, along with the service specific flags.
- */
-struct fw_comn_req_hdr
-{
-	/* LW0 */
-	uint8_t resrvd1;
-	/* reserved field */
-
-	uint8_t service_cmd_id;
-	/* Service Command Id  - this field is service-specific
-	 * Please use service-specific command Id here e.g.Crypto Command Id
-	 * or Compression Command Id etc. */
-
-	uint8_t service_type;
-	/* Service type */
-
-	uint8_t hdr_flags;
-	/* This represents a flags field for the Service Request.
-	 * The most significant bit is the 'valid' flag and the only
-	 * one used. All remaining bit positions are unused and
-	 * are therefore reserved and need to be set to 0. */
-
-	/* LW1 */
-	uint16_t serv_specif_flags;
-	/* Common Request service-specific flags
-	 * e.g. Symmetric Crypto Command Flags */
-
-	uint16_t comn_req_flags;
-	/* Common Request Flags consisting of
-	 * - 14 reserved bits,
-	 * - 1 Content Descriptor field type bit and
-	 * - 1 Source/destination pointer type bit */
-
-};
-
-/*
- * Definition of the common QAT FW request parameter field.
- *
- * Service specific section of the request used across all of the services
- * exposed by the QAT FW. Each of the services populates this block
- * uniquely. Refer to service-specific header structures e.g.
- * 'fw_comn_req_cipher_rqpars_s' (for Cipher) etc.
- *
- */
-struct fw_comn_req_rqpars
-{
-	/* LWs 14-26 */
-	uint32_t serv_specif_rqpars_lw[FW_NUM_LONGWORDS_13];
-
-};
-
-/*
- * Definition of the common request structure with service specific
- * fields
- * This is a definition of the full qat request structure used by all
- * services. Each service is free to use the service fields in its own
- * way. This struct is useful as a message passing argument before the
- * service contained within the request is determined.
- */
-struct fw_comn_req
-{
-	/* LWs 0-1 */
-	struct fw_comn_req_hdr comn_hdr;
-	/* Common request header */
-
-	/* LWs 2-5 */
-	union fw_comn_req_hdr_cd_pars cd_pars;
-	/* Common Request content descriptor field which points either to a
-	 * content descriptor
-	 * parameter block or contains the service-specific data itself. */
-
-	/* LWs 6-13 */
-	struct fw_comn_req_mid comn_mid;
-	/* Common request middle section */
-
-	/* LWs 14-26 */
-	struct fw_comn_req_rqpars serv_specif_rqpars;
-	/* Common request service-specific parameter field */
-
-	/* LWs 27-31 */
-	struct fw_comn_req_cd_ctrl cd_ctrl;
-	/* Common request content descriptor control block -
-	 * this field is service-specific */
-
-};
-
-/*
- * Error code field
- *
- * Overloaded field with 8 bit common error field or two
- * 8 bit compression error fields for compression and translator slices
- */
-union fw_comn_error {
-	struct
-	{
-		uint8_t resrvd;
-		/* 8 bit reserved field */
-
-		uint8_t comn_err_code;
-		/* 8 bit common error code */
-
-	} s;
-	/* Structure which is used for non-compression responses */
-
-	struct
-	{
-		uint8_t xlat_err_code;
-		/* 8 bit translator error field */
-
-		uint8_t cmp_err_code;
-		/* 8 bit compression error field */
-
-	} s1;
-	/* Structure which is used for compression responses */
-
-};
-
-/*
- * Definition of the common QAT FW response header.
- * This section of the response is common across all of the services
- * that generate a firmware interface response
- */
-struct fw_comn_resp_hdr
-{
-	/* LW0 */
-	uint8_t resrvd1;
-	/* Reserved field - this field is service-specific -
-	 * Note: The Response Destination Id has been removed
-	 * from first QWord */
-
-	uint8_t service_id;
-	/* Service Id returned by service block */
-
-	uint8_t response_type;
-	/* Response type - copied from the request to
-	 * the response message */
-
-	uint8_t hdr_flags;
-	/* This represents a flags field for the Response.
-	 * Bit<7> = 'valid' flag
-	 * Bit<6> = 'CNV' flag indicating that CNV was executed
-	 *          on the current request
-	 * Bit<5> = 'CNVNR' flag indicating that a recovery happened
-	 *          on the current request following a CNV error
-	 * All remaining bits are unused and are therefore reserved.
-	 * They must to be set to 0.
-	 */
-
-	/* LW 1 */
-	union fw_comn_error comn_error;
-	/* This field is overloaded to allow for one 8 bit common error field
-	 *   or two 8 bit error fields from compression and translator  */
-
-	uint8_t comn_status;
-	/* Status field which specifies which slice(s) report an error */
-
-	uint8_t cmd_id;
-	/* Command Id - passed from the request to the response message */
-
-};
-
-/*
- * Definition of the common response structure with service specific
- * fields
- * This is a definition of the full qat response structure used by all
- * services.
- */
-struct fw_comn_resp
-{
-	/* LWs 0-1 */
-	struct fw_comn_resp_hdr comn_hdr;
-	/* Common header fields */
-
-	/* LWs 2-3 */
-	uint64_t opaque_data;
-	/* Opaque data passed from the request to the response message */
-
-	/* LWs 4-7 */
-	uint32_t resrvd[FW_NUM_LONGWORDS_4];
-	/* Reserved */
-
-};
-
-/*  Common QAT FW request header - structure of LW0
- *  + ===== + ---- + ----------- + ----------- + ----------- + ----------- +
- *  |  Bit  |  31  |  30 - 24    |  21 - 16    |  15 - 8     |  7 - 0      |
- *  + ===== + ---- + ----------- + ----------- + ----------- + ----------- +
- *  | Flags |  V   |   Reserved  | Serv Type   | Serv Cmd Id |  Reserved   |
- *  + ===== + ---- + ----------- + ----------- + ----------- + ----------- +
- */
-
-#define FW_COMN_VALID		__BIT(7)
-
-/*  Common QAT FW response header - structure of LW0
- *  + ===== + --- + --- + ----- + ----- + --------- + ----------- + ----- +
- *  |  Bit  | 31  | 30  |   29  | 28-24 |  21 - 16  |  15 - 8     |  7-0  |
- *  + ===== + --- + ----+ ----- + ----- + --------- + ----------- + ----- +
- *  | Flags |  V  | CNV | CNVNR | Rsvd  | Serv Type | Serv Cmd Id |  Rsvd |
- *  + ===== + --- + --- + ----- + ----- + --------- + ----------- + ----- +  */
-/* Macros defining the bit position and mask of 'CNV' flag
- * within the hdr_flags field of LW0 (service response only)  */
-#define FW_COMN_CNV_FLAG_BITPOS 6
-#define FW_COMN_CNV_FLAG_MASK 0x1
-
-/* Macros defining the bit position and mask of CNVNR flag
- * within the hdr_flags field of LW0 (service response only)  */
-#define FW_COMN_CNVNR_FLAG_BITPOS 5
-#define FW_COMN_CNVNR_FLAG_MASK 0x1
-
-/*
- * Macro for extraction of Service Type Field
- *
- * struct fw_comn_req_hdr  Structure 'fw_comn_req_hdr_t'
- *                 to extract the Service Type Field
- */
-#define FW_COMN_OV_SRV_TYPE_GET(fw_comn_req_hdr_t)	\
-	fw_comn_req_hdr_t.service_type
-
-/*
- * Macro for setting of Service Type Field
- *
- * 'fw_comn_req_hdr_t' structure to set the Service
- *                  Type Field
- * val    Value of the Service Type Field
- */
-#define FW_COMN_OV_SRV_TYPE_SET(fw_comn_req_hdr_t, val)	\
-	fw_comn_req_hdr_t.service_type = val
-
-/*
- * Macro for extraction of Service Command Id Field
- *
- * struct fw_comn_req_hdr  Structure 'fw_comn_req_hdr_t'
- *                 to extract the Service Command Id Field
- */
-#define FW_COMN_OV_SRV_CMD_ID_GET(fw_comn_req_hdr_t)	\
-	fw_comn_req_hdr_t.service_cmd_id
-
-/*
- * Macro for setting of Service Command Id Field
- *
- * 'fw_comn_req_hdr_t' structure to set the
- *                  Service Command Id Field
- * val    Value of the Service Command Id Field
- */
-#define FW_COMN_OV_SRV_CMD_ID_SET(fw_comn_req_hdr_t, val)	\
-	fw_comn_req_hdr_t.service_cmd_id = val
-
-/*
- * Extract the valid flag from the request or response's header flags.
- *
- * hdr_t  Request or Response 'hdr_t' structure to extract the valid bit
- *  from the  'hdr_flags' field.
- */
-#define FW_COMN_HDR_VALID_FLAG_GET(hdr_t)	\
-	FW_COMN_VALID_FLAG_GET(hdr_t.hdr_flags)
-
-/*
- * Extract the CNVNR flag from the header flags in the response only.
- *
- * hdr_t  Response 'hdr_t' structure to extract the CNVNR bit
- *  from the  'hdr_flags' field.
- */
-#define FW_COMN_HDR_CNVNR_FLAG_GET(hdr_flags)	\
-	FIELD_GET(hdr_flags,	\
-			      FW_COMN_CNVNR_FLAG_BITPOS,	\
-			      FW_COMN_CNVNR_FLAG_MASK)
-
-/*
- * Extract the CNV flag from the header flags in the response only.
- *
- * hdr_t  Response 'hdr_t' structure to extract the CNV bit
- *  from the  'hdr_flags' field.
- */
-#define FW_COMN_HDR_CNV_FLAG_GET(hdr_flags)	\
-	FIELD_GET(hdr_flags,	\
-			      FW_COMN_CNV_FLAG_BITPOS,	\
-			      FW_COMN_CNV_FLAG_MASK)
-
-/*
- * Set the valid bit in the request's header flags.
- *
- * hdr_t  Request or Response 'hdr_t' structure to set the valid bit
- * val    Value of the valid bit flag.
- */
-#define FW_COMN_HDR_VALID_FLAG_SET(hdr_t, val)	\
-	FW_COMN_VALID_FLAG_SET(hdr_t, val)
-
-/*
- * Common macro to extract the valid flag from the header flags field
- * within the header structure (request or response).
- *
- * hdr_t  Structure (request or response) to extract the
- *  valid bit from the 'hdr_flags' field.
- */
-#define FW_COMN_VALID_FLAG_GET(hdr_flags)	\
-	FIELD_GET(hdr_flags,	\
-			      FW_COMN_VALID_FLAG_BITPOS,	\
-			      FW_COMN_VALID_FLAG_MASK)
-
-/*
- * Common macro to extract the remaining reserved flags from the header
- * flags field within the header structure (request or response).
- *
- * hdr_t  Structure (request or response) to extract the
- *  remaining bits from the 'hdr_flags' field (excluding the
- *  valid flag).
- */
-#define FW_COMN_HDR_RESRVD_FLD_GET(hdr_flags)	\
-	(hdr_flags & FW_COMN_HDR_RESRVD_FLD_MASK)
-
-/*
- * Common macro to set the valid bit in the header flags field within
- * the header structure (request or response).
- *
- * hdr_t  Structure (request or response) containing the header
- *  flags field, to allow the valid bit to be set.
- * val    Value of the valid bit flag.
- */
-#define FW_COMN_VALID_FLAG_SET(hdr_t, val)	\
-	FIELD_SET((hdr_t.hdr_flags),	\
-			      (val),	\
-			      FW_COMN_VALID_FLAG_BITPOS,	\
-			      FW_COMN_VALID_FLAG_MASK)
-
-/*
- * Macro that must be used when building the common header flags.
- * Note that all bits reserved field bits 0-6 (LW0) need to be forced to 0.
- *
- * ptr   Value of the valid flag
- */
-
-#define FW_COMN_HDR_FLAGS_BUILD(valid)	\
-	(((valid)&FW_COMN_VALID_FLAG_MASK)	\
-	 << FW_COMN_VALID_FLAG_BITPOS)
-
-/*
- *  Common Request Flags Definition
- *  The bit offsets below are within the flags field. These are NOT relative to
- *  the memory word. Unused fields e.g. reserved bits, must be zeroed.
- *
- *  + ===== + ------ + --- + --- + --- + --- + --- + --- + --- + --- +
- *  | Bits [15:8]    |  15 |  14 |  13 |  12 |  11 |  10 |  9  |  8  |
- *  + ===== + ------ + --- + --- + --- + --- + --- + --- + --- + --- +
- *  | Flags[15:8]    | Rsv | Rsv | Rsv | Rsv | Rsv | Rsv | Rsv | Rsv |
- *  + ===== + ------ + --- + --- + --- + --- + --- + --- + --- + --- +
- *  | Bits  [7:0]    |  7  |  6  |  5  |  4  |  3  |  2  |  1  |  0  |
- *  + ===== + ------ + --- + --- + --- + --- + --- + --- + --- + --- +
- *  | Flags [7:0]    | Rsv | Rsv | Rsv | Rsv | Rsv | BnP | Cdt | Ptr |
- *  + ===== + ------ + --- + --- + --- + --- + --- + --- + --- + --- +
- */
-
-#define COMN_PTR_TYPE_BITPOS 0
-/* Common Request Flags - Starting bit position indicating
- * Src&Dst Buffer Pointer type   */
-
-#define COMN_PTR_TYPE_MASK 0x1
-/* Common Request Flags - One bit mask used to determine
- * Src&Dst Buffer Pointer type  */
-
-#define COMN_CD_FLD_TYPE_BITPOS 1
-/* Common Request Flags - Starting bit position indicating
- * CD Field type   */
-
-#define COMN_CD_FLD_TYPE_MASK 0x1
-/* Common Request Flags - One bit mask used to determine
- * CD Field type  */
-
-#define COMN_BNP_ENABLED_BITPOS 2
-/* Common Request Flags - Starting bit position indicating
- * the source buffer contains batch of requests. if this
- * bit is set, source buffer is type of Batch And Pack OpData List
- * and the Ptr Type Bit only applies to Destination buffer.  */
-
-#define COMN_BNP_ENABLED_MASK 0x1
-/* Batch And Pack Enabled Flag Mask - One bit mask used to determine
- * the source buffer is in Batch and Pack OpData Link List Mode.  */
-
-/* ========================================================================= */
-/*                                       Pointer Type Flag definitions       */
-/* ========================================================================= */
-#define COMN_PTR_TYPE_FLAT 0x0
-/* Constant value indicating Src&Dst Buffer Pointer type is flat
- * If Batch and Pack mode is enabled, only applies to Destination buffer. */
-
-#define COMN_PTR_TYPE_SGL 0x1
-/* Constant value indicating Src&Dst Buffer Pointer type is SGL type
- * If Batch and Pack mode is enabled, only applies to Destination buffer. */
-
-#define COMN_PTR_TYPE_BATCH 0x2
-/* Constant value indicating Src is a batch request
- * and Dst Buffer Pointer type is SGL type  */
-
-/* ========================================================================= */
-/*                                       CD Field Flag definitions           */
-/* ========================================================================= */
-#define COMN_CD_FLD_TYPE_64BIT_ADR 0x0
-/* Constant value indicating CD Field contains 64-bit address  */
-
-#define COMN_CD_FLD_TYPE_16BYTE_DATA 0x1
-/* Constant value indicating CD Field contains 16 bytes of setup data  */
-
-/* ========================================================================= */
-/*                       Batch And Pack Enable/Disable Definitions           */
-/* ========================================================================= */
-#define COMN_BNP_ENABLED 0x1
-/* Constant value indicating Source buffer will point to Batch And Pack OpData
- * List  */
-
-#define COMN_BNP_DISABLED 0x0
-/* Constant value indicating Source buffer will point to Batch And Pack OpData
- * List  */
-
-/*
- * Macro that must be used when building the common request flags (for all
- * requests but comp BnP).
- * Note that all bits reserved field bits 2-15 (LW1) need to be forced to 0.
- *
- * ptr   Value of the pointer type flag
- * cdt   Value of the cd field type flag
-*/
-#define FW_COMN_FLAGS_BUILD(cdt, ptr)	\
-	((((cdt)&COMN_CD_FLD_TYPE_MASK) << COMN_CD_FLD_TYPE_BITPOS) |	\
-	 (((ptr)&COMN_PTR_TYPE_MASK) << COMN_PTR_TYPE_BITPOS))
-
-/*
- * Macro that must be used when building the common request flags for comp
- * BnP service.
- * Note that all bits reserved field bits 3-15 (LW1) need to be forced to 0.
- *
- * ptr   Value of the pointer type flag
- * cdt   Value of the cd field type flag
- * bnp   Value of the bnp enabled flag
- */
-#define FW_COMN_FLAGS_BUILD_BNP(cdt, ptr, bnp)	\
-	((((cdt)&COMN_CD_FLD_TYPE_MASK) << COMN_CD_FLD_TYPE_BITPOS) |	\
-	 (((ptr)&COMN_PTR_TYPE_MASK) << COMN_PTR_TYPE_BITPOS) |	\
-	 (((bnp)&COMN_BNP_ENABLED_MASK) << COMN_BNP_ENABLED_BITPOS))
-
-/*
- * Macro for extraction of the pointer type bit from the common flags
- *
- * flags      Flags to extract the pointer type bit from
- */
-#define FW_COMN_PTR_TYPE_GET(flags)	\
-	FIELD_GET(flags, COMN_PTR_TYPE_BITPOS, COMN_PTR_TYPE_MASK)
-
-/*
- * Macro for extraction of the cd field type bit from the common flags
- *
- * flags      Flags to extract the cd field type type bit from
- */
-#define FW_COMN_CD_FLD_TYPE_GET(flags)	\
-	FIELD_GET(flags, COMN_CD_FLD_TYPE_BITPOS, COMN_CD_FLD_TYPE_MASK)
-
-/*
- * Macro for extraction of the bnp field type bit from the common flags
- *
- * flags      Flags to extract the bnp field type type bit from
- *
- */
-#define FW_COMN_BNP_ENABLED_GET(flags)	\
-	FIELD_GET(flags, COMN_BNP_ENABLED_BITPOS, COMN_BNP_ENABLED_MASK)
-
-/*
- * Macro for setting the pointer type bit in the common flags
- *
- * flags      Flags in which Pointer Type bit will be set
- * val        Value of the bit to be set in flags
- *
- */
-#define FW_COMN_PTR_TYPE_SET(flags, val)	\
-	FIELD_SET(flags, val, COMN_PTR_TYPE_BITPOS, COMN_PTR_TYPE_MASK)
-
-/*
- * Macro for setting the cd field type bit in the common flags
- *
- * flags      Flags in which Cd Field Type bit will be set
- * val        Value of the bit to be set in flags
- *
- */
-#define FW_COMN_CD_FLD_TYPE_SET(flags, val)	\
-	FIELD_SET(	\
-		flags, val, COMN_CD_FLD_TYPE_BITPOS, COMN_CD_FLD_TYPE_MASK)
-
-/*
- * Macro for setting the bnp field type bit in the common flags
- *
- * flags      Flags in which Bnp Field Type bit will be set
- * val        Value of the bit to be set in flags
- *
- */
-#define FW_COMN_BNP_ENABLE_SET(flags, val)	\
-	FIELD_SET(	\
-		flags, val, COMN_BNP_ENABLED_BITPOS, COMN_BNP_ENABLED_MASK)
-
-/*
- * Macros using the bit position and mask to set/extract the next
- * and current id nibbles within the next_curr_id field of the
- * content descriptor header block. Note that these are defined
- * in the common header file, as they are used by compression, cipher
- * and authentication.
- *
- * cd_ctrl_hdr_t      Content descriptor control block header pointer.
- * val                Value of the field being set.
- */
-#define FW_COMN_NEXT_ID_BITPOS 4
-#define FW_COMN_NEXT_ID_MASK 0xF0
-#define FW_COMN_CURR_ID_BITPOS 0
-#define FW_COMN_CURR_ID_MASK 0x0F
-
-#define FW_COMN_NEXT_ID_GET(cd_ctrl_hdr_t)	\
-	((((cd_ctrl_hdr_t)->next_curr_id) & FW_COMN_NEXT_ID_MASK) >>	\
-	 (FW_COMN_NEXT_ID_BITPOS))
-
-#define FW_COMN_NEXT_ID_SET(cd_ctrl_hdr_t, val)	\
-	((cd_ctrl_hdr_t)->next_curr_id) =	\
-		((((cd_ctrl_hdr_t)->next_curr_id) & FW_COMN_CURR_ID_MASK) |	\
-		 ((val << FW_COMN_NEXT_ID_BITPOS) &	\
-		  FW_COMN_NEXT_ID_MASK))
-
-#define FW_COMN_CURR_ID_GET(cd_ctrl_hdr_t)	\
-	(((cd_ctrl_hdr_t)->next_curr_id) & FW_COMN_CURR_ID_MASK)
-
-#define FW_COMN_CURR_ID_SET(cd_ctrl_hdr_t, val)	\
-	((cd_ctrl_hdr_t)->next_curr_id) =	\
-		((((cd_ctrl_hdr_t)->next_curr_id) & FW_COMN_NEXT_ID_MASK) |	\
-		 ((val)&FW_COMN_CURR_ID_MASK))
-
-/*
- *  Common Status Field Definition  The bit offsets below are within the COMMON
- *  RESPONSE status field, assumed to be 8 bits wide. In the case of the PKE
- *  response (which follows the CPM 1.5 message format), the status field is 16
- *  bits wide.
- *  The status flags are contained within the most significant byte and align
- *  with the diagram below. Please therefore refer to the service-specific PKE
- *  header file for the appropriate macro definition to extract the PKE status
- *  flag from the PKE response, which assumes that a word is passed to the
- *  macro.
- *  + ===== + ------ + --- + --- + ---- + ---- + -------- + ---- + ---------- +
- *  |  Bit  |   7    |  6  |  5  |  4   |  3   |    2     |   1  |      0     |
- *  + ===== + ------ + --- + --- + ---- + ---- + -------- + ---- + ---------- +
- *  | Flags | Crypto | Pke | Cmp | Xlat | EOLB | UnSupReq | Rsvd | XltWaApply |
- *  + ===== + ------ + --- + --- + ---- + ---- + -------- + ---- + ---------- +
- * Note:
- * For the service specific status bit definitions refer to service header files
- * Eg. Crypto Status bit refers to Symmetric Crypto, Key Generation, and NRBG
- * Requests' Status. Unused bits e.g. reserved bits need to have been forced to
- * 0.
- */
-
-#define COMN_RESP_CRYPTO_STATUS_BITPOS 7
-/* Starting bit position indicating Response for Crypto service Flag  */
-
-#define COMN_RESP_CRYPTO_STATUS_MASK 0x1
-/* One bit mask used to determine Crypto status mask  */
-
-#define COMN_RESP_PKE_STATUS_BITPOS 6
-/* Starting bit position indicating Response for PKE service Flag  */
-
-#define COMN_RESP_PKE_STATUS_MASK 0x1
-/* One bit mask used to determine PKE status mask  */
-
-#define COMN_RESP_CMP_STATUS_BITPOS 5
-/* Starting bit position indicating Response for Compression service Flag  */
-
-#define COMN_RESP_CMP_STATUS_MASK 0x1
-/* One bit mask used to determine Compression status mask  */
-
-#define COMN_RESP_XLAT_STATUS_BITPOS 4
-/* Starting bit position indicating Response for Xlat service Flag  */
-
-#define COMN_RESP_XLAT_STATUS_MASK 0x1
-/* One bit mask used to determine Translator status mask  */
-
-#define COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS 3
-/* Starting bit position indicating the last block in a deflate stream for
-  the compression service Flag */
-
-#define COMN_RESP_CMP_END_OF_LAST_BLK_MASK 0x1
-/* One bit mask used to determine the last block in a deflate stream
-   status mask */
-
-#define COMN_RESP_UNSUPPORTED_REQUEST_BITPOS 2
-/* Starting bit position indicating when an unsupported service request Flag  */
-
-#define COMN_RESP_UNSUPPORTED_REQUEST_MASK 0x1
-/* One bit mask used to determine the unsupported service request status mask  */
-
-#define COMN_RESP_XLT_WA_APPLIED_BITPOS 0
-/* Bit position indicating a firmware workaround was applied to translation  */
-
-#define COMN_RESP_XLT_WA_APPLIED_MASK 0x1
-/* One bit mask  */
-
-/*
- * Macro that must be used when building the status
- * for the common response
- *
- * crypto   Value of the Crypto Service status flag
- * comp     Value of the Compression Service Status flag
- * xlat     Value of the Xlator Status flag
- * eolb     Value of the Compression End of Last Block Status flag
- * unsupp   Value of the Unsupported Request flag
- * xlt_wa   Value of the Translation WA marker
- */
-#define FW_COMN_RESP_STATUS_BUILD(	\
-	crypto, pke, comp, xlat, eolb, unsupp, xlt_wa)	\
-	((((crypto)&COMN_RESP_CRYPTO_STATUS_MASK)	\
-	  << COMN_RESP_CRYPTO_STATUS_BITPOS) |	\
-	 (((pke)&COMN_RESP_PKE_STATUS_MASK)	\
-	  << COMN_RESP_PKE_STATUS_BITPOS) |	\
-	 (((xlt_wa)&COMN_RESP_XLT_WA_APPLIED_MASK)	\
-	  << COMN_RESP_XLT_WA_APPLIED_BITPOS) |	\
-	 (((comp)&COMN_RESP_CMP_STATUS_MASK)	\
-	  << COMN_RESP_CMP_STATUS_BITPOS) |	\
-	 (((xlat)&COMN_RESP_XLAT_STATUS_MASK)	\
-	  << COMN_RESP_XLAT_STATUS_BITPOS) |	\
-	 (((eolb)&COMN_RESP_CMP_END_OF_LAST_BLK_MASK)	\
-	  << COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS) |	\
-	 (((unsupp)&COMN_RESP_UNSUPPORTED_REQUEST_BITPOS)	\
-	  << COMN_RESP_UNSUPPORTED_REQUEST_MASK))
-
-/*
- * Macro for extraction of the Crypto bit from the status
- *
- * status Status to extract the status bit from
- */
-#define FW_COMN_RESP_CRYPTO_STAT_GET(status)	\
-	FIELD_GET(status,	\
-			      COMN_RESP_CRYPTO_STATUS_BITPOS,	\
-			      COMN_RESP_CRYPTO_STATUS_MASK)
-
-/*
- * Macro for extraction of the PKE bit from the status
- *
- * status Status to extract the status bit from
- */
-#define FW_COMN_RESP_PKE_STAT_GET(status)	\
-	FIELD_GET(status,	\
-			      COMN_RESP_PKE_STATUS_BITPOS,	\
-			      COMN_RESP_PKE_STATUS_MASK)
-
-/*
- * Macro for extraction of the Compression bit from the status
- *
- * status Status to extract the status bit from
- */
-#define FW_COMN_RESP_CMP_STAT_GET(status)	\
-	FIELD_GET(status,	\
-			      COMN_RESP_CMP_STATUS_BITPOS,	\
-			      COMN_RESP_CMP_STATUS_MASK)
-
-/*
- * Macro for extraction of the Translator bit from the status
- *
- * status Status to extract the status bit from
- */
-#define FW_COMN_RESP_XLAT_STAT_GET(status)	\
-	FIELD_GET(status,	\
-			      COMN_RESP_XLAT_STATUS_BITPOS,	\
-			      COMN_RESP_XLAT_STATUS_MASK)
-
-/*
- * Macro for extraction of the Translation Workaround Applied bit from the
- * status
- *
- * status Status to extract the status bit from
- */
-#define FW_COMN_RESP_XLT_WA_APPLIED_GET(status)	\
-	FIELD_GET(status,	\
-			      COMN_RESP_XLT_WA_APPLIED_BITPOS,	\
-			      COMN_RESP_XLT_WA_APPLIED_MASK)
-
-/*
- * Macro for extraction of the end of compression block bit from the
- * status
- *
- * status
- * Status to extract the status bit from
- */
-#define FW_COMN_RESP_CMP_END_OF_LAST_BLK_FLAG_GET(status)	\
-	FIELD_GET(status,	\
-			      COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS,	\
-			      COMN_RESP_CMP_END_OF_LAST_BLK_MASK)
-
-/*
- * Macro for extraction of the Unsupported request from the status
- *
- * status
- * Status to extract the status bit from
- */
-#define FW_COMN_RESP_UNSUPPORTED_REQUEST_STAT_GET(status)	\
-	FIELD_GET(status,	\
-			      COMN_RESP_UNSUPPORTED_REQUEST_BITPOS,	\
-			      COMN_RESP_UNSUPPORTED_REQUEST_MASK)
-
-#define FW_COMN_STATUS_FLAG_OK 0
-/* Definition of successful processing of a request  */
-
-#define FW_COMN_STATUS_FLAG_ERROR 1
-/* Definition of erroneous processing of a request  */
-
-#define FW_COMN_STATUS_CMP_END_OF_LAST_BLK_FLAG_CLR 0
-/* Final Deflate block of a compression request not completed  */
-
-#define FW_COMN_STATUS_CMP_END_OF_LAST_BLK_FLAG_SET 1
-/* Final Deflate block of a compression request completed  */
-
-#define ERR_CODE_NO_ERROR 0
-/* Error Code constant value for no error  */
-
-#define ERR_CODE_INVALID_BLOCK_TYPE -1
-/* Invalid block type (type == 3)*/
-
-#define ERR_CODE_NO_MATCH_ONES_COMP -2
-/* Stored block length does not match one's complement */
-
-#define ERR_CODE_TOO_MANY_LEN_OR_DIS -3
-/* Too many length or distance codes */
-
-#define ERR_CODE_INCOMPLETE_LEN -4
-/* Code lengths codes incomplete */
-
-#define ERR_CODE_RPT_LEN_NO_FIRST_LEN -5
-/* Repeat lengths with no first length */
-
-#define ERR_CODE_RPT_GT_SPEC_LEN -6
-/* Repeat more than specified lengths */
-
-#define ERR_CODE_INV_LIT_LEN_CODE_LEN -7
-/* Invalid lit/len code lengths */
-
-#define ERR_CODE_INV_DIS_CODE_LEN -8
-/* Invalid distance code lengths */
-
-#define ERR_CODE_INV_LIT_LEN_DIS_IN_BLK -9
-/* Invalid lit/len or distance code in fixed/dynamic block */
-
-#define ERR_CODE_DIS_TOO_FAR_BACK -10
-/* Distance too far back in fixed or dynamic block */
-
-/* Common Error code definitions */
-#define ERR_CODE_OVERFLOW_ERROR -11
-/* Error Code constant value for overflow error  */
-
-#define ERR_CODE_SOFT_ERROR -12
-/* Error Code constant value for soft error  */
-
-#define ERR_CODE_FATAL_ERROR -13
-/* Error Code constant value for hard/fatal error  */
-
-#define ERR_CODE_COMP_OUTPUT_CORRUPTION -14
-/* Error Code constant for compression output corruption */
-
-#define ERR_CODE_HW_INCOMPLETE_FILE -15
-/* Error Code constant value for incomplete file hardware error  */
-
-#define ERR_CODE_SSM_ERROR -16
-/* Error Code constant value for error detected by SSM e.g. slice hang  */
-
-#define ERR_CODE_ENDPOINT_ERROR -17
-/* Error Code constant value for error detected by PCIe Endpoint, e.g. push
- * data error   */
-
-#define ERR_CODE_CNV_ERROR -18
-/* Error Code constant value for cnv failure  */
-
-#define ERR_CODE_EMPTY_DYM_BLOCK -19
-/* Error Code constant value for submission of empty dynamic stored block to
- * slice   */
-
-#define ERR_CODE_KPT_CRYPTO_SERVICE_FAIL_INVALID_HANDLE -20
-/* Error Code constant for invalid handle in kpt crypto service */
-
-#define ERR_CODE_KPT_CRYPTO_SERVICE_FAIL_HMAC_FAILED -21
-/* Error Code constant for failed hmac in kpt crypto service */
-
-#define ERR_CODE_KPT_CRYPTO_SERVICE_FAIL_INVALID_WRAPPING_ALGO -22
-/* Error Code constant for invalid wrapping algo in kpt crypto service */
-
-#define ERR_CODE_KPT_DRNG_SEED_NOT_LOAD -23
-/* Error Code constant for no drng seed is not loaded in kpt ecdsa signrs
-/service */
-
-#define FW_LA_ICV_VER_STATUS_PASS FW_COMN_STATUS_FLAG_OK
-/* Status flag indicating that the ICV verification passed  */
-
-#define FW_LA_ICV_VER_STATUS_FAIL FW_COMN_STATUS_FLAG_ERROR
-/* Status flag indicating that the ICV verification failed  */
-
-#define FW_LA_TRNG_STATUS_PASS FW_COMN_STATUS_FLAG_OK
-/* Status flag indicating that the TRNG returned valid entropy data  */
-
-#define FW_LA_TRNG_STATUS_FAIL FW_COMN_STATUS_FLAG_ERROR
-/* Status flag indicating that the TRNG Command Failed.  */
-
-/* -------------------------------------------------------------------------- */
-
-/*
- * Definition of the full bulk processing request structure.
- * Used for hash, cipher, hash-cipher and authentication-encryption
- * requests etc.
- */
-struct fw_la_bulk_req
-{
-	/* LWs 0-1 */
-	struct fw_comn_req_hdr comn_hdr;
-	/* Common request header - for Service Command Id,
-	 * use service-specific Crypto Command Id.
-	 * Service Specific Flags - use Symmetric Crypto Command Flags
-	 * (all of cipher, auth, SSL3, TLS and MGF,
-	 * excluding TRNG - field unused) */
-
-	/* LWs 2-5 */
-	union fw_comn_req_hdr_cd_pars cd_pars;
-	/* Common Request content descriptor field which points either to a
-	 * content descriptor
-	 * parameter block or contains the service-specific data itself. */
-
-	/* LWs 6-13 */
-	struct fw_comn_req_mid comn_mid;
-	/* Common request middle section */
-
-	/* LWs 14-26 */
-	struct fw_comn_req_rqpars serv_specif_rqpars;
-	/* Common request service-specific parameter field */
-
-	/* LWs 27-31 */
-	struct fw_comn_req_cd_ctrl cd_ctrl;
-	/* Common request content descriptor control block -
-	 * this field is service-specific */
-
-};
-
-/* clang-format off */
-
-/*
- *  LA BULK (SYMMETRIC CRYPTO) COMMAND FLAGS
- *
- *  + ===== + ---------- + ----- + ----- + ----- + ----- + ----- + ----- + ----- + ----- + ----- + ----- +
- *  |  Bit  |   [15:13]  |  12   |  11   |  10   |  7-9  |   6   |   5   |   4   |  3    |   2   |  1-0  |
- *  + ===== + ---------- + ----- + ----- + ----- + ----- + ----- + ----- + ----- + ----- + ------+ ----- +
- *  | Flags | Resvd Bits | ZUC   | GcmIV |Digest | Prot  | Cmp   | Rtn   | Upd   | Ciph/ | CiphIV| Part- |
- *  |       |     =0     | Prot  | Len   | In Buf| flgs  | Auth  | Auth  | State | Auth  | Field |  ial  |
- *  + ===== + ---------- + ----- + ----- + ----- + ----- + ----- + ----- + ----- + ----- + ------+ ----- +
- */
-
-/* clang-format on */
-
-/* Private defines */
-
-#define FW_LA_ZUC_3G_PROTO			__BIT(12)
-/* Indicating ZUC processing for a encrypt command
- * Must be set for Cipher-only, Cipher + Auth and Auth-only   */
-
-#define FW_LA_GCM_IV_LEN_12_OCTETS		__BIT(11)
-/* Indicates the IV Length for GCM protocol is 96 Bits (12 Octets)
- * If set FW does the padding to compute CTR0  */
-
-#define FW_LA_DIGEST_IN_BUFFER			__BIT(10)
-/* Flag representing that authentication digest is stored or is extracted
- * from the source buffer. Auth Result Pointer will be ignored in this case.  */
-
-#define FW_LA_PROTO				__BITS(7, 9)
-#define FW_LA_PROTO_SNOW_3G			__BIT(9)
-/* Indicates SNOW_3G processing for a encrypt command  */
-#define FW_LA_PROTO_GCM				__BIT(8)
-/* Indicates GCM processing for a auth_encrypt command  */
-#define FW_LA_PROTO_CCM				__BIT(7)
-/* Indicates CCM processing for a auth_encrypt command  */
-#define FW_LA_PROTO_NONE			0
-/* Indicates no specific protocol processing for the command  */
-
-#define FW_LA_CMP_AUTH_RES			__BIT(6)
-/* Flag representing the need to compare the auth result data to the expected
- * value in DRAM at the auth_address.  */
-
-#define FW_LA_RET_AUTH_RES			__BIT(5)
-/* Flag representing the need to return the auth result data to dram after the
- * request processing is complete  */
-
-#define FW_LA_UPDATE_STATE			__BIT(4)
-/* Flag representing the need to update the state data in dram after the
- * request processing is complete  */
-
-#define FW_CIPH_AUTH_CFG_OFFSET_IN_SHRAM_CP	__BIT(3)
-/* Flag representing Cipher/Auth Config Offset Type, where the offset
- * is contained in SHRAM constants page. When the SHRAM constants page
- * is not used for cipher/auth configuration, then the Content Descriptor
- * pointer field must be a pointer (as opposed to a 16-byte key), since
- * the block pointed to must contain both the slice config and the key  */
-
-#define FW_CIPH_IV_16BYTE_DATA			__BIT(2)
-/* Flag representing Cipher IV field contents as 16-byte data array
- * Otherwise Cipher IV field contents via 64-bit pointer */
-
-#define FW_LA_PARTIAL				__BITS(0, 1)
-#define FW_LA_PARTIAL_NONE			0
-/* Flag representing no need for partial processing condition i.e.
- * entire packet processed in the current command  */
-#define FW_LA_PARTIAL_START			1
-/* Flag representing the first chunk of the partial packet  */
-#define FW_LA_PARTIAL_MID			3
-/* Flag representing a middle chunk of the partial packet  */
-#define FW_LA_PARTIAL_END			2
-/* Flag representing the final/end chunk of the partial packet  */
-
-/* The table below defines the meaning of the prefix_addr & hash_state_sz in
- * the case of partial processing. See the HLD for further details
- *
- *  + ====== + ------------------------- + ----------------------- +
- *  | Parial |       Prefix Addr         |       Hash State Sz     |
- *  | State  |                           |                         |
- *  + ====== + ------------------------- + ----------------------- +
- *  |  FULL  | Points to the prefix data | Prefix size as below.   |
- *  |        |                           | No update of state      |
- *  + ====== + ------------------------- + ----------------------- +
- *  |  SOP   | Points to the prefix      | = inner prefix rounded  |
- *  |        | data. State is updated    | to qwrds + outer prefix |
- *  |        | at prefix_addr - state_sz | rounded to qwrds. The   |
- *  |        | - 8 (counter size)        | writeback state sz      |
- *  |        |                           | comes from the CD       |
- *  + ====== + ------------------------- + ----------------------- +
- *  |  MOP   | Points to the state data  | State size rounded to   |
- *  |        | Updated state written to  | num qwrds + 8 (for the  |
- *  |        | same location             | counter) + inner prefix |
- *  |        |                           | rounded to qwrds +      |
- *  |        |                           | outer prefix rounded to |
- *  |        |                           | qwrds.                  |
- *  + ====== + ------------------------- + ----------------------- +
- *  |  EOP   | Points to the state data  | State size rounded to   |
- *  |        |                           | num qwrds + 8 (for the  |
- *  |        |                           | counter) + inner prefix |
- *  |        |                           | rounded to qwrds +      |
- *  |        |                           | outer prefix rounded to |
- *  |        |                           | qwrds.                  |
- *  + ====== + ------------------------- + ----------------------- +
- *
- *  Notes:
- *
- *  - If the EOP is set it is assumed that no state update is to be performed.
- *    However it is the clients responsibility to set the update_state flag
- *    correctly i.e. not set for EOP or Full packet cases. Only set for SOP and
- *    MOP with no EOP flag
- *  - The SOP take precedence over the MOP and EOP i.e. in the calculation of
- *    the address to writeback the state.
- *  - The prefix address must be on at least the 8 byte boundary
- */
-
-/* Macros for extracting field bits */
-/*
- *   Macro for extraction of the Cipher IV field contents (bit 2)
- *
- * flags        Flags to extract the Cipher IV field contents
- *
- */
-#define FW_LA_CIPH_IV_FLD_FLAG_GET(flags)	\
-	FIELD_GET(flags, LA_CIPH_IV_FLD_BITPOS, LA_CIPH_IV_FLD_MASK)
-
-/*
- *   Macro for extraction of the Cipher/Auth Config
- *   offset type (bit 3)
- *
- * flags        Flags to extract the Cipher/Auth Config offset type
- *
- */
-#define FW_LA_CIPH_AUTH_CFG_OFFSET_FLAG_GET(flags)	\
-	FIELD_GET(flags,	\
-	    LA_CIPH_AUTH_CFG_OFFSET_BITPOS,	\
-	    LA_CIPH_AUTH_CFG_OFFSET_MASK)
-
-/*
- * Macro for extraction of the ZUC protocol bit
- * information (bit 11)
- *
- * flags        Flags to extract the ZUC protocol bit
- */
-#define FW_LA_ZUC_3G_PROTO_FLAG_GET(flags)	\
-	FIELD_GET(flags,	\
-	    FW_LA_ZUC_3G_PROTO_FLAG_BITPOS,	\
-	    FW_LA_ZUC_3G_PROTO_FLAG_MASK)
-
-/*
- * Macro for extraction of the GCM IV Len is 12 Octets / 96 Bits
- * information (bit 11)
- *
- * flags        Flags to extract the GCM IV length
- */
-#define FW_LA_GCM_IV_LEN_FLAG_GET(flags)	\
-	FIELD_GET(	\
-		flags, LA_GCM_IV_LEN_FLAG_BITPOS, LA_GCM_IV_LEN_FLAG_MASK)
-
-/*
- * Macro for extraction of the LA protocol state (bits 9-7)
- *
- * flags        Flags to extract the protocol state
- */
-#define FW_LA_PROTO_GET(flags)	\
-	FIELD_GET(flags, LA_PROTO_BITPOS, LA_PROTO_MASK)
-
-/*
- * Macro for extraction of the "compare auth" state (bit 6)
- *
- * flags        Flags to extract the compare auth result state
- *
- */
-#define FW_LA_CMP_AUTH_GET(flags)	\
-	FIELD_GET(flags, LA_CMP_AUTH_RES_BITPOS, LA_CMP_AUTH_RES_MASK)
-
-/*
- * Macro for extraction of the "return auth" state (bit 5)
- *
- * flags        Flags to extract the return auth result state
- *
- */
-#define FW_LA_RET_AUTH_GET(flags)	\
-	FIELD_GET(flags, LA_RET_AUTH_RES_BITPOS, LA_RET_AUTH_RES_MASK)
-
-/*
- * Macro for extraction of the "digest in buffer" state (bit 10)
- *
- * flags     Flags to extract the digest in buffer state
- *
- */
-#define FW_LA_DIGEST_IN_BUFFER_GET(flags)	\
-	FIELD_GET(	\
-		flags, LA_DIGEST_IN_BUFFER_BITPOS, LA_DIGEST_IN_BUFFER_MASK)
-
-/*
- * Macro for extraction of the update content state value. (bit 4)
- *
- * flags        Flags to extract the update content state bit
- */
-#define FW_LA_UPDATE_STATE_GET(flags)	\
-	FIELD_GET(flags, LA_UPDATE_STATE_BITPOS, LA_UPDATE_STATE_MASK)
-
-/*
- * Macro for extraction of the "partial" packet state (bits 1-0)
- *
- * flags        Flags to extract the partial state
- */
-#define FW_LA_PARTIAL_GET(flags)	\
-	FIELD_GET(flags, LA_PARTIAL_BITPOS, LA_PARTIAL_MASK)
-
-/* Macros for setting field bits */
-/*
- *   Macro for setting the Cipher IV field contents
- *
- * flags        Flags to set with the Cipher IV field contents
- * val          Field contents indicator value
- */
-#define FW_LA_CIPH_IV_FLD_FLAG_SET(flags, val)	\
-	FIELD_SET(	\
-		flags, val, LA_CIPH_IV_FLD_BITPOS, LA_CIPH_IV_FLD_MASK)
-
-/*
- * Macro for setting the Cipher/Auth Config
- * offset type
- *
- * flags        Flags to set the Cipher/Auth Config offset type
- * val          Offset type value
- */
-#define FW_LA_CIPH_AUTH_CFG_OFFSET_FLAG_SET(flags, val)	\
-	FIELD_SET(flags,	\
-	    val,	\
-	    LA_CIPH_AUTH_CFG_OFFSET_BITPOS,	\
-	    LA_CIPH_AUTH_CFG_OFFSET_MASK)
-
-/*
- * Macro for setting the ZUC protocol flag
- *
- * flags      Flags to set the ZUC protocol flag
- * val        Protocol value
- */
-#define FW_LA_ZUC_3G_PROTO_FLAG_SET(flags, val)	\
-	FIELD_SET(flags,	\
-	    val,	\
-	    FW_LA_ZUC_3G_PROTO_FLAG_BITPOS,	\
-	    FW_LA_ZUC_3G_PROTO_FLAG_MASK)
-
-/*
- * Macro for setting the GCM IV length flag state
- *
- * flags      Flags to set the GCM IV length flag state
- * val        Protocol value
- */
-#define FW_LA_GCM_IV_LEN_FLAG_SET(flags, val)	\
-	FIELD_SET(flags,	\
-	    val,	\
-	    LA_GCM_IV_LEN_FLAG_BITPOS,	\
-	    LA_GCM_IV_LEN_FLAG_MASK)
-
-/*
- * Macro for setting the LA protocol flag state
- *
- * flags        Flags to set the protocol state
- * val          Protocol value
- */
-#define FW_LA_PROTO_SET(flags, val)	\
-	FIELD_SET(flags, val, LA_PROTO_BITPOS, LA_PROTO_MASK)
-
-/*
- * Macro for setting the "compare auth" flag state
- *
- * flags      Flags to set the compare auth result state
- * val        Compare Auth value
- */
-#define FW_LA_CMP_AUTH_SET(flags, val)	\
-	FIELD_SET(	\
-		flags, val, LA_CMP_AUTH_RES_BITPOS, LA_CMP_AUTH_RES_MASK)
-
-/*
- * Macro for setting the "return auth" flag state
- *
- * flags      Flags to set the return auth result state
- * val        Return Auth value
- */
-#define FW_LA_RET_AUTH_SET(flags, val)	\
-	FIELD_SET(	\
-		flags, val, LA_RET_AUTH_RES_BITPOS, LA_RET_AUTH_RES_MASK)
-
-/*
- * Macro for setting the "digest in buffer" flag state
- *
- * flags     Flags to set the digest in buffer state
- * val       Digest in buffer value
- */
-#define FW_LA_DIGEST_IN_BUFFER_SET(flags, val)	\
-	FIELD_SET(flags,	\
-	    val,	\
-	    LA_DIGEST_IN_BUFFER_BITPOS,	\
-	    LA_DIGEST_IN_BUFFER_MASK)
-
-/*
- *   Macro for setting the "update state" flag value
- *
- * flags      Flags to set the update content state
- * val        Update Content State flag value
- */
-#define FW_LA_UPDATE_STATE_SET(flags, val)	\
-	FIELD_SET(	\
-		flags, val, LA_UPDATE_STATE_BITPOS, LA_UPDATE_STATE_MASK)
-
-/*
- *   Macro for setting the "partial" packet flag state
- *
- * flags      Flags to set the partial state
- * val        Partial state value
- */
-#define FW_LA_PARTIAL_SET(flags, val)	\
-	FIELD_SET(flags, val, LA_PARTIAL_BITPOS, LA_PARTIAL_MASK)
-
-/*
- * Definition of the Cipher header Content Descriptor pars block
- * Definition of the cipher processing header cd pars block.
- * The structure is a service-specific implementation of the common
- * 'fw_comn_req_hdr_cd_pars_s' structure.
- */
-union fw_cipher_req_hdr_cd_pars {
-	/* LWs 2-5 */
-	struct
-	{
-		uint64_t content_desc_addr;
-		/* Address of the content descriptor */
-
-		uint16_t content_desc_resrvd1;
-		/* Content descriptor reserved field */
-
-		uint8_t content_desc_params_sz;
-		/* Size of the content descriptor parameters in quad words. These
-		 * parameters describe the session setup configuration info for the
-		 * slices that this request relies upon i.e. the configuration word and
-		 * cipher key needed by the cipher slice if there is a request for
-		 * cipher processing. */
-
-		uint8_t content_desc_hdr_resrvd2;
-		/* Content descriptor reserved field */
-
-		uint32_t content_desc_resrvd3;
-		/* Content descriptor reserved field */
-	} s;
-
-	struct
-	{
-		uint32_t cipher_key_array[FW_NUM_LONGWORDS_4];
-		/* Cipher Key Array */
-
-	} s1;
-
-};
-
-/*
- * Definition of the Authentication header Content Descriptor pars block
- * Definition of the authentication processing header cd pars block.
- */
-/* Note: Authentication uses the common 'fw_comn_req_hdr_cd_pars_s'
- * structure - similarly, it is also used by SSL3, TLS and MGF. Only cipher
- * and cipher + authentication require service-specific implementations of
- * the structure  */
-
-/*
- * Definition of the Cipher + Auth header Content Descriptor pars block
- * Definition of the cipher + auth processing header cd pars block.
- * The structure is a service-specific implementation of the common
- * 'fw_comn_req_hdr_cd_pars_s' structure.
- */
-union fw_cipher_auth_req_hdr_cd_pars {
-	/* LWs 2-5 */
-	struct
-	{
-		uint64_t content_desc_addr;
-		/* Address of the content descriptor */
-
-		uint16_t content_desc_resrvd1;
-		/* Content descriptor reserved field */
-
-		uint8_t content_desc_params_sz;
-		/* Size of the content descriptor parameters in quad words. These
-		 * parameters describe the session setup configuration info for the
-		 * slices that this request relies upon i.e. the configuration word and
-		 * cipher key needed by the cipher slice if there is a request for
-		 * cipher processing. */
-
-		uint8_t content_desc_hdr_resrvd2;
-		/* Content descriptor reserved field */
-
-		uint32_t content_desc_resrvd3;
-		/* Content descriptor reserved field */
-	} s;
-
-	struct
-	{
-		uint32_t cipher_key_array[FW_NUM_LONGWORDS_4];
-		/* Cipher Key Array */
-
-	} sl;
-
-};
-
-/*
- * Cipher content descriptor control block (header)
- * Definition of the service-specific cipher control block header
- * structure. This header forms part of the content descriptor
- * block incorporating LWs 27-31, as defined by the common base
- * parameters structure.
- */
-struct fw_cipher_cd_ctrl_hdr
-{
-	/* LW 27 */
-	uint8_t cipher_state_sz;
-	/* State size in quad words of the cipher algorithm used in this session.
-	 * Set to zero if the algorithm doesnt provide any state */
-
-	uint8_t cipher_key_sz;
-	/* Key size in quad words of the cipher algorithm used in this session */
-
-	uint8_t cipher_cfg_offset;
-	/* Quad word offset from the content descriptor parameters address i.e.
-	 * (content_address + (cd_hdr_sz << 3)) to the parameters for the cipher
-	 * processing */
-
-	uint8_t next_curr_id;
-	/* This field combines the next and current id (each four bits) -
-	  * the next id is the most significant nibble.
-	  * Next Id:  Set to the next slice to pass the ciphered data through.
-	  * Set to FW_SLICE_DRAM_WR if the data is not to go through
-	  * any more slices after cipher.
-	  * Current Id: Initialised with the cipher  slice type */
-
-	/* LW 28 */
-	uint8_t cipher_padding_sz;
-	/* State padding size in quad words. Set to 0 if no padding is required.
-	 */
-
-	uint8_t resrvd1;
-	uint16_t resrvd2;
-	/* Reserved bytes to bring the struct to the word boundary, used by
-	 * authentication. MUST be set to 0 */
-
-	/* LWs 29-31 */
-	uint32_t resrvd3[FW_NUM_LONGWORDS_3];
-	/* Reserved bytes used by authentication. MUST be set to 0 */
-
-};
-
-/*
- * Authentication content descriptor control block (header)
- * Definition of the service-specific authentication control block
- * header structure. This header forms part of the content descriptor
- * block incorporating LWs 27-31, as defined by the common base
- * parameters structure, the first portion of which is reserved for
- * cipher.
- */
-struct fw_auth_cd_ctrl_hdr
-{
-	/* LW 27 */
-	uint32_t resrvd1;
-	/* Reserved bytes, used by cipher only. MUST be set to 0 */
-
-	/* LW 28 */
-	uint8_t resrvd2;
-	/* Reserved byte, used by cipher only. MUST be set to 0 */
-
-	uint8_t hash_flags;
-	/* General flags defining the processing to perform. 0 is normal
-	 * processing
-	 * and 1 means there is a nested hash processing loop to go through */
-
-	uint8_t hash_cfg_offset;
-	/* Quad word offset from the content descriptor parameters address to the
-	 * parameters for the auth processing */
-
-	uint8_t next_curr_id;
-	/* This field combines the next and current id (each four bits) -
-	  * the next id is the most significant nibble.
-	  * Next Id:  Set to the next slice to pass the authentication data through.
-	  * Set to FW_SLICE_DRAM_WR if the data is not to go through
-	  * any more slices after authentication.
-	  * Current Id: Initialised with the authentication slice type */
-
-	/* LW 29 */
-	uint8_t resrvd3;
-	/* Now a reserved field. MUST be set to 0 */
-
-	uint8_t outer_prefix_sz;
-	/* Size in bytes of outer prefix data */
-
-	uint8_t final_sz;
-	/* Size in bytes of digest to be returned to the client if requested */
-
-	uint8_t inner_res_sz;
-	/* Size in bytes of the digest from the inner hash algorithm */
-
-	/* LW 30 */
-	uint8_t resrvd4;
-	/* Now a reserved field. MUST be set to zero. */
-
-	uint8_t inner_state1_sz;
-	/* Size in bytes of inner hash state1 data. Must be a qword multiple */
-
-	uint8_t inner_state2_offset;
-	/* Quad word offset from the content descriptor parameters pointer to the
-	 * inner state2 value */
-
-	uint8_t inner_state2_sz;
-	/* Size in bytes of inner hash state2 data. Must be a qword multiple */
-
-	/* LW 31 */
-	uint8_t outer_config_offset;
-	/* Quad word offset from the content descriptor parameters pointer to the
-	 * outer configuration information */
-
-	uint8_t outer_state1_sz;
-	/* Size in bytes of the outer state1 value */
-
-	uint8_t outer_res_sz;
-	/* Size in bytes of digest from the outer auth algorithm */
-
-	uint8_t outer_prefix_offset;
-	/* Quad word offset from the start of the inner prefix data to the outer
-	 * prefix information. Should equal the rounded inner prefix size, converted
-	 * to qwords  */
-
-};
-
-/*
- * Cipher + Authentication content descriptor control block header
- * Definition of both service-specific cipher + authentication control
- * block header structures. This header forms part of the content
- * descriptor block incorporating LWs 27-31, as defined by the common
- * base  parameters structure.
- */
-struct fw_cipher_auth_cd_ctrl_hdr
-{
-	/* LW 27 */
-	uint8_t cipher_state_sz;
-	/* State size in quad words of the cipher algorithm used in this session.
-	 * Set to zero if the algorithm doesnt provide any state */
-
-	uint8_t cipher_key_sz;
-	/* Key size in quad words of the cipher algorithm used in this session */
-
-	uint8_t cipher_cfg_offset;
-	/* Quad word offset from the content descriptor parameters address i.e.
-	 * (content_address + (cd_hdr_sz << 3)) to the parameters for the cipher
-	 * processing */
-
-	uint8_t next_curr_id_cipher;
-	/* This field combines the next and current id (each four bits) -
-	  * the next id is the most significant nibble.
-	  * Next Id:  Set to the next slice to pass the ciphered data through.
-	  * Set to FW_SLICE_DRAM_WR if the data is not to go through
-	  * any more slices after cipher.
-	  * Current Id: Initialised with the cipher  slice type */
-
-	/* LW 28 */
-	uint8_t cipher_padding_sz;
-	/* State padding size in quad words. Set to 0 if no padding is required.
-	 */
-
-	uint8_t hash_flags;
-	/* General flags defining the processing to perform. 0 is normal
-	 * processing
-	 * and 1 means there is a nested hash processing loop to go through */
-
-	uint8_t hash_cfg_offset;
-	/* Quad word offset from the content descriptor parameters address to the
-	 * parameters for the auth processing */
-
-	uint8_t next_curr_id_auth;
-	/* This field combines the next and current id (each four bits) -
-	  * the next id is the most significant nibble.
-	  * Next Id:  Set to the next slice to pass the authentication data through.
-	  * Set to FW_SLICE_DRAM_WR if the data is not to go through
-	  * any more slices after authentication.
-	  * Current Id: Initialised with the authentication slice type */
-
-	/* LW 29 */
-	uint8_t resrvd1;
-	/* Reserved field. MUST be set to 0 */
-
-	uint8_t outer_prefix_sz;
-	/* Size in bytes of outer prefix data */
-
-	uint8_t final_sz;
-	/* Size in bytes of digest to be returned to the client if requested */
-
-	uint8_t inner_res_sz;
-	/* Size in bytes of the digest from the inner hash algorithm */
-
-	/* LW 30 */
-	uint8_t resrvd2;
-	/* Now a reserved field. MUST be set to zero. */
-
-	uint8_t inner_state1_sz;
-	/* Size in bytes of inner hash state1 data. Must be a qword multiple */
-
-	uint8_t inner_state2_offset;
-	/* Quad word offset from the content descriptor parameters pointer to the
-	 * inner state2 value */
-
-	uint8_t inner_state2_sz;
-	/* Size in bytes of inner hash state2 data. Must be a qword multiple */
-
-	/* LW 31 */
-	uint8_t outer_config_offset;
-	/* Quad word offset from the content descriptor parameters pointer to the
-	 * outer configuration information */
-
-	uint8_t outer_state1_sz;
-	/* Size in bytes of the outer state1 value */
-
-	uint8_t outer_res_sz;
-	/* Size in bytes of digest from the outer auth algorithm */
-
-	uint8_t outer_prefix_offset;
-	/* Quad word offset from the start of the inner prefix data to the outer
-	 * prefix information. Should equal the rounded inner prefix size, converted
-	 * to qwords  */
-
-};
-
-#define FW_AUTH_HDR_FLAG_DO_NESTED 1
-/* Definition of the hash_flags bit of the auth_hdr to indicate the request
- * requires nested hashing  */
-
-#define FW_AUTH_HDR_FLAG_NO_NESTED 0
-/* Definition of the hash_flags bit of the auth_hdr for no nested hashing
- * required  */
-
-#define FW_CCM_GCM_AAD_SZ_MAX 240
-/* Maximum size of AAD data allowed for CCM or GCM processing. AAD data size90 -
- * is stored in 8-bit field and must be multiple of hash block size. 240 is
- * largest value which satisfy both requirements.AAD_SZ_MAX is in byte units  */
-
-/*
- * request parameter #defines
- */
-#define FW_HASH_REQUEST_PARAMETERS_OFFSET	\
-	(sizeof(fw_la_cipher_req_params_t))
-/* Offset in bytes from the start of the request parameters block to the hash
- * (auth) request parameters  */
-
-#define FW_CIPHER_REQUEST_PARAMETERS_OFFSET (0)
-/* Offset in bytes from the start of the request parameters block to the cipher
- * request parameters  */
-
-/*
- * Definition of the cipher request parameters block
- *
- * Definition of the cipher processing request parameters block
- * structure, which forms part of the block incorporating LWs 14-26,
- * as defined by the common base parameters structure.
- * Unused fields must be set to 0.
- */
-struct fw_la_cipher_req_params {
-	/* LW 14 */
-	uint32_t cipher_offset;
-	/* Cipher offset long word. */
-
-	/* LW 15 */
-	uint32_t cipher_length;
-	/* Cipher length long word. */
-
-	/* LWs 16-19 */
-	union {
-		uint32_t cipher_IV_array[FW_NUM_LONGWORDS_4];
-		/* Cipher IV array  */
-
-		struct
-		{
-			uint64_t cipher_IV_ptr;
-			/* Cipher IV pointer or Partial State Pointer */
-
-			uint64_t resrvd1;
-			/* reserved */
-
-		} s;
-
-	} u;
-
-};
-
-/*
- * Definition of the auth request parameters block
- * Definition of the authentication processing request parameters block
- * structure, which forms part of the block incorporating LWs 14-26,
- * as defined by the common base parameters structure. Note:
- * This structure is used by TLS only.
- */
-struct fw_la_auth_req_params {
-	/* LW 20 */
-	uint32_t auth_off;
-	/* Byte offset from the start of packet to the auth data region */
-
-	/* LW 21 */
-	uint32_t auth_len;
-	/* Byte length of the auth data region */
-
-	/* LWs 22-23 */
-	union {
-		uint64_t auth_partial_st_prefix;
-		/* Address of the authentication partial state prefix
-		 * information */
-
-		uint64_t aad_adr;
-		/* Address of the AAD info in DRAM. Used for the CCM and GCM
-		 * protocols */
-
-	} u1;
-
-	/* LWs 24-25 */
-	uint64_t auth_res_addr;
-	/* Address of the authentication result information to validate or
-	 * the location to which the digest information can be written back to */
-
-	/* LW 26 */
-	union {
-		uint8_t inner_prefix_sz;
-		/* Size in bytes of the inner prefix data */
-
-		uint8_t aad_sz;
-		/* Size in bytes of padded AAD data to prefix to the packet for CCM
-		 *  or GCM processing */
-	} u2;
-
-	uint8_t resrvd1;
-	/* reserved */
-
-	uint8_t hash_state_sz;
-	/* Number of quad words of inner and outer hash prefix data to process
-	 * Maximum size is 240 */
-
-	uint8_t auth_res_sz;
-	/* Size in bytes of the authentication result */
-
-} __packed;
-
-/*
- * Definition of the auth request parameters block
- * Definition of the authentication processing request parameters block
- * structure, which forms part of the block incorporating LWs 14-26,
- * as defined by the common base parameters structure. Note:
- * This structure is used by SSL3 and MGF1 only. All fields other than
- * inner prefix/ AAD size are unused and therefore reserved.
- */
-struct fw_la_auth_req_params_resrvd_flds {
-	/* LWs 20-25 */
-	uint32_t resrvd[FW_NUM_LONGWORDS_6];
-
-	/* LW 26 */
-	union {
-		uint8_t inner_prefix_sz;
-		/* Size in bytes of the inner prefix data */
-
-		uint8_t aad_sz;
-		/* Size in bytes of padded AAD data to prefix to the packet for CCM
-		 *  or GCM processing */
-	} u2;
-
-	uint8_t resrvd1;
-	/* reserved */
-
-	uint16_t resrvd2;
-	/* reserved */
-};
-
-/*
- *   Definition of the shared fields within the parameter block
- *   containing SSL, TLS or MGF information.
- *   This structure defines the shared fields for SSL, TLS or MGF
- *   within the parameter block incorporating LWs 14-26, as defined
- *   by the common base parameters structure.
- *   Unused fields must be set to 0.
- */
-struct fw_la_key_gen_common {
-	/* LW 14 */
-	union {
-		/* SSL3 */
-		uint16_t secret_lgth_ssl;
-		/* Length of Secret information for SSL. In the case of TLS the
-		* secret is supplied in the content descriptor */
-
-		/* MGF */
-		uint16_t mask_length;
-		/* Size in bytes of the desired output mask for MGF1*/
-
-		/* TLS */
-		uint16_t secret_lgth_tls;
-		/* TLS Secret length */
-
-	} u;
-
-	union {
-		/* SSL3 */
-		struct
-		{
-			uint8_t output_lgth_ssl;
-			/* Output length */
-
-			uint8_t label_lgth_ssl;
-			/* Label length */
-
-		} s1;
-
-		/* MGF */
-		struct
-		{
-			uint8_t hash_length;
-			/* Hash length */
-
-			uint8_t seed_length;
-			/* Seed length */
-
-		} s2;
-
-		/* TLS */
-		struct
-		{
-			uint8_t output_lgth_tls;
-			/* Output length */
-
-			uint8_t label_lgth_tls;
-			/* Label length */
-
-		} s3;
-
-	} u1;
-
-	/* LW 15 */
-	union {
-		/* SSL3 */
-		uint8_t iter_count;
-		/* Iteration count used by the SSL key gen request */
-
-		/* TLS */
-		uint8_t tls_seed_length;
-		/* TLS Seed length */
-
-		uint8_t resrvd1;
-		/* Reserved field set to 0 for MGF1 */
-
-	} u2;
-
-	uint8_t resrvd2;
-	uint16_t resrvd3;
-	/* Reserved space - unused */
-
-};
-
-/*
- *   Definition of the SSL3 request parameters block
- *   This structure contains the the SSL3 processing request parameters
- *   incorporating LWs 14-26, as defined by the common base
- *   parameters structure. Unused fields must be set to 0.
- */
-struct fw_la_ssl3_req_params {
-	/* LWs 14-15 */
-	struct fw_la_key_gen_common keygen_comn;
-	/* For other key gen processing these field holds ssl, tls or mgf
-	 *   parameters */
-
-	/* LW 16-25 */
-	uint32_t resrvd[FW_NUM_LONGWORDS_10];
-	/* Reserved */
-
-	/* LW 26 */
-	union {
-		uint8_t inner_prefix_sz;
-		/* Size in bytes of the inner prefix data */
-
-		uint8_t aad_sz;
-		/* Size in bytes of padded AAD data to prefix to the packet for CCM
-		 *  or GCM processing */
-	} u2;
-
-	uint8_t resrvd1;
-	/* reserved */
-
-	uint16_t resrvd2;
-	/* reserved */
-
-};
-
-/*
- * Definition of the MGF request parameters block
- * This structure contains the the MGF processing request parameters
- * incorporating LWs 14-26, as defined by the common base parameters
- * structure. Unused fields must be set to 0.
- */
-struct fw_la_mgf_req_params {
-	/* LWs 14-15 */
-	struct fw_la_key_gen_common keygen_comn;
-	/* For other key gen processing these field holds ssl or mgf
-	 *   parameters */
-
-	/* LW 16-25 */
-	uint32_t resrvd[FW_NUM_LONGWORDS_10];
-	/* Reserved */
-
-	/* LW 26 */
-	union {
-		uint8_t inner_prefix_sz;
-		/* Size in bytes of the inner prefix data */
-
-		uint8_t aad_sz;
-		/* Size in bytes of padded AAD data to prefix to the packet for CCM
-		 *  or GCM processing */
-	} u2;
-
-	uint8_t resrvd1;
-	/* reserved */
-
-	uint16_t resrvd2;
-	/* reserved */
-
-};
-
-/*
- * Definition of the TLS request parameters block
- * This structure contains the the TLS processing request parameters
- * incorporating LWs 14-26, as defined by the common base parameters
- * structure. Unused fields must be set to 0.
- */
-struct fw_la_tls_req_params {
-	/* LWs 14-15 */
-	struct fw_la_key_gen_common keygen_comn;
-	/* For other key gen processing these field holds ssl, tls or mgf
-	 *   parameters */
-
-	/* LW 16-19 */
-	uint32_t resrvd[FW_NUM_LONGWORDS_4];
-	/* Reserved */
-
-};
-
-/*
- * Definition of the common QAT FW request middle block for TRNG.
- * Common section of the request used across all of the services exposed
- * by the QAT FW. Each of the services inherit these common fields. TRNG
- * requires a specific implementation.
- */
-struct fw_la_trng_req_mid {
-	/* LWs 6-13 */
-	uint64_t opaque_data;
-	/* Opaque data passed unmodified from the request to response messages by
-	 * firmware (fw) */
-
-	uint64_t resrvd1;
-	/* Reserved, unused for TRNG */
-
-	uint64_t dest_data_addr;
-	/* Generic definition of the destination data supplied to the QAT AE. The
-	 * common flags are used to further describe the attributes of this
-	 * field */
-
-	uint32_t resrvd2;
-	/* Reserved, unused for TRNG */
-
-	uint32_t entropy_length;
-	/* Size of the data in bytes to process. Used by the get_random
-	 * command. Set to 0 for commands that dont need a length parameter */
-
-};
-
-/*
- * Definition of the common LA QAT FW TRNG request
- * Definition of the TRNG processing request type
- */
-struct fw_la_trng_req {
-	/* LWs 0-1 */
-	struct fw_comn_req_hdr comn_hdr;
-	/* Common request header */
-
-	/* LWs 2-5 */
-	union fw_comn_req_hdr_cd_pars cd_pars;
-	/* Common Request content descriptor field which points either to a
-	 * content descriptor
-	 * parameter block or contains the service-specific data itself. */
-
-	/* LWs 6-13 */
-	struct fw_la_trng_req_mid comn_mid;
-	/* TRNG request middle section - differs from the common mid-section */
-
-	/* LWs 14-26 */
-	uint32_t resrvd1[FW_NUM_LONGWORDS_13];
-
-	/* LWs 27-31 */
-	uint32_t resrvd2[FW_NUM_LONGWORDS_5];
-
-};
-
-/*
- * Definition of the Lookaside Eagle Tail Response
- * This is the response delivered to the ET rings by the Lookaside
- * QAT FW service for all commands
- */
-struct fw_la_resp {
-	/* LWs 0-1 */
-	struct fw_comn_resp_hdr comn_resp;
-	/* Common interface response format see fw.h */
-
-	/* LWs 2-3 */
-	uint64_t opaque_data;
-	/* Opaque data passed from the request to the response message */
-
-	/* LWs 4-7 */
-	uint32_t resrvd[FW_NUM_LONGWORDS_4];
-	/* Reserved */
-
-};
-
-/*
- *   Definition of the Lookaside TRNG Test Status Structure
- *   As an addition to FW_LA_TRNG_STATUS Pass or Fail information
- *   in common response fields, as a response to TRNG_TEST request, Test
- *   status, Counter for failed tests and 4 entropy counter values are
- *   sent
- *   Status of test status and the fail counts.
- */
-struct fw_la_trng_test_result {
-	uint32_t test_status_info;
-	/* TRNG comparator health test status& Validity information
-	see Test Status Bit Fields below. */
-
-	uint32_t test_status_fail_count;
-	/* TRNG comparator health test status, 32bit fail counter */
-
-	uint64_t r_ent_ones_cnt;
-	/* Raw Entropy ones counter */
-
-	uint64_t r_ent_zeros_cnt;
-	/* Raw Entropy zeros counter */
-
-	uint64_t c_ent_ones_cnt;
-	/* Conditioned Entropy ones counter */
-
-	uint64_t c_ent_zeros_cnt;
-	/* Conditioned Entropy zeros counter */
-
-	uint64_t resrvd;
-	/* Reserved field must be set to zero */
-
-};
-
-/*
- * Definition of the Lookaside SSL Key Material Input
- * This struct defines the layout of input parameters for the
- * SSL3 key generation (source flat buffer format)
- */
-struct fw_la_ssl_key_material_input {
-	uint64_t seed_addr;
-	/* Pointer to seed */
-
-	uint64_t label_addr;
-	/* Pointer to label(s) */
-
-	uint64_t secret_addr;
-	/* Pointer to secret */
-
-};
-
-/*
- * Definition of the Lookaside TLS Key Material Input
- * This struct defines the layout of input parameters for the
- * TLS key generation (source flat buffer format)
- * NOTE:
- * Secret state value (S split into S1 and S2 parts) is supplied via
- * Content Descriptor. S1 is placed in an outer prefix buffer, and S2
- * inside the inner prefix buffer.
- */
-struct fw_la_tls_key_material_input {
-	uint64_t seed_addr;
-	/* Pointer to seed */
-
-	uint64_t label_addr;
-	/* Pointer to label(s) */
-
-};
-
-/*
- * Macros using the bit position and mask to set/extract the next
- * and current id nibbles within the next_curr_id field of the
- * content descriptor header block, ONLY FOR CIPHER + AUTH COMBINED.
- * Note that for cipher only or authentication only, the common macros
- * need to be used. These are defined in the 'fw.h' common header
- * file, as they are used by compression, cipher and authentication.
- *
- * cd_ctrl_hdr_t      Content descriptor control block header.
- * val                Value of the field being set.
- */
-/* Cipher fields within Cipher + Authentication structure */
-#define FW_CIPHER_NEXT_ID_GET(cd_ctrl_hdr_t)	\
-	((((cd_ctrl_hdr_t)->next_curr_id_cipher) &	\
-	  FW_COMN_NEXT_ID_MASK) >>	\
-	 (FW_COMN_NEXT_ID_BITPOS))
-
-#define FW_CIPHER_NEXT_ID_SET(cd_ctrl_hdr_t, val)	\
-	(cd_ctrl_hdr_t)->next_curr_id_cipher =	\
-		((((cd_ctrl_hdr_t)->next_curr_id_cipher) &	\
-		  FW_COMN_CURR_ID_MASK) |	\
-		 ((val << FW_COMN_NEXT_ID_BITPOS) &	\
-		  FW_COMN_NEXT_ID_MASK))
-
-#define FW_CIPHER_CURR_ID_GET(cd_ctrl_hdr_t)	\
-	(((cd_ctrl_hdr_t)->next_curr_id_cipher) & FW_COMN_CURR_ID_MASK)
-
-#define FW_CIPHER_CURR_ID_SET(cd_ctrl_hdr_t, val)	\
-	(cd_ctrl_hdr_t)->next_curr_id_cipher =	\
-		((((cd_ctrl_hdr_t)->next_curr_id_cipher) &	\
-		  FW_COMN_NEXT_ID_MASK) |	\
-		 ((val)&FW_COMN_CURR_ID_MASK))
-
-/* Authentication fields within Cipher + Authentication structure */
-#define FW_AUTH_NEXT_ID_GET(cd_ctrl_hdr_t)	\
-	((((cd_ctrl_hdr_t)->next_curr_id_auth) & FW_COMN_NEXT_ID_MASK) >>	\
-	 (FW_COMN_NEXT_ID_BITPOS))
-
-#define FW_AUTH_NEXT_ID_SET(cd_ctrl_hdr_t, val)	\
-	(cd_ctrl_hdr_t)->next_curr_id_auth =	\
-		((((cd_ctrl_hdr_t)->next_curr_id_auth) &	\
-		  FW_COMN_CURR_ID_MASK) |	\
-		 ((val << FW_COMN_NEXT_ID_BITPOS) &	\
-		  FW_COMN_NEXT_ID_MASK))
-
-#define FW_AUTH_CURR_ID_GET(cd_ctrl_hdr_t)	\
-	(((cd_ctrl_hdr_t)->next_curr_id_auth) & FW_COMN_CURR_ID_MASK)
-
-#define FW_AUTH_CURR_ID_SET(cd_ctrl_hdr_t, val)	\
-	(cd_ctrl_hdr_t)->next_curr_id_auth =	\
-		((((cd_ctrl_hdr_t)->next_curr_id_auth) &	\
-		  FW_COMN_NEXT_ID_MASK) |	\
-		 ((val)&FW_COMN_CURR_ID_MASK))
-
-/*  Definitions of the bits in the test_status_info of the TRNG_TEST response.
- *  The values returned by the Lookaside service are given below
- *  The Test result and Test Fail Count values are only valid if the Test
- *  Results Valid (Tv) is set.
- *
- *  TRNG Test Status Info
- *  + ===== + ------------------------------------------------ + --- + --- +
- *  |  Bit  |                   31 - 2                         |  1  |  0  |
- *  + ===== + ------------------------------------------------ + --- + --- +
- *  | Flags |                 RESERVED = 0                     | Tv  | Ts  |
- *  + ===== + ------------------------------------------------------------ +
- */
-/*
- *   Definition of the Lookaside TRNG Test Status Information received as
- *   a part of fw_la_trng_test_result_t
- *
- */
-#define FW_LA_TRNG_TEST_STATUS_TS_BITPOS 0
-/* TRNG Test Result t_status field bit pos definition. */
-
-#define FW_LA_TRNG_TEST_STATUS_TS_MASK 0x1
-/* TRNG Test Result t_status field mask definition. */
-
-#define FW_LA_TRNG_TEST_STATUS_TV_BITPOS 1
-/* TRNG Test Result test results valid field bit pos definition. */
-
-#define FW_LA_TRNG_TEST_STATUS_TV_MASK 0x1
-/* TRNG Test Result test results valid field mask definition. */
-
-/*
- *   Definition of the Lookaside TRNG test_status values.
- *
- *
- */
-#define FW_LA_TRNG_TEST_STATUS_TV_VALID 1
-/* TRNG TEST Response Test Results Valid Value. */
-
-#define FW_LA_TRNG_TEST_STATUS_TV_NOT_VALID 0
-/* TRNG TEST Response Test Results are NOT Valid Value. */
-
-#define FW_LA_TRNG_TEST_STATUS_TS_NO_FAILS 1
-/* Value for TRNG Test status tests have NO FAILs Value. */
-
-#define FW_LA_TRNG_TEST_STATUS_TS_HAS_FAILS 0
-/* Value for TRNG Test status tests have one or more FAILS Value. */
-
-/*
- *  Macro for extraction of the Test Status Field returned in the response
- *  to TRNG TEST command.
- *
- * test_status        8 bit test_status value to extract the status bit
- */
-#define FW_LA_TRNG_TEST_STATUS_TS_FLD_GET(test_status)	\
-	FIELD_GET(test_status,	\
-			      FW_LA_TRNG_TEST_STATUS_TS_BITPOS,	\
-			      FW_LA_TRNG_TEST_STATUS_TS_MASK)
-/*
- *  Macro for extraction of the Test Results Valid Field returned in the
- *  response to TRNG TEST command.
- *
- * test_status        8 bit test_status value to extract the Tests
- *         Results valid bit
- */
-#define FW_LA_TRNG_TEST_STATUS_TV_FLD_GET(test_status)	\
-	FIELD_GET(test_status,	\
-			      FW_LA_TRNG_TEST_STATUS_TV_BITPOS,	\
-			      FW_LA_TRNG_TEST_STATUS_TV_MASK)
-
-/*
- * MGF Max supported input parameters
- */
-#define FW_LA_MGF_SEED_LEN_MAX 255
-/* Maximum seed length for MGF1 request in bytes
- * Typical values may be 48, 64, 128 bytes (or any). */
-
-#define FW_LA_MGF_MASK_LEN_MAX 65528
-/* Maximum mask length for MGF1 request in bytes
- * Typical values may be 8 (64-bit), 16 (128-bit). MUST be quad word multiple  */
-
-/*
- * SSL Max supported input parameters
- */
-#define FW_LA_SSL_SECRET_LEN_MAX 512
-/* Maximum secret length for SSL3 Key Gen request (bytes)  */
-
-#define FW_LA_SSL_ITERATES_LEN_MAX 16
-/* Maximum iterations for SSL3 Key Gen request (integer)  */
-
-#define FW_LA_SSL_LABEL_LEN_MAX 136
-/* Maximum label length for SSL3 Key Gen request (bytes)  */
-
-#define FW_LA_SSL_SEED_LEN_MAX 64
-/* Maximum seed length for SSL3 Key Gen request (bytes)  */
-
-#define FW_LA_SSL_OUTPUT_LEN_MAX 248
-/* Maximum output length for SSL3 Key Gen request (bytes)  */
-
-/*
- * TLS Max supported input parameters
- */
-#define FW_LA_TLS_SECRET_LEN_MAX 128
-/* Maximum secret length for TLS Key Gen request (bytes)  */
-
-#define FW_LA_TLS_V1_1_SECRET_LEN_MAX 128
-/* Maximum secret length for TLS Key Gen request (bytes)  */
-
-#define FW_LA_TLS_V1_2_SECRET_LEN_MAX 64
-/* Maximum secret length for TLS Key Gen request (bytes)  */
-
-#define FW_LA_TLS_LABEL_LEN_MAX 255
-/* Maximum label length for TLS Key Gen request (bytes)  */
-
-#define FW_LA_TLS_SEED_LEN_MAX 64
-/* Maximum seed length for TLS Key Gen request (bytes)  */
-
-#define FW_LA_TLS_OUTPUT_LEN_MAX 248
-/* Maximum output length for TLS Key Gen request (bytes)  */
-
-#endif
diff --git a/sys/dev/qat/qat_hw17var.h b/sys/dev/qat/qat_hw17var.h
deleted file mode 100644
index 1f3d62b86f5e..000000000000
--- a/sys/dev/qat/qat_hw17var.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/* SPDX-License-Identifier: BSD-2-Clause-NetBSD AND BSD-3-Clause */
-/*	$NetBSD: qat_hw17var.h,v 1.1 2019/11/20 09:37:46 hikaru Exp $	*/
-
-/*
- * Copyright (c) 2019 Internet Initiative Japan, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-/*
- *   Copyright(c) 2014 Intel Corporation.
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions
- *   are met:
- *
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in
- *       the documentation and/or other materials provided with the
- *       distribution.
- *     * Neither the name of Intel Corporation nor the names of its
- *       contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/* $FreeBSD$ */
-
-#ifndef _DEV_PCI_QAT_HW17VAR_H_
-#define _DEV_PCI_QAT_HW17VAR_H_
-
-CTASSERT(CONTENT_DESC_MAX_SIZE >=
-    roundup(sizeof(union hw_cipher_algo_blk), 8) +
-    roundup(sizeof(union hw_auth_algo_blk), 8));
-
-int		qat_adm_mailbox_init(struct qat_softc *);
-int		qat_adm_mailbox_send_init(struct qat_softc *);
-int		qat_arb_init(struct qat_softc *);
-int		qat_set_ssm_wdtimer(struct qat_softc *);
-int		qat_check_slice_hang(struct qat_softc *);
-
-void		qat_hw17_crypto_setup_desc(struct qat_crypto *,
-		    struct qat_session *, struct qat_crypto_desc *);
-void		qat_hw17_crypto_setup_req_params(struct qat_crypto_bank *,
-		    struct qat_session *, struct qat_crypto_desc const *,
-		    struct qat_sym_cookie *, struct cryptop *);
-
-#endif
diff --git a/sys/dev/qat/qat.c b/sys/dev/qat_c2xxx/qat.c
index 02da9024de64..5f131c715844 100644
--- a/sys/dev/qat/qat.c
+++ b/sys/dev/qat_c2xxx/qat.c
@@ -92,21 +92,9 @@ __KERNEL_RCSID(0, "$NetBSD: qat.c,v 1.6 2020/06/14 23:23:12 riastradh Exp $");
 #include "qat_aevar.h"
 
 extern struct qat_hw qat_hw_c2xxx;
-extern struct qat_hw qat_hw_c3xxx;
-extern struct qat_hw qat_hw_c62x;
-extern struct qat_hw qat_hw_d15xx;
-extern struct qat_hw qat_hw_dh895xcc;
 
 #define PCI_VENDOR_INTEL			0x8086
 #define PCI_PRODUCT_INTEL_C2000_IQIA_PHYS	0x1f18
-#define PCI_PRODUCT_INTEL_C3K_QAT		0x19e2
-#define PCI_PRODUCT_INTEL_C3K_QAT_VF		0x19e3
-#define PCI_PRODUCT_INTEL_C620_QAT		0x37c8
-#define PCI_PRODUCT_INTEL_C620_QAT_VF		0x37c9
-#define PCI_PRODUCT_INTEL_XEOND_QAT		0x6f54
-#define PCI_PRODUCT_INTEL_XEOND_QAT_VF		0x6f55
-#define PCI_PRODUCT_INTEL_DH895XCC_QAT		0x0435
-#define PCI_PRODUCT_INTEL_DH895XCC_QAT_VF	0x0443
 
 static const struct qat_product {
 	uint16_t qatp_vendor;
@@ -118,18 +106,6 @@ static const struct qat_product {
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_C2000_IQIA_PHYS,
 	  "Intel C2000 QuickAssist PF",
 	  QAT_CHIP_C2XXX, &qat_hw_c2xxx },
-	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_C3K_QAT,
-	  "Intel C3000 QuickAssist PF",
-	  QAT_CHIP_C3XXX, &qat_hw_c3xxx },
-	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_C620_QAT,
-	  "Intel C620/Xeon D-2100 QuickAssist PF",
-	  QAT_CHIP_C62X, &qat_hw_c62x },
-	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_XEOND_QAT,
-	  "Intel Xeon D-1500 QuickAssist PF",
-	  QAT_CHIP_D15XX, &qat_hw_d15xx },
-	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_DH895XCC_QAT,
-	  "Intel 8950 QuickAssist PCIe Adapter PF",
-	  QAT_CHIP_DH895XCC, &qat_hw_dh895xcc },
 	{ 0, 0, NULL, 0, NULL },
 };
 
@@ -2283,12 +2259,12 @@ static device_method_t qat_methods[] = {
 };
 
 static driver_t qat_driver = {
-	.name		= "qat",
+	.name		= "qat_c2xxx",
 	.methods	= qat_methods,
 	.size		= sizeof(struct qat_softc),
 };
 
-DRIVER_MODULE(qat, pci, qat_driver, 0, 0);
-MODULE_VERSION(qat, 1);
-MODULE_DEPEND(qat, crypto, 1, 1, 1);
-MODULE_DEPEND(qat, pci, 1, 1, 1);
+DRIVER_MODULE(qat_c2xxx, pci, qat_driver, 0, 0);
+MODULE_VERSION(qat_c2xxx, 1);
+MODULE_DEPEND(qat_c2xxx, crypto, 1, 1, 1);
+MODULE_DEPEND(qat_c2xxx, pci, 1, 1, 1);
diff --git a/sys/dev/qat/qat_ae.c b/sys/dev/qat_c2xxx/qat_ae.c
index 853069706079..853069706079 100644
--- a/sys/dev/qat/qat_ae.c
+++ b/sys/dev/qat_c2xxx/qat_ae.c
diff --git a/sys/dev/qat/qat_aevar.h b/sys/dev/qat_c2xxx/qat_aevar.h
index 4aea6a5f8e99..4aea6a5f8e99 100644
--- a/sys/dev/qat/qat_aevar.h
+++ b/sys/dev/qat_c2xxx/qat_aevar.h
diff --git a/sys/dev/qat/qat_c2xxx.c b/sys/dev/qat_c2xxx/qat_c2xxx.c
index 60ddafe07576..60ddafe07576 100644
--- a/sys/dev/qat/qat_c2xxx.c
+++ b/sys/dev/qat_c2xxx/qat_c2xxx.c
diff --git a/sys/dev/qat/qat_c2xxxreg.h b/sys/dev/qat_c2xxx/qat_c2xxxreg.h
index f3190cf27d2e..f3190cf27d2e 100644
--- a/sys/dev/qat/qat_c2xxxreg.h
+++ b/sys/dev/qat_c2xxx/qat_c2xxxreg.h
diff --git a/sys/dev/qat/qat_hw15.c b/sys/dev/qat_c2xxx/qat_hw15.c
index aab5be9b647d..aab5be9b647d 100644
--- a/sys/dev/qat/qat_hw15.c
+++ b/sys/dev/qat_c2xxx/qat_hw15.c
diff --git a/sys/dev/qat/qat_hw15reg.h b/sys/dev/qat_c2xxx/qat_hw15reg.h
index df3fa14a0d85..df3fa14a0d85 100644
--- a/sys/dev/qat/qat_hw15reg.h
+++ b/sys/dev/qat_c2xxx/qat_hw15reg.h
diff --git a/sys/dev/qat/qat_hw15var.h b/sys/dev/qat_c2xxx/qat_hw15var.h
index 4939aba7ff12..4939aba7ff12 100644
--- a/sys/dev/qat/qat_hw15var.h
+++ b/sys/dev/qat_c2xxx/qat_hw15var.h
diff --git a/sys/dev/qat/qatreg.h b/sys/dev/qat_c2xxx/qatreg.h
index 076354fc6108..076354fc6108 100644
--- a/sys/dev/qat/qatreg.h
+++ b/sys/dev/qat_c2xxx/qatreg.h
diff --git a/sys/dev/qat/qatvar.h b/sys/dev/qat_c2xxx/qatvar.h
index 284b4c27fa05..284b4c27fa05 100644
--- a/sys/dev/qat/qatvar.h
+++ b/sys/dev/qat_c2xxx/qatvar.h
diff --git a/sys/modules/Makefile b/sys/modules/Makefile
index d624df4c4e0e..74dab4e6fa6d 100644
--- a/sys/modules/Makefile
+++ b/sys/modules/Makefile
@@ -307,7 +307,7 @@ SUBDIR=	\
 	pty  \
 	puc \
 	pwm \
-	${_qat} \
+	${_qat_c2xxx} \
 	${_qatfw} \
 	${_qlxge} \
 	${_qlxgb} \
@@ -681,7 +681,7 @@ _mgb=		mgb
 _nctgpio=	nctgpio
 _ntb=		ntb
 _ocs_fc=	ocs_fc
-_qat=		qat
+_qat_c2xxx=	qat_c2xxx
 _qatfw=		qatfw
 .if ${MK_OFED} != "no" || defined(ALL_MODULES)
 _rdma=		rdma
diff --git a/sys/modules/qat/Makefile b/sys/modules/qat_c2xxx/Makefile
index 57301b5b78e3..88d63282d345 100644
--- a/sys/modules/qat/Makefile
+++ b/sys/modules/qat_c2xxx/Makefile
@@ -1,18 +1,13 @@
 # $FreeBSD$
 
-.PATH:	${SRCTOP}/sys/dev/qat
+.PATH:	${SRCTOP}/sys/dev/qat_c2xxx
 
-KMOD=	qat
+KMOD=	qat_c2xxx
 
 SRCS=	qat.c		\
 	qat_ae.c	\
 	qat_c2xxx.c	\
-	qat_c3xxx.c	\
-	qat_c62x.c	\
-	qat_d15xx.c	\
-	qat_dh895xcc.c	\
-	qat_hw15.c	\
-	qat_hw17.c
+	qat_hw15.c
 
 SRCS+=	bus_if.h cryptodev_if.h device_if.h pci_if.h
 
diff --git a/sys/modules/qatfw/Makefile b/sys/modules/qatfw/Makefile
index f6bbe662eee8..e043fd390d2a 100644
--- a/sys/modules/qatfw/Makefile
+++ b/sys/modules/qatfw/Makefile
@@ -1,9 +1,5 @@
 # $FreeBSD$
 
-SUBDIR=	qat_c2xxx \
-	qat_c3xxx \
-	qat_c62x \
-	qat_d15xx \
-	qat_dh895xcc
+SUBDIR=	qat_c2xxx
 
 .include <bsd.subdir.mk>
diff --git a/sys/modules/qatfw/qat_c3xxx/Makefile b/sys/modules/qatfw/qat_c3xxx/Makefile
deleted file mode 100644
index 7e2efadbefd8..000000000000
--- a/sys/modules/qatfw/qat_c3xxx/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-# $FreeBSD$
-
-.PATH: ${SRCTOP}/sys/contrib/dev/qat
-
-KMOD=	qat_c3xxxfw
-IMG1=	qat_c3xxx
-IMG2=	qat_c3xxx_mmp
-
-FIRMWS=	${IMG1}.bin:${KMOD}:111 ${IMG2}.bin:${IMG2}:111
-
-.include <bsd.kmod.mk>
diff --git a/sys/modules/qatfw/qat_c62x/Makefile b/sys/modules/qatfw/qat_c62x/Makefile
deleted file mode 100644
index e2dc67f54319..000000000000
--- a/sys/modules/qatfw/qat_c62x/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-# $FreeBSD$
-
-.PATH: ${SRCTOP}/sys/contrib/dev/qat
-
-KMOD=	qat_c62xfw
-IMG1=	qat_c62x
-IMG2=	qat_c62x_mmp
-
-FIRMWS=	${IMG1}.bin:${KMOD}:111 ${IMG2}.bin:${IMG2}:111
-
-.include <bsd.kmod.mk>
diff --git a/sys/modules/qatfw/qat_d15xx/Makefile b/sys/modules/qatfw/qat_d15xx/Makefile
deleted file mode 100644
index d9a2f384f865..000000000000
--- a/sys/modules/qatfw/qat_d15xx/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-# $FreeBSD$
-
-.PATH: ${SRCTOP}/sys/contrib/dev/qat
-
-KMOD=	qat_d15xxfw
-IMG1=	qat_d15xx
-IMG2=	qat_d15xx_mmp
-
-FIRMWS=	${IMG1}.bin:${KMOD}:111 ${IMG2}.bin:${IMG2}:111
-
-.include <bsd.kmod.mk>
diff --git a/sys/modules/qatfw/qat_dh895xcc/Makefile b/sys/modules/qatfw/qat_dh895xcc/Makefile
deleted file mode 100644
index be86b33aa675..000000000000
--- a/sys/modules/qatfw/qat_dh895xcc/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-# $FreeBSD$
-
-.PATH: ${SRCTOP}/sys/contrib/dev/qat
-
-KMOD=	qat_dh895xccfw
-IMG1=	qat_895xcc
-IMG2=	qat_895xcc_mmp
-
-FIRMWS=	${IMG1}.bin:${KMOD}:111 ${IMG2}.bin:${IMG2}:111
-
-.include <bsd.kmod.mk>