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| author | Andrew Turner <andrew@FreeBSD.org> | 2016-07-27 10:33:45 +0000 |
|---|---|---|
| committer | Andrew Turner <andrew@FreeBSD.org> | 2016-07-27 10:33:45 +0000 |
| commit | c7716441be3a4a48aa7b7cdf69a15625c1cd8ef5 (patch) | |
| tree | 2a59dacd09463974e72f84b0e05f237b0ba3f57b /Bindings/arc | |
| parent | 235ad806ee815395bce54dc1b0ce1c06cd29b44a (diff) | |
| download | src-c7716441be3a4a48aa7b7cdf69a15625c1cd8ef5.tar.gz src-c7716441be3a4a48aa7b7cdf69a15625c1cd8ef5.zip | |
Import the updated devicetree files fromvendor/device-tree/devicetree-965f3718
Notes
Notes:
svn path=/vendor/device-tree/dist/; revision=303380
svn path=/vendor/device-tree/devicetree-965f3718/; revision=303381; tag=vendor/device-tree/devicetree-965f3718
Diffstat (limited to 'Bindings/arc')
| -rw-r--r-- | Bindings/arc/archs-pct.txt | 2 | ||||
| -rw-r--r-- | Bindings/arc/eznps.txt | 7 | ||||
| -rw-r--r-- | Bindings/arc/pct.txt | 2 |
3 files changed, 9 insertions, 2 deletions
diff --git a/Bindings/arc/archs-pct.txt b/Bindings/arc/archs-pct.txt index 1ae98b87c640..e4b9dcee6d41 100644 --- a/Bindings/arc/archs-pct.txt +++ b/Bindings/arc/archs-pct.txt @@ -2,7 +2,7 @@ The ARC HS can be configured with a pipeline performance monitor for counting CPU and cache events like cache misses and hits. Like conventional PCT there -are 100+ hardware conditions dynamically mapped to upto 32 counters. +are 100+ hardware conditions dynamically mapped to up to 32 counters. It also supports overflow interrupts. Required properties: diff --git a/Bindings/arc/eznps.txt b/Bindings/arc/eznps.txt new file mode 100644 index 000000000000..1aa50c640678 --- /dev/null +++ b/Bindings/arc/eznps.txt @@ -0,0 +1,7 @@ +EZchip NPS Network Processor Platforms Device Tree Bindings +--------------------------------------------------------------------------- + +Appliance main board with NPS400 ASIC. + +Required root node properties: + - compatible = "ezchip,arc-nps"; diff --git a/Bindings/arc/pct.txt b/Bindings/arc/pct.txt index 7b9588444f20..4e874d9a38a6 100644 --- a/Bindings/arc/pct.txt +++ b/Bindings/arc/pct.txt @@ -2,7 +2,7 @@ The ARC700 can be configured with a pipeline performance monitor for counting CPU and cache events like cache misses and hits. Like conventional PCT there -are 100+ hardware conditions dynamically mapped to upto 32 counters +are 100+ hardware conditions dynamically mapped to up to 32 counters Note that: * The ARC 700 PCT does not support interrupts; although HW events may be |