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author | Emmanuel Vadot <manu@FreeBSD.org> | 2019-05-08 19:00:46 +0000 |
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committer | Emmanuel Vadot <manu@FreeBSD.org> | 2019-05-08 19:00:46 +0000 |
commit | 0db636cb5e9747c177d4fe9ae36c20987819a1b6 (patch) | |
tree | b45f33ee0918192a1d0373c223d19aa906875c98 /Bindings/cpufreq | |
parent | 2131505c51f1ac8ac0a6db71efcda1b4bd61084b (diff) | |
download | src-0db636cb5e9747c177d4fe9ae36c20987819a1b6.tar.gz src-0db636cb5e9747c177d4fe9ae36c20987819a1b6.zip |
Import Linux 5.1 DTS filesvendor/device-tree/5.1
Notes
Notes:
svn path=/vendor/device-tree/dist/; revision=347363
svn path=/vendor/device-tree/5.1/; revision=347364; tag=vendor/device-tree/5.1
Diffstat (limited to 'Bindings/cpufreq')
-rw-r--r-- | Bindings/cpufreq/nvidia,tegra124-cpufreq.txt | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/Bindings/cpufreq/nvidia,tegra124-cpufreq.txt b/Bindings/cpufreq/nvidia,tegra124-cpufreq.txt index b1669fbfb740..03196d5ea515 100644 --- a/Bindings/cpufreq/nvidia,tegra124-cpufreq.txt +++ b/Bindings/cpufreq/nvidia,tegra124-cpufreq.txt @@ -9,11 +9,9 @@ Required properties: See ../clocks/clock-bindings.txt for details. - clock-names: Must include the following entries: - cpu_g: Clock mux for the fast CPU cluster. - - cpu_lp: Clock mux for the low-power CPU cluster. - pll_x: Fast PLL clocksource. - pll_p: Auxiliary PLL used during fast PLL rate changes. - dfll: Fast DFLL clocksource that also automatically scales CPU voltage. -- vdd-cpu-supply: Regulator for CPU voltage Optional properties: - clock-latency: Specify the possible maximum transition latency for clock, @@ -31,13 +29,11 @@ cpus { reg = <0>; clocks = <&tegra_car TEGRA124_CLK_CCLK_G>, - <&tegra_car TEGRA124_CLK_CCLK_LP>, <&tegra_car TEGRA124_CLK_PLL_X>, <&tegra_car TEGRA124_CLK_PLL_P>, <&dfll>; - clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll"; + clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; clock-latency = <300000>; - vdd-cpu-supply: <&vdd_cpu>; }; <...> |