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author | Andrew Turner <andrew@FreeBSD.org> | 2016-07-27 10:33:45 +0000 |
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committer | Andrew Turner <andrew@FreeBSD.org> | 2016-07-27 10:33:45 +0000 |
commit | c7716441be3a4a48aa7b7cdf69a15625c1cd8ef5 (patch) | |
tree | 2a59dacd09463974e72f84b0e05f237b0ba3f57b /Bindings/gpio/gpio-pisosr.txt | |
parent | 235ad806ee815395bce54dc1b0ce1c06cd29b44a (diff) | |
download | src-c7716441be3a4a48aa7b7cdf69a15625c1cd8ef5.tar.gz src-c7716441be3a4a48aa7b7cdf69a15625c1cd8ef5.zip |
Import the updated devicetree files fromvendor/device-tree/devicetree-965f3718
Notes
Notes:
svn path=/vendor/device-tree/dist/; revision=303380
svn path=/vendor/device-tree/devicetree-965f3718/; revision=303381; tag=vendor/device-tree/devicetree-965f3718
Diffstat (limited to 'Bindings/gpio/gpio-pisosr.txt')
-rw-r--r-- | Bindings/gpio/gpio-pisosr.txt | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/Bindings/gpio/gpio-pisosr.txt b/Bindings/gpio/gpio-pisosr.txt new file mode 100644 index 000000000000..414a01cdf715 --- /dev/null +++ b/Bindings/gpio/gpio-pisosr.txt @@ -0,0 +1,34 @@ +Generic Parallel-in/Serial-out Shift Register GPIO Driver + +This binding describes generic parallel-in/serial-out shift register +devices that can be used for GPI (General Purpose Input). This includes +SN74165 serial-out shift registers and the SN65HVS88x series of +industrial serializers. + +Required properties: + - compatible : Should be "pisosr-gpio". + - gpio-controller : Marks the device node as a GPIO controller. + - #gpio-cells : Should be two. For consumer use see gpio.txt. + +Optional properties: + - ngpios : Number of used GPIO lines (0..n-1), default is 8. + - load-gpios : GPIO pin specifier attached to load enable, this + pin is pulsed before reading from the device to + load input pin values into the the device. + +For other required and optional properties of SPI slave +nodes please refer to ../spi/spi-bus.txt. + +Example: + + gpio@0 { + compatible = "ti,sn65hvs882", "pisosr-gpio"; + gpio-controller; + #gpio-cells = <2>; + + load-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; + + reg = <0>; + spi-max-frequency = <1000000>; + spi-cpol; + }; |