diff options
author | Emmanuel Vadot <manu@FreeBSD.org> | 2017-03-07 12:41:06 +0000 |
---|---|---|
committer | Emmanuel Vadot <manu@FreeBSD.org> | 2017-03-07 12:41:06 +0000 |
commit | ff018dbf5bb142aa83bd955e5b6c55d66e9e9c1e (patch) | |
tree | 5cd0b74d984dae06ea54b6b09998163538d3c162 /Bindings/reset/uniphier-reset.txt | |
parent | c7716441be3a4a48aa7b7cdf69a15625c1cd8ef5 (diff) | |
download | src-ff018dbf5bb142aa83bd955e5b6c55d66e9e9c1e.tar.gz src-ff018dbf5bb142aa83bd955e5b6c55d66e9e9c1e.zip |
Update to Linux 4.10vendor/device-tree/4.10
Notes
Notes:
svn path=/vendor/device-tree/dist/; revision=314847
svn path=/vendor/device-tree/4.10/; revision=314848; tag=vendor/device-tree/4.10
Diffstat (limited to 'Bindings/reset/uniphier-reset.txt')
-rw-r--r-- | Bindings/reset/uniphier-reset.txt | 93 |
1 files changed, 93 insertions, 0 deletions
diff --git a/Bindings/reset/uniphier-reset.txt b/Bindings/reset/uniphier-reset.txt new file mode 100644 index 000000000000..5020524cddeb --- /dev/null +++ b/Bindings/reset/uniphier-reset.txt @@ -0,0 +1,93 @@ +UniPhier reset controller + + +System reset +------------ + +Required properties: +- compatible: should be one of the following: + "socionext,uniphier-sld3-reset" - for sLD3 SoC. + "socionext,uniphier-ld4-reset" - for LD4 SoC. + "socionext,uniphier-pro4-reset" - for Pro4 SoC. + "socionext,uniphier-sld8-reset" - for sLD8 SoC. + "socionext,uniphier-pro5-reset" - for Pro5 SoC. + "socionext,uniphier-pxs2-reset" - for PXs2/LD6b SoC. + "socionext,uniphier-ld11-reset" - for LD11 SoC. + "socionext,uniphier-ld20-reset" - for LD20 SoC. +- #reset-cells: should be 1. + +Example: + + sysctrl@61840000 { + compatible = "socionext,uniphier-ld11-sysctrl", + "simple-mfd", "syscon"; + reg = <0x61840000 0x4000>; + + reset { + compatible = "socionext,uniphier-ld11-reset"; + #reset-cells = <1>; + }; + + other nodes ... + }; + + +Media I/O (MIO) reset, SD reset +------------------------------- + +Required properties: +- compatible: should be one of the following: + "socionext,uniphier-sld3-mio-reset" - for sLD3 SoC. + "socionext,uniphier-ld4-mio-reset" - for LD4 SoC. + "socionext,uniphier-pro4-mio-reset" - for Pro4 SoC. + "socionext,uniphier-sld8-mio-reset" - for sLD8 SoC. + "socionext,uniphier-pro5-sd-reset" - for Pro5 SoC. + "socionext,uniphier-pxs2-sd-reset" - for PXs2/LD6b SoC. + "socionext,uniphier-ld11-mio-reset" - for LD11 SoC. + "socionext,uniphier-ld20-sd-reset" - for LD20 SoC. +- #reset-cells: should be 1. + +Example: + + mioctrl@59810000 { + compatible = "socionext,uniphier-ld11-mioctrl", + "simple-mfd", "syscon"; + reg = <0x59810000 0x800>; + + reset { + compatible = "socionext,uniphier-ld11-mio-reset"; + #reset-cells = <1>; + }; + + other nodes ... + }; + + +Peripheral reset +---------------- + +Required properties: +- compatible: should be one of the following: + "socionext,uniphier-ld4-peri-reset" - for LD4 SoC. + "socionext,uniphier-pro4-peri-reset" - for Pro4 SoC. + "socionext,uniphier-sld8-peri-reset" - for sLD8 SoC. + "socionext,uniphier-pro5-peri-reset" - for Pro5 SoC. + "socionext,uniphier-pxs2-peri-reset" - for PXs2/LD6b SoC. + "socionext,uniphier-ld11-peri-reset" - for LD11 SoC. + "socionext,uniphier-ld20-peri-reset" - for LD20 SoC. +- #reset-cells: should be 1. + +Example: + + perictrl@59820000 { + compatible = "socionext,uniphier-ld11-perictrl", + "simple-mfd", "syscon"; + reg = <0x59820000 0x200>; + + reset { + compatible = "socionext,uniphier-ld11-peri-reset"; + #reset-cells = <1>; + }; + + other nodes ... + }; |