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author | Emmanuel Vadot <manu@FreeBSD.org> | 2020-02-28 15:14:48 +0000 |
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committer | Emmanuel Vadot <manu@FreeBSD.org> | 2020-02-28 15:14:48 +0000 |
commit | 995ee34fd27211af598f9adf111cb49609d1b3de (patch) | |
tree | 26bf77523200f7648333ede47840b29088cf66eb /Bindings/spi/st,stm32-qspi.yaml | |
parent | c3f1cfc76c9a579767282ac81d2be1cfb20aea92 (diff) | |
download | src-32c279be1a5855839d9de2624cfc67c9f20599c2.tar.gz src-32c279be1a5855839d9de2624cfc67c9f20599c2.zip |
DTS: Update the device-tree files to Linux 5.5vendor/device-tree/5.5
Diffstat (limited to 'Bindings/spi/st,stm32-qspi.yaml')
-rw-r--r-- | Bindings/spi/st,stm32-qspi.yaml | 83 |
1 files changed, 83 insertions, 0 deletions
diff --git a/Bindings/spi/st,stm32-qspi.yaml b/Bindings/spi/st,stm32-qspi.yaml new file mode 100644 index 000000000000..3665a5fe6b7f --- /dev/null +++ b/Bindings/spi/st,stm32-qspi.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/st,stm32-qspi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 Quad Serial Peripheral Interface (QSPI) bindings + +maintainers: + - Christophe Kerello <christophe.kerello@st.com> + - Patrice Chotard <patrice.chotard@st.com> + +allOf: + - $ref: "spi-controller.yaml#" + +properties: + compatible: + const: st,stm32f469-qspi + + reg: + items: + - description: registers + - description: memory mapping + + reg-names: + items: + - const: qspi + - const: qspi_mm + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + + resets: + maxItems: 1 + + dmas: + items: + - description: tx DMA channel + - description: rx DMA channel + + dma-names: + items: + - const: tx + - const: rx + +required: + - compatible + - reg + - reg-names + - clocks + - interrupts + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/stm32mp1-clks.h> + #include <dt-bindings/reset/stm32mp1-resets.h> + spi@58003000 { + compatible = "st,stm32f469-qspi"; + reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; + reg-names = "qspi", "qspi_mm"; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&mdma1 22 0x10 0x100002 0x0 0x0>, + <&mdma1 22 0x10 0x100008 0x0 0x0>; + dma-names = "tx", "rx"; + clocks = <&rcc QSPI_K>; + resets = <&rcc QSPI_R>; + + #address-cells = <1>; + #size-cells = <0>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; + }; + }; + +... |