diff options
| author | Warner Losh <imp@FreeBSD.org> | 2025-04-23 18:02:54 +0000 |
|---|---|---|
| committer | Warner Losh <imp@FreeBSD.org> | 2025-04-23 18:02:54 +0000 |
| commit | 8f6bda97a4734bec74d5787766b177112dc8a3f5 (patch) | |
| tree | 36b30c90ce307f59ff198416fe65bb1c405e68f3 /MdePkg/Include | |
| parent | 5d8674f2bdd536124b1dd026dfa729a1376b3cac (diff) | |
Import edk2 edk2-stable202502 (hash fbe0805b2091393406952e84724188f8c1941837)vendor/edk2/edk2-stable202502vendor/edk2
Bring in the latest stable branch for updated defines (especailly
Loongson). Remove ^M as described in sys/contrib/edk2/FREEBSD-upgrade.
Not the absolute latest, but aligned to the edk2-stable202502 tag.
Sponsored by: Netflix
Diffstat (limited to 'MdePkg/Include')
31 files changed, 2422 insertions, 194 deletions
diff --git a/MdePkg/Include/AArch64/AArch64.h b/MdePkg/Include/AArch64/AArch64.h index 58f884627780..e6b93b71cf68 100644 --- a/MdePkg/Include/AArch64/AArch64.h +++ b/MdePkg/Include/AArch64/AArch64.h @@ -66,6 +66,7 @@ #define ARM_HCR_AMO BIT5 #define ARM_HCR_TSC BIT19 #define ARM_HCR_TGE BIT27 +#define ARM_HCR_E2H BIT34 // Exception Syndrome Register #define AARCH64_ESR_EC(Ecr) ((0x3F << 26) & (Ecr)) @@ -129,6 +130,10 @@ // build for ARMv8.0, we need to define the register here. #define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 +// The RNDR register is not recognized by older assemblers, +// so we need to define it here +#define RNDR S3_3_C2_C4_0 + #define VECTOR_BASE(tbl) \ .section .text.##tbl##,"ax"; \ .align 11; \ diff --git a/MdePkg/Include/AArch64/AArch64Mmu.h b/MdePkg/Include/AArch64/AArch64Mmu.h index 0d9f98b63077..138857089526 100644 --- a/MdePkg/Include/AArch64/AArch64Mmu.h +++ b/MdePkg/Include/AArch64/AArch64Mmu.h @@ -67,6 +67,7 @@ #define TT_NS BIT5 #define TT_AF BIT10 +#define TT_NG BIT11 #define TT_SH_NON_SHAREABLE (0x0 << 8) #define TT_SH_OUTER_SHAREABLE (0x2 << 8) diff --git a/MdePkg/Include/Base.h b/MdePkg/Include/Base.h index 72bf6f31366a..6989b10f9e0b 100644 --- a/MdePkg/Include/Base.h +++ b/MdePkg/Include/Base.h @@ -800,12 +800,12 @@ typedef UINTN *BASE_LIST; @param Message Raised compiler diagnostic message when expression is false. **/ -#ifdef MDE_CPU_EBC -#define STATIC_ASSERT(Expression, Message) -#elif defined (_MSC_EXTENSIONS) || defined (__cplusplus) +#if defined (__cplusplus) #define STATIC_ASSERT static_assert -#else +#elif defined (__GNUC__) || defined (__clang__) #define STATIC_ASSERT _Static_assert +#elif defined (_MSC_EXTENSIONS) +#define STATIC_ASSERT static_assert #endif // @@ -888,7 +888,7 @@ STATIC_ASSERT (ALIGNOF (__VERIFY_INT32_ENUM_SIZE) == sizeof (__VERIFY_INT32_ENUM @return A pointer to the structure from one of it's elements. **/ -#define BASE_CR(Record, TYPE, Field) ((TYPE *) ((CHAR8 *) (Record) - OFFSET_OF (TYPE, Field))) +#define BASE_CR(Record, TYPE, Field) ((TYPE *) (VOID *) ((CHAR8 *) (Record) - OFFSET_OF (TYPE, Field))) /** Checks whether a value is a power of two. diff --git a/MdePkg/Include/Guid/ImageAuthentication.h b/MdePkg/Include/Guid/ImageAuthentication.h index f4c472d75a59..47489cc82328 100644 --- a/MdePkg/Include/Guid/ImageAuthentication.h +++ b/MdePkg/Include/Guid/ImageAuthentication.h @@ -123,6 +123,19 @@ typedef struct { EFI_TIME TimeOfRevocation; } EFI_CERT_X509_SHA512; +typedef UINT8 EFI_SM3_HASH[32]; + +typedef struct { + /// + /// The SM3 hash of an X.509 certificate's To-Be-Signed contents. + /// + EFI_SM3_HASH ToBeSignedHash; + /// + /// The time that the certificate shall be considered to be revoked. + /// + EFI_TIME TimeOfRevocation; +} EFI_CERT_X509_SM3; + #pragma pack() /// @@ -167,6 +180,15 @@ typedef struct { } /// +/// This identifies a signature containing a SM3 hash. The SignatureSize shall always +/// be 16 (size of SignatureOwner component) + 32 bytes. +/// +#define EFI_CERT_SM3_GUID \ + { \ + 0x57347f87, 0x7a9b, 0x403a, { 0xb9, 0x3c, 0xdc, 0x4a, 0xfb, 0x7a, 0xe, 0xbc } \ + } + +/// /// TThis identifies a signature containing a RSA-2048 signature of a SHA-1 hash. The /// SignatureHeader size shall always be 0. The SignatureSize shall always be 16 (size of /// SignatureOwner component) + 256 bytes. @@ -191,6 +213,19 @@ typedef struct { } /// +/// This identifies a signature containing the SM3 hash of an X.509 certificate's To-Be-Signed +/// contents, and a time of revocation. The SignatureHeader size shall always be 0. The +/// SignatureSize shall always be 16 (size of the SignatureOwner component) + 32 bytes for +/// an EFI_CERT_X509_SM3 structure. If the TimeOfRevocation is non-zero, the certificate should +/// be considered to be revoked from that time and onwards, and otherwise the certificate shall +/// be considered to always be revoked. +/// +#define EFI_CERT_X509_SM3_GUID \ + { \ + 0x60d807e5, 0x10b4, 0x49a9, {0x93, 0x31, 0xe4, 0x4, 0x37, 0x88, 0x8d, 0x37 } \ + } + +/// /// This identifies a signature containing a SHA-224 hash. The SignatureHeader size shall /// always be 0. The SignatureSize shall always be 16 (size of SignatureOwner component) + /// 28 bytes. @@ -344,5 +379,7 @@ extern EFI_GUID gEfiCertX509Sha256Guid; extern EFI_GUID gEfiCertX509Sha384Guid; extern EFI_GUID gEfiCertX509Sha512Guid; extern EFI_GUID gEfiCertPkcs7Guid; +extern EFI_GUID gEfiCertSm3Guid; +extern EFI_GUID gEfiCertX509Sm3Guid; #endif diff --git a/MdePkg/Include/Guid/Rng.h b/MdePkg/Include/Guid/Rng.h new file mode 100644 index 000000000000..acf0895b2b0d --- /dev/null +++ b/MdePkg/Include/Guid/Rng.h @@ -0,0 +1,155 @@ +/** @file + Random Number Generator (RNG) GUIDs and structures shared across RNG interfaces. + + Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR> + Copyright (c) Microsoft Corporation. + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef RNG_GUID_H_ +#define RNG_GUID_H_ + +typedef struct _EFI_RNG_INTERFACE EFI_RNG_INTERFACE; + +/// +/// A selection of EFI_RNG_PROTOCOL algorithms. +/// The algorithms listed are optional, not meant to be exhaustive and be argmented by +/// vendors or other industry standards. +/// +typedef EFI_GUID EFI_RNG_ALGORITHM; + +/// +/// The algorithms corresponds to SP800-90 as defined in +/// NIST SP 800-90, "Recommendation for Random Number Generation Using Deterministic Random +/// Bit Generators", March 2007. +/// +#define EFI_RNG_ALGORITHM_SP800_90_HASH_256_GUID \ + { \ + 0xa7af67cb, 0x603b, 0x4d42, {0xba, 0x21, 0x70, 0xbf, 0xb6, 0x29, 0x3f, 0x96 } \ + } +#define EFI_RNG_ALGORITHM_SP800_90_HMAC_256_GUID \ + { \ + 0xc5149b43, 0xae85, 0x4f53, {0x99, 0x82, 0xb9, 0x43, 0x35, 0xd3, 0xa9, 0xe7 } \ + } +#define EFI_RNG_ALGORITHM_SP800_90_CTR_256_GUID \ + { \ + 0x44f0de6e, 0x4d8c, 0x4045, {0xa8, 0xc7, 0x4d, 0xd1, 0x68, 0x85, 0x6b, 0x9e } \ + } + +/// +/// The algorithms correspond to X9.31 as defined in +/// NIST, "Recommended Random Number Generator Based on ANSI X9.31 Appendix A.2.4 Using +/// the 3-Key Triple DES and AES Algorithm", January 2005. +/// +#define EFI_RNG_ALGORITHM_X9_31_3DES_GUID \ + { \ + 0x63c4785a, 0xca34, 0x4012, {0xa3, 0xc8, 0x0b, 0x6a, 0x32, 0x4f, 0x55, 0x46 } \ + } +#define EFI_RNG_ALGORITHM_X9_31_AES_GUID \ + { \ + 0xacd03321, 0x777e, 0x4d3d, {0xb1, 0xc8, 0x20, 0xcf, 0xd8, 0x88, 0x20, 0xc9 } \ + } + +/// +/// The "raw" algorithm, when supported, is intended to provide entropy directly from +/// the source, without it going through some deterministic random bit generator. +/// +#define EFI_RNG_ALGORITHM_RAW \ + { \ + 0xe43176d7, 0xb6e8, 0x4827, {0xb7, 0x84, 0x7f, 0xfd, 0xc4, 0xb6, 0x85, 0x61 } \ + } + +/// +/// The Arm Architecture states the RNDR that the DRBG algorithm should be compliant +/// with NIST SP800-90A, while not mandating a particular algorithm, so as to be +/// inclusive of different geographies. +/// +#define EFI_RNG_ALGORITHM_ARM_RNDR \ + { \ + 0x43d2fde3, 0x9d4e, 0x4d79, {0x02, 0x96, 0xa8, 0x9b, 0xca, 0x78, 0x08, 0x41} \ + } + +/** + Returns information about the random number generation implementation. + + @param[in] This A pointer to this interface instance. + @param[in,out] RNGAlgorithmListSize On input, the size in bytes of RNGAlgorithmList. + On output with a return code of EFI_SUCCESS, the size + in bytes of the data returned in RNGAlgorithmList. On output + with a return code of EFI_BUFFER_TOO_SMALL, + the size of RNGAlgorithmList required to obtain the list. + @param[out] RNGAlgorithmList A caller-allocated memory buffer filled by the driver + with one EFI_RNG_ALGORITHM element for each supported + RNG algorithm. The list must not change across multiple + calls to the same driver. The first algorithm in the list + is the default algorithm for the driver. + + @retval EFI_SUCCESS The RNG algorithm list was returned successfully. + @retval EFI_UNSUPPORTED The services is not supported by this driver. + @retval EFI_DEVICE_ERROR The list of algorithms could not be retrieved due to a + hardware or firmware error. + @retval EFI_INVALID_PARAMETER One or more of the parameters are incorrect. + @retval EFI_BUFFER_TOO_SMALL The buffer RNGAlgorithmList is too small to hold the result. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_RNG_GET_INFO)( + IN EFI_RNG_INTERFACE *This, + IN OUT UINTN *RNGAlgorithmListSize, + OUT EFI_RNG_ALGORITHM *RNGAlgorithmList + ); + +/** + Produces and returns an RNG value using either the default or specified RNG algorithm. + + @param[in] This A pointer to this interface instance. + @param[in] RNGAlgorithm A pointer to the EFI_RNG_ALGORITHM that identifies the RNG + algorithm to use. May be NULL in which case the function will + use its default RNG algorithm. + @param[in] RNGValueLength The length in bytes of the memory buffer pointed to by + RNGValue. The driver shall return exactly this numbers of bytes. + @param[out] RNGValue A caller-allocated memory buffer filled by the driver with the + resulting RNG value. + + @retval EFI_SUCCESS The RNG value was returned successfully. + @retval EFI_UNSUPPORTED The algorithm specified by RNGAlgorithm is not supported by + this driver. + @retval EFI_DEVICE_ERROR An RNG value could not be retrieved due to a hardware or + firmware error. + @retval EFI_NOT_READY There is not enough random data available to satisfy the length + requested by RNGValueLength. + @retval EFI_INVALID_PARAMETER RNGValue is NULL or RNGValueLength is zero. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_RNG_GET_RNG)( + IN EFI_RNG_INTERFACE *This, + IN EFI_RNG_ALGORITHM *RNGAlgorithm OPTIONAL, + IN UINTN RNGValueLength, + OUT UINT8 *RNGValue + ); + +/// +/// The Random Number Generator (RNG) interface provides random bits for use in +/// applications, or entropy for seeding other random number generators. +/// +/// This interface is shared between the RNG Protocol defined in the UEFI 2.4 Specification +/// and the RNG PPI defined in the PI 1.9 Specification. +/// +struct _EFI_RNG_INTERFACE { + EFI_RNG_GET_INFO GetInfo; + EFI_RNG_GET_RNG GetRNG; +}; + +extern EFI_GUID gEfiRngAlgorithmSp80090Hash256Guid; +extern EFI_GUID gEfiRngAlgorithmSp80090Hmac256Guid; +extern EFI_GUID gEfiRngAlgorithmSp80090Ctr256Guid; +extern EFI_GUID gEfiRngAlgorithmX9313DesGuid; +extern EFI_GUID gEfiRngAlgorithmX931AesGuid; +extern EFI_GUID gEfiRngAlgorithmRaw; +extern EFI_GUID gEfiRngAlgorithmArmRndr; + +#endif // #ifndef RNG_GUID_H_ diff --git a/MdePkg/Include/Guid/StatusCodeDataTypeId.h b/MdePkg/Include/Guid/StatusCodeDataTypeId.h index 0e6b119a00ac..4b9c5a3b0297 100644 --- a/MdePkg/Include/Guid/StatusCodeDataTypeId.h +++ b/MdePkg/Include/Guid/StatusCodeDataTypeId.h @@ -107,6 +107,12 @@ extern EFI_GUID gEfiStatusCodeDataTypeStringGuid; /// - EFI_COMPUTING_UNIT_MICROCODE_UPDATE_ERROR_DATA /// - EFI_COMPUTING_UNIT_TIMER_EXPIRED_ERROR_DATA /// - EFI_HOST_PROCESSOR_MISMATCH_ERROR_DATA +/// - EFI_COMPUTING_UNIT_THERMAL_ERROR_DATA +/// - EFI_CACHE_INIT_DATA +/// - EFI_COMPUTING_UNIT_CPU_DISABLED_ERROR_DATA +/// - EFI_MEMORY_EXTENDED_ERROR_DATA +/// - EFI_STATUS_CODE_DIMM_NUMBER +/// - EFI_MEMORY_MODULE_MISMATCH_ERROR_DATA /// - EFI_MEMORY_RANGE_EXTENDED_DATA /// - EFI_DEBUG_ASSERT_DATA /// - EFI_STATUS_CODE_EXCEP_EXTENDED_DATA diff --git a/MdePkg/Include/IndustryStandard/Cxl20.h b/MdePkg/Include/IndustryStandard/Cxl20.h index 75c5ba4af6c4..25e279886c30 100755 --- a/MdePkg/Include/IndustryStandard/Cxl20.h +++ b/MdePkg/Include/IndustryStandard/Cxl20.h @@ -14,6 +14,7 @@ #define CXL20_H_ #include <IndustryStandard/Cxl11.h> +#include <IndustryStandard/Acpi.h> // // CXL DVSEC IDs @@ -103,6 +104,16 @@ #define CXL_MEM_DEVICE_MEDIA_STATUS_DISABLED 0x3 // +// "CEDT" CXL Early Discovery Table +// Compute Express Link Specification Revision 2.0 - Chapter 9.14.1 +// +#define CXL_EARLY_DISCOVERY_TABLE_SIGNATURE SIGNATURE_32 ('C', 'E', 'D', 'T') + +#define CXL_EARLY_DISCOVERY_TABLE_REVISION_01 0x1 + +#define CEDT_TYPE_CHBS 0x0 + +// // Ensure proper structure formats // #pragma pack(1) @@ -458,6 +469,36 @@ typedef union { UINT64 Uint64; } CXL_MEMORY_DEVICE_STATUS_REGISTER; +// +// CEDT header +// Compute Express Link Specification Revision 2.0 - Chapter 9.14.1.1 +// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; +} CXL_EARLY_DISCOVERY_TABLE; + +// +// Node header definition shared by all CEDT structure types +// +typedef struct { + UINT8 Type; + UINT8 Reserved; + UINT16 Length; +} CEDT_STRUCTURE; + +// +// Definition for CXL Host Bridge Structure (CHBS) +// Compute Express Link Specification Revision 2.0 - Chapter 9.14.1.2 +// +typedef struct { + CEDT_STRUCTURE Header; + UINT32 Uid; + UINT32 CxlVersion; + UINT32 Reserved; + UINT64 Base; + UINT64 Length; +} CXL_HOST_BRIDGE_STRUCTURE; + #pragma pack() #endif diff --git a/MdePkg/Include/IndustryStandard/Cxl30.h b/MdePkg/Include/IndustryStandard/Cxl30.h index 5b921891ef44..3f2688764b11 100644 --- a/MdePkg/Include/IndustryStandard/Cxl30.h +++ b/MdePkg/Include/IndustryStandard/Cxl30.h @@ -46,6 +46,14 @@ #define CXL_HDM_12_WAY_INTERLEAVING 0xA // +// "CEDT" CXL Early Discovery Table +// Compute Express Link Specification Revision 3.0 - Chapter 9.17.1 +// +#define CEDT_TYPE_CFMWS 0x1 +#define CEDT_TYPE_CXIMS 0x2 +#define CEDT_TYPE_RDPAS 0x3 + +// // Ensure proper structure formats // #pragma pack(1) @@ -311,6 +319,57 @@ typedef struct { CXL_3_0_CXL_TIMEOUT_AND_ISOLATION_STATUS TimeoutAndIsolationStatus; } CXL_3_0_CXL_TIMEOUT_AND_ISOLATION_CAPABILITY_STRUCTURE; +// +// Definition for CXL Fixed Memory Window Structure (CFMWS) +// Compute Express Link Specification Revision 3.0 - Chapter 9.17.1.3 +// +// The number of entries in TargetList (Interleave Target List) shall +// match the Number of Interleave Ways (NIW). The current maximum is 16. +// +typedef struct { + CEDT_STRUCTURE Header; + UINT32 Reserved; + UINT64 BaseHpa; + UINT64 WindowSize; + UINT8 EncodedInterleaveWays; + UINT8 InterleaveArithmetic; + UINT16 Reserved1; + UINT32 Granularity; + UINT16 Restrictions; + UINT16 QtgId; + UINT32 TargetList[16]; +} CXL_FIXED_MEMORY_WINDOW_STRUCTURE; + +// +// Definition for CXL XOR Interleave Math Structure (CXIMS) +// Compute Express Link Specification Revision 3.0 - Chapter 9.17.1.4 +// +// The number of entries in XORMAPList depends on NIB. 4 is the current +// maximum for 16-way interleaving. +// +typedef struct { + CEDT_STRUCTURE Header; + UINT16 Reserved; + UINT8 HBIG; + UINT8 NIB; + UINT64 XORMAPList[4]; +} CXL_XOR_INTERLEAVE_MATH_STRUCTURE; + +// +// Definition for RCEC Downstream Port Association Structure (RDPAS) +// Compute Express Link Specification Revision 3.0 - Chapter 9.17.1.5 +// +// The errata released at CXL 3.2 fixed that RCEC BDF field overlaps +// Protocol Type field. +// +typedef struct { + CEDT_STRUCTURE Header; + UINT16 SegmentNumber; + UINT16 Bdf; + UINT64 BaseAddress; + UINT8 ProtocolType; +} RCEC_DOWNSTREAM_PORT_ASSOCIATION_STRUCTURE; + #pragma pack() #endif diff --git a/MdePkg/Include/IndustryStandard/Cxl31.h b/MdePkg/Include/IndustryStandard/Cxl31.h new file mode 100644 index 000000000000..a94bf597b563 --- /dev/null +++ b/MdePkg/Include/IndustryStandard/Cxl31.h @@ -0,0 +1,47 @@ +/** @file + CXL 3.1 definitions + + This file contains the register definitions and firmware interface based + on the Compute Express Link (CXL) Specification Revision 3.1. + + Copyright (c) 2024, Phytium Technology Co Ltd. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Reference(s): + - Compute Express Link (CXL) Specification Revision 3.1. + (https://computeexpresslink.org/cxl-specification/) + +**/ + +#ifndef CXL31_H_ +#define CXL31_H_ + +#include <IndustryStandard/Cxl30.h> + +// +// "CEDT" CXL Early Discovery Table +// Compute Express Link Specification Revision 3.1 - Chapter 9.18.1 +// +#define CXL_EARLY_DISCOVERY_TABLE_REVISION_02 0x2 + +#define CEDT_TYPE_CSDS 0x4 + +// +// Ensure proper structure formats +// +#pragma pack(1) + +// +// Definition for CXL System Description Structure (CSDS) +// Compute Express Link Specification Revision 3.1 - Chapter 9.18.6 +// +typedef struct { + CEDT_STRUCTURE Header; + UINT16 Capabilities; + UINT16 Reserved; +} CXL_DOWNSTREAM_PORT_ASSOCIATION_STRUCTURE; + +#pragma pack() + +#endif diff --git a/MdePkg/Include/IndustryStandard/IpmiSerial.h b/MdePkg/Include/IndustryStandard/IpmiSerial.h new file mode 100644 index 000000000000..09366ee7da08 --- /dev/null +++ b/MdePkg/Include/IndustryStandard/IpmiSerial.h @@ -0,0 +1,66 @@ +/** @file + IPMI Serial Definitions + + Copyright (c) 2024, ARM Limited. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + - IPMI Specification + Version 2.0, Rev. 1.1 + + https://www.intel.com/content/www/us/en/products/docs/servers/ipmi/ipmi-second-gen-interface-spec-v2-rev1-1.html +**/ + +#ifndef IPMI_SERIAL_H_ +#define IPMI_SERIAL_H_ + +/// +/// IPMI Serial Escaped Character Definition +/// Section 14.4.1 & 14.4.2 +/// +#define BASIC_MODE_START 0xA0 +#define BASIC_MODE_STOP 0xA5 +#define BASIC_MODE_HANDSHAKE 0xA6 +#define BASIC_MODE_ESCAPE 0xAA +#define BASIC_MODE_ESC_CHAR 0x1B +#define BASIC_MODE_START_ENCODED_BYTE 0xB0 +#define BASIC_MODE_STOP_ENCODED_BYTE 0xB5 +#define BASIC_MODE_HANDSHAKE_ENCODED_BYTE 0xB6 +#define BASIC_MODE_ESCAPE_ENCODED_BYTE 0xBA +#define BASIC_MODE_ESC_CHAR_ENCODED_BYTE 0x3B + +/// +/// IPMI Serial State Machine +/// +#define MSG_IDLE 0 +#define MSG_IN_PROGRESS 1 + +/// +/// IPMI Serial Message Field Definition +/// Section 14.4.3 +/// +#define IPMI_MAX_LUN 0x3 +#define IPMI_MAX_NETFUNCTION 0x3F +#define IPMI_SERIAL_CONNECTION_HEADER_LENGTH 3 +#define IPMI_SERIAL_REQUEST_DATA_HEADER_LENGTH 3 +#define IPMI_SERIAL_MAXIMUM_PACKET_SIZE_IN_BYTES 256 +#define IPMI_SERIAL_MIN_REQUEST_LENGTH 7 + +#pragma pack (1) +/// +/// IPMI Serial Message Field +/// Section 14.4.3 +/// +typedef struct { + UINT8 ResponderAddress; + UINT8 ResponderNetFnLun; + UINT8 CheckSum; + UINT8 RequesterAddress; + UINT8 RequesterSeqLun; + UINT8 Command; + UINT8 Data[]; +} IPMI_SERIAL_HEADER; + +#pragma pack () + +#endif /* IPMI_SERIAL_H_ */ diff --git a/MdePkg/Include/IndustryStandard/ServiceProcessorManagementInterfaceTable.h b/MdePkg/Include/IndustryStandard/ServiceProcessorManagementInterfaceTable.h index 8886a7174b46..8886a7174b46 100644..100755 --- a/MdePkg/Include/IndustryStandard/ServiceProcessorManagementInterfaceTable.h +++ b/MdePkg/Include/IndustryStandard/ServiceProcessorManagementInterfaceTable.h diff --git a/MdePkg/Include/IndustryStandard/Tpm12.h b/MdePkg/Include/IndustryStandard/Tpm12.h index 031b206740ed..13395ed3d599 100644 --- a/MdePkg/Include/IndustryStandard/Tpm12.h +++ b/MdePkg/Include/IndustryStandard/Tpm12.h @@ -744,8 +744,8 @@ typedef struct tdTPM_PERMANENT_FLAGS { BOOLEAN TPMpost; BOOLEAN TPMpostLock; BOOLEAN FIPS; - BOOLEAN operator; - BOOLEAN enableRevokeEK; + BOOLEAN operator_; + BOOLEAN enableRevokeEK; BOOLEAN nvLocked; BOOLEAN readSRKPub; BOOLEAN tpmEstablished; diff --git a/MdePkg/Include/IndustryStandard/Tpm20.h b/MdePkg/Include/IndustryStandard/Tpm20.h index 78e6c7094fe1..637aa3d5036a 100644 --- a/MdePkg/Include/IndustryStandard/Tpm20.h +++ b/MdePkg/Include/IndustryStandard/Tpm20.h @@ -1248,7 +1248,7 @@ typedef union { TPMI_AES_KEY_BITS aes; TPMI_SM4_KEY_BITS SM4; TPM_KEY_BITS sym; - TPMI_ALG_HASH xor; + TPMI_ALG_HASH xor_; } TPMU_SYM_KEY_BITS; // Table 123 - TPMU_SYM_MODE Union @@ -1321,7 +1321,7 @@ typedef struct { // Table 136 - TPMU_SCHEME_KEYEDHASH Union typedef union { TPMS_SCHEME_HMAC hmac; - TPMS_SCHEME_XOR xor; + TPMS_SCHEME_XOR xor_; } TPMU_SCHEME_KEYEDHASH; // Table 137 - TPMT_KEYEDHASH_SCHEME Structure diff --git a/MdePkg/Include/IndustryStandard/Tpm2Acpi.h b/MdePkg/Include/IndustryStandard/Tpm2Acpi.h index 10a6190ee037..4ef570284479 100644 --- a/MdePkg/Include/IndustryStandard/Tpm2Acpi.h +++ b/MdePkg/Include/IndustryStandard/Tpm2Acpi.h @@ -17,9 +17,11 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #define EFI_TPM2_ACPI_TABLE_REVISION_3 3 #define EFI_TPM2_ACPI_TABLE_REVISION_4 4 +#define EFI_TPM2_ACPI_TABLE_REVISION_5 5 #define EFI_TPM2_ACPI_TABLE_REVISION EFI_TPM2_ACPI_TABLE_REVISION_4 #define EFI_TPM2_ACPI_TABLE_START_METHOD_SPECIFIC_PARAMETERS_MAX_SIZE_REVISION_4 12 +#define EFI_TPM2_ACPI_TABLE_START_METHOD_SPECIFIC_PARAMETERS_MAX_SIZE_REVISION_5 16 #define EFI_TPM2_ACPI_TABLE_START_METHOD_SPECIFIC_PARAMETERS_MAX_SIZE EFI_TPM2_ACPI_TABLE_START_METHOD_SPECIFIC_PARAMETERS_MAX_SIZE_REVISION_4 typedef struct { @@ -40,6 +42,7 @@ typedef struct { #define EFI_TPM2_ACPI_TABLE_START_METHOD_COMMAND_RESPONSE_BUFFER_INTERFACE 7 #define EFI_TPM2_ACPI_TABLE_START_METHOD_COMMAND_RESPONSE_BUFFER_INTERFACE_WITH_ACPI 8 #define EFI_TPM2_ACPI_TABLE_START_METHOD_COMMAND_RESPONSE_BUFFER_INTERFACE_WITH_SMC 11 +#define EFI_TPM2_ACPI_TABLE_START_METHOD_COMMAND_RESPONSE_BUFFER_INTERFACE_WITH_FFA 15 typedef struct { UINT32 Reserved; diff --git a/MdePkg/Include/IndustryStandard/Ufs.h b/MdePkg/Include/IndustryStandard/Ufs.h new file mode 100644 index 000000000000..dac2fd9b78e7 --- /dev/null +++ b/MdePkg/Include/IndustryStandard/Ufs.h @@ -0,0 +1,1022 @@ +/*++ @file + + Common definitions for Universal Flash Storage (UFS) + + Copyright (c) Microsoft Corporation. All rights reserved. + Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + JESD220 - Universal Flash Storage (UFS) + Version 4.0 + https://www.jedec.org/system/files/docs/JESD220F.pdf +--*/ + +#ifndef __UFS_H__ +#define __UFS_H__ + +#include <Base.h> + +#define UFS_LUN_0 0x00 +#define UFS_LUN_1 0x01 +#define UFS_LUN_2 0x02 +#define UFS_LUN_3 0x03 +#define UFS_LUN_4 0x04 +#define UFS_LUN_5 0x05 +#define UFS_LUN_6 0x06 +#define UFS_LUN_7 0x07 +#define UFS_WLUN_REPORT_LUNS 0x81 +#define UFS_WLUN_UFS_DEV 0xD0 +#define UFS_WLUN_BOOT 0xB0 +#define UFS_WLUN_RPMB 0xC4 + +#pragma pack(1) + +// +// UFS 4.0 Spec Table 10.13 - UTP Command UPIU +// +typedef struct { + // + // DW0 + // + UINT8 TransCode : 6; /* Transaction Type - 0x01*/ + UINT8 Dd : 1; + UINT8 Hd : 1; + UINT8 Flags; + UINT8 Lun; + UINT8 TaskTag; /* Task Tag */ + + // + // DW1 + // + UINT8 CmdSet : 4; /* Command Set Type */ + UINT8 Iid : 4; /* Initiator ID */ + UINT8 Rsvd1; + UINT8 Rsvd2; + UINT8 Rsvd3 : 4; + UINT8 Ext_Iid : 4; /* Initiator ID Extended */ + + // + // DW2 + // + UINT8 EhsLen; /* Total EHS Length - 0x00 */ + UINT8 Rsvd4; + UINT16 DataSegLen; /* Data Segment Length - Big Endian - 0x0000 */ + + // + // DW3 + // + UINT32 ExpDataTranLen; /* Expected Data Transfer Length - Big Endian */ + + // + // DW4 - DW7 + // + UINT8 Cdb[16]; +} UTP_COMMAND_UPIU; + +// +// UFS 4.0 Spec Table 10.15 - UTP Response UPIU +// +typedef struct { + // + // DW0 + // + UINT8 TransCode : 6; /* Transaction Type - 0x21*/ + UINT8 Dd : 1; + UINT8 Hd : 1; + UINT8 Flags; + UINT8 Lun; + UINT8 TaskTag; /* Task Tag */ + + // + // DW1 + // + UINT8 CmdSet : 4; /* Command Set Type */ + UINT8 Iid : 4; /* Initiator ID */ + UINT8 Rsvd1 : 4; + UINT8 Ext_Iid : 4; /* Initiator ID Extended */ + UINT8 Response; /* Response */ + UINT8 Status; /* Status */ + + // + // DW2 + // + UINT8 EhsLen; /* Total EHS Length - 0x00 */ + UINT8 DevInfo; /* Device Information */ + UINT16 DataSegLen; /* Data Segment Length - Big Endian */ + + // + // DW3 + // + UINT32 ResTranCount; /* Residual Transfer Count - Big Endian */ + + // + // DW4 - DW7 + // + UINT8 Rsvd2[16]; + + // + // Data Segment - Sense Data + // + UINT16 SenseDataLen; /* Sense Data Length - Big Endian */ + UINT8 SenseData[18]; /* Sense Data */ +} UTP_RESPONSE_UPIU; + +// +// UFS 4.0 Spec Table 10.21 - UTP Data-Out UPIU +// +typedef struct { + // + // DW0 + // + UINT8 TransCode : 6; /* Transaction Type - 0x02*/ + UINT8 Dd : 1; + UINT8 Hd : 1; + UINT8 Flags; + UINT8 Lun; + UINT8 TaskTag; /* Task Tag */ + + // + // DW1 + // + UINT8 Rsvd1 : 4; + UINT8 Iid : 4; /* Initiator ID */ + UINT8 Rsvd2[2]; + UINT8 Rsvd3 : 4; + UINT8 Ext_Iid : 4; /* Initiator ID Extended */ + + // + // DW2 + // + UINT8 EhsLen; /* Total EHS Length - 0x00 */ + UINT8 Rsvd4; + UINT16 DataSegLen; /* Data Segment Length - Big Endian */ + + // + // DW3 + // + UINT32 DataBufOffset; /* Data Buffer Offset - Big Endian */ + + // + // DW4 + // + UINT32 DataTranCount; /* Data Transfer Count - Big Endian */ + + // + // DW5 - DW7 + // + UINT8 Rsvd5[12]; + + // + // Data Segment - Data to be sent out + // + // UINT8 Data[]; /* Data to be sent out, maximum is 65535 bytes */ +} UTP_DATA_OUT_UPIU; + +// +// UFS 4.0 Spec Table 10.23 - UTP Data-In UPIU +// +typedef struct { + // + // DW0 + // + UINT8 TransCode : 6; /* Transaction Type - 0x22*/ + UINT8 Dd : 1; + UINT8 Hd : 1; + UINT8 Flags; + UINT8 Lun; + UINT8 TaskTag; /* Task Tag */ + + // + // DW1 + // + UINT8 Rsvd1 : 4; + UINT8 Iid : 4; /* Initiator ID */ + UINT8 Rsvd2 : 4; + UINT8 Ext_Iid : 4; /* Initiator ID Extended */ + UINT8 Rsvd3[2]; + + // + // DW2 + // + UINT8 EhsLen; /* Total EHS Length - 0x00 */ + UINT8 Rsvd4; + UINT16 DataSegLen; /* Data Segment Length - Big Endian */ + + // + // DW3 + // + UINT32 DataBufOffset; /* Data Buffer Offset - Big Endian */ + + // + // DW4 + // + UINT32 DataTranCount; /* Data Transfer Count - Big Endian */ + + // + // DW5 + // + UINT8 HintControl : 4; /* Hint Control */ + UINT8 Rsvd5 : 4; + UINT8 HintIid : 4; /* Hint Initiator ID */ + UINT8 HintExt_Iid : 4; /* Hint Initiator ID Extended */ + UINT8 HintLun; /* Hint LUN */ + UINT8 HintTaskTag; /* Hint Task Tag */ + + // + // DW6 + // + UINT32 HintDataBufOffset; /* Hint Data Buffer Offset - Big Endian */ + + // + // DW7 + // + UINT32 HintDataCount; /* Hint Data Count - Big Endian */ + + // + // Data Segment - Data to be read + // + // UINT8 Data[]; /* Data to be read, maximum is 65535 bytes */ +} UTP_DATA_IN_UPIU; + +// +// UFS 4.0 Spec Table 10.25 - UTP Ready-To-Transfer UPIU +// +typedef struct { + // + // DW0 + // + UINT8 TransCode : 6; /* Transaction Type - 0x31*/ + UINT8 Dd : 1; + UINT8 Hd : 1; + UINT8 Flags; + UINT8 Lun; + UINT8 TaskTag; /* Task Tag */ + + // + // DW1 + // + UINT8 Rsvd1 : 4; + UINT8 Iid : 4; /* Initiator ID */ + UINT8 Rsvd2 : 4; + UINT8 Ext_Iid : 4; /* Initiator ID Extended */ + UINT8 Rsvd3[2]; + + // + // DW2 + // + UINT8 EhsLen; /* Total EHS Length - 0x00 */ + UINT8 Rsvd4; + UINT16 DataSegLen; /* Data Segment Length - Big Endian - 0x0000 */ + + // + // DW3 + // + UINT32 DataBufOffset; /* Data Buffer Offset - Big Endian */ + + // + // DW4 + // + UINT32 DataTranCount; /* Data Transfer Count - Big Endian */ + + // + // DW5 + // + UINT8 HintControl : 4; /* Hint Control */ + UINT8 Rsvd5 : 4; + UINT8 HintIid : 4; /* Hint Initiator ID */ + UINT8 HintExt_Iid : 4; /* Hint Initiator ID Extended */ + UINT8 HintLun; /* Hint LUN */ + UINT8 HintTaskTag; /* Hint Task Tag */ + + // + // DW6 + // + UINT32 HintDataBufOffset; /* Hint Data Buffer Offset - Big Endian */ + + // + // DW7 + // + UINT32 HintDataCount; /* Hint Data Count - Big Endian */ + + // + // Data Segment - Data to be read + // + // UINT8 Data[]; /* Data to be read, maximum is 65535 bytes */ +} UTP_RDY_TO_TRAN_UPIU; + +// +// UFS 4.0 Spec Table 10.27 - UTP Task Management Request UPIU +// +typedef struct { + // + // DW0 + // + UINT8 TransCode : 6; /* Transaction Type - 0x04*/ + UINT8 Dd : 1; + UINT8 Hd : 1; + UINT8 Flags; + UINT8 Lun; + UINT8 TaskTag; /* Task Tag */ + + // + // DW1 + // + UINT8 Rsvd1 : 4; + UINT8 Iid : 4; /* Initiator ID */ + UINT8 TskManFunc; /* Task Management Function */ + UINT8 Rsvd2; + UINT8 Rsvd3 : 4; + UINT8 Ext_Iid : 4; /* Initiator ID Extended */ + + // + // DW2 + // + UINT8 EhsLen; /* Total EHS Length - 0x00 */ + UINT8 Rsvd4; + UINT16 DataSegLen; /* Data Segment Length - Big Endian - 0x0000 */ + + // + // DW3 + // + UINT32 InputParam1; /* Input Parameter 1 - Big Endian */ + + // + // DW4 + // + UINT32 InputParam2; /* Input Parameter 2 - Big Endian */ + + // + // DW5 + // + UINT32 InputParam3; /* Input Parameter 3 - Big Endian */ + + // + // DW6 - DW7 + // + UINT8 Rsvd5[8]; +} UTP_TM_REQ_UPIU; + +// +// UFS 4.0 Spec Table 10.30 - UTP Task Management Response UPIU +// +typedef struct { + // + // DW0 + // + UINT8 TransCode : 6; /* Transaction Type - 0x24*/ + UINT8 Dd : 1; + UINT8 Hd : 1; + UINT8 Flags; + UINT8 Lun; + UINT8 TaskTag; /* Task Tag */ + + // + // DW1 + // + UINT8 Rsvd1 : 4; + UINT8 Iid : 4; /* Initiator ID */ + UINT8 Rsvd2 : 4; + UINT8 Ext_Iid : 4; /* Initiator ID Extended */ + UINT8 Resp; /* Response */ + UINT8 Rsvd3; + + // + // DW2 + // + UINT8 EhsLen; /* Total EHS Length - 0x00 */ + UINT8 Rsvd4; + UINT16 DataSegLen; /* Data Segment Length - Big Endian - 0x0000 */ + + // + // DW3 + // + UINT32 OutputParam1; /* Output Parameter 1 - Big Endian */ + + // + // DW4 + // + UINT32 OutputParam2; /* Output Parameter 2 - Big Endian */ + + // + // DW5 - DW7 + // + UINT8 Rsvd5[12]; +} UTP_TM_RESP_UPIU; + +// +// UFS 4.0 Spec Table 10.35 - 10.57 - Transaction Specific Fields for (Genericized) Opcode +// +typedef struct { + UINT8 Opcode; + UINT8 DescId; + UINT8 Index; + UINT8 Selector; + UINT16 Rsvd1; + UINT16 Length; + UINT32 Value; + UINT32 Rsvd2; +} UTP_UPIU_TSF; + +// +// UFS 4.0 Spec Table 10.33 - UTP Query Request UPIU +// +typedef struct { + // + // DW0 + // + UINT8 TransCode : 6; /* Transaction Type - 0x16*/ + UINT8 Dd : 1; + UINT8 Hd : 1; + UINT8 Flags; + UINT8 Rsvd1; + UINT8 TaskTag; /* Task Tag */ + + // + // DW1 + // + UINT8 Rsvd2; + UINT8 QueryFunc; /* Query Function */ + UINT8 Rsvd3[2]; + + // + // DW2 + // + UINT8 EhsLen; /* Total EHS Length - 0x00 */ + UINT8 Rsvd4; + UINT16 DataSegLen; /* Data Segment Length - Big Endian */ + + // + // DW3 - 6 + // + UTP_UPIU_TSF Tsf; /* Transaction Specific Fields */ + + // + // DW7 + // + UINT8 Rsvd5[4]; + + // + // Data Segment - Data to be transferred + // + // UINT8 Data[]; /* Data to be transferred, maximum is 65535 bytes */ +} UTP_QUERY_REQ_UPIU; + +#define QUERY_FUNC_STD_READ_REQ 0x01 +#define QUERY_FUNC_STD_WRITE_REQ 0x81 + +// +// UFS 4.0 Spec Table 10.36 - Query Function opcode values +// +typedef enum { + UtpQueryFuncOpcodeNop = 0x00, + UtpQueryFuncOpcodeRdDesc = 0x01, + UtpQueryFuncOpcodeWrDesc = 0x02, + UtpQueryFuncOpcodeRdAttr = 0x03, + UtpQueryFuncOpcodeWrAttr = 0x04, + UtpQueryFuncOpcodeRdFlag = 0x05, + UtpQueryFuncOpcodeSetFlag = 0x06, + UtpQueryFuncOpcodeClrFlag = 0x07, + UtpQueryFuncOpcodeTogFlag = 0x08 +} UTP_QUERY_FUNC_OPCODE; + +// +// UFS 4.0 Spec Table 10.46 - UTP Query Response UPIU +// +typedef struct { + // + // DW0 + // + UINT8 TransCode : 6; /* Transaction Type - 0x36*/ + UINT8 Dd : 1; + UINT8 Hd : 1; + UINT8 Flags; + UINT8 Rsvd1; + UINT8 TaskTag; /* Task Tag */ + + // + // DW1 + // + UINT8 Rsvd2; + UINT8 QueryFunc; /* Query Function */ + UINT8 QueryResp; /* Query Response */ + UINT8 Rsvd3; + + // + // DW2 + // + UINT8 EhsLen; /* Total EHS Length - 0x00 */ + UINT8 DevInfo; /* Device Information */ + UINT16 DataSegLen; /* Data Segment Length - Big Endian */ + + // + // DW3 - 6 + // + UTP_UPIU_TSF Tsf; /* Transaction Specific Fields */ + + // + // DW7 + // + UINT8 Rsvd4[4]; + + // + // Data Segment - Data to be transferred + // + // UINT8 Data[]; /* Data to be transferred, maximum is 65535 bytes */ +} UTP_QUERY_RESP_UPIU; + +// +// UFS 4.0 Spec Table 10.47 - Query Response Code +// +typedef enum { + UfsUtpQueryResponseSuccess = 0x00, + UfsUtpQueryResponseParamNotReadable = 0xF6, + UfsUtpQueryResponseParamNotWriteable = 0xF7, + UfsUtpQueryResponseParamAlreadyWritten = 0xF8, + UfsUtpQueryResponseInvalidLen = 0xF9, + UfsUtpQueryResponseInvalidVal = 0xFA, + UfsUtpQueryResponseInvalidSelector = 0xFB, + UfsUtpQueryResponseInvalidIndex = 0xFC, + UfsUtpQueryResponseInvalidIdn = 0xFD, + UfsUtpQueryResponseInvalidOpc = 0xFE, + UfsUtpQueryResponseGeneralFailure = 0xFF +} UTP_QUERY_RESP_CODE; + +// +// UFS 4.0 Spec Table 10.58 - UTP Reject UPIU +// +typedef struct { + // + // DW0 + // + UINT8 TransCode : 6; /* Transaction Type - 0x3F*/ + UINT8 Dd : 1; + UINT8 Hd : 1; + UINT8 Flags; + UINT8 Lun; + UINT8 TaskTag; /* Task Tag */ + + // + // DW1 + // + UINT8 Rsvd1 : 4; + UINT8 Iid : 4; /* Initiator ID */ + UINT8 Rsvd2 : 4; + UINT8 Ext_Iid : 4; /* Initiator ID Extended */ + UINT8 Response; /* Response - 0x01 */ + UINT8 Rsvd3; + + // + // DW2 + // + UINT8 EhsLen; /* Total EHS Length - 0x00 */ + UINT8 DevInfo; /* Device Information - 0x00 */ + UINT16 DataSegLen; /* Data Segment Length - Big Endian - 0x0000 */ + + // + // DW3 + // + UINT8 HdrSts; /* Basic Header Status */ + UINT8 Rsvd4; + UINT8 E2ESts; /* End-to-End Status */ + UINT8 Rsvd5; + + // + // DW4 - DW7 + // + UINT8 Rsvd6[16]; +} UTP_REJ_UPIU; + +// +// UFS 4.0 Spec Table 10.61 - UTP NOP OUT UPIU +// +typedef struct { + // + // DW0 + // + UINT8 TransCode : 6; /* Transaction Type - 0x00*/ + UINT8 Dd : 1; + UINT8 Hd : 1; + UINT8 Flags; + UINT8 Rsvd1; + UINT8 TaskTag; /* Task Tag */ + + // + // DW1 + // + UINT8 Rsvd2[4]; + + // + // DW2 + // + UINT8 EhsLen; /* Total EHS Length - 0x00 */ + UINT8 Rsvd3; + UINT16 DataSegLen; /* Data Segment Length - Big Endian - 0x0000 */ + + // + // DW3 - DW7 + // + UINT8 Rsvd4[20]; +} UTP_NOP_OUT_UPIU; + +// +// UFS 4.0 Spec Table 10.62 - UTP NOP IN UPIU +// +typedef struct { + // + // DW0 + // + UINT8 TransCode : 6; /* Transaction Type - 0x20*/ + UINT8 Dd : 1; + UINT8 Hd : 1; + UINT8 Flags; + UINT8 Rsvd1; + UINT8 TaskTag; /* Task Tag */ + + // + // DW1 + // + UINT8 Rsvd2[2]; + UINT8 Resp; /* Response - 0x00 */ + UINT8 Rsvd3; + + // + // DW2 + // + UINT8 EhsLen; /* Total EHS Length - 0x00 */ + UINT8 DevInfo; /* Device Information - 0x00 */ + UINT16 DataSegLen; /* Data Segment Length - Big Endian - 0x0000 */ + + // + // DW3 - DW7 + // + UINT8 Rsvd4[20]; +} UTP_NOP_IN_UPIU; + +// +// UFS 4.0 Spec Table 14.1 - Descriptor identification values +// +typedef enum { + UfsDeviceDesc = 0x00, + UfsConfigDesc = 0x01, + UfsUnitDesc = 0x02, + UfsInterConnDesc = 0x04, + UfsStringDesc = 0x05, + UfsGeometryDesc = 0x07, + UfsPowerDesc = 0x08, + UfsDevHealthDesc = 0x09 +} UFS_DESC_IDN; + +// +// UFS 4.0 Spec Table 14.4 - Device Descriptor +// +typedef struct { + UINT8 Length; + UINT8 DescType; + UINT8 Device; + UINT8 DevClass; + UINT8 DevSubClass; + UINT8 Protocol; + UINT8 NumLun; + UINT8 NumWLun; + UINT8 BootEn; + UINT8 DescAccessEn; + UINT8 InitPowerMode; + UINT8 HighPriorityLun; + UINT8 SecureRemovalType; + UINT8 SecurityLun; + UINT8 BgOpsTermLat; + UINT8 InitActiveIccLevel; + UINT16 SpecVersion; + UINT16 ManufactureDate; + UINT8 ManufacturerName; + UINT8 ProductName; + UINT8 SerialName; + UINT8 OemId; + UINT16 ManufacturerId; + UINT8 Ud0BaseOffset; + UINT8 Ud0ConfParamLen; + UINT8 DevRttCap; + UINT16 PeriodicRtcUpdate; + UINT8 UFSFeaturesSupport; // Deprecated, use ExtendedUFSFeaturesSupport + UINT8 FFUTimeout; + UINT8 QueueDepth; + UINT16 DeviceVersion; + UINT8 NumSecureWPArea; + UINT32 PSAMaxDataSize; + UINT8 PSAStateTimeout; + UINT8 ProductRevisionLevel; + UINT8 Rsvd1[5]; + UINT8 Rsvd2[16]; + UINT8 Rsvd3[3]; + UINT8 Rsvd4[12]; + UINT32 ExtendedUFSFeaturesSupport; + UINT8 WriteBoosterBufPreserveUserSpaceEn; + UINT8 WriteBoosterBufType; + UINT32 NumSharedWriteBoosterAllocUnits; +} UFS_DEV_DESC; + +// +// UFS 4.0 Spec Table 14.4 (Offset 10h) - Specification version +// +typedef union { + struct { + UINT8 Suffix : 4; + UINT8 Minor : 4; + UINT8 Major; + } Bits; + UINT16 Data; +} UFS_SPEC_VERSION; + +// +// UFS 4.0 Spec Table 14.4 (Offset 4Fh) - Extended UFS Features Support +// +typedef union { + struct { + UINT32 FFU : 1; + UINT32 PSA : 1; + UINT32 DeviceLifeSpan : 1; + UINT32 RefreshOperation : 1; + UINT32 TooHighTemp : 1; + UINT32 TooLowTemp : 1; + UINT32 ExtendedTemp : 1; + UINT32 Rsvd1 : 1; + UINT32 WriteBooster : 1; + UINT32 PerformanceThrottling : 1; + UINT32 AdvancedRPMB : 1; + UINT32 Rsvd2 : 3; + UINT32 Barrier : 1; + UINT32 ClearErrorHistory : 1; + UINT32 Ext_Iid : 1; + UINT32 Rsvd3 : 1; + UINT32 Rsvd4 : 14; + } Bits; + UINT32 Data; +} EXTENDED_UFS_FEATURES_SUPPORT; + +// +// UFS 4.0 Spec Table 14.10 - Configuration Descriptor Header (INDEX = 0) +// and Device Descriptor Configuration parameters +// +typedef struct { + UINT8 Length; + UINT8 DescType; + UINT8 ConfDescContinue; + UINT8 BootEn; + UINT8 DescAccessEn; + UINT8 InitPowerMode; + UINT8 HighPriorityLun; + UINT8 SecureRemovalType; + UINT8 InitActiveIccLevel; + UINT16 PeriodicRtcUpdate; + UINT8 Rsvd1; + UINT8 RpmbRegionEnable; + UINT8 RpmbRegion1Size; + UINT8 RpmbRegion2Size; + UINT8 RpmbRegion3Size; + UINT8 WriteBoosterBufPreserveUserSpaceEn; + UINT8 WriteBoosterBufType; + UINT32 NumSharedWriteBoosterAllocUnits; +} UFS_CONFIG_DESC_GEN_HEADER; + +// +// UFS 4.0 Spec Table 14.11 - Configuration Descriptor Header (INDEX = 1/2/3) +// +typedef struct { + UINT8 Length; + UINT8 DescType; + UINT8 ConfDescContinue; + UINT8 Rsvd1[19]; +} UFS_CONFIG_DESC_EXT_HEADER; + +// +// UFS 4.0 Spec Table 14.12 - UNit Descriptor configurable parameters +// +typedef struct { + UINT8 LunEn; + UINT8 BootLunId; + UINT8 LunWriteProt; + UINT8 MemType; + UINT32 NumAllocUnits; + UINT8 DataReliability; + UINT8 LogicBlkSize; + UINT8 ProvisionType; + UINT16 CtxCap; + UINT8 Rsvd1[3]; + UINT8 Rsvd2[6]; + UINT32 LuNumWriteBoosterBufAllocUnits; +} UFS_UNIT_DESC_CONFIG_PARAMS; + +// +// UFS 4.0 Spec Table 14.6 - Configuration Descriptor Format +// +// WARNING: This struct contains variable-size members! (across spec versions) +// To maintain backward compatibility, UnitDescConfParams should not be +// accessed as a struct member. +// Instead, use `Ud0BaseOffset` and `Ud0ConfParamLen` from the Device +// Descriptor to calculate the offset and location of the Unit Descriptors. +// +typedef struct { + UFS_CONFIG_DESC_GEN_HEADER Header; + UFS_UNIT_DESC_CONFIG_PARAMS UnitDescConfParams[8]; +} UFS_CONFIG_DESC; + +// +// UFS 4.0 Spec Table 14.13 - Geometry Descriptor +// +typedef struct { + UINT8 Length; + UINT8 DescType; + UINT8 MediaTech; + UINT8 Rsvd1; + UINT64 TotalRawDevCapacity; + UINT8 MaxNumberLu; + UINT32 SegSize; + UINT8 AllocUnitSize; + UINT8 MinAddrBlkSize; + UINT8 OptReadBlkSize; + UINT8 OptWriteBlkSize; + UINT8 MaxInBufSize; + UINT8 MaxOutBufSize; + UINT8 RpmbRwSize; + UINT8 DynamicCapacityResourcePolicy; + UINT8 DataOrder; + UINT8 MaxCtxIdNum; + UINT8 SysDataTagUnitSize; + UINT8 SysDataResUnitSize; + UINT8 SupSecRemovalTypes; + UINT16 SupMemTypes; + UINT32 SysCodeMaxNumAllocUnits; + UINT16 SupCodeCapAdjFac; + UINT32 NonPersMaxNumAllocUnits; + UINT16 NonPersCapAdjFac; + UINT32 Enhance1MaxNumAllocUnits; + UINT16 Enhance1CapAdjFac; + UINT32 Enhance2MaxNumAllocUnits; + UINT16 Enhance2CapAdjFac; + UINT32 Enhance3MaxNumAllocUnits; + UINT16 Enhance3CapAdjFac; + UINT32 Enhance4MaxNumAllocUnits; + UINT16 Enhance4CapAdjFac; + UINT32 OptLogicBlkSize; + UINT8 Rsvd2[5]; + UINT8 Rsvd3[2]; + UINT32 WriteBoosterBufMaxNumAllocUnits; + UINT8 DeviceMaxWriteBoosterLus; + UINT8 WriteBoosterBufCapAdjFac; + UINT8 SupWriteBoosterBufUserSpaceReductionTypes; + UINT8 SupWriteBoosterBufTypes; +} UFS_GEOMETRY_DESC; + +// +// UFS 4.0 Spec Table 14.14 - Unit Descriptor +// +typedef struct { + UINT8 Length; + UINT8 DescType; + UINT8 UnitIdx; + UINT8 LunEn; + UINT8 BootLunId; + UINT8 LunWriteProt; + UINT8 LunQueueDep; + UINT8 PsaSensitive; + UINT8 MemType; + UINT8 DataReliability; + UINT8 LogicBlkSize; + UINT64 LogicBlkCount; + UINT32 EraseBlkSize; + UINT8 ProvisionType; + UINT64 PhyMemResCount; + UINT16 CtxCap; + UINT8 LargeUnitGranularity; + UINT8 Rsvd1[6]; + UINT32 LuNumWriteBoosterBufAllocUnits; +} UFS_UNIT_DESC; + +// +// UFS 4.0 Spec Table 14.15 - RPMB Unit Descriptor +// +typedef struct { + UINT8 Length; + UINT8 DescType; + UINT8 UnitIdx; + UINT8 LunEn; + UINT8 BootLunId; + UINT8 LunWriteProt; + UINT8 LunQueueDep; + UINT8 PsaSensitive; + UINT8 MemType; + UINT8 RpmbRegionEnable; + UINT8 LogicBlkSize; + UINT64 LogicBlkCount; + UINT8 RpmbRegion0Size; + UINT8 RpmbRegion1Size; + UINT8 RpmbRegion2Size; + UINT8 RpmbRegion3Size; + UINT8 ProvisionType; + UINT64 PhyMemResCount; + UINT8 Rsvd3[3]; +} UFS_RPMB_UNIT_DESC; + +// +// UFS 4.0 Spec Table 7.13 - Format for Power Parameter element +// +typedef struct { + UINT16 Value : 12; + UINT16 Rsvd1 : 2; + UINT16 Unit : 2; +} UFS_POWER_PARAM_ELEMENT; + +// +// UFS 4.0 Spec Table 14.16 - Power Parameters Descriptor +// +typedef struct { + UINT8 Length; + UINT8 DescType; + UFS_POWER_PARAM_ELEMENT ActiveIccLevelVcc[16]; + UFS_POWER_PARAM_ELEMENT ActiveIccLevelVccQ[16]; + UFS_POWER_PARAM_ELEMENT ActiveIccLevelVccQ2[16]; +} UFS_POWER_DESC; + +// +// UFS 4.0 Spec Table 14.17 - Interconnect Descriptor +// +typedef struct { + UINT8 Length; + UINT8 DescType; + UINT16 UniProVer; + UINT16 MphyVer; +} UFS_INTER_CONNECT_DESC; + +// +// UFS 4.0 Spec Table 14.18 - 14.22 - String Descriptor +// +typedef struct { + UINT8 Length; + UINT8 DescType; + CHAR16 Unicode[126]; +} UFS_STRING_DESC; + +// +// UFS 4.0 Spec Table 14.26 - Flags +// +typedef enum { + UfsFlagDevInit = 0x01, + UfsFlagPermWpEn = 0x02, + UfsFlagPowerOnWpEn = 0x03, + UfsFlagBgOpsEn = 0x04, + UfsFlagDevLifeSpanModeEn = 0x05, + UfsFlagPurgeEn = 0x06, + UfsFlagRefreshEn = 0x07, + UfsFlagPhyResRemoval = 0x08, + UfsFlagBusyRtc = 0x09, + UfsFlagPermDisFwUpdate = 0x0B, + UfsFlagWriteBoosterEn = 0x0E, + UfsFlagWbBufFlushEn = 0x0F, + UfsFlagWbBufFlushHibernate = 0x10 +} UFS_FLAGS_IDN; + +// +// UFS 4.0 Spec Table 14.28 - Attributes +// +typedef enum { + UfsAttrBootLunEn = 0x00, + UfsAttrCurPowerMode = 0x02, + UfsAttrActiveIccLevel = 0x03, + UfsAttrOutOfOrderDataEn = 0x04, + UfsAttrBgOpStatus = 0x05, + UfsAttrPurgeStatus = 0x06, + UfsAttrMaxDataInSize = 0x07, + UfsAttrMaxDataOutSize = 0x08, + UfsAttrDynCapNeeded = 0x09, + UfsAttrRefClkFreq = 0x0a, + UfsAttrConfigDescLock = 0x0b, + UfsAttrMaxNumOfRtt = 0x0c, + UfsAttrExceptionEvtCtrl = 0x0d, + UfsAttrExceptionEvtSts = 0x0e, + UfsAttrSecondsPassed = 0x0f, + UfsAttrContextConf = 0x10, + UfsAttrDeviceFfuStatus = 0x14, + UfsAttrPsaState = 0x15, + UfsAttrPsaDataSize = 0x16, + UfsAttrRefClkGatingWaitTime = 0x17, + UfsAttrDeviceCaseRoughTemp = 0x18, + UfsAttrDeviceTooHighTempBound = 0x19, + UfsAttrDeviceTooLowTempBound = 0x1a, + UfsAttrThrottlingStatus = 0x1b, + UfsAttrWriteBoosterBufFlushStatus = 0x1c, + UfsAttrAvailableWriteBoosterBufSize = 0x1d, + UfsAttrWriteBoosterBufLifeTimeEst = 0x1e, + UfsAttrCurrentWriteBoosterBufSize = 0x1f, + UfsAttrExtIidEn = 0x2a, + UfsAttrHostHintCacheSize = 0x2b, + UfsAttrRefreshStatus = 0x2c, + UfsAttrRefreshFreq = 0x2d, + UfsAttrRefreshUnit = 0x2e, + UfsAttrRefreshMethod = 0x2f, + UfsAttrTimestamp = 0x30 +} UFS_ATTR_IDN; + +#pragma pack() + +#endif diff --git a/MdePkg/Include/IndustryStandard/UfsHci.h b/MdePkg/Include/IndustryStandard/UfsHci.h new file mode 100644 index 000000000000..6a6c819dc6e2 --- /dev/null +++ b/MdePkg/Include/IndustryStandard/UfsHci.h @@ -0,0 +1,533 @@ +/*++ @file + + Common definitions for UFS Host Controller Interface (UFSHCI) + + Copyright (c) Microsoft Corporation. All rights reserved. + Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + JESD223 - Universal Flash Storage Host Controller Interface (UFSHCI) + Version 2.0 + https://www.jedec.org/system/files/docs/JESD223C.pdf +--*/ + +#ifndef __UFS_HCI_H__ +#define __UFS_HCI_H__ + +#include <Base.h> + +#include <IndustryStandard/Ufs.h> + +// +// Host Capabilities Register Offsets +// +#define UFS_HC_CAP_OFFSET 0x0000 // Controller Capabilities +#define UFS_HC_VER_OFFSET 0x0008 // Version +#define UFS_HC_DDID_OFFSET 0x0010 // Device ID and Device Class +#define UFS_HC_PMID_OFFSET 0x0014 // Product ID and Manufacturer ID +#define UFS_HC_AHIT_OFFSET 0x0018 // Auto-Hibernate Idle Timer +// +// Operation and Runtime Register Offsets +// +#define UFS_HC_IS_OFFSET 0x0020 // Interrupt Status +#define UFS_HC_IE_OFFSET 0x0024 // Interrupt Enable +#define UFS_HC_STATUS_OFFSET 0x0030 // Host Controller Status +#define UFS_HC_ENABLE_OFFSET 0x0034 // Host Controller Enable +#define UFS_HC_UECPA_OFFSET 0x0038 // Host UIC Error Code PHY Adapter Layer +#define UFS_HC_UECDL_OFFSET 0x003c // Host UIC Error Code Data Link Layer +#define UFS_HC_UECN_OFFSET 0x0040 // Host UIC Error Code Network Layer +#define UFS_HC_UECT_OFFSET 0x0044 // Host UIC Error Code Transport Layer +#define UFS_HC_UECDME_OFFSET 0x0048 // Host UIC Error Code DME +#define UFS_HC_UTRIACR_OFFSET 0x004c // UTP Transfer Request Interrupt Aggregation Control Register +// +// UTP Transfer Register Offsets +// +#define UFS_HC_UTRLBA_OFFSET 0x0050 // UTP Transfer Request List Base Address +#define UFS_HC_UTRLBAU_OFFSET 0x0054 // UTP Transfer Request List Base Address Upper 32-Bits +#define UFS_HC_UTRLDBR_OFFSET 0x0058 // UTP Transfer Request List Door Bell Register +#define UFS_HC_UTRLCLR_OFFSET 0x005c // UTP Transfer Request List CLear Register +#define UFS_HC_UTRLRSR_OFFSET 0x0060 // UTP Transfer Request Run-Stop Register +// +// UTP Task Management Register Offsets +// +#define UFS_HC_UTMRLBA_OFFSET 0x0070 // UTP Task Management Request List Base Address +#define UFS_HC_UTMRLBAU_OFFSET 0x0074 // UTP Task Management Request List Base Address Upper 32-Bits +#define UFS_HC_UTMRLDBR_OFFSET 0x0078 // UTP Task Management Request List Door Bell Register +#define UFS_HC_UTMRLCLR_OFFSET 0x007c // UTP Task Management Request List CLear Register +#define UFS_HC_UTMRLRSR_OFFSET 0x0080 // UTP Task Management Run-Stop Register +// +// UIC Command Register Offsets +// +#define UFS_HC_UIC_CMD_OFFSET 0x0090 // UIC Command Register +#define UFS_HC_UCMD_ARG1_OFFSET 0x0094 // UIC Command Argument 1 +#define UFS_HC_UCMD_ARG2_OFFSET 0x0098 // UIC Command Argument 2 +#define UFS_HC_UCMD_ARG3_OFFSET 0x009c // UIC Command Argument 3 +// +// UMA Register Offsets +// +#define UFS_HC_UMA_OFFSET 0x00b0 // Reserved for Unified Memory Extension + +#define UFS_HC_HCE_EN BIT0 +#define UFS_HC_HCS_DP BIT0 +#define UFS_HC_HCS_UCRDY BIT3 +#define UFS_HC_IS_ULSS BIT8 +#define UFS_HC_IS_UCCS BIT10 +#define UFS_HC_CAP_64ADDR BIT24 +#define UFS_HC_CAP_NUTMRS (BIT16 | BIT17 | BIT18) +#define UFS_HC_CAP_NUTRS (BIT0 | BIT1 | BIT2 | BIT3 | BIT4) +#define UFS_HC_UTMRLRSR BIT0 +#define UFS_HC_UTRLRSR BIT0 + +// +// The initial value of the OCS field of UTP TRD or TMRD descriptor +// defined in JEDEC JESD223 specification +// +#define UFS_HC_TRD_OCS_INIT_VALUE 0x0F + +// +// A maximum of length of 256KB is supported by PRDT entry +// +#define UFS_MAX_DATA_LEN_PER_PRD 0x40000 + +#define UFS_STORAGE_COMMAND_TYPE 0x01 + +#define UFS_REGULAR_COMMAND 0x00 +#define UFS_INTERRUPT_COMMAND 0x01 + +#pragma pack(1) + +// +// UFSHCI 2.0 Spec Section 5.2.1 Offset 00h: CAP - Controller Capabilities +// +typedef struct { + UINT8 Nutrs : 4; // Number of UTP Transfer Request Slots + UINT8 Rsvd1 : 4; + + UINT8 NoRtt; // Number of outstanding READY TO TRANSFER (RTT) requests supported + + UINT8 Nutmrs : 3; // Number of UTP Task Management Request Slots + UINT8 Rsvd2 : 4; + UINT8 AutoHs : 1; // Auto-Hibernation Support + + UINT8 As64 : 1; // 64-bit addressing supported + UINT8 Oodds : 1; // Out of order data delivery supported + UINT8 UicDmetms : 1; // UIC DME_TEST_MODE command supported + UINT8 Ume : 1; // Reserved for Unified Memory Extension + UINT8 Rsvd4 : 4; +} UFS_HC_CAP; + +// +// UFSHCI 2.0 Spec Section 5.2.2 Offset 08h: VER - UFS Version +// +typedef struct { + UINT8 Vs : 4; // Version Suffix + UINT8 Mnr : 4; // Minor version number + + UINT8 Mjr; // Major version number + + UINT16 Rsvd1; +} UFS_HC_VER; + +// +// UFSHCI 2.0 Spec Section 5.2.3 Offset 10h: HCPID - Host Controller Product ID +// +#define UFS_HC_PID UINT32 + +// +// UFSHCI 2.0 Spec Section 5.2.4 Offset 14h: HCMID - Host Controller Manufacturer ID +// +#define UFS_HC_MID UINT32 + +// +// UFSHCI 2.0 Spec Section 5.2.5 Offset 18h: AHIT - Auto-Hibernate Idle Timer +// +typedef struct { + UINT32 Ahitv : 10; // Auto-Hibernate Idle Timer Value + UINT32 Ts : 3; // Timer scale + UINT32 Rsvd1 : 19; +} UFS_HC_AHIT; + +// +// UFSHCI 2.0 Spec Section 5.3.1 Offset 20h: IS - Interrupt Status +// +typedef struct { + UINT16 Utrcs : 1; // UTP Transfer Request Completion Status + UINT16 Udepri : 1; // UIC DME_ENDPOINT_RESET Indication + UINT16 Ue : 1; // UIC Error + UINT16 Utms : 1; // UIC Test Mode Status + + UINT16 Upms : 1; // UIC Power Mode Status + UINT16 Uhxs : 1; // UIC Hibernate Exit Status + UINT16 Uhes : 1; // UIC Hibernate Enter Status + UINT16 Ulls : 1; // UIC Link Lost Status + + UINT16 Ulss : 1; // UIC Link Startup Status + UINT16 Utmrcs : 1; // UTP Task Management Request Completion Status + UINT16 Uccs : 1; // UIC Command Completion Status + UINT16 Dfes : 1; // Device Fatal Error Status + + UINT16 Utpes : 1; // UTP Error Status + UINT16 Rsvd1 : 3; + + UINT16 Hcfes : 1; // Host Controller Fatal Error Status + UINT16 Sbfes : 1; // System Bus Fatal Error Status + UINT16 Rsvd2 : 14; +} UFS_HC_IS; + +// +// UFSHCI 2.0 Spec Section 5.3.2 Offset 24h: IE - Interrupt Enable +// +typedef struct { + UINT16 Utrce : 1; // UTP Transfer Request Completion Enable + UINT16 Udeprie : 1; // UIC DME_ENDPOINT_RESET Enable + UINT16 Uee : 1; // UIC Error Enable + UINT16 Utmse : 1; // UIC Test Mode Status Enable + + UINT16 Upmse : 1; // UIC Power Mode Status Enable + UINT16 Uhxse : 1; // UIC Hibernate Exit Status Enable + UINT16 Uhese : 1; // UIC Hibernate Enter Status Enable + UINT16 Ullse : 1; // UIC Link Lost Status Enable + + UINT16 Ulsse : 1; // UIC Link Startup Status Enable + UINT16 Utmrce : 1; // UTP Task Management Request Completion Enable + UINT16 Ucce : 1; // UIC Command Completion Enable + UINT16 Dfee : 1; // Device Fatal Error Enable + + UINT16 Utpee : 1; // UTP Error Enable + UINT16 Rsvd1 : 3; + + UINT16 Hcfee : 1; // Host Controller Fatal Error Enable + UINT16 Sbfee : 1; // System Bus Fatal Error Enable + UINT16 Rsvd2 : 14; +} UFS_HC_IE; + +// +// UFSHCI 2.0 Spec Section 5.3.3 Offset 30h: HCS - Host Controller Status +// +typedef struct { + UINT8 Dp : 1; // Device Present + UINT8 UtrlRdy : 1; // UTP Transfer Request List Ready + UINT8 UtmrlRdy : 1; // UTP Task Management Request List Ready + UINT8 UcRdy : 1; // UIC COMMAND Ready + UINT8 Rsvd1 : 4; + + UINT8 Upmcrs : 3; // UIC Power Mode Change Request Status + UINT8 Rsvd2 : 1; // UIC Hibernate Exit Status Enable + UINT8 Utpec : 4; // UTP Error Code + + UINT8 TtagUtpE; // Task Tag of UTP error + UINT8 TlunUtpE; // Target LUN of UTP error +} UFS_HC_STATUS; + +// +// UFSHCI 2.0 Spec Section 5.3.4 Offset 34h: HCE - Host Controller Enable +// +typedef struct { + UINT32 Hce : 1; // Host Controller Enable + UINT32 Rsvd1 : 31; +} UFS_HC_ENABLE; + +// +// UFSHCI 2.0 Spec Section 5.3.5 Offset 38h: UECPA - Host UIC Error Code PHY Adapter Layer +// +typedef struct { + UINT32 Ec : 5; // UIC PHY Adapter Layer Error Code + UINT32 Rsvd1 : 26; + UINT32 Err : 1; // UIC PHY Adapter Layer Error +} UFS_HC_UECPA; + +// +// UFSHCI 2.0 Spec Section 5.3.6 Offset 3ch: UECDL - Host UIC Error Code Data Link Layer +// +typedef struct { + UINT32 Ec : 15; // UIC Data Link Layer Error Code + UINT32 Rsvd1 : 16; + UINT32 Err : 1; // UIC Data Link Layer Error +} UFS_HC_UECDL; + +// +// UFSHCI 2.0 Spec Section 5.3.7 Offset 40h: UECN - Host UIC Error Code Network Layer +// +typedef struct { + UINT32 Ec : 3; // UIC Network Layer Error Code + UINT32 Rsvd1 : 28; + UINT32 Err : 1; // UIC Network Layer Error +} UFS_HC_UECN; + +// +// UFSHCI 2.0 Spec Section 5.3.8 Offset 44h: UECT - Host UIC Error Code Transport Layer +// +typedef struct { + UINT32 Ec : 7; // UIC Transport Layer Error Code + UINT32 Rsvd1 : 24; + UINT32 Err : 1; // UIC Transport Layer Error +} UFS_HC_UECT; + +// +// UFSHCI 2.0 Spec Section 5.3.9 Offset 48h: UECDME - Host UIC Error Code +// +typedef struct { + UINT32 Ec : 1; // UIC DME Error Code + UINT32 Rsvd1 : 30; + UINT32 Err : 1; // UIC DME Error +} UFS_HC_UECDME; + +// +// UFSHCI 2.0 Spec Section 5.3.10 Offset 4Ch: UTRIACR - UTP Transfer Request Interrupt Aggregation Control Register +// +typedef struct { + UINT8 IaToVal; // Interrupt aggregation timeout value + + UINT8 IacTh : 5; // Interrupt aggregation counter threshold + UINT8 Rsvd1 : 3; + + UINT8 Ctr : 1; // Counter and Timer Reset + UINT8 Rsvd2 : 3; + UINT8 Iasb : 1; // Interrupt aggregation status bit + UINT8 Rsvd3 : 3; + + UINT8 IapwEn : 1; // Interrupt aggregation parameter write enable + UINT8 Rsvd4 : 6; + UINT8 IaEn : 1; // Interrupt Aggregation Enable/Disable +} UFS_HC_UTRIACR; + +// +// UFSHCI 2.0 Spec Section 5.4.1 Offset 50h: UTRLBA - UTP Transfer Request List Base Address +// +typedef struct { + UINT32 Rsvd1 : 10; + UINT32 UtrlBa : 22; // UTP Transfer Request List Base Address +} UFS_HC_UTRLBA; + +// +// UFSHCI 2.0 Spec Section 5.4.2 Offset 54h: UTRLBAU - UTP Transfer Request List Base Address Upper 32-bits +// +#define UFS_HC_UTRLBAU UINT32 + +// +// UFSHCI 2.0 Spec Section 5.4.3 Offset 58h: UTRLDBR - UTP Transfer Request List Door Bell Register +// +#define UFS_HC_UTRLDBR UINT32 + +// +// UFSHCI 2.0 Spec Section 5.4.4 Offset 5Ch: UTRLCLR - UTP Transfer Request List CLear Register +// +#define UFS_HC_UTRLCLR UINT32 + +#if 0 +// +// UFSHCI 2.0 Spec Section 5.4.5 Offset 60h: UTRLRSR - UTP Transfer Request List Run Stop Register +// +typedef struct { + UINT32 UtrlRsr : 1; // UTP Transfer Request List Run-Stop Register + UINT32 Rsvd1 : 31; +} UFS_HC_UTRLRSR; +#endif + +// +// UFSHCI 2.0 Spec Section 5.5.1 Offset 70h: UTMRLBA - UTP Task Management Request List Base Address +// +typedef struct { + UINT32 Rsvd1 : 10; + UINT32 UtmrlBa : 22; // UTP Task Management Request List Base Address +} UFS_HC_UTMRLBA; + +// +// UFSHCI 2.0 Spec Section 5.5.2 Offset 74h: UTMRLBAU - UTP Task Management Request List Base Address Upper 32-bits +// +#define UFS_HC_UTMRLBAU UINT32 + +// +// UFSHCI 2.0 Spec Section 5.5.3 Offset 78h: UTMRLDBR - UTP Task Management Request List Door Bell Register +// +typedef struct { + UINT32 UtmrlDbr : 8; // UTP Task Management Request List Door bell Register + UINT32 Rsvd1 : 24; +} UFS_HC_UTMRLDBR; + +// +// UFSHCI 2.0 Spec Section 5.5.4 Offset 7Ch: UTMRLCLR - UTP Task Management Request List CLear Register +// +typedef struct { + UINT32 UtmrlClr : 8; // UTP Task Management List Clear Register + UINT32 Rsvd1 : 24; +} UFS_HC_UTMRLCLR; + +#if 0 +// +// UFSHCI 2.0 Spec Section 5.5.5 Offset 80h: UTMRLRSR - UTP Task Management Request List Run Stop Register +// +typedef struct { + UINT32 UtmrlRsr : 1; // UTP Task Management Request List Run-Stop Register + UINT32 Rsvd1 : 31; +} UFS_HC_UTMRLRSR; +#endif + +// +// UFSHCI 2.0 Spec Section 5.6.1 Offset 90h: UICCMD - UIC Command +// +typedef struct { + UINT32 CmdOp : 8; // Command Opcode + UINT32 Rsvd1 : 24; +} UFS_HC_UICCMD; + +// +// UFSHCI 2.0 Spec Section 5.6.2 Offset 94h: UICCMDARG1 - UIC Command Argument 1 +// +#define UFS_HC_UICCMD_ARG1 UINT32 + +// +// UFSHCI 2.0 Spec Section 5.6.2 Offset 98h: UICCMDARG2 - UIC Command Argument 2 +// +#define UFS_HC_UICCMD_ARG2 UINT32 + +// +// UFSHCI 2.0 Spec Section 5.6.2 Offset 9ch: UICCMDARG3 - UIC Command Argument 3 +// +#define UFS_HC_UICCMD_ARG3 UINT32 + +// +// UIC command opcodes +// +typedef enum { + UfsUicDmeGet = 0x01, + UfsUicDmeSet = 0x02, + UfsUicDmePeerGet = 0x03, + UfsUicDmePeerSet = 0x04, + UfsUicDmePwrOn = 0x10, + UfsUicDmePwrOff = 0x11, + UfsUicDmeEnable = 0x12, + UfsUicDmeReset = 0x14, + UfsUicDmeEndpointReset = 0x15, + UfsUicDmeLinkStartup = 0x16, + UfsUicDmeHibernateEnter = 0x17, + UfsUicDmeHibernateExit = 0x18, + UfsUicDmeTestMode = 0x1A +} UFS_UIC_OPCODE; + +// +// UFSHCI 2.0 Spec Section 6.1.1 - UTP Transfer Request Descriptor +// +typedef struct { + // + // DW0 + // + UINT32 Rsvd1 : 24; + UINT32 Int : 1; /* Interrupt */ + UINT32 Dd : 2; /* Data Direction */ + UINT32 Rsvd2 : 1; + UINT32 Ct : 4; /* Command Type */ + + // + // DW1 + // + UINT32 Rsvd3; + + // + // DW2 + // + UINT32 Ocs : 8; /* Overall Command Status */ + UINT32 Rsvd4 : 24; + + // + // DW3 + // + UINT32 Rsvd5; + + // + // DW4 + // + UINT32 Rsvd6 : 7; + UINT32 UcdBa : 25; /* UTP Command Descriptor Base Address */ + + // + // DW5 + // + UINT32 UcdBaU; /* UTP Command Descriptor Base Address Upper 32-bits */ + + // + // DW6 + // + UINT16 RuL; /* Response UPIU Length */ + UINT16 RuO; /* Response UPIU Offset */ + + // + // DW7 + // + UINT16 PrdtL; /* PRDT Length */ + UINT16 PrdtO; /* PRDT Offset */ +} UTP_TRD; + +typedef enum { + UfsNoData = 0, + UfsDataOut = 1, + UfsDataIn = 2, + UfsDdReserved +} UFS_DATA_DIRECTION; + +typedef struct { + // + // DW0 + // + UINT32 Rsvd1 : 2; + UINT32 DbAddr : 30; /* Data Base Address */ + + // + // DW1 + // + UINT32 DbAddrU; /* Data Base Address Upper 32-bits */ + + // + // DW2 + // + UINT32 Rsvd2; + + // + // DW3 + // + UINT32 DbCount : 18; /* Data Byte Count */ + UINT32 Rsvd3 : 14; +} UTP_TR_PRD; + +// +// UFSHCI 2.0 Spec Section 6.2.1 - UTP Task Management Request Descriptor +// +typedef struct { + // + // DW0 + // + UINT32 Rsvd1 : 24; + UINT32 Int : 1; /* Interrupt */ + UINT32 Rsvd2 : 7; + + // + // DW1 + // + UINT32 Rsvd3; + + // + // DW2 + // + UINT32 Ocs : 8; /* Overall Command Status */ + UINT32 Rsvd4 : 24; + + // + // DW3 + // + UINT32 Rsvd5; + + // + // DW4 - DW11 + // + UTP_TM_REQ_UPIU TmReq; /* Task Management Request UPIU */ + + // + // DW12 - DW19 + // + UTP_TM_RESP_UPIU TmResp; /* Task Management Response UPIU */ +} UTP_TMRD; + +#pragma pack() + +#endif diff --git a/MdePkg/Include/Library/ArmLib.h b/MdePkg/Include/Library/ArmLib.h index 99260652f4c0..1287fca30c67 100644 --- a/MdePkg/Include/Library/ArmLib.h +++ b/MdePkg/Include/Library/ArmLib.h @@ -156,7 +156,7 @@ ArmInstructionCacheLineLength ( VOID ); -UINTN +UINT32 EFIAPI ArmCacheWritebackGranule ( VOID diff --git a/MdePkg/Include/Library/StackCheckLib.h b/MdePkg/Include/Library/StackCheckLib.h new file mode 100644 index 000000000000..bfbaa20cadf3 --- /dev/null +++ b/MdePkg/Include/Library/StackCheckLib.h @@ -0,0 +1,78 @@ +/** @file + This library provides stack cookie checking functions for symbols inserted by the compiler. This header + is not intended to be used directly by modules, but rather defines the expected interfaces to each supported + compiler, so that if the compiler interface is updated it is easier to track. + + Copyright (c) Microsoft Corporation. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef STACK_CHECK_LIB_H_ +#define STACK_CHECK_LIB_H_ + +#include <Base.h> + +#if defined (__GNUC__) || defined (__clang__) + +// The __stack_chk_guard is a random value placed on the stack between the stack variables +// and the return address so that continuously writing past the stack variables will cause +// the stack cookie to be overwritten. Before the function returns, the stack cookie value +// will be checked and if there is a mismatch then StackCheckLib handles the failure. +extern VOID *__stack_chk_guard; + +/** + Called when a stack cookie check fails. The return address is the failing address. + +**/ +VOID +EFIAPI +__stack_chk_fail ( + VOID + ); + +#elif defined (_MSC_VER) + +// The __security_cookie is a random value placed on the stack between the stack variables +// and the return address so that continuously writing past the stack variables will cause +// the stack cookie to be overwritten. Before the function returns, the stack cookie value +// will be checked and if there is a mismatch then StackCheckLib handles the failure. +extern VOID *__security_cookie; + +/** + Called when a buffer check fails. This functionality is dependent on MSVC + C runtime libraries and so is unsupported in UEFI. + +**/ +VOID +EFIAPI +__report_rangecheckfailure ( + VOID + ); + +/** + The GS handler is for checking the stack cookie during SEH or + EH exceptions and is unsupported in UEFI. + +**/ +VOID +EFIAPI +__GSHandlerCheck ( + VOID + ); + +/** + Checks the stack cookie value against __security_cookie and calls the + stack cookie failure handler if there is a mismatch. + + @param UINTN CheckValue The value to check against __security_cookie + +**/ +VOID +EFIAPI +__security_check_cookie ( + UINTN CheckValue + ); + +#endif // Compiler type + +#endif // STACK_CHECK_LIB_H_ diff --git a/MdePkg/Include/Library/StandaloneMmCoreEntryPoint.h b/MdePkg/Include/Library/StandaloneMmCoreEntryPoint.h new file mode 100644 index 000000000000..1bc95d9508fb --- /dev/null +++ b/MdePkg/Include/Library/StandaloneMmCoreEntryPoint.h @@ -0,0 +1,91 @@ +/** @file + Module entry point library for STANDALONE MM core. + +Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2016 - 2018, ARM Limited. All rights reserved.<BR> + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __MODULE_ENTRY_POINT_H__ +#define __MODULE_ENTRY_POINT_H__ + +/// +/// Global variable that contains a pointer to the Hob List passed into the STANDALONE MM Core entry point. +/// +extern VOID *gHobList; + +/** + The entry point of PE/COFF Image for the STANDALONE MM Core. + + This function is the entry point for the STANDALONE MM Core. This function is required to call + ProcessModuleEntryPointList() and ProcessModuleEntryPointList() is never expected to return. + The STANDALONE MM Core is responsible for calling ProcessLibraryConstructorList() as soon as the EFI + System Table and the image handle for the STANDALONE MM Core itself have been established. + If ProcessModuleEntryPointList() returns, then ASSERT() and halt the system. + + @param HobStart Pointer to the beginning of the HOB List passed in from the PEI Phase. + +**/ +VOID +EFIAPI +_ModuleEntryPoint ( + IN VOID *HobStart + ); + +/** + Required by the EBC compiler and identical in functionality to _ModuleEntryPoint(). + + This function is required to call _ModuleEntryPoint() passing in HobStart. + + @param HobStart Pointer to the beginning of the HOB List passed in from the PEI Phase. + +**/ +VOID +EFIAPI +EfiMain ( + IN VOID *HobStart + ); + +/** + Auto generated function that calls the library constructors for all of the module's dependent libraries. + + This function must be called by _ModuleEntryPoint(). + This function calls the set of library constructors for the set of library instances + that a module depends on. This includes library instances that a module depends on + directly and library instances that a module depends on indirectly through other + libraries. This function is auto generated by build tools and those build tools are + responsible for collecting the set of library instances, determine which ones have + constructors, and calling the library constructors in the proper order based upon + each of the library instances own dependencies. + + @param ImageHandle The image handle of the STANDALONE MM Core. + @param SystemTable A pointer to the EFI System Table. + +**/ +VOID +EFIAPI +ProcessLibraryConstructorList ( + IN EFI_HANDLE ImageHandle, + IN EFI_MM_SYSTEM_TABLE *MmSystemTable + ); + +/** + Autogenerated function that calls a set of module entry points. + + This function must be called by _ModuleEntryPoint(). + This function calls the set of module entry points. + This function is auto generated by build tools and those build tools are responsible + for collecting the module entry points and calling them in a specified order. + + @param HobStart Pointer to the beginning of the HOB List passed in from the PEI Phase. + +**/ +VOID +EFIAPI +ProcessModuleEntryPointList ( + IN VOID *HobStart + ); + +#endif diff --git a/MdePkg/Include/Library/UefiUsbLib.h b/MdePkg/Include/Library/UefiUsbLib.h index c570d71ad64a..a6570b7e8a9e 100644 --- a/MdePkg/Include/Library/UefiUsbLib.h +++ b/MdePkg/Include/Library/UefiUsbLib.h @@ -3,6 +3,7 @@ and the standard requests defined in USB 1.1 spec. Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2024, American Megatrends Intenational LLC. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -552,4 +553,134 @@ UsbClearEndpointHalt ( OUT UINT32 *Status ); +/** + Retrieve the interface descriptor details from the interface setting. + + This is an extended version of UsbIo->GetInterfaceDescriptor. It returns the interface + descriptor for an alternate setting of the interface without executing SET_INTERFACE + transfer. It also returns the number of class specific interfaces. + AlternateSetting parameter is the zero-based interface descriptor index that is used in USB + interface descriptor as USB_INTERFACE_DESCRIPTOR.AlternateSetting. + + @param[in] This A pointer to the EFI_USB_IO_PROTOCOL instance. + @param[in] AlternateSetting Interface alternate setting. + @param[out] Descriptor The caller allocated buffer to return the contents of the Interface descriptor. + @param[out] CsInterfaceNumber Number of class specific interfaces for this interface setting. + + @retval EFI_SUCCESS Output parameters were updated successfully. + @retval EFI_INVALID_PARAMETER Descriptor or CsInterfaceNumber is NULL. + @retval EFI_UNSUPPORTED Setting is greater than the number of alternate settings in this interface. + @retval EFI_DEVICE_ERROR Error reading device data. + +**/ +EFI_STATUS +EFIAPI +UsbGetInterfaceDescriptorSetting ( + IN EFI_USB_IO_PROTOCOL *This, + IN UINT16 AlternateSetting, + OUT EFI_USB_INTERFACE_DESCRIPTOR *Descriptor, + OUT UINTN *CsInterfacesNumber + ); + +/** + Retrieve the endpoint descriptor from the interface setting. + + This is an extended version of UsbIo->GetEndpointDescriptor. It returns the endpoint + descriptor for an alternate setting of a given interface. + AlternateSetting parameter is the zero-based interface descriptor index that is used in USB + interface descriptor as USB_INTERFACE_DESCRIPTOR.AlternateSetting. + + Note: The total number of endpoints can be retrieved from the interface descriptor + returned by EDKII_USBIO_EXT_GET_INTERFACE_DESCRIPTOR function. + + @param[in] This A pointer to the EFI_USB_IO_PROTOCOL instance. + @param[in] AlternateSetting Interface alternate setting. + @param[in] Index Index of the endpoint to retrieve. The valid range is 0..15. + @param[out] Descriptor A pointer to the caller allocated USB Interface Descriptor. + + @retval EFI_SUCCESS Output parameters were updated successfully. + @retval EFI_INVALID_PARAMETER Descriptor is NULL. + @retval EFI_UNSUPPORTED Setting is greater than the number of alternate settings in this interface. + @retval EFI_NOT_FOUND Index is greater than the number of endpoints in this interface. + @retval EFI_DEVICE_ERROR Error reading device data. + +**/ +EFI_STATUS +EFIAPI +UsbGetEndpointDescriptorSetting ( + IN EFI_USB_IO_PROTOCOL *This, + IN UINT16 AlternateSetting, + IN UINTN Index, + OUT EFI_USB_ENDPOINT_DESCRIPTOR *Descriptor + ); + +/** + Retrieve class specific interface descriptor. + + AlternateSetting parameter is the zero-based interface descriptor index that is used in USB + interface descriptor as USB_INTERFACE_DESCRIPTOR.AlternateSetting. + + @param[in] This A pointer to the EFI_USB_IO_PROTOCOL instance. + @param[in] AlternateSetting Interface alternate setting. + @param[in] Index Zero-based index of the class specific interface. + @param[in][out] BufferSize On input, the size in bytes of the return Descriptor buffer. + On output the size of data returned in Descriptor. + @param[out] Descriptor The buffer to return the contents of the class specific interface descriptor. May + be NULL with a zero BufferSize in order to determine the size buffer needed. + + @retval EFI_SUCCESS Output parameters were updated successfully. + @retval EFI_INVALID_PARAMETER BufferSize is NULL. + Buffer is NULL and *BufferSize is not zero. + @retval EFI_UNSUPPORTED Setting is greater than the number of alternate settings in this interface. + @retval EFI_NOT_FOUND Index is greater than the number of class specific interfaces. + @retval EFI_BUFFER_TOO_SMALL The BufferSize is too small for the result. BufferSize has been updated with the size + needed to complete the request. + @retval EFI_DEVICE_ERROR Error reading device data. + +**/ +EFI_STATUS +EFIAPI +UsbGetCsInterfaceDescriptor ( + IN EFI_USB_IO_PROTOCOL *This, + IN UINT16 AlternateSetting, + IN UINTN Index, + IN OUT UINTN *BufferSize, + OUT VOID *Buffer + ); + +/** + Retrieve class specific endpoint descriptor. + + AlternateSetting parameter is the zero-based interface descriptor index that is used in USB + interface descriptor as USB_INTERFACE_DESCRIPTOR.AlternateSetting. + + @param[in] This A pointer to the EFI_USB_IO_PROTOCOL instance. + @param[in] AlternateSetting Interface alternate setting. + @param[in] Index Zero-based index of the non-zero endpoint. + @param[in][out] BufferSize On input, the size in bytes of the return Descriptor buffer. + On output the size of data returned in Descriptor. + @param[out] Descriptor The buffer to return the contents of the class specific endpoint descriptor. May + be NULL with a zero BufferSize in order to determine the size buffer needed. + + @retval EFI_SUCCESS Output parameters were updated successfully. + @retval EFI_INVALID_PARAMETER BufferSize is NULL. + Buffer is NULL and *BufferSize is not zero. + @retval EFI_UNSUPPORTED Setting is greater than the number of alternate settings in this interface. + @retval EFI_NOT_FOUND Index is greater than the number of endpoints in this interface. + Endpoint does not have class specific endpoint descriptor. + @retval EFI_BUFFER_TOO_SMALL The BufferSize is too small for the result. BufferSize has been updated with the size + needed to complete the request. + @retval EFI_DEVICE_ERROR Error reading device data. + +**/ +EFI_STATUS +EFIAPI +UsbGetCsEndpointDescriptor ( + IN EFI_USB_IO_PROTOCOL *This, + IN UINT16 AlternateSetting, + IN UINTN Index, + IN OUT UINTN *BufferSize, + OUT VOID *Buffer + ); + #endif diff --git a/MdePkg/Include/Pi/PiHob.h b/MdePkg/Include/Pi/PiHob.h index d2a2da43c454..1040e6232540 100644 --- a/MdePkg/Include/Pi/PiHob.h +++ b/MdePkg/Include/Pi/PiHob.h @@ -5,7 +5,7 @@ Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent @par Revision Reference: - PI Version 1.6 + PI Version 1.9 **/ @@ -291,6 +291,7 @@ typedef UINT32 EFI_RESOURCE_ATTRIBUTE_TYPE; #define EFI_RESOURCE_ATTRIBUTE_ENCRYPTED 0x04000000 #define EFI_RESOURCE_ATTRIBUTE_SPECIAL_PURPOSE 0x08000000 +#define EFI_RESOURCE_ATTRIBUTE_HOT_PLUGGABLE 0x10000000 // // Physical memory relative reliability attribute. This // memory provides higher reliability relative to other diff --git a/MdePkg/Include/Pi/PiStatusCode.h b/MdePkg/Include/Pi/PiStatusCode.h index 2daa8887ebae..dc0186d578d4 100644 --- a/MdePkg/Include/Pi/PiStatusCode.h +++ b/MdePkg/Include/Pi/PiStatusCode.h @@ -2,6 +2,7 @@ StatusCode related definitions in PI. Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. SPDX-License-Identifier: BSD-2-Clause-Patent @par Revision Reference: @@ -140,6 +141,7 @@ typedef struct { #define EFI_COMPUTING_UNIT_CACHE (EFI_COMPUTING_UNIT | 0x00040000) #define EFI_COMPUTING_UNIT_MEMORY (EFI_COMPUTING_UNIT | 0x00050000) #define EFI_COMPUTING_UNIT_CHIPSET (EFI_COMPUTING_UNIT | 0x00060000) +#define EFI_COMPUTING_UNIT_MANAGEABILITY (EFI_COMPUTING_UNIT | 0x00070000) ///@} /// @@ -344,6 +346,16 @@ typedef struct { ///@} /// +/// Computing Unit Manageability Subclass Error Code definitions. +/// The detail information is reported by REPORT_STATUS_CODE_WITH_EXTENDED_DATA +// with ASCII string in EFI_STATUS_CODE_STRING_DATA. +///@{ +#define EFI_MANAGEABILITY_EC_REDFISH_COMMUNICATION_ERROR (EFI_SUBCLASS_SPECIFIC | 0x00000000) +#define EFI_MANAGEABILITY_EC_REDFISH_HOST_INTERFACE_ERROR (EFI_SUBCLASS_SPECIFIC | 0x00000001) +#define EFI_MANAGEABILITY_EC_REDFISH_BOOTSTRAP_CREDENTIAL_ERROR (EFI_SUBCLASS_SPECIFIC | 0x00000002) +///@} + +/// /// Peripheral Subclass definitions. /// Values of 12-127 are reserved for future use by this specification. /// Values of 128-255 are reserved for OEM use. diff --git a/MdePkg/Include/Ppi/Rng.h b/MdePkg/Include/Ppi/Rng.h new file mode 100644 index 000000000000..f44c5cc22122 --- /dev/null +++ b/MdePkg/Include/Ppi/Rng.h @@ -0,0 +1,27 @@ +/** @file + The Random Number Generator (RNG) PPI is used to provide random bits for use + in PEIMs, or entropy for seeding other random number generators. The PPI was + introduced in the PI 1.9 Specification. + + Copyright (c) Microsoft Corporation. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef RNG_PPI_H_ +#define RNG_PPI_H_ + +#include <Guid/Rng.h> + +/// +/// Global ID for the Random Number Generator PPI +/// +#define RNG_PPI_GUID \ + { \ + 0xeaed0a7e, 0x1a70, 0x4c2b, { 0x85, 0x58, 0x37, 0x17, 0x74, 0x56, 0xd8, 0x06 } \ + } + +typedef EFI_RNG_INTERFACE RNG_PPI; + +extern EFI_GUID gEfiRngPpiGuid; + +#endif diff --git a/MdePkg/Include/Protocol/AtaPassThru.h b/MdePkg/Include/Protocol/AtaPassThru.h index 545a88db7550..d6f0e79e251a 100644 --- a/MdePkg/Include/Protocol/AtaPassThru.h +++ b/MdePkg/Include/Protocol/AtaPassThru.h @@ -270,6 +270,10 @@ EFI_STATUS If PortMultiplierPort is the port multiplier port number of the last ATA device on the port of the ATA controller, then EFI_NOT_FOUND is returned. + When port multiplier is not connected to the Port, GetNextDevice() may either return + EFI_SUCCESS and set PortMultiplierPort to 0xFFFF or return EFI_NOT_FOUND (in which case the + PortMultiplierPort value is undefined). + @param[in] This A pointer to the EFI_ATA_PASS_THRU_PROTOCOL instance. @param[in] Port The port number present on the ATA controller. @param[in,out] PortMultiplierPort On input, a pointer to the port multiplier port number of an diff --git a/MdePkg/Include/Protocol/BootManagerPolicy.h b/MdePkg/Include/Protocol/BootManagerPolicy.h index dc27ccaa1dfd..ed4d86b9b871 100644 --- a/MdePkg/Include/Protocol/BootManagerPolicy.h +++ b/MdePkg/Include/Protocol/BootManagerPolicy.h @@ -5,6 +5,7 @@ to connect devices using platform policy. Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR> + Copyright (c) Microsoft Corporation.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -31,6 +32,11 @@ 0x113B2126, 0xFC8A, 0x11E3, { 0xBD, 0x6C, 0xB8, 0xE8, 0x56, 0x2C, 0xBA, 0xFA } \ } +#define EFI_BOOT_MANAGER_POLICY_STORAGE_GUID \ + { \ + 0xCD68FE79, 0xD3CB, 0x436E, { 0xA8, 0x50, 0xF4, 0x43, 0xC8, 0x8C, 0xFB, 0x49 } \ + } + typedef struct _EFI_BOOT_MANAGER_POLICY_PROTOCOL EFI_BOOT_MANAGER_POLICY_PROTOCOL; #define EFI_BOOT_MANAGER_POLICY_PROTOCOL_REVISION 0x00010000 @@ -98,6 +104,12 @@ EFI_STATUS EFI_BOOT_SERVICES.ConnectController(). If the Boot Manager has policy associated with connect all UEFI drivers this policy will be used. + If Class is EFI_BOOT_MANAGER_POLICY_STORAGE_GUID then the Boot Manager will + connect the protocols associated with the discoverable storage disks. This may include + EFI_BLOCK_IO_PROTOCOL, EFI_SIMPLE_FILE_SYSTEM_PROTOCOL, or other storage protocols + appropriate to the device. Some platforms may choose to restrict the connected + devices to exclude USB or other peripherals. + A platform can also define platform specific Class values as a properly generated EFI_GUID would never conflict with this specification. @@ -128,5 +140,6 @@ extern EFI_GUID gEfiBootManagerPolicyProtocolGuid; extern EFI_GUID gEfiBootManagerPolicyConsoleGuid; extern EFI_GUID gEfiBootManagerPolicyNetworkGuid; extern EFI_GUID gEfiBootManagerPolicyConnectAllGuid; +extern EFI_GUID gEfiBootManagerPolicyStorageGuid; #endif diff --git a/MdePkg/Include/Protocol/CcMeasurement.h b/MdePkg/Include/Protocol/CcMeasurement.h index 43d24036c5b8..ef9e111605d5 100644 --- a/MdePkg/Include/Protocol/CcMeasurement.h +++ b/MdePkg/Include/Protocol/CcMeasurement.h @@ -33,9 +33,10 @@ typedef struct { // // EFI_CC Type/SubType definition // -#define EFI_CC_TYPE_NONE 0 -#define EFI_CC_TYPE_SEV 1 -#define EFI_CC_TYPE_TDX 2 +#define EFI_CC_TYPE_NONE 0 +#define EFI_CC_TYPE_SEV 1 +#define EFI_CC_TYPE_TDX 2 +#define EFI_CC_TYPE_APTEE 3 typedef struct { UINT8 Type; diff --git a/MdePkg/Include/Protocol/DebugSupport.h b/MdePkg/Include/Protocol/DebugSupport.h index 8882d4425819..65f737140e7d 100644 --- a/MdePkg/Include/Protocol/DebugSupport.h +++ b/MdePkg/Include/Protocol/DebugSupport.h @@ -680,23 +680,23 @@ typedef struct { UINT32 STVAL; } EFI_SYSTEM_CONTEXT_RISCV64; -// -// LoongArch processor exception types. -// -// The exception types is located in the CSR ESTAT -// register offset 16 bits, width 6 bits. -// -// If you want to register an exception hook, you can -// shfit the number left by 16 bits, and the exception -// handler will know the types. -// -// For example: -// mCpu->CpuRegisterInterruptHandler ( -// mCpu, -// (EXCEPT_LOONGARCH_PPI << CSR_ESTAT_EXC_SHIFT), -// PpiExceptionHandler -// ); -// +/// +/// LoongArch processor exception types. +/// +/// The exception types is located in the CSR ESTAT +/// register offset 16 bits, width 6 bits. +/// +/// If you want to register an exception hook, you can +/// shfit the number left by 16 bits, and the exception +/// handler will know the types. +/// +/// For example: +/// mCpu->CpuRegisterInterruptHandler ( +/// mCpu, +/// (EXCEPT_LOONGARCH_PPI << CSR_ESTAT_EXC_SHIFT), +/// PpiExceptionHandler +/// ); +/// #define EXCEPT_LOONGARCH_INT 0 #define EXCEPT_LOONGARCH_PIL 1 #define EXCEPT_LOONGARCH_PIS 2 @@ -716,11 +716,22 @@ typedef struct { #define EXCEPT_LOONGARCH_SXD 16 #define EXCEPT_LOONGARCH_ASXD 17 #define EXCEPT_LOONGARCH_FPE 18 -#define EXCEPT_LOONGARCH_TBR 64 // For code only, there is no such type in the ISA spec, the TLB refill is defined for an independent exception. +#define EXCEPT_LOONGARCH_WPE 19 +#define EXCEPT_LOONGARCH_BTD 20 +#define EXCEPT_LOONGARCH_BTE 21 +#define EXCEPT_LOONGARCH_GSPR 22 +#define EXCEPT_LOONGARCH_HVC 23 +#define EXCEPT_LOONGARCH_GCXC 24 -// -// LoongArch processor Interrupt types. -// +/// +/// For coding convenience, define the maximum valid +/// LoongArch exception. +/// +#define MAX_LOONGARCH_EXCEPTION 64 + +/// +/// LoongArch processor Interrupt types. +/// #define EXCEPT_LOONGARCH_INT_SIP0 0 #define EXCEPT_LOONGARCH_INT_SIP1 1 #define EXCEPT_LOONGARCH_INT_IP0 2 @@ -735,11 +746,11 @@ typedef struct { #define EXCEPT_LOONGARCH_INT_TIMER 11 #define EXCEPT_LOONGARCH_INT_IPI 12 -// -// For coding convenience, define the maximum valid -// LoongArch interrupt. -// -#define MAX_LOONGARCH_INTERRUPT 14 +/// +/// For coding convenience, define the maximum valid +/// LoongArch interrupt. +/// +#define MAX_LOONGARCH_INTERRUPT 16 typedef struct { UINT64 R0; diff --git a/MdePkg/Include/Protocol/FirmwareManagement.h b/MdePkg/Include/Protocol/FirmwareManagement.h index 458101584396..e0dbee1c17da 100644 --- a/MdePkg/Include/Protocol/FirmwareManagement.h +++ b/MdePkg/Include/Protocol/FirmwareManagement.h @@ -351,7 +351,10 @@ EFI_STATUS @retval EFI_INVALID_PARAMETER The Image was NULL. @retval EFI_NOT_FOUND The current image is not copied to the buffer. @retval EFI_UNSUPPORTED The operation is not supported. - @retval EFI_SECURITY_VIOLATION The operation could not be performed due to an authentication failure. + @retval EFI_SECURITY_VIOLATION The operation could not be completed due to an image corruption. + If the image is able to be read, the Image buffer will be updated + with the retrieved image contents. + @retval EFI_DEVICE_ERROR The image could not be read. **/ typedef diff --git a/MdePkg/Include/Protocol/PxeBaseCode.h b/MdePkg/Include/Protocol/PxeBaseCode.h index 4fc44ca31300..e01f6fed71e7 100644 --- a/MdePkg/Include/Protocol/PxeBaseCode.h +++ b/MdePkg/Include/Protocol/PxeBaseCode.h @@ -34,7 +34,7 @@ typedef EFI_PXE_BASE_CODE_PROTOCOL EFI_PXE_BASE_CODE; /// /// Default IP TTL and ToS. /// -#define DEFAULT_TTL 16 +#define DEFAULT_TTL 64 #define DEFAULT_ToS 0 /// diff --git a/MdePkg/Include/Protocol/Rng.h b/MdePkg/Include/Protocol/Rng.h index 882d66011867..5c3e1daa1e2e 100644 --- a/MdePkg/Include/Protocol/Rng.h +++ b/MdePkg/Include/Protocol/Rng.h @@ -8,8 +8,10 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/ -#ifndef __EFI_RNG_PROTOCOL_H__ -#define __EFI_RNG_PROTOCOL_H__ +#ifndef EFI_RNG_PROTOCOL_H_ +#define EFI_RNG_PROTOCOL_H_ + +#include <Guid/Rng.h> /// /// Global ID for the Random Number Generator Protocol @@ -19,142 +21,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent 0x3152bca5, 0xeade, 0x433d, {0x86, 0x2e, 0xc0, 0x1c, 0xdc, 0x29, 0x1f, 0x44 } \ } -typedef struct _EFI_RNG_PROTOCOL EFI_RNG_PROTOCOL; - -/// -/// A selection of EFI_RNG_PROTOCOL algorithms. -/// The algorithms listed are optional, not meant to be exhaustive and be argmented by -/// vendors or other industry standards. -/// - -typedef EFI_GUID EFI_RNG_ALGORITHM; - -/// -/// The algorithms corresponds to SP800-90 as defined in -/// NIST SP 800-90, "Recommendation for Random Number Generation Using Deterministic Random -/// Bit Generators", March 2007. -/// -#define EFI_RNG_ALGORITHM_SP800_90_HASH_256_GUID \ - { \ - 0xa7af67cb, 0x603b, 0x4d42, {0xba, 0x21, 0x70, 0xbf, 0xb6, 0x29, 0x3f, 0x96 } \ - } -#define EFI_RNG_ALGORITHM_SP800_90_HMAC_256_GUID \ - { \ - 0xc5149b43, 0xae85, 0x4f53, {0x99, 0x82, 0xb9, 0x43, 0x35, 0xd3, 0xa9, 0xe7 } \ - } -#define EFI_RNG_ALGORITHM_SP800_90_CTR_256_GUID \ - { \ - 0x44f0de6e, 0x4d8c, 0x4045, {0xa8, 0xc7, 0x4d, 0xd1, 0x68, 0x85, 0x6b, 0x9e } \ - } -/// -/// The algorithms correspond to X9.31 as defined in -/// NIST, "Recommended Random Number Generator Based on ANSI X9.31 Appendix A.2.4 Using -/// the 3-Key Triple DES and AES Algorithm", January 2005. -/// -#define EFI_RNG_ALGORITHM_X9_31_3DES_GUID \ - { \ - 0x63c4785a, 0xca34, 0x4012, {0xa3, 0xc8, 0x0b, 0x6a, 0x32, 0x4f, 0x55, 0x46 } \ - } -#define EFI_RNG_ALGORITHM_X9_31_AES_GUID \ - { \ - 0xacd03321, 0x777e, 0x4d3d, {0xb1, 0xc8, 0x20, 0xcf, 0xd8, 0x88, 0x20, 0xc9 } \ - } -/// -/// The "raw" algorithm, when supported, is intended to provide entropy directly from -/// the source, without it going through some deterministic random bit generator. -/// -#define EFI_RNG_ALGORITHM_RAW \ - { \ - 0xe43176d7, 0xb6e8, 0x4827, {0xb7, 0x84, 0x7f, 0xfd, 0xc4, 0xb6, 0x85, 0x61 } \ - } -/// -/// The Arm Architecture states the RNDR that the DRBG algorithm should be compliant -/// with NIST SP800-90A, while not mandating a particular algorithm, so as to be -/// inclusive of different geographies. -/// -#define EFI_RNG_ALGORITHM_ARM_RNDR \ - { \ - 0x43d2fde3, 0x9d4e, 0x4d79, {0x02, 0x96, 0xa8, 0x9b, 0xca, 0x78, 0x08, 0x41} \ - } - -/** - Returns information about the random number generation implementation. - - @param[in] This A pointer to the EFI_RNG_PROTOCOL instance. - @param[in,out] RNGAlgorithmListSize On input, the size in bytes of RNGAlgorithmList. - On output with a return code of EFI_SUCCESS, the size - in bytes of the data returned in RNGAlgorithmList. On output - with a return code of EFI_BUFFER_TOO_SMALL, - the size of RNGAlgorithmList required to obtain the list. - @param[out] RNGAlgorithmList A caller-allocated memory buffer filled by the driver - with one EFI_RNG_ALGORITHM element for each supported - RNG algorithm. The list must not change across multiple - calls to the same driver. The first algorithm in the list - is the default algorithm for the driver. - - @retval EFI_SUCCESS The RNG algorithm list was returned successfully. - @retval EFI_UNSUPPORTED The services is not supported by this driver. - @retval EFI_DEVICE_ERROR The list of algorithms could not be retrieved due to a - hardware or firmware error. - @retval EFI_INVALID_PARAMETER One or more of the parameters are incorrect. - @retval EFI_BUFFER_TOO_SMALL The buffer RNGAlgorithmList is too small to hold the result. - -**/ -typedef -EFI_STATUS -(EFIAPI *EFI_RNG_GET_INFO)( - IN EFI_RNG_PROTOCOL *This, - IN OUT UINTN *RNGAlgorithmListSize, - OUT EFI_RNG_ALGORITHM *RNGAlgorithmList - ); - -/** - Produces and returns an RNG value using either the default or specified RNG algorithm. - - @param[in] This A pointer to the EFI_RNG_PROTOCOL instance. - @param[in] RNGAlgorithm A pointer to the EFI_RNG_ALGORITHM that identifies the RNG - algorithm to use. May be NULL in which case the function will - use its default RNG algorithm. - @param[in] RNGValueLength The length in bytes of the memory buffer pointed to by - RNGValue. The driver shall return exactly this numbers of bytes. - @param[out] RNGValue A caller-allocated memory buffer filled by the driver with the - resulting RNG value. - - @retval EFI_SUCCESS The RNG value was returned successfully. - @retval EFI_UNSUPPORTED The algorithm specified by RNGAlgorithm is not supported by - this driver. - @retval EFI_DEVICE_ERROR An RNG value could not be retrieved due to a hardware or - firmware error. - @retval EFI_NOT_READY There is not enough random data available to satisfy the length - requested by RNGValueLength. - @retval EFI_INVALID_PARAMETER RNGValue is NULL or RNGValueLength is zero. - -**/ -typedef -EFI_STATUS -(EFIAPI *EFI_RNG_GET_RNG)( - IN EFI_RNG_PROTOCOL *This, - IN EFI_RNG_ALGORITHM *RNGAlgorithm OPTIONAL, - IN UINTN RNGValueLength, - OUT UINT8 *RNGValue - ); - -/// -/// The Random Number Generator (RNG) protocol provides random bits for use in -/// applications, or entropy for seeding other random number generators. -/// -struct _EFI_RNG_PROTOCOL { - EFI_RNG_GET_INFO GetInfo; - EFI_RNG_GET_RNG GetRNG; -}; +typedef EFI_RNG_INTERFACE EFI_RNG_PROTOCOL; extern EFI_GUID gEfiRngProtocolGuid; -extern EFI_GUID gEfiRngAlgorithmSp80090Hash256Guid; -extern EFI_GUID gEfiRngAlgorithmSp80090Hmac256Guid; -extern EFI_GUID gEfiRngAlgorithmSp80090Ctr256Guid; -extern EFI_GUID gEfiRngAlgorithmX9313DesGuid; -extern EFI_GUID gEfiRngAlgorithmX931AesGuid; -extern EFI_GUID gEfiRngAlgorithmRaw; -extern EFI_GUID gEfiRngAlgorithmArmRndr; #endif diff --git a/MdePkg/Include/Uefi/UefiSpec.h b/MdePkg/Include/Uefi/UefiSpec.h index 7c21234eecb2..d469d2a36ce0 100644 --- a/MdePkg/Include/Uefi/UefiSpec.h +++ b/MdePkg/Include/Uefi/UefiSpec.h @@ -106,6 +106,16 @@ typedef enum { #define EFI_MEMORY_CPU_CRYPTO 0x0000000000080000ULL // +// If this flag is set, the memory region is present and capable of having +// memory dynamically removed from the platform. This attribute serves as +// a hint to the OS prior to its ACPI subsystem initialization to avoid +// allocating this memory for core OS data or code that cannot be dynamically +// relocated at runtime. If this flag is clear, the memory region is not +// capable of being dynamically removed from the platform at runtime. +// +#define EFI_MEMORY_HOT_PLUGGABLE 0x0000000000100000 + +// // Runtime memory attribute // #define EFI_MEMORY_RUNTIME 0x8000000000000000ULL @@ -1839,21 +1849,24 @@ EFI_STATUS // // EFI Runtime Services Table // -#define EFI_SYSTEM_TABLE_SIGNATURE SIGNATURE_64 ('I','B','I',' ','S','Y','S','T') -#define EFI_2_80_SYSTEM_TABLE_REVISION ((2 << 16) | (80)) -#define EFI_2_70_SYSTEM_TABLE_REVISION ((2 << 16) | (70)) -#define EFI_2_60_SYSTEM_TABLE_REVISION ((2 << 16) | (60)) -#define EFI_2_50_SYSTEM_TABLE_REVISION ((2 << 16) | (50)) -#define EFI_2_40_SYSTEM_TABLE_REVISION ((2 << 16) | (40)) -#define EFI_2_31_SYSTEM_TABLE_REVISION ((2 << 16) | (31)) -#define EFI_2_30_SYSTEM_TABLE_REVISION ((2 << 16) | (30)) -#define EFI_2_20_SYSTEM_TABLE_REVISION ((2 << 16) | (20)) -#define EFI_2_10_SYSTEM_TABLE_REVISION ((2 << 16) | (10)) -#define EFI_2_00_SYSTEM_TABLE_REVISION ((2 << 16) | (00)) -#define EFI_1_10_SYSTEM_TABLE_REVISION ((1 << 16) | (10)) -#define EFI_1_02_SYSTEM_TABLE_REVISION ((1 << 16) | (02)) -#define EFI_SYSTEM_TABLE_REVISION EFI_2_70_SYSTEM_TABLE_REVISION -#define EFI_SPECIFICATION_VERSION EFI_SYSTEM_TABLE_REVISION +#define EFI_SYSTEM_TABLE_SIGNATURE SIGNATURE_64 ('I','B','I',' ','S','Y','S','T') +#define EFI_2_110_SYSTEM_TABLE_REVISION ((2 << 16) | (110)) +#define EFI_2_100_SYSTEM_TABLE_REVISION ((2 << 16) | (100)) +#define EFI_2_90_SYSTEM_TABLE_REVISION ((2 << 16) | (90)) +#define EFI_2_80_SYSTEM_TABLE_REVISION ((2 << 16) | (80)) +#define EFI_2_70_SYSTEM_TABLE_REVISION ((2 << 16) | (70)) +#define EFI_2_60_SYSTEM_TABLE_REVISION ((2 << 16) | (60)) +#define EFI_2_50_SYSTEM_TABLE_REVISION ((2 << 16) | (50)) +#define EFI_2_40_SYSTEM_TABLE_REVISION ((2 << 16) | (40)) +#define EFI_2_31_SYSTEM_TABLE_REVISION ((2 << 16) | (31)) +#define EFI_2_30_SYSTEM_TABLE_REVISION ((2 << 16) | (30)) +#define EFI_2_20_SYSTEM_TABLE_REVISION ((2 << 16) | (20)) +#define EFI_2_10_SYSTEM_TABLE_REVISION ((2 << 16) | (10)) +#define EFI_2_00_SYSTEM_TABLE_REVISION ((2 << 16) | (00)) +#define EFI_1_10_SYSTEM_TABLE_REVISION ((1 << 16) | (10)) +#define EFI_1_02_SYSTEM_TABLE_REVISION ((1 << 16) | (02)) +#define EFI_SYSTEM_TABLE_REVISION EFI_2_70_SYSTEM_TABLE_REVISION +#define EFI_SPECIFICATION_VERSION EFI_SYSTEM_TABLE_REVISION #define EFI_RUNTIME_SERVICES_SIGNATURE SIGNATURE_64 ('R','U','N','T','S','E','R','V') #define EFI_RUNTIME_SERVICES_REVISION EFI_SPECIFICATION_VERSION |