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authorKristof Provost <kp@FreeBSD.org>2020-07-06 21:29:50 +0000
committerKristof Provost <kp@FreeBSD.org>2020-07-06 21:29:50 +0000
commit38d715f78937d5a641d06affb82e57bfe8b3e580 (patch)
tree76669901de0569844f0c75b4f218d2e90a8663c7 /cddl
parent26dd4278000890378d1660509fc68c2a03aa4fcb (diff)
riscv plic: Do not complete interrupts until the interrupt handler has run
We cannot complete the interrupt (i.e. write to the claims/complete register until the interrupt handler has actually run. We don't run the interrupt handler immediately from intr_isrc_dispatch(), we only schedule it for later execution. If we immediately complete it (i.e. before the interrupt handler proper has run) the interrupt may be triggered again if the interrupt source remains set. From RISC-V Instruction Set Manual: Volume II: Priviliged Architecture, 7.4 Interrupt Gateways: "If a level-sensitive interrupt source deasserts the interrupt after the PLIC core accepts the request and before the interrupt is serviced, the interrupt request remains present in the IP bit of the PLIC core and will be serviced by a handler, which will then have to determine that the interrupt device no longer requires service." In other words, we may receive interrupts twice. Avoid that by postponing the completion until after the interrupt handler has run. If the interrupt is handled by a filter rather than by scheduling an interrupt thread we must also complete the interrupt, so set up a post_filter handler (which is the same as the post_ithread handler). Reviewed by: mhorne Sponsored by: Axiado Differential Revision: https://reviews.freebsd.org/D25531
Notes: svn path=/head/; revision=362977
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