diff options
| author | cvs2svn <cvs2svn@FreeBSD.org> | 2001-11-01 09:24:30 +0000 |
|---|---|---|
| committer | cvs2svn <cvs2svn@FreeBSD.org> | 2001-11-01 09:24:30 +0000 |
| commit | 21f2b10c40d508090141a64e9b7367b5e13844b0 (patch) | |
| tree | 6d6c155b41795ced8acdb7e3ff444e992497fbbb /contrib/binutils/include/opcode | |
| parent | adc940bfc719044f1b025222d66bed9e62c130ba (diff) | |
This commit was manufactured by cvs2svn to create tagvendor/binutils/2.11.20011031
'binutils-vendor-binutils_2_11_cvs_20011031'.
Diffstat (limited to 'contrib/binutils/include/opcode')
| -rw-r--r-- | contrib/binutils/include/opcode/mips.h | 749 | ||||
| -rw-r--r-- | contrib/binutils/include/opcode/tic30.h | 691 | ||||
| -rw-r--r-- | contrib/binutils/include/opcode/v850.h | 166 |
3 files changed, 0 insertions, 1606 deletions
diff --git a/contrib/binutils/include/opcode/mips.h b/contrib/binutils/include/opcode/mips.h deleted file mode 100644 index 68fe57a8aae2..000000000000 --- a/contrib/binutils/include/opcode/mips.h +++ /dev/null @@ -1,749 +0,0 @@ -/* mips.h. Mips opcode list for GDB, the GNU debugger. - Copyright 1993, 94, 95, 96, 1997 Free Software Foundation, Inc. - Contributed by Ralph Campbell and OSF - Commented and modified by Ian Lance Taylor, Cygnus Support - -This file is part of GDB, GAS, and the GNU binutils. - -GDB, GAS, and the GNU binutils are free software; you can redistribute -them and/or modify them under the terms of the GNU General Public -License as published by the Free Software Foundation; either version -1, or (at your option) any later version. - -GDB, GAS, and the GNU binutils are distributed in the hope that they -will be useful, but WITHOUT ANY WARRANTY; without even the implied -warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -the GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this file; see the file COPYING. If not, write to the Free -Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#ifndef _MIPS_H_ -#define _MIPS_H_ - -/* These are bit masks and shift counts to use to access the various - fields of an instruction. To retrieve the X field of an - instruction, use the expression - (i >> OP_SH_X) & OP_MASK_X - To set the same field (to j), use - i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X) - - Make sure you use fields that are appropriate for the instruction, - of course. - - The 'i' format uses OP, RS, RT and IMMEDIATE. - - The 'j' format uses OP and TARGET. - - The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT. - - The 'b' format uses OP, RS, RT and DELTA. - - The floating point 'i' format uses OP, RS, RT and IMMEDIATE. - - The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT. - - A breakpoint instruction uses OP, CODE and SPEC (10 bits of the - breakpoint instruction are not defined; Kane says the breakpoint - code field in BREAK is 20 bits; yet MIPS assemblers and debuggers - only use ten bits). An optional two-operand form of break/sdbbp - allows the lower ten bits to be set too. - - The syscall instruction uses SYSCALL. - - The general coprocessor instructions use COPZ. */ - -#define OP_MASK_OP 0x3f -#define OP_SH_OP 26 -#define OP_MASK_RS 0x1f -#define OP_SH_RS 21 -#define OP_MASK_FR 0x1f -#define OP_SH_FR 21 -#define OP_MASK_FMT 0x1f -#define OP_SH_FMT 21 -#define OP_MASK_BCC 0x7 -#define OP_SH_BCC 18 -#define OP_MASK_CODE 0x3ff -#define OP_SH_CODE 16 -#define OP_MASK_CODE2 0x3ff -#define OP_SH_CODE2 6 -#define OP_MASK_RT 0x1f -#define OP_SH_RT 16 -#define OP_MASK_FT 0x1f -#define OP_SH_FT 16 -#define OP_MASK_CACHE 0x1f -#define OP_SH_CACHE 16 -#define OP_MASK_RD 0x1f -#define OP_SH_RD 11 -#define OP_MASK_FS 0x1f -#define OP_SH_FS 11 -#define OP_MASK_PREFX 0x1f -#define OP_SH_PREFX 11 -#define OP_MASK_CCC 0x7 -#define OP_SH_CCC 8 -#define OP_MASK_SYSCALL 0xfffff -#define OP_SH_SYSCALL 6 -#define OP_MASK_SHAMT 0x1f -#define OP_SH_SHAMT 6 -#define OP_MASK_FD 0x1f -#define OP_SH_FD 6 -#define OP_MASK_TARGET 0x3ffffff -#define OP_SH_TARGET 0 -#define OP_MASK_COPZ 0x1ffffff -#define OP_SH_COPZ 0 -#define OP_MASK_IMMEDIATE 0xffff -#define OP_SH_IMMEDIATE 0 -#define OP_MASK_DELTA 0xffff -#define OP_SH_DELTA 0 -#define OP_MASK_FUNCT 0x3f -#define OP_SH_FUNCT 0 -#define OP_MASK_SPEC 0x3f -#define OP_SH_SPEC 0 -#define OP_SH_LOCC 8 /* FP condition code */ -#define OP_SH_HICC 18 /* FP condition code */ -#define OP_MASK_CC 0x7 -#define OP_SH_COP1NORM 25 /* Normal COP1 encoding */ -#define OP_MASK_COP1NORM 0x1 /* a single bit */ -#define OP_SH_COP1SPEC 21 /* COP1 encodings */ -#define OP_MASK_COP1SPEC 0xf -#define OP_MASK_COP1SCLR 0x4 -#define OP_MASK_COP1CMP 0x3 -#define OP_SH_COP1CMP 4 -#define OP_SH_FORMAT 21 /* FP short format field */ -#define OP_MASK_FORMAT 0x7 -#define OP_SH_TRUE 16 -#define OP_MASK_TRUE 0x1 -#define OP_SH_GE 17 -#define OP_MASK_GE 0x01 -#define OP_SH_UNSIGNED 16 -#define OP_MASK_UNSIGNED 0x1 -#define OP_SH_HINT 16 -#define OP_MASK_HINT 0x1f -#define OP_SH_MMI 0 /* Multimedia (parallel) op */ -#define OP_MASK_MMI 0x3f -#define OP_SH_MMISUB 6 -#define OP_MASK_MMISUB 0x1f -#define OP_MASK_PERFREG 0x1f /* Performance monitoring */ -#define OP_SH_PERFREG 1 - -/* This structure holds information for a particular instruction. */ - -struct mips_opcode -{ - /* The name of the instruction. */ - const char *name; - /* A string describing the arguments for this instruction. */ - const char *args; - /* The basic opcode for the instruction. When assembling, this - opcode is modified by the arguments to produce the actual opcode - that is used. If pinfo is INSN_MACRO, then this is 0. */ - unsigned long match; - /* If pinfo is not INSN_MACRO, then this is a bit mask for the - relevant portions of the opcode when disassembling. If the - actual opcode anded with the match field equals the opcode field, - then we have found the correct instruction. If pinfo is - INSN_MACRO, then this field is the macro identifier. */ - unsigned long mask; - /* For a macro, this is INSN_MACRO. Otherwise, it is a collection - of bits describing the instruction, notably any relevant hazard - information. */ - unsigned long pinfo; - /* A collection of bits describing the instruction sets of which this - instruction or macro is a member. */ - unsigned long membership; -}; - -/* These are the characters which may appears in the args field of an - instruction. They appear in the order in which the fields appear - when the instruction is used. Commas and parentheses in the args - string are ignored when assembling, and written into the output - when disassembling. - - Each of these characters corresponds to a mask field defined above. - - "<" 5 bit shift amount (OP_*_SHAMT) - ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT) - "a" 26 bit target address (OP_*_TARGET) - "b" 5 bit base register (OP_*_RS) - "c" 10 bit breakpoint code (OP_*_CODE) - "d" 5 bit destination register specifier (OP_*_RD) - "h" 5 bit prefx hint (OP_*_PREFX) - "i" 16 bit unsigned immediate (OP_*_IMMEDIATE) - "j" 16 bit signed immediate (OP_*_DELTA) - "k" 5 bit cache opcode in target register position (OP_*_CACHE) - "o" 16 bit signed offset (OP_*_DELTA) - "p" 16 bit PC relative branch target address (OP_*_DELTA) - "q" 10 bit extra breakpoint code (OP_*_CODE2) - "r" 5 bit same register used as both source and target (OP_*_RS) - "s" 5 bit source register specifier (OP_*_RS) - "t" 5 bit target register (OP_*_RT) - "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE) - "v" 5 bit same register used as both source and destination (OP_*_RS) - "w" 5 bit same register used as both target and destination (OP_*_RT) - "C" 25 bit coprocessor function code (OP_*_COPZ) - "B" 20 bit syscall function code (OP_*_SYSCALL) - "x" accept and ignore register name - "z" must be zero register - - Floating point instructions: - "D" 5 bit destination register (OP_*_FD) - "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up) - "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up) - "S" 5 bit fs source 1 register (OP_*_FS) - "T" 5 bit ft source 2 register (OP_*_FT) - "R" 5 bit fr source 3 register (OP_*_FR) - "V" 5 bit same register used as floating source and destination (OP_*_FS) - "W" 5 bit same register used as floating target and destination (OP_*_FT) - - Coprocessor instructions: - "E" 5 bit target register (OP_*_RT) - "G" 5 bit destination register (OP_*_RD) - "P" 5 bit performance-monitor register (OP_*_PERFREG) - - Macro instructions: - "A" General 32 bit expression - "I" 32 bit immediate - "F" 64 bit floating point constant in .rdata - "L" 64 bit floating point constant in .lit8 - "f" 32 bit floating point constant - "l" 32 bit floating point constant in .lit4 - - Other: - "()" parens surrounding optional value - "," separates operands - - Characters used so far, for quick reference when adding more: - "<>()," - "ABCDEFGILMNSTRVW" - "abcdfhijklopqrstuvwxz" -*/ - -/* These are the bits which may be set in the pinfo field of an - instructions, if it is not equal to INSN_MACRO. */ - -/* Modifies the general purpose register in OP_*_RD. */ -#define INSN_WRITE_GPR_D 0x00000001 -/* Modifies the general purpose register in OP_*_RT. */ -#define INSN_WRITE_GPR_T 0x00000002 -/* Modifies general purpose register 31. */ -#define INSN_WRITE_GPR_31 0x00000004 -/* Modifies the floating point register in OP_*_FD. */ -#define INSN_WRITE_FPR_D 0x00000008 -/* Modifies the floating point register in OP_*_FS. */ -#define INSN_WRITE_FPR_S 0x00000010 -/* Modifies the floating point register in OP_*_FT. */ -#define INSN_WRITE_FPR_T 0x00000020 -/* Reads the general purpose register in OP_*_RS. */ -#define INSN_READ_GPR_S 0x00000040 -/* Reads the general purpose register in OP_*_RT. */ -#define INSN_READ_GPR_T 0x00000080 -/* Reads the floating point register in OP_*_FS. */ -#define INSN_READ_FPR_S 0x00000100 -/* Reads the floating point register in OP_*_FT. */ -#define INSN_READ_FPR_T 0x00000200 -/* Reads the floating point register in OP_*_FR. */ -#define INSN_READ_FPR_R 0x00000400 -/* Modifies coprocessor condition code. */ -#define INSN_WRITE_COND_CODE 0x00000800 -/* Reads coprocessor condition code. */ -#define INSN_READ_COND_CODE 0x00001000 -/* TLB operation. */ -#define INSN_TLB 0x00002000 -/* Reads coprocessor register other than floating point register. */ -#define INSN_COP 0x00004000 -/* Instruction loads value from memory, requiring delay. */ -#define INSN_LOAD_MEMORY_DELAY 0x00008000 -/* Instruction loads value from coprocessor, requiring delay. */ -#define INSN_LOAD_COPROC_DELAY 0x00010000 -/* Instruction has unconditional branch delay slot. */ -#define INSN_UNCOND_BRANCH_DELAY 0x00020000 -/* Instruction has conditional branch delay slot. */ -#define INSN_COND_BRANCH_DELAY 0x00040000 -/* Conditional branch likely: if branch not taken, insn nullified. */ -#define INSN_COND_BRANCH_LIKELY 0x00080000 -/* Moves to coprocessor register, requiring delay. */ -#define INSN_COPROC_MOVE_DELAY 0x00100000 -/* Loads coprocessor register from memory, requiring delay. */ -#define INSN_COPROC_MEMORY_DELAY 0x00200000 -/* Reads the HI register. */ -#define INSN_READ_HI 0x00400000 -/* Reads the LO register. */ -#define INSN_READ_LO 0x00800000 -/* Modifies the HI register. */ -#define INSN_WRITE_HI 0x01000000 -/* Modifies the LO register. */ -#define INSN_WRITE_LO 0x02000000 -/* Takes a trap (easier to keep out of delay slot). */ -#define INSN_TRAP 0x04000000 -/* Instruction stores value into memory. */ -#define INSN_STORE_MEMORY 0x08000000 -/* Instruction uses single precision floating point. */ -#define FP_S 0x10000000 -/* Instruction uses double precision floating point. */ -#define FP_D 0x20000000 -/* Instruction is part of the tx39's integer multiply family. */ -#define INSN_MULT 0x40000000 -/* Instruction synchronize shared memory. */ -#define INSN_SYNC 0x80000000 - -/* Instruction is actually a macro. It should be ignored by the - disassembler, and requires special treatment by the assembler. */ -#define INSN_MACRO 0xffffffff - - - - - -/* MIPS ISA field--CPU level at which insn is supported. */ -#define INSN_ISA 0x0000000F -/* An instruction which is not part of any basic MIPS ISA. - (ie it is a chip specific instruction) */ -#define INSN_NO_ISA 0x00000000 -/* MIPS ISA 1 instruction. */ -#define INSN_ISA1 0x00000001 -/* MIPS ISA 2 instruction (R6000 or R4000). */ -#define INSN_ISA2 0x00000002 -/* MIPS ISA 3 instruction (R4000). */ -#define INSN_ISA3 0x00000003 -/* MIPS ISA 4 instruction (R8000). */ -#define INSN_ISA4 0x00000004 -#define INSN_ISA5 0x00000005 - -/* Chip specific instructions. These are bitmasks. */ -/* MIPS R4650 instruction. */ -#define INSN_4650 0x00000010 -/* LSI R4010 instruction. */ -#define INSN_4010 0x00000020 -/* NEC VR4100 instruction. */ -#define INSN_4100 0x00000040 -/* Toshiba R3900 instruction. */ -#define INSN_3900 0x00000080 - -/* 32-bit code running on a ISA3+ CPU. */ -#define INSN_GP32 0x00001000 - -/* Test for membership in an ISA including chip specific ISAs. - INSN is pointer to an element of the opcode table; ISA is the - specified ISA to test against; and CPU is the CPU specific ISA - to test, or zero if no CPU specific ISA test is desired. - The gp32 arg is set when you need to force 32-bit register usage on - a machine with 64-bit registers; see the documentation under -mgp32 - in the MIPS gas docs. */ - -#define OPCODE_IS_MEMBER(insn,isa,cpu,gp32) \ - ((((insn)->membership & INSN_ISA) != 0 \ - && ((insn)->membership & INSN_ISA) <= isa \ - && ((insn)->membership & INSN_GP32 ? gp32 : 1)) \ - || (cpu == 4650 \ - && ((insn)->membership & INSN_4650) != 0) \ - || (cpu == 4010 \ - && ((insn)->membership & INSN_4010) != 0) \ - || ((cpu == 4100 \ - || cpu == 4111 \ - ) \ - && ((insn)->membership & INSN_4100) != 0) \ - || (cpu == 3900 \ - && ((insn)->membership & INSN_3900) != 0)) - -/* This is a list of macro expanded instructions. - * - * _I appended means immediate - * _A appended means address - * _AB appended means address with base register - * _D appended means 64 bit floating point constant - * _S appended means 32 bit floating point constant - */ -enum { - M_ABS, - M_ADD_I, - M_ADDU_I, - M_AND_I, - M_BEQ, - M_BEQ_I, - M_BEQL_I, - M_BGE, - M_BGEL, - M_BGE_I, - M_BGEL_I, - M_BGEU, - M_BGEUL, - M_BGEU_I, - M_BGEUL_I, - M_BGT, - M_BGTL, - M_BGT_I, - M_BGTL_I, - M_BGTU, - M_BGTUL, - M_BGTU_I, - M_BGTUL_I, - M_BLE, - M_BLEL, - M_BLE_I, - M_BLEL_I, - M_BLEU, - M_BLEUL, - M_BLEU_I, - M_BLEUL_I, - M_BLT, - M_BLTL, - M_BLT_I, - M_BLTL_I, - M_BLTU, - M_BLTUL, - M_BLTU_I, - M_BLTUL_I, - M_BNE, - M_BNE_I, - M_BNEL_I, - M_DABS, - M_DADD_I, - M_DADDU_I, - M_DDIV_3, - M_DDIV_3I, - M_DDIVU_3, - M_DDIVU_3I, - M_DIV_3, - M_DIV_3I, - M_DIVU_3, - M_DIVU_3I, - M_DLA_AB, - M_DLI, - M_DMUL, - M_DMUL_I, - M_DMULO, - M_DMULO_I, - M_DMULOU, - M_DMULOU_I, - M_DREM_3, - M_DREM_3I, - M_DREMU_3, - M_DREMU_3I, - M_DSUB_I, - M_DSUBU_I, - M_DSUBU_I_2, - M_J_A, - M_JAL_1, - M_JAL_2, - M_JAL_A, - M_L_DOB, - M_L_DAB, - M_LA_AB, - M_LB_A, - M_LB_AB, - M_LBU_A, - M_LBU_AB, - M_LD_A, - M_LD_OB, - M_LD_AB, - M_LDC1_AB, - M_LDC2_AB, - M_LDC3_AB, - M_LDL_AB, - M_LDR_AB, - M_LH_A, - M_LH_AB, - M_LHU_A, - M_LHU_AB, - M_LI, - M_LI_D, - M_LI_DD, - M_LI_S, - M_LI_SS, - M_LL_AB, - M_LLD_AB, - M_LS_A, - M_LW_A, - M_LW_AB, - M_LWC0_A, - M_LWC0_AB, - M_LWC1_A, - M_LWC1_AB, - M_LWC2_A, - M_LWC2_AB, - M_LWC3_A, - M_LWC3_AB, - M_LWL_A, - M_LWL_AB, - M_LWR_A, - M_LWR_AB, - M_LWU_AB, - M_MUL, - M_MUL_I, - M_MULO, - M_MULO_I, - M_MULOU, - M_MULOU_I, - M_NOR_I, - M_OR_I, - M_REM_3, - M_REM_3I, - M_REMU_3, - M_REMU_3I, - M_ROL, - M_ROL_I, - M_ROR, - M_ROR_I, - M_S_DA, - M_S_DOB, - M_S_DAB, - M_S_S, - M_SC_AB, - M_SCD_AB, - M_SD_A, - M_SD_OB, - M_SD_AB, - M_SDC1_AB, - M_SDC2_AB, - M_SDC3_AB, - M_SDL_AB, - M_SDR_AB, - M_SEQ, - M_SEQ_I, - M_SGE, - M_SGE_I, - M_SGEU, - M_SGEU_I, - M_SGT, - M_SGT_I, - M_SGTU, - M_SGTU_I, - M_SLE, - M_SLE_I, - M_SLEU, - M_SLEU_I, - M_SLT_I, - M_SLTU_I, - M_SNE, - M_SNE_I, - M_SB_A, - M_SB_AB, - M_SH_A, - M_SH_AB, - M_SW_A, - M_SW_AB, - M_SWC0_A, - M_SWC0_AB, - M_SWC1_A, - M_SWC1_AB, - M_SWC2_A, - M_SWC2_AB, - M_SWC3_A, - M_SWC3_AB, - M_SWL_A, - M_SWL_AB, - M_SWR_A, - M_SWR_AB, - M_SUB_I, - M_SUBU_I, - M_SUBU_I_2, - M_TEQ_I, - M_TGE_I, - M_TGEU_I, - M_TLT_I, - M_TLTU_I, - M_TNE_I, - M_TRUNCWD, - M_TRUNCWS, - M_ULD, - M_ULD_A, - M_ULH, - M_ULH_A, - M_ULHU, - M_ULHU_A, - M_ULW, - M_ULW_A, - M_USH, - M_USH_A, - M_USW, - M_USW_A, - M_USD, - M_USD_A, - M_XOR_I, - M_COP0, - M_COP1, - M_COP2, - M_COP3, - M_NUM_MACROS -}; - - -/* The order of overloaded instructions matters. Label arguments and - register arguments look the same. Instructions that can have either - for arguments must apear in the correct order in this table for the - assembler to pick the right one. In other words, entries with - immediate operands must apear after the same instruction with - registers. - - Many instructions are short hand for other instructions (i.e., The - jal <register> instruction is short for jalr <register>). */ - -extern const struct mips_opcode mips_builtin_opcodes[]; -extern const int bfd_mips_num_builtin_opcodes; -extern struct mips_opcode *mips_opcodes; -extern int bfd_mips_num_opcodes; -#define NUMOPCODES bfd_mips_num_opcodes - - -/* The rest of this file adds definitions for the mips16 TinyRISC - processor. */ - -/* These are the bitmasks and shift counts used for the different - fields in the instruction formats. Other than OP, no masks are - provided for the fixed portions of an instruction, since they are - not needed. - - The I format uses IMM11. - - The RI format uses RX and IMM8. - - The RR format uses RX, and RY. - - The RRI format uses RX, RY, and IMM5. - - The RRR format uses RX, RY, and RZ. - - The RRI_A format uses RX, RY, and IMM4. - - The SHIFT format uses RX, RY, and SHAMT. - - The I8 format uses IMM8. - - The I8_MOVR32 format uses RY and REGR32. - - The IR_MOV32R format uses REG32R and MOV32Z. - - The I64 format uses IMM8. - - The RI64 format uses RY and IMM5. - */ - -#define MIPS16OP_MASK_OP 0x1f -#define MIPS16OP_SH_OP 11 -#define MIPS16OP_MASK_IMM11 0x7ff -#define MIPS16OP_SH_IMM11 0 -#define MIPS16OP_MASK_RX 0x7 -#define MIPS16OP_SH_RX 8 -#define MIPS16OP_MASK_IMM8 0xff -#define MIPS16OP_SH_IMM8 0 -#define MIPS16OP_MASK_RY 0x7 -#define MIPS16OP_SH_RY 5 -#define MIPS16OP_MASK_IMM5 0x1f -#define MIPS16OP_SH_IMM5 0 -#define MIPS16OP_MASK_RZ 0x7 -#define MIPS16OP_SH_RZ 2 -#define MIPS16OP_MASK_IMM4 0xf -#define MIPS16OP_SH_IMM4 0 -#define MIPS16OP_MASK_REGR32 0x1f -#define MIPS16OP_SH_REGR32 0 -#define MIPS16OP_MASK_REG32R 0x1f -#define MIPS16OP_SH_REG32R 3 -#define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18)) -#define MIPS16OP_MASK_MOVE32Z 0x7 -#define MIPS16OP_SH_MOVE32Z 0 -#define MIPS16OP_MASK_IMM6 0x3f -#define MIPS16OP_SH_IMM6 5 - -/* These are the characters which may appears in the args field of an - instruction. They appear in the order in which the fields appear - when the instruction is used. Commas and parentheses in the args - string are ignored when assembling, and written into the output - when disassembling. - - "y" 3 bit register (MIPS16OP_*_RY) - "x" 3 bit register (MIPS16OP_*_RX) - "z" 3 bit register (MIPS16OP_*_RZ) - "Z" 3 bit register (MIPS16OP_*_MOVE32Z) - "v" 3 bit same register as source and destination (MIPS16OP_*_RX) - "w" 3 bit same register as source and destination (MIPS16OP_*_RY) - "0" zero register ($0) - "S" stack pointer ($sp or $29) - "P" program counter - "R" return address register ($ra or $31) - "X" 5 bit MIPS register (MIPS16OP_*_REGR32) - "Y" 5 bit MIPS register (MIPS16OP_*_REG32R) - "6" 6 bit unsigned break code (MIPS16OP_*_IMM6) - "a" 26 bit jump address - "e" 11 bit extension value - "l" register list for entry instruction - "L" register list for exit instruction - - The remaining codes may be extended. Except as otherwise noted, - the full extended operand is a 16 bit signed value. - "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned) - ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned) - "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned) - "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned) - "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed) - "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5) - "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5) - "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5) - "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5) - "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5) - "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) - "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8) - "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8) - "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned) - "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8) - "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8) - "p" 8 bit conditional branch address (MIPS16OP_*_IMM8) - "q" 11 bit branch address (MIPS16OP_*_IMM11) - "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8) - "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5) - "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5) - */ - -/* For the mips16, we use the same opcode table format and a few of - the same flags. However, most of the flags are different. */ - -/* Modifies the register in MIPS16OP_*_RX. */ -#define MIPS16_INSN_WRITE_X 0x00000001 -/* Modifies the register in MIPS16OP_*_RY. */ -#define MIPS16_INSN_WRITE_Y 0x00000002 -/* Modifies the register in MIPS16OP_*_RZ. */ -#define MIPS16_INSN_WRITE_Z 0x00000004 -/* Modifies the T ($24) register. */ -#define MIPS16_INSN_WRITE_T 0x00000008 -/* Modifies the SP ($29) register. */ -#define MIPS16_INSN_WRITE_SP 0x00000010 -/* Modifies the RA ($31) register. */ -#define MIPS16_INSN_WRITE_31 0x00000020 -/* Modifies the general purpose register in MIPS16OP_*_REG32R. */ -#define MIPS16_INSN_WRITE_GPR_Y 0x00000040 -/* Reads the register in MIPS16OP_*_RX. */ -#define MIPS16_INSN_READ_X 0x00000080 -/* Reads the register in MIPS16OP_*_RY. */ -#define MIPS16_INSN_READ_Y 0x00000100 -/* Reads the register in MIPS16OP_*_MOVE32Z. */ -#define MIPS16_INSN_READ_Z 0x00000200 -/* Reads the T ($24) register. */ -#define MIPS16_INSN_READ_T 0x00000400 -/* Reads the SP ($29) register. */ -#define MIPS16_INSN_READ_SP 0x00000800 -/* Reads the RA ($31) register. */ -#define MIPS16_INSN_READ_31 0x00001000 -/* Reads the program counter. */ -#define MIPS16_INSN_READ_PC 0x00002000 -/* Reads the general purpose register in MIPS16OP_*_REGR32. */ -#define MIPS16_INSN_READ_GPR_X 0x00004000 -/* Is a branch insn. */ -#define MIPS16_INSN_BRANCH 0x00010000 - -/* The following flags have the same value for the mips16 opcode - table: - INSN_UNCOND_BRANCH_DELAY - INSN_COND_BRANCH_DELAY - INSN_COND_BRANCH_LIKELY (never used) - INSN_READ_HI - INSN_READ_LO - INSN_WRITE_HI - INSN_WRITE_LO - INSN_TRAP - INSN_ISA3 - */ - -extern const struct mips_opcode mips16_opcodes[]; -extern const int bfd_mips16_num_opcodes; - -#endif /* _MIPS_H_ */ diff --git a/contrib/binutils/include/opcode/tic30.h b/contrib/binutils/include/opcode/tic30.h deleted file mode 100644 index a70027591188..000000000000 --- a/contrib/binutils/include/opcode/tic30.h +++ /dev/null @@ -1,691 +0,0 @@ -/* tic30.h -- Header file for TI TMS320C30 opcode table - Copyright 1998 Free Software Foundation, Inc. - Contributed by Steven Haworth (steve@pm.cse.rmit.edu.au) - -This file is part of GDB, GAS, and the GNU binutils. - -GDB, GAS, and the GNU binutils are free software; you can redistribute -them and/or modify them under the terms of the GNU General Public -License as published by the Free Software Foundation; either version -1, or (at your option) any later version. - -GDB, GAS, and the GNU binutils are distributed in the hope that they -will be useful, but WITHOUT ANY WARRANTY; without even the implied -warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -the GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this file; see the file COPYING. If not, write to the Free -Software Foundation, 59 Temple Place - Suite 330, Boston, MA -02111-1307, USA. */ - -/* FIXME: The opcode table should be in opcodes/tic30-opc.c, not in a - header file. */ - -#ifndef _TMS320_H_ -#define _TMS320_H_ - -struct _register -{ - char *name; - unsigned char opcode; - unsigned char regtype; -}; - -typedef struct _register reg; - -#define REG_Rn 0x01 -#define REG_ARn 0x02 -#define REG_DP 0x03 -#define REG_OTHER 0x04 - -static const reg tic30_regtab[] = { - { "r0", 0x00, REG_Rn }, - { "r1", 0x01, REG_Rn }, - { "r2", 0x02, REG_Rn }, - { "r3", 0x03, REG_Rn }, - { "r4", 0x04, REG_Rn }, - { "r5", 0x05, REG_Rn }, - { "r6", 0x06, REG_Rn }, - { "r7", 0x07, REG_Rn }, - { "ar0",0x08, REG_ARn }, - { "ar1",0x09, REG_ARn }, - { "ar2",0x0A, REG_ARn }, - { "ar3",0x0B, REG_ARn }, - { "ar4",0x0C, REG_ARn }, - { "ar5",0x0D, REG_ARn }, - { "ar6",0x0E, REG_ARn }, - { "ar7",0x0F, REG_ARn }, - { "dp", 0x10, REG_DP }, - { "ir0",0x11, REG_OTHER }, - { "ir1",0x12, REG_OTHER }, - { "bk", 0x13, REG_OTHER }, - { "sp", 0x14, REG_OTHER }, - { "st", 0x15, REG_OTHER }, - { "ie", 0x16, REG_OTHER }, - { "if", 0x17, REG_OTHER }, - { "iof",0x18, REG_OTHER }, - { "rs", 0x19, REG_OTHER }, - { "re", 0x1A, REG_OTHER }, - { "rc", 0x1B, REG_OTHER }, - { "R0", 0x00, REG_Rn }, - { "R1", 0x01, REG_Rn }, - { "R2", 0x02, REG_Rn }, - { "R3", 0x03, REG_Rn }, - { "R4", 0x04, REG_Rn }, - { "R5", 0x05, REG_Rn }, - { "R6", 0x06, REG_Rn }, - { "R7", 0x07, REG_Rn }, - { "AR0",0x08, REG_ARn }, - { "AR1",0x09, REG_ARn }, - { "AR2",0x0A, REG_ARn }, - { "AR3",0x0B, REG_ARn }, - { "AR4",0x0C, REG_ARn }, - { "AR5",0x0D, REG_ARn }, - { "AR6",0x0E, REG_ARn }, - { "AR7",0x0F, REG_ARn }, - { "DP", 0x10, REG_DP }, - { "IR0",0x11, REG_OTHER }, - { "IR1",0x12, REG_OTHER }, - { "BK", 0x13, REG_OTHER }, - { "SP", 0x14, REG_OTHER }, - { "ST", 0x15, REG_OTHER }, - { "IE", 0x16, REG_OTHER }, - { "IF", 0x17, REG_OTHER }, - { "IOF",0x18, REG_OTHER }, - { "RS", 0x19, REG_OTHER }, - { "RE", 0x1A, REG_OTHER }, - { "RC", 0x1B, REG_OTHER }, - { "", 0, 0 } -}; - -static const reg *const tic30_regtab_end - = tic30_regtab + sizeof(tic30_regtab)/sizeof(tic30_regtab[0]); - -/* Indirect Addressing Modes Modification Fields */ -/* Indirect Addressing with Displacement */ -#define PreDisp_Add 0x00 -#define PreDisp_Sub 0x01 -#define PreDisp_Add_Mod 0x02 -#define PreDisp_Sub_Mod 0x03 -#define PostDisp_Add_Mod 0x04 -#define PostDisp_Sub_Mod 0x05 -#define PostDisp_Add_Circ 0x06 -#define PostDisp_Sub_Circ 0x07 -/* Indirect Addressing with Index Register IR0 */ -#define PreIR0_Add 0x08 -#define PreIR0_Sub 0x09 -#define PreIR0_Add_Mod 0x0A -#define PreIR0_Sub_Mod 0x0B -#define PostIR0_Add_Mod 0x0C -#define PostIR0_Sub_Mod 0x0D -#define PostIR0_Add_Circ 0x0E -#define PostIR0_Sub_Circ 0x0F -/* Indirect Addressing with Index Register IR1 */ -#define PreIR1_Add 0x10 -#define PreIR1_Sub 0x11 -#define PreIR1_Add_Mod 0x12 -#define PreIR1_Sub_Mod 0x13 -#define PostIR1_Add_Mod 0x14 -#define PostIR1_Sub_Mod 0x15 -#define PostIR1_Add_Circ 0x16 -#define PostIR1_Sub_Circ 0x17 -/* Indirect Addressing (Special Cases) */ -#define IndirectOnly 0x18 -#define PostIR0_Add_BitRev 0x19 - -typedef struct { - char *syntax; - unsigned char modfield; - unsigned char displacement; -} ind_addr_type; - -#define IMPLIED_DISP 0x01 -#define DISP_REQUIRED 0x02 -#define NO_DISP 0x03 - -static const ind_addr_type tic30_indaddr_tab[] = { - { "*+ar", PreDisp_Add, IMPLIED_DISP }, - { "*-ar", PreDisp_Sub, IMPLIED_DISP }, - { "*++ar", PreDisp_Add_Mod, IMPLIED_DISP }, - { "*--ar", PreDisp_Sub_Mod, IMPLIED_DISP }, - { "*ar++", PostDisp_Add_Mod, IMPLIED_DISP }, - { "*ar--", PostDisp_Sub_Mod, IMPLIED_DISP }, - { "*ar++%", PostDisp_Add_Circ, IMPLIED_DISP }, - { "*ar--%", PostDisp_Sub_Circ, IMPLIED_DISP }, - { "*+ar()", PreDisp_Add, DISP_REQUIRED }, - { "*-ar()", PreDisp_Sub, DISP_REQUIRED }, - { "*++ar()", PreDisp_Add_Mod, DISP_REQUIRED }, - { "*--ar()", PreDisp_Sub_Mod, DISP_REQUIRED }, - { "*ar++()", PostDisp_Add_Mod, DISP_REQUIRED }, - { "*ar--()", PostDisp_Sub_Mod, DISP_REQUIRED }, - { "*ar++()%", PostDisp_Add_Circ, DISP_REQUIRED }, - { "*ar--()%", PostDisp_Sub_Circ, DISP_REQUIRED }, - { "*+ar(ir0)", PreIR0_Add, NO_DISP }, - { "*-ar(ir0)", PreIR0_Sub, NO_DISP }, - { "*++ar(ir0)", PreIR0_Add_Mod, NO_DISP }, - { "*--ar(ir0)", PreIR0_Sub_Mod, NO_DISP }, - { "*ar++(ir0)", PostIR0_Add_Mod, NO_DISP }, - { "*ar--(ir0)", PostIR0_Sub_Mod, NO_DISP }, - { "*ar++(ir0)%",PostIR0_Add_Circ, NO_DISP }, - { "*ar--(ir0)%",PostIR0_Sub_Circ, NO_DISP }, - { "*+ar(ir1)", PreIR1_Add, NO_DISP }, - { "*-ar(ir1)", PreIR1_Sub, NO_DISP }, - { "*++ar(ir1)", PreIR1_Add_Mod, NO_DISP }, - { "*--ar(ir1)", PreIR1_Sub_Mod, NO_DISP }, - { "*ar++(ir1)", PostIR1_Add_Mod, NO_DISP }, - { "*ar--(ir1)", PostIR1_Sub_Mod, NO_DISP }, - { "*ar++(ir1)%",PostIR1_Add_Circ, NO_DISP }, - { "*ar--(ir1)%",PostIR1_Sub_Circ, NO_DISP }, - { "*ar", IndirectOnly, NO_DISP }, - { "*ar++(ir0)b",PostIR0_Add_BitRev, NO_DISP }, - { "", 0,0 } -}; - -static const ind_addr_type *const tic30_indaddrtab_end - = tic30_indaddr_tab + sizeof(tic30_indaddr_tab)/sizeof(tic30_indaddr_tab[0]); - -/* Possible operand types */ -/* Register types */ -#define Rn 0x0001 -#define ARn 0x0002 -#define DPReg 0x0004 -#define OtherReg 0x0008 -/* Addressing mode types */ -#define Direct 0x0010 -#define Indirect 0x0020 -#define Imm16 0x0040 -#define Disp 0x0080 -#define Imm24 0x0100 -#define Abs24 0x0200 -/* 3 operand addressing mode types */ -#define op3T1 0x0400 -#define op3T2 0x0800 -/* Interrupt vector */ -#define IVector 0x1000 -/* Not required */ -#define NotReq 0x2000 - -#define GAddr1 Rn | Direct | Indirect | Imm16 -#define GAddr2 GAddr1 | AllReg -#define TAddr1 op3T1 | Rn | Indirect -#define TAddr2 op3T2 | Rn | Indirect -#define Reg Rn | ARn -#define AllReg Reg | DPReg | OtherReg - -typedef struct _template -{ - char *name; - unsigned int operands; /* how many operands */ - unsigned int base_opcode; /* base_opcode is the fundamental opcode byte */ - /* the bits in opcode_modifier are used to generate the final opcode from - the base_opcode. These bits also are used to detect alternate forms of - the same instruction */ - unsigned int opcode_modifier; - - /* opcode_modifier bits: */ -#define AddressMode 0x00600000 -#define PCRel 0x02000000 -#define StackOp 0x001F0000 -#define Rotate StackOp - - /* operand_types[i] describes the type of operand i. This is made - by OR'ing together all of the possible type masks. (e.g. - 'operand_types[i] = Reg|Imm' specifies that operand i can be - either a register or an immediate operand */ - unsigned int operand_types[3]; - /* This defines the number type of an immediate argument to an instruction. */ - int imm_arg_type; -#define Imm_None 0 -#define Imm_Float 1 -#define Imm_SInt 2 -#define Imm_UInt 3 -} -template; - -static const template tic30_optab[] = { - { "absf" ,2,0x00000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "absi" ,2,0x00800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "addc" ,2,0x01000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "addc3" ,3,0x20000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, - { "addf" ,2,0x01800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "addf3" ,3,0x20800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None }, - { "addi" ,2,0x02000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "addi3" ,3,0x21000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, - { "and" ,2,0x02800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, - { "and3" ,3,0x21800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, - { "andn" ,2,0x03000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, - { "andn3" ,3,0x22000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, - { "ash" ,2,0x03800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ash3" ,3,0x22800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, - { "b" ,1,0x68000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bu" ,1,0x68000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "blo" ,1,0x68010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bls" ,1,0x68020000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bhi" ,1,0x68030000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bhs" ,1,0x68040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "beq" ,1,0x68050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bne" ,1,0x68060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "blt" ,1,0x68070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "ble" ,1,0x68080000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bgt" ,1,0x68090000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bge" ,1,0x680A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bz" ,1,0x68050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnz" ,1,0x68060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bp" ,1,0x68090000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bn" ,1,0x68070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnn" ,1,0x680A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnv" ,1,0x680C0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bv" ,1,0x680D0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnuf" ,1,0x680E0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "buf" ,1,0x680F0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnc" ,1,0x68040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bc" ,1,0x68010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnlv" ,1,0x68100000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "blv" ,1,0x68110000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnluf" ,1,0x68120000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bluf" ,1,0x68130000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bzuf" ,1,0x68140000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bd" ,1,0x68200000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bud" ,1,0x68200000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "blod" ,1,0x68210000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "blsd" ,1,0x68220000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bhid" ,1,0x68230000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bhsd" ,1,0x68240000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "beqd" ,1,0x68250000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bned" ,1,0x68260000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bltd" ,1,0x68270000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bled" ,1,0x68280000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bgtd" ,1,0x68290000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bged" ,1,0x682A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bzd" ,1,0x68250000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnzd" ,1,0x68260000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bpd" ,1,0x68290000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnd" ,1,0x68270000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnnd" ,1,0x682A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnvd" ,1,0x682C0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bvd" ,1,0x682D0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnufd" ,1,0x682E0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bufd" ,1,0x682F0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bncd" ,1,0x68240000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bcd" ,1,0x68210000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnlvd" ,1,0x68300000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "blvd" ,1,0x68310000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnlufd" ,1,0x68320000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "blufd" ,1,0x68330000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bzufd" ,1,0x68340000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "br" ,1,0x60000000,0, { Imm24, 0, 0 }, Imm_UInt }, - { "brd" ,1,0x61000000,0, { Imm24, 0, 0 }, Imm_UInt }, - { "call" ,1,0x62000000,0, { Imm24, 0, 0 }, Imm_UInt }, - { "callu" ,1,0x70000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "calllo" ,1,0x70010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callls" ,1,0x70020000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callhi" ,1,0x70030000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callhs" ,1,0x70040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "calleq" ,1,0x70050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callne" ,1,0x70060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "calllt" ,1,0x70070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callle" ,1,0x70080000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callgt" ,1,0x70090000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callge" ,1,0x700A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callz" ,1,0x70050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callnz" ,1,0x70060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callp" ,1,0x70090000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "calln" ,1,0x70070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callnn" ,1,0x700A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callnv" ,1,0x700C0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callv" ,1,0x700D0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callnuf",1,0x700E0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "calluf" ,1,0x700F0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callnc" ,1,0x70040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callc" ,1,0x70010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callnlv",1,0x70100000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "calllv" ,1,0x70110000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callnluf",1,0x70120000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callluf",1,0x70130000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callzuf",1,0x70140000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "cmpf" ,2,0x04000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "cmpf3" ,2,0x23000000,AddressMode, { TAddr1, TAddr2, 0 }, Imm_None }, - { "cmpi" ,2,0x04800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "cmpi3" ,2,0x23800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, 0 }, Imm_None }, - { "db" ,2,0x6C000000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbu" ,2,0x6C000000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dblo" ,2,0x6C010000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbls" ,2,0x6C020000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbhi" ,2,0x6C030000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbhs" ,2,0x6C040000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbeq" ,2,0x6C050000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbne" ,2,0x6C060000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dblt" ,2,0x6C070000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dble" ,2,0x6C080000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbgt" ,2,0x6C090000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbge" ,2,0x6C0A0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbz" ,2,0x6C050000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnz" ,2,0x6C060000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbp" ,2,0x6C090000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbn" ,2,0x6C070000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnn" ,2,0x6C0A0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnv" ,2,0x6C0C0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbv" ,2,0x6C0D0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnuf" ,2,0x6C0E0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbuf" ,2,0x6C0F0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnc" ,2,0x6C040000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbc" ,2,0x6C010000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnlv" ,2,0x6C100000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dblv" ,2,0x6C110000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnluf" ,2,0x6C120000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbluf" ,2,0x6C130000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbzuf" ,2,0x6C140000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbd" ,2,0x6C200000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbud" ,2,0x6C200000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dblod" ,2,0x6C210000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dblsd" ,2,0x6C220000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbhid" ,2,0x6C230000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbhsd" ,2,0x6C240000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbeqd" ,2,0x6C250000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbned" ,2,0x6C260000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbltd" ,2,0x6C270000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbled" ,2,0x6C280000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbgtd" ,2,0x6C290000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbged" ,2,0x6C2A0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbzd" ,2,0x6C250000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnzd" ,2,0x6C260000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbpd" ,2,0x6C290000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnd" ,2,0x6C270000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnnd" ,2,0x6C2A0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnvd" ,2,0x6C2C0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbvd" ,2,0x6C2D0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnufd" ,2,0x6C2E0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbufd" ,2,0x6C2F0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbncd" ,2,0x6C240000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbcd" ,2,0x6C210000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnlvd" ,2,0x6C300000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dblvd" ,2,0x6C310000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnlufd",2,0x6C320000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dblufd" ,2,0x6C330000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbzufd" ,2,0x6C340000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "fix" ,2,0x05000000,AddressMode, { GAddr1, AllReg, 0 }, Imm_Float }, - { "float" ,2,0x05800000,AddressMode, { GAddr2, Rn, 0 }, Imm_SInt }, - { "iack" ,1,0x1B000000,AddressMode, { Direct|Indirect, 0, 0 }, Imm_None }, - { "idle" ,0,0x06000000,0, { 0, 0, 0 }, Imm_None }, - { "idle2" ,0,0x06000001,0, { 0, 0, 0 }, Imm_None }, /* LC31 Only */ - { "lde" ,2,0x06800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldf" ,2,0x07000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfu" ,2,0x40000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldflo" ,2,0x40800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfls" ,2,0x41000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfhi" ,2,0x41800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfhs" ,2,0x42000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfeq" ,2,0x42800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfne" ,2,0x43000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldflt" ,2,0x43800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfle" ,2,0x44000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfgt" ,2,0x44800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfge" ,2,0x45000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfz" ,2,0x42800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfnz" ,2,0x43000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfp" ,2,0x44800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfn" ,2,0x43800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfnn" ,2,0x45000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfnv" ,2,0x46000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfv" ,2,0x46800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfnuf" ,2,0x47000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfuf" ,2,0x47800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfnc" ,2,0x42000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfc" ,2,0x40800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfnlv" ,2,0x48000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldflv" ,2,0x48800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfnluf",2,0x49000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfluf" ,2,0x49800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfzuf" ,2,0x4A000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfi" ,2,0x07800000,AddressMode, { Direct|Indirect, Rn, 0 }, Imm_None }, - { "ldi" ,2,0x08000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldiu" ,2,0x50000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldilo" ,2,0x50800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldils" ,2,0x51000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldihi" ,2,0x51800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldihs" ,2,0x52000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldieq" ,2,0x52800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldine" ,2,0x53000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldilt" ,2,0x53800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldile" ,2,0x54000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldigt" ,2,0x54800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldige" ,2,0x55000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldiz" ,2,0x52800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldinz" ,2,0x53000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldip" ,2,0x54800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldin" ,2,0x53800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldinn" ,2,0x55000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldinv" ,2,0x56000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldiv" ,2,0x56800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldinuf" ,2,0x57000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldiuf" ,2,0x57800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldinc" ,2,0x52000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldic" ,2,0x50800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldinlv" ,2,0x58000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldilv" ,2,0x58800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldinluf",2,0x59000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldiluf" ,2,0x59800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldizuf" ,2,0x5A000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldii" ,2,0x08800000,AddressMode, { Direct|Indirect, AllReg, 0 }, Imm_None }, - { "ldm" ,2,0x09000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldp" ,2,0x08700000,0, { Abs24|Direct, DPReg|NotReq, 0 }, Imm_UInt }, - { "lopower",0,0x10800001,0, { 0, 0, 0 }, Imm_None }, /* LC31 Only */ - { "lsh" ,2,0x09800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, - { "lsh3" ,3,0x24000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, - { "maxspeed",0,0x10800000,0, { 0, 0, 0 }, Imm_None }, /* LC31 Only */ - { "mpyf" ,2,0x0A000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "mpyf3" ,3,0x24800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None }, - { "mpyi" ,2,0x0A800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "mpyi3" ,3,0x25000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, - { "negb" ,2,0x0B000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "negf" ,2,0x0B800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "negi" ,2,0x0C000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "nop" ,1,0x0C800000,AddressMode, { AllReg|Indirect|NotReq, 0, 0 }, Imm_None }, - { "norm" ,2,0x0D000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, /*Check another source*/ - { "not" ,2,0x0D800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, - { "or" ,2,0x10000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, - { "or3" ,3,0x25800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, - { "pop" ,1,0x0E200000,StackOp, { AllReg, 0, 0 }, Imm_None }, - { "popf" ,1,0x0EA00000,StackOp, { Rn, 0, 0 }, Imm_None }, - { "push" ,1,0x0F200000,StackOp, { AllReg, 0, 0 }, Imm_None }, - { "pushf" ,1,0x0FA00000,StackOp, { Rn, 0, 0 }, Imm_None }, - { "reti" ,0,0x78000000,0, { 0, 0, 0 }, Imm_None }, - { "retiu" ,0,0x78000000,0, { 0, 0, 0 }, Imm_None }, - { "retilo" ,0,0x78010000,0, { 0, 0, 0 }, Imm_None }, - { "retils" ,0,0x78020000,0, { 0, 0, 0 }, Imm_None }, - { "retihi" ,0,0x78030000,0, { 0, 0, 0 }, Imm_None }, - { "retihs" ,0,0x78040000,0, { 0, 0, 0 }, Imm_None }, - { "retieq" ,0,0x78050000,0, { 0, 0, 0 }, Imm_None }, - { "retine" ,0,0x78060000,0, { 0, 0, 0 }, Imm_None }, - { "retilt" ,0,0x78070000,0, { 0, 0, 0 }, Imm_None }, - { "retile" ,0,0x78080000,0, { 0, 0, 0 }, Imm_None }, - { "retigt" ,0,0x78090000,0, { 0, 0, 0 }, Imm_None }, - { "retige" ,0,0x780A0000,0, { 0, 0, 0 }, Imm_None }, - { "retiz" ,0,0x78050000,0, { 0, 0, 0 }, Imm_None }, - { "retinz" ,0,0x78060000,0, { 0, 0, 0 }, Imm_None }, - { "retip" ,0,0x78090000,0, { 0, 0, 0 }, Imm_None }, - { "retin" ,0,0x78070000,0, { 0, 0, 0 }, Imm_None }, - { "retinn" ,0,0x780A0000,0, { 0, 0, 0 }, Imm_None }, - { "retinv" ,0,0x780C0000,0, { 0, 0, 0 }, Imm_None }, - { "retiv" ,0,0x780D0000,0, { 0, 0, 0 }, Imm_None }, - { "retinuf",0,0x780E0000,0, { 0, 0, 0 }, Imm_None }, - { "retiuf" ,0,0x780F0000,0, { 0, 0, 0 }, Imm_None }, - { "retinc" ,0,0x78040000,0, { 0, 0, 0 }, Imm_None }, - { "retic" ,0,0x78010000,0, { 0, 0, 0 }, Imm_None }, - { "retinlv",0,0x78100000,0, { 0, 0, 0 }, Imm_None }, - { "retilv" ,0,0x78110000,0, { 0, 0, 0 }, Imm_None }, - { "retinluf",0,0x78120000,0, { 0, 0, 0 }, Imm_None }, - { "retiluf",0,0x78130000,0, { 0, 0, 0 }, Imm_None }, - { "retizuf",0,0x78140000,0, { 0, 0, 0 }, Imm_None }, - { "rets" ,0,0x78800000,0, { 0, 0, 0 }, Imm_None }, - { "retsu" ,0,0x78800000,0, { 0, 0, 0 }, Imm_None }, - { "retslo" ,0,0x78810000,0, { 0, 0, 0 }, Imm_None }, - { "retsls" ,0,0x78820000,0, { 0, 0, 0 }, Imm_None }, - { "retshi" ,0,0x78830000,0, { 0, 0, 0 }, Imm_None }, - { "retshs" ,0,0x78840000,0, { 0, 0, 0 }, Imm_None }, - { "retseq" ,0,0x78850000,0, { 0, 0, 0 }, Imm_None }, - { "retsne" ,0,0x78860000,0, { 0, 0, 0 }, Imm_None }, - { "retslt" ,0,0x78870000,0, { 0, 0, 0 }, Imm_None }, - { "retsle" ,0,0x78880000,0, { 0, 0, 0 }, Imm_None }, - { "retsgt" ,0,0x78890000,0, { 0, 0, 0 }, Imm_None }, - { "retsge" ,0,0x788A0000,0, { 0, 0, 0 }, Imm_None }, - { "retsz" ,0,0x78850000,0, { 0, 0, 0 }, Imm_None }, - { "retsnz" ,0,0x78860000,0, { 0, 0, 0 }, Imm_None }, - { "retsp" ,0,0x78890000,0, { 0, 0, 0 }, Imm_None }, - { "retsn" ,0,0x78870000,0, { 0, 0, 0 }, Imm_None }, - { "retsnn" ,0,0x788A0000,0, { 0, 0, 0 }, Imm_None }, - { "retsnv" ,0,0x788C0000,0, { 0, 0, 0 }, Imm_None }, - { "retsv" ,0,0x788D0000,0, { 0, 0, 0 }, Imm_None }, - { "retsnuf",0,0x788E0000,0, { 0, 0, 0 }, Imm_None }, - { "retsuf" ,0,0x788F0000,0, { 0, 0, 0 }, Imm_None }, - { "retsnc" ,0,0x78840000,0, { 0, 0, 0 }, Imm_None }, - { "retsc" ,0,0x78810000,0, { 0, 0, 0 }, Imm_None }, - { "retsnlv",0,0x78900000,0, { 0, 0, 0 }, Imm_None }, - { "retslv" ,0,0x78910000,0, { 0, 0, 0 }, Imm_None }, - { "retsnluf",0,0x78920000,0, { 0, 0, 0 }, Imm_None }, - { "retsluf",0,0x78930000,0, { 0, 0, 0 }, Imm_None }, - { "retszuf",0,0x78940000,0, { 0, 0, 0 }, Imm_None }, - { "rnd" ,2,0x11000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "rol" ,1,0x11E00001,Rotate, { AllReg, 0, 0 }, Imm_None }, - { "rolc" ,1,0x12600001,Rotate, { AllReg, 0, 0 }, Imm_None }, - { "ror" ,1,0x12E0FFFF,Rotate, { AllReg, 0, 0 }, Imm_None }, - { "rorc" ,1,0x1360FFFF,Rotate, { AllReg, 0, 0 }, Imm_None }, - { "rptb" ,1,0x64000000,0, { Imm24, 0, 0 }, Imm_UInt }, - { "rpts" ,1,0x139B0000,AddressMode, { GAddr2, 0, 0 }, Imm_UInt }, - { "sigi" ,0,0x16000000,0, { 0, 0, 0 }, Imm_None }, - { "stf" ,2,0x14000000,AddressMode, { Rn, Direct|Indirect, 0 }, Imm_Float }, - { "stfi" ,2,0x14800000,AddressMode, { Rn, Direct|Indirect, 0 }, Imm_Float }, - { "sti" ,2,0x15000000,AddressMode, { AllReg, Direct|Indirect, 0 }, Imm_SInt }, - { "stii" ,2,0x15800000,AddressMode, { AllReg, Direct|Indirect, 0 }, Imm_SInt }, - { "subb" ,2,0x16800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "subb3" ,3,0x26000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, - { "subc" ,2,0x17000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, - { "subf" ,2,0x17800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "subf3" ,3,0x26800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None }, - { "subi" ,2,0x18000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "subi3" ,3,0x27000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, - { "subrb" ,2,0x18800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "subrf" ,2,0x19000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "subri" ,2,0x19800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "swi" ,0,0x66000000,0, { 0, 0, 0 }, Imm_None }, - { "trap" ,1,0x74800020,0, { IVector, 0, 0 }, Imm_None }, - { "trapu" ,1,0x74800020,0, { IVector, 0, 0 }, Imm_None }, - { "traplo" ,1,0x74810020,0, { IVector, 0, 0 }, Imm_None }, - { "trapls" ,1,0x74820020,0, { IVector, 0, 0 }, Imm_None }, - { "traphi" ,1,0x74830020,0, { IVector, 0, 0 }, Imm_None }, - { "traphs" ,1,0x74840020,0, { IVector, 0, 0 }, Imm_None }, - { "trapeq" ,1,0x74850020,0, { IVector, 0, 0 }, Imm_None }, - { "trapne" ,1,0x74860020,0, { IVector, 0, 0 }, Imm_None }, - { "traplt" ,1,0x74870020,0, { IVector, 0, 0 }, Imm_None }, - { "traple" ,1,0x74880020,0, { IVector, 0, 0 }, Imm_None }, - { "trapgt" ,1,0x74890020,0, { IVector, 0, 0 }, Imm_None }, - { "trapge" ,1,0x748A0020,0, { IVector, 0, 0 }, Imm_None }, - { "trapz" ,1,0x74850020,0, { IVector, 0, 0 }, Imm_None }, - { "trapnz" ,1,0x74860020,0, { IVector, 0, 0 }, Imm_None }, - { "trapp" ,1,0x74890020,0, { IVector, 0, 0 }, Imm_None }, - { "trapn" ,1,0x74870020,0, { IVector, 0, 0 }, Imm_None }, - { "trapnn" ,1,0x748A0020,0, { IVector, 0, 0 }, Imm_None }, - { "trapnv" ,1,0x748C0020,0, { IVector, 0, 0 }, Imm_None }, - { "trapv" ,1,0x748D0020,0, { IVector, 0, 0 }, Imm_None }, - { "trapnuf",1,0x748E0020,0, { IVector, 0, 0 }, Imm_None }, - { "trapuf" ,1,0x748F0020,0, { IVector, 0, 0 }, Imm_None }, - { "trapnc" ,1,0x74840020,0, { IVector, 0, 0 }, Imm_None }, - { "trapc" ,1,0x74810020,0, { IVector, 0, 0 }, Imm_None }, - { "trapnlv",1,0x74900020,0, { IVector, 0, 0 }, Imm_None }, - { "traplv" ,1,0x74910020,0, { IVector, 0, 0 }, Imm_None }, - { "trapnluf",1,0x74920020,0, { IVector, 0, 0 }, Imm_None }, - { "trapluf",1,0x74930020,0, { IVector, 0, 0 }, Imm_None }, - { "trapzuf",1,0x74940020,0, { IVector, 0, 0 }, Imm_None }, - { "tstb" ,2,0x1A000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, - { "tstb3" ,2,0x27800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, 0 }, Imm_None }, - { "xor" ,2,0x1A800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, - { "xor3" ,3,0x28000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, - { "" ,0,0x00000000,0, { 0, 0, 0 }, 0 } -}; - -static const template *const tic30_optab_end = - tic30_optab + sizeof(tic30_optab)/sizeof(tic30_optab[0]); - -typedef struct { - char *name; - unsigned int operands_1; - unsigned int operands_2; - unsigned int base_opcode; - unsigned int operand_types[2][3]; - /* Which operand fits into which part of the final opcode word. */ - int oporder; -} partemplate; - -/* oporder defines - not very descriptive. */ -#define OO_4op1 0 -#define OO_4op2 1 -#define OO_4op3 2 -#define OO_5op1 3 -#define OO_5op2 4 -#define OO_PField 5 - -static const partemplate tic30_paroptab[] = { - { "q_absf_stf", 2,2,0xC8000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, - OO_4op1 }, - { "q_absi_sti", 2,2,0xCA000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, - OO_4op1 }, - { "q_addf3_stf", 3,2,0xCC000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, - OO_5op1 }, - { "q_addi3_sti", 3,2,0xCE000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, - OO_5op1 }, - { "q_and3_sti", 3,2,0xD0000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, - OO_5op1 }, - { "q_ash3_sti", 3,2,0xD2000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } }, - OO_5op2 }, - { "q_fix_sti", 2,2,0xD4000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, - OO_4op1 }, - { "q_float_stf", 2,2,0xD6000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, - OO_4op1 }, - { "q_ldf_ldf", 2,2,0xC4000000, { { Indirect, Rn, 0 }, { Indirect, Rn, 0 } }, - OO_4op2 }, - { "q_ldf_stf", 2,2,0xD8000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, - OO_4op1 }, - { "q_ldi_ldi", 2,2,0xC6000000, { { Indirect, Rn, 0 }, { Indirect, Rn, 0 } }, - OO_4op2 }, - { "q_ldi_sti", 2,2,0xDA000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, - OO_4op1 }, - { "q_lsh3_sti", 3,2,0xDC000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } }, - OO_5op2 }, - { "q_mpyf3_addf3",3,3,0x80000000, { { Rn | Indirect, Rn | Indirect, Rn }, - { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField }, - { "q_mpyf3_stf", 3,2,0xDE000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, - OO_5op1 }, - { "q_mpyf3_subf3",3,3,0x84000000, { { Rn | Indirect, Rn | Indirect, Rn }, - { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField }, - { "q_mpyi3_addi3",3,3,0x88000000, { { Rn | Indirect, Rn | Indirect, Rn }, - { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField }, - { "q_mpyi3_sti", 3,2,0xE0000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, - OO_5op1 }, - { "q_mpyi3_subi3",3,3,0x8C000000, { { Rn | Indirect, Rn | Indirect, Rn }, - { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField }, - { "q_negf_stf", 2,2,0xE2000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, - OO_4op1 }, - { "q_negi_sti", 2,2,0xE4000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, - OO_4op1 }, - { "q_not_sti", 2,2,0xE6000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, - OO_4op1 }, - { "q_or3_sti", 3,2,0xE8000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, - OO_5op1 }, - { "q_stf_stf", 2,2,0xC0000000, { { Rn, Indirect, 0 }, { Rn, Indirect, 0 } }, - OO_4op3 }, - { "q_sti_sti", 2,2,0xC2000000, { { Rn, Indirect, 0 }, { Rn, Indirect, 0 } }, - OO_4op3 }, - { "q_subf3_stf", 3,2,0xEA000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } }, - OO_5op2 }, - { "q_subi3_sti", 3,2,0xEC000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } }, - OO_5op2 }, - { "q_xor3_sti", 3,2,0xEE000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, - OO_5op1 }, - { "", 0,0,0x00000000, { { 0, 0, 0 }, { 0, 0, 0 } }, 0 } -}; - -static const partemplate *const tic30_paroptab_end = - tic30_paroptab + sizeof(tic30_paroptab)/sizeof(tic30_paroptab[0]); - -#endif diff --git a/contrib/binutils/include/opcode/v850.h b/contrib/binutils/include/opcode/v850.h deleted file mode 100644 index 737faf88d0de..000000000000 --- a/contrib/binutils/include/opcode/v850.h +++ /dev/null @@ -1,166 +0,0 @@ -/* v850.h -- Header file for NEC V850 opcode table - Copyright 1996, 1997 Free Software Foundation, Inc. - Written by J.T. Conklin, Cygnus Support - -This file is part of GDB, GAS, and the GNU binutils. - -GDB, GAS, and the GNU binutils are free software; you can redistribute -them and/or modify them under the terms of the GNU General Public -License as published by the Free Software Foundation; either version -1, or (at your option) any later version. - -GDB, GAS, and the GNU binutils are distributed in the hope that they -will be useful, but WITHOUT ANY WARRANTY; without even the implied -warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -the GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this file; see the file COPYING. If not, write to the Free -Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#ifndef V850_H -#define V850_H - -/* The opcode table is an array of struct v850_opcode. */ - -struct v850_opcode -{ - /* The opcode name. */ - const char *name; - - /* The opcode itself. Those bits which will be filled in with - operands are zeroes. */ - unsigned long opcode; - - /* The opcode mask. This is used by the disassembler. This is a - mask containing ones indicating those bits which must match the - opcode field, and zeroes indicating those bits which need not - match (and are presumably filled in by operands). */ - unsigned long mask; - - /* An array of operand codes. Each code is an index into the - operand table. They appear in the order which the operands must - appear in assembly code, and are terminated by a zero. */ - unsigned char operands[8]; - - /* Which (if any) operand is a memory operand. */ - unsigned int memop; - - /* Target processor(s). A bit field of processors which support - this instruction. Note a bit field is used as some instructions - are available on multiple, different processor types, whereas - other instructions are only available on one specific type. */ - unsigned int processors; -}; - -/* Values for the processors field in the v850_opcode structure. */ -#define PROCESSOR_V850 (1 << 0) /* Just the V850. */ -#define PROCESSOR_ALL -1 /* Any processor. */ -#define PROCESSOR_V850E (1 << 1) /* Just the V850E. */ -#define PROCESSOR_NOT_V850 (~ PROCESSOR_V850) /* Any processor except the V850. */ -#define PROCESSOR_V850EA (1 << 2) /* Just the V850EA. */ - -/* The table itself is sorted by major opcode number, and is otherwise - in the order in which the disassembler should consider - instructions. */ -extern const struct v850_opcode v850_opcodes[]; -extern const int v850_num_opcodes; - - -/* The operands table is an array of struct v850_operand. */ - -struct v850_operand -{ - /* The number of bits in the operand. */ - /* If this value is -1 then the operand's bits are in a discontinous distribution in the instruction. */ - int bits; - - /* (bits >= 0): How far the operand is left shifted in the instruction. */ - /* (bits == -1): Bit mask of the bits in the operand. */ - int shift; - - /* Insertion function. This is used by the assembler. To insert an - operand value into an instruction, check this field. - - If it is NULL, execute - i |= (op & ((1 << o->bits) - 1)) << o->shift; - (i is the instruction which we are filling in, o is a pointer to - this structure, and op is the opcode value; this assumes twos - complement arithmetic). - - If this field is not NULL, then simply call it with the - instruction and the operand value. It will return the new value - of the instruction. If the ERRMSG argument is not NULL, then if - the operand value is illegal, *ERRMSG will be set to a warning - string (the operand will be inserted in any case). If the - operand value is legal, *ERRMSG will be unchanged (most operands - can accept any value). */ - unsigned long (* insert) PARAMS ((unsigned long instruction, long op, - const char ** errmsg)); - - /* Extraction function. This is used by the disassembler. To - extract this operand type from an instruction, check this field. - - If it is NULL, compute - op = o->bits == -1 ? ((i) & o->shift) : ((i) >> o->shift) & ((1 << o->bits) - 1); - if (o->flags & V850_OPERAND_SIGNED) - op = (op << (32 - o->bits)) >> (32 - o->bits); - (i is the instruction, o is a pointer to this structure, and op - is the result; this assumes twos complement arithmetic). - - If this field is not NULL, then simply call it with the - instruction value. It will return the value of the operand. If - the INVALID argument is not NULL, *INVALID will be set to - non-zero if this operand type can not actually be extracted from - this operand (i.e., the instruction does not match). If the - operand is valid, *INVALID will not be changed. */ - unsigned long (* extract) PARAMS ((unsigned long instruction, int * invalid)); - - /* One bit syntax flags. */ - int flags; -}; - -/* Elements in the table are retrieved by indexing with values from - the operands field of the v850_opcodes table. */ - -extern const struct v850_operand v850_operands[]; - -/* Values defined for the flags field of a struct v850_operand. */ - -/* This operand names a general purpose register */ -#define V850_OPERAND_REG 0x01 - -/* This operand names a system register */ -#define V850_OPERAND_SRG 0x02 - -/* This operand names a condition code used in the setf instruction */ -#define V850_OPERAND_CC 0x04 - -/* This operand takes signed values */ -#define V850_OPERAND_SIGNED 0x08 - -/* This operand is the ep register. */ -#define V850_OPERAND_EP 0x10 - -/* This operand is a PC displacement */ -#define V850_OPERAND_DISP 0x20 - -/* This is a relaxable operand. Only used for D9->D22 branch relaxing - right now. We may need others in the future (or maybe handle them like - promoted operands on the mn10300?) */ -#define V850_OPERAND_RELAX 0x40 - -/* The register specified must not be r0 */ -#define V850_NOT_R0 0x80 - -/* CYGNUS LOCAL v850e */ -/* push/pop type instruction, V850E specific. */ -#define V850E_PUSH_POP 0x100 - -/* 16 bit immediate follows instruction, V850E specific. */ -#define V850E_IMMEDIATE16 0x200 - -/* 32 bit immediate follows instruction, V850E specific. */ -#define V850E_IMMEDIATE32 0x400 - -#endif /* V850_H */ |